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FPGA Device

1. gt 4 uiti Micro SD Connector Figure 2 2 Development Board bottom view The board has many features that allow users to implement a wide range of designed circuits from simple circuits to various multimedia projects The following hardware 15 provided on the board FPGA Device Cyclone V SoC 5CSXFC6D6F31 Device e Dual core ARM Cortex A9 HPS e 110K Programmable Logic Elements e 5 140 Kbits embedded memory e 6 Fractional PLLs 2 Hard Memory Controllers 3 125G Transceivers 1 5 Terasic SoCKit User Manual www terasic com www Ceresic com ARROW Configuration and Debug Quad Serial Configuration device 256 on FPGA e On Board USB Blaster II micro USB type B connector Memory Device IGB 2x256MBx16 DDR3 SDRAM on FPGA IGB 2x256MBx16 DDR3 SDRAM on HPS 128MB QSPI Flash on HPS Micro SD Card Socket on HPS Communication USB 2 0 OTG ULPI interface with micro USB type AB connector e USB to UART micro USB type B connector e 10 100 1000 Ethernet Connectors One HSMC 8 channel Transceivers Configurable I O standards 1 5 1 8 2 5 3 3 One LTC connector One Serial Peripheral Interface SPI Master one I2C and one GPIO interface Display 24 bit VGA DAC 128x064 dots LCD Module with Backlight A
2. 77 TAREVISION PIS TOR M MM SE 71 2 Tasic Terasic SoCKit User Manual www terasic com ARROW Chapter 1 SoCKIt Development Kit The SoCKit Development Kit presents a robust hardware design platform built around the Altera System on Chip SoC FPGA which combines the latest dual core Cortex A9 embedded cores with industry leading programmable logic for ultimate design flexibility Users can now leverage the power of tremendous re configurability paired with a high performance low power processor system Altera s SoC integrates an ARM based hard processor system HPS consisting of processor peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high bandwidth interconnect backbone The SoCKit development board includes hardware such as high speed DDR3 memory video and audio capabilities Ethernet networking and much more In addition an HSMC connector with high speed transceivers allows for an even greater array of hardware setups By leveraging all of these capabilities the SoCKit 15 the perfect solution for showcasing evaluating and prototyping the true potential of the Altera SoC The SoCKit Development Kit contains all components needed to use the board in conjunction with a computer that runs the Microsoft Windows XP or later 1 1 Package Contents Figure 1 1 shows a pho
3. ADV7123 vB ME Soc SYNC VGA BLANK N Figure 3 17 VGA Connections between FPGA and VGA VGA VS VGA HS The timing specification for VGA synchronization and RGB red green blue data can be found on various educational website for example search for VGA signal timing Figure 3 18 illustrates the basic timing requirements for each row horizontal that 15 displayed on a monitor An active low pulse of specific duration time a in the figure 15 applied to the horizontal synchronization hsync input of the monitor which signifies the end of one row of data and the 21 SoCKit User Manual eraic com www terasic com ARROW start of the next The data RGB output to the monitor must be off driven to 0 V for a time period called the back porch b after the hsync pulse occurs which is followed by the display interval c During the data display interval the RGB data drives each pixel in turn across the row being displayed Finally there is a time period called the front porch d where the RGB signals must again be off before the next hsync pulse can occur The timing of the vertical synchronization vsync is the similar as shown in Figure 3 18 except that a vsync pulse signifies the end of one frame and the start of the next and the data refers to the set of rows in the frame horizontal timing Table 3 15 and Table 3 16 show
4. level Verilog HDL file for Quartus level Verilog HDL file for Quartus Il cr a lt Project name gt qpf X Il Project File Project name gt qsf Quartus ll Setting File Project name gt sdc Synopsis Design Constraints file for Quartus Il Project name gt htm Pin Assignment Document Users can use Quartus II software to add custom logic into the project and compile the project to generate the SRAM Object File sof 51 Terasic SoCKit User Manual www terasic com www Ceresic com ARROW Chapter 5 Examples For FPGA This chapter provides a number of examples of advanced circuits implemented by RTL or Qsys on the SoCKit board These circuits provide demonstrations of the major features which connected to FPGA interface on the board such as audio DDR3 and IR receiver of the associated files can be found in the Demonstrations FPGA folder on the SoCKit System CD B Installing the Demonstrations To install the demonstrations on your computer Copy the directory Demonstrations into local directory of your choice It is important to ensure that the path to your local directory contains no spaces otherwise the Nios II software will not work Note Quartus II v13 is required for all SoCKit demonstrations to support Cyclone V SoC device 5 1 Audio Recording and Playing This demonstration shows how to implement an audio recorder and player using SoC Ki
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7. 40 E TOA AEE 41 42 6416 43 CHAPTER 4 5 SYSTEM 848 8898 8 45 RIO Ce 45 Gir IS Te EPI 45 4 3 USING SOCKIT SYSTEM veut 46 CHAPTER 5 EXAMPLES FOR FPGA lt lt 52 S THAUDIOJSBC ORDING AND al Be bd e eatem idisse em mA EUN ird 52 SLA KARAOKE ENA 55 58 5 4 DDR3 SDRAM TEST BY NIOS horret retro stesse 60 5 5 RECEIVER DEMONSTRATION 62 5 6 TEMPERATURE 5 67 CHAPTER 6 STEPS OF PROGRAMMING THE QUAD SERIAL CONFIGURATION DEVICE TO CHAPTER 7 APPENDIX VE CERE
8. 29 Slide Switch 3 2 5V Table 3 10 Pin Assignments for Push buttons Signal Name FPGA Pin No Description Standard KEY 0 PIN AE9 Push button 0 3 3V KEY 1 PIN AE12 Push button 1 3 3V KEY 2 PIN AD9 Push button 2 3 3V KEY 3 PIN AD11 Push button 3 3 3V Table 3 14 Pin Assignments for LEDs Signal Name FPGA Pin No Description Standard LED 0 PIN AF10 LED 0 3 3V LED 1 PIN AD10 LED 1 3 3V LED 2 PIN AE11 LED 2 3 3V LED 3 PIN AD7 LED 3 3 3V 3 6 2 HSMC connector The board contains a High Speed Mezzanine Card HSMC interface to provide a mechanism for extending the peripheral set of an FPGA host board by means of add on daughter cards which can address today s high speed signaling requirements as well as low speed device interface support The HSMC interface support JTAG clock outputs and inputs high speed serial I O transceivers and single ended or differential signaling Signals on the HSMC port are shown in Figure 3 15 Table 3 12 shows the maximum power consumption of the daughter card that connects to HSMC port 22 Terasic SoCKit User Manual www terasic com t C C C C M www Ceresic com ARROW Bank 1 Power 8 TX Channels CDR 8 Channels JTAG SMBus CLKINO CLKOUTO Bank 2 Power D 39 0 D
9. dA MCLK XTI AUD BCLK BCLK AUD DACDAT B4AN AUD DACLRCK AUD ADCDAT 1 RECDAT Line In D AUD ADCLRCK Cyclone RECLRC SoC MUTE AUD SCLK Line Out U7 SCLK AUD SDAT SDIN Figure 3 16 Connections between FPGA and Audio CODEC 26 www terasic com Terasic SoCKit User Manual www Cerasic com ARROW Table 3 14 Pin Assignments for Audio CODEC Signal Name FPGA Pin No Description VO Standard AUD ADCLRCK PIN AG30 Audio CODEC ADC LR Clock 3 3V AUD_ADCDAT PIN_AC27 Audio CODEC ADC Data 3 3V AUD_DACLRCK PIN_AH4 Audio CODEC DAC LR Clock 3 3V AUD_DACDAT PIN_AG3 Audio CODEC DAC Data 3 3V AUD_XCK PIN AC9 Audio CODEC Chip Clock 3 3V AUD BCLK PIN AE7 Audio CODEC Bit Stream Clock 3 3V AUD 2 SCLK PIN 2 Clock 3 3V AUD 12 SDAT PIN AF30 2 Data 3 3V AUD MUTE PIN AD26 DAC Output Mute Active Low 3 3V 3 6 4 VGA The board includes a 15 pin D SUB connector for output The synchronization signals are provided directly from the Cyclone V SoC FPGA and the Analog Devices ADV7123 triple 10 high speed video DAC only the higher 8 bits are used 15 used to produce the analog data signals red green and blue It could support the SXGA standard 1280 1024 with a bandwidth of 100MHz Figure 3 17 gives the associated schematic VGA R 7 0 R 7 0 AU RYAN DAC
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11. Search altera com a You can also import input file information from other files and save the conversion setup information created here for future use Conversion setup files Output programming file Programming file type Indirect Configuration File jic C altera 13 0 output file jic Remote Local update difference file NONE Create Memory Map File Generate output file map Create files Generate output file periph jic and output file core rbf File Data area Flash Loader Data Figure 6 2 Convert Programming Files Dialog Box 7 Click Add File 8 Select the SOF that you want to convert to a JIC file 9 Click Open 10 Highlight the Flash Loader and click Add Device See Figure 6 3 11 Click OK The Select Devices page displays 72 124 51 SoCKit User Manual www terasic com www Ceresic com ARROW ur Convert Programminc File Tools You can also import input information from other files and save the conversion setup information created here for future use Conversion setup files Output programming file Ops anion deve Mode File name C output_file jic Remote Local update difference file NONE Create Memory Map File Generate output_file map _ Create files Generate output file pe
12. Table 3 4 lists BOOTSEL and CLKSEL settings Table 3 5 lists the settings for selecting a suitable boot source Figure 3 4 HPS BOOTSEL Setting Headers 13 Terasic SoCKit User Manual www terasic com Figure 3 5 HPS CLKSEL Setting Headers Table 3 4 HPS BOOTSEL and CLKSEL Setting Headers Board Reference Signal Name Setting Default Short Pm zanda Logeo Shen 1 and Shom Logeo PON Pn Zand Shon Pin zanda Short Pin 1 and Short Pin 1 and 2 Logic 1 LKSEL Short Pin 2 and 3 Logic 0 Short Pin 1 and 2 Logic 1 Short Pin 2 and 3 Logic 0 Short Pin 2 and 3 CLKSEL1 Short Pin 2 and 3 Table 3 5 BOOTSEL 2 0 Setting Values and Flash Device Selection 3 0 V SD MMC Flash memory 1 8 V SPI or quad SPI Flash memory 1 3 0 V SPI or quad SPI Flash memory 2140 18VSD MMC Flash memory 1 1 Not supported SoCKit board 14 SoCKit User Manual www terasic com ARROW 3 1 4 HSMC VCCIO Voltage Level Setting Header On the SoCKit the I O standards of the FPGA HSMC pins can be adjusted via JP2 See Figure 3 6 Adjustable standards allow even more flexibility and selection of daughter cards or interconnect devices The connector s default standard is 2 5 V Users must ensure that the voltage standards for both the main board and daughter card are the same or damage incompatibility may occur Table 3 6 lists JP2 set
13. provided by the device 55 Terasic SoCKit User Manual www terasic com www Cerasic com ARROW pP Line Out e Push Button Figure 5 3 Block diagram of the Karaoke Machine demonstration Demonstration Setup File Locations and Instructions Project directory SOCKIT 12sound Bit stream used SOCKIT 12sound sof Connect a microphone to microphone in port pink color on the SOCKIT board Connect the audio output of a music player such as an MP3 player or computer to the line in port blue color on the SOCKIT board Connect headset speaker to the line out port green color on the SOCKIT board Load the bit stream into the FPGA by execute the batch file SOCKIT_12sound under the SOCKIT i2soundMemo batch folder You should be able to hear a mixture of the microphone sound and the sound from the music player Press KEYO to adjust the volume it cycles between volume levels 0 to 9 Figure 5 4 illustrates the setup for this demonstration 56 www terasic com SoCKit User Manual erasic com www Microphone Speaker Clock Data Frequency Generator Figure 5 4 Setup for the Karaoke Machine 57 www terasic com ARROW 5 3 DDR3 SDRAM Test This demonstration presents a memory test function the bank of DDR3 SDRAM on the SoCKit board The memory size of the DDR3 SDRAM bank is 1GB B Function Block Dia
14. 3 3V GMII and receive data valid 3 3V GMII and receive data 0 3 3V GMII and receive data 1 3 3V GMII and receive data 2 3 3V GMII and MII receive data 3 3 3V GMII and MII receive clock 3 3V Hardware Reset Signal 3 3V Management Data 3 3V Management Data Clock Reference 3 3V Interrupt Open Drain Output 3 3V GMII Transmit Clock 3 3V Additionally the Ethernet PHY KSZ9021 RND LED status has been set to tri color dual LED mode www Terasic SoCKit User Manual 35 www terasic com ARROW The LED control signals are connected to LEDs orange and green on the RJ45 connector States and definitions can be found in Table 3 23 which can display the current status of the Ethernet For example once the green LED lights on the board has been connected to Giga bit Ethernet Table 3 23 Tri Color Dual LED Mode Pin Definition LED State LED Definition Link Activity LED2 LED1 LED2 LED1 H H OFF OFF Link off L H ON OFF 1000 Link No Activity Toggle H Blinking OFF 1000 Link Activity RX TX H L OFF ON 100 Link No Activity H Toggle OFF Blinking 100 Link Activity RX TX L L ON ON 10 Link No Activity Toggle Toggle Blinking Blinking 10 Link Activity TX 3 7 3 UART The board has one UART interface connected for communication with the HPS This interface wouldn t support HW flow control signals The physical interface 15 done using UART USB onboard bridge from an FT232R chip and co
15. Demonstration Setup File Locations and Instructions Make sure Quartus II and Nios II are installed on your Power on the SoCKit board Connect USB Blaster to the SoCKit board and install USB Blaster driver if necessary Execute the demo batch file SoCKit under the batch file folder IR Memo batch e After Nios II program is downloaded and executed successfully a prompt message will be displayed in nios2 terminal e Point the IR receiver with the remote controller and press any button e the information will be displayed in nios2 terminal shown in Figure 5 13 Em Altera Nios II EDS 13 0 gcc ote controller ote controll ote controll Ai n ote controll na ote controll Ai ote controll ote controll n ote controll rb ote controll rb ote controll n ote controll P K K K K K K K K K K n ote controll Figure 5 13 Running results of the IR demonstration Figure 5 14 illustrates the setup for this demonstration 66 Terasic SoCKit User Manual www terasic com www Cerasic com D Lite Remote 4 m estis 7 Controller IR Receiver Figure 5 14 The Setup of the IR receiver demonstration 5 6 Temperature Demonstration This demonstration illustrates how to use the ADT7301 device with the Nios II Processor to realiz
16. 15 Class SSTL 15 Class DIFFERENTIAL 1 5 V SSTL CLASS Differential 1 5 V SSTL Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class www terasic com ARROW DDR3 DM 3 DDR3 DQ 0 DDR3 DQ 1 DDR3 0012 DDR3 DQ 3 DDR3 DQ 4 DDR3 DQ 5 DDR3 DQ 6 DDR3 DQ 7 DDR3 0018 DDR3 DQ 9 DDR3 DQ 10 DDR3 DQ 11 DDR3 DQ 12 DDR3 DQ 13 DDR3 14 DDR3 DQ 15 DDR3 16 DDR3 DQ 17 DDR3 18 DDR3 DQ 19 DDR3 DQ 20 DDR3 21 DDR3 DQ 22 DDR3 DQ 23 0083 24 DDR3 DQ 25 DDR3 26 DDR3 DQ 27 0083 28 DDR3 DQ 29 DDR3 DQ 30 DDR3 DQ 31 DDR3 005 n 0 DDR3 DOS n 1 DDR3 DOS 2 DDR3 DOS n 3 DDR3 DOS DDR3 005 p 1 DDR3 005 2 Terasic SoCKit User Manual www Ceresic com PIN AJ27 PIN AF18 PIN AE17 PIN AG16 PIN AF16 PIN AH20 PIN 21 PIN AJ16 PIN AH18 PIN AK18 PIN AJ17 PIN AG18 PIN AK19 PIN AG20 PIN AF19 PIN AJ20 PIN AH24 PIN AE19 PIN AE18 PIN AG22 PIN AK22 PIN 21 PIN AF20 PIN AH23 PIN AK24 PIN AF24 PIN AF23 PIN AJ24 PIN AK26 PIN AE23 PIN AE22 PIN AG25 PIN AK27 PIN W16 PIN W17 PIN AA18 PIN AD19 PIN V16 PIN V17 PIN Y17 DDR3 Data Mask 3 DDR3 Data 0 DDR3 Data 1 DDR3 Data 2 DDR3 Data 3 DDR3 Data 4 DDR3 Data 5 DDR3 Data 6 DDR3 Data 7 DDR3 Data 8 DDR3 Data 9 DDR3 Data 10 DDR3 Data 11 DDR3 Data 12 DDR3 Data 13 DDR3 Data 14 DDR3 Data 15 DDR3 Data 16 DDR3 Data 17 D
17. 4 23 600 1 40 SVGA 75Hz 800x600 3 21 600 1 49 SVGA 85Hz 800x600 3 27 600 1 56 XGA 60Hz 1024x768 6 29 768 3 65 XGA 70Hz 1024x768 6 29 768 3 75 XGA 85Hz 1024x768 3 36 768 1 95 1280x1024 60Hz 1280x1024 3 38 1024 1 108 Table3 17 Pin Assignments for VGA Signal Name FPGA Pin No Description Standard VGA R 0 PIN AG5 VGA Red 0 3 3V VGA R 1 PIN AA12 VGA Red 1 3 3V VGA_R 2 PIN AB12 VGA Red 2 3 3V PIN AF6 VGA Red 3 3 3V VGA R 4 PIN AG6 VGA Red 4 3 3V R 5 PIN AJ2 VGA Red 5 3 3V VGA 161 PIN AH5 VGA Red 6 3 3V 6171 AJ1 VGA 71 3 3V G 0 PIN 21 VGA Green 0 3 3V G 1 PIN AA25 Green 1 3 3V 621 26 VGA Green 2 3 3V G 3 22 Green 3 3 3V G 4 PIN AB23 VGA Green 4 3 3V VGA G 5 PIN AA24 Green 5 3 3V G 6 PIN AB25 Green 6 3 3V G 7 PIN AE27 Green 7 3 3V 0 PIN AE28 Blue 0 3 3V B 1 PIN Y23 Blue 1 3 3V VGA_B 2 Y24 VGA Blue 2 3 3V 28 VGA Blue 3 3 3V B 4 PIN AF28 Blue 4 3 3V VGA B 5 PIN V23 VGA Blue 5 3 3V B 6 PIN W24 Blue 6 3 3V VGA 7 PIN AF29 VGA Blue 7 3 3V VGA_CLK PIN W20 Clock 3 3V VGA BLANK n PIN AH3 VGA BLANK 3 3V VGA HS PIN AD12 VGAH SYNC 3 3V VGA VS PIN AC12 VGAV SYNC 3 3V VGA SYNC n PIN AG2 VGA SYNC 3 3V ARROW 3 6 5 IR Receiver The board provides an infrared rem
18. D 3 0 LVDS CLKIN1 CLKOUT1 Bank 3 Power 0 79 40 CLKIN2 CLKOUT2 Figure 3 15 HSMC Signal Bank Diagram Table3 12 Power Supply of the HSMC Supplied Voltage Max Current Limit 12V 3 3V 1A 1 5A Table 3 13 Pin Assignments for HSMC connector Signal Name FPGA Pin No Description HSMC CLK INO PIN J14 Dedicated clock input HSMC CLKIN n1 PIN AB27 LVDS or CMOS or differential clock input HSMC CLKIN n2 PIN G15 LVDS or CMOS or differential clock input HSMC CLKIN p1 PIN AA26 LVDS or CMOS or differential clock input HSMC CLKIN p2 PIN H15 LVDS or CMOS or differential clock input HSMC CLK OUTO PIN AD29 Dedicated clock output HSMC CLKOUT n1 PIN E6 LVDS TX or CMOS or differential clock input output HSMC CLKOUT n2 PIN A10 LVDS TX or CMOS or differential clock input output HSMC CLKOUT p1 PIN E7 LVDS TX or CMOS or 23 SoCKit User Manual Standard Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 www terasic com ARROW HSMC CLKOUT p2 HSMC 0101 HSMC 0111 HSMC 0121 HSMC 031 HSMC SCL HSMC SDA HSMC GXB 0 HSMC GXB 1 HSMC GXB 2 HSMC GXB HSMC GXB RX 4 HSMC GXB RX p 5 HSMC GXB p 6 HSMC 7 HSMC GXB TX p 0 HSMC GXB TX 1 HSMC GXB TX p 2 HSMC GXB TX HSM
19. HPS DDR3 A 3 HPS DDR3 A 4 HPS DDR3 A 5 HPS DDR3 A 6 HPS DDR3 7 HPS DDR3 A 8 HPS DDR3 A 9 HPS DDR3 A 10 HPS DDR3 A 11 HPS DDR3 A 12 HPS DDR3 A 13 HPS DDR3 A 14 HPS DDR3 0 HPS DDR3 1 HPS DDR3 BA 2 HPS DDR3 CAS n HPS DDR3 CKE HPS DDR3 CK n HPS DDR3 CK p HPS DDR3 CS n 5 DDR3 HPS DDR3 HPS DDR3 2 HPS DDR3 PIN F26 PIN G30 PIN F28 PIN F30 PIN J25 PIN J27 PIN F29 PIN E28 PIN H27 PIN G26 PIN D29 PIN C30 PIN B30 PIN C29 PIN H25 PIN E29 PIN J24 PIN J23 PIN E27 PIN L29 PIN L23 PIN M23 PIN H24 PIN K28 PIN M28 PIN R28 PIN W30 HPS DDR3 Address 0 HPS DDR3 Address 1 HPS DDR3 Address 2 HPS DDR3 Address 3 HPS DDR3 Address 4 HPS DDR3 Address 5 HPS DDR3 Address 6 HPS DDR3 Address 7 HPS DDR3 Address 8 HPS DDR3 Address 9 HPS DDR3 Address 10 HPS DDR3 Address 11 HPS DDR3 Address 12 HPS DDR3 Address 13 HPS DDR3 Address 14 HPS DDR3 Bank Address 0 HPS DDR3 Bank Address 1 HPS DDR3 Bank Address 2 DDR3 Column Address Strobe HPS DDR3 Clock Enable HPS DDR3 Clock HPS DDR3 Clock p HPS DDR3 Chip Select HPS DDR3 Data Mask 0 HPS DDR3 Data Mask 1 HPS DDR3 Data Mask 2 HPS DDR3 Data Mask 3 57 Terasic SoCKit User Manual www Ceresic com SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class
20. NE TE 4 PEU 9 3 Inc All Rights Reserved les rasic Technologi 2013 Copyright 2003 ARROW CONTENTS CHAPTER 1 SOCKIT DEVELOPMENT 3 MN xe dq co UID UU 3 quic b T P 4 IN ie rudi a 23 P NE 4 CHAPTER 2 INTRODUCTION OF THE SOCKIT 5 2 1 LAYOUTAND COMPONENTS TP 5 2 2 BLOCK DIAGRAM OF THE SOC KIT 8 CHAPTER USING THE SOCKIT BOARD ux canis a ER S YE 10 31 BOARD SETUP COMPONENTS educ t 10 3 1 1 JTAG CHAIN AND SETUP SWITCHES oda RM RR SU ends 10 3 1 2 FPGA CONFIGURATION MODE SWITCH 12 3 1 3 HPS BOOTSEL AND CLKSEL SETTING HEADERS 13 3 1 4 HSMC VCCIO VOLTAGE LEVEL SETTING 2
21. Quartus 13 0 Demonstration Source Code Project directory SoCKit DDR3 RTL Test Bit stream used SoCKit DDR3 RTL Test sof Demonstration Batch File Demo Batch File Folder SoCKit DDR3 RTL batch The demo batch file includes following files Batch File SoCKit DDR3 RTL Test bat FPGA Configure File SoCKit DDR3 Test sof Demonstration Setup Make sure Quartus II 15 installed on your Connect the USB cable to the USB Blaster II connector J2 on the SoCKit board and host PC Power on SoCKit board Execute the demo batch file SoCKit_ DDR3 RTL Test bat under the batch file folder SoCKit DDR3 RTL Test demo batch Press KEYO on the SoCKit board to start the verification process When KEYO is pressed LEDs LED 2 0 should turn on At the instant of releasing KEYO LED1 LED2 should start blinking After approximately 13 seconds LED1 should stop blinking and stay on to indicate that the DDR3 has passed the test respectively Table 4 2 lists the LED indicators If LED2 is not blinking it means the 50MHz clock source is not working If LEDI do not start blinking after releasing KEYO it indicates local init done or local cal success of the corresponding DDR3 failed If LEDI fail to remain on after 13 seconds the corresponding DDR3 test has failed Press KEYO again to regenerate the test control signals for a repeat test Table 5 3 LED Indicators NAME Description LEDO Reset LED1 If ligh
22. SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class Differential 1 5 V SSTL Class Differential 1 5 V SSTL Class Differential 1 5 V SSTL Class Differential 1 5 V SSTL Class Differential 1 5 V SSTL Class Differential 1 5 V SSTL Class Differential 1 5 V SSTL Class Differential 1 5 V SSTL Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class 1 5 V www terasic com ARROW 3 7 5 QSPI Flash The board supports a 1G bit serial NOR flash device for non volatile storage of HPS boot code user data and program The device is connected to HPS dedicated interface It may contain secondary boot code This device has 4 bit data interface and uses 3 3 V CMOS signaling standard Connections between Cyclone V SoC FPGA and Flash are shown in Figure 3 24 To program the QSPI flash the HPS Flash Programmer is provided both as part of the Altera Quartus II suite and as part of the free Altera Quartus II Programmer The HPS Flash Programmer sends file contents over an Altera download cable such as the USB Blaster II to the HPS and instructs the HPS to write the data to the flash memory HPS FLASH DATA 3 HOLD n DQ3 HPS FLASH DATA 2 W n Vpp DQ2 NOTS HPS FLASH DATA 1 HPS FLASH DATA 0 Cyclone SoC HPS FLASH DCLK HPS HPS FLASH NCSO FLASH Figure 3 24 Connections Between Cyclone V SoC FPGA and QSPI Flash Table 3 26 below
23. SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class Differential 1 5 V SSTL Class Differential 1 5 V SSTL Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class www terasic com ARROW HPS DDR3 0 HPS DDR3 DQ 1 HPS DDR3 2 HPS DDR3 DQ 3 HPS DDR3 DO 4 HPS DDR3 DQ 5 HPS DDR3 00161 HPS DDR3 7 HPS DDR3 8 HPS DDR3 DQ 9 HPS DDR3 DQ 10 HPS DDR3 HPS DDR3 DQ 12 HPS DDR3 DQ 13 HPS DDR3 14 HPS DDR3 DQ 15 HPS DDR3 DQ 16 HPS DDR3 DQ 17 HPS DDR3 DQ 18 HPS DDR3 DQ 19 HPS DDR3 DQ 20 HPS DDR3 21 HPS DDR3 DQ 22 HPS DDR3 DQ 23 HPS DDR3 DQ 24 HPS DDR3 DQ 25 HPS DDR3 DQ 26 HPS DDR3 DQ 7 HPS DDR3 DQ 28 HPS DDR3 29 HPS DDR3 DQ 30 HPS DDR3 DQ 31 HPS DDR3 005 HPS DDR3 005 n 1 HPS DDR3 005 2 HPS DDR3 005 n 3 HPS DDR3 005 0 HPS DDR3 005 p 1 HPS DDR3 005 2 HPS DDR3 005 HPS DDR3 ODT HPS DDR3 RAS n HPS DDR3 RESET n HPS DDR3 WE n 5 DDR3 RZQ PIN 23 PIN K22 PIN H30 PIN G28 PIN L25 PIN L24 PIN J30 PIN J29 PIN K26 PIN L26 PIN K29 PIN K27 PIN M26 PIN M27 PIN L28 PIN M30 PIN U26 PIN T26 PIN N29 PIN N28 PIN P26 PIN P27 PIN N27 PIN R29 PIN P24 PIN P25 PIN T29 PIN T28 PIN R27 PIN R26 PIN V30 PIN W29 PIN M19 PIN N24 PIN R18 PIN R21 PIN N18 PIN N25 PIN R19 PIN R22 PIN H28 PIN D30 P
24. to Code Detector block The Code Detector block will check the Lead Code and feedback the examination result to State Machine block The State Machine block will change the state from IDLE to GUIDANCE once the Lead code 15 detected Once the Code Detector has detected the Custom Code status the current state will change from GUIDANCE to DATAREAD state At this state the Code Detector will save the Custom Code and Key Inv Key Code and output to Shift Register then displays it in nios2 terminal Figure 5 12 shows the state shift diagram of State Machine block Note that the input clock should be 50M Hz IR Signal Code Detector m shift Register State Machine Figure 5 11 The Receiver controller IDLE End Code Lead Code Custom Code Figure 5 12 State shift diagram of State Machine We can apply the IR receiver to many applications such as integrating to the SD Card Demo and you can also develop other related interesting applications with it 65 www terasic com ARROW Demonstration Source Code Project directory SoCKit IR Bit stream used SoCKit_IR sof e Nios Workspace SoCKit_IR Software Demonstration Batch File Demo Batch File Folder SoCKit IRMemo batch The demo batch file includes the following files e Batch File SoCKit IR bat SoCKit IR bashrc FPGA Configure File SoCKit_IR sof Nios II Program SoCKit_IR elf
25. 2 000 0000000000000055 000000054 00000 15 3 2 BOARD STATUS 15 2 3 BOARD RESET ELEMENTS D 16 3 4 PROGRAMMING THE QUAD SERIAL CONFIGURATION 4 04 00 40 17 S er ip I m S 18 OANA CE ON 19 3 6 1 USER PUSH BUTTONS SWITCHES AND LED ON FPGA 19 CONECTO 22 SNO AVVIO CODEC M 26 SUB ET E 27 TTE 30 30 TEMPERATURE 33 3 7 INTERFACE ON HARD PROCESSOR SYSTEM 5 34 3 7 1 USER PUSH BUTTONS SWITCHES AND LED ON 5 34 UP SES Mo dU E MEER OD TS 34 36 3 7 4 DDR3 MEMORY 37 m M 30 40 SoCKit User Manual www terasic com ARROW A
26. 5N HSMC CLKIN n1 HPS CLOCK1 25 25MHz CLK2A 425 2 HPS CLK7P CLKIN p2 HPS CLOCK2 25 25MH CLK2B 25 2 HPS CLK2 CLK7N 5 2 Figure 3 10 Block diagram of the clock distribution 3 6 Interface on FPGA This section describes the interfaces to FPGA Users can control or monitor the different interfaces with user logic on the FPGA 3 6 1 User Push buttons Switches and LED on FPGA The board provides four push button switches connected to FPGA as shown in Figure 3 11 Each of these switches 15 debounced using a Schmitt Trigger circuit as indicated in Figure 3 12 The four outputs called KEYO KEY2 and KEY3 of the Schmitt Trigger devices are connected directly to the Cyclone V SoC FPGA Each push button switch provides a high logic level when it is not pressed and provides a low logic level when depressed Since the push button switches are debounced they are appropriate for using as clock or reset inputs in a circuit 19 SoCKit User Manual www terasic com www Ceresic com ARROW 74HC245 Figure 3 11 Connections between the push button and Cyclone V SoC FPGA oem depressed poem released Before ww Schmitt Trigger Debounced 5 Figure 3 12 Switch debouncing There are four slide switches connected to FPGA on the board See Figure 3 13 These switches are not
27. Batch File Demo Batch File Folder SoCKit_DDR3_Nios_Test demo_batch The demo batch file includes following files e Batch File for USB Blaster II SoCKit_DDR3_Nios_Test bat SoCKit DDR3 Nios Test bashrc e FPGA Configure File SoCKit DDR3 Nios Test sof e Nios II Program SoCKit DDR3 Nios Test e f B Demonstration Setup e Make sure Quartus II and Nios II are installed on your PC e Power on the SoCKit board e Use USB cable to connect PC and the SoCKit board J2 and install USB Blaster driver if necessary 61 Terasic SoCKit User Manual www terasic com www Cerasic com ARROW e Execute demo batch SoCKit DDR3 Nios for USB Blaster II under the batch file folder SoCKit DDR3 Nios batch e After Nios II program 1s downloaded and executed successfully a prompt message will be displayed in nios2 terminal e Press Button3 KEYO of the SoCKit board to start SDRAM verify process Press KEYO for continued test and press any to terminate the continued test e The program will display progressing and result information as shown in Figure 5 7 Altera Nios II EDS 13 0 gcc4 El S Using cable USB BlasterII USB 1 device 1 instance 0x00 Pausing target processor OK Initializing CPU cache if present OK Downloaded 61KB 9 15 Verified OK Starting processor at address 0x400201B4 nios2 terminal connected to hardware target using JTAG UART on cable nios2 term
28. C GXB TX p 4 HSMC GXB TX p 5 HSMC GXB TX 6 HSMC GXB TX 7 HSMC GXB 0 HSMC GXB RX n 1 HSMC GXB 2 HSMC GXB RX n 3 HSMC GXB 4 HSMC GXB RX n 5 HSMC GXB 6 HSMC GXB n 7 HSMC GXB TX HSMC GXB TX n 1 HSMC GXB TX 2 HSMC GXB TX n 3 HSMC GXB TX 4 HSMC GXB TX n 5 HSMC GXB TX 6 HSMC GXB TX 7 HSMC HSMC n 1 HSMC n 2 HSMC n 3 HSMC 141 Terasic SoCKit User Manual www Cerasic com PIN 11 PIN C10 PIN H13 PIN C9 PIN H12 PIN AA28 PIN AE29 PIN AE2 PIN AC2 PIN AA2 PIN W2 PIN U2 PIN R2 PIN N2 PIN J2 PIN 04 PIN ABA PIN Y4 PIN V4 4 PIN P4 PIN M4 PIN H4 PIN AE1 PIN AC1 PIN AA1 PIN W1 PIN U1 PIN R1 PIN N1 PIN J1 PIN AD3 PIN AB3 PIN Y3 PIN V3 PIN T3 PIN P3 PIN M3 PIN H3 PIN G11 PIN J12 PIN F10 PIN J9 PIN K8 differential clock input output LVDS TX or CMOS or differential clock input output LVDS TX or CMOS LVDS RX or CMOS LVDS TX or CMOS I O LVDS or CMOS Management serial data Management serial clock Transceiver RX bit 0 Transceiver RX bit 1 Transceiver RX bit 2 Transceiver RX bit 3 Transceiver RX bit 4 Transceiver RX bit 5 Transceiver RX bit 6 Transceiver RX bit 7 Transceiver TX bit 0 Transceiver TX bit 1 Transceiver TX bit 2 Transceiver TX bit 3 Transceiver TX bit 4 Transceiver TX bit 5 Transceiver TX bit 6 Transceiver TX bit 7 Transceiver RX bit
29. DATA 4 HPS USB DATA 5 PIN C14 HPS USB DATA 5 HPS USB DATA 6 PIN D15 HPS USB DATA 6 HPS USB DATA 7 PIN M17 HPS USB DATA 7 HPS USB DIR PIN E14 Direction of the Data Bus HPS USB NXT PIN A14 Throttle the Data HPS USB RESET PHY PIN G17 HPS USB PHY Reset HPS USB STP PIN C15 Stop Data Stream on theBus 3 7 8 G Sensor Standard 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V The board is equipped with a digital accelerometer sensor module The ADXL345 is a small thin ultralow power assumption 3 axis accelerometer with high resolution measurement Digitalized output is formatted as 16 bit twos complement and can be accessed using I2C interface Connected to I2C interface includes two peripherals the G sensor and the connector The I2C address of the G Sensor device is 0xA6 0xA7 For more detailed information of better using this chip please refer to its datasheet which 15 available on manufacturer s website or under the Datasheet folder of the SoCKit System CD Figure 3 27 shows the connections between ADXL345 and HPS The associated pin assignments are listed in Table 3 29 SoCKit User Manual 4 www terasic com ARROW LTC Connector U32 zi HPS NUTS RTA NM ae SDA SDI SDIO 5 GSENSOR NE HPS ADXL345 Figure 3 27 Connections between Cyclone V SoC FPGA and G Sensor Table 3 29 G Sensor
30. DR3 Data 18 DDR3 Data 19 DDR3 Data 20 DDR3 Data 21 DDR3 Data 22 DDR3 Data 23 DDR3 Data 24 DDR3 Data 25 DDR3 Data 26 DDR3 Data 27 DDR3 Data 28 DDR3 Data 29 DDR3 Data 30 DDR3 Data 31 DDR3 Data Strobe n 0 DDR3 Data Strobe n 1 DDR3 Data Strobe n 2 DDR3 Data Strobe n 3 DDR3 Data Strobe p 0 DDR3 Data Strobe p 1 DDR3 Data Strobe p 2 SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class Differential 1 5 V SSTL Class Differential 1 5 SSTL Class Differential 1 5 SSTL Class Differential 1 5 SSTL Class Differential 1 5 SSTL Class Differential 1 5 SSTL Class Differential 1 5 SSTL www terasic com ARROW Class l Diff ial 1 5 V SSTL DDR3 DOS PIN AC20 DDR3 Data Strobe p 3 vs DDR3 ODT PIN AE16 DDR3 On die Termination SSTL 15 Class DDR3 RAS n PIN AH8 DDR3 Row Address Strobe SSTL 15 Class DDR3 RESET n P
31. Figure 5 6 Block diagram of the DDR3 Basic Demonstration The system flow is controlled by a Nios program First the Nios program writes test patterns into the whole of SDRAM Then it calls Nios system function alt_dache_flush_all to make sure all data has been written to SDRAM Finally it reads data from SDRAM for data verification The program will show progress in JTAG Terminal when writing reading data to from the SDRAM When verification process is completed the result is displayed in the JTAG Terminal 60 SoCKit User Manual www terasic com ARROW B Altera DDR3 SDRAM Controller with UniPHY To use Altera DDR3 controller users need to perform the four major steps 1 Create correct pin assignments for DDR3 Setup correct parameters in DDR3 controller dialog 3 Perform Analysis and Synthesis by clicking Quartus menu Process Start Start Analysis amp Synthesis 4 Run TCL files generated by DDR3 IP by clicking Quartus menu Tools gt TCL Scripts B Design Tools e Quartus II 13 0 e Nios II Eclipse 13 0 B Demonstration Source Code e Quartus Project directory SoCKit DDR3 Nios Test e Nios II Eclipse SoCKit Nios TestNSoftware B Nios Project Compilation Before you attempt to compile the reference design under Nios II Eclipse make sure the project is cleaned first by clicking Clean from the Project menu of Nios Eclipse B Demonstration
32. HSMC RX p 13 HSMC RX p 14 HSMC RX p 15 HSMC RX p 16 HSMC TX HSMC TX n 1 HSMC TX _ 2 HSMC TX n 3 HSMC TX ni4 HSMC TX n 5 HSMC TX n 6 HSMC TX nI7 HSMC TX n 6 HSMC TX n 9 HSMC TX n 10 HSMC TX n 11 HSMC TX n 12 HSMC TX n 13 HSMC TX n 14 HSMC TX n 15 HSMC TX n 16 Terasic SoCKit User Manual www Cerasic com PIN H7 PIN G8 PIN F8 PIN E11 PIN B5 PIN D9 PIN D12 PIN D10 PIN B12 PIN E13 PIN G13 PIN F14 PIN G12 PIN K12 PIN G10 PIN J10 PIN K7 PIN J7 PIN H8 PIN F9 PIN PIN B6 PIN E9 PIN E12 PIN D11 PIN C13 PIN F13 PIN H14 PIN F15 PIN A8 PIN D7 PIN F6 PIN C5 PIN C4 PIN E2 PIN 04 PIN B3 PIN D1 PIN C2 PIN B1 PIN A3 PIN A5 PIN B7 PIN B8 PIN B11 PIN A13 LVDS bit 5n or CMOS LVDS RX bit or CMOS I O LVDS RX bit 7n or CMOS I O LVDS RX bit 8n or CMOS I O LVDS RX bit 9n or CMOS I O LVDS bit 10n or CMOS I O LVDS RX bit or CMOS I O LVDS RX bit 12n or CMOS I O LVDS RX bit 13n or CMOS I O LVDS RX bit 14n or CMOS I O LVDS RX bit 15n or CMOS I O LVDS RX bit 16n or CMOS LVDS RX bit 0 or CMOS I O LVDS RX bit 1 or CMOS I O LVDS RX bit 2 or CMOS I O LVDS RX bit 3 or CMOS I O LVDS RX bit 4 or CMOS I O LVDS RX bit 5 or CMOS I O LVDS RX bit 6 or CMOS I O LVDS RX bit 7 or CMOS I O LVDS RX bit 8 or CMOS I O LVDS bit 9 or CMOS I O LVDS RX bit 10 or CMOS I O LVDS RX bit 11 or CMOS I O LVDS RX bit 12 or CMOS I O LVDS bit 13 or CMOS I O LVDS RX
33. IN AK21 DDR3 Reset SSTL 15 Class DDR3 WE n PIN AJ6 DDR3 Write Enable SSTL 15 Class DDR3 RZQ PIN AG17 External reference ball for 1 5V output drive calibration 3 6 7 Temperature Sensor The board contains a temperature sensor Analog Devices ADT7301 to monitor the ambient temperature It is a band gap temperature sensor with a 13 bit ADC to monitor and digitize the temperature reading to a resolution of 0 03125 The interface between sensor and FPGA 15 SPI serial interface Detailed information for using the sensor 15 available in its datasheet which can be found on the manufacturer s website in the Datasheets TEMP Sensor folder on the SoCKit System CD Figure 3 21 shows the connections between temperature sensor and Cyclone V SoC FPGA Table 3 20 gives the all the pin assignments of the sensor U22 TEMP SLCK N DTE SYN TEMP CS n SoC TEMP OUT ADT7301 Figure 3 21 Connections between FPGA and Temperature Sensor Table 3 20 Pin Assignments for Temperature Sensor Signal Name FPGA Pin No Description Standard TEMP CS n PIN AF8 Temp Sensor Chip Select Input 3 3V TEMP DIN AG7 Temp Sensor Serial Data Input 3 3V TEMP DOUT PIN AG1 Temp Sensor Serial Data Output 3 3V TEMP SCLK PIN AF9 Temp Sensor Serial Clock Input 3 3V 33 Terasic SoCKit User Manual www terasic com www Cerasic com ARROW 3 7 Interface on Hard Processor System HPS Th
34. IN P30 PIN C28 PIN D27 HPS DDR3 Data 0 HPS DDR3 Data 1 HPS DDR3 Data 2 HPS DDR3 Data 3 HPS DDR3 Data 4 HPS DDR3 Data 5 HPS DDR3 Data 6 HPS DDR3 Data 7 HPS DDR3 Data 8 HPS DDR3 Data 9 HPS DDR3 Data 10 HPS DDR3 Data 11 HPS DDR3 Data 12 HPS DDR3 Data 13 HPS DDR3 Data 14 HPS DDR3 Data 15 HPS DDR3 Data 16 HPS DDR3 Data 17 HPS DDR3 Data 18 HPS DDR3 Data 19 HPS DDR3 Data 20 HPS DDR3 Data 21 HPS DDR3 Data 22 HPS DDR3 Data 23 HPS DDR3 Data 24 HPS DDR3 Data 25 HPS DDR3 Data 26 HPS DDR3 Data 27 HPS DDR3 Data 28 HPS DDR3 Data 29 HPS DDR3 Data 30 HPS DDR3 Data 31 HPS DDR3 Data Strobe 0 HPS DDR3 Data Strobe n 1 HPS DDR3 Data Strobe n 2 HPS DDR3 Data Strobe n 3 HPS DDR3 Data Strobe p 0 HPS DDR3 Data Strobe p 1 HPS DDR3 Data Strobe p 2 HPS DDR3 Data Strobe p 3 HPS DDR3 On die Termination DDR3 Row Address Strobe HPS DDR3 Reset HPS DDR3 Write Enable External reference ball for output drive calibration 38 Terasic SoCKit User Manual www Cerasic com SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class
35. N D6 LVDS TX bit 3 or CMOS I O Depend on JP2 HSMC TX 4 PIN D5 LVDS TX bit 4 or CMOS I O Depend on JP2 HSMC p 5 PIN LVDS TX bit 5 or CMOS I O Depend on JP2 HSMC TX 6 PIN E4 LVDS TX bit 6 or CMOS I O Depend on JP2 HSMC TX p 7 PIN C3 LVDS TX bit 7 or CMOS I O Depend on JP2 HSMC TX 8 PIN E1 LVDS TX bit 8 or CMOS I O Depend on JP2 HSMC TX p 9 PIN D2 LVDS TX bit 9 or CMOS I O Depend on JP2 HSMC TX p 10 PIN B2 LVDS TX bit 10 or CMOS I O Depend on JP2 HSMC TX p 11 PIN A4 LVDS TX bit 11 or CMOS I O Depend on JP2 HSMC TX p 12 PIN A6 LVDS TX bit 12 or CMOS I O Depend on JP2 HSMC TX p 13 PIN C7 LVDS TX bit 13 or CMOS I O Depend on JP2 HSMC TX p 14 PIN C8 LVDS TX bit 14 or CMOS I O Depend on JP2 HSMC TX p 15 PIN C12 LVDS TX bit 15 or CMOS Depend on JP2 HSMC TX p 16 PIN B13 LVDS TX bit 16 or CMOS Depend on JP2 3 6 3 Audio CODEC The board provides high quality 24 bit audio via the Analog Devices 55 2603 audio CODEC Encoder Decoder This chip supports microphone in line in and line out ports with a sample rate adjustable from 8 kHz to 96 kHz The SSM2603 is controlled via a serial I2C bus interface which is connected to pins on the Cyclone V SoC FPGA A schematic diagram of the audio circuitry 1s shown in Figure 3 16 Detailed information for using the 55 2603 codec 15 available in its datasheet which can be found on the manufacturer s website or in Datasheets Audio CODEC folder on the SoCKit System CD
36. OCK EErEE Button x 4 Reset Switch x 4 DDRS IR Receiver Audio 1 Temperature 515338 2C HSMC Wo voltage gw Default 3 i Figure 4 5 HSMC Expansion Group The Prefix Name is an optional feature that denotes the pin name of the daughter card assigned in your design Users may leave this field empty B Project Setting Management The SoC Kit System Builder also provides functions to restore default setting loading a setting and saving users board configuration file shown in Figure 4 6 Users can save the current board configuration information into file and load it to the SoCKit System Builder 50 SoCKit User Manual www terasic com www Ceresic com Cylone SoCEit 1 0 0 ovstem Configuration ter www com Project Name Cylone V SoCKit Evaluation Board CLOCK LED x 4 Button x 4 Reset Switch x 4 Audio 1 Temperature 515338 voltage gw Default Figure 4 6 Project Settings B Project Generation When users press the Generate button the SoCKit System Builder will generate the corresponding Quartus II files and documents as listed in the Table 4 1 Table 4 1 The files generated by SoCKit System Builder E Proetnamev
37. On Transceiver RX bit 1n Transceiver RX bit 2n Transceiver RX bit 3n Transceiver RX bit 4n Transceiver RX bit 5n Transceiver RX bit 6n Transceiver RX bit 7n Transceiver TX bit On Transceiver TX bit 1n Transceiver TX bit 2n Transceiver TX bit 3n Transceiver TX bit 4n Transceiver TX bit 5n Transceiver TX bit 6n Transceiver TX bit 7n LVDS RX or CMOS I O LVDS RX bit 1n or CMOS I O LVDS RX bit 2n or CMOS I O LVDS RX bit 3n or CMOS I O LVDS or CMOS I O 24 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 www terasic com ARROW HSMC RX n 5 HSMC RX n 6 HSMC nI7 HSMC _ 8 HSMC n 9 HSMC RX n 10 HSMC n t1 HSMC RX n 12 HSMC RX n 13 HSMC RX n 14 HSMC RX n 15 HSMC RX n 16 HSMC p O0 HSMC HSMC p 2 HSMC p 3 HSMC HSMC p 5 HSMC RX p 6 HSMC pI7 HSMC 8 HSMC p 9 HSMC RX p 10 HSMC 11 HSMC RX p 12
38. PS Ethernet PHY UART and USB OTG device Active low input that will reset all HPS logics that can be reset Places the HPS in a default state sufficient for software to boot system reset domains which allows debugging to operate his signal connects to the Cyclone V DEV CLRn pin When his pin is driven low all the device registers are KEY5 HPS RESET n 4 FPGA RESET USB Blaster JTAG Connector PIN 6 VCC3P3 KEY 6 HPS FPGA HPS WARM RST n ELLEN WARM RST VCC3P3 HPS RESET n KEY 5 m HPS ENET RESET n HPS RESET n 10 100 1000 Ethernet PHY KSZ9021RN RESET N USB to UART FT232R RESET HPS RESET UART n USB 2 0 PHY 0583300 USB RESET RESET USB3300 MR n VCC3P3 KEY 4 RESET n FPGA RESET n FPGA RESET n Figure 3 8 Reset Tree on the Development Board 3 4 Programming the Quad Serial Configuration Device e The board contains a quad serial configuration device EPCQ256 that stores configuration data for the Cyclone V SoC FPGA This configuration data 15 automatically loaded from the quad 17 SoCKit User Manual www terasic com www Ceresic com ARROW serial configuration device chip into the FPGA when the board is powered up To program the configuration device users will need to use a Serial Flash Loader SFL function to program the quad serial configuration device via the JTAG inte
39. Pin Assignments Signal Name FPGA Pin No Description Standard HPS GSENSOR PIN B22 HPS GSENSOR Interrupt Output 3 3V HPS I2C CLK PIN H23 HPS I2C Clock share bus with LTC 3 3V HPS I2C SDA PIN_A25 HPS 2 Data share bus 83V 3 7 9 128x64 Dots LCD The board equips an LCD Module with 128x64 dots for display capabilities The LCD module uses serial peripheral interface to connect with the HPS To use the LCD module please refer to the datasheet folder in SoCKit System CD Figure 3 28 shows the connections between the HPS and LCD module The default setting for LCD backlight power is ON by shorting the pins of header 1 1 Table 3 30 lists the pin assignments between LCD module and Cyclone V SoC FPGA 42 SoCKit User Manual www terasic com ARROW J20 128x64 LCD Module HPS LCM SPIM SS EN CS1 N E B4 AN 4 HPS LCM SPIM HPS LCM DC Au SoC HPS LCM SPIM MOSI DB7 Sh HPS LCM RST n HPS LCM Backlight Figure 3 28 Connections between Cyclone SoC and LCD Module Table 3 30 LCD Module Pin Assignments Signal Name FPGA Pin No Description Standard HPS LCM D C PIN G22 HPS LCM Data bit is Data Command 3 3V HPS LCM RST N PIN B26 HPS LCM Reset 3 3V HPS LCM SPIM CLK PIN C23 SPI Clock 3 3V HPS LCM SPIM MOSI PIN D22 SPI Master Output Slave Input 3 3V HPS LCM SPIM SS PIN D24 SPI Slave Sele
40. Quartus II Programmer window 1 Choose Programmer Tools menu and the Chain cdf window appears Click Add File From the Select Programming File page browse to file Click Open 2 Program the serial configuration device by checking the corresponding Program Configure box a factory default SFL image will be loaded See Figure 6 6 74 SoCKit User Manual www terasic com www Lerasic com ip Programmer Chain2 cdf Edit View Processing Tools Window 5 S Hardware Setup USB BlasterII USB 1 Enable real time ISP to allow background programming for II and MAX V devices File Device ipli Start Checksum Usercode Factory default enhanced 5CSXFC6 C output file jic OOC6BB6A FFFFFFFF EPCQ256 Auto Detect 97C88BBE Add File 7 Change File Save File fup 0 Down Figure 6 6 Quartus programmer window with JIC file 3 Click Start to program serial configuration device B Erase Quad Serial Configuration Device To erase the existed file in the serial configuration device follow the steps listed below 1 Choose Programmer Tools menu and the Chain cdf window appears 2 Click Add File From the Select Programming File page browse to a JIC file 3 Click Open Erase the serial configuration device by checking the corre
41. User Manual VCC3 P3 C93 VO Standard 5 LTC GPIO 3 3V HPS 12 Clock share bus with 3 3V G Sensor HPS 12 Data share bus with G Sensor 3 3V SPI Clock 3 3V SPI Master Input Slave Output 3 3 SPI Master Output Slave Input 3 3 SPI Slave Select 3 3V 44 www terasic com ARROW Chapter 4 System Builder This chapter describes how users can create a custom design project on the board by using the SoCKit Software Tool SoCKit System Builder 4 1 Introduction The SoCKit System Builder 1s a Windows based software utility designed to assist users to create a Quartus II project for the board within minutes The generated Quartus II project files include Quartus II Project File qpf Quartus II Setting File qsf e Top Level Design File v e Synopsis Design Constraints file sdc e Pin Assignment Document htm By providing the above files the SoCKit System Builder prevents occurrence of situations that are prone to errors when users manually edit the top level design file or place pin assignments The common mistakes that users encounter are the following 1 Board damage due to wrong pin bank voltage assignments 2 Board malfunction caused by wrong device connections or missing pin counts for connected ends 3 Performance degeneration due to improper pin assignments 4 2 General Design Flow This section will i
42. User Manual www terasic com www Cerasic com ARROW A Figure 5 8 Terasic Remote controller Table 5 4 Key code information for each Key on remote controller Key Code Key Code Key Code Key Code om 63 124 51 Terasic SoCKit User Manual www terasic com www 50 MHz TE IR E Controller System Intercoment Fabric Figure 5 9 Block Diagram of the IR Receiver Demonstration Next we will introduce how this information 1s decoded and then displayed in this demo When a key on the remote controller 1s pressed the remote controller will emit a standard frame shown in Figure 5 10 The beginning of the frame 15 the lead code represents the start bit and then is the key related information and the last 1 bit end code represents the end of the frame End Inv Key Code Code Lead Code 151 Custom Code 16bits Key Code 8bits bits Figure 5 10 The transmitting frame of the IR remote controller Terasic SoCKit User Manual www terasic com www Lerasic com ARROW After the IR receiver SoCKit receives this frame it will directly transmit that to FPGA In this demo the IP of IR receiver controller is implemented in the FPGA As Figure 5 11 shows it includes Code Detector State Machine and Shift Register First the IR receiver demodulates the signal input
43. bit 14 or CMOS I O LVDS bit 15 or CMOS I O LVDS bit 16 or CMOS I O LVDS TX bit On or CMOS I O LVDS TX bit 1n or CMOS I O LVDS TX bit 2n or CMOS I O LVDS TX bit or CMOS I O LVDS TX bit 4n or CMOS I O LVDS TX bit 5n or CMOS LVDS TX bit or CMOS I O LVDS TX bit 7n or CMOS I O LVDS TX bit 8n or CMOS I O LVDS TX bit 9n or CMOS I O LVDS TX bit 10n or CMOS I O LVDS TX bit 11n or CMOS I O LVDS TX bit 12n or CMOS I O LVDS TX bit 13n or CMOS I O LVDS TX bit 14n or CMOS I O LVDS TX bit 15n or CMOS I O LVDS TX bit 16n or CMOS I O 25 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 Depend on JP2 www terasic com ARROW HSMC TX PIN A9 LVDS TX bit 0 or CMOS I O Depend on JP2 HSMC TX PIN E8 LVDS TX bit 1 or CMOS I O Depend on JP2 HSMC TX 2 PIN G7 LVDS TX bit 2 or CMOS I O Depend on JP2 HSMC TX p 3 PI
44. ces FPGA default works in ASx4 mode However once the FPGA is in AS x4 mode and after successfully configuring the FPGA via the 256 SoCKit will be unable to boot Linux from SD card or other devices Please switch SW6 to another mode i e MSEL 0 4 00001 to enable normal operations of Linux Figure 3 3 FPGA Configuration Mode Switch Table 3 2 SW6 FPGA Configuration Mode Switch o On ____ 8462 Sets the Cyclone MSEL 0 4 pins 222 6 630000 Use these pins to set the configuration On _ 2 SW 4 Scheme and POR delay On Of Table 3 3 MSEL pin Settings for each Scheme of Cyclone V Device Configuration Design Security Delay Compression Feature Valid MSEL 4 0 Scheme Feature 2 3000 _ Standard 11000 Disabled Enabled 12 Terasic SoCKit User Manual www terasic com Standard Enabled Disabled EOS Standard Fast 00000 Disabled Enabled Fast 00001 Disabled Disabled Standard Fast 00010 Enabled Enabled Standard Fast 10000 Enabled Disabled Disabled Standard Fast AS X1 and X4 Enabled Disabled Enabled Standard 3 1 3 HPS BOOTSEL and CLKSEL Setting Headers The processor in the HPS can be boot from many sources such as the SD card QSPI Flash or FPGA Selecting the boot source for the HPS can be set using the BOOTSEL jumpers J17 J19 See Figure 3 4 and CLKSEL jumpers J15 J16 See Figure 3 5
45. ct 3 3V 3 7 10 LTC Connector The board allows connection to interface card from Linear Technology The interface is implemented using al4 pin header that can be connected to a variety of demo boards from Linear Technology It will be connected to SPI Master and I2C ports of the HPS to allow bidirectional communication with two types of protocols The 14 pin header will allow for GPIO SPI and 2 extension for user purposes if the interfaces to Linear Technology board aren t in use Connections between the LTC connector and the HPS are shown in Figure 3 29 and the functions of the 14 pins is listed in Table 3 31 43 SoCKit User Manual www terasic com www Ceresic com ARROW JA DTE RYA 5 HPS 5 ow O HPS 2 SDA HPS SPIM CLK HPS HPS SPIM CLK HPS SPIM SS HPS SPIM MOSI HPS SPIM MISO HPS 2 SDA 116 HPS 2 HPS 049 TS3A5018 MOSI SDA VCCSP3 LTC ohm Connector 0 ohm N IN HPS GPIO Figure 3 29 Connections between the LTC Connector and HPS Signal Name HPS LTC GPIO HPS I2C CLK HPS I2C SDA HPS SPIM CLK HPS SPIM MISO HPS SPIM MOSI HPS SPIM SS Table 3 31 LTC Connector Pin Assignments FPGA Pin No Description PIN F16 PIN H23 A25 PIN A23 PIN B23 PIN C22 PIN H20 Terasic SoCKit
46. d as shown in Figure 4 4 Each component of the board is listed where users can enable or disable a component according to their design by simply marking a check or removing the check in the field provided If the component 1s enabled the SoCKit System Builder will automatically generate the associated pin assignments including the pin name pin location pin direction and I O standard 48 Terasic User Manual www terasic com www Ceresic com Cylone SoCEit 1 0 0 ter ovstem Configuration www com Project Name Cylone V SoCKit Evaluation Board CLOCK LED x4 Button x 4 Reset Switch x 4 Audio 1 Temperature HSMC Wo voltage 25 Default 9 Figure 4 4 System Configuration Group B HSMC Expansion Users can connect HSMC daughter cards onto the HSMC connector located on the development board shown in Figure 4 5 Select the daughter card you wish to add to your design under the appropriate HSMC connector to which the daughter is connected The System Builder will automatically generate the associated pin assignment including pin name pin location pin direction and I O standard 40 SoCKit User Manual www terasic com www Ceresic com Cylone SoCEit 1 0 0 ovstem Configuration ter www com Project Name Cylone V SoCKit Evaluation Board a W CL
47. debounced and are assumed for use as level sensitive data inputs to a circuit Each switch 1s connected directly to a pin on the Cyclone V SoC FPGA When the switch is in the DOWN position closest to the edge of the board it provides a low logic level to the FPGA and when the switch 1s in the UP position it provides a high logic level 20 Terasic SoCKit User Manual www terasic com ARROW ANU S RYA 1 1 1 Logic SW3 SW2 SW1 Figure 3 13 Connections between slide switches and Cyclone SoC FPGA There are also four user controllable LEDs connected to FPGA on the board Each LED 1s driven directly by a pin on the Cyclone SoC driving its associated pin to a high logic level turns the LED on and driving the pin low turns it off Figure 3 14 shows the connections between LEDs and Cyclone V SoC FPGA Table 3 9 Table 3 10 and Table 3 11 list the pin assignments of these user interfaces LEDO LEDO LED1 A A IZ JA DTE RYA b ngs LLED2 LED2 LEDS A A LED3 Figure 3 14 Connections between the LEDs and Cyclone V SoC FPGA 21 1 5 Terasic SoCKit User Manual www terasic com www ARROW Table 3 9 Pin Assignments for Slide Switches Signal Name FPGA Pin No Description VO Standard 25 Slide Switch 0 2 5V SW 1 PIN V25 Slide Switch 1 2 5V SW 2 PIN_AC28 Slide Switch 2 2 5V SW 3
48. different resolutions and durations of time periods a b c and d for both horizontal and vertical timing Detailed information for using the ADV7123 video DAC is available in its datasheet which can found on the manufacturer s website or in the Datasheets VIDEO DAC folder on the SoCKit System CD The pin assignments between the Cyclone V SoC FPGA and the ADV7123 are listed in Table 3 17 Back porch b Front porch d Display interval c I yS DATA HSYNC sync Figure 3 18 VGA horizontal timing specification Table 3 15 Horizontal Timing Specification VGA mode Horizontal Timing Spec Configuration Resolution HxV a us b us c us d us Pixel clock MHz VGA 60Hz 640x480 3 8 1 9 25 4 0 6 25 VGA 85Hz 640x480 1 6 2 2 17 8 1 6 36 SVGA 60Hz 800x600 3 2 2 2 20 1 40 SVGA 75Hz 800x600 1 6 3 2 16 2 0 3 49 SVGA 85Hz 800x600 1 1 2 7 14 2 0 6 56 XGA 60Hz 1024x768 2 1 2 5 15 8 0 4 65 XGA 70Hz 1024x768 1 8 1 9 13 7 0 3 75 XGA 85Hz 1024x768 1 0 2 2 10 8 0 5 95 1280x1024 60Hz 1280x1024 1 0 2 3 11 9 0 4 108 28 SoCKit User Manual www terasic com ARROW Table 3 16 VGA Vertical Timing Specification Terasic SoCKit User Manual www Ceresic com 29 www terasic com VGA mode Vertical Timing Spec Configuration Resolution HxV a lines b lines c lines d lines Pixel clock MHz VGA 60Hz 640x480 2 33 480 10 25 VGA 85Hz 640x480 3 25 480 1 36 SVGA 60Hz 800x600
49. e the function of board temperature detection Figure 5 15 shows the system block diagram of this demonstration The ambient temperature information which is collected by a built in temperature sensor on the SoCKit board can be converted into digital data by a 13 bit A D converter The generated digital data will be stored into the Temperature Value Register The sensor connects the FPGA device through a SPI interface In this demonstration a SPI master core is used by Nios II software to access the sensor s Temperature Value registers Based on the register s values reading out in every five seconds the program calculates the centigrade degree The relative values are finally displayed onto the nios2 terminal window in order to let the user monitor the board real time temperature 67 1 5 Terasic SoCKit User Manual www terasic com www Ceresic com ARROW FPGA QSYS 50 2 Sensor Figure 5 15 Block diagram of the Temperature Demonstration Demonstration Source Code Project directory SoCKit TEMP Bit stream used SOCkit TEMP Nios If Workspace SoCKit_TEMP Software Demonstration Batch File Demo Batch File Folder SoCKit TEMP demo_ batch The demo batch file includes the following files Batch File SoCKit TEMP bat SoCKit TEMP bashrc FPGA Configure File SoCKit_TEMP sof Nios Program SoCKit Demonstration Setup File Locations and Instructions e Make sur
50. e Quartus II and Nios II are installed on your PC Power on the SoCKit board Connect USB Blaster to the SoCKit board and install USB Blaster driver II if necessary 68 SoCKit User Manual www terasic com ARROW Execute demo batch file SoCKit _TEMP bat under the batch file folder SoCKit TEMP batch After Nios II program is downloaded and executed successfully the related information will be displayed in nios2 terminal shown in Figure 5 16 E Altera Nios II EDS 13 0 4 EL 1 r p LL LL LL LL L L E E L ru n E EL EL m mr m 1 rr rtr rt rt rt rt rt rt rt mr pu pu x E p Lai Lui Pel fa fa Figure 5 16 Running results of the Temperature demonstration 69 Terasic SoCKit User Manual www terasic com www ARROW Chapter 6 Steps of Programming the Quad Serial Configuration Device This chapter describes how to program the quad serial configuration device with Serial Flash Loader SFL function via the JTAG interface User can program quad serial configuration devices with a JTAG indirect configuration jic file To generate JIC programming files with the Quartus II software users need to generate a user specified SRAM ob
51. e SoCKit includes several jumpers switches etc that control various system functions including JTAG chain HSMC I O voltage control HPS boot source select and others This section will explain the settings and functions in detail 3 1 1 J TAG Chain and Setup Switches The SoCKit allows users to access FPGA HPS debug or other JTAG chain devices via on board USB Blaster II Figure 3 1 shows the JTAG chain Users can control whether the HPS or HSMC connector is included in the chain via SW4 See Figure 3 2 where Table 3 1 lists the configuration details SoCKit User Manual www terasic com ARROW Extemal J TAG Header Not Installed Micro Connector HPS Switch HSMC TDI HSMC 5 M C JTAG EN 5 EN DIP Switch SWA Figure 3 1 The JTAG chain on the board Figure 3 2 JTAG Chain and Setup Switches Table 3 1 5 4 JTAG Control DIP Switch Board Reference Signal Name Default On Bypass HPS On Bypass HSMC 11 User Manual www terasic com www Ceresic com ARROW 3 1 2 FPGA Configuration Mode Switch The Dipswitch SW6 See Figure 3 3 can set the MSEL pins to decide the FPGA configuration modes Table 3 2 shows the switch controls and descriptions Table 3 3 gives the MSEL pins setting for each configuration scheme of Cyclone V devi
52. gram Figure 5 5 shows the function block diagram of this demonstration The controller uses 50 MHz as a reference clock generates one 300 MHz clock as memory clock and generates one half rate system clock 150MHz for the controller itself ew ew ew DDR3 Memory UNIPHY Avalon Tes SRAM H 9 RZQ Figure 5 5 Block Diagram of the DDR3 SDRAM 1G Demonstration RW test modules read and write the entire memory space of the DDR3 through the Avalon interface of the controller In this project the Avalon bus read write test module will first write the entire memory and then compare the read back data with the regenerated data the same sequence as the write data KEYO will trigger test control signals for the DDR3 and the LEDs will indicate the test results according to Table 5 3 B Altera DDR3 SDRAM Controller with UniPHY To use the Altera DDR3 controller users need to perform three major steps 1 Create correct pin assignments for the DDR3 Setup correct parameters in DDR3 controller dialog Perform Analysis and Synthesis by selecting from the Quartus menu Process Start Start Analysis amp Synthesis 4 Run the TCL files generated by DDR3 IP by selecting from the Quartus II menu Tools gt TCL Scripts d 58 SoCKit User Manual www terasic com ARROW Design Tools 64 Bit
53. hown in Figure 2 1 and Figure 2 2 It depicts the layout of the board and indicates the location of the connectors and key components HPS m FPGA System USB UART Controller 12V DC Power Supply Connector Altera USB Blaster Controller Chip Power ON OFF Switch USB OTG Controller ULPI TSE PHY LTC Connector HPS DDR3 1GB CLKSEL Jumper 128x64 Dots LCD G Sensor LCD Backlight Jumper USB 2 0 OTG Port JTAG USB Blaster II USB UART Header Port Port HPS System HPS User Keys Reset Keys HPS User Port Ethernet 10 100 1000 VGA 24 bit DAC Connector Switches Switches HPS User LEDs FPGA User LEDs Line Mic In In FPGA User FPGA User Keys FPGA Reset Key Figure 2 1 Development Board top view SoCKit User Manual www Ceresic com Bottom Side Components QSPI Flash 128MB Micro SD Card Socket FPGA Configuration Mode Switch JTAG Switch Audio Codec FPGA DDR3 1GB EPCQ 256Mb HSMC Connector Altera 28 nm Cyclone V FPGA with ARM Cortex A9 BOOTSEL Jumper Temperature Sensor Clock Circuit for FPGA and HPS IR Receiver HSMC Voltage Level Jumper www terasic com ARROW 5 ee d 013040006 es Tic TEC 197 em 5 218 6 1988199 c Due ad ee 116 OR3_VREF_FPGA 4 8223 1551979 91225 Configuration Mode Switch QSPI Flash 128MB 1 217 a2
54. inal USB BlasterII USB 1 device 1 instance 0 nios2 terminal Use the IDE stop button or Ctrl C to terminate DDR3 Test Size 102HMB CPU Clock 100000000 Press any KEV to start test KEVO for continued test DDR3 Testing Iteration 1 write 19 20 30 40 50 60 70 80 90 100 1 19 20 30 40 50 60 70 80 90 100 DDR3 test Pass 180 seconds KEYO for continued test gt DDR3 Testing Iteration 1 write 10 20 _ Figure 5 7 Display Progress and Result Information for the DDR3 Demonstration 5 5 IR Receiver Demonstration In this demonstration the key code information that the user has pressed on the remote controller Figure 5 8 Table 5 4 will be displayed in nios2 terminal The remote controller can be purchased from website or user can use any remote control We use Terasic remote controller for the following demonstration Users only need to point the remote controller to the IR receiver on SoC Kit and press the key After the signal being decoded and processed through FPGA the related information will be included in hexadecimal format which contains Custom Code Key Code and Inversed Key Code The Custom Code and Key Code are used to identify a remote controller and key on the remote controller respectively Finally the key code information will be displayed in nios2 terminal Figure 5 9 shows the block diagram of the design 62 Terasic SoCKit
55. is section introduces the interfaces connected to the HPS section of the FPGA Users can access these interfaces via the HPS processor 3 7 1 User Push buttons Switches and LED on HPS Like the FPGA the HPS also features its own set of switches buttons LEDs and other user interfaces Users can control these interfaces for observing HPS status and debugging Table 3 21 gives the all the pin assignments of all the user interfaces Table 3 21 Pin Assignments for LEDs Switches and Buttons Signal HPS GPIO Register bit Function Pe GPIO2 21 Input only HPS 1 GPI9 GPIO2 22 Input only HPS KEY 2 10 GPIO2 23 Input only HPS 3 11 GPIO2 24 Input only _ HPS SWIO GPIO2 20 Input HPS GPI6 2 19 Input only HPS SWI2 EE GPIO2 18 Input only _ HPS SWIS GPIO2 17 Input only HPS LED O GPIO54 GPIO1 25 VO HPS GPIOSS GPIO1 26 Vo HPS_LED 2 GPIOS6 GPIO1 27 Vo HPS GPIO57 GPIO1 28 3 7 2 Gigabit Ethernet The board provides Ethernet support via an external Micrel KSZ9021 RN PHY chip and HPS Ethernet MAC function The KSZ9021RN chip with integrated 10 100 1000 Mbps Gigabit Ethernet transceiver support RGMII interfaces Figure 3 22 shows the connection setup between the Gigabit Ethernet PHY and Cyclone V SoC FPGA 34 Terasic SoCKit User Manual www Cere
56. ject sof which is the input file first Next users need to convert the SOF to a file To convert a SOF to a JIC file in Quartus II software follow these steps B Before you Begin To use the Quad serial flash as a FPGA configuration device the FPGA will need to be set in Asx4 mode To do this adjust the configuration mode switch SW6 to let MSEL 4 0 to be set as 10010 B Convert SOF File to file l Choose Convert Programming Files on Quartus window File menu 70 Terasic SoCKit User Manual www terasic com www Cerasic com ARROW Edit View Project Assignments Process Close New Project Wizard Open Project Save Project Close Project Save Ctrl4 5 Save Save All Ctrl 5hift 5 File Properties Create Update Convert Programming Files Figure 6 1 File menu of Quartus In the Convert Programming Files dialog box scroll to the JTAG Indirect Configuration File jic from the Programming file type field In the Configuration device field choose EPCQ256 In the Mode field choose Active Serial X4 In the File name field browse to the target directory and specify an output file name Highlight the SOF data in the Input files to convert section See Figure 6 2 71 1 5 Terasic SoCKit User Manual www terasic com www ARROW ij Convert Programming File J File Tools Window
57. n DDR3 DDR3 CK n DDR3 CK p DDR3 CS n DDR3_DM 0 DDR3 DM 1 DDR3 DM 2 Datax16 Address amp Command Datax16 Figure 3 20 Connections between FPGA and DDR3 Table 3 19 Pin Assignments for DDR3 FPGA Pin No PIN AJ14 PIN AK14 PIN AH12 PIN AJ12 PIN AG15 PIN AH15 PIN AK12 PIN AK13 PIN AH13 PIN AH14 PIN AJ9 PIN AK9 PIN AK7 PIN AK8 PIN AG12 PIN AH10 PIN AJ11 11 AJ21 15 14 15 17 23 23 DDR3 Address 0 DDR3 Address 1 DDR3 Address 2 DDR3 Address 3 DDR3 Address 4 DDR3 Address 5 DDR3 Address 6 DDR3 Address 7 DDR3 Address 8 DDR3 Address 9 DDR3 Address 10 DDR3 Address 11 DDR3 Address 12 DDR3 Address 13 DDR3 Address 14 DDR3 Bank Address 0 DDR3 Bank Address 1 DDR3 Bank Address 2 DDR3 Column Address Strobe Clock Enable pin for DDR3 Clock for DDR3 Clock for DDR3 DDR3 Chip Select DDR3 Data Mask 0 DDR3 Data Mask 1 DDR3 Data Mask 2 31 Terasic SoCKit User Manual www Ceresic com DDR3 Device DDR3 Device Standard SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL 15 Class SSTL
58. nnects to the host using a Micro USB B connector For detailed information on how to use the transceiver please refer to the datasheet which 1s available on the manufacturer s website or in the Datasheets VFT232 folder on the SoCKit System CD Figure 3 23 shows the related schematics and Table 3 24 lists the pin assignments of HPS in Cyclone V SoC FPGA FT232 DP ATERA T FT232 DM 4 5 Micro USB B Connector HPS RESET n FT232R Jm Figure 3 23 Connections between Cyclone SoC FPGA and FT232R Chip 36 SoCKit User Manual www terasic com ARROW Table 3 24 UART Interface O Signal Name FPGA Pin No Description VO Standard HPS_UART_RX PIN_B25 HPS UART Receiver 3 3V HPS_UART_TX 25 HPS UART Transmitter 3 3V HPS CONV USB n PIN B15 Reserve 3 3V 3 7 4 DDR3 Memory on HPS The DDR3 devices that are connected to the HPS are the exact same devices connected to the FPGA capacity 1GB and data width 32 bit comprised of two x16 devices with a single address command bus This interface connects to dedicate Hard Memory Controller for HPS I O banks and the target speed is 400 MHz Table 3 25 lists DDR3 pin assignments I O standards and descriptions with Cyclone V SoC FPGA Table 3 25 Pin Assignments for DDR3 Memory Standard Signal Name FPGA Pin No Description HPS DDR3 0 HPS DDR3 A 1 HPS DDR3 2
59. ntroduce the general design flow to build a project for the development board via the SoCKit System Builder The general design flow is illustrated in Figure 4 1 Users should launch the SoCKit System Builder and create a new project according to their design requirements When users complete the settings the SoCKit System Builder will generate two major files a top level design file v and a Quartus II setting file qsf 45 Terasic SoCKit User Manual www terasic com www Cerasic com ARROW The top level design file contains top level Verilog HDL wrapper for users to add their own design logic The Quartus II setting file contains information such as FPGA device type top level pin assignment and the I O standard for each user defined pin Finally the Quartus II programmer must be used to download SOF file to the development board using a JTAG interface Launch SOC Kit System Builder Create New SOC Kit System Builder Project Launch Quartus and Open Project Add User Design Logic Compile to generate Configure Generate Quartus Project and Document Figure 4 1 The general design flow of building a design 4 3 Using SoCKit System Builder This section provides the detailed procedures on how the SoCKit System Builder 15 used B Install and launch the SoCKit System Builder The SoC Kit System Builder is located in the directory ToolsNSOC Kit system builder the SoCKit S
60. ote control receiver module model IRM V5XX TR1 whose datasheet is offered in the Datasheets folder SoCKit System CD The accompanied remote controller with an encoding chip of uPD6121G is very suitable of generating expected infrared signals Figure 3 19 shows the related schematic of the IR receiver Table 3 18 shows the IR receiver interface pin assignments IRDA RXD OUT JNO VCC3P3 Cyclone GND CHASSIS Figure 3 19 Connection between FPGA and Table 3 18 Pin Assignments for IR Signal Name FPGA Pin Description _ Standard PIN 2 IR Receiver 3 3V 3 6 6 DDR3 Memory on FPGA The board supports IGB of DDR3 SDRAM comprising of two x16 bit DDR3 devices on FPGA side The DDR3 devices shipped with this board are running at 400MHz if the hard external memory interface is enabled and at 300MHz if the hard external memory interface if not enabled Figure 3 20 shows the connections between the DDR3 and Cyclone V SoC FPGA Table 3 19 shows the DDR3 interface pin assignments 30 SoCKit User Manual www terasic com ANU RIA Signal DDR3 DDR3 A 1 DDR3 2 DDR3 A 3 DDR3 A 4 DDR3 A 5 DDR3 A 6 DDR3 A 7 DDR3 A 8 DDR3 A 9 DDR3 A 10 DDR3 A 11 DDR3 A 12 DDR3 A 13 DDR3 A 14 DDR3 DDR3 BA 1 DDR3 BA 2 DDR3 CAS
61. r audio source Slide Switches 0 DOWN Position 1 UP Position Audio is from MIC Audio is from LINE IN 54 Terasic SoCKit User Manual www terasic com ARROW Table 5 2 Slide switch setting for sample rate switching for audio recorder and player SW3 SW2 SW1 0 DOWN 0 DOWN 0 DOWN Sample Rate 1 UP 1 UP 1 UP 0 0 0 96K 0 0 1 48K 0 1 0 44 1K 0 1 1 32K 1 0 0 8K Unlisted combination 96K 1 Execute SoCKit _Audio SoCKit _Audio bat will download sof and elf files 2 Recording process will stop if audio buffer is full 3 Playing process will stop if audio data is played completely 5 2 A Karaoke Machine This demonstration uses the microphone in line in and line out ports on the SOCKIT board to create a Karaoke Machine application The SSM2603 audio CODEC 15 configured in the master mode with which the audio CODEC generates AD DA serial bit clock BCK and the left right channel clock LRCK automatically As indicated in Figure 5 3 the I2C interface is used to configure the Audio CODEC The sample rate and gain of the CODEC are set this manner and the data input from the line in port 15 then mixed with the microphone in port and the result 15 sent to the line out port For this demonstration the sample rate is set to 48kHz Pressing the pushbutton KEYO reconfigures the gain of the audio CODEC via I2C bus cycling within ten predefined gain values volume levels
62. rface The FPGA based SFL is a soft intellectual property IP core within the FPGA that bridges the JTAG and flash interfaces The SFL mega function is available from Quartus II software Figure 3 9 shows the programming method when adopting a SFL solution Please refer to Chapter Steps of Programming the Quad Serial Configuration Device for the basic programming instruction on the serial configuration device ANU S RYAN Quartus Programmer SFL Image i JTAG ASx4 USB Blaster to Bridge ASM E Configuration Circuit The JTAG Device Figure 3 9 Programming a Quad Serial Configuration Device with the SFL Solution Note Before programming the quad serial configuration device please set the FPGA configuration mode switch SW6 to ASx4 mode 3 5 Clock Circuits Figure 3 10 is a diagram showing the default frequencies of all of the external clocks going to the Cyclone V SoC FPGA 18 SoCKit User Manual www terasic com ARROW 515338 Level OSC 50 B5B 50MHz m Translator CLKAP Level 50 BBA 50MHz CLK6P Translator OSC 50 B3B 50MHz CLKOP OSC 50 4 50 HAMC REF p 100MH CLK2A pl 2 REFCLK2LP CLK6N HSMC_CLK_INO HSMC REF CLK n 100MHz CLK2B REFCLK2LN CLK5P HSMC CLKIN p1 CLK
63. riph jic and output_file core rbf File E x Properties Figure 6 3 Highlight Flash Loader 12 Select the targeted FPGA that you are using to program the serial configuration device See Figure 6 4 13 Click OK The Convert Programming Files page displays See Figure 6 5 14 Click Generate 13 Terasic SoCKit User Manual www terasic com www Ceresic com ARROW Figure 6 4 Select Devices Page MA Convert Programming Fil Search altera com You can also import input file information from other files and save the conversion setup information created here for future use Conversion setup files Output programming file Programing Ops Congraton deve File name C output file jic Advanced Remote Local update difference file NONE Create Memory Map File Generate output file map Create CvP files Generate output file periph jic and output file core rbf Input files to convert area Add Sof Page Add Device Remove Properties Figure 6 5 Convert Programming Files Page B Write JIC File into Quad Serial Configuration Device To program the serial configuration device with the JIC file that you just created add the file to the Quartus II Programmer window and follow the steps 1 When SOF to JIC file conversion is complete add the file to the
64. rs In this example the audio chip 15 configured in Master Mode The audio interface 1s configured as 125 and 16 bit mode 18 432MHz clock generated by the PLL 15 connected to the MCLK XTI pin of the audio chip through the AUDIO Controller 53 Terasic SoCKit User Manual www terasic com www Ceresic com ARROW s Store Audio Data Clock to SDRAM 4 LED KEY KON ALAC QSYS SOMHz RESET n gt 5 5 Figure 5 2 Block diagram of the audio recorder and player Demonstration Setup File Locations and Instructions Hardware Project directory SoCKit Audio Bit stream used SoCKit Audio sof Software Project directory SoCKit _Audio software Connect an Audio Source to the LINE IN port of the SoCKit board Connect a Microphone to MIC IN port on the SoCKit board Connect a speaker or headset to LINE OUT port on the SoCKit board Load the bit stream into FPGA note 1 Load the Software Execution File into FPGA note 1 Configure audio with the Slide switches SWO as shown in Table 5 1 Press KEY3 on the SoCKit board to start stop audio recording note 72 During audio recording process LED 3 will illuminate Press KEY2 on the SoCKit board to start stop audio playing note 3 During audio playing process LED 2 will illuminate Table 5 1 Slide switches usage fo
65. s USB interfaces using the SMSC USB3300 controller A SMSC USB3300 device a 32 QFN package device is used to interface to a single AB Micro USB connector This device supports UTMI Low Pin Interface ULPI to communicate to USB 2 0 controller in HPS As defined by OTG mode the PHY can operate in Host or Device modes When operating in Host mode the interface will supply the power to the device through the Micro USB interface Figure 3 26 shows the schematic diagram of the USB circuitry the pin assignments for the associated interface are listed in Table 3 28 40 Tasic Terasic SoCKit User Manual www terasic com ARROW Ui HPS USB DATA 7 0 USB CPEN DATA 7 0 CPEN EN TTE LaL UEM CLKOUT EXTVBUS 2 EAULT S RYA b HPS USB NXT vgus 4 USB VBUS TPS2553DRVR HPS USB DIR USB DM Soc HPS USB STP USB DP HPS USB ID U7 B3 51502 253500 CLE U30 amp 1883300 HPS RESET ADMB11 USB VOCS Micro USB AB Connector Figure 3 26 Connections between Cyclone V SoC FPGA and USB OTG PHY Table 3 28 USB OTG PHY Pin Assignments Signal Name FPGA Pin No Description HPS USB CLKOUT PIN N16 60MHz Reference Clock Output HPS USB DATA 0 PIN E16 HPS USB DATA 0 HPS USB DATA 1 PIN G16 HPS USB DATA 1 HPS USB DATA 2 PIN D16 HPS USB DATA 2 HPS USB DATA 3 PIN D14 HPS USB DATA 3 HPS USB DATA 4 PIN A15 HPS USB
66. sic com www terasic com ARROW The associated pin assignments are listed in Table 3 22 For detailed information on how to use the KSZ9021RN refers to its datasheet and application notes which are available on the manufacturer s website HPS TX DATA 3 0 HPS ENET GTX CLK 5 ILC HPS ENET TX EN HPS DATA 3 0 HPS ENET RX CLK HPS ENET RX DV HPS ENET MDC HPS ENET MDIO HPS ENET INT N HPS ENET RESET N KSZ9021RN U13 TXD 3 0 GTX CLK TX EN 01 DV MDC MDIO INT N RESET N MDI HPS N MDI HPS P LED2 DUAL 1 LED2 DUAL 2 RJ45 1368589 5 Figure 3 22 Connections between Cyclone V SoC FPGA and Ethernet Table 3 22 Pin Assignments for Ethernet PHY Signal Name HPS ENET TX EN HPS DATA O HPS ENET TX DATA 1 HPS ENET TX DATA 2 HPS TX DATA 3 HPS ENET RX DV HPS DATA 0 HPS ENET RX DATA 1 HPS ENET RX DATA 2 HPS ENET RX DATA 3 HPS ENET RX CLK HPS ENET RESET n HPS ENET MDIO HPS ENET MDC HPS ENET INT n HPS ENET GTX CLK FPGA Pin No PIN A20 PIN F20 PIN J19 PIN F21 PIN F19 PIN K17 PIN A21 PIN B20 PIN B18 PIN D21 PIN G20 PIN E18 PIN E21 PIN B21 PIN C19 PIN H19 Description Standard GMII and MII transmit enable 3 3V MII transmit data 0 3 3V Mil transmit data 1 3 3V Mil transmit data 2 3 3V Mil transmit data 3
67. sponding Erase box a Factory default SFL image will be load See Figure 6 7 T3 SoCKit User Manual www terasic com ARROW Chain3 Edit View Processing Tools Window Help 57 Search altera com i enn m oc Enable real time ISP to allow background programming for MAX II and MAX V devices Figure 6 7 Erasing setting in Quartus Il programmer window 5 Click Start to erase the serial configuration device 76 TuasiC Terasic SoCKit User Manual www terasic com www Lerasic com ARROW Chapter 7 Appendix 7 1 Revision History Change Log Initial Version Preliminary Add 5 and Modify CH3 7 2 Copyright Statement Copyright 2013 Terasic Technologies All rights reserved 7 SoCKit User Manual www terasic com
68. summarizes the pins on the flash device Signal names are from the device datasheet and directions are relative to the Cyclone V SoC FPGA Table 3 26 QSPI Flash Interface I O Signal Name FPGA Pin No Description Standard HPS FLASH PIN C20 HPS FLASH Data 0 3 3V HPS FLASH DATA 1 PIN H18 HPS FLASH Data 1 3 3V HPS FLASH DATA 2 PIN A19 HPS FLASH Data 2 3 3V HPS FLASH DATA 3 PIN E19 HPS FLASH Data 3 3 3V HPS FLASH DCLK PIN D19 HPS FLASH Data Clock 3 3V HPS FLASH NCSO PIN A18 HPS FLASH Chip Enable 3 3V 39 SoCKit User Manual www terasic com ARROW 3 7 6 Micro SD The board supports Micro SD card interface using x4 data lines And it may contain secondary boot code for HPS Figure 3 25 shows the related signals Finally Table 3 27 lists all the associated pins for interfacing HPS respectively SD_CLK SD_CMD A DTE RYAN SD DATO Micro SD Card Ec Soke SCSXFCSDEFS1 Vu HPS y SD_DAT3 CD W ESD ESD ESD 1 Figure 3 25 Connections between Cyclone V SoC FPGA and SD Card Socket Table 3 27 SD Card Socket Pin Assignments Signal Name FPGA Pin Description Standard HPS SD CLK PIN A16 HPS SD Clock 3 3V HPS SD CMD PIN F18 HPS SD Command Line 3 3V HPS SD PIN G18 HPS SD Data 0 3 3V HPS SD DATA 1 PIN C17 HPS SD Data 1 3 3V HPS SD DATA 2 PIN D17 HPS SD Data 2 3 3V 5 SD DATA 3 PIN B16 HPS SD Data 3 3 3V 3 7 7 USB 2 0 OTG PHY The board provide
69. t DDR3 test pass LED2 Blinks 59 Terasic SoCKit User Manual www terasic com www Cerasic com 5 4 DDR3 SDRAM Test by Nios Many applications use a high performance RAM such as a DDR3 SDRAM to provide temporary storage In this demonstration hardware and software designs are provided to illustrate how to perform DDR3 memory access in QS YS We describe how the Altera s DDR3 SDRAM Controller with UniPHY IP 1s used to access a DDR3 SDRAM and how the Nios II processor is used to read and write the SDRAM for hardware verification The DDR3 SDRAM controller handles complex aspects of using DDR3 SDRAM by initializing the memory devices managing SDRAM banks and keeping the devices refreshed at appropriate intervals B System Block Diagram Figure 5 6 shows the system block diagram of this demonstration The system requires a 50 MHz clock provided from the board The DDR3 controller is configured as a GB DDR3 300 controller DDR3 IP generates 300 MHz clock as SDRAM s data clock and one half rate system clock 150 MHz for those host controllers e g Nios II processor accessing the SDRAM In the QSYS Nios and the On Chip Memory are designed running with the 100MHz clock and the Nios program is running the on chip memory FPGA Q9 5 5 50 MHz Ee EN Timer On Chip Memory dmm DDR3 gt DDR3 Controller SDRAM System Intercoment Fabric
70. t board with the built in Audio CODEC chip This demonstration is developed based on Qsys and Eclipse Figure 5 1 shows the man machine interface of this demonstration Two push buttons and four slide switches are used for users to configure this audio system SWO 15 used to specify recording source to be Line in or MIC In SW1 SW2 and SW3 are used to specify recording sample rate as 96K 48K 44 1K 32K or 8K Table 5 1 and Table 5 2 summarize the usage of Slide switches for configuring the audio recorder and player 52 Terasic SoCKit User Manual www terasic com www Cerasic com E ee DE Nl UL t gt gt Sample rate Play P Record Audio Source Figure 5 1 Man Machine Interface of Audio Recorder and Player Figure 5 2 shows the block diagram of the Audio Recorder and Player design There are hardware and software parts in the block diagram The software part stores the Nios II program in the on chip memory The software part 15 built by Eclipse in C programming language The hardware part 15 built by Qsys under Quartus II The hardware part includes all the other blocks The AUDIO Controller 15 user defined Qsys component It 15 designed to send audio data to the audio chip or receive audio data from the audio chip The audio chip 15 programmed through I2C protocol which 15 implemented in C code The I2C pins from audio chip are connected to Qsys System Interconnect Fabric through PIO controlle
71. tings Figure 3 6 HSMC VCCIO Voltage Level Setting Header Table 3 6 JP2 Header Setting for Different I O Standard JP2 Jumper Setting Voltage of HSMC Connector Short Pin 1 and 2 Short Pin 3 and 4 Short Pin 5 and 6 2 5V Default Short Pin 7 and 8 Note 1 JP2 only allows for one jumper at one time 2 If no jumper is attached on JP2 the voltage standard will default to 1 5V 3 2 Board Status Elements The board includes status LEDs Please refer to Table 3 7 for the status of the LED indicator 15 SoCKit User Manual www terasic com ARROW Table 3 7 LED Indicators Board Reference LED Name Description D5 12 V Power illuminates when 12 power is active UART TXD when data from FT232R to USB Host UARTRxp when data from USB Host to FT232R HSMC PSNTN when connecting a daughter on connector SC RX 4 SC TX 3 3 Board Reset Elements The board equips two HPS reset circuits and one FPGA Device Clear button See Figure 3 7 Table 3 8 shows the buttons references and its descriptions Figure 3 8 shows the reset tree on the board 5 RST n FPGA RESET n Figure 3 7 Board Reset Elements 16 www terasic com www Ceresic com Table 3 8 Reset Elements Board Reference Signal Name Description Cold reset to the H
72. tograph of the SoCKit package Q SoCKit Board SoCKit Quick Start Guide Power DC Adapter 12V Ethernet Cat 5e Cable A to Micro B USB Cable x2 Figure 1 1 The SoCKit package contents www terasic com ARROW The SoCKit package includes SoCKit development board USB Cable for FPGA programming and control Ethernet Cable 12V DC power adapter 1 2 SoCKit System CD The SoCKit System CD containing the SoCKit documentation and supporting materials including the User Manual System Builder reference designs and device datasheets User can download this System CD form the link http sockit_support terasic com 1 3 Getting Help For discussion support and reference designs please go to o RocketBoards or Arrow SoCKit Evaluation Board Arrow SoCKIT Evaluation Board How to Boot Linux Here are the addresses where you can get help if you encounter any problem e Terasic Technologies Taiwan 9F No 176 Sec 2 Gongdao 5th Rd East Dist Hsinchu City Taiwan 300 70 Email support terasic com Tel 886 3 5750 880 Web http sockit terasic com SoCKit User Manual www terasic com ARROW Chapter 2 Introduction of the SoCkit This chapter presents the features and design characteristics of the board 2 1 Layout and Components Board A photograph of the board is s
73. udio 24 bit CODEC line out and microphone in jacks Switches Buttons and LEDs User Keys FPGA x4 HPS x 4 User Switches FPGA x4 HPS x 4 e 8 User LEDs FPGA x4 HPS x 4 2 HPS Reset Buttons HPS RSET n and 5 WARM RST n Y Terasic SoCKit User Manual www terasic com www Cerasic com ARROW Sensors G Sensor on HPS e Temperature Sensor on FPGA Power 12V DC input 2 2 Block Diagram of the SoCKit Board Figure 2 3 gives the block diagram of the board To provide maximum flexibility for the user all connections are made through the Cyclone V SoC FPGA device Thus the user can configure the FPGA to implement any system design SoCKit User Manual www terasic com www ARROW LTC Connector to SPI I2C Devices x6 HSMC Connector x3 i _ G Sensor Soc 5CSXFC6D6F31 RGMII Ethernet DDR3 x16 10 100 1000 SDRAM x32 1024 MB 5 ew USB 2 0 OTG DDR3 72 32 1024 5 s Line In ew Mircro B SD Card Slide Switch x8 Button Switch x8 Figure 2 3 Board Block Diagram 9 1 5 Terasic SoCKit User Manual www terasic com www Ceresic com ARROW Chapter 3 Using the SoCkKit Board This chapter gives instructions for using the board and describes each of its peripherals 3 1 Board Setup Components Th
74. ystem CD Users can copy the whole folder to a host computer without installing the utility Launch the SoCKit System Builder by executing the SOC Kit SystemBuilder exe on the host computer and the GUI window will appear as shown in Figure 4 2 46 SoCKit User Manual www terasic com Cylone SoCEit 1 0 0 ter ovstem Configuration www com Project Name Cylone V SoCKit Evaluation Board 4 McLock MLEDx4 Button x 4 Reset Switch x 4 Audio 1 Temperature 515338 HSMC Wo voltage 25 Default 9 Figure 4 2 SoCKit System Builder window B Input Project Name Input project name as show in Figure 4 3 Project Name Type in an appropriate name here it will automatically be assigned as the name of your top level design entity 47 SoCKit User Manual www terasic com www Ceresic com Cylone SoCEit 1 0 0 ter System Configuration www com Project Name Cylone V SoCKit Evaluation Board Sockt M CLOCK e LED x4 Button x 4 Reset Switch x 4 DDRS IR Receiver HVGA Audio 1 Temperature 515338 LC HSMC Voltage 25 Default 9 Figure 4 3 Board Type and Project Name B System Configuration Under the System Configuration users are given the flexibility of enabling their choice of included components on the boar

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