56F805 - HW.cz
Contents
1. 5 Y 81 JO 1994 5001 1900159 1 0002 v0 Aepsany 9120 Es 8 ASH UNTER 99 1 m 7 3SN3S 1N3HHflO0 H3AO 5 AHVQNOO3S ANY enu T the 9567 568 219 4 0626 968 216 B 8698 96 8 XL unsny 189M uouue 1099 UOISIAIg 194125406 85994 HSNHS T TW HSNHS LINYA SNA OG LNWNWN0O V SNA V INN ANVINOOSS Wei 535 DI H3AO Ted 18190va lt lt z CH wm SENTES KSE 4 d 9757 DIR Ser DIE T T c anyo IH SSNHS LINYA aver uo 1 E IV ASNES Linwd 1 LNSWHOD NHAO SNA SLE ATAO SNA eer IND WE eny INN XNVWINd Wi om 8018 eg 99 60 E wesen al sroHd ens VEBENT ER lt en eaLinvs lt lt SCH EIDA lt lt eu ASNES LINYA AC HSNHS LINYA Ae ASWHd zu LNWHHD ASWHd t INQ 5 AHVNWI Id 5 He Wh 928 Wh SE F ig 20 wot2. 00 57115 NES STOWE tns HOLOHNNOD IND ANVINODSS SI 8Hd ENS Si VHd ens lt 3W3 8 tns 8 3W3 X8 tns X ou 7 DS ge SSNS ONS g Y HW3 SS Ens 9 X oYaz tns V aswa YONI A ENS Dr us 8 X 0437 ens 2 L OH3Z 5 94155042 ONSZ 4 9 gt 8 X OH3Z ENS NISsOWO rr SNISSONO 2 V aSWHa V X 0437 ENS n 03d 505 Od CNS AAO Ens oe 984 AIVA HSNSS FAING YOLOW d ENS 92 SILOHd_ NS SNES INgNNDD O geng YOLOW ASNAS Auen SSVHd SI Hd ENS ve ENS SNES 1 V 5 ASNES Aan 508 20 INN ANVINOOSS SH Od S ens 8 91 r ob ob vBINMd 8 gg 9 zaWMd 2 zv 3 5 a Y 56F805EVM Schematics Rev 5 Appendix A 9 Freescale Semiconductor si duunr pue esoding 9 1 6 4 a 8658 55 8 XL unsny ISOM uouue 1099 UOISIAIG 4 411254 lt 55 gt JO 6 1994 1001 19uBis q 0002 vo
3. J31 Pin Signal Pin Signal 21 Motor DC Bus Voltage Sense 22 Motor DC Bus Current Sense 23 Motor Phase A Current Sense 24 Motor Phase B Current Sense 25 Motor Phase C Current Sense 26 Motor Drive Temperature Sense 27 NC 28 Shield 29 Motor Drive Brake Control 30 Serial COM 31 PFC PWM 32 PFC Inhibit 33 PFC Zero Cross 34 Zero Cross A 35 Zero Cross B 36 Zero Cross C 37 Shield 38 Back EMF Phase A Sense 39 Back EMF Phase B Sense 40 Back EMF Phase C Sense Table 2 9 Unused Secondary UNI 3 Connector Signal Description J14 Pin Signal Pin Signal 1 SU3 ZERO X A 2 SU3 ZERO X B 3 SU3 ZERO X C 4 SU3 BK EMF A 5 SU3 BK EMF B 6 SU3 BK EMF C 7 SU3 PHA IS 8 503 PHB 15 9 503 15 10 503 S 11 GND 12 5 0V 13 NC 14 NC DSP56F805EVM User Manual Rev 5 Freescale Semiconductor General Switches Run Stop Switch 2 13 General Purpose Switches and Run Stop Switch Two general purpose user push button switches are connected to Port D GPIO signals PD3 and A Run Stop toggle switch is connected to GPIO signal 5 Refer to Figure 2 9 56F805 GP SWITCH 1 2 SWITCH 2 Figure 2 9 Run Stop and General Purpose Switches Technical Summary Rev 5 Freescale Semiconductor 2 17 2 14 Serial 10 bit 4 channel D A Converter 56F805EVM board contains a serial 10
4. DSP56F805EVM User Manual Rev 5 Freescale Semiconductor Appendix A 6 5837 Joen 99241 NMd 9 V 4 JO 9 19945 1001 juawdojaneg 19 61590 0002 vo Aepsony d EL Joaquin NSQ WA3508395dSQ 9215 957 9351 V iHOd ant vi 3O dN 959 568 215 XV4 0626 568 216 8698 96 8 X1 utisny ISOM uouue 1099 UOISIAIG 199 11259 5 55 70974 lt zgd EL gt Dr 9 3611 00 lt 18 MOT13A T cou Ber wasn ae 08d lt CN WM 9 5 gt 70974 0611 amp FHM 4371 MOTISA 8931 9611 00 lt EYNMd S IH I q31 Diss oz vein lt lt ALLS WMd an mons K mm 00 lt IVINMd 1 LLAZA atin z lt lt 031 MO113A gt seu A 8 3 I 8 56F805EVM Schematics Rev 5 7 Freescale Semiconductor 1 Z Y eJnBi4 3 8 10 19945 001 ueuBiseq 0002 0 Aepseny ejeg 8 1 D Jequin NSa WAaS0849SdSq will azs 9 8 1 6
5. J3 Pin Signal Alternate 1 TAO 0 2 1 PhaseBO 3 TA2 INDEXO 4 5 3 3 3 3V 6 GND GND Technical Summary Rev 5 Freescale Semiconductor 2 29 2 22 6 Secondary Encoder Timer Channel Expansion Connector Secondary Channel port is port attached to expansion connector The port can act as Quadrature Decoder interface port or as a general purpose Timer port Refer to Table 2 19 for the signals attached to the connector Table 2 19 Timer B Connector Description J6 Pin Signal Alternate 1 TBO PhaseA1 2 TB1 PhaseB1 3 TB2 INDEX1 4 TB3 HOME1 5 3 3 3 3 6 GND GND 2 22 7 Timer Channel C Expansion Connector The Timer Channel C port 15 port attached to the Timer C expansion connector Refer to Table 2 20 for the signals attached to the connector Table 2 20 Timer C Connector Description J8 Pin Signal 1 2 3 3 3V 4 DSP56F805EVM User Manual Rev 5 2 30 Freescale Semiconductor 2 22 8 Timer Channel D Expansion Connector Peripheral Connectors The Timer Channel D port is an MPIO port attached to the Timer D expansion connector See Table 2 21 for the signals attached to the connector Table 2 21 Timer D Connector Description J5 Pin Signal
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7. T 71630 0 9997 968 219 XV4 0626 568 019 E arg yrs 8698 66282 X1 unsny 00 90 94 00 9019 00 bed ISM uouue en 1059 T lt T T lt h sea T lt 16 494125406 SSAIM vg sum onn PODHYL OOHVL SNOLOSNNOO SNOLOSNNOO 24551477 sna sna 1 gt S anyo anyo 90 56F805EVM Schematics Rev 5 R JAN Ag Ag A0S i A0S T A0S D A0S E6ENWT E6 EWT 6 6 6 IVIMHS 5 NVO i Jn s t RI 1 d Ab a ML x 1 1 anyo anyo anyo anyo 1 559 zeo 2 059 127 3229 gt i i sl ii 892 020 60 810 910 Ag e VA E 1 L HILIttWNGIV HOLOHNNOO 6 INN Hr 2454 Freescale Semiconductor DSP56F805EVM User Manual Rev 5 Appendix A 20 Freescale Semiconductor 56F805EVM Bill Material Qty Description Ref Designators Vendor Part s Integra
8. 2 33 A D Connector DOSCGHDBON La A eas d 2 33 SCIO Connector ETAN ARO EE LEDET ides 2 34 SCII Connector Desen uuu dada AREE ESAE 2 34 List Tables Rev 5 Freescale Semiconductor V 2 27 SPI Connector Descriptions a Aire hg 2 35 2 28 CAN Connector Des riphio 2 35 2 29 Port A Connector Description 2 36 2 30 Port B Connector Description 2 37 2 31 Secondary UNI 3 Unattached Signal Connector Description 2 38 DSP56F805EVM User Manual Rev 5 vi Freescale Semiconductor Preface This reference manual describes in detail the hardware on the 56F805 Evaluation Module Audience This document is intended for application developers who are creating software for devices using the Freescale 56F805 part Organization This manual is organized into two chapters and two appendixes Chapter 1 Introduction provides an overview of the EVM and its features Chapter 2 Technical Summary describes in detail the 56 805 hardware Appendix 56F805EVM Schematics contains the schematics of the 56 805 Appendix 56 805 Bill Material provides list the materials used the 56F805EVM board Suggested Reading Documentation on the 56 805 and the 56 805 kit may be found at this URL htt
9. 2 14 Secondary 2552235 heh ohh yaq 2 15 General Purpose Switches and Run Stop 2 17 Serial 10 bit 4 channel D A Converter 2 18 Motor Control PWM Signals and 2 19 Table of Contents Rev 5 Freescale Semiconductor i 2 16 Motor Protection 2524555 EX FERRE HER 2 19 2 16 1 Primary UNI 3 Motor Protection Logic CANAL EEN EE A 2 20 2102 Secondary UNI 3 Motor Protection Logic 2 21 2 17 Back EMF and Motor Phase Current Sensing 2 23 2 18 Quadrature Encoder Interface 2 24 FALE Co Eoo n EE EEN EE ITEM 2 24 A20 CAN DIESEL dep ddr dene dod aepo HAC e EI AERA e od EE 2 25 221 Soa Feature JOD 2 26 226 d dde ax dd 2 27 2284 Pon B Expansion La iin des 64540456 ap RACER eR E 2 27 2222 PortD Expansion EEN 2 28 2223 FORE Expansion vasi cada quce Au ACER ER 2 28 2 22 4 External Memory Control Signal Expansion Connector 2 29 2 22 5 Primary Encoder Timer Channel A Expansion 2 29 2 22 6 Secondary Encoder Timer Channel B Expansion Connector 2 30 2444 Timer Channel C Expansion Connector aad
10. 318VN3 5 DSP56F805EVM User Manual Rev 5 Freescale Semiconductor Appendix A 4 sio 9 uuo2 195 pue 262 564 eJnDi4 514 SLO JO 19945 1001 juawdojaneg 4946 0002 vo Aepsony 91 1 d Jequun NSQ WA3s0849sdsQ 928 SHOLIO3NNOO 19 ANY 222 58 LEO ON 996 668 219 4 0626 568 216 8698 98 8 utisny ISOM UOUURD 1099 UOISIAIG 4 4 1254 6 5592941 AL ould NISH AL GH AL GU Suvalieewav Su NIEL AL SH ovid LG asd SHOLOHNNOO cec sa 0105 anyo 159 770 d WIGVNH CEC SH WIHVSIG 2620 54 NMOGQLRHS 2 c SH 56F805EVM Schematics Rev 5 Appendix A 5 Freescale Semiconductor J9349AUO2 eles s V 81 JO 19945 sont 5 0002 0 Aepsany eieq EL V 847 1 3508495450 juaunaon azis H31H3ANOO 1VIH3S 9ng3q 71530 955 568 215 4 0626 568 216 8698 9818 XL ullsny ISOM UOUURD 1099 UOISIAIG 19911259 5 85 41 301 1018 VAG et tv d c ov d YOLOANNOO V G 1 5
11. enu 71530 0 959 568 019 41 0626 56 219 9668 6 8 unsny JS8M uouue 1099 UOISIAIg 1941 254 lt Sso oJIM OV HSNHS Linva 1 01 ZA S A 19 SNAS 29 694 NOILOzLLHG LINVA ONY 89H 198 ge nak lt 001 WHdWOD LISIHNI EE 9 sS 1 ONISSOYD ZAL 5 0887 03 INn 101 21 WMd Odd tor MOLOSNNOO INN ANVWINd am aswa O 4W3 yg Ov 6 X aswHa uet V SSVHd 86 CS 9 Xx oux 96 e gt gt dx 2 841 0937 ee 1e S800 0837 Odd LIgIHNI 539 WMd Odd ROS 1825 62 lt 584 mn f ZSNSS HOLON se S OHd sms 1 SSVHd ut e 8 ed Ki SI 8Hd S VHd 5 5 INHSNS V INN wd d yw ONY HSN3S SOVITIOA 508 NOLOW Ste 5 INIT waste vae e s 991
12. connector the 56F805EVM allows the connection of an external Host Target Interface for downloading programs and working with the 56F805 s registers This connector is used to communicate with an external Host Target Interface which passes information and data back and forth with a host processor running a debugger program Table 2 3 shows the pin out for this connector Table 2 3 JTAG Connector Description J29 Pin Signal Pin Signal 1 TDI 2 GND 3 TDO 4 GND 5 TCK 6 GND 7 NC 8 KEY 9 RESET 10 TMS 11 3 3V 12 NC 13 NC 14 TRST When this connector is used with an external Host Target Interface the parallel JTAG interface should be disabled by placing a jumper in jumper block JG5 Reference Table 2 4 for this jumpers selection options Table 2 4 Parallel JTAG Interface Disable Jumper Selection JG5 Comment No jumpers On board Parallel JTAG Interface Enabled 1 2 Disable on board Parallel JTAG Interface DSP56F805EVM User Manual Rev 5 2 8 Freescale Semiconductor Debug Support 2 7 2 Parallel JTAG Interface Connector The Parallel JTAG Interface Connector P1 allows the 56 805 to communicate with a Parallel Printer Port on a Windows PC refer to Figure 2 5 By using this connector the user can download programs and work with the 56F805 s registers Table 2 5 shows the pin out for this connector When using the parallel JTAG interface the jumper a
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14. 1 1 x z Jequun 847 1 3508495450 9715 5 ANY S3HOLIMS 3SOdHfid IVH3N39 Hash 71530 955 568 215 4 0626 568 216 GOOD SHHOLIMS IVeHHNHO 1545 MS o e dOLS NA W DSP56F805EVM User Manual Rev 5 Freescale Semiconductor Appendix A 10 10 2 1 6ojeuy JIN3 42eg 1usSJin 3 eseud JOJOW 0L V inBij gt JO 1994 1001 juawdojaneg 19 61590 0002 vo Aepsony 91 d EL Joaquin NSQ WA3508395dSQ 9215 YOLOATAS LNdNI AWS MOVE LNAYYND ASVHd HOLON enu 959 568 215 XV4 0626 568 016 8698 96 8 X1 ISOM 1099 UOISIAIG 199 11259 5 55 Hanens 019r 6 8 L 6 lt SI 8 MN Ma 4 lt ss 9241518 AN 9 lt SI lt lt S Soe t lt 8 x8 CDS avror AO NO SI OTOL AO NOLLVOO I ALON 56F805EVM Schematics Rev 5 Appendix A 11 Freescale Semiconductor 5 pue Lp V
15. 2 22 3 Port E Expansion Connector Port E is an MPIO port with signal lines attached to various headers The pins of the port are shared with SCI port SCI0 two Address bus lines 6 and 7 and the SPI port Table 2 16 shows the shared pins and functions Table 2 16 Port E Connector Description J7 Pin Signal Alternate Funct Pin Signal Alternate Funct 1 PE0 TXD0 2 PE1 RXD0 3 PE2 TXD1 4 PE3 RXD1 5 4 SCLK 6 5 MOSI 7 MISO 8 PE7 ss 9 GND GND 10 3 3V 3 3V DSP56F805EVM User Manual Rev 5 2 28 Freescale Semiconductor Peripheral Connectors 2 22 4 External Memory Control Signal Expansion Connector The External Memory Control Signal connector contains the controller s external memory control signal lines Refer to Table 2 17 for the names of these signals Table 2 17 External Memory Control Signal Connector Description J27 Pin Signal Pin Signal 1 RD 2 IRQA 3 WR 4 5 5 6 7 DS 8 RSTO 9 CLKO 10 DE 11 GND 12 3 3V 2 22 5 Primary Encoder Timer Channel A Expansion Connector The Primary Encoder Timer Channel A port is an MPIO port attached to the Timer A expansion connector The port can act as a Quadrature Decoder interface port or as a general purpose Timer port See to Table 2 18 for the signals attached to the connector Table 2 18 Timer A Connector Description
16. 56 805 Evaluation Module User Manual 56F800 16 bit Digital Signal Controllers DSP56F805EVMUM Rev 5 07 2005 freescale com ky freescale semiconductor VW 1 1 1 2 L3 2 1 2 2 2 2 2 4 2 5 2 6 4 2 51 2 1 2 2 8 29 2 10 2 11 2 14 2 13 2 14 2 13 5 Preface AUN E TQUE vii dci reU E Are eene mdi 2225454 vii os cd viii Definitions Acronyms and Abbreviations PCT PH X Chapter 1 Introduction EE ebe E RACE OE 1 2 SDPRUSEVM Configuration Jumpers 1 3 SOFSOSE get d EE EE er gd 1 4 Chapter 2 Technical Summary 2 3 Program and Data ENER Ae 2 4 RS 232 Serial Communications 2 5 A 2 6 EE 2 6 Io 2 7 2 7 oo MET gt 2 8 Parallel JTAG Interface 2 9 Eng Bae UR r e dee S 2 11 BON ER Edu oe dot Ecran EE 2 12 FM EENT E 2 13 Pimary
17. 1 TDO 2 TD1 3 TD2 4 TD3 5 3 3V 6 GND Technical Summary Rev 5 Freescale Semiconductor 2 31 2 22 9 Address Bus Expansion Connector The 16 bit Address bus connector contains the controller s external memory address signal lines The upper 8 bits A8 A15 can also be used as Port A GPIO lines Refer to Table 2 22 for the Address bus connector information Table 2 22 External Memory Address Bus Connector Description J1 Pin Signal Pin Signal 1 0 2 1 3 2 4 5 4 6 5 7 6 8 9 8 10 9 11 10 12 11 13 12 14 A13 15 A14 16 A15 17 GND 18 3 3V DSP56F805EVM User Manual Rev 5 2 32 Freescale Semiconductor Peripheral Connectors 2 22 10 Data Bus Expansion Connector The 16 bit Data bus connector contains the controller s external memory data signal lines Refer to Table 2 23 for the Data bus connector information Table 2 23 External Memory Address Bus Connector Description J2 Pin Signal Pin Signal 1 DO 2 D1 3 D2 4 D3 5 04 6 05 7 06 8 07 9 08 10 09 11 010 12 011 13 012 14 013 15 014 16 015 17 GND 18 3 3V 2 22 11 A D Port Expansion Connector The 8 channel Analog to Digital conversion port is attached to this connector See Table 2 24 for connection information Table 2 24 A D Connector Description J9 Pin Signal P
18. 19945 290615901 0002 vo unt Kepsenj 9180 8 D 194 30 3908396450 will azs 53114405 H3MOd YLEJO ON 959 568 019 4 0626 56 219 SOLV IOQDSMH N VAEE ENSE PIRA 141 Edl 541 LNIOd LSAL LNIOd LSAL LNIOd LSHL LNIOd LSHL AE tt OO IVNV e AOL Ans L 1g69zeeOW e ayaa 3113833 Ae y 100 ano ei LNOA NIA z anro Eu AS 01031 GOOD T E Ord AOL Amt 0 5 LQ69266OW 3118833 anro ME anger y 100 ano PE uo Agora n ma NIA Le EINN A0 S NHMOd ta 3 5 a Y DSP56F805EVM User Manual Rev 5 Freescale Semiconductor Appendix A 18 Sojec oJedg pue sio i5edeo ssed g 79 ainbi4 Appendix A 19 3 a 5 u Y 81 10 gt 19945 sjooy ueuBiseq 0002 vo Aepseny 19180 1 NSa waasog49sasa will ep S31V9 3HVdS QNY SHOLIOVdVO
19. 2 19995 1euDIseq 0002 01 Aepuoy eieq E L Jequun 547 4 3508 95450 9215 9 X00710 JAQON 13S3H eni 1 30 dW 9559 568 216 4 0626 568 216 8698 06 8 XL utsny ISAM ALG uouueo 1089 UOISIAIG 29912259 5 ssoj 8JIM 10081 3 lt lt eum LOOS LNI Zor ON LOOd LXH 4 1008 8vu Ag et 1 lt NOLIN S d Lassa CS dno 975 lt lt 28 NOLLQOdHS d 8041 974 Ag EE stor Stu 0 SSVdAH OSO L aor NOLLQdHHS d 6 2 10078 LA gor Ag et 56F805EVM Schematics Rev 5 Appendix A 3 Freescale Semiconductor IN VS 9 4 a 81 JO 19945 siooj 5 EL 0002 0 918 NSQ WA3S08398dSQ juawnooy Jequiny 9715 AYOWAW WVHS S VLVG 9 NvHOOHd enit vi 3O QW 955 568 215 4 0626 568 216 8698 9818 ullsny ISOM UOUURD 1099 UOISIAIG 19911259 5 5591941 aTavsid WV3SS Ses in N U Z M01 6ru Q c gt lt lt lt lt lt lt Is Ager 3TQ 9IXMTO9 H ISVNH WWAS NOILdO 8
20. The Motor Phase Current signals are derived from current sense resistors Both of these signal groups are then routed to a group of header pins that allow the end user to select which signal group the device s A D will monitor Refer to Figure 2 15 for the design of a single channel The Secondary UNI 3 s Back EMF signals are unbuffered and then routed to a header that contains all of the unconnected Secondary UNI 3 signals reference Table 2 9 BACK A 5 PHASE SENSE gt gt Figure 2 15 Primary Back EMF or Motor Phase Current Sense Signals Technical Summary Rev 5 Freescale Semiconductor 2 23 2 18 Quadrature Encoder Hall Effect Interface 56F805EVM board contains Primary and Secondary Quadrature Encoder Hall Effect interface connected to the controller s first and second Quad Encoder input ports The circuit is designed to accept 3 0V to 5 0V encoder Hall Effect sensor inputs Input noise filtering is supplied on the input path for the Quadrature Encoder Hall Effect interface along with additional noise rejection circuitry inside the device Figure 2 16 contains the primary encoder interface The secondary encoder interface is a duplicate of the primary encoder interface 2 19 Zero Crossing Detection An attached UNI 3 motor drive board contains logic that can send out pulses when the phase voltage of an attached 3 phase motor drops to zero The motor drive board circuits ge
21. 2 34 Serial Communications Interface SCI Preface ix Serial Peripheral Interface SPI Preface ix SPI Preface ix Serial Peripheral Interface 2 35 SPI compatible peripheral 2 1 SRAM Preface ix external data 2 1 external program 2 1 Static Random Access Memory SRAM Preface ix T Timer compatible peripheral 2 2 U UART Preface ix UNI 3 Back EMF 2 23 connector interface 2 14 DC Bus Over Voltage signal 2 20 Motor Drive interface 2 15 Motor interface Primary 2 2 Secondary 2 3 Over Voltage signal 2 21 Unattached Signal Connector 2 38 Universal Asynchronous Receiver Transmitter UART Preface ix Index Rev 5 Freescale Semiconductor Index 3 How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor
22. 8 JTAG port interface 2 1 Jumper Group 1 3 JG1 1 3 JG10 1 4 JG11 1 4 JG12 1 4 JG13 1 4 1014 1 4 1015 1 4 JG16 1 4 JG17 1 4 JG18 1 4 JG2 1 3 JG3 1 3 764 1 3 JG5 1 3 JG6 1 3 JG7 1 3 768 1 3 JG9 1 3 L Logic motor bus over current 2 1 motor bus over voltage 2 1 motor zero crossing 2 1 Low Profile Quad Flat Pack LQFP Preface ix LQFP Preface ix motor bus over current 2 1 over voltage 2 1 Motor Phase Current 2 23 Motor Protection Logic 2 19 MPIO Preface ix 2 28 2 30 port 2 30 2 31 MPIO compatible peripheral 2 1 2 2 Multi Purpose Input and Output MPIO Preface ix power regulation 2 2 Preface ix 1 1 Emulation Preface ix Parallel Host Target Interface 2 1 PCB Preface ix Phase Locked Loop PLL Preface ix PLL Preface ix Printed Circuit Board PCB Preface ix Program memory 2 4 Pulse Width Modulation PWM Preface ix PWM Preface ix PWM compatible peripheral 2 2 Q Quad Encoder 2 24 Quadrature Decoder interface port 2 29 DSP56F805EVM User Manual Rev 5 Index 2 Freescale Semiconductor R 2 RAM Preface ix Zero Crossing Random Access Memory RAM Preface ix Zero Crossing Detection 2 24 Read Only Memory ROM Preface ix real time debugging 2 7 ROM Preface ix RS 232 interface 2 5 level converter 2 5 schematic diagram 2 5 RS 232 interface 2 1 S SCI Preface ix Serial Communications Port
23. Aer THNNVHO BLU 184 98d v v moa Sad 9 5 vad E co n et AE Et 0 59 DH 28d z 101 2 0835 isi SS H OSIN 18d 2 08d 001 EECH ISON XIOS 1QXH H LOXL Kal ef T 00X8 2 00 z rs T NWO E 0155 T 1125 E lt mos z z z gt osin lt XL lt Ison Ser or LP or un VAEE O 0 6 NV 8 1 9 Ed SNY INY 272 2 ONY er T D SVWMd VWMd oL ZYNMd 6 6 8 8 ovWMd 1 ealmnvs 1 uch 9 zannya 9 5 Lane 5 ema 0811 3 zasi 2 51 2 1851 2 l 0851 ovSi E sna nn sna ssssaqv TONLNOD 55 IC ep Se Ag et no amp zig y ny 1N3A3 ona3a 0 6 ono ora EN 8 1 sg 06 0 6 0 13538 9 5 59 8 1 38 8 1 t uW 50 9 5 E 8 9 5 voul 2 qu t v i za tv i zV Ter Id od IV Qv gt lt stvola lt zal EL uL rei 56F805EVM Schematics Rev 5 Appendix 15 Freescale S
24. Analog Evaluation Module General Purpose Input and Output Port Integrated Circuit Joint Test Action Group a bus protocol interface used for test and debug Low profile Quad Flat Pack Multi Purpose Input and Output Port shares package pins with other peripherals on the chip and can function as a GPIO On Chip Emulation a debug bus and port created by Freescale to enable designers to create a low cost hardware interface for a professional quality debug environment Printed Circuit Board Phase Locked Loop Pulse Width Modulation Random Access Memory Read Only Memory Serial Communications Interface Serial Peripheral Interface Port Static Random Access Memory Universal Asynchronous Receiver Transmitter Preface Rev 5 Freescale Semiconductor ix References The following sources were referenced to produce this manual 1 DSP56800 Family Manual Freescale Semiconductor DSP56800FM 2 DSP56F801 803 805 807 User s Manual Freescale Semiconductor DSP56F801 7UM 3 56 805 Technical Data Freescale Semiconductor DSP56F805 4 CiA Draft Recommendation DR 303 1 Cabling and Connector Pin Assignment Version 1 0 CAN in Automation 5 CAN Specification 2 0B BOSCH or CAN in Automation DSP56F805EVM User Manual Rev 5 x Freescale Semiconductor Chapter 1 Introduction 56F805EVM is used to demonstrate the abilities of the 56F805 and to provide a hardware tool allowing the development of applications th
25. R62 R63 SMEC RC73L2A2700HMJT R64 R65 R66 16 24 0 R76 R77 R79 R80 R82 R83 SMEC RC73L2A24OHMJT R85 R86 R88 R89 R91 R92 R94 R95 R97 R98 1 120 1 4W R118 YAGEO CFR 120QBK Potentioneters 7 10K R5 R14 R15 R71 R107 BC MEPCOPAL ST4B103CT R116 R117 Inductors 4 1 0mH L1 L2 L3 L4 Fair Rite 2743015112 LEDs 1 Red LED LED1 Hewlett Packard HSMS C650 4 Yellow LED LED2 LED4 LED6 LED8 Hewlett Packard HSMY C650 5 Green LED LED3 LED5 LED7 LEDS9 Hewlett Packard HSMG C650 LED10 Diode 3 S2B FM401 D1 D2 D3 Vishay DL4001DICT DSP56F805EVM User Manual Rev 5 Appendix B 2 Freescale Semiconductor Qty Description Ref Designators Vendor Part s Capacitors 5 2 2uF 50V DC C1 C2 C23 C54 C60 NICHICON UWX1H2R2MCR2GB 49 0 1uF C3 C4 C5 C6 C7 C8 C9 SMEC MCCE104K2NR T1 C10 C12 C14 C16 C17 C18 C19 C20 C21 C22 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C35 C38 C39 C40 C41 C44 C46 C47 C48 C49 C50 C51 C52 C53 C59 C65 C67 C68 C69 C70 C71 C72 1 470uF 16V DC C11 PANASONIC ECE V1CA471P 2 47uF 10V DC C13 C15 PANASONIC ECE V1AA470P 8 470pF C55 C56 C57 C58 C61 C62 SMEC MCCE471J2NO T1 C63 C64 Jumpers 9 3 x 1 Bergstick JG1 JG2 JG6 JG11 JG15 SAMTEC TSW 103 08 S S JG16 J16 J17 J25 4 4 x 2 Bergstick 903 JG4 J4 J20 SAMTEC TSW 104 08 S D 6 1 x 2 Bergstick JG5 JG7 JG8
26. bit 4 channel D A converter connected to the 56F805 s SPI port The output pins are uncommitted and are connected to a 4X2 header J20 to allow easy user connections Refer to Figure 2 10 for the D A connections and to Table 2 10 for the header s pin out The D A s output full scale range value can be set to a value from 0 0V to 2 4V by a trimpot This trimpot is preset to 2 05V which provides approximately 2mV per step 56F805 Figure 2 10 Serial 10 bit 4 Channel D A Converter 3 3V 3 Table 2 10 Header Description J20 Pin Signal Pin Signal 1 D A Channel 0 2 AGND 3 D A Channel 1 4 AGND 5 D A Channel 2 6 AGND 7 D A Channel 3 8 AGND DSP56F805EVM User Manual Rev 5 2 18 Freescale Semiconductor Motor Protection Logic 2 15 Motor Control PWM Signals and LEDs The 56 805 has two independent groups of dedicated PWM units Each unit contains six PWM three Phase Current sense and four Fault input lines PWM group A s PWM lines are connected to the UNI 3 interface connector and to a set of six PWM LEDS via inverting buffers The buffers are used to isolate and drive the controller s PWM outputs to the PWM LEDs Most of the secondary PWM signals are routed to the Secondary UNI 3 connector PWM LEDs indicate the status of PWM group A signals as shown in Figure 2 11 PWM Group A and B signals are routed out to headers and ar
27. for external interrupt generation as shown in Figure 2 6 S1 allows the user to generate a hardware interrupt for signal line IRQA S2 allows the user to generate a hardware interrupt for signal line IRQB These two switches allow the user to generate interrupts for his user specific programs 56F805 IRQA Figure 2 6 Schematic Diagram of the User Interrupt Interface Technical Summary Rev 5 Freescale Semiconductor 2 11 2 9 Reset Logic is provided on the 56F805 to generate a clean power on RESET signal Additional reset logic is provided to support the RESET signals from the JTAG connector the Parallel JTAG Interface and the user RESET push button see Figure 2 7 RESET PUSHBUTTON 575 MANUAL Figure 2 7 Schematic Diagram of the RESET Interface DSP56F805EVM User Manual Rev 5 2 12 Freescale Semiconductor Power Supply 2 10 Power Supply The main power input 12V DC at 4 0A to the 56 805 is through 2 1mm coax power jack 4 0Amp power supply is provided with the 56F805EVM however less than 500mA is required by the EVM The remaining current is available for user motor control applications when connected to an optional motor power stage board The 56F805EVM provides 3 3 DC voltage regulation for the device memory D A CAN parallel JTAG interface and supporting logic refer to Figure 2 8 Power applied to the 56F805EVM is indicat
28. push button GPIO PD4 S5 General purpose toggle switch for RUN STOP control PD5 S6 2 1 56F805 The 56F805EVM uses a Freescale DSP56F805FV80 part designated as U1 on the board and in the schematics This part will operate at a maximum speed of 80MHz A full description of the 56F805 including functionality and user information is provided in the following documents DSP56800 Family Manual DSP56800FM Provides a detailed description of the core processor including internal status and control registers and a detailed description of the family instruction set DSP56F801 803 805 807 User s Manual DSP56F801 7UM Provides an overview description of the controller and detailed information about the on chip components including the memory and I O maps peripheral functionality and control status register descriptions for each subsystem 56F805 Technical Data DSP56F805 Provides features list and specifications including signal descriptions DC power requirements AC timing requirements and available packaging Refer to these documents for detailed information about chip functionality and operation They can be found on the following URL http www freescale com Technical Summary Rev 5 Freescale Semiconductor 2 3 2 2 Program Data Memory 56F805EVM uses one bank of 128Kx16 bit Fast Static GSI 65572116 labeled 015 for external memory expansion see the FSRAM schematic diagram in Figu
29. u 444 si uuo wyo pz vey T lt s Cen z8u A0 22197 _ 189 8 5 uh 39027 075 uuo 999 uuo pz i 9 083svHd a s eer aziar AL 814 A0S Jnz z T 790 39027 075 uuo vc 59 uuo vc anyo 659 0 35 4 lt lt T 9 u valor 0 6 LOHddd 0 S TIVH rac ouaz NOLLWWYOANT 6 EET lt lt ouaz LOANNOOD d lt lt vx ouaz ONISSOHO 56F805EVM Schematics Rev 5 13 Freescale Semiconductor 10509126 1299J3 H 10 3 0 49 04 7 4 a 9 gt JO 1994 1001 Juawdojanaq 0002 vo 1 91 24 We Ee Aen NSQ WA35083954SQ 925 9 NId S NId 40194138S 193443 T1VH HO 0 8550 0 37 5 71530 955 568 219 vi 0626 568 216 V HSVHd NId 8698 96 8 XL ullsnv _ Nid ISOM UOUUeD 1059 AO S NId UOISIAIg 494112545 585 SR mor 1 gat SHOLOHNNOO i3WoH 169 390 7 SR ER S m SES AWVINOOSHS 3902
30. user to connect his own Timer D MPIO compatible peripheral J5 Connector to allow the user to attach his own Port B GPIO compatible peripheral J28 Connector to allow the user to attach his own Port D GPIO compatible peripheral J4 Connector to allow the user to attach his own Port E GPIO compatible peripheral J7 56F805 s external memory expansion connectors J1 J2 and J27 On board power regulation from an external 12V DC supplied power input P2 Light Emitting Diode LED power indicator LED10 Three on board real time user debugging LEDs LEDI 3 Six on board Primary PWM monitoring LEDs LED4 9 Primary UNI 3 Motor interface J30 Encoder Hall Effect interface Over Voltage sensing U8 Over Current sensing U5 Phase Current sensing U8 and U21 sensing Temperature sensing Zero Crossing detection Pulse Width Modulation DSP56F805EVM User Manual Rev 5 2 2 Freescale Semiconductor 56 805 Secondary UNI 3 Motor interface J31 Encoder Hall Effect interface Over Voltage sensing U6 Over Current sensing U22 Phase Current sensing U6 and U7 sensing Temperature sensing Zero Crossing detection Pulse Width Modulation Manual RESET push button S1 Manual interrupt push button for IRQA S2 Manual interrupt push button for IRQB S3 General purpose push button on GPIO PD3 S4 General purpose
31. 0 wer 3 oer gr ane oy pve eve T 1 L ISHU 6 z ER G t Sr 13539 d BT Gel 13838 d 158 13588 lt ars seu eog Prepa Mo wyo 16 ons Gg IO3NNOO 1HOd eog Xr egal uuo 18 o 001 1H0d o 22 7 DON 1804 STT IS DIS 5 E TS 2 anro po MES eS L adioa e Cl szia En 959 CUT 019 74 1581 1HOd 9 E ge 8r sedi T 5 pa pd 5 i HDC 1 ET 1HOd Y TT 2492 iwz HiT os SWI 1804 T 5 EAL E 3 18535 1804 z 4 INIO 1804 OWL 56F805EVM Schematics Rev 5 Appendix 17 Freescale Semiconductor saijddns L V 9 3 8658 66 8 JS8M uouue 1099 UOISIAIg 1941 254 lt ss 1I A gi JO
32. 1 503 ZERO X A 2 SU3 ZERO X B 3 503 ZERO X C 4 SU3 BK EMF A 5 503 BK B 6 SU3 BK EMF C 7 SU3 PHA IS 8 503 PHB IS 9 SU3 PHC IS 10 SU3 S DCB 11 GND 12 5 0V 13 NC 14 NC 2 24 Test Points The 56F805EVM board has a total of eight test points Four test points are located near the breadboard area 3 3VA AGND 3 3V and GND Four test points are located near the Primary UNI 3 connector J30 15VA GND 15 GND DSP56F805EVM User Manual Rev 5 2 38 Freescale Semiconductor 56F805EVM Schematics 56F805EVM Schematics Rev 5 Freescale Semiconductor Appendix A 1 105590044 108496 nBDid 5 E Y gt 10 199US 001 iueudojeneg ueuBiseq 0002 o Aepseny 9120 8 ES E Jequinv 0813908398950 8 921 d N A3S0849SdSG0 juawnoog IS APEX Green ssA Leet gaan ISSA SIL 10589901 SSSA d 808395950 te PSSA E E aan ESSA 998 668 219 0606 568 215 T P aan cask ty 8 Or 8698 96 8 unsny NOS Anz z 08 31272 L VSSA EZ 57 MI 1050 M veer i ia nga zo 38 UOISIAIg 1941 254 lt ss 1I A T T azr dd Xd NVOSN Les lt Xu Neien 204 NVOSN 5 NvosW Se 104 0 134183 gr ss m 94d OSIN T OSIN 51 g
33. 2 16 PWM Expansion Connector PWM port is attached to this connector Refer to Table 2 29 for the connection information Table 2 29 PWM Port A Connector Description J21 Pin Signal 1 ISAO 2 ISA1 3 ISA2 4 FAULTAO 5 FAULTA1 6 FAULTA2 7 FAULTA3 8 PWMAO 9 PWMA1 10 PWMA2 11 12 PWMA4 13 PWMA5 14 GND DSP56F805EVM User Manual Rev 5 2 36 Freescale Semiconductor 2 22 17 PWM Expansion PWM port B is attached to this connector Refer to Table 2 30 for the connection information Table 2 30 PWM Port B Connector Description J22 Pin Signal 1 ISBO 2 ISB1 3 ISB2 4 FAULTBO 5 FAULTB1 6 FAULTB2 7 FAULTB3 8 PWMBO 9 PWMB1 10 PWMB2 11 12 13 5 14 GND Technical Summary Rev 5 Peripheral Connectors Freescale Semiconductor 2 37 2 23 Secondary UNI 3 Unattached Signal The Secondary UNI 3 signal group has several lines that do not connect to the controller These unattached lines are connected to a header where they are available for use by the end user Refer to Table 2 31 for the location of these signals Table 2 31 Secondary UNI 3 Unattached Signal Connector Description J14 Pin Signal Pin Signal
34. 7 290 uuo vc 26 vc 192 vc I 884 Load TIVH WJ3dOONH 55 Odd 2 1 lt lt 0 x ouaz ens DLOHNNOO lt lt 8 X ouaz ens 5 5 lt lt v x ouaz ens E INL 5 DSP56F805EVM User Manual Rev 5 Freescale Semiconductor Appendix A 14 10 D9UUO0D uoisuedx3 E 81 JO p 1994 spo aU IS q 0002 po Aepseny 19190 et 8 7 l6qunN en THNNVHO S THNNVHO JAWIL H NSQ WA3S0849SdS0 juawnooq 5 zT 9 P d poneer oer en sad SuO193NNOO NOISNVdX3 1808 450 a add Tor SON 194 009 2 nn 2 999 968 219 0606 568 215 001 EN 9r 8698 98284 XL urisny eau uouue9 1059 UOISIAIg 1941 264 lt SSAIM V THNNVHO WHWIL Iaoa 9 E
35. A SPI for real time user data display U18 8 00MHz crystal oscillator for frequency generation Y1 Optional external oscillator frequency input connector JG6 and JG18 Joint Test Action Group JTAG port interface connector for an external debug Host Target Interface J29 On board Parallel JTAG Host Target Interface with a connector for a PC printer port cable P1 RS 232 interface for easy connection to a host processor U16 and P3 CAN interface for high speed 1 0Mbps communications U20 and J26 CAN bypass and bus termination J32 and JG17 Connector to allow the user to connect his own SPIO MPIO compatible peripheral J16 Technical Summary Rev 5 Freescale Semiconductor 2 1 Connector to allow user to connect his own SCII MPIO compatible peripheral 717 Connector to allow the user to connect his own SPI MPIO compatible peripheral J19 Connector to allow the user to connect his own PWMA or MPIO compatible peripheral 721 Connector to allow user to connect his own PWMB MPIO compatible peripheral J22 Connector to allow the user to connect his own CAN physical layer peripheral J25 Connector to allow the user to connect his own Timer A MPIO compatible peripheral 13 Connector to allow the user to connect his own Timer MPIO compatible peripheral J6 Connector to allow the user to connect his own Timer C MPIO compatible peripheral J8 Connector to allow the
36. A0 S O e e t d 6 red quvog JHL LV E 1 91 END Er os D E DH t LWWMd OVINMd IV oer 3 5 a Y DSP56F805EVM User Manual Rev 5 Freescale Semiconductor Appendix A 8 juaJ1n 3 19AQ pue INN g v ainbi4 3 8 10 g 1994 5001 uewdojaneg 219061891 0002 po Kepsenj 19180 8 y J qun NSO WA3S0849SdSG0 SYL eng 3 3 1N3H8f0 H3AO 39V110A H3AO iW3 MOV8 IND AHVONOO3S 1630 0W 9597 568 219 XV3 0626 968 21 8669 66 8 USMY uouue 1099 UOISIAIG 194112540 ssajoJIM STWNDIS INN 5 GQHHOV LLVNO gh 5 5 LIONVA T VESENT 81770 Su 9 WI u ed 824 S A ENS LINYA 5 TaN 18 101 LISIHNI WOO 9 E 72184 oun WOD WHdW D ONISSOND ONSZ CULL DH ser 0837 eme 0415 2 53 f TOT WOO VINSS ANVINOOSS
37. Ead bd I E ard 2 5 Liner MOSS 2 6 JTAG Connector Liege EE EE eee ee EC 2 8 Parallel JTAG Interface Disable Jumper Selection 2 8 Parallel JTAG Interface Connector Description 2 9 On Board Host Target Interface Power Source Jumper Selection 2 10 Primary UNI 3 Connector Description 2 14 Secondary UNI 3 Connector Description 2 15 Unused Secondary UNI 3 Connector Signal Description 2 16 KA Header a a exceeds uk dd ERA hb x dra ERA CE ac db 2 18 FAULTAT Source Selection i 2 20 FAULTBI Source Selechon Jumper bk EE 2 22 CAN Header DOSGHPUDIL 2 26 Port B Connector DOSCHDUDR AE acia d ed RO 2 27 Port D Connector Description 2 28 Port E Connector Description 2 28 External Memory Control Signal Connector Description 2 29 Time Pes oo so 60 eo 2 29 Timer Connector Desc TEE 2 30 Timer C Conmector DoscrmiDolt e o3 aq E VICE qaa 2 30 Timer aas op cR C ER EROS ewe d 2 31 External Memory Address Bus Connector 2 32 External Memory Address Bus Connector
38. Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by
39. JG9 JG17 SAMTEC TSW 102 08 S S JG18 1 1 x 1 Bergstick JG10 SAMTEC TSW 101 08 S S 3 3 x 3 Bergstick JG12 JG13 JG14 SAMTEC TSW 103 07 S T 2 9 x 2 Bergstick J1 J2 SAMTEC TSW 109 08 S D 3 6 x 1 Bergstick J3 J5 J6 SAMTEC TSW 106 08 S S 5 5 x 2 Bergstick J7 J9 J26 J28 J32 SAMTEC TSW 105 08 S D 2 4 x 1 Bergstick J8 J19 SAMTEC TSW 104 08 S S 2 7 x 2 Bergstick J29 J14 SAMTEC TSW 107 08 S D 2 14 x 1 Bergstick J21 J22 SAMTEC TSW 114 08 S S 2 6x1MTA J23 J24 AMP MTA 640456 6 1 6 x 2 Bergstick J27 SAMTEC TSW 106 08 S D 2 20 x 2 Shrouded J30 J31 3M 2540 6002UB 56F805EVM Bill of Material Rev 5 Freescale Semiconductor Appendix B 3 Qty Description Ref Designators Vendor Part s Test Points 8 1 x 1 Bergstick 1 TP2 TP5 TP6 Samtec TSW 101 08 S S TP7 TP8 Crystals 1 8 00 2 Crystal Y1 ECS 80 18 5P Connectors 1 DB25M Connector P1 617 C025P AJ121 1 2 1mm coax P2 Switch Craft RAPC 722 Power Connector 1 DE9F Connector P3 AMPHENOL 617 C009S AJ120 Switches 5 SPST Pushbutton S1 S2 S3 S4 S5 Panasonic EVQ QS205K 1 SPDT Toggle S6 C amp K GT11MSCKE Transistors 1 2N2222A Q1 ZETEX FMMT2222ACT Miscellaneous 27 Shunt SH1 SH27 Samtec SNT 100 BL T 6 Rubber Feet RF1 RF6 3M SJ5018BLKC DSP56F805EVM User Manual Rev 5 Appendix B 4 Freescale Semiconductor INDEX Numerics D 16 bit 3 3V hybrid contro
40. PIO signals The pinout of connector P3 is listed in Table 2 1 The RS 232 level converter transceiver can be disabled by removing the jumper at JG9 RS 232 56F805 Level Interface T1out 1 1 2 7 3 8 4 9 5 232 DB9 Figure 2 2 Schematic Diagram the RS 232 Interface Table 2 1 RS 232 Serial Connector Description P3 Pin Signal Pin Signal 1 Jumper to 6 amp 4 6 Jumper to 1 amp 4 2 TXD 7 Jumper to 8 3 RXD 8 Jumper to 7 4 Jumper to 1 amp 6 9 5 GND Technical Summary Rev 5 Freescale Semiconductor 2 5 2 4 Clock Source 56F805EVM uses 8 00MHz crystal Y 1 connected to its External Crystal Inputs EXTAL and XTAL The 56F805 uses its internal PLL to multiply the input frequency by 10 to achieve its 80MHz maximum operating frequency An external oscillator source can be connected to the controller by using the oscillator bypass connectors JG6 and JG18 see Figure 2 3 EXTERNAL 56F805 OSCILLATOR HEADERS 8 00MHz Figure 2 3 Schematic Diagram of the Clock Interface 2 5 Operating Mode The 56F805EVM provides a boot up MODE selection jumper JG7 This jumper is used to select the operating mode of the device as it exits RESET Refer to the DSP56F801 803 805 807 User s Manual for a complete de
41. SNL S3d ISOW gt ISON OWL 101 2 101 4g S nos OG amp oa 1981 5 22 161 1 Hg lt 10X4 woo eios 904 L0XL HUA NV gz NY 13d 00XH ogr lt ONY ONY 03d 00XL r5 DON asnas ai SNY SNY asnas 2 awg X8 I en E HSNZS 8 og X8 I tn Gabi eal 601 SNISSON SNES dWaL ENS 5 5 V YG I EN V or 241 55 042 01 SSNSS I en INV LNY ML IEEE 101 asnasa ONY 001 5 Assen t IND Azepuoo s 6811 3 68 1901 LOL Oda INSSH D t IND xepuooes 28110 4 ealinvs oL 1 8 091 LISIHNI 244 c IN xepuooes 8 m t INn 0811 4 oaLinvs wu mue 2851 Wx IE Wx 1851 ono 0851 t INn Azepuoo s 10081X3 10081x3 IND xepuooeg vaMd 13938 OIT 8 te LIN EN For INn Azepuooes BDH Les goul t INn Azepuoo s Kee Lea c INn gt aui LNWYND zeng 2 11 4 HM Lea V
42. Timer Channel B Timer Channel C Timer Channel D Port A Address Bus Data Bus A D Input Port Serial Communications Port 0 Serial Communications Port 1 Serial Peripheral Port PWM Port A PWM Port B 2 22 1 Port B Expansion Connector Port B is GPIO port which is connected to the Port B header The pins of the port PBO PB7 are dedicated to general purpose I O and Interrupt operations The GPIO port pins may be programmed as inputs outputs or level sensitive interrupt inputs Table 2 14 shows the port pin to headed connections Table 2 14 Port B Connector Description J28 Pin Signal Pin Signal 1 PBO 2 PB1 3 PB2 4 PB3 5 4 6 5 7 8 PB7 9 GND 10 3 3V Technical Summary Rev 5 Freescale Semiconductor 2 27 2 22 2 Port D Expansion Port D is an MPIO port with signal lines attached to various headers The six pins of the port PDO PDS are dedicated to general purpose operation The remaining two pins PD6 and are shared with the TXD1 and RXDI signal lines The GPIO port pins may be programmed as inputs outputs or level sensitive interrupt inputs Table 2 15 shows the exclusive Port D signals The shared Port D signals are contained in Table 2 22 Table 2 15 Port D Connector Description 44 Pin Signal Pin Signal 1 PD0 2 PD1 3 PD2 4 PD3 5 PD4 6 PD5 7 GND 8 3 3V
43. VM User Manual Rev 5 Freescale Semiconductor Secondary UNI 3 Interface Table 2 7 Primary UNI 3 Connector Description Continued J30 Pin Signal Pin Signal 35 Zero Cross B 36 Zero Cross C 37 Shield 38 Back EMF Phase A Sense 39 Back EMF Phase B Sense 40 Back EMF Phase C Sense 2 12 Secondary UNI 3 Interface A Secondary UNI 3 Motor Drive interface is available on the EVM board Motor control signals from a family of motor driver boards can be connected to the EVM board via the Secondary UNI 3 connector interface The Secondary UNI 3 connector interface contains a majority of the signals needed to drive and control the motor drive boards The unused signals are connected to a header J14 These signals are connected to differing groups of the controller s input and output ports A D TIMER and PWM B Refer to Table 2 8 for the pin out of the Secondary UNI 3 connector and to Table 2 9 for the pin out of the unused signal header Table 2 8 Secondary UNI 3 Connector Description J31 Pin Signal Pin Signal 1 PWM AT 2 Shield 3 PWM AB 4 Shield 5 PWM BT 6 Shield 7 PWM BB 8 Shield 9 PWM CT 10 Shield 11 PWM CB 12 GND 13 GND 14 NC 15 NC 16 NC 17 Analog GND 18 Analog GND 19 NC 20 NC Technical Summary Rev 5 Freescale Semiconductor 2 15 Table 2 8 Secondary UNI 3 Connector Description Continued
44. a RE 2 30 2226 Timer Channel D Expansion 2 31 2 0 Address Bus Expansion qbus pasas wawa 2 32 2 22 10 Data Bus Expansion Connector AER EEN EE 2 33 222411 A D Port Expansion 2 33 2 22 12 Serial Communications Port 0 Expansion 2 34 2 22 13 Serial Communications Port 1 Expansion 2 34 2 22 14 Serial Peripheral Interface Expansion Connector 2 35 22215 CAN Expansion cud 2 35 2 22 16 PWM Port A Expansion 2 36 2 22 17 PWM Port B Expansion Connector 2 37 223 Secondary UNI 3 Unattached Signal Connector 2 38 251 TEPC E E AEL ET ode e ea 2 38 Appendix A 56F805EVM Schematics Appendix B 56F805EVM Bill of Material DSP56F805EVM User Manual Rev 5 Freescale Semiconductor 1 1 1 2 1 3 si 4 23 2 4 2 5 2 6 7 2 8 2 9 2 10 511 13 24 2 14 2 15 2 16 47 2 18 A 1 2 3 4 5 6 7 LIST OF FIGURES Block Diagram of the SOFSOSEVM 1 2 SOFS0SEVM Referenc ade 1 3 WE E the S56FSUSEVM Cables 2 d 1 4 Schematic Diagram of the Exter
45. at use the 56F805 The 56F805EVM is an evaluation module board that includes a 56F805 part peripheral expansion connectors external memory and a CAN interface The expansion connectors are for signal monitoring and user feature expandability The 56F805EVM is designed for the following purposes Allowing new users to become familiar with the features of the 56800 architecture The tools and examples provided with the 56F805EVM facilitate evaluation of the feature set and the benefits of the family Serving as a platform for real time software development The tool suite enables the user to develop and simulate routines download the software to on chip or on board RAM run it and debug it using a debugger via the JTAG OnCE port The breakpoint features of the OnCE port enable the user to easily specify complex break conditions and to execute user developed software at full speed until the break conditions are satisfied The ability to examine and modify all user accessible registers memory and peripherals through the OnCE port greatly facilitates the task of the developer Serving as a platform for hardware development The hardware platform enables the user to connect external hardware peripherals The on board peripherals can be disabled providing the user with the ability to reassign any and all of the controller s peripherals The OnCE port s unobtrusive design means that all of the memory on the board and on the chip are available to
46. customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized foruse as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part 2 freescale semiconductor Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners This product incorporates SuperFlash technology licensed from SST Freescale Semiconductor Inc 2005 All rights reserved DSP56F805EVMUM Rev 5 07 2005
47. e 1 1 Block Diagram of the 56F805EVM DSP56F805EVM User Manual Rev 5 Freescale Semiconductor 56F805EVM Configuration Jumpers 1 2 56F805EVM Configuration Jumpers Eighteen jumper groups JG1 JG18 shown in Figure 1 2 are used to configure various features on the 56F805EVM board Table 1 1 describes the default jumper group settings MOTOROLA bsessstvw 92 Figure 1 2 56F805EVM Jumper Reference Table 1 1 56F805EVM Default Jumper Options pi Comment onnections JG1 PDO input selected as a high 1 2 JG2 PD1 input selected as a high 1 2 JG3 Primary UNI 3 serial selected 1 2 3 4 5 6 amp 7 8 904 Secondary UNI 3 serial selected 1 2 3 4 5 6 amp 7 8 465 Enable on board Parallel JTAG Host Target Interface NC JG6 Use on board crystal for oscillator input 2 3 JG7 Selects the device s Mode 0 operation upon exit from reset 1 2 JG8 Enable on board SRAM 1 2 469 Enable RS 232 output 1 2 Introduction Rev 5 Freescale Semiconductor 1 3 Table 1 1 56F805EVM Default Jumper Options Continued ps Comment 4610 Secondary UNI 3 Analog Temperature Input unused 1 2 4611 Use Host power for Host Target Interface 1 2 9012 Pri
48. e Over Current signals are connected to the device s PWM group A s fault inputs i e FAULTAI FAULTA2 and FAULTA3 Figure 2 13 contains the diagram of the Over Voltage and one phase of the Phase Over Current circuit for the UNI 3 interface The FAULTAI input can be sourced from the Phase A Over Current circuit or the DC Bus Over Current circuit Jumper JG15 provides the selection see Figure 2 12 and Table 2 11 DC BUS CURRENT SENSE sense DCH 25 AA e JG15 3 2 gt gt FAULTA1 1 4 PHASE A CURRENT SENSE _1 gt AAA cnp Figure 2 12 FAULTA1 Selection Circuit Table 2 11 FAULTA1 Source Selection Jumper JG15 Comment 1 2 Phase Over Current Sense input 2 3 DC Bus Over Current Sense input DSP56F805EVM User Manual Rev 5 Freescale Semiconductor 2 20 Motor Protection Logic 2 16 2 Secondary UNI 3 Motor Protection Logic The Secondary UNI 3 interface is similar to the Primary UNI 3 interface The Secondary UNI 3 Over Voltage signal is connected to the controller s PWM group B s fault input device s FAULTBO The three Secondary UNI 3 Phase Over Current signals are connected to the controller s PWM group B fault inputs 1 FAULTB1 FAULTB2 and FAULTB3 The Secondary UNI 3 interface is similar to the circuits contained in Figure 2 13 The FAULTBI input can be sourced from the Phase A Over Current circuit or
49. e available for use by the end user 56F805 UNI 3 PWMAO gt gt PWMAO PWMA1 gt gt PWMA1 PWMA2 SS PWMA2 PWMA3 SS PWMA3 PWMA4 SS PWMA4 PWMAS5 gt PWMAS 50 YELLOW LED RA 4 PWM_AT 0 GREEN LED AN PWM_AB 1 YELLOW LED AUS 4 PWM BT 2 GREEN LED 4 4 PWM BB 3 YELLOW CM 4 4 PWM 4 GREEN LED 774 PWM CB 5 Figure 2 11 PWM Group A Interface and LEDs 2 16 Motor Protection Logic The 56F805EVM contains two UNI 3 connectors that interface with various motor drive boards Primary UNI 3 and Secondary UNI 3 The device can sense error conditions generated by the motor power stage boards via signals on the UNI 3 connector The motor driver board s Motor Supply DC Bus Voltage Current and Motor Phase Currents are sensed on the power stage board The conditioned signals are transferred to the board via the UNI 3 connector These analog input signals are compared to a limit set by trimpots If the input analog signals are greater than the limit set by the trimpot a controller digital voltage compatible 3 3V DC fault signal is generated Technical Summary Rev 5 Freescale Semiconductor 2 19 2 16 1 UNI 3 Motor Protection Logic The Primary UNI 3 DC Bus Over Voltage signal is connected to the controller s PWM group A fault inputs The three Primary UNI 3 Phas
50. e provided by adding a jumper to JG17 Refer to Table 2 13 for the CAN connector signals and Figure 2 17 for a connection diagram CAN CONNECTOR 56F805 MSCAN TX VCC VREF MSCAN_RX CANH CANL GND PCA82C250T TERMINATION 32 9 1 3 5 7 8 9 10 DAISY CHAIN CAN CONNECTOR Figure 2 17 CAN Interface Technical Summary Rev 5 Freescale Semiconductor 2 25 Table 2 13 Header Description J26 and J32 Pin Signal Pin Signal 1 NC 2 NC 3 CANL 4 CANH 5 GND 6 NC 7 NC 8 NC 9 NC 10 NC 2 21 Software Feature Jumpers The 56F805EVM board contains two software feature jumpers that allow the user to select User Defined software features Two GPIO port pins PDO and PD1 are pulled high with 10k ohm resistors on JG1 and JG2 Attaching a jumper will ground the respective Port D signal line see Figure 2 18 56F805 Figure 2 18 Software Feature Jumpers DSP56F805EVM User Manual Rev 5 2 26 Freescale Semiconductor Peripheral Connectors 2 22 Peripheral Connectors The EVM board contains a group of Peripheral Expansion Connectors used to gain access to the resources of the 56F805 The following signal groups have Expansion Connectors e Port B Port D PortE External Memory Control Encoder A Timer Channel A Encoder B
51. ed with a Power On LED referenced as LED10 5 0V 3 3V Regulator Regulator 56F805 56F805EVM Figure 2 8 Schematic Diagram of the Power Supply Technical Summary Rev 5 Freescale Semiconductor 2 13 2 11 Primary UNI 3 Interface Motor control signals from a family of motor driver boards can be connected to the EVM board via the Primary UNI 3 connector interface The Primary UNI 3 connector interface contains all of the signals needed to drive and control the motor drive boards These signals are connected to differing groups of the controller s input and output ports A D TIMER PWM Refer to Table 2 7 for the pin out of the Primary UNI 3 connector Table 2 7 Primary UNI 3 Connector Description J30 Pin Signal Pin Signal 1 PWM AT 2 Shield 3 PWM AB 4 Shield 5 PWM BT 6 Shield 7 PWM BB 8 Shield 9 PWM CT 10 Shield 11 PWM CB 12 GND 13 GND 14 5 0V DC 15 5 0V DC 16 Analog 3 3V DC 17 Analog GND 18 Analog GND 19 Analog 15V DC 20 Analog 15V DC 21 Motor DC Bus Voltage 22 Motor DC Bus Current Sense Sense 23 Motor Phase A Current 24 Motor Phase B Current Sense Sense 25 Motor Phase C Current 26 Motor Drive Temperature Sense Sense 27 NC 28 Shield 29 Motor Drive Brake Control 30 Serial COM 31 PFC PWM 32 PFC Inhibit 33 PFC Zero Cross 34 Zero Cross A DSP56F805E
52. emiconductor NVO peeds uBiH 81 JO 19945 sont 5 0002 0 Aepsony Jequiny NSQ WA3S0849SdSG juawnooy 9215 3OVdH3lNI NYO Q33dS HOIH vi 3O QW 955 568 215 XV4 0626 568 216 8698 9818 XL ullsny ISOM UOUURD 1099 UOISIAIG 19911259 5 5591941 NOILVNIWUISL sna NWO YOLOANNOO 5 NWO NIVHO ASIVG XI XX x HOLOZNNOO SNA NVO 1052028 24 9 9 34016 INYO TNV2 9 HNVO z UNES 0181 EE e AHA 99 axi gt gt Xu NVOSW lt XL DSP56F805EVM User Manual Rev 5 Freescale Semiconductor Appendix A 16 5 9 1 pue 3soH JojeJed 791 4 3 d gt gi 109 19945 1001 29001590 000z po Aepsany 2910 J qun NERT e eng Ov1f 30V3H31NI 139HVI LSOH 1311VHVd ll ti 30 0W 959 568 215 94 0626 968 19 UOISIAIG 194112540 ssajoJIM 8698 96 8 unsny AAG 1059 2 L 101 H gt od 9 s bs x 0 6 a 3838
53. in Signal 1 ANO 2 4 3 1 4 5 5 AN2 6 AN6 7 AN3 8 7 9 10 3 3VA Technical Summary Rev 5 Freescale Semiconductor 2 33 2 22 12 Serial Communications Port 0 Expansion Connector The Serial Communications Port 0 SCIO is attached to this connector Refer to Table 2 25 for connection information Table 2 25 SCIO Connector Description J16 Pin Signal 1 TXDO 2 RXDO 3 GND 2 22 13 Serial Communications Port 1 Expansion Connector The Serial Communications Port 1 SCII 1s attached to this connector Refer to Table 2 26 for connection information Table 2 26 SCI1 Connector Description J17 Pin Signal 1 TXD1 2 RXD1 3 GND DSP56F805EVM User Manual Rev 5 2 34 Freescale Semiconductor Peripheral Connectors 2 22 14 Serial Peripheral Interface Expansion Connector The Serial Peripheral Interface SPI is attached to this connector Refer to Table 2 27 for connection information Table 2 27 SPI Connector Description J19 Pin Signal 1 MOSI 2 MISO 3 SCLK 4 GND 2 22 15 CAN Expansion Connector The CAN port is attached to this connector Refer to Table 2 28 for connection information Table 2 28 CAN Connector Description J25 Pin Signal 1 MSCAN TX 2 MSCAN RX 3 GND Technical Summary Rev 5 Freescale Semiconductor 2 35 2 2
54. ller 2 1 D A Preface ix 4 0Amp power supply 2 13 D A converter 2 18 4 Channel 10 bit Serial D A 2 1 Data memory 2 4 56F805 Technical Data Preface x Debugging 2 7 64 16 bits of data memory 2 1 Development Card 2 1 64Kx16 bits of program memory 2 1 Digital to Audio 8 00MHz crystal oscillator 2 1 D A Preface ix DSP56800 Family Manual Preface x A DSP56F801 803 805 807 User s Manual Preface x A D Preface ix E Analog to Digital A D Preface ix Encoder Hall Effect 2 24 circuits 2 24 B Encoder Timer 2 30 Evaluation Module Back EMF 2 23 EVM Preface ix C EVM Preface ix External Memory Control Signal 2 29 external memory expansion connectors 2 2 external oscillator frequency input 2 1 bus termination 2 1 bypass 2 1 F interface 2 1 CAN in Automation FSRAM 2 1 2 4 CiA Preface ix CAN interface 2 1 G CAN physical layer peripheral 2 2 Preface ix General Purpose Input and Output Connector GPIO Preface ix A D 2 33 GPIO Preface ix 2 27 2 32 Address bus 2 32 signals 2 17 CAN 2 35 Data bus 2 33 H External Memory Control 2 29 PWM 2 36 Hall Effect Quadrature Encoder interface 2 1 SCI 2 34 Host Parallel Interface Connector 2 7 SPI 2 35 Host Target Interface 2 7 Connectors Peripheral Expansion 2 27 Controller Area Network CAN Preface ix Index Rev 5 Freescale Semiconductor Index 1 Preface ix Integrated Circuit IC Preface ix J Joint Test Action Group JTAG Preface ix JTAG Preface ix 1 1 2 1 connector 2
55. mary Encoder Input Selected 2 3 5 6 amp 8 9 JG13 Secondary Encoder Input Selected 2 3 5 6 amp 8 9 9014 Primary UNI 3 3 Phase Current Sense Selected as Analog Inputs 2 3 5 6 amp 8 9 JG15 Primary UNI 3 Phase A Over Current Selected for FAULTA1 1 2 4616 Secondary UNI 3 Phase Over Current Selected for FAULTB1 1 2 4617 termination unselected NC JG18 Use on board crystal for oscillator input 1 2 1 3 56F805EVM Connections An interconnection diagram is shown in Figure 1 3 for connecting the PC and the external 12V DC power supply to the 56F805EVM board PC compatible Computer Parallel Extension Cable Connect cable to Parallel Printer port P2 External 12V Power 56F805EVM P1 with 2 1mm receptacle connector Figure 1 3 Connecting the 56F805EVM Cables DSP56F805EVM User Manual Rev 5 Freescale Semiconductor 56F805EVM Connections Perform the following steps to connect the 56F805EVM cables 1 Connect the parallel extension cable to the Parallel port of the host computer 2 Connect the other end of the parallel extension cable to P1 shown in Figure 1 3 on the 56 805 board This provides the connection which allows the host computer to control the board 3 Make sure that the external 12V DC 4 0A power supply is not plugged into a 120V AC power source 4 Connect the 2 1mm output power plug from the external po
56. nal Memory 2 4 Schematic Diagram of the RS 232 2 5 Schematic Diagram ot th Clock Dicti oie pex ord e aci EROR E Rl 2 6 Schematic Diagram of the Debug LED Interface 2 7 Block Diagram of the Parallel JTAG 2 9 Schematic Diagram of the User Interrupt Interface 2 11 Schematic Diagram of the RESET Interface 2 12 Schematic Diagram of the Power Supply 2 13 Run Stop and General Purpose Switches 2 17 Serial 10 bit 4 Channel D A Converter 2 18 PWM Group A Interface and LEDS EE e 2 19 FAULTA I auda tn dC erae eo C e 2 20 DC Bus Over Voltage and Phase Over Current Detection Circuits 2 21 FAULTBI Selection Circuit 1 210 vir Ead re dE duh qr geb A ERE Ye xd as 2 22 Primary Back EMF or Motor Phase Current Sense 2 23 Zero Crossing e ai 2 24 2 25 EE ENER EE EE EE EES geg 2 26 __ CIE ak des 2 Rost Mode Clock amp IRO EE 3 3 Program amp Data SRAM Memory A 4 RS 232 a
57. nd 5 Debug Seral Dy A COG ER E E db 6 PWM r ELE User I d d RA TERRA EX dd d ad 7 Primary TER 8 List Figures Rev 5 Freescale Semiconductor iii 8 Secondary UNI 3 Over Voltage and Over Current 9 9 User General Purpose Switches and Jumpers A 10 A 10 Motor Phase Current Back EMF Voltage Analog Input Selector A 11 A 11 Primary and Secondary 3 Phase Over Current Sense 12 12 Primary Zero Crossing Quadrature Encoder or Selector 13 13 Secondary Zero Crossing Quadrature Encoder or Selector 14 14 Port 15 15 High Speed CAN SE EE E geg 16 16 Parallel JTAG Host Target Interface and JTAG Connector A 17 A 17 Pus Ey adc wi dad dE ERE A 18 A 18 Bypass Capacitors and Spare G8teg aa sasawa HER E ed E on A 19 DSP56F805EVM User Manual Rev 5 iv Freescale Semiconductor Preliminary 1 1 2 1 2 2 23 2 4 2 5 2 6 25 2 8 2 9 2 10 sd ERR 2 13 2 14 2 15 2 16 23 2 18 2 19 2 20 Ge 9 93 2 23 2 24 2 25 2 26 LIST OF TABLES 56F805EVM Default Jumper 1 3 RS 232 Serial Connector Dese fipti n uu uuu ask exe d
58. nerate a 0 to 3 3V DC pulse via voltage comparators The resulting pulse signals are sent to a set of jumper blocks shared with the Encoder Hall Effect interface The jumper blocks allow the selection of Zero Crossing signals or Quadrature Encoder Hall Effect signals When in operation the controller will only monitor one set of signals Encoder Hall Effect or Zero Crossing Figure 2 16 contains the Zero Crossing and Encoder Hall circuits ZERO X A 5 ZERO X B gt gt ZERO X C 5 56F805 FILTER PHASEB0 FILTER FILTER INDEX0 5 0V GROUND PHASE A PHASE B INDEX HOME Figure 2 16 Zero Crossing Encoder Interface DSP56F805EVM User Manual Rev 5 2 24 Freescale Semiconductor Interface 2 20 Interface 56F805EVM board contains CAN physical layer interface chip that is attached to the MSCAN and MSCAN TX pins on the 56F805 The EVM board uses a Philips PCA82C250 high speed 1Mbps physical layer interface chip Due to the 5 0V operating voltage of the CAN chip a pull up to 5 0V is required to level shift the Transmit Data output line from the 56F805 A primary J26 and daisy chain J32 CAN connector are provided to allow easy daisy chaining of CAN devices CAN bus termination of 120 ohms can b
59. p www freescale com Preface Rev 5 Freescale Semiconductor vii Notation Conventions This document uses the following conventions Term or Value Symbol Examples Exceptions Active High Signals No special symbol 0 Logic One attached to the CLKO signal name Active Low Signals Noted with an WE In schematic drawings Logic Zero overbar in text and OE Active Low Signals in most figures may be noted by a backslash WE Hexadecimal Begin with a Values symbol 80 Decimal Values No special symbol 10 attached to the 34 number Binary Values Begin with the letter 61010 attached to the b0011 number Numbers Considered positive 5 Voltage is often shown unless specifically 10 as positive 3 3V noted as a negative value Bold Reference sources See http www freescale com paths emphasis DSP56F805EVM User Manual Rev 5 viii Freescale Semiconductor Definitions 5 Abbreviations Definitions acronyms abbreviations for terms used this document defined below for reference A D CAN CiA D A EVM GPIO IC JTAG LQFP MPIO OnCE PCB PLL PWM ROM SCI SPI SRAM UART Analog to Digital Controller Area Network a serial communications peripheral and method CAN in Automation an international CAN user s group that coordinates standards for CAN communications protocols Digital to
60. re 2 1 This physical memory bank 1 split into two logical memory banks of 64Kx16 bits for Program memory and the other for Data memory By using the device s program strobe PS signal line along with the memory chip s 0 signal line half of the memory chip is selected when Program memory accesses are requested and the other half of the memory chip is selected when Data memory accesses are requested This memory bank will operate with zero wait state accesses while the 56 805 is running at 70MHz However when running at 80MHz the memory bank operates with four wait state accesses This memory bank can be disabled by removing the jumper at JG8 56F805 GS72116 A0 A15 A1 A16 Connect Pin 1 2 68 Enable SRAM Jumper Removed Disable SRAM Figure 2 1 Schematic Diagram of the External Memory Interface DSP56F805EVM User Manual Rev 5 2 4 Freescale Semiconductor RS 232 Serial Communications 2 3 RS 232 Serial Communications The 56F805EVM provides an RS 232 interface by the use of an RS 232 level converter Analog Devices ADM3311EARS designated as U16 refer to the RS 232 schematic diagram in Figure 2 2 The RS 232 level converter transitions the SCI UART s 3 3V signal levels to RS 232 compatible signal levels and connects to the host s serial port via connector P3 Flow control is not provided but could be implemented using uncommitted G
61. scription of the chip s operating modes Table 2 2 shows the two operation modes available on the 56 805 Table 2 2 Operating Mode Selection Operating Mode JG7 Comment 0 1 2 Bootstrap from internal memory GND 3 No Jumper Bootstrap from external memory 3 3V DSP56F805EVM User Manual Rev 5 2 6 Freescale Semiconductor Debug Support 2 6 Debug LEDs Three on board Light Emitting Diodes LEDs are provided to allow real time debugging for user programs These LEDs will allow the programmer to monitor program execution without having to stop the program during debugging refer to Figure 2 4 User LEDI is controlled by Port B s signal User LED2 is controlled by PB1 User LED3 is controlled by PB2 Setting 0 or PB2 to a Logic One value will turn on the associated LED 56F805 BUFFER PBO SN YELLOW LED ARK 4 GREEN LED C Figure 2 4 Schematic Diagram of the Debug LED Interface 2 7 Debug Support The 56F805EVM provides an on board Parallel JTAG Host Target Interface and a JTAG interface connector for external Target Interface support Two interface connectors are provided to support each of these debugging approaches These two connectors are designated the JTAG connector and the Host Parallel Interface Connector Technical Summary Rev 5 Freescale Semiconductor 2 7 2 7 1 The
62. t JG5 should be removed as shown in Table 2 4 A jumper JG11 is provided to allow the on board Host Target Interface to be powered by the Target board instead of the Host system when necessary reference Table 2 6 This may be necessary when using a 3 3V Host computer parallel port PARALLEL JTAG DB 25 INTERFACE LOGIC 56F805 PORT TDI TDI PORT TDO PORT TRST TRST PORT TMS TMS PORT TCK TCK PORT RESET RESET Figure 2 5 Block Diagram of the Parallel JTAG Interface Table 2 5 Parallel JTAG Interface Connector Description P1 Pin Signal Pin Signal 1 NC 14 NC 2 PORT RESET 15 PORT IDENT 3 PORT TMS 16 NC 4 PORT TCK 17 NC 5 PORT TDI 18 GND 6 PORT TRST 19 GND 7 NC 20 GND Technical Summary Rev 5 Freescale Semiconductor 2 9 Table 2 5 Parallel JTAG Interface Connector Description Continued P1 Pin Signal Pin Signal 8 PORT IDENT 21 GND 9 PORT VCC 22 GND 10 NC 23 GND 11 PORT TDO 24 GND 12 NC 25 GND 13 PORT CONNECT Table 2 6 On Board Host Target Interface Power Source Jumper Selection JG11 Comment 1 2 Host supplied power 2 3 Target supplied power DSP56F805EVM User Manual Rev 5 Freescale Semiconductor External Interrupts 2 8 External Interrupts Two on board push button switches are provided
63. ted Circuits 1 DSP56F805FV80 U1 Freescale DSP56F805FV80 6 LM393M U5 U6 U7 U8 U21 U22 National LM393M 2 MC74HC244DW U9 U10 ON Semiconductor MC74HC244DW 2 74 045 011 019 Fairchild 74 045 1 MC33269DT 5 0 U12 ON Semiconductor MC33269DT 5 0 1 MC33269DT 3 3 U13 ON Semiconductor MC33269DT 3 3 1 GS72116TP 12 U15 GSI GS72116TP 12 1 ADM3311EARS U16 Analog Devices ADM3311EARS 1 MAX5251BEAP U18 Maxim MAX5251BEAP 1 PCA82C250T U20 Philips Semiconductor PCA82C250T Resistors 20 16K R1 R2 R6 R7 R9 R10 R16 SMEC RC73L2A16KOHMJT R17 R20 R21 R24 R25 R28 R29 R67 R68 R108 R109 R111 R112 10 1M OQ R3 R8 R11 R18 R22 R26 SMEC RC73L2A1MOHMJT R30 R69 R110 R113 21 5 1K Q R4 R12 R13 R19 R23 R27 SMEC RC73L2A5 1KOHMJT R31 R32 R35 R37 R41 R57 R70 R105 R106 R114 R115 R121 R122 R123 R126 11 10K R42 R43 R44 R46 R48 R49 SMEC RC73L2A10KOHMJT R72 R73 R74 R119 R120 56F805EVM Bill of Material Rev 5 Freescale Semiconductor Appendix B 1 Qty Description Ref Designators Vendor Part s Resistors Continued 2 510 R33 R34 RC73L2A510HMJT 3 47K Q R36 R38 R104 SMEC RC73L2A47KOHMJT 1 4700 R40 SMEC RC73L2A470OHMJT 1 10M R45 SMEC RC73L2A10MOHMJT 19 1KQ R50 R51 R52 R53 R55 R75 SMEC RC73L2A1KOHMJT R78 R81 R84 R87 R90 R93 R96 R100 R101 R102 9 2700 R58 R59 R60 R61
64. the DC Bus Over Current circuit Jumper JG16 provides the selection reference Figure 2 14 and Table 2 12 DC BUS VOLTAGE SENSE V sense DCB gt gt gt FAULTO EXAMPLE CURRENT SENSE 5 0 gt gt FAULT2 Figure 2 13 DC Bus Over Voltage and Phase Over Current Detection Circuits Technical Summary Rev 5 Freescale Semiconductor 2 21 CURRENT SENSE sense DCB gt AAA AAA 5 0V 5 0V 1 PHASE A CURRENT SENSE PHA 15 2 A AA e AAA Figure 2 14 FAULTB1 Selection Circuit FAUuLTB1 Table 2 12 FAULTB1 Source Selection Jumper JG16 Comment 1 2 Phase A Over Current Sense input 2 3 DC Bus Over Current Sense input DSP56F805EVM User Manual Rev 5 2 22 Freescale Semiconductor Motor Phase Current Sensing 2 17 Back EMF and Motor Phase Current Sensing The primary and secondary UNI 3 connectors supply Back EMF and Motor Phase Current signals from the three phases of a motor attached to a motor drive unit Back EMF signals on the UNI 3 connectors are derived from a resistor divider network contained in the motor drive unit These resistors divide down the attached motor s Back EMF voltages to a 0 to 3 3V level In certain instances the Back EMF signals can exceed this maximum range
65. the user Introduction Rev 5 Freescale Semiconductor 1 1 1 1 56F805EVM Architecture The 56F805EVM facilitates the evaluation of various features present in the 56 805 part The 56 805 be used to develop real time software and hardware products based on the 56 805 The 56F805EVM provides the features necessary for a user to write and debug software demonstrate the functionality of that software and interface with the customer s application specific device s The 56F805EVM is flexible enough to allow a user to fully exploit the 56F805 s features to optimize the performance of his product as shown in Figure 1 1 56F805 RESET 4 Channel LOGIC RESET EM 10 bit D A MODE IRQ MODE RS 232 DSub LOGIC IRQ SE Interface 9 Pin Program Address CAN Interface Memory Data amp 11616 bit Control SCI 1 Peripheral Debug LEDs CAN Expansion LEDs Data Memory TIMER Connector s 64Kx16 bit Grid Over V Sense Over Sense Memory Expansion Zero Crossing Connector s Detect A D e UNI 3 Secondary Interface PWM 2 d Low Freq XTAL 3318 Power Supply Crystal EXTAL GND 3 3V 5 0V amp 3 3VA Figur
66. wer supply into P2 shown in Figure 1 3 on the 56F805EVM board 5 Apply power to the external power supply The green Power On LED LED10 will illuminate when power is correctly applied Introduction Rev 5 Freescale Semiconductor 1 5 DSP56F805EVM User Manual Rev 5 Freescale Semiconductor Chapter 2 Technical Summary 56F805EVM is designed as a versatile controller development card for developing real time software and hardware products to support a new generation of applications in digital and wireless messaging servo and motor control digital answering machines feature phones modems and digital cameras The power of the 16 bit 56F805 controller combined with the on board 64K x 16 bit external program static RAM SRAM 64K x 16 bit external data SRAM CAN interface Hall Effect Quadrature Encoder interface motor zero crossing logic motor bus over current logic motor bus over voltage logic and parallel JTAG interface makes the 56F805EVM ideal for developing and implementing many motor controlling algorithms as well as for learning the architecture and instruction set of the 56F805 processor The main features of the 56F805EVM include 56F805 16 bit 3 3V controller operating at 830MHz U1 External fast static RAM FSRAM memory U15 configured as 64 16 bits of program memory with 0 wait states at 70MHz 64 16 bits of data memory with 0 wait states at 70M Hz 4 Channel 10 bit Serial D
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