UM10391 - NXP Semiconductors
Contents
1. 3 o tly S o tly M a fE 2 f 8 5 3SN3SHS 8T 1 T 8 5 8 ET i H3AIHQ g gait LES mom o g 34 ac n ol HE Q aue wo x ups 2 S 5 1 15 eo O lt S Ey e 1d z me 2 s lt i 85 LE R 4 1 I ELE aye 8 NE ol a SF mi 43 i 2 sje af SES 5 x ol o N SES E 5 E mu EZ 9 lt 2 1 rir c xX gt d t Ea B 2 S TUN 99 o9 Q e o o ite Ke H ES HP j e Hue m jm asNasaa i il H3 dei 53 fano T T o hi a o or 3SN3SOA e o N m E 2 M Fe i5 p SAH 3ewasNA lt x o A EIN Il 2 8 SAH a 9 u l I jei I H TF tk gt lil HHE z c 2 gt lt E G s umo gt 8 3 Q m gi I Tp N x AVE aja o II E ike e z Slt E N W o a o a c t Ki gt 8 a A Hie 8 o E o ui _ FAI HE 9 Tz o G I No E E a g m a o m zd of c AAA r AAA z n j2. 14 Fig 12 External Over Temperature Protection OTP 15 Fig 13 Fast Latch Reset FLR 16 Fig 14 Ripple and noise 0 0 eee 19 Fig 15 Dynamic load response 20 Fig 16 Conducted EMI 110 Vline 21 Fig 17 Conducted EMI 230 Vline 22 Fig 18 Mains harmonic currents absolute values 24 Fig 19 Mains harmonic currents graphic representation 00 0 cece eee eee 24 Fig 20 Schematic of 90 W TEA1751T and TEA1791T adapter solution 20000000 25 Fig 21 Flyback transformer schematic 29 Fig 22 PFC inductor L2 schematic 30 Fig 23 Demo board top silk top view 31 Fig 24 Demo board bottom silk bottom view 31 Fig 25 Demo board bottom copper bottom view 32 UM10391 1 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 01 20 April 2010 36 of 37 NXP Semiconductors U M1 0391 90 Watt notebook adapter with TEA1751T and TEA1791T 13 Contents 1 Introduction lesen 3 13 Contents 0 cece cece eee eee 37 2 Specification 0 0c eee eee eee 4 3 Performance data 00 0ee sence eee 4 3 1 TeSt SetUp icu epa x ER PE oia 4 3 1 1 Test equipment 0 0 eee eee 4 3 1 2 Test conditions 0 00 e eee eee 4 3 2 EMClOnCy ice
3. Table 6 Load regulation Output voltage as a function of the output load and the mains input voltage Input voltage V Hz 90 60 90 60 264 50 264 50 Vout lout V A 19 404 0 19 147 4 62 19 403 0 19 143 4 62 Load regulation at 90 V 60 Hz is calculated as follows 19 404 V 19 147 V 195 V x 100 1 32 96 2 Load regulation at 264 V 50 Hz is calculated as follows 19 403 V 19 145 V 195 V x 100 1 33 96 3 3 4 2 Line regulation Test conditions The output voltage deviation was measured while the mains voltage on the input was increased from 90 V AC to 264 V AC The measurement was repeated for different mains input voltages Remark The output voltage was measured at the end of the output cable The load current was 4 62 A The line regulation was calculated using the following equation Vo UTmax Vo UTmin x 100 96 4 Voutnom where Voutnom 19 5 V UM10391_1 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 01 20 April 2010 17 of 37 NXP Semiconductors U M1 0391 3 4 3 90 Watt notebook adapter with TEA1751T and TEA1791T Criteria to pass The output voltage deviation must remain within 0 05 96 Table 7 Line regulation Output voltage at full load as a function of the mains input voltage Input voltage V Hz 90 60 115 60 132 60 180 50 230 50 264 50 Vout V 19 147
4. UM10391_1 90 Watt notebook adapter with TEA1751T and TEA1791T ANALYZER 6630 2089 04 85 15 43 07 Current Harmonics Gen setting 1 1 U 230 83 U fu 49 998 Hz fmaluysed periods 4 1 457 5 m P 97 94 Linit Class D EM61808B Aid 11 431 5 m Change to Note har graph THD 35 16 4 PF 8 931 PASSED nA Lin nA ma Lim mA n Lin nh Relative current z 25 1 13 0 22 2 12 2 19 6 16 8 WAND UN 16 4 15 1 e c ma VD ma OO me Th ee e NUS Ml D 14 0 a Ul C0 0 UG OG OD D UD QU NOP S2 IN e D e DNO QD e QD iR AJ Sie Se Ne CS 05 06 e Dw P i z 5 1212 81 001aak818 Fig 18 Mains harmonic currents absolute values ANALYZER 6630 2089 04 85 15 42 34 Current Harmonics Gen setting 161 U 238 83 U fu 49 999 Hz fnalysed periods 4 1 457 5 m P 97 9 U Linit Class D EM61B8H 614 I1 431 5 mA Note THD 35 16 4 PF 8 931 PASSED Relative current B 2 4 6 B 16 12 14 16 18 28 22 24 26 28 38 32 34 36 38 4A Harnonic order Appl ERIC 1212 B8 001aak819 Fig 19 Mains harmonic currents graphic representation All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 01 20 April 2010 24 of 37 NXP Semiconductors UM1 0391 90 Watt notebook adapter with TEA1751T and TEA1791T 5 Schematic diagram o Vout o Vout 001aak825
5. 29 7 2 PFC inductor L2 specifications 30 7 2 1 Inductor L2 specifications 30 8 PCB layout is asasan sre oce Rex ean 31 9 Abbreviations 000 00 eee eee ee 33 10 Legal information 34 10 1 Definitions za oac ce Sie see oe RED 34 10 2 Disclaimers scil ll rh 34 10 3 Trademarks ernieren wen radi ni nea 34 11 TADIOS iii 22s n nao n nain 35 12 Figures autas or x Rm ox SUE CR e 36 Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information NXP B V 2010 All rights reserved For more information please visit http Awww nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 20 April 2010 Document identifier UM10391 1
6. C31 Not mounted C34 0 1 uF 25 V X7R 0603 C35 10 nF 25 V X7R 0603 C36 Not mounted CX1 0 33 uF 275 V AC X2 MKP CY1 1000 pF 400 V AC Y1 Pitch 10 mm UM10391 1 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 01 20 April 2010 27 of 37 NXP Semiconductors UM10391 90 Watt notebook adapter with TEA1751T and TEA1791T Table 13 Default bill of materials for a 90 W TEA1751T and TEA1791T adapter solution continued Reference Component Package Remark BD1 GBU806 8 A 600 V Flat mini D1 MUR460 4 A 600 V DO 201AD Vishay D2 1N4148W SOD 123 D3 S2M SMB D4 1N4148W SOD 123 D5 BAS21 SOT23 NXP BAS20 is permitted D23A BAS21 SOT23 NXP BAS20 is permitted D27A 1N4148W SOD 123 D30 BAS21 SOT23 NXP Q1 2SK3568 TO220F Q2 2SK3569 TO220F Q4 PSMNO015 100P TO220 NXP U1 TEA1751T SO16 NXP GreenChip Ill PFC flyback controller U2 LTV817B DIP4 W CTR 130 260 spacing 10 16 mm U3 TEA1791T SO8 NXP GreenChip SR controller U4 AP431SR SOT 23R diodes T1 Flyback transformer 450 uH PQ3220 see specification L1 Inductor 210 uH T50 52 L2 PFC inductor 250 uH RM10 see specification L3 Inductor CM 200 uH T12 6 4 LF1 Inductor CM 500 uH T12 6 4 LF2 Inductor CM 12 8 MH T16 12 18 BC1 Bead core R5B XP N4 AMAX RH 4 6 2 placed at cathode of D1 BC2 Bead core S6H JK N6 AMAX RH 3 5 4 2 1 3 placed at lead of CY1 F1 Fuse T3 15 A 250 V LT5 UM10
7. x H i o o I Aree O dpeen z o E z oT i i Jr e l o N o Lu UM10391 1 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 01 20 April 2010 25 of 37 NXP Semiconductors U M1 0391 90 Watt notebook adapter with TEA1751T and TEA1791T 6 Bill of materials Table 13 Default bill of materials for a 90 W TEA1751T and TEA1791T adapter solution Reference Component Package Remark R1 2 MO 1 1206 R2 2 MO 1 96 1206 R3 560 kQ 1 96 1206 R4 47 kQ 1 96 0603 R5 3 3 MQ 1 96 1206 R5A 3 3 MQ 1 1206 R6 2 7 MQ 1 96 1206 R7 60 4 kO 1 96 0603 R8 10 0 5 96 0805 R9 10 0 5 96 0805 R10 0 10 596 1W Axial metal oxide film R11 15 KQ 5 96 0603 R12 1 kQ 5 96 0805 R13 10 0 5 96 0805 R14 10 0 5 96 0805 R15 0 10 5 1W Axial metal oxide film R15A 0 30 1 RL1632 R16 27 KQ 5 96 0603 R16A 750 Q 5 96 0603 R17 1 kQ 5 96 0603 R18 43 kO 5 96 1206 R19 43 kO 5 96 1206 R20 47 Q 5 96 0805 R21 00 0805 R22 10 KQ 5 96 0805 R23 82 kQ 1 96 0603 R23A 47 kQ 1 96 0603 R24 39 kO 5 96 0603 R25 39 kQ 5 96 0603 R26 10 KQ 5 96 0603 R27 5 1 KQ 5 96 1206 R30 10 0 5 96 0805 R32 1 kQ 5 96 0805 R33 Not Mounted R34 1 kQ 5 96 0603 R35 2 7 KQ 5 96 0603 R36 10 KQ 5 96 0603 R37 35 7 kQ 1 96 0603 R38 5 23 kQ 1 96 0603 UM10391 1 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User
8. and adapters supplied with notebooks as Energy Star efficient they have to pass the active mode and no load criteria as stated in the Energy Star standard for External Power Supplies EPS2 0 The minimum active mode efficiency is defined as the arithmetic average efficiency at 25 50 75 and 100 of the rated output power as printed on the name plate of the adapter 3 2 2 1 Active mode efficiency Test Conditions The unit was set to maximum load and well pre heated until temperature stabilization was achieved Temperature stabilization was established for every load step before recording any measurements Remark The output voltage was measured at the end of the output cable Criteria to pass To comply with Energy Star EPS2 0 the arithmetic average of the four efficiency measurements must be greater than or equal to 87 96 Universal mains adapters have to pass the criteria at both 115 V 60 Hz and 230 V 50 Hz UM10391 1 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 01 20 April 2010 5 of 37 NXP Semiconductors U M1 0391 3 2 2 2 90 Watt notebook adapter with TEA1751T and TEA1791T Table 2 Active mode efficiency at 115 V 60 Hz Load lout A Vout V Pour W Pin W Efficiency Power percentage factor 100 4 624 19 130 88 45 98 59 89 72 0 984 75 3 468 19 198 66 58 73 47 90 63 0 973 50 2 312 19 266 44 53 49 05 90
9. customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof UM10391_1 All information provided in this document is subject to legal disclaimers Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in medical military aircraft space or life support equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors accepts no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification NXP Semiconductors does not accept any liability related to any d
10. mode and Vo 0 V The electronic load was set to the maximum output current Criteria to pass Switch on delay two seconds maximum after the AC mains voltage is applied to the time when the output is within regulation Output rise time The output voltage shall rise from 10 96 of the maximum to the regulation limit within 30 mS There must be a smooth and continuous ramp up of the output voltage No voltage with a negative polarity shall be present at the output during start up Tek Prevu E Tek Prevu E a H i Cha Rise Ch4 Rise s g j 12 96ms 12 83ms 2 2 35 3 TEPPEEPEPER i IER ge E METEPEZCEEEEEES zi Mi200ms Al Ch4 f ME 500v amp Ch2 20 0V 5 M 200ms A Ch4 f 13 0V Ch3 500mV AiCh4 10 0 V 8 25 Mar 2009 Ch3 500mV AiCh4 10 0V 8 25 Mar 2009 17 09 22 17 10 44 001aak782 001aak783 Mains input 90 V 60 Hz delay time 488 ms Mains input 264 V 50 Hz delay time 488 ms Load 4 63 A CH1 mains input CH2 VCC pin TEA1751T CH3 FBSENSE pin TEA1751T soft start Load 4 68 A CH1 mains input CH2 VCC pin TEA1751T CH3 FBSENSE pin TEA1751T soft start CH4 Vout CH4 Vout Fig 2 Delay between switch on and output in regulation UM10391 1 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 01 20 April 2010 7 of 37 NXP Semiconductors UM10391 90 Wat
11. 001aak795 001aak794 1 60 V Output short circuit applied before start up Load 4 63 A CH1 VINSENSE pin TEA1751T CH2 VCC pin TEA1751T CH3 FBDRIVER pin TEA1751T CH4 FBCTRL pin TEA1751T Tek Prevu 4 4 20 0V WiE 5 00V M 200ms A Chl 2 00 V Mains input 90 V 60 Hz input power 0 96 W Load 0 A CH1 VCC pin TEA1751T CH2 FBCTRL pin TEA1751T CH3 Vdrn flyback Mosfet CH4 Vout Fig 9 Output short circuit protection Chi 20 0 V 5 5 00 V_ Chi 20 0 V A SIE 5 00 V M 200ms A Chl 7 2 00 V Ch3 200V amp Ch4 20 0V amp 3 Apr 2009 Ch3 200V amp Ch4 20 0V amp 3 Apr 2009 10 25 51 10 28 36 001aak796 001aak797 Mains input 264 V 50 Hz input power 0 84 W Load 0A CH1 VCC pin TEA1751T CH2 FBCTRL pin TEA1751T CH3 Varn flyback Mosfet CH4 Vout UM10391_1 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 01 20 April 2010 12 of 37 NXP Semiconductors U M1 0391 90 Watt notebook adapter with TEA1751T and TEA1791T 3 3 4 Over current protection Test Conditions The load was increased from the maximum value to an estimated over current value in several steps The test was repeated for different input voltages Criteria to pass The output power should be limited and may not exceed 240 W just before the triggering of the over current p
12. 19 147 19 147 19 143 19 143 19 143 Load regulation at 90 V 60 Hz was calculated using the following equation 19 147 V 19 1435 V IDEE x 100 0 02 5 Ripple and noise PARD Periodic And Random Deviation Ripple and noise are defined as the periodic or random signals over a frequency band of 10 Hz to 20 MHz Test Conditions The measurement was made with an oscilloscope having a 20 MHz bandwidth The output was shunted at the end of the output cable by a 0 1 uF ceramic disk capacitor and a 22 uF electrolytic capacitor to simulate loading Criteria to pass The P A R D of the output must remain within the specified limits 100 mVp p at a maximum load current of 4 62 A Table 8 Ripple and noise P A R D Ripple and noise at maximum load as a function of the mains input voltage Input voltage V Hz 90 60 115 60 132 60 180 50 230 50 264 50 PARD mV 84 88 83 62 60 60 UM10391_1 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 01 20 April 2010 18 of 37 NXP Semiconductors UM10391 90 Watt notebook adapter with TEA1751T and TEA1791T Tek Stop J i j 1 J 1 1 1 i 1 1 J i i M10 Ops A Chi tf 4 00mv 100mV VAi 26 Mar 2009 1539 20 18 23 17 001aak807 a Mains input 90 V 60 Hz Ch1 Vout Tek Stop eee ere e
13. manual Rev 01 20 April 2010 26 of 37 NXP Semiconductors UM10391 90 Watt notebook adapter with TEA1751T and TEA1791T Table 13 Default bill of materials for a 90 W TEA1751T and TEA1791T adapter solution continued Reference Component Package Remark R39 not mounted RT1 Jumper RT2 NTC 100 kQ D 5 mm Radial lead TTC050104 C1 Film capacitor 0 47 pF 450 V 10 C2 Film capacitor 0 47 uF 450V 10 C3 Electrolytic capacitor Radial 16x30 mm 100 uF 400V 105 C C3A 10 nF 1 kV Z5U Disk 11 5 mm C4 10 nF 25 V X7R 0603 C5 220 pF 630 V NPO 1206 C6 0 1 uF 25 V X7R 0603 C8 3300 pF 630 V 1206 C9 100 pF 630 V NPO 1206 C10 0 1 uF 25 V X7R 0805 C12 220 pF 100 V NPO 0805 C13 Electrolytic capacitor Radial 5 x 11 mm low impedance type 47 uF 35V 105 C C14 1 uF 50 V Y5V 0805 C15 10 nF 25 V X7R 0603 C16 0 33 nF 10 V X7R 0603 timing capacitor review tolerance C17 0 33 nF 10 V X7R 0603 C18 0 47 uF 10 V X7R 0603 C19 10 nF 25 V X7R 0603 C20 2 2 uF 10 V Y5V 0603 C21 2 2 uF 10 V Y5V 0603 C22 220 pF 50 V NPO 0603 10 V is permitted C23 220 pF 50 V NPO 0603 10 V is permitted C27 Electrolytic capacitor Radial 10 x 12 5 mm low impedance type 470 pF 25V 105 C C28 Electrolytic capacitor Radial 10 x 12 5 mm low impedance type 470 pF 25V 105 C C29 Electrolytic capacitor Radial 10 x 12 5 mm low impedance type 470 pF 25V 105 C C30 1 uF 50 V Y5V 0805
14. se toile eee Y ivy iA we ee 5 3 2 1 Efficiency PFC plus flyback stage 5 3 2 2 Energy Star efficiency 0 5 3 2 2 1 Active mode efficiency 5 3 2 2 2 No load input power 6 3 3 Timing and protection 7 3 3 1 Switch on delay and output rise time 7 3 3 2 Brownout and brownout recovery 8 3 3 3 Output short circuit and open loop protection 9 3 3 3 1 Open loop protection 9 3 3 3 2 Short circuit protection 11 3 3 4 Over current protection 4 13 3 3 5 Output Over Voltage Protection OVP 13 3 3 6 Over temperature protection 15 3 3 7 Fast latch reset 00 eee eae 15 3 4 Output regulation and characterization 17 3 4 1 Load regulation llle 17 3 4 2 Line regulation 0 00 eee 17 3 4 3 Ripple and noise PARD Periodic And Random Deviation 18 3 4 4 Dynamic load response 20 4 ElectroMagnetic Compatibility EMC 21 4 1 Conducted emission 5 21 4 2 Immunity against lighting surges 22 4 3 Immunity against ESD 23 4 4 Mains harmonic reduction 23 5 Schematic diagram 25 6 Bill of materials suseee 26 7 Transformer and inductor specifications 29 7 1 Flyback transformer T1 specifications
15. subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 01 20 April 2010 31 of 37 NXP Semiconductors UM1 0391 90 Watt notebook adapter with TEA1751T and TEA1791T 001aak824 Fig 25 Demo board bottom copper bottom view UM10391 1 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 01 20 April 2010 32 of 37 NXP Semiconductors UM10391 9 Abbreviations 90 Watt notebook adapter with TEA1751T and TEA1791T UM10391_1 Table 16 Abbreviations table Acronym CC CR CV EMC EMI EMS ESD FLR LISN MHR OTP OCP OVP PCB PE PFC SCP SMPS SR TIW UEW USTC Description Constant Current Constant Resistance Constant Voltage ElectroMagnetic Compatibility ElectroMagnetic Interference ElectroMagnetic Susceptibility ElectroStatic discharge Fast Latch Reset Line Impedance Standardization Network Mains Harmonic Reduction Over Temperature Protection Over Current Protection Over Voltage Protection Printed Circuit Board Protective Earth Power Factor Correction Short Circuit Protection Switched Mode Power Supply Synchronous Rectification Triple Insulated Wire PolyUrethane Enameled Wire PolyUrethane Silk Tetrone Covered All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User man
16. 0 us short circuit current Test voltage 2 kV L1 L2 2 ohm L1 PE L2 PE amp L1 L2 PE 12 ohm Phase angle 0 90 180 and 270 degrees Number of tests 5 positive and 5 negative Pulse repetition rate 20 s Test result There was no disruption of functionality UM10391 1 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 01 20 April 2010 22 of 37 NXP Semiconductors U M1 0391 UM10391_1 4 3 4 4 90 Watt notebook adapter with TEA1751T and TEA1791T Immunity against ESD Test conditions ESD air discharge at the ground terminal of the output cable connector Criteria to pass EC61000 4 2 air discharge level 3 8 kV and level 4 15 kV Table 12 Immunity against ESD Performance of the adapter at an ESD air discharge ESD performance No disruption of function Auto recovery Demo board according to schematic 12kV 15 kV Demo board with 6 x 10 M across Y cap 16 5 kV Mains harmonic reduction Test conditions The unit was set to maximum load The input voltage was 230 V 50 Hz Criteria to pass Compliance with EN61000 3 2 A14 class D Test result Passed see Figure 18 and Figure 19 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 01 20 April 2010 23 of 37 NXP Semiconductors U M1 0391
17. 10391 1 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 01 20 April 2010 3 of 37 NXP Semiconductors U M1 0391 2 Specification 90 Watt notebook adapter with TEA1751T and TEA1791T Mains input voltage 90 V to 264 V 47 Hz to 63 Hz DC output 19 5 V 2 Maximum continuous output current 4 62 A Peak output current 7 5 A Efficiency 87 96 at maximum load CEC active mode efficiency gt 90 No load power consumption 0 3 W Dynamic load response lt 1 V 0 5 V Output ripple and noise 100 MVp p max CISPR22 class B conducted EMI EN61000 4 2 immunity against ESD EN61000 3 2 A14 harmonics compliance Short Circuit Protection SCP and output Over Current Protection OCP input power 3 W at both SCP and OCP test Latched output Over Voltage Protection OVP 25 V Latched Over Temperature Protection OTP Fast Latch Reset FLR 3 sec 3 Performance data UM10391 1 3 1 Test setup 3 1 1 Test equipment Programmable AC Source Chroma Model 61503 Power HiTester Hioki Model 3332 DC Electronic Load Chroma Model 63030 Digital Oscilloscope Tektronix Model TDS5104B Current Probe Amplifier Tektronix Model TCP305 TCPA300 100 MHz High Voltage Differential Probe Tektronix Model P5205 6 Digit Multimeter Agilent Model 34401A EMC receiver Rohde amp Schwarz ESPI 3 LISN ENV216 3 1 2 Test condit
18. 391 1 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 01 20 April 2010 28 of 37 NXP Semiconductors UM10391 90 Watt notebook adapter with TEA1751T and TEA1791T 7 Transformer and inductor specifications 7 1 Flyback transformer T1 specifications Primary inductance 450 uH 5 96 Leakage inductance 6 uH max Core Bobbin PQ3220 Core material PC44 HI POT prim sec 3 kV 5 mA 3 sec Manufacturer Send Power Electronics Co LTD Taiwan ROC Primary Secondary 2 E 7 N5 1 N1 N6 Bi 9 N2 l 1 9 E 10 E4 l N4 N7 5 NI 8 E3 Na 3l N8 6 Le s 11 i E2 nad xm E1 E1 E2 E3 E4 N1 Bobbin Start Teflon tube Tape E Black teflon tube 014aab118 Fig 21 Flyback transformer schematic Table 14 Flyback transformer winding details Winding Pin number Wire type Number of Number of turns Remarks order Start Finish wires Winding MYLAR tape 1 N1 7 9 TEX E 3L 0 3 mm 2 6 1 2 El 6 Copper foil 0 025 mm x 7 mm 1 1 finished with wire 0 3 3 N2 1 4 2 UEW 0 5 mm 1 16 1 4 E2 6 Copper foil 0 025 mm x 7 mm 1 1 finished with wire 0 3 5 N3 6 2 UEW 0 25 mm 2 7 1 6 N4 10 TEX E 3L 0 3 mm 2 6 1 7 E3 6 Copper foil 0 025 mm x 7 mm 1 1 finished with wire 0 3 8 N5 4 2 2 UEW 0 5 mm 1 16 1 9 E4 6 Copper foil 0 025 mm x 7 m
19. 5 mm x 59 mm The PCBs are produced on 1 6 mm FR2 with single sided 2 Oz copper 70 um The Gerber File set for production of the PCB is available through the local NXP sales office E i NN E N E f E py Q1 Di C1 C2 C3A J3 T3 15 A 250 V R15 Eec T Q4 Y D NAR a c APBADCOS1 Ver A 7 FE s2 Fiet Frnt 001 aak82 Fig 23 Demo board top silk top view R15B R15A C9 R13 D3 lt 4 kd eo R19 D4 68 Iris C Re R5 R8 ped n D23A E 4 p2 C30 H R39 L 1R23A gg mee PEN Ies eow R36 ra R16 j 1 i C36 Rai R20 E cio He RUD 120w a 93 ieas TIREN CI pz TEA1751 TT or yas ene AL Ca R R38 NES na WE c22 _ TEA1752 R2 R33 Qu Los es na ieee C14 lt IL ILLELLL R25 O nss C15 ECII 1o 1 R27 HE HL cie C 1 3 ier R3 C31 R32 R30 R94 R26 CL R4 cig C21 C17 C20 001aak823 Fig 24 Demo board bottom silk bottom view All information provided in this document is
20. 80 0 950 25 1 156 19 329 22 35 24 61 90 83 0 452 Average s 90 49 Table 3 Active mode efficiency at 230 V 50 Hz Load lout A Vout V Pour W Pin W Efficiency Power percentage factor 100 4 624 19 124 88 42 97 84 90 37 0 924 75 3 468 19 195 66 57 73 76 90 25 0 901 50 2 312 19 262 44 53 50 18 88 74 0 880 25 1 157 19 330 22 36 24 59 90 94 0 379 Average 5 90 08 No load input power Test Conditions The unit was set to maximum load and preheated After 5 minutes the load was removed The no load input power measurements were recorded after stabilization of the input power reading Criteria to pass To comply with Energy Star EPS2 0 the input power shall be less than 0 5 W Universal mains adapters have to pass the criteria at both maximum input voltages 115 V 60 Hz and 230 V 50 Hz Table4 No load input power No load input power as a function of the mains input voltage V Hz 90 60 115 60 132 60 180 50 230 50 264 50 Input power Pin W 0 124 0 130 0 137 0 158 0 186 0 200 UM10391_1 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 01 20 April 2010 6 of 37 UM10391 90 Watt notebook adapter with TEA1751T and TEA1791T NXP Semiconductors 3 3 Timing and protection 3 3 1 Switch on delay and output rise time Test conditions e The electronic load was set to Constant Current CC
21. UM10391 90 Watt notebook adapter with TEA1751T and TEA1791T Rev 01 20 April 2010 User manual Document information Info Content Keywords GreenChip III TEA1751T GreenChip SR TEA1791T PFC flyback synchronous rectification high efficiency adapter notebook PC power Abstract This manual provides the specification performance schematics bill of materials and PCB layout of a 90 W notebook adapter with the TEA1751T and TEA1791T For design details on the TEA1751T and TEA1791T please refer to the application notes NXP Semiconductors U M1 0391 90 Watt notebook adapter with TEA1751T and TEA1791T Revision history Rev Date Description UM10391 1 20100420 First release Contact information For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com UM10391 1 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 01 20 April 2010 2 of 37 NXP Semiconductors U M1 0391 90 Watt notebook adapter with TEA1751T and TEA1791T 1 Introduction This manual describes a universal input 19 5 V 4 62 A single output power supply using TEA1751T and TEA1791T devices from NXPsemiconductor s GreenChip III and GreenChip SR family It contains the power supply specifications circuit diagram component list to build the supply PCB layout and component po
22. ad change Table9 Dynamic load response Deviation of the output voltage at a load step from 4 62 A to 0 A and from 0A to 4 62 A Input voltage V Hz Deviation mV 90 60 264 50 600 580 Tek Stop t 26 Mar 2009 26 Mar 2009 1530 20 18 48 14 15 30 20 18 49 07 001aak813 001aak814 Mains input 90 V 60 Hz Mains input 264 V 50 Hz CH1 Vout CH1 Vout CH2 lout CH2 lout Fig 15 Dynamic load response UM10391_1 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 01 20 April 2010 20 of 37 NXP Semiconductors UM1 0391 90 Watt notebook adapter with TEA1751T and TEA1791T 4 ElectroMagnetic Compatibility EMC 4 1 Conducted emission Test Conditions The unit was subjected to maximum load The ground connection of the output cable was connected to EMC ground Criteria to pass CISPR22 Class B with 10 dB production margin 100 001aak816 dBuV 80 1 60 1 2 2 40 1 Xx x 3 20 0 10 1 1 10 102 f MHz 1 QP limit 2 AV limit 3 Peak reading The conducted EMI measurement of 110 V neutral is close to 110 V line Fig 16 Conducted EMI 110 V line Table 10 Conducted EMI measurements 110 V line Refer to Figure 16 points 1 and 2 on the
23. ation 0005 18 Table 8 Ripple and noise P A R D 18 Table 9 Dynamic load response 20 Table 10 Conducted EMI measurements 110 V line 21 Table 11 Conducted EMI measurements 230 V line 22 Table 12 Immunity against ESD 23 Table 13 Default bill of materials for a 90 W TEA1751T and TEA1791T adapter solution 26 Table 14 Flyback transformer winding details 29 Table 15 PFC inductor L2 winding details 30 Table 16 Abbreviations table 33 UM10391_1 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 01 20 April 2010 35 of 37 NXP Semiconductors U M1 0391 90 Watt notebook adapter with TEA1751T and TEA1791T 12 Figures Fig 1 90 W TEA1751T and TEA1791T demo board 3 Fig 2 Delay between switch on and output in regulation ite eee RA ee Re 7 Fig 3 Output rise time at full load start up 8 Fig 4 Brownout and brownout recovery 9 Fig 5 Normal start up at 90 V 60Hz 10 Fig 6 Normal start up at 264 V 50Hz 10 Fig 7 Output short circuit at 90 V 60Hz 11 Fig 8 Output short circuit at 264 V 50Hz 12 Fig 9 Output short circuit protection 12 Fig 10 Output over current protection 138 Fig 11 Output over voltage protection
24. e input power must be less than 3 W during the short circuit test After removal of the short circuit the unit shall recover automatically Tek Stop E i TekStop F v i T i T D j i Pe H B e i 3 chil 2 00 V WCh2 20 0 V iMD0 0ms A Ch4 V Chit 2 00 V Wch2 20 0V E M 20 0ms A Ch4 Ch3 10 0 V SRE 2 00V j 26 Mar 2009 Ch3 10 0 V SiR 2 00V A 26 Mar 2009 i3 50 40 15 18 50 i3 30 20 15 20 00 001aak793 001aak792 Output short circuit during normal operation Output short circuit applied before start up Load 4 63 A Load 4 63 A CH1 VINSENSE pin TEA1751T CH1 VINSENSE pin TEA1751T CH2 VCC pin TEA1751T CH2 VCC pin TEA1751T CH3 FBDRIVER pin TEA1751T CH3 FBDRIVER pin TEA1751T CH4 FBCTRL pin TEA1751T CH4 FBCTRL pin TEA1751T Fig 7 Output short circuit at 90 V 60 Hz UM10391_1 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 01 20 April 2010 11 of 37 NXP Semiconductors UM10391 90 Watt notebook adapter with TEA1751T and TEA1791T Tek Stop V M20 0ms A Ch4 X 2 36 V Output short circuit during normal operation Load 4 63 A CH1 VINSENSE pin TEA1751T CH2 VCC pin TEA1751T CH3 FBDRIVER pin TEA1751T CH4 FBCTRL pin TEA1751T Fig 8 Output short circuit at 264 V 50 Hz Ch3 10 0 V sE 2 00V 5i 26 Mar 2009 26 Mar 2009 50 20 15 21 55 30 20 15 20 58
25. e latch reset Remark Both live and neutral must be switched Criteria to pass The latch should be reset within 3 seconds after switching off and subsequently switching on the mains input voltage Tek Stop E Tek Prevu E J Chi 20 0 V jch2 20 0V iM 1 00 S 2 QE 500V sicha 2 00V 4 2 1 1 001aak805 001aak806 Mains input 90 V 60 Hz FLR 1 6 s Mains input 264 V 50 Hz IFLR 1 3 s CH1 Vout CH1 Vout CH2 VCC pin TEA1751T CH2 VCC pin TEA1751T CH3 AC mains input CH3 AC mains input CH4 VINSENSE pin TEA1751T CH4 VINSENSE pin TEA1751T Fig 13 Fast Latch Reset FLR UM10391_1 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 01 20 April 2010 16 of 37 NXP Semiconductors U M1 0391 90 Watt notebook adapter with TEA1751T and TEA1791T 3 4 Output regulation and characterization 3 4 1 Load regulation Test conditions The output voltage deviation was measured while the load current on the output was increased from 0 A to 4 62 A The measurement was repeated for different mains input voltages Remark The output voltage was measured at the end of the output cable Criteria to pass e The output load regulation must remain within 2 96 The load regulation was calculated using the following equation V V OUTmax OUTmin x 100 1 Voutnom where Voutnom 19 5 V
26. efault damage costs or problem which is based on a weakness or default in the customer application use or the application use of customer s third party customer s hereinafter both referred to as Application It is customer s sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product NXP Semiconductors does not accept any liability in this respect Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from national authorities 10 3 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners GreenChip is a trademark of NXP B V NXP B V 2010 All rights reserved User manual Rev 01 20 April 2010 34 of 37 NXP Semiconductors UM10391 90 Watt notebook adapter with TEA1751T and TEA1791T 11 Tables Table 1 Efficiency PFC plus flyback stage 5 Table 2 Active mode efficiency at 115 V 60Hz 6 Table 3 Active mode efficiency at 230 V 5O Hz 6 Table 4 No load input power esses 6 Table 5 Output over voltage protection 14 Table 6 Load regulation 0005 17 Table 7 Line regul
27. h off The unit shall power up by the time the input AC line voltage reaches 85 V max UM10391 1 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 01 20 April 2010 8 of 37 NXP Semiconductors UM1 0391 90 Watt notebook adapter with TEA1751T and TEA1791T Tek stop E n Tek Stop E y u i ve E ite i4 HE PH H 1 il Hi Chi 250V j ch2 200V q M20 0ms A Ch4 X 13 2 v A hi 250 V ICh2 200 V TEXTE E cha 13 2v Ch3 250V Ni 20 0V 14 Apr 2009 ch3 250V sW 20 0 v 14 Apr 2009 50 40 08 46 39 15 30 00 08 54 17 001aak787 001aak786 Mains input from 90 V AC to 0 V AC brownout Mains input from 0 V AC to 90 V AC brownout voltage 70 V AC recovery 75 V AC Load 4 63 A Load 4 63 A CH1 mains input CH1 mains input CH2 Vdrn PFC Mosfet CH2 Vdrn PFC Mosfet CH3 Varn flyback Mosfet CHS Vdrn flyback Mosfet CH4 Vout CH4 Vout Fig 4 Brownout and brownout recovery 3 3 3 Output short circuit and open loop protection To protect the adapter and application against an output short circuit or a single fault open flyback feedback loop situation a time out protection is implemented When the voltage on FBCTRL pin rises above 4 5 V typ a fault is assumed and switching is blocked The time out protection should not trigger during a normal start up with maximum load 3 3 8 4 Open loop protection Test Condi
28. ions Unit on the lab table with the heat sinks downwards No casing was present on the unit Lab temperature between 20 C and 25 C Measurements were made after stabilization of temperature according test method for calculating the efficiency of single voltage external AC DC and AC AC power supplies of Energy Star All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 01 20 April 2010 4 of 37 NXP Semiconductors U M1 0391 90 Watt notebook adapter with TEA1751T and TEA1791T 3 2 Efficiency 3 2 1 Efficiency PFC plus flyback stage Test conditions Before any measurements were recorded the unit was set to maximum load and well pre heated so that stabilization of the input and output meter readings was achieved Remark The output voltage was measured at the end of the output cable Criteria to pass e The efficiency must be gt 87 96 at the maximum continuous output load Table 1 Efficiency PFC plus flyback stage Efficiency total converter at full load as a function of the mains input Input Voltage l n RMS A Pour W Pin W Efficiency Power factor V Hz 90 60 1 134 88 43 99 98 88 45 0 991 100 50 1 016 88 45 99 41 88 96 0 990 115 60 0 883 88 45 98 59 89 72 0 984 230 50 0 468 88 42 97 84 90 37 0 924 264 50 0 414 89 27 97 58 90 46 0 907 3 2 2 Energy Star efficiency To market adapters sold as stand alone adapters
29. ler should shut down and stay in a latched mode Asingle point fault should not cause a sustained over voltage condition at the output Table 5 Output over voltage protection Output over voltage at no load as a function of the mains input voltage with protection mode latched Input voltage V Hz 90 60 OVP trip point V 22 0 132 60 180 50 264 50 22 4 22 6 22 5 Tek Stop t Tek Stop t i s Mj400ms 1 80 V 3 Apr 2009 3 Apr 2009 11 34 12 11 36 06 001aak800 001aak801 a Mains input 90 V 60 Hz b Mains input 132 V 60 Hz Tekstop t Tek Stop f 10 0 V 3 Apr 2009 3 Apr 2009 11 34 12 11 36 06 001aak800 001aak801 c Mains input 180 V 50 Hz CH1 Vout CH2 VCC pin TEA1751T d Mains input 264 V 50 Hz Fig 11 Output over voltage protection UM10391 1 All information provided in this document is subject to legal disclaimers User manual Rev 01 20 April 2010 NXP B V 2010 All rights reserved 14 of 37 NXP Semiconductors U M1 0391 90 Watt notebook adapter with TEA1751T and TEA1791T 3 3 6 Over temperature protection An accurate external over temperature protection TEA1751T LATCH pin RT2 R26 and C19 is provided in the demo board to protect the flyback transformer against overheating Normally the flyback transformer is the most heat sensitive component Test Conditions The NTC temperature
30. m 1 1 finished with wire 0 3 10 N6 7 9 TEX E 3L 0 3 mm 2 6 1 11 N7 8 10 TEX E 3L 0 3 mm 2 6 1 12 N8 11 8 TEX E 3L 0 3 mm 1 5 3 close winding method UM10391 1 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 01 20 April 2010 29 of 37 NXP Semiconductors U M1 0391 90 Watt notebook adapter with TEA1751T and TEA1791T 7 2 PFC inductor L2 specifications 7 2 4 Inductor L2 specifications Primary inductance 250 uH 10 Core Bobbin RM10 Core material NC 2H Manufacturer Send Power Electronics Co LTD Taiwan ROC Primary Auxilary 9 7 F 12 N2 l N1 Jl N2 l NN E l jELE2 N1 PER rn zl J Bobbin Start Teflon tube Tape 014aab121 Fig 22 PFC inductor L2 schematic Table 15 PFC inductor L2 winding details Layer Pin number Wire type Number Number of turns Remarks order Start Finish of wires Winding MYLAR tape 1 N1 9 7 USTC 30 x 0 1 mm 1 40 1 2 N2 12 1 2 UEW 0 22 mm 2 2 5 3 UM10391 1 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 01 20 April 2010 30 of 37 NXP Semiconductors UM10391 8 PCB layout 90 Watt notebook adapter with TEA1751T and TEA1791T UM10391_1 The SMPS printed circuit board is a single sided board Dimensions are 12
31. n TEA1751T CH4 FBCTRL pin TEA1751T CH4 FBCTRL pin TEA1751T Fig 5 Normal start up at 90 V 60 Hz zA ee ey EE z MCh2 EOD KC IET Al Ch3 7 ME 10 0V amp iCh4 26 Mar 2009 GE 10 0V amp iCh4 2 00V i 26 Mar 2009 10 56 40 i 30 20 11 06 19 001aak789 001aak788 Detail of left side picture Load 4 63 A CH1 VINSENSE pin TEA1751T CH2 VCC pin TEA1751T CH3 FBDRIVER pin TEA1751T CH4 FBCTRL pin TEA1751T UM10391_1 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 01 20 April 2010 10 of 37 NXP Semiconductors U M1 0391 90 Watt notebook adapter with TEA1751T and TEA1791T 3 3 3 2 Short circuit protection Test Conditions The adapter is switched on with no load on the output A short circuit is applied manually to the output at the end of the cable The mains voltage is adopted to obtain the worst case condition Ashort circuit is applied to the output at the end of the cable before startup of the adapter The adapter is switched on with a short circuit at the output The mains voltage is adopted to obtain the worst case condition Remark An output short circuit is defined as an output impedance of less than 0 1 ohm Criteria to pass The unit shall be capable of withstanding a continuous short circuit at the output without damage or overstress of the unit under any input conditions The averag
32. peak reading graph Frequency Correction Reading Emission Limit dBuV Margins dB factor dBuV dBuV No MHz dB QP AV QP AV QP AV QP AV 1 0 20112 0 12 32 67 27 68 32 79 27 80 63 56 53 56 30 77 25 76 2 24 36328 1 50 35 94 30 50 37 44 32 00 60 00 50 00 22 56 18 00 UM10391_1 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 01 20 April 2010 21 of 37 NXP Semiconductors U M1 0391 90 Watt notebook adapter with TEA1751T and TEA1791T 001aak817 100 dBuV 80 1 60 2 40 3 20 0 101 1 10 102 f MHz QP limit AV limit Peak reading anaa on Sa ae The conducted EMI measurement of 230 V neutral is close to 230 V line Fig 17 Conducted EMI 230 V line Table 11 Conducted EMI measurements 230 V line Refer to Figure 17 points 1 2 and 3 on the peak reading graph No Frequency Correction Reading Emission LimitdBuV Margins dB factor dBuV dBuV MHz dB QP AV QP AV QP AV QP AV 0 18906 0 09 38 38 37 05 38 47 37 14 64 508 54 08 25 01 16 94 0 43516 0 20 32 37 24 52 32 57 24 72 5715 47 15 24 58 2243 25 11328 1 14 38 45 32 14 39 59 33 28 60 00 50 00 20 41 16 72 4 2 Immunity against lighting surges Test conditions Combination wave 1 2 50 us open circuit voltage and 8 2
33. ra ree NE T n m eee 100mV 5 Mi10 00s A Chi 4 00mV 26 Mar 2009 39 20 18 23 48 001aak809 c Mains input 132 V 60 Hz Ch1 Vour Tek Stop E i 1 BH ooma M TO 0us A Chi 7 4 00mV 26 Mar 2009 39 20 18 24 21 001aak811 e Mains input 230 V 50 Hz Ch1 Vout Fig 14 Ripple and noise Tek stop chill 26 Mar 2009 39 20 18 23 34 001aak808 b Mains input 115 V 60 Hz Ch1 Voy Tek Stop feu 100mv v M10 0us A Chi FS 4 00mV u 26 Mar 2009 39 20 18 24 05 001aak810 d Mains input 180 V 50 Hz Ch1 Vout Tek Stop t it SU i00mV W Mi6 0us A Ch 4 00mV 26 Mar 2009 39 20 18 24 40 001aak812 f Mains input 264 V 50 Hz Ch1 Vout UM10391 1 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 01 20 April 2010 19 of 37 NXP Semiconductors UM10391 90 Watt notebook adapter with TEA1751T and TEA1791T 3 4 4 Dynamic load response Test Conditions The unit was subjected to a load change from 0 to 100 at a slew rate of 1 A msec The frequency of change was set to give the best readability of the deviation and setting time Remark The voltage was measured at the end of the output cable Criteria to pass The output is not allowed to have an overshoot or undershoot beyond the specified limits 1 V to 0 5 V after a lo
34. rotection The average input power shall be less than 3 W once the over current protection has been triggered Tek stop t Tek Stop Pehi 20 0 V amp cCh2 5 00 V a A Chi f TIE D Chi E 20 0 V jCh2 5 00 V cm 400ms A Chi f 200V amp jch4 20 0V 5j 3 Apr 2009 200V amp jCchd 20 0V 54 3 Apr 2009 10 39 05 10 36 0 001aak798 001aak799 Mains input 90 V 60 Hz lo OCP 8 72 A input power Mains input 264 V 50 Hz lo OCP 9 02 A input 1 26 W power 1 14 W Load before short circuit 0 A Load before short circuit 0 A CH1 VCC pin TEA1751T CH1 VCC pin TEA1751T CH2 FBCTRL pin TEA1751T CH2 FBCTRL pin TEA1751T CH3 Varn flyback Mosfet CHS Vdrn flyback Mosfet CH4 Vout CH4 Vout Fig 10 Output over current protection 3 3 5 Output Over Voltage Protection OVP Test Conditions An output overvoltage was created by applying a short circuit across the opto LED of U2 e An AC input voltage was selected so that the worst case condition occurred There was no load on the output Criteria to pass The output voltage may not exceed 25 V or stabilize between 25 V and the rated voltage UM10391 1 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 01 20 April 2010 13 of 37 NXP Semiconductors UM10391 90 Watt notebook adapter with TEA1751T and TEA1791T At the moment OVP occurs the primary side control
35. sensor glued to the transformer was heated using a heat gun Criteria to pass The IC should latch off the output at a VLATCH trip level of 1 25V No output bounce or hiccup is allowed TY ined idi TERETE SEAMEN Chi 20 0 V Ch2 _ 20 0V 5 M 2 00s A Ch2 f S800mV GE 250V amp ich4 2 00V 5j 2 001aak804 OTP trigger temperature 108 xC Load before short circuit 0 A CH1 Vout CH2 TEA1751T VCC pin CH3 Mains input voltage CH4 TEA1751T LATCH pin Fig 12 External Over Temperature Protection OTP 3 3 7 Fast latch reset A fast latch reset function FLR is implemented to enable latched protection to be reset without discharging the bulk electrolytic capacitor The latch protection will be reset as soon as the voltage on VINSENSE pin drops below 0 75 V and then raised to 0 87 V Test conditions No load at the output UM10391 1 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 01 20 April 2010 15 of 37 NXP Semiconductors UM1 0391 90 Watt notebook adapter with TEA1751T and TEA1791T The test sequence was as follows 1 The latch protection was triggered by an OVP caused by a short circuit across the opto LED 2 The mains input was switched off and the voltage at VINSENSE dropped below 0 75 V 3 The mains input was reinstated and as soon as the voltage at VINSENSE rose above 0 87 V th
36. sitions PFC choke and transformer documentation along with test data and oscilloscope pictures of the most important waveforms The GreenChip III combines the control and drive functions for both the PFC and the flyback stages into a single device The TEA1751T provides complete SMPS control functionality to comply with the IEC61000 3 2 harmonic current emission requirements obtain a significant reduction of components save PCB space and give a cost benefit It also offers extremely low power consumption in no load mode which makes it suitable for the low power consumer markets The special built in green functions allow a high efficiency at all power levels which results in a design that can easily meet all existing and proposed energy efficiency standards such as Code of Conduct Europe Energy Star US California Energy Commission Minimum Energy Performance Standards Australian amp New Zealand and China Energy Conservation Program The GreenChip SR is the only synchronous rectification control IC available that needs no external components for tuning of the timing Used in notebook adapter designs the GreenChip SR offers a wide VCC operation range of 8 5 V to 38 V minimizing the number of external components required and enabling simpler designs In addition the high driver output voltage 10 V makes the GreenChip SR compatible with all brands of MOSfets 001aak826 Fig 1 90 W TEA1751T and TEA1791T demo board UM
37. t notebook adapter with TEA1751T and TEA1791T Tek Stop t Ep Ch4 Rise 12 10ms chi 250V NCh2 20 0V S5 M O 0ms A Chad 13 0V Ch3 500mV sEm 10 0V 3 10 Apr 2009 50 20 17 12 03 001aak784 Mains input 90 V 60 Hz output rise time 12 64 ms Load 4 63 A CH1 mains input CH2 VCC pin TEA1751T CH3 FBSENSE pin TEA1751T soft start Tek Stop I4 Ch4 Rise 12 24ms icy 500V 5 Ch2 20 0 Mi10 0ms A Ch3 500mV AiCh4 10 0 V i 25 Mar 2009 i3 50 20 17 13 55 001aak785 Mains input 264 V 50 Hz output rise time 12 24 ms Load 4 63 A CH1 mains input CH2 VCC pin TEA1751T CH3 FBSENSE pin TEA1751T soft start CH4 Vout CH4 Vout Fig 3 Output rise time at full load start up 3 3 2 Brownout and brownout recovery The voltage on the VINSENSE pin is sensed continuously to prevent the PFC from operating at very low mains input voltages Test Conditions The mains input voltage decreased from 90 V AC down to zero and then increased from zero to 90 V AC The electronic load was set to Constant Current CC mode and Von 0 V The electronic load was set to the maximum output current Criteria to pass The unit shall survive the test without damage and not exceeding specified operating temperature test limits The output voltage remains within the specified regulation limits or switch off No output bounce or hiccup is allowed during switch on or switc
38. tions The electronic load was set to Constant Current CC mode and Von 0 V The electronic load is set to the maximum output current Criteria to pass A normal start up with a smooth and continuous ramp up of the output voltage No output bounce or hiccup is allowed during switch on or switch off There be must be sufficient margin between the FBCTRL level and the 4 5 V time out trigger level to avoid false triggering of the time out protection due to component tolerances UM10391 1 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved User manual Rev 01 20 April 2010 9 of 37 NXP Semiconductors UM10391 90 Watt notebook adapter with TEA1751T and TEA1791T Chi 2 00 V WCh2 20 0V M 1 00s A Ch3 6 40 V Chi 2 00 V WCh2 20 0V M I0 0ms A Ch3 6 40 V Overview picture Load 4 63 A CH1 VINSENSE pin TEA1751T CH2 VCC pin TEA1751T CH3 FBDRIVER pin TEA1751T CH4 FBCTRL pin TEA1751T Normal start up at 264 V 50 Hz Fig 6 GE 10 0V amp iChd 2 00V 5j 26 Mar 2009 iE 10 0V Aich4 2 00V 54 26 Mar 2009 10 56 40 30 20 11 06 19 001aak789 001aak788 Overview picture Detail of left side picture Load 4 63 A Load 4 63 A CH1 VINSENSE pin TEA1751T CH1 VINSENSE pin TEA1751T CH2 VCC pin TEA1751T CH2 VCC pin TEA1751T CH3 FBDRIVER pin TEA1751T CH3 FBDRIVER pi
39. ual Rev 01 20 April 2010 33 of 37 NXP Semiconductors UM10391 90 Watt notebook adapter with TEA1751T and TEA1791T 10 Legal information 10 1 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information 10 2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards
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