Home

FADCTF system - User`s manual (V1.05, 31 July 2002)

1. Titel D 2xADC Date 05 2002 Company HEPHY Author M Pernicka Design S Schmid gt gt 4 Si NI NI H LP Nee mole N g 38 8 gt gt gt gt lk L4 X6 IN E D9 109 E SIN 7 In Ge 18 108 D7 18 107 4129 pEFOUT D6 19 De 31 REFIN DST 2e 105 D4 1D4 24 SI 2 erp Dol 25 JS 2 26 Tu 100M ADC1 D157 101 S Jeer GE me 100N 12 oe HTE a Css DTDTDUTDUUTD E EEECECCE OOOO OO o vie SE BCE 444 Ha E gt ef P Le wi 5 LE HHH Hoe f Moje N 333 gt gt gt B PES IN D9 16 209 IN D8 17 208 D7 18 207 REFOUT D6Mig 208 REFIN D5r28 205 D4 24 2D4 REFP DS 25 a 26 COM ADC2 D157 201 REFN Der o8 220 12 o PDF 33 a Css O00U0U0U0U0 c ee co cc EED ED ES OCS o slow les S 444 oe Ha e oe CLK20 10v 10V La l 3 3V 19 Both identical ADC channels are shown here while the Samtec connector pinout can be found at the bottom The differential analog inputs from the REBO are IN1 and IN2 These inputs are symmetrical to GND and terminated to GND with 50Q each Alternatively this could be changed to a purely differential 100Q termination A common mode has to be introduced to match the ADC inputs which is done with the amplifiers ICA1 and ICA2 respectively Moreover AC coupled test inputs TEST common to both channels and DAC offsets DAC1 and DAC2 are added through the amplifiers ICA3 and ICA4
2. Ext CLK gt INT EXT An IN 4 An OUT lt TTM_ IN OUT PCI_ OUT 2 3 o e HEPHY VIENNA JP MP HS SS O Differential TTL Connection to the TTM system LVDS Test input for PCl Link TTL Start signal output scope trigger TTL Wired or LO monitor TTL Wired or L1 5 monitor NIM Optional clock input 20MHz Switch EXT repeat TTM signals INT use sequencer Analog input terminated with 50Q to be added to An OUT 4 identical analog test outputs RJ45 connector The various modes of operation will be explained below 3 1 External TTM signals Whenever the front panel switch is in the external right position the Sequencer acts as a repeater for the TTM signals described in the following table With the switch in internal left position TTM or internal signals can be selected by a VME register The signal flow is from the TIM to the 37 Sequencer for all signals except BUSY and REV which are propagated in the opposite direction Name Function CLK20 20 MHz system clock ADCCLKS gate for the data taking in transparent mode Start begin of a 128 channel strip data block begin of valid data Stop end of 128 channel strip data block end of valid data not used in the FADCTF system EFT Enables high or disables low Fast Or comparator EVTAGIO 3 4 bit event number BUSY indicates that FADCTF FIFOs are almost full only space for 1 event left
3. input 18 input 19 input 20 Now input 21 input 22 input 23 input 24 Now anARNM ODAN o BR N ONAN SECH Oo RN DDAN input 1 input 2 input 3 input 4 input 5 input 6 input 7 input 8 input 9 input 10 input 11 input 12 hitmap 0 hitmap 1 hitmap 2 hitmap 3 hitmap 4 hitmap 5 lie Strobe input 13 input 14 input 15 input 16 input 18 input 18 input 19 input 20 input 21 input 22 input 23 input 24 yey seddn sindui amp ojeuy corresponds to A IN2 corresponds to A IN3 corresponds to A IN4 corresponds to A IN5 corresponds to A IN6 corresponds to A IN7 jeu 18mol sjndui Boyeuy NIM Optional clock input 20MHz alternative to TTM Sequencer Indicates that a LO trigger track was found Differential ECL Output to the LO trigger width 120ns NIM unused optional LO input from TOF segment NIM Output to the LO trigger width 50ns NIM unused connected to the LO trigger processor unit NIM unused optional simple L1 5 trigger output 12 VME e DB 2xADC DAP2 DB 2xADC wel VME1 A_IN3 gt L DB 2xADC DE A_IN4 DB 2xADC DB 2xADC Bo hitmap1 EJ DAC TIP1 TRP1 hitmap2 Ez DB 2xADC e P2 A IN5 gt DB 2xADC A IN65 CT DB 2xADC DAP DB 2xADC A_IN7 gt
4. 15 Optional Trigger processor for L1 5 Optionally the FADCTF can also use the detected hitmap output to create a L1 5 trigger Each DAP with 4 analog input channels is connected to the L1 5 trigger processor over 8 lines Moreover an interconnection bus of 24 lines is provided to each left and right neighboring modules A simple implementation of the L1 5 processor would be to combine groups of 64 silicon detector strips by OR to one line The decision time in that case is less than 50ns but other combinations are possible as well The number of gates in the TRP1 Altera chip is a hard limit for the implementation The limit of bus lines however could be could be overcome by time multiplexing of the signals if necessary 2 PCI Link The PCI Link provides the connection between the FADCTF and the DAQ PCs One PCI Link card is connected to each 24ADC PRESELDA module through the P3 backplane as shown in the photographs below On the other end 3 PCI cards are hosted by one Linux PC and the connection is made with a 96pin Sony connector and differential LVDS signals 33 The outer dimensions of the ADC daughter board including the front panel are approximately 100 x 120 x 20 mm The signals coming from the FADCTF module have open collector outputs and are terminated with 3300 on the PCI Link module and the signals from this module to the FADCTF are also open collector outputs and are terminated there The signals between t
5. 7 LI DB 2xADC DAP7 CLK TN O DB 2xADC Lo e LOTW c O 6 P3 LOF fid LOC L1P5 Each analog input connector RJ45 type on the front panel contains 4 twisted pair differential signals from top to bottom as shown on the picture above pin1 IN1 pine IN1 pin3 IN2 which are digitized on 2 DB 2xADC daughter boards with 2 channels each These 4 channels 10 bit each are then sent to a DAP unit which has a 4 event FIFO Moreover it processes the strip data for the L1 5 trigger provided that a suitable pedestal threshold pattern has been stored in the DAP internal memory before The analog data is digitized at 20MHz but only every 4 value synchronized to the start signal is taken since the VA1TA output is 5MHz Thus the zero suppressed strip data of 4 input channels is multiplexed and sent to the L1 5 trigger on the hitmap RJ45 front panel connectors The hitmap1 plug contains 4 twisted pairs each carrying the zero suppressed data of 4x4 16 channels processed from A IN2 A INS hitmap1 pin h1 pin2 h1 pin3 h2 while hitmap2 carries 2x4 8 channels A ING A IN7 on pins 1 4 plus a 20 MHz strobe signal pair on pins 7 and 8 The Fast Or signals from the comparators on the DB 2xADC daughter boards are sent to the LOP1 2 units which searches for valid trigger patterns and signals such an LO condition on both the LOX NIM and the LOTW differential ECL outputs This signal is shaped with a width of
6. Vee cM ele PD ES 21 ger EAA WA E EE 2 1 1 2 4 1 22 pin Samtec socket sssennnnnnnnnunnnnnnnnnnnnnnzu 21 1 2 4 2 40 pin Samtec socket ssennnnnnnnnunnnnnnnnnnnnnnnu 22 Let COMVerPSIO c e enr amor ee 1 2 5 1 AM EE Te dE 23 T8652 E e EN 23 1 2 5 3 DAC O ADE EE 23 7 2 59 4 E LOMPAarator E 23 e e de ae ae a hausse 23 T280 5 7 IM 25 ADD E 23 1 2 6 2 TESI o Te EE 25 1 2 6 3 E E dax a PE ki i A 26 1 2 6 4 ADC Step Response ssenennnnunnnnnnnnnnnnnnnnnnnnnzu 27 1 3 Trigger processor for LO 29 Toce dr Wb uOOPDGOLBIGQOEIDCIS ass ess none AL 31 sse LO Outer eeh eg 32 Seb A itmap DUEOEUG S sra i Cte FR eat LACE CERA 32 1 5 Optional Trigger processor for L1 5 33 Se lei D BR Ve Es rincer Ke 3 TTM Sequencer V2 aU VME 35 3 1 External TIM signalSsesic 245 0e4 eras EE 37 c e Internal elt e SEENEN d 38 3 2 1 Sequencer operation 38 3 2 2 Transparent mode simulation 39 3 3 Input Output sSi igNalS i ii ie a dos ORE EN 39 ue qe Analog DUUDDEIO o rop e d i Rie Pe C de ER c cda ag here SUI I pEb coe te owes nebo Mac Qo abe ono cd 40 3 3 3 Scope trigger OLIEDUM rv vore 3x3 Iota eno o oda 40 3 3 4 LO and L1 5 Trigger oububDUutbs sia kal alba ri ik 40 cue ceu BOMVERbET G Edge eebe E 40 4 VME bus systems crrn nnn nnnm 40 PV EL EE SSSR dei i Sn eti eit sd 41 da mBpBegconreugbelasuassatbr rs doe Xx ebe Eechen 41 d FES CORMEEEON iii ai ved vx aa b l
7. and must be read before further events can be stored REJ L1 5 trigger accept signal data should be transferred to final memory and read out REV unused The Sequencer is transparent to these signals between TTM and P2 backplane with one exceptions The stop signal is not used The window of the ADC clock on the Pe backplane is opened by a start signal and closed again after 128 cycles In transparent mode the ADCCLKS5 gate is forwarded to the Pe bus and synchronized to 200ns or 50ns multiples in the TIP1 of the FADCTF die Internal signals This operation requires the front panel switch in internal left position and the internal mode enabled bv VME see the programmer s manual for VME details Either the 20MHz internal oscillator or the front panel input can be selected as a clock source while the latter can be varied to check out the limits 3 2 1 Sequencer operation With this facility a complete module and crate test is possible without any external components Different signals and event types can be produced in this mode EFT is enabled in idle mode Once the STA bit is set by VME a TTM signal cycle is initiated with a time unit TU 64 200ns 12 8us assuming a 20MHz system clock After TU e clock cycles a test pulse is issued onto the P2 backplane and thus to all FADCTF modules which emulates the Fast Or signal the Test Procedures section below informs on how to enable disable the Fast Or detection for individual c
8. hence known as Fast Or which is sent to the FADCTF After the peaking time T which is in the order of 600ns a Hold signal has to be applied to the chip such that the peak value of the slow shaping curve is stored in the chip internal sample hold circuit This condition is indicated by the dashed curve in the top waveform When shift in and clock signals are presented to the chip it writes out the serialized strip data in analog form 10 Depending on which side of the detector is read out signal amplitudes may be positive or negative w r t the pedestal but the Fast Or is always positive Note that the Fast Or is asynchronous and thus can occur at any time unlike the synchronous strip data which are later sent on the same line provided that shift in and clock signals are received by the VATTA The REBO sends differential signals to the FADC system which are terminated with 2x50Q against GND there The expected levels at the input of the FADCTF are shown below Vinai Vina in 1V 1V max Fast Or Pulse Strip data 22V span always positive pos neg The width of the Fast Or pulse is approximately 100 130ns with a jitter span of up to 7Ons across the inputs while the strip data is read out at SMHz corresponding to a period of 2O00ns For test purposes single channels can be displayed in transparent mode where the full shaped waveform is presented on the analog lines Modules 1 FADCTF These boards
9. with all 4 VATTA chips have to be considered in the rz case In the ro case where strips run along the z axis not all 4 VA1TA chips need to be transferred in all cases since those which are not contained within the segment may be omitted For instance only the leftmost quarter of the innermost red module in the following graph actually belongs to the blue segment thus there is no need to consider the rest of that module eg Interconnections definitive iem gt optional md left ee 30 There are definitively interconnections within such a group of 3 segments modules Basically the 6 triplets are independent on each other and symmetric in both r and rz cases but the possibility of interconnection between neighboring triplets is foreseen in the hardware as indicated by the dashed arrows above Including this feature could result in an increased LO noise trigger rate that would be disadvantageous The final implementation will be a tradeoff between efficiency and noise contribution The Fast Or trigger patterns will be implemented within the LOP1 and LOP2 if required FPGAs for both r and rz directions Simulations have been done in both cases to get the probabilities for all possible combinations that will be implemented inside the IOP1 2 units Therefore six different programs are need
10. Output signals 3 3 1 Analog output A 10 bit DAC of which only the 7 least significant bits are used can be directly set by VME Its output is connected to four identical amplifiers whose outputs are routed to an RJ45 connector which is pin compatible to 39 the FADCTF inputs Thus any group of 4 channels can be tested by connecting this analog output to any FADCTF input There is no synchronized memory buffer between VME and DAC so it should only be used for DC measurements since the timing is not defined otherwise Alternatively an inverse ramp with DAC values from 127 0 can be automatically issued during the sequence which has a fixed timing wrt the start signal as shown in the graph above The ADCs will measure the sum of the test pulse and the analog output Moreover there is an analog input on the front panel LEMO connector terminated with 500 which is added to the DAC output and commonly distributed to the 4 outputs 3 3 2 PCI Link input The 32 bit data on the PCl link is synchronously filled into two parallel 16k word FIFOs The handshake procedure is controlled by VME commands which can read the state of XREQUEST and set XEANBLE and XREADY In idle condition both XENABLE and XREADY are high Upon reception of an XREQUEST one has to set XENABLE and XREADY low and the Sequencer waits for XVALID to indicate valid data which are strobed into the FIFOs using the XCLOCK The parallel FIFOs can then be read out
11. are the core of the FADC system containing a lot of logic functionality within several Altera FPGAs Moreover 12 DB 2xADC daughter boards digitize the analog signals and search for Fast Or pulses 4 1 Mother board 24ADC PRESELDA The front panel layout and the side view of the module are shown below 11 VME A IN2 INP 1 4 gt A IN3 INP 5 8 A IN4 INP 9 12 hitmap1 30UT L1 5 hitmap2 3OUT L1 5 A IN5 INP 13 16 A IN6 INP 17 20 gt A IN7 INP 21 24 gt CLK TN gt LO LOTW e LOF gt LOX LOC L1P5 al VME DISPLAY lu HEPHY VIENNA JP MP HS SS 30UT L1 5 L d 30UT L1 5 T ja CLK Indicates VME bus activity input 1 input 2 input 3 input 4 NOW input 5 input 6 input 7 input 8 Nowa input 9 input 10 input 11 Input 12 Nowa hitmap 0 hitmap 1 hitmap 2 hitmap 3 NOW hitmap 4 hitmap 5 n c Strobe Now input 13 input 14 input 15 input 16 NOW input 17
12. directly shows the shaper output of one single strip channel While the ADC always runs at 20MHz only every fourth digitized value is stored thus SMHz VATTA output rate in normal operation Optionally the readout speed can be set to the full 20MHz sampling which can be useful in transparent mode as illustrated below 45 Test of the 24 single transparent channels of a 24 VA1TAs ASL LEEFER Eck NS EME EE ELT Width 2 3 clocks 7 200ns Width 17 19 clocks 4 x 200ns ADCCLK5 Single channel memory Single channel memory 1 il lii s 2 1 2 3 4 input gt 1 n 128 200 ns or 50 ns 24 EZ steps After 128 starts the data block will After 128 4 starts 200ns sampling be transferred the data block will be transferred 1 12 128 words 32 bit Final memory Final memory 3 How to test the hybrid with VA1TA REBO and FADCTF module c General It is possible to test every input channel of the VA1TA chip by switching the chip into transparent mode and selecting one of the 128 inputs In this mode the shaper output of the selected channel is directly presented at the output without the subsequent sample hold and multiplexing stages that are operative in normal mode Moreover a test signal AC coupled step pulse is sent to the VA1TA input simulating a particle signal The VA1TA preamp shaper convert this current spike into a CR RC shaping curve with an adjustable peaking time of approximately 500ns The VA1TA transparent mode out
13. over the VME bus 3 3 3 Scope trigger output The start signal is available on a front panel connector LEMO style to be used as a scope trigger The level is TTL with a 5000 serial resistor such that it can be terminated with 50Q at the cost of level reduction 3 3 4 LO and L1 5 Trigger outputs Each FADCTF module can produce LO and L1 5 optional trigger signals which are sent to the P2 backplane with open collector drivers such that the bus signals are the wired or result of all module signals The status of these wired or LO and L1 5 signals can be queried by VME or monitored on two front panel outputs LEMO style which again provide TTL levels protected by serial resistors 3 4 12 V converters The Sequencer board also provides two DC DC converters to generate 12V which is needed by the Sparc interface These voltages are put onto the dedicated bus lines Obviously the Sequencer board must not be plugged to a VME crate that already supplies the 12V by itself 4 VME bus systems The system uses the VME connectors P1 P2 and P3 with 5 32 contacts each All standard pin assignments are respected but several user defined signals are added Moreover there are some extra power support pins Therefore the crate should be only used for modules of the FADCTF system 40 P2 and P3 use custom backplanes which are plugged onto the rear of the crate All three buses will be described in the following sections 4 1 P1 connect
14. word 16 gt VME X DAP Q up 15 14 13 12 11 10 9 8 7 6 5 44 312 0 STOSTA Channel 10 bit ADC data D down 15 14 13 12 11 10 9 8 716 5 4 3 2 0 STOSTA Event 10 bit ADC data loword 115 14 13 12 11 110 9 8 7 6 5 4 312 0 STOSTA Event 10 bit ADC data up hiword 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 STOSTA Channel 10 bit ADC data down B 31 30 29 28 27 26 25 24 23 22 21120 19 1811711615 14 13 12 11 00 9 8 7161514312 0 PAR 0 Event 10 bit ADC data down STOSTA Channel 4 10 bit ADC data up 14 The communication with the VME bus is handled by the VME1 bridge which communicates to all logic units on the FADCTF board Moreover the logic units can be reprogrammed over VME The 20K Altera FPGAs are loaded from external EEPROMs at startup or upon request which can be written to via the VMET unit The same is true for the other FPGAs with internal flash memories This is particularly interesting for fast changes in the LO trigger patterns which are contained within the LOP1 2 devices All logic devices are Altera FPGAs The following table gives a summary of the functionality of each unit Name Altera P N Function DAPx EP20K100E ADC readout 4 event FIFO zero suppression for the L1 5 hitmap data Fast Or counter TIP 1 EPM7258B Clock timing control distribution THP1 EPM7512B optional simple L 1 5 trigger processor DACPR1 EP2OK3OOE Final memory LOPx EPM75128B LO processor LOP2 i
15. 3ADC mV BELLE DAUGHTERBOARD TEST1 loj x MIN MAX MAX MIN AVERAGE SIGMA Q Q DACI DAC4 T AUTOSCALE 495 772 277 1626 86 131 33 BIT Histogram SE TEST Ext v4 COMP Le 200 200 150 150 100 IB 100 o o ler Clem 0 2 2 80 100 120 140 160 180 200 220 2 1 2 6 3 Comparator The comparator behavior was simulated with SPICE Please note that the V lines have a common mode voltage of 1 15V i e they are not symmetric around zero but both reside at that voltage when there is zero input Moreover the comparator limits are quite sensitive to its output which is TTL with measured levels of O 36V low and 3 64V high The plot below shows a triangular differential input signal V with both positive and negative parts and the corresponding comparator output signal Vous Date Time run 05 21 02 17 47 54 Temperature 27 0 A db_2xadc_1 dat active 600mv eege derre degen pS 400mV ER PRE le cols RE a SR A oles Se ze 200mV 0 078s 0 200s 0 400 0 600s 0 800s 1 000s 1 200s 1 400s S n V SUM1 OUT SUM2 O0UT o V LIMIT2 OUT Time Al 182 628m 292 045m A2 1 4230 246 560m DIFF A 1 2403 45 485m Date May 21 2002 Page 1 Time 17 49 10 The simulated On Off limits referred to V are approximately 292 and 247mV The hysteresis of 45mV corresponds to 22 ADC counts or an input span V gi o
16. 4H Jeouenbes Nd9 eds VME Crate 11 12 13 14 15 16 17 18 19 20 21 10 2 6U 1 Slots 9U FRONT VIEW UOJ 9U units FADCTF 6U units Sparc CPU Sequencer Power Supply P2 back plane ES back plane ADC_PCI Link SIDE VIEW Each FADCTF board will be mechanically coded such that it can only be inserted in either L M or R positions e g L modules are allowed in slots 4 7 10 13 16 19 This is done for reasons of the LO trigger The ADC PCI Link boards are located on the back side of the crate In order to provide the control signals to the P2 backplane the Sequencer board must be installed in slot 3 or higher IMPORTANT The VME crate MUST be switched off whenever any module is inserted or removed since the Altera VME protocol FPGA may be damaged if hot plugged We decline any responsibility for the consequences of such action Power Consumption The 9U VME crates can be operated with both European and US Japanese power as shown below AC Input Range Voltage 92 265V Current 16A max Frequency 47 63Hz The current consumption of one fully equipped crate at the low voltage side is shown in the table below Rail V Current A SNE 12 od 16 3 3 60 5 0 33 5 0 19 Power 520W Neighborhood The FADC system is embedded within the SVD readout system and communicates w
17. 5O0ns NIM or 120ns ECL Moreover the LO LED flashes For proper functionality the LO processor also needs Fast Or signals from neighboring FADCTF modules which correspond to neighboring detector modules This is achieved by 16 input and 16 output lines on the P3 13 connector 8 8 lines to each neighbor module where a custom designed backplane provides the interconnections Clock timing and control signals are provided by the TTM system and sent to a custom P2 backplane via the Sequencer board The TIP1 unit distributes these signals to the other logic blocks on the FADCTF board Two control busses supply the upper and lower DAPs The DACPR1 unit contains the final memory to which the event data is transferred This device contains a FIFO for 2 events plus a small headroom which are pushed out to the PCI Link boards through the P3 connector D 16 VME 4 DAP 16 VME 4 gt DAP 16 VME D up VME 4 DAP e 16 16 gt Final i 32 Memor Eu PCI 46 y ac gt VME 4 16 gt DAP 16 2 m gt VME D down 4 DAP VME PCI lo hi
18. Altera where they are counted On one line simply the number of triggers is counted whereas on the other line the LO decision is AND gated with the VME system clock running at 16MHz such that several counts appear there depending on the width of the LO trigger as shown in the drawing below 1 2 Straight LO output 2 counts VME system clock 16MHz Clock gated LO output 6 counts The average LO width can be deducted from the ratio of the two counters Together with the individual Fast Or counters in the DAPs and some statistics the randomness of the Fast Or triggers can be calculated 1 4 Hitmap output The serial hitmap output is presented at a frequency of 20MHz since the zero suppressed and digitized strip data of a full module 4 VA1TA chips is 32 multiplexed there The data is presented in the non return to zero change on ones NRZ1 code which is characterized by the following translation e D same output state as before e 1 change in output state e g O to 1 if previous state was 0 In other words a data 1 is characterized by a transition while data O does not change the current state The data are sent out in differential LV TTL O 3 3 1V including a strobe pair Data 0 1001 0 1 1 1 0nothing return t transitom II to zero Strobe UUU II
19. FTO P2 TOF P2 TTM Seg Sequencer FADCTF FADCTF FADCTF Description Gate for data taking in external test mode 20MHZ system clock Start signal for data taking High Enable Fast Or comparators Low Disable Event number Accept signal from L1 5 trigger Test pulse Wired or of all L1 5 trigger outputs optional Wired or of all LO trigger outputs Wired or of all TOF trigger outputs currently unused The voltage support pins for 2 5 5 5 1 8 and 3 3V were only used for the first version of the Sequencer board and thus are obsolete now VME Comnector 16 pin P2 42 4 3 P3 connector The P3 connector is almost fully user defined and again has a custom backplane plugged onto the rear side which connects the PCI Link modules and provides the interconnection between neighboring FADCTF modules Row B is used to transfer the 32 bit data word to the PCI Link module with the control lines con C25 32 The power supply for the PCI Link is provided on C20 5V and C24 4 3 5V C17 19 21 and 23 are GND Rows C and A are used to transmit or receive the Fast Or LO information fr
20. Kn V e Di i EY c ry Zell SE s nm ki T Tx ed ds H as 3 LI no TT VIT umen ri T f 2 dr E Ww AA s co MN j E 3 zt aerga ER S av 2 Zar feat zar taje saig bs id TUE pep bh SIE Wr LI cK Ps iiu LI TE pt pes H a Sie nili T helical sl jr x A chu FADCTF system Belle SVD 2 0 readout BE S BELLE HEPHYVIENNA User s Manual V1 05 31 July 2002 DISCLAIMER The FADCTF is a complex electronic system which can be damaged if handled improperly In particular the following guidelines must be respected by the operator We decline any responsibility for errors damage or injury resulting from such misuse e Crate and modules belong together Do not use the VME modules FADCTF Sequencer PCI Link in a VME crate other than the one provided with the system The user defined V1 and V2 rails are used to supply special voltages to the FADCTF modules while the Sequencer board provides 12V which is required by the Sparc interface Moreover the FADCTF modules are mechanically coded with the corresponding counterparts in the crate e Always power off to change modules Never remove or insert a VME module of the system when the crate power is on Ensure that each module is fully inserted needs some force The VME interface Altera EPM7256S 5V core is not specified for hot swapping It can take damage by contention between
21. acting as a Fast Or see below for details Then EFT is turned off and a start signal is transmitted Again a short test pulse is created simulating a hit in two subsequent strip channels See below for details on how to generate arbitrary hit patterns This test procedure has a well defined timing and can be executed repeatedly 1 1 Fast Or A fast digital test pulse originating from the Sequencer is received by the mother board which is commonly forwarded to all daughter board inputs All 24 DAC settings can be accessed in order to individually shift the baseline of each channel such that a Fast Or is only detected by the comparator if the Signal is above a certain threshold Thus by switching the DAC settings to a very low value the test pulse above baseline will not reach the comparator threshold and no Fast Or is detected on that particular channel By this method any arbitrary Fast Or pattern can be generated by setting a normal DAC level and thus baseline to channels which shall fire and a low DAC level to the ones which shall be quiet Please note that a continuous Fast Or resulting from a baseline setting above the comparator threshold is not accepted by the subsequent logic 1 2 Strip data The Fast Or on the analog input is followed by zero input no signal will be represented by a central ADC value around 512 counts with a normal DAC setting around 127 for the strip data Any arbitrary zero suppressed hitmap output can be
22. crate slots will be correspondingly 31 coded in groups of 3 For example the left rz modules can only be inserted in slots 4 7 10 13 16 19 of the proper crate However the correct setting of the VME base address remains the crucial item In order to make this easier we propose to use the slot number for the A24 A31 bits of the module We will provide a list showing the correct associations between slot number mechanical coding and VME addresses and attach this list as a label onto every FADCTF module The loading of the Trigger Processor firmware will be restricted to the proper VME address i e it is not possible to accidentally program a module in a left rz position with middle or right firmware provided that the VME address is correct There are 2 groups if I O pins with 8 lines each Depending on the module type one of those will be declared as input the other as an output by VME commands This is done with two dedicated signal lines enable up and enable down from the VME protocol unit to the Trigger Processor With all of these protections no accidents should happen provided that the VME address is set correctly corresponding to the slot number and the mechanical coding 7 3 2 LO counter The LO Trigger Processor is asynchronous it just connects all Fast Or inputs in the proper way using AND and OR gates The LO trigger decisions are sent on two lines from the Trigger Processor to the VME protocol
23. e delay between clock and data can be adjusted with a jumper in three steps resulting in 32 37 or 42ns delay to the clock line wrt the data The clock must be symmetrical 50 duty cycle otherwise the delay between data and clock will be different because the inverted clock is used there 3 TTM Sequencer V2 GU VME Basically the task of the Sequencer is to distribute the clock timing and control signals from the TTM to the FADCTF modules via the P2 backplane However the Sequencer board version 2 has some additional features For test purposes in a standalone configuration without a TTM system it can generate the relevant TTM signals clock start EFT Event Number ADC clock and a test pulse on its own Moreover it can be used to generate common signals on 4 channels to be plugged into one particular input of the FADCTF modules Finally one PCl Link output can be plugged into the Sequencer to be read back via VME There are TTL monitoring outputs which indicate the wired or LO and optional L1 5 signals over all FADCTF modules in the crate These two signals and the state of the wired or BUSY signal can be read by VME The mechanical dimensions of the TTM Sequencer are that of a standard 6U VME board The photograph below shows the module 39 a 7 The front panel of the Sequencer is shown below S Hal DA m LI Hi I k 4 H L 36 TTM IN OUT 4 PCI OUT SYNC lt LO L1 5
24. ed one each for left middle and right modules in both ro and rz variants The trigger simulation including a detailed description and online software is available at http www nanuk at cern index php project BELLE trigger 1 3 1 Interconnections Maybe the most critical part of the system is the interconnection between left middle and right modules on the custom P3 backplane Every trigger processor has 8 inputs and 8 outputs that are used by the adjacent neighbor modules within a segment as shown in the picture below 8 CO dco 00 dco dco 7 0 Due to the straight layout of the P3 backplane the hardware makes no difference between inputs and outputs The direction of the data flow is only defined by the type of the corresponding Altera pins Thus it is possible to accidentally connect two outputs by incorrect Altera programming or wrong module positioning which results in overheating and successive destruction of both FPGAs involved without any indication of that condition to the outside world Therefore some protection mechanisms are foreseen to prevent such an accident The VME crates will have mechanical coding of slots such that each module can only be inserted in the proper place One mechanical code will be assigned to each of the 6 different FADCTF module types left middle and right for both r and rz variants The
25. ential subsequent readout phase The delay between particle crossing a silicon detector and Hold signal arriving at the VA1TA chips must match its shaping time As soon as the Hold is asserted a snapshot of the detector signals is stored in the sample hold circuits inside the VATTA chips Thus some time is available for a more sophisticated trigger decision by the L1 system which is fed by other subdetectors and possibly the LO information of the SVD as well In case of rejection EFT is reset and the system is back in idle state An L1 trigger enables the shift in and clock signals required for the VA1TA readout and at the same time communicates this condition to the FADC After reception of start signal and event number which are distributed via the TTM system and the Sequencer board the FADC digitizes and stores the strip data arriving on the analog inputs A IN in an internal FIFO which can buffer up to 4 events including an event and channel O 11 number and start stop bits 16 bits in total Moreover the strip data are processed and passed on to the L1 5 trigger already during reception This operation requires a threshold value for each strip which must have been stored in an internal memory before This threshold basically consists of the pedestal value plus a few times the channel noise and is compared to the current data yielding a digital hit map This coarse hit map is immediately sent to the L 1 5 trigger which searches for
26. evels are TTL 0 3 3 5v Supply for amplifiers and comparators Analog supply for ADCs Supply for amplifiers and comparators System ground analog 1 2 4 2 40 pin Samtec socket The table below shows the pinout of the 40 pin Samtec connector which mainly delivers digital signals Name Pin 1DO 1D9 hoon 1E eDO 2D9 27 36 CLK1 Tv CLK2 23 DAC 18 DAC2 24 EFT 19 3 3V 20 22 GND d d T9 16 21 25 26 37 40 Description Two parallel digitized 10 bit busses Output levels are LV TTL 0 3 3 1V Note that even and odd pins are swapped wrt to the bit order e g 1D0 6 1D1 5 1D2 8 Independent clocks for both channels Input levels are LV TTL 0 3 3 1V Analog offsets for both channels to optimize the ADC range Input range 538mV input span corresponds to full ADC range 1024 Offset 442mV input corresponds to central ADC 512 IN OV and TEST OV Enables Fast Or detection if EFT High Input levels are TTL Digital supply for ADCs System ground digital 1 2 5 Conversion Three different types of input affect the ADC reading e IN differential e TEST differential e DAC single 22 The ADC offset voltage at zero differential input voltages can be set by the DAC value Since the offset depends on the DAC setting only a slope will be given for IN and TEST signals Moreover the comparator threshold values will be stated See the block diagram in section O for the definition of d
27. f 45mV The measured values are in good agreement with the 26 simulation results 23 ADC counts The scope screenshot in section 1 2 6 1 shows Mou in green 1 2 6 4 ADC Step Response On their way towards the ADC the input signals are subjected to two RC low pass filters The first RC stage is located in the feedback of ICA1 R 470Q C 10pF T 4 7ns on each polarity The second is directly in front of the ADC input and consists of a series resistor plus the discrete capacitor between the ADC inputs in parallel to the parasitic capacitance of the protection diodes which is specified to be less than 10pF at 1V reverse voltage Thus we have R 150Q C 21pF t 3 15ns in a single ended equivalent circuit diagram The calculated step response assuming an ideal input step function is shown below ADC filter response dual stage RC low pass 0 9 4 27ns 1 deviation filter time constants T1 4 7ns 38ns 0 19 deviation T2 3 15ns 0 8 0 7 4 0 6 4 input 0 5 4 output 0 4 4 relative amplitude 10 0 10 20 30 40 50 60 70 80 90 100 time ns The VA1TA strip data is delivered with a period of 200 ns Thus 4 samples are taken by the ADC for each strip data but only the last one at a distance of approximately 170 180 ns from the edge is of interest and will be processed The scope screenshots below show a step function at the input after the first filter stage and at the ADC input Positive and
28. hannels After 3 TU EFT is disabled and a start signal is created After one more TU another test pulse is sent out thus representing a hit in strips 64 and 65 counting from zero Finally 38 after two more TU EFT is set high again and a L1 5 accept signal is created only if the 1 5 bit is set by VME If the STO bit is set the cycle is finished otherwise it starts over in a loop The timing and signals are illustrated below VME stop VME start effective time Ap 1 2 4 4 5 6 n unit 64xCLK 41 Fast Or Signal on strips 64 65 Test pulse EE o GSGEAR EFT Start analog read L1 5 Event number _ D Analog output Analog data acquisition 3 2 2 Transparent mode simulation In order to test the ADCCLKS synchronization in the TIP1 of the FADCTF the Sequencer can generate ADCCLKS gate signals of variable length Such a gate is issued by a VME write command to N START The first 4 N START commands generate a gate of only 200ns width thus representing one 5 MHz or four 20 MHz samples depending on the sampling speed set on the FADCTF The next 4 N STARTs result in and ADC clock window of 400ns width followed by GOOns 800ns and so on Eventually the DAP FIFO buffer is filled and provided that the FADCTF is set to test mode automatically transferred to the final memory where it can be read out The gate length count of the Sequencer can be reset to the initial state by writing to N RESET 3 3 Input
29. he PCI Link and the PCI card are differential LVDS Incoming signals are terminated differentially with 1000 The table below explains the signals between PCI Link module and the PCI card in the Linux PC Name XREQUEST XVALID XCLOCK XOCLK XDIR XPRV XENABLE XREADY Direction FADCTF l PC FADCTF l PC FADCTF l PC FADCTF l PC PC l FADCTF Function Goes low when the FADCTF wants to transfer 32 bit data to the PC i e data is to be read out from the Final Memory Goes low when data are transferred during the falling transition of the corresponding clock pulse is omitted for timing reasons The final data transfer is determined with XVALID low followed by a data word and then a clock Same clock as used on the FADCTF modules 20MHZ It would be possible to change to 10MHz untested Transmitted but unused Must both be low when a data transfer to the PC is possible 34 As soon as data is available in the final memory FIFO not empty the XREQUEST signal is sent out When the PC is ready to receive data both XENABLE and XREADY go low and the PCI Link can begin to send data The JOMHz system clock is sent out on XCLOCK all the time except for one cycle which is interleaved due to timing specifications while XVALID Low indicates valid data to be received on the XDATA lines After the transfer is finished XVALID goes high to indicate idle state XOCLK XDIR and XPRV are unused Th
30. ifferential and single ended voltage inputs The following relations are measured on one typical daughter board but obviously do not exactly match the nominal values 7 2 5 1 IN ADC The input voltage Vna is measured in terminated state between the differential inputs Vu a Vu S Vu AV un MV 2 026 AADC AADC 0 493 AV are MV 1 2 5 2 TEST ADC The test voltage Vs is measured between the differential inputs Please note that these inputs are AC coupled VIEST am Vase d Maer Ae an MV 23 34 AADC AADC 0 043 AVsegr ar MV 1 2 5 3 DAC c ADC The DAC voltage Vrac is measured towards GND Please note that these equations below are obtained with V gig Vies 44 OV Vy mV 173 0 53 ADC ADC 328 1 90 V mV 7 2 5 4 Comparator The comparator threshold values are given in terms of ADC output values Compon 618 ADC Compo 995 ADC Thus the hysteresis corresponds to a differential input voltage difference of AV naire 47 mV 1 2 6 Signals The scope screenshots shown here refer to the probe test points shown in the schematics in section 1 2 1 7 2 6 7 IN ADC 23 Tek Sto p 200mV SE 200mV M 200ns A Chi X 2 44 V Math 200mv 200ns i8 6 800 This is an arbitrary electrical input blue V cyan Vy red Vinar measured on the connector The peak to peak amplitude of Vy is approximately 1368mV It translates to a V voltage ADC input before low pass fil
31. ime a GNDIO TE L Ce Lk e SL l DI om Hi e o ER Ka O Oo ON calme iit EL gn A L om 3 bet L uino 1 en di oH e Jn IMAX144477 20 HUMAN 1444 8 X Dmm Date 02 2002 V5 Company HEPHY Vienna M Pernicka S Schmid 1 2 3 Mechanics The outer dimensions of the ADC daughter board including components are approximately 70 x 20 x 6 mm The only mechanical connection are two Samtec sockets with 22 and 40 pins respectively All components except the connectors and a few capacitors are located on the top side such that the device can be easily probed and debugged while in operation 1 2 4 Pinout 1 2 4 1 22 pin Samtec socket The following table describes the pinout of the 22 pin Samtec connector which carries mainly analog signals Name INT IN1 IN2 IN2 TEST Pin 19 21 Description Two differential analog input channels from the front end Termination is 50Q to GND for each input by default but can be changed to 1000 differentially Input range 2 075V differential input span corresponds to full ADC range 1024 The offset can be set by DAC Test input which is added to both regular inputs 21 TEST 15 CMP1 g CMP2 13 5V 6 18 3 3V 2 22 5V 10 14 GND 4 5 8 11 12 16 17 20 Input range 6 6V differential input span corresponds to 277 ADC counts Fast Or detect Requires EFT High for operation Output l
32. ith several parts The regular data flow should be illustrated by the block diagram below This figure is simplified and shows only parts which are relevant for the data flow with the FADC system The description of the data flow is very coarse and lacks a lot of details as well since it is only meant as a general introduction to the FADC functionality DAQ Control Data Si FADC PU TTM bi Busy gt SEQ VA1TA Y EFT j I j Fast Or Analog REBO A IN KK 30m Start EvNr Control Data L1 5 al a LO hitmap Shift_in Hold Information Busy Clock from other i subdetectors y y YY TRIGGER final final final LO L1 L1 5 30m Let us assume that there are no triggers or data transfers are pending In this idle condition particles corssing the silicon detectors generate Fast Or signals in the VA1TA front end chips which are sent to the FADC via the HEBO MAMBO system Only a subset of all possible Fast Or combinations represent valid particle tracks The FADC constantly watches out for such combinations and asserts an LO trigger if detecting a track This information when in coincidence with trigger information from other subdetectors is used to generate a Hold signal for the VA1TA chips At the same time EFT toggles to turn off the Fast Or detection during the pot
33. l di 43 VME communication ee un wv Se Test procedures ssssssmmmmnmmnnnunnnnnnn Bee 1 Internal tests wsseeeeenen neem 183 lil FASO E YR VE aco den eus a du 44 le USERID eeu a eet a Que ee eee entres 44 TL Sequencer ee e REENEN 45 e External tests Lunnnnnnanzumunnunununnununnun AD 2 1 VAT transparent Mode ek 45 3 How to test the hybrid with VATTA REBO and FADCTF module 46 chos Series ems vb atra a P C dde ui 46 Se Methodi eria ones dd fide E Ke 46 4 Secreenshots Lsnunnnzannamunmanzunnnnunnunnununu GA 4 1 Standard internal testi ig ebe ANEN bin 47 4 2 Sequencer DAC EECHER a iii a OC da Se 48 4 3 Transparent mode simulation 48 Abstract This is a general description of the modules of the FACD system A separate manual is dedicated to the VME connectivity of the system Additional information for the expert such as electric schematics the logic circuits inside the Altera units along with bus systems timing trigger simulation etc are provided in a separate folder but are not contained herein Contact The mother board is designed built and maintained by Institute of High Energy Physics Austrian Academy of Sciences Nikolsdorfergasse 18 A 1050 Vienna Austria Phone 443 1 5447328 0 Fax 443 1 5447328 54 Overview Introduction The FADC system receives the analog output data of the VA1TA readout chip via the REBO chain and digitizes them finds tracks on a seg
34. logic levels and power supply during plugging of the module or in case of bad contact e Double check the VME base addresses It is extremely important that each FADCTF module has the correct VME base address set Altera programming and I O interfacing to neighboring modules as used by the LO trigger processor rely on the correct VME base address setting which corresponds to the mechanical coding If the address is wrong and outputs of two modules are connected both modules will be damaged by overheating e Do not use the JTAG feature Programming Altera devices on the FADCTF modules is for experts only All Altera devices except for the VME protocol interface can be programmed by the JTAG bus that is accessible by VME Obviously much harm can be done by improper use of this feature The worst case is to blow up all Altera devices on the board Table of Contents Abstract LR 5 Contact LR 5 Overview BENH NHNNMNEENESNMENSENENENSESFSNESN ENENSFNENS SSNSESNSESNSESNEENSF NESN NENSHNESNEHN E Introduction osc Sri assises osier 5 Modules of the system re rrr nnn 5 Power Consumption c reor nnn 7 Neighborhood tai ia ka iii a RE REEYWERR ES EE RE RM ERAN EE EK 7 V Swing WII Le ss ssxukunswswnwrkusah ceed ea ee 9 Ve e RU EES P E 1 FEALDIUGTE EE EE 11 1 1 Mother board 24ADC PRESELDAJ 11 1 2 Daughter Board DB 2xADC 18 eA Schematics deeg jw Ee Ne 19 lee DON OI E eo
35. ment basis trigger LO by analyzing the Fast Or signals performs a simple hit finding algorithm and presents those data to the trigger L1 5 logic buffers up to 5 accepted events and finally passes data on to the DAQ farm PCs Modules of the system The FADC system consists of two 9U VME crates one for the readout of ro and the other for rz directions please note that the detector strips run along the z axis in the ro readout subsystem and vice versa Each crate has 3 slots for GU modules and 18 9U slots which are filled with e 1 Sparc CPU 50 crate controller GU VME e 18 FADCTF mother boards 9U VME equipped with 12 DB 2xADC daughter boards each e 1 sequencer board BU VME slot number must be 3 or above e 1 custom P2 backplane distributing timing and control signals e 1 custom P3 backplane for FADCTF interconnection of Fast Or signals with neighbor modules for the LO processor and event signals for the possibility of a simple L1 5 trigger and PCI Link connection e 18 ADC PCI Link boards sitting on the P3 backplane The diagram below visualizes these components 0 IL Segment number 3 segment groups eue dy9eq zd eue dxoeq ed ALOAVA ALOAVA ALOGVA ALOGVA ALOGVA ALOAVA ALOGVA JLOQV4H JLOQV4H JLOQV4H JLOQV4H JLOQVH4H JLOQV4H JLOQVH4H JLOQV4H JLOQVH4H JLOQV4H JLOQV
36. negative inputs are shown in blue and cyan respectively and the difference is drawn in red 27 Tes stop Math Rise 1 790ns La imer tC RT d ls GE dl 7 May 2002 Math 1 00V 20 0ns 11 20 13 31 01 Input pulse measured at Vinar red Tok stop Math Rise 21 02ns Chil 200mv 4 260mV ME ons A Chi 7 10 DUT 7 May 2002 Math 200mV 20 0ns 11 20 13 33 13 Step function measured after the first filter V 28 Math Rise 35 95ns 7 May 2002 Math 200mV 20 0ns ii 11 20 13 37 58 Step function at the ADC input Vioc Compared to the calculation both filters are stronger than expected but without any impact on the sampling point T d Trigger processor for LO The trigger processor looks for particle tracks in the four Silicon layers that origin from the beam interaction region Each FADCTF basically reads out one segment 1 18 of 360 20 of the SVD detector modules The graph below shows 1 6 60 of the silicon detector This allows to build a fast LO trigger with the smallest segment of one single VA1TA 128 strips The FADCTF modules are shown in the same colors as the detector modules which they read out One FADCTF reads out either a segment of planes 1 3 4 or 2 3 4 The arrows indicate which information needs to be provided to neighboring modules to properly build LO triggers from the Fast Or signals This principle applies to both ro and rz readout directions Full modules
37. of the VATTA readout chip via the REBO chain and digitizes them with 10 bits at 20 MHz although the strip data is only clocked at 5 MHz Moreover the Fast Or trigger output is detected with a comparator in the time window where it is expected During analog data readout the comparator is disabled Each ADC daughter board has two channels with individual ADCs level shifting and test inputs Twelve such boards will be sitting on a single mother board Alternatively single ADC boards can be tested and debugged on a specific VME test board Only one of these two channels is shown in the simplified block diagram below DAC Viac TEST B D ADC p TEST p A 1 0 pal i LS dT IN BL P Via IN l Jd CM P at l V CH OS EFT This picture also defines the way in which differential and single input voltages are measured EFT and CMP levels are TTL 0 3 3 5V The ADC output range is O 1023 represented on a 10 bit bus The nominal amplification factors are V 0 084 Virus 0 39 Vbac Vo Vinar V4 ADC 0 51 V mV More details on the conversion factors are given in the last section of this document 18 1 Schematics The full schematics of the ADC daughter board are shown below including probe test points 1 Vinar zm 100n fres
38. om the neighboring FADCTF modules 2x8 lines to each neighbor Rows D and Z also provide interconnections for the L 1 5 processor optional VME Connector 160pin P BB SS Z gt gt b 1 P_P3_A3 I P P3 A4 1 P_P3_ A5 IaP P3 A6 I P P3 A7 I P P3 A PAP AP AP oP AP dD O Ln C4 RS M 5 S 1 a gt ID B e D B E 5 BB SD BD SS LA Z a gt gt ns D a gt O d FI D L a LI x D gt N Ri VME communication The VME communication is explained in the Programmer s Manual Test procedures Two different types of tests can be performed on the FADCTF internal tests involving only the FADCTF crate or parts of it and external tests where the whole DAQ chain is checked 1 Internal tests In normal operation the Sequencer board is used to transceive and distribute the TTM signals However in a standalone mode it can also generate all these signals which are required for autonomous testing 43 purposes It has its own clock generator and is able to create EFT start L1 5 and the event number When the test sequence is initialized in standalone mode EFT is high and a test pulse is sent after a certain time
39. or Four user defined voltage pins are used for special supply voltages The 12V voltages are provided by the Sequencer board and needed by the Sparc interface Pin Name Voltage D3 VI 2 5V D4 V2 1 8V DB V1 5 0V D7 V2 1 8V A31 12V 12V Cali EE 12 The picture below shows all signals on the P1 connector VME Connector 16 pin P1 4 2 P2 connector On the P2 connector a special bus is plugged onto the rear side which connects some user defined pins from slots 3 until 21 This bus uses only rows A and C while row B carries standard VME signals 41 The TTM signals row A some reserve signals and the test signals are transmitted differentially with LVDS levels This bus is properly terminated at slot 21 which is the far end from the Sequencer slot 3 The user defined bus signals are described in the table below Pins A C1 A C2 A C3 A C5 A C6 9 A C12 A C15 A C30 A C31 A C32 Name Source ADC CKL BM TTM Seq CLK 20M TTM Seq ADC START TIM Seq EFT TTM Seg EVTAG1 4 TIM Sec HEJ TEST FTI P2
40. produced by loading proper values into the pedestal threshold cut memory such that specific channels are above or below the threshold In addition strips 64 and 65 counting from zero are also pulsed by a test signal similar to the Fast Or test pulse It is recommended that the DAC offsets of each input channel is set individually such that the output data can be easily verified e g forming a staircase by increasing the DAC offsets with the input channel number The graph below indicates the test procedures for Fast Or and Strip data 44 10 bit 16 bit Se DAC Data for L1 5 processor Testpulse Data for onboard LO processor For LO Trig No hit from testpulse Pedestal threshold cut memory ee 4 comparator threshold 646 Q x 128 Hit from testpulse Ch y a Zero input comparator threshold Hit Hit Hit testpulse 1 3 Sequencer board The Sequencer does not only provide the clock control and timing signals but is can also be used to output an arbitrary waveform on the 4 channels of an RJ45 connector which can be connected to any of the FADCTF inputs for test purposes Moreover the PCI Link output can be plugged into the Sequencer board to read back the output data via VME 2 External tests These tests invoke external components such as the VATTA chips or the TIM system 2 1 VA1TA transparent mode The VA1TA chips can be switched to transparent mode where the output is not multiplexed but
41. put is sampled in the FADCTF modules with either 5 or 20 MHz One can either collect several samples of the shaping curve to reconstruct the maximum by software or collect only a single sample and tune the timing until it is obtained at the peak of the shaping curve In any case all 24 inputs of an FADCTF work in parallel 3 2 Method The user has to decide how many components he she will include in the test As an example the START signal to initiate a data taking sequence can 46 originate from the TIM the Sequencer or the FADCTF itself The CLOCK can be taken from TTM or from the Sequencer Due to limitations in the number of available pins there is no global switch between 5 and 20 MHz corresponding to 200 and 50 ns but each DAP Data Processor has to be switched individually The FADCTF module s must be switched to the test mode TESTEX by a VME command writing DO2 1 to the TIP1 B register VME address offset OxO 18800 If the internal START signal should be used it must be set with D03 1 in the same write command For such tests only the DAP FIFO memory with address O is used The Final Memory to which the data are then transferred can store 2 events at maximum The ADCCLKS signal from the TTM system defines the time slots where one or more samples are taken from the input This gate will be synchronized to the 200ns ADC sampling period The width of ADCCLKS defines the number of samples to be stored e g if it i
42. respectively Please note that these DACs are located on the mother board The ADOs internally generate their reference and common mode voltages The latter is buffered by ICB1 and fed into the designated inputs on ICA1 and ICA2 respectively Their outputs are presented to the ADCs through protection diodes towards GND and a low pass filter The nominal ADC clocks CLK1 and CLK2 will be 20 MHz although the devices can be operated up to 40 MHz As long as the EFT signal to the comparators CMP1 and CMP2 is high these devices watch for the Fast Or trigger which is signalled on the CMP1 and CMP2 lines respectively For trigger test purposes a Fast Or should be emulated only on specific channels This can be achieved by individual DAC voltage settings and a common TEST signal applied to all channels Those channels which should not produce a Fast Or signal should have a low DAC setting such that the TEST signal will not exceed the comparator threshold Other channels with a normal DAC setting will generate a comparator signal when a TEST pulse is applied By that method which is supported by the mother board a completely arbitrary Fast Or pattern can be produced although using a TEST pulse that is common to all channels on all mother boards 1 2 2 Layout The electrical layout of the PCB is shown below followed by photographs of an assembled device Green components are mounted on top while red parts are located on the bottom side c
43. rimposed as shown below Again four different pedestal DAC settings are used to distinguish the inputs Lon ADC_DATA Read_DAP_LocalBus1 4 3 Transparent mode simulation A triangular input is presented to the Sequencer analog input and fed from its RJ45 output into the FADCTF The picture below shows the result of the transparent nibble mode test of the FADCTF with the Sequencer In the beginning there are 4 single samples 200ns window each followed by 4x2 samples 40Ons 4x3 600ns and 4x4 80Ons After that beginning at sample 40 the ADC sampling is switched to 5Ons period 2OMHz This produces 4x20 samples 1000ns followed by a fraction of 4x24 samples 1200ns n NIBBLE MODE 100 0 5 IOS 715 20 25 30 3805 45 0550 bb 80 65 7050775 780 7 85 90 SE 100 5105 110 5119 120 127 P3 Cable has to be connected IIl 48
44. s 200ns or less only one sample will be taken The maximum length is 128 200ns or 128 50ns depending on the sampling rate 5 or 20MHz If the ADCCLKS gate is always on 128 samples will be taken after the start STARTEX signal and after that the data block is transferred to the Final Memory where it can be read out The event number can be taken either from the TTM from the Sequencer or from the Timing control the latter two can be set by VME In any case 128 stored samples are required before the data block can be read out In order to read another 128 samples another Start signal is required 4 Screenshots 4 1 Standard internal test Every input is set to a different pedestal DAC setting in order to easily distinguish the different inputs The left plot shows an overlay of 4 inputs with the test pulse over 128 samples the center plot shows 12 channels as they are serialized in the Final Memory half word and the right plot monitors both low and high half words of the final memory 1 ADC READOUT G x 0 0 200 400 600 800 1000 1200 14001535 ml ZER Read_DACPR_LocalBus2 Read_DACPR gt P3 47 4 2 Sequencer DAC ramp The Sequencer can generate a DAC ramp synchronous to the start signal which is available on the RJ45 analog output connector When this signal is connected to an FADCTF input the falling ramp with 128 different signal values is measured by the ADC with the test pulse supe
45. s optional and depends on utilization of gates within LOP1 A block diagram with all interconnections between the logic units is shown on the next page except for the JTAG buses 15 CIKO 17 24 DAP oO Ru45 CH 18 16 RJ45 CH 17 20 Ru45 CH 21 24 jjj Es I Oo rj el III d o IB M 6 CT SIS U E E TIL d S IB al JE LI ed RIS O gt Ut m Bg C Hal wL i D Terminator B Abschluss Wid 100Ohm differentiell Abschluss Wid 1000hm auf 3 3V D Abschluss Wid 1000hm auf GND NIM gt TTL i TAA amp ITI im w Comparator TIL 2NIM 16 DAP2 out EX 16 DAP4 out EX DACPRI EP20K300E Tor gt HM TL FIO e L TIL 2NIM reo Q lt EPM7512B VME 1 EPM72568 3 3V 2 5V 4 1 8V 5V GND IN OUT MTTM 33V 2 5V 5 DS 5V GND 5 Q For LO trigger L1 5 5V GND 16 The 3 JTAG buses DAPx TIP1 TRP1 DACPR1 10P1 I0P2 used for programming and testing the Altera devices are shown below JTAG Bus 2 Loc Bus 1 VME 1 EPM7256S Serial Bus 1 IOP 1 IOP 2 EPM7512B EPM7512B 17 1 2 Daughter Board DB 2xADC The ADC daughter board receives the analog output data
46. t sex H zi z T esch 1 2k e e amp e Lem Zeie V testa o AD8132ARM 2 i 9 5V 150 470 150 470 EL pr tain a EFT IN2 470 j 3 3V 6 L19 9 3 3V l 4 om gt B 7 o o x y sl s is DIE Sji Te E EH 100n 2 u frest 15 Hs pacal g 1 2k SR D AD8132A SL e 5v BAT54AW DI 7470 H 1 2k 470 5 6k gt 470 ei gt wIEMAX9B3CSA CMP2 Samtec 22pol f KSE X
47. ter as shown below The comparator switching has some effect on the analog lines but these spikes are not seen on the digitized Tek Stop Chil S00mV Soomv Mi 200ns ch X T 80 V Cha 2 00V 29 May 2002 Math 1 00 V 200ns i8 6 800 11 23 21 24 As indicated before the amplifier stage is just buffering the input signal yielding an amplitude of about 1334mVpp The conversion corresponds very well with the nominal factor of 1 The green curve corresponds to the comparator output Vomp which is described below The next picture shows the ADC representation of the same signal yellow and the comparator output red Again the measured amplitude of 675ADC corresponds very well to the nominal ADC gain of 0 51ADC mV referred to MIN MAX MAX MIN Tao el DAC4 2 AUTOSCALE 150 825 575 1490 04 04 1233 44 44 TEST Ext E ER KS SS gi T EN S FEE EEI 120 140 160 180 200 220 240 255 1 2 6 2 TEST ADC Tels Stop Ch1 i5 V Ch 200v Maoons chi X TI 6 May 2002 2 00 V 400ns 181 18 80 15 44 26 This is a differential test pulse input provided by a differential LV TTL driver which is used on both the daughter board tester and the mother board to generate test pulses with a differential peak to peak amplitude of approximately 6600mVpp eo The corresponding ADC output is shown below yielding an amplitude of 277ADC which is in good agreement with the nominal gain of 0 04
48. tracks on the strip level If there is no positive L 1 5 decision before the next start signal the following event overwrites the current memory thus discarding the previous data Upon reception of a L1 5 accept the stored event data will be transferred to another internal FIFO final memory with a maximum capacity of 2 events From there the data is pushed out through the DAQ PCI links to the Linux farm Due to the FIFOs inside the FADC new signal inputs may arrive while earlier events are still in the queue However if a total of 5 FIFOs are filled a busy signal is sent out which vetoes any further triggers until the current data are processed and the space for one event in the DAP FIFOs is freed As a general rule there is stil room for one more event after the busy notification is sent out VA1TA Rebo The VA1TA output signals are amplified by the REBO repeater boards The typical waveforms are shown in the graph below Slow shaper Fast shaper TOns jitter Fast Or S Hold Strip data 128 channel multiplexed analog strip data Peaking time T fixed delay Time for LO decision reduced by Fast Or jitter The chip internal outputs of slow and fast shaper of a single channel are shown when a particle hit occurs in that particular channel If the tunable threshold for the fast shaper is exceeded a short digital pulse is generated and combined from all 128 channels with an OH logic

FADCTF system - User`s manual (V1.05, 31 July 2002)

Contents

Download Pdf Manuals

Related Search

Related Contents