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SpW-10X SpaceWire Router User Manual

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2. Austrian Aerospace 11 2 ABSOLUTE MAXIMUM RATINGS The absolute maximum ratings are listed in Table 11 2 For a detailed list of the maximum conditions see AD3 Table 11 2 Absolute Maximum Ratings Supply voltage range V Input voltage range Input pin current ME Siral pi Lead temperature soldering 10 sec Storage temperature range Maximum junction temperature 11 3 RELIABILITY INFORMATION The information required for reliability analysis of the SpW 10X device has been collated and is presented in Table 11 3 Temperature Application dependent Package QFP196 with 25 mil pin spacing Environment Application dependent Learning factor Established Atmel ASIC technology MH1RT for several years 139 SpW 1 OX Ref UoD SpW 10X ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 weus User Manual Date 7 January 2015 GH Austrian Aerospace 12 APPLICATION GUIDELINES In this section an example circuit diagram is provided and PCB and design guidelines presented 12 1 EXAMPLE CIRCUIT DIAGRAM A schematic showing how the SpW 10X device should be connected is provided on the following page This is a complete schematic for a stand alone router except for the 3 3V power supply and reset signal 140 pW 10X_ UserManual 3 5 UoD S Ref Issue 7 January 2015 RIV SH OWG NO Date SpW 10X SpaceWire Router 6 ASTRIUM School of omputin EADS
3. NS Max CLK rising edge to full flag output 18 Read enable setup time to CLK rising edge 5 ns min CLK rising edge to empty flag output TEXTEFCKO 5 ns min CLK rising edge to empty flag output 10 4 TIME CODE INTERFACE TIMING PARAMETERS The following diagrams define the timing parameters for the time code input and output Toon Toten some NONN KONNY amen NONN EEN TteLkisu TCLKIHLD gt Figure 10 4 Time Code Input Interface 132 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual n SpaceWire Router K School of Computing Issue 3 5 omg User Manual Date 7 January 2015 Austrian Aerospace Troukor Trorkor EXT TICK OUT VVVVVVV VVVVVVV Ex TIMEOUT HAKK KKK Figure 10 5 Time Code Output Interface Troun TIME_CTR_RST Figure 10 6 Time code TIME CTR RST interface The Time code timing parameters are shown below Table 10 4 Time code interface timing parameters Tick in and time reset low time Trcukit period DNS Tick in and time reset high time Select external time and Time code in set up time in hold ti Select external time and Time code in hold time ns max Tick out low time TTcLKOL 3 CLK Minto periods max 5ns Tick out high time TTcLKOH 4 CLK min periods Time code output valid delay time relative to falling edge of Trcukoe 5 ns eer ed 133 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router School of Computing Issue 3 5 User M
4. Undefined after power on Unaltered by reset 4 Delete header when set the leading header R W byte of the input packet will be removed before it is transferred to the output port When a packet has a logical address with an R W entry in the priority filed of this register set the packet will be granted access to a particular output port in preference to packets with priority bit set to Zero When the Invalid Address bit is set it indicates R W that the corresponding logical address is invalid In this case any packets arriving at the router with an invalid address are spilt and an address error is reported in the port status register 109 SpW 1 OX Ref UoD SpW 10X ASTRIUM i UserManual n SpaceWire Router K School of Computing Issue 3 5 User Manual Date 7 January 2015 Austrian Aerospace WARNING Care must be taken when setting a the routing tables to avoid a possible infinite loop For example if there is a SpaceWire link made between two ports of a single router and a logical address routes a packet out of one of these ports then that packet will arrive back at the router and be routed back out of the port again Depending on the size of the packet it may block because it cannot get access to the output port the second time around as the tail of the packet is still being fed to the output port In this case the blockage will cause a timeout when watchdog timer mode set see section
5. ERE ENET TEE EAET EAET zeg OS E o Kan lt o Oma Td 1100 Etgen o Yin 1n0s ON 1NOS Td1N0S E Od INOS L TN NS OWE TANIS I ONS TN NO T ON NIC ONO OGNA ar b uo Duwa PUD SDIg avM3IDLdS 9 L vg m 141 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 Kam User Manual Date 7 January 2015 Austrian Aerospace 12 2 PCB DESIGN AND LAYOUT GUIDELINES PCB design and layout guide lines are provided in this section 12 2 1 CLK 1 Series termination should be used on the CLK signal 2 Stubs on the CLK signal shall not be used 3 Guard tracks shall be provided around the CLK signal trace connected to the ground plane approximately every 1 cm 12 2 2 RST N Guard tracks shall be provided around the RST_N signal trace connected to the ground plane approximately every 1 cm 12 2 3 Chip Test Signals The two chip test signals TestlOEn and TestEn shall both be tied directly to the ground plane 12 2 4 Power and Decoupling 1 Each power pin shall be decoupled to ground using a 100 nF decoupling capacitor 2 The 100 nF decoupling capacitors shall be fitted close to the each power pin with the other end of the capacitor connected to the ground plane 3 In addition to the 100 nF decoupling capacitors four 1 uF decoupling capacitors shall be fitted close to the SpW 10X device 12 2 5 Ground 1 A solid ground plane shall be used 2 The ground
6. e a a Value Description Read Write Allowed Mode When 1 Blocking Allowed Mode Watchdog Set by the input signal Timer Mode POR TIMEOUT ENN ON When 0 Watchdog Timer Mode 3 1 Timeout Selection Set by the input signal POR SEL TIMEOUTO N When 1 timeout period is 60 80 us When 0 timeout period is 1 3 ms Enable disable on silence Set by the input signal POR DISCONNECT ON SILENCE N When set to 1 then the watchdog timer mode is enabled When set to 0 then the blocking allowed mode is enabled See section 8 3 5 Selects the blockage timeout period Values as below 000 gt 60 80 us N 2 001 gt 1 3 ms N 6 010 gt 10 ms N 9 011 gt 82 ms N 12 100 gt 1 3 s N 16 401 gt 1 3 s N 16 110 gt 1 3 s N 16 111 gt 1 3 s N 16 The actual value of the timeout period is given by 200 x 2 N x TCLK 200 x TCLK where TCLK is the period of the 10 MHz clock signal When set the corresponding SpaceWire port will be disconnected if no activity is detected over the timeout period The SpaceWire port will only be disconnected if the port was initially started when a packet arrived at the router to be routed out of the specific SpaceWire port and the start on request bit was set If an external device starts SpW 10X ASTRIUM K School of Computing
7. omputing User Manual Austrian Aerospace NA packet is corrupted Early EOP Cargo too Large Early EEP Verify Buffer Overrun Error Command not implemented Invalid Data Length The command packet was terminated early with an EOP reply packet is sent if the early EOP error occurs on the data part of the packet The expected amount of SpaceWire cargo has been received without receiving an EOP marker The command packet was terminated early with an EEP reply packet is sent if the early EEP error occurs on the data part of the packet The data length field is invalid when performing a verified write command The valid length is 4 bytes of data A command code was received which is not supported by the SpaceWire router Supported command codes are listed in F1 18 The data length field is invalid A data length error is recorded when 1 The data length is not a multiple of 4 The data length is zero The data length is outside the range 4 1064 when performing an incrementing read The data length is not 4 in a verified write mn Ref UoD SpW 10X UserManual Issue 3 5 Date 7 January 2015 Early EOP Cargo too large Early EEP Verify Buffer Overrun RMAP Command not implemented or not authorised RMAP Command not implemented or not authorised ote 1 a Verify Buffer Overrun error shall be returned when the data length is not 4ina v
8. 73 DUNDEI Command Byte Destination Key Source Path Address Source Logical Address Transaction Identifier Extended Write Address Write Address Data Length Header CRC The 32 bit data value to write to the SpaceWire router register 4 Data CRC The data CRC used to detect errors in the data part of the command packet SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router School of Computing Issue 3 5 User Manual Date 7 January 2015 Austrian Aerospace the number of source path addresses required as defined in section 7 6 9 The destination key identifier must match the contents of the destination key register see section 9 5 10 The source path address field is used to add source path addresses to the 0 4 8 12 head of the reply packet The expected number of source path addresses is specified in the command byte See section 7 6 9 for source path address The command byte indicates a write single address with verification and acknowledgement packet The Source path address length fields are set to decoding The source logical address should be set to the logical address of the node which sent the command The transaction identifier identifies the command packet and reply packet with a unique number The extended write address is not used in the SpaceWire router and is always expected to be zero write addresses are defined in section 9 The data
9. ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 GH Austrian Aerospace VERN 123 9 5 6 Device Manufacturer and Chip ID Register 0nnnnnnannennannennnnnnnnnennrnnrrrsrrnnrsrrrnrrnrrerrsrrsnenne 124 9 5 7 General Purpose Heger 125 9 5 8 Time Code Enable Register 00nn00nnnnnnnnnnennounnnnnnsnnnerinnrrsnrrsnnrerrnnrrsnrrsnrrrrrrrrrsnrrsnererrrnrene 125 9 5 9 Transmit Clock Control Heger 126 9 5 10 Destination Key Register nnnannennennnnenennnannnrsrrrrnrrsrrsrrrrrrrsrrsrrnrrnrsnrnrrnrrrrsrrnrrnrrnrenrerenne 129 9 5 11 Unused Registers and Register Bits cccccccccecccsseeeeeeeeeeceeeceueeeeeeseeeceueceueeseeesseeseeesaaes 129 DE ENN Sa 129 96 WRITING TOA READ ONLY REGISTER sccccssscocsseccseseceesuncromsaceusmcreusnceumseccenenarcsanscavacarsasetes 129 10 SWITCHING CHARACTERISTICS NE 130 10 1 CLOCK AND RESET TIMING PBARAMETIERG 130 102 SERIAL SIGNALS TIMING PARAMETERS siascininisiciusntninindeinininacdusaininindeinininaxieiininindeineits 130 10 3 EXTERNAL PORT TIMING PARAMETERS enee 131 10 4 TIME CODE INTERFACE TIMING PARAMETERS iinnannnnnnnnnnnnnennnnnnnnennnnrrrnnnrnserreenrrserrene 132 10 5 ERROR STATUS INTERFACE TIMING PARAMET ERS nainannnannnennnnnnsnnnnnnnennnnnnsnrnsnrnnreneenne 134 100 Jeekelen 135 DL OP 135 VE SN ANN E 135 E FR BEEN 135 10 6 4 Time code Latency onnnnnoennennennsnrsnnorrrrrrrrrerrrrnrrrr
10. Austrian Aerospace Table 9 14 Time Code Enable Register Fields Reset Description Read Write Value 8 1 SpaceWire Time code distribution enable bits for SpaceWire Time Code ports 8 to 1 respectively The appropriate bit Enable should be set to 1 to enable time code distribution through the corresponding port External Time 1 Time code distribution enable for External time Code Interface Enable code port 11 10 Not Used All bits set to zero 12 Time code Flag Time code flag interpretation mode mode When 0 Time code control bit flags are distributed with valid time code values regardless of the value of the time code control flags When 1 When the time code control flags are 00 then valid time codes are distributed When the time code control flags are not 00 then the time code is discarded and the internal time code register is not updated 31 13 Not used All bits set to zero 9 5 9 Transmit Clock Control Register The transmit clock control register address is 264 0x0000 0108 The transmit clock control register is shown in Figure 9 10 Bits 1 to 0 are used to determine the output divide ratio TXDIV for the transmit clock internal PLL Bits 15 to 8 are used to stop the transmitter clocks of SpaceWire interfaces that are not being used to save power i e only clock of the SpaceWire ports that are going to be used should be enabled Bits 20 to 16 are used to set the default 10Mbits s transm
11. Transaction The transaction identifier identifies the command packet and reply packet Identifier with a unique number The transaction identifier in the reply packet is copied from the command packet and returned in this field so that the command and the corresponding reply have the same transaction identifier value Data Length The data length field is set to 4 bytes as 4 bytes are returned in the Read Modify Write command Header CRC The header CRC used to detect errors in the header part of the command packet See section 7 6 7 for CRC generation Data The data read from the SpaceWire router registers before the modify operation is performed Data CRC The data CRC used to detect errors in the data part of the reply packet See section 7 6 7 for CRC generation 7 6 5 Write Command The write command characteristics of the SpaceWire router are defined in Table 7 14 Table 7 14 Write Command Characteristics Supported Maximum number Non aligned access of bytes accepted Not Supported Accepted address ranges 0x00 0000 0000 0x00 0000 0109 12 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 Pran User Manual Date 7 January 2015 GH Austrian Aerospace The RMAP write single address with data verify and acknowledgement command is supported in the SpaceWire router The RMAP write command is used to write a 32 bit value into one of the SpaceWire router regi
12. TrxPeriop Receive bit rate period 2 Where Receive bit rate period is the period of the input bit rate 10 6 2 Switching Latency Switching latency is the time it takes the router to connect a waiting input port to an output port that has just finished sending a packet It includes any time for group adaptive routing and arbitration of two or more input ports competing for the same output port Switching latency for the router is defined as follows Tswircy 4 x Tsysperiop 10 6 3 Router Latency Router latency is the time taken for a character in a packet to pass through the router assuming that the packet has already been switched to an output port and that there is no blocking of the output port Router latency for the SpaceWire router is defined for port to port data transfer operations as follows 135 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 GH Austrian Aerospace SpaceWire port to SpaceWire port Last bit of data into receiver to last bit of data out of transmitter Worst case where transmitter is sending a time code and FCT character before data TsspaTa 5 X T RXPERIOD 8 x Ts YSPERIOD 23 X TTXPERIOD SpaceWire port to External port Last bit of data into receiver to external port not empty flag TSEDATA 5 X TRXPERIOD 8 x Ts YSPERIOD External port to SpaceWire port External port write enable to la
13. 0 These inputs should be driven or pulled up or down e g 4k7 Q depending on what information is required from the status outputs given in section 6 3 STAT MUX OUT 7 inout Multi function pin CMOS3V3 STAT MUX OUT 6 Power on Configuration STAT MUX OUT 5 After reset the STAT MUX OUT pins are STAT MUX OUT 4 inputs which define the power on configuration se eee status of the router The pin mappings are EN en listed in section 5 6 STAT MUX OUT 1 STAT MUX OUT 0 These pins should be pulled up or down e g 4k7 Q to provide the required power on configuration input values Normal Operation After the power on reset configuration of the router has been read from STAT MUX OUT the pins are driven as outputs by the router The function of these output pins is defined by STAT MUX ADDR 3 0 Further details are 43 SpW 1 OX Ref UoD SpW 10X ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 Austrian Aerospace STAT MUX OUT POR SIGNALS STAT MUX OUT Inputs Outputs Figure 5 2 Configuration interface timing specification The POR configuration signals POR SIGNALS listed in Table 5 6 are loaded into the appropriate internal configuration registers of the router after RST is de asserted To make sure that the POR configuration signal values are loaded properly they should be held stable for at least three CLK cycles following RST being de asserted
14. 00 00 12 01 02 B2 03 05 00 32 01 02 07 02 05 08 00 00 00 00 00 00 00 00 00 02 03 00 01 00 00 00 00 00 00 02 00 00 01 00 00 00 00 00 02 03 00 01 Figure 7 12 and Figure 7 13 illustrate how source path addresses are returned in relation to the RMAP packet description SS 79 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 Pran User Manual Date 7 January 2015 GH Austrian Aerospace Dest Logical Protocol ID Dest Key o x e Source Logical Trans ID 1 Trans ID 0 Address 4 Figure 7 12 Source Path Address field decoding Local Source Figure 7 13 Source Path Addresses in Reply Packet 7 6 10 Command Packet Fill Bytes The Configuration port accepts packets which are addressed to port 0 In the RMAP command the next byte after the destination address 0 is the destination logical address byte which in the router is expected to be the default 254 value The format is shown in Figure 7 14 Path Address 0 RMAP Header Figure 7 14 Normal Configuration Packet Header Structure To allow source nodes which have a 16 24 or 32 bit access port then the configuration port accepts up to three null bytes at the start of the packet The null bytes must be zero otherwise they will be treated as the destination logical address and an invalid destination logical address shall be recorded if the byte is not 254 The header with f
15. 16 x 10 MHz clk period An external pull down resistor e g 4k7 Q is recommended on this pin to provide the longer timeout interval STAT MUX OUT 6 Power on reset signal which determines if the CMOS3V3 maps to gt output ports automatically start up when they POR START ON REQ N are the destination address of a packet When asserted low the output port will automatically start on request This signal is active low STAT MUX OUT 7 Power on reset signal which determines if the CMOS3V3 maps to gt output ports are disabled when no activity is POR DSBLE ON SILENCE Ni detected on an output port for the current timeout period When asserted low an output port is disabled when it has not sent any information for longer than the current timeout period This signal is active low WARNING In most onboard applications it is recommended to have Stat mux out 4 pulled low by default in order to enable the watchdog timers on reset WARNING When the watchdog timers are not enabled the SpaceWire and external ports can block indefinitely if for example a source stops sending data in the middle of a packet If watchdog timers are not enabled then it must be possible for a network manager to detect blocking situations and to reset the router or node creating the problem 46 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 Pran User Manual Date 7 January 2015 Austr
16. 3 5 User Manual Date 7 January 2015 Austrian Aerospace The serial signal timing parameters are defined in the table below Table 10 2 Serial signal timing parameters DS maximum input bit rate 200 2 Mbits s max DS minimum consecutive edge separation Minimum edge separation between 2 consecutive edges Data Strobe output skew amp jitter incl LVDS driver 10 3 EXTERNAL PORT TIMING PARAMETERS The external port input timing parameters can be viewed below CLK Textwrsu T EXxTWRHLD KO O sd EXT IN WRITE N XXXXXXX KXKXKKX T ExTODATSU T EXTODATHLD EXTINDATA XXXXXK il KAKA EXT IN FULL N Figure 10 2 External port input FIFO timing parameters The external port input timing parameters can be viewed below CLK T FXTRDSU T FXTRDHLD al A EXT OUT READN MAAN JG AAAY EXT OUT DATA AAA AAA T EXTODATCKO EXT OUT EMPTY N Figure 10 3 External port output FIFO timing parameters 131 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual n SpaceWire Router K School of Computing Issue 3 5 omg User Manual Date 7 January 2015 Austrian Aerospace Table 10 3 External port timing parameters Description Symbol Value Write enable setup time to CLK rising edge 5 ns min Write enable hold time after CLK rising edge 5 ns min Write data setup time to CLK rising edge ns min Write data hold time after CLK rising edge 5 5 ns min CLK rising edge to full flag output 5 ns min
17. 3 5 Bags User Manual Date 7 January 2015 L Austrian Aerospace WARNING The default timeout intervals of 60 80 us or 1 3 ms are short It may be necessary to increase the timeout interval by a configuration command writing to the router control register When initially prototyping a SpaceWire system it is advisable to set the timeout interval to 1 3 s and then decrease it to an appropriate value once basic system operation has been established 9 5 4 Error active Register The error active register address is 259 0x0000 0103 The error active register indicates the Error Active bit of the each of the port control status registers By reading from this register a network manager can determine which ports currently have errors This register is also used to clear the error bits of the port control status registers To do this a write command is sent to the error active register with bits set for those errors that are to be cleared The error active register fields are shown in Figure 9 6 and described in Table 9 11 31 30 1 0 Error Active Configuration Port Error Active SpaceWire and External Ports Not used Figure 9 6 Error Active Register Fields 122 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 Pran User Manual Date 7 January 2015 Austrian Aerospace Table 9 11 Error Active Register Fields Reset Description Read Write Value Configuration
18. 3 5 omg User Manual Date 7 January 2015 Austrian Aerospace 100MHz 20MHz FEEDBDIV d 2 ng 1 10MbitRate TX10MbitDIV 1 To provide a SpaceWire signal with a nominal 50 50 duty cycle TXRATE and TX10MbitDIV should be even integers Not all values of FEEDBDIV TXDIV and TXRATE give valid clock signals Table 8 1shows the recommended values to use to achieve a range of SpaceWire transmit data rates Table 8 1 Setting SpaceWire Transmit Data Rate TXRATE Initialisation Data Rate 9 10 Data Duty 1 1 Soul 2 11 Rate Cycle 19 21 0 17 19 ES asasi Er 11 100 909 10 000 fan 11 100 909 20 000 ez oo 90 818 20000 fr 1 1 Lem es a toed n toed mg a Coed EG 2 el co ei Kei H 2000 ES On On On I Ex O O 200 0 Q faa Q mr mr Ll UT omg d W mlm rm N U1 Oo co Sy lU alelu N N NjolN N N 60 0 17 15 Uli zl W OD CO N O O 3 m N ia Es LA Es O N LA Oo SEE me AJ gt NIN O 20 0 LA m e WO m e Al eR w w lar 1 1 1 Ww LA W A LA bei E CO eu O LA 23 33 7 14 7 14 16 67 10 0 16 67 w o oO In Table 8 1 the values with a white background are the values that should be used The values which are shaded red should not be used The first three columns give settings for the FEEDBDIV pins on the SpW 10X device the TXDIV f
19. 31 8 Not used All bits set to zero 9 5 11 Unused Registers and Register Bits If an unused register address is referenced in a configuration command then the command will not be acted upon and a NACK will be sent in the reply to the command All unused bits in valid configuration registers will return 0 when read 9 5 12 Empty packets An empty packet received at the configuration port is discarded by the configuration port and no reply packet is sent An empty packet has no address or cargo bytes and consists only of an EOP 9 6 WRITING TO A READ ONLY REGISTER If a write command is sent with a register address that corresponds to a register whose entire contents is read only then an appropriate error will be generated See section 9 4 2 129 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router School of Computing Issue 3 5 User Manual Date 7 January 2015 10 SWITCHING CHARACTERISTICS 10 1 CLOCK AND RESET TIMING PARAMETERS The global clock and asynchronous reset timing parameters are listed below Table 10 1 Clock and reset timing parameters 35 5 10 2 SERIAL SIGNALS TIMING PARAMETERS The data strobe minimum consecutive edge separation timing parameter is defined as shown in the figure below DIN n SIN n Tpsns Tpsns Figure 10 1 DS minimum consecutive edge separation 130 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual on SpaceWire Router K School of Computing Issue
20. 5 4 111 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual n SpaceWire Router K School of Computing Issue 3 5 omg User Manual Date 7 January 2015 Austrian Aerospace Table 9 5 Configuration Port Control Status Register Fields Reset Description Read Write Value Port timeout error The error active bit is set when one of the error bits is active The port timeout error bit is set when a timeout event is detected by the configuration port routing logic The Invalid header CRC bit is set when the header CRC is invalid The invalid data CRC is set when the data part of the packet is corrupted and the CRC does not match the internally generated CRC ND Invalid Header CRC Invalid Data CRC Invalid Destination Key The invalid destination key bit is set when the destination key in the command packet is invalid Command not The command not implemented bit is set when the command code is a valid RMAP code but the command is not supported by the implemented SpaceWire Router Invalid Data Length The invalid data length bit is set when a data length error is detected Invalid RMW Data The read modify write command data length is Length invalid When a read modify write is performed the expected data length is 8 Invalid Destination The invalid destination logical address bit is set when the destination logical address in the command packet is not the default value of 204 Logical Add
21. 8 3 5 and the packet will be spilt If the packet is a small packet it could continually circle around the loop A SpaceWire network architecture and configuration should be checked for possible loops for all logical addresses being used Unused logical addresses should NOT be configured in the SpW 10X routing tables so that a packet arriving at a router with an invalid unused logical address will be spilt immediately 9 4 PORT CONTROL STATUS REGISTERS The port control status registers address range is 0 31 0x0000 0000 0x0000 001F The port control status registers provide the means to configure and control the ports of the router and for reading the status of each port There is a port control status register for each SpaceWire port each External port and for the configuration port The address in configuration memory space of a port control status register reflects the physical address of the port For example the register for port 0 the configuration port is at address 0 and the register for a SoaceWire port number 3 is at address 3 Each port control status register is a 32 bit register The fields within the port control status register depend on the type of port that it is attached to All port control status registers have fields for port type and current port connection These generic fields are described first followed by the specific fields for the configuration port SpaceWire ports and External ports Port control st
22. CROSSBAR urrrnunnnnennnnevnnnnnnnnennnnennnnennnnennnnennnnennnnennnnennnne 25 3 6 TIME CODE PROCESSING sisinisinisinieinieininininisinisieisieisie ere ereintaintsinteiereinisieteieieininisinisiaisiati 26 Ir CONTROL STATUS REGISTER rrean eee eee ace 26 A PUN OCA ta LE 27 GE vi ES EG SN NE MN 33 EL ELSE 33 EE e EE EE 34 5 2 1 SpW 10X SpaceWire Signals ccccccseccceccceeeceeeseeeccecsceeeceeeseeesseesceeeceeecseesseesceesseeeseeenes 34 5 2 2 SpaceWire Input Fail Safe RESISIOS usann 37 5 2 3 Operation with DV Powered LVDS Devices 39 SpW 10X Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 GH Austrian Aerospace 59 EXTERNALPORT DATA MS 39 Da HNE ENN 41 EE SATU MEN ENN 43 5 6 RESETCONFIGURATON SIENA Suave 44 5 7 POWER GROUND PLL AND LVDS SIGNALS rrronnennnnnrnnnnnennnnnennnnnrnnnnnsnnnnnennnnnsnnnnnsennnnsennnn 47 AES EEE ENE 47 VE VE de 47 ET BS ANN 47 PECE gt Te ag fe 9 EC 47 b INTERFACE EES 49 61 EXTERNAL PORT INTERFACE EH UE eeg 49 6 2 TIME CODE INTERFACE OPERATION 50 63 STATUS INTERFACE OPERATION sicpsicccctiencrciscncnininenietnnicnictincticiansiciciee EE EEEE EEEE EEEE EEEE 51 6 4 RESET CONFIGURATION INTERFACE OPERATION cc ccccsecceeeeeeeeeeseeeeeeeeeeeeeeaeeeeaaees 53 7 SPACEWIRE ROUTER PACKET TYPES annnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnennnnnennnnnennnnnennnn 54 Tks GE
23. Documents Document Number Document Title LVDS Owner s Manual National Semiconductor Downloadable from http www national com appinfo lvds files National LVDS Owners Manual 4th Edition 2008 pdf AN 1194 Application Note AN 1194 Failsafe Biasing of LVDS Interfaces Downloadable from http www national com an AN AN 1194 pdf page 1 MH1RT Rad Hard 1 6M Used Gates 0 35 Micron CMOS Sea of Gates Embedded Gates ASIC families Downloadable from http www atmel com dyn resources prod documen ts doc4110 pdf 17 SpW 1 OX Ref UoD SpW 10X ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 GH Austrian Aerospace 2 USER APPLICATIONS The SpW 10X SpaceWire router device may be used in several different ways as described in the following sub sections Note SpW 10X is pronounced SpaceWire Ten X This name derives from the abbreviation for SpaceWire SpW the fact that the router has eight SpaceWire ports and two external ports giving ten ports in total and the used of X to represent a cross bar switch 2 1 STAND ALONE ROUTER The SpaceWire Router may be used as a stand alone router with up to eight SpaceWire links connected to it Configuration of the routing tables etc may be done by sending SpaceWire packets containing configuration commands to the router SpaceWire Links Instrument 1 SpW 10X Router Instrument 2
24. El 54 Pe FEE EE 55 Ro PACKET HEADER DELEN Nr 55 7 4 INVALID ADDRESSES E 56 7 5 RTR E EEN 57 WEE eege 57 161 SUPPE COMMONS arr 57 ro FEN 58 Fe EC Ne leen ln Te 160 10100010 EEE EEE 62 7 6 4 Read Modify Write Commande 67 765 Wie ComM serieei aa a a a aa aa ae aai 72 200 ETNE 76 7 6 7 Command Packet Cyclic Redundancy Check 78 reeL 78 7 6 9 Source Path Address Eed 78 1000 COMMMaAMG PACK Sl Tl EE 80 8 CONTROL LOGIC AND OPERATIONAL MODES nnunnnnvrnnnunnnnvnnnnuennnvennnvennnvennnvennnvennnnennnuennnner 81 Bal OPACEWIRE GNK NO 81 Geh 81 SpW 10X Ref UoD_SpW 10X_ 7 ASTRIUM SpaceWire Router UserManual ER School of Computing Issue 3 5 User Manual Date 7 January 2015 L Austrian Aerospace L NTN 81 MA EAS 81 NE Re e e te tects tee cies repose EE E EE EE E E EEEE 82 8 1 5 Automatic deactivate driver mode 82 8 1 6 Setting the SpaceWire port transmit datarate 84 8 2 GLOBAL SPACEWIRE LINK CONTROL esurnnnonnnnonnnnennnnrnnnnennnnnnnnnennnnennnnennnnennnnennnnennnnennnnennnne 87 PN SAO CUE Lee 87 8 2 2 Disable on Silence mode 87 8 3 GONTROL LOGIC AND ROUTING Lure 88 Oal le let 2051 0 a ee a E E E 88 da NNN 88 8 3 2 1 Arbitration of packets with matching priority 1 89 8 3 2 2 Arbitration of packets with matching priority 31 90 8 3 2 3 Arbitration of packets with different priority 1 91 8 3 2 4 Arbitration of packets with different priority 2 ccecceccseeceeeceeeseeeeeeeeeeseeeeeeseeene
25. OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 Austrian Aerospace written to or read from synchronously with the 30MHz system clock An eight bit data interface and an extra control bit for end of packet markers are provided by each external port FIFO Packets received by the external port are routed by the routing control logic to the configuration port SpaceWire link ports or the other external port dependent on the packet address Packets with invalid addresses are discarded by the SpaceWire router 3 3 CONFIGURATION PORT The SpaceWire router has one configuration port which performs read and write operations to internal router registers Packets are routed to the configuration port when a packet with a leading address byte of zero is received The Remote Memory Access Protocol RMAP AD2 to access the configuration port A detailed description of the RMAP command packet format is provided in section 7 6 If an invalid command packet is received then the error is flagged to an associated status register and the packet is discarded The internal router registers are described in section 9 3 4 ROUTING TABLE The SpaceWire router routing table is set by the router command packets to assign logical addresses to physical destination ports on the router A group of destination ports can be set in each routing table location to enable group adaptiv
26. Router K School of Computing Issue 3 5 Bam User Manual Date 7 January 2015 H Austrian Aerospace Table 7 5 Read Single Address Characteristics Supported Maximum number Non aligned access Not Supported of bytes accepted 8 bit read 16 bit read m pp EE SE P o 64 bit read The RMAP read single address command is supported in the SpaceWire router The single address command is used to read a single 32 bit register location from the router registers In Figure 7 3 the format of a read single address command is illustrated The first byte received by the SpaceWire router configuration logic is the port address followed by the destination logical address Fields which are depicted in bold text are expected values Fields which are shaded are optional First Byte Received Config Port Address Oh Destination Logical Address Protocol Identifier Packet Type Command Destination K FEh 01h Source Path Addr Len ee Oh Read ae MS da Last Byte Received Bits in Packet Type Command Source Path Address Length Byte MSB LSB a A Ps Address Length Address Length MD Packet Type DE Command Er Source Path Address Length Figure 7 3 Read Single Address Command Format 59 DUNDEI SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router School of Computing Issue 3 5 User Manual Date 7 January 2015 Austrian Aerospace Table 7 6 Read Single Address Command Packet Fields i i
27. The table below defines the header deletion settings for each address 55 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 Austrian Aerospace Table 7 3 Packet Header Deletion Mapping Packet Address Header Deletion Physical Port type Configuration por SpaceWire ink por SpacaWire lnk por 2 SpaceWire nk por 3 SpaceWie nk por 4 SpacaWire ink por 5 SpacaWire nk por 6 7 Enabled SpaceWire link port 7 Enabled SpaceWire link port 8 Enabled External FIFO port 1 10 Enabled External FIFO port 2 32 255 Dependent on routing table default not Logical addresses enabled Note that header deletion is always enabled for path addresses and cannot be changed by configuration Header deletion for logical addresses can be enabled or disabled via a configuration register see section 9 3 7 4 INVALID ADDRESSES Packets which have invalid addresses are discarded by the routing control logic Path addresses which are in the range 11 31 logical addresses which are set as invalid in the routing table and empty packets packets with no address or cargo input to the external port are flagged as invalid packet addresses A packet address error is also generated when a packet address causes the packet to be routed back through the port on which the packet was received i e a loop back and the router control register bit address self is not e
28. UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 GH Austrian Aerospace The crossbar switch connects an input port to an output port allowing data to flow from the input port to the output port Several input ports may be connected simultaneously to several output ports all passing data Two or more input ports may not be connected to a single output port The crossbar switch is a non blocking type because the connection of one input port to an output port does not prevent another input port being connected to another output port at the same time It is possible for all eight input ports to be each connected to an output port so that all input ports and output ports are being used 3 6 TIME CODE PROCESSING An internal time code register is used in the router to allow the router to be a time code master or a time code slave In master mode the time code interface is used to provide a tick in to the SpaceWire routing causing time codes to be propagated through the network Two modes of time master operation are supported an automatic mode where a time code is propagated on each external tick in and a normal mode where the time code is propagated dependent on the external time in signal In time code slave mode a valid received time code one plus the value of the router time code register causes a tick out to be sent to the SpaceWire links and the external time code interface The ti
29. When operating with IEEE 1355 devices like the old SMCS332 and SMCS116 devices it is recommended that the old devices are replaced by the new SpaceWire compliant SMCS332SpW and SMCS116SpW devices which are or shortly will be available from Atmel If operation with legacy units which use IEEE 1355 devices is necessary and these devices cannot be replaced by the new SpaceWire compliant parts then the following reset sequence is recommended 1 Assert the reset for the SoW 10X device 2 Assert the reset for any IEEE 1355 devices attached to the SoW 10X device 3 Release the reset of the SoW 10X device 4 Wait for at least 10 us 5 Release the reset of the IEEE 1355 devices Alternatively when only a reset of the SpW 10 is required and an attached IEEE 1355 device is not to be reset at the same time then the following reset sequence is recommended 1 Send configuration commands to the SpW 10X device to disable the ports attached to IEEE 1355 devices 2 Once all these ports have been disabled wait for at least 10 us 3 Assert the reset for the SoW 10X device 4 Release the reset of the SoW 10X device 149 SpW 1 OX Ref UoD SpW 10X ASTRIUM i UserManual e SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 Austrian Aerospace 13 4 PARITY ERROR ANOMALY 13 4 1 Parity Error Action A parity error on the SpaceWire link causes the link to be disconnected by the SpaceWire router If
30. after characterisation tests of the SoW 10X prototypes Corrected STATMUXOUT input valid time after reset Clock and Reset switching characteristics added DS skew parameter changed to total Tx skew amp jitter External port timing added Time code interface timing completed corrected Error Status interface timing added Power consumption parameters updated 15 3 ISSUE 3 2 TO ISSUE 3 3 Ref Change eee 2 EE changed to more appropriate reference document that includes information on LVDS 8 15 1 5 Figure 8 3 Bias resistor value corrected to 20k ohms LL 3 Table 9 3 The reset values of the GAR bits are undefined after power on and unchanged after reset except the Invalid Address bit which is 1 after power on or reset 153 SpW 1 OX Ref UoD SpW 10X ASTRIUM i UserManual n SpaceWire Router K School of Computing Issue 3 5 omg User Manual Date 7 January 2015 Austrian Aerospace 12 2 6 Editorial change to text 14 ff Correction made to support email address 15 4 ISSUE 3 1 TO ISSUE 3 2 Change Table 1 2 RD3 added Atmel MH1RT Cold Sparing I O Buffers Figure 3 1 Text in diagram change from non blocking crossbar switch to crossbar switch Explanation of non blocking nature of crossbar switch added sentence added explaining that LVDS inputs and output are oe cold sparing and giving reference to RD3 SP VCO bias resistor value corrected Section 5 7 4 Tri state mode chan
31. as the logical SpaceWire router does not have a logical address address Transaction The transaction identifier identifies the command packet and reply packet with a Identifier unique number The transaction identifier in the reply packet is copied from the command packet and returned in this field so that the command and the corresponding reply have the same transaction identifier value Data The data length field is set to 4 bytes as this is a single read command Length Header The header CRC used to detect errors in the header part of the command CRC packet See section 7 6 7 for CRC generation The data read from the registers in the device Data CRC The data CRC used to detect errors in the data part of the reply packet See 1 section 7 6 7 for CRC generation 7 6 3 Read Incrementing Command The read incrementing address characteristics of the SpaceWire router are defined in Table 7 8 62 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual n SpaceWire Router K School of Computing Issue 3 5 omg User Manual Date 7 January 2015 Austrian Aerospace Table 7 8 Read Incrementing Address Characteristics Supported Maximum number Non aligned access of bytes accepted Not Supported 8 bit read 32 bit read The RMAP read incrementing address command is supported in the SpaceWire router The read incrementing address is used to read a continuous block of registers from the SpaceWire router e g the
32. bias resistor values are determined as follows 1 Determine the amount of noise protection required E g if the maximum noise voltage expected is less than 10 mV then the bias current required is lb 10 mV 100 Q 0 1 mA Note the bias current should be at least an order of magnitude lower than the 3 mA current loop used for normal LVDS operation 2 Determine the total resistance Ra from bias supply Von to ground Rs Vpp bb E g Rs 3 3 V 0 1 mA 33 KQ Since Rr is much smaller than this value it can be ignored 3 Determine the ratio of R2 to the total resistance Re The line common mode voltage Von should be 1 25 V so the ratio of R2 to Rs is R2 Rg 1 25 V 3 3 V 0 379 4 Calculate the value of R2 and round down to a standard value E g R2 0 379 x 33 kQ 12 5 kQ so the nearest standard value is 12 kQ E24 series 5 Now recalculate the value of Re to give the required line common mode voltage E g Ra 12kQ 0 379 V 31 6 kQ 6 Calculate the value of R1 R1 Re R2 and round to a standard value E g R1 31 6 kQ 12 KQ 19 6 kQ so the nearest standard value is 20 kQ E24 series or 19 6 KQ E48 series 7 Check the maximum noise voltage and common mode voltage E g Vn 3 3 V x 100 Q 32 KQ 10 3 mV and Vom 3 3 V x 12 KQ 32 KQ 1 24 V If the noise on the disconnected inputs is likely to be higher than 10 mV then other resistor values need to be calculated For further details see RD1 and
33. connected to this input if External FIFO port 9 is not being used ut In EXT10 OUT DATA 8 ut Output data from external port number two CMOS3V3 EXT10 OUT DATA 7 FIFO Bit eight determines the type data EXT10 OUT DATA 6 eop or eep The encodings are defined as EXT10 OUT DATA 5 EXT10 OUT DATA 4 Bits EXT10 OUT DATA 3 dddddddd Data byte EXT10 OUT DATA 2 XXXXXXX0 EOP EXT10 OUT DATA 1 XXXXXKX1 EEP EXT10 OUT DATA 0 Bit 7 is the most significant bit of the data byte In In 124 EXT9 IN FULL N FIFO ready signal for external input port zero CMOS3V3 127 EXT9 IN WRITE N 139 EXT10 OUT EMPTY N Out FIFO ready signal for external output port one CMOS3V3 When high the FIFO has data When low the FIFO is empty EXT10 OUT READ N Asserted low to read from the external output CMOS3V3 port one FIFO A pull up resistor e g 4k7 Q should be connected to this input if External FIFO port 10 is not being used EXT10 IN DATA 8 Input data to external port number two FIFO CMOS3V3 EXT10 IN DATA 7 Bit eight determines the type data eop or EXT1 IN DATA 6 eep The encodings are defined as EXT10 IN DATA 5 EXT10 IN DATA 4 40 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 Pran User Manual Date 7 January 2015 Austrian Aerospace EXT10 IN DATA 3 0 dddddddd Data byte EXT10 IN DATA 2 1 XXXXXXX0 EOP EXT10 IN
34. in section 0 Table 7 1 Packet Address Mapping Packet Address Expected Packet Type Physical Port type Command packet Any ype Any ype Any ype Any ype Any ype Any ype Any ype Any ype Any ype Any ype NA Any pe Note that logical address 255 is reserved in the SpaceWire standard AD1 I 54 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual on SpaceWire Router K School of Computing Issue 3 5 Bam User Manual Date 7 January 2015 Austrian Aerospace 7 2 PACKET PRIORITY Each packet which is input to the router has an associated priority level either as a result of the packet address or the internal routing table Two priority levels HIGH and LOW are supported The table below defines the priority levels for packet addresses Table 7 2 Packet Priority Mapping Packet Address Packet Priority Physical Port type Configuration por SpaceWie ink por SpacaWire lnk por 2 SpaceWire nk por 3 SpaceWire nk por 4 SpaceWire ink por 5 SpaceWire ink por 6 SpacoWire ink por 7 SpaceWire ink por 8 vac addresses Dependent on routing table Logical addresses Default LOW May be configured HIGH see section 9 3 7 3 PACKET HEADER DELETION Header deletion is performed on packets dependent on the packet address Packets which have path addresses or logical addresses which have the header deletion bit set in the routing table have the header address byte removed before the packet is routed to the destination
35. logic For example if input port 2 is transferring data to output port 1 and input ports 5 and 7 are waiting to transfer data to port 1 then port 5 will selected next Packets which have high priority are always selected before low priority packets in the router If two or more packets of the same priority level are attempting to use the same destination port then the packets are arbitrated in a fair manner Note that router configuration packets both commands and replies are treated the same as any other packet as far as arbitration is concerned The arbitration scheme is equally applicable to all types of packets with no exceptions When sending long packets arbitration can cause substantial delays in transferring information The following sub sections illustrate the various scenarios where arbitration is necessary 8 3 2 1 Arbitration of packets with matching priority 1 In the Figure 8 6 an example of arbitrating between packets with the same priority is illustrated Only router ports 1 5 are shown for clarity At stage one input ports 1 and 3 have packets to be routed to output port 5 The previous input port to use output port 5 was input port 3 therefore the next input port to be selected by output port 5 will be input port 1 assuming input ports 6 7 8 9 10 and 0 are not requesting to use output port 5 At stage two the router selects the packet arriving at input port 1 and the packet is routed through Output port 5 Input p
36. packet type 23 20 Not Used Source logical The source logical address error bit is set when address error an invalid source logical address is received a SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 weus User Manual Date 7 January 2015 Austrian Aerospace 9 4 3 SpaceWire port control status register bits The port control status fields specific to SoaceWire ports are shown in Figure 9 3 and Table 9 6 31 28 27 24 23 22 16 15 12 11 8 7 0 Error Status Interface State Interface Control Transmit Rate Not Used Arbiter Connection Port Type Figure 9 3 SpaceWire Port Control Status Register Fields Note Error status bits are cleared by writing to the Error Active register see section 9 5 4 114 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual on SpaceWire Router K School of Computing Issue 3 5 Bam User Manual Date 7 January 2015 Austrian Aerospace Table 9 6 SpaceWire Port Control Status Register Fields Name Reset Value Description The error active bit is set when one of the error bits are set Packet address error Read Write The packet address error bit is set when a packet is received with an incorrect address Output port timeout error The output timeout error bit set when the output port has become blocked for a period of time The disconnect error bit is set when a disconnect error occurs on the
37. router port the packet arrived on For example if SoaceWire port 1 passed a configuration command to the configuration port then the reply packet is returned to port 1 7 6 9 Source Path Address Field The RMAP command field source path address length indicates the number of source path addresses which are expected in the packet Up to 12 source path addresses can be accepted by the router configuration port The source path addresses shall be decoded by the SpaceWire router as follows 78 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 Pran User Manual Date 7 January 2015 GH Austrian Aerospace e Leading zero source path address bytes are not returned in the RMAP reply packet e If the source path address contains only zero bytes the Source Path Address Sequence error is reported see section 7 6 6 e After the first non zero byte in the packet any following zeros shall be treated as an error source path address sequence Is reported see section 7 6 6 The table below gives some examples of how to set the source path address length and packet address fields for the required path addresses Table 7 18 Source Path Address Reference Table Source Path Address RMAP Source Path Address fields Reply Path Address Length First gt Last Transmitted First gt Last Reply None None 0 00 00 00 20 Z 00 00 00 00 00 00 00 02 00 00 00 00 101 02 03 02
38. routes the packet to the configuration Address port of the router The configuration port address is always present when configuring the SpaceWire Router Destination The destination logical address is not used in the SpaceWire Router The Logical SpaceWire router accepts packets which have the default destination logical Address address of 254h FEh Protocol The RMAP protocol identifier is 01h Identifier Command The command byte indicates a read incrementing packet The Source path Byte address length fields are set to the number of source path addresses required as defined in section 7 6 9 DUNDEI Destination Key Source Path Address Source Logical Address Transaction Identifier Extended Read Address Read Address Data Length Header CRC SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router School of Computing Issue 3 5 User Manual Date 7 January 2015 GH Austrian Aerospace The destination key identifier must match the contents of the destination key register see section 9 5 10 The source path address field is used to add source path addresses to the head of the reply packet The expected number of source path addresses is specified in the command byte See section 7 6 9 for source path address decoding The source logical address should be set to the logical address of the node which sent the command or it should be set to the default value of FEh The t
39. signals in that interface These tables have the following fields Pin No The device pin number Signal The name of the signal Dir The direction of the signal in out or in out Description An explanation of what the signal does Type The type of signal The sections below define the pin out of the SpaceWire router Its interfaces are split into several types separated by headings for clarity 5 1 Global signals clock and reset 5 2 SpaceWire interface signals 5 3 External port signals 5 4 Time code interface signals 5 5 Configuration signals 5 6 Reset configuration signals 5 7 Power and Ground The following signal types are used in the SpaceWire Router CMOS3V3 3 3 Volt CMOS logic LVDS Low Voltage Differential Signal 3V3 3 3 Volt power GND Ground 5 1 GLOBAL SIGNALS The global system clock and reset signals are listed in Table 5 1 33 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router School of Computing Issue 3 5 User Manual Date 7 January 2015 Table 5 1 Global Signals pej ise in e System clock Provides the reference clock for all CMOS3V3 modules except the interface receivers RST_N Asynchronous system reset active low CMOS3V3 4 TestlOEn In ASIG Test control signal Shall be connected to CMOS3V3 logic 0 during normal operation Internal pull down Tie to ground ASIC Test control signal Shall be connected to CMOS3V3 logic 0 during n
40. the priority of the logical address when packets waiting at two input ports wish to use the same output port 1 high priority 0 low priority The INVALID_ADDR bit is set to indicate that the corresponding logical address is not valid Table 9 3 describes each field in the GAR register 108 ASTRIUM K School of Computit DUNDEI 6 GH Austrian Aerospace SpW 1 OX Ref UoD_SpW 10X_ i UserManual SpaceWire Router Issue 3 5 User Manual Date 7 January 2015 Table 9 3 GAR Table Register Description Address Range 32 255 0x0000 0020 0x0000 OOFF Reset Description Read Write Value 10 1 28 11 D CA NO O RESERVED REQUEST NOT USED DEL_HEAD PRIORITY INVALID_ADDR oC Reserved bit always set to zero Undefined after power on Unaltered by reset The request bits determine which output ports R W the logical address will arbitrate for When bit 1 is set then SpaceWire port 1 will be requested When bit 2 is set then SpaceWire port 2 will be accessed and so on By setting more than one bit group adaptive routing can be used allowing the input packet to arbitrate for more than one output port If a write is performed and bits 10 1 are set to zero then the INVALID ADDR bit will be set and all other bits will be set to zero Note The configuration port port 0 is not accessible through logical addresses Undefined after power on Unaltered by reset
41. use The figure below shows the effect of the deactivate bit when the link setting is Auto start only 82 SpW 1 OX Ref UoD_SpW 10X_ DS ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 eg User Manual Date 7 January 2015 Austrian Aerospace Disconnect Return NULLs Data Received Detected Deactivated Deactivated DOUT Deactivated Deactivated SOUT Ei A hi NULL received DS reset Activate output Deactivate output Connection made Data Transfer Disconnect DIN SIN Figure 8 1 Deactivate driver operating mode Note the DOUT deactivate driver disable is performed one CLK cycle before the SOUT deactivate avoiding any simultaneous transitions on Data or Strobe When the LVDS drivers are deactivated the equivalent circuit of these outputs is a shown in Figure 8 2 3 V Vdd Se 28500 Out Out Deactivated NMOS Transistors off 17250 Vss Figure 8 2 Deactivated LDVS driver output When external bias resistors are being used see section 5 2 2 and a deactivated LVDS output is connected to a powered LVDS input with external bias resistors the equivalent circuit is as shown in Figure 8 3 83 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual n SpaceWire Router K School of Computing Issue 3 5 User Manual Date 7 January 2015 Austrian Aerospace Vdd R 100 Q 99uA 304v Figure 8 3 Deactivated LDVS driver output connected to external bias net
42. zero 6 bit time code value PRO 9 5 6 Device Manufacturer and Chip ID Register The device manufacturer and chip ID register address is 261 0x0000 0105 This register contains three eight bit fields which hold a device manufacturer identity chip identity and version number The fields of the device manufacturer and chip ID register are shown in Figure 9 8 and described in Table 9 13 31 24 23 16 15 8 7 0 Version number Chip ID code Manufacturer Code Not used Figure 9 8 Device Manufacturer and Chip ID Register Fields Table 9 13 Device Manufacturer and Chip ID Register Fields 7 0 Version Version Number of Version number of the chip design Number chip design 15 8 Chip ID Code Chip type Identity code for the SpaceWire chip from the particular manufacturer 23 16 Manufacturer Manufacturer identity Manufacturer identity code code 00000000 Unknown Manufacturer 00000001 University of Dundee 124 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 Austrian Aerospace 9 5 7 General Purpose Register The general purpose register address is 262 0x0000 0106 The general purpose register contains 32 bits and may be set by a configuration write command to a user defined value as required It may also be read with a configuration read command The general purpose register has no effect on the operation of the rou
43. 0X ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 Austrian Aerospace configuration memory address range of the GAR table is 32 255 0x0000 0020 0x0000 00FF The configuration memory address corresponds to the logical address hence the GAR table entry at address 39 corresponds to logical address 39 The logical address to port mapping is held in the REQUEST field Each bit in this field represents a physical output port thus up to 28 possible output ports can be specified using the GAR register although only 10 ports plus the configuration port are provided in the SpW 10X The configuration port is port number 0 the SpaceWire ports are port numbers 1 to 8 and the External ports are ports 9 and 10 When a bit is set in the REQUEST field packets may be routed to the corresponding output ports The port number corresponds to the bit position in the GAR register For example if configuration memory address 39 has bit 2 set then a packet with logical address 39 may be routed out of port 2 If bits 2 and 4 are both set then the packet may be routed out of either port 2 or 4 Port 0 the configuration port is a special port which can only be accessed using address 0 so this bit position in the GAR table registers is reserved and will always be set to zero The DEL_HEAD bit when set causes the leading byte header of a packer to be deleted The PRIORITY bit determines
44. 15 GH Austrian Aerospace c Figure 8 19 Destination Node Blocked Watchdog Mode c d The packet waiting at routing switch R1 port 2 is routed and the network blockage is cleared Routing switch R2 port 5 still has data waiting to be sent followed by the end of packet therefore packets routed to port 5 will again cause a blockage which will be cleared again in the same manner until the fault is detected by a higher level protocol ma oy d d Figure 8 20 Destination Node Blocked Watchdog Mode d 8 3 5 2 Stalled source A source of a SpaceWire packet can stall for some reason and stop sending data part way through sending a packet A router will see this situation as an input port which has stalled no longer sending data part way through sending a packet although the SpaceWire link is still running This situation can occur due to an error in the network or in the node that was providing data In blocking allowed mode the network path will be blocked until the source node supplies the end of packet Other packets waiting to use the network path will wait indefinitely In watchdog timer mode the routers will timeout and the network path will be cleared so other packets can use the path Blocking Allowed The sequence of events when a source is stalled and Blocking Allowed mode is being used is illustrated in Figure 8 21 to Figure 8 24 a A packet arrives at routing switch port 3 with destination address 4
45. 2 1 R2 2 Packet with Connection Attempt cc address 2 1 R 2700s 2 Link Started and Data Transfer 2 Figure 8 4 Start on Request mode 8 2 2 Disable on Silence mode The Disable on Silence mode is enabled by setting the CFG_DISABLE_ON_SILENCE bit in the router control register The input signal POR_DISABLE_ON_SILENCE_N determines the power on or reset state of the CFG_DISABLE_ON_SILENCE bit Figure 8 5 illustrates operation in the Disable on Silence mode 87 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 User Manual Date 7 January 2015 Austrian Aerospace Auto Start default mode O and Start on Request enabled and Disable on Silence enable in both routers 1 R1 2 1 R2 2 D OG 2 1 R2 2 Packetwith Connection Attempt address 2 1R 2A l 222 Link Started and Data transfer 1 RI 2 UW SSS SNY Data transfer completed Link Disabled after timeout period O Figure 8 5 Disable on Silence mode The SpaceWire router Disable on Silence mode is used to disable a SpaceWire link when it no longer has any data to transfer The Disable on Silence mode is enabled only when the router timeouts are enabled The SpaceWire port is disabled if no data or end of packet character has been transmitted for the timeout period set in the router control register The SpaceWire router will only disable a SpaceWire port when the SpaceWire router is the source of the
46. 5 which will route to routing switch R2 port 5 Another packet arrives which is destined for routing switch R2 port 4 100 SpW 1 OX Ref UoD_SpW 10X__ ASTRIUM i UserManual n SpaceWire Router K School of Computing Issue 3 5 User Manual Date 7 January 2015 Austrian Aerospace Figure 8 21 Source Node Stalled a b The packet from routing switch R1 port 3 is routed towards its destination but during packet transfer the source node stalls and does not supply any further data or the end of packet Figure 8 22 Source Node Stalled b c The packet is blocked and the packet waiting at routing switch R1 port 2 cannot be routed Figure 8 23 Source Node Stalled c d After an undetermined time the source node supplies the remaining data and end of packet and the packet waiting at R1 2 can be routed Figure 8 24 Source Node Stalled d Watchdog Timer Mode What happens when a source stalls and Watchdog Timer mode is being used is illustrated in Figure 8 25 to Figure 8 28 a A packet arrives at routing switch port 3 with destination address 4 5 which will route to routing switch R2 port 5 Another packet arrives which is destined for routing switch R2 port 4 101 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual n SpaceWire Router K School of Computing Issue 3 5 User Manual Date 7 January 2015 Austrian Aerospace a Figure 8 25 Source Node Stalled Watchdog Mode a b The packe
47. DATA 1 1 XXXXXXX1 EEP EXT10 IN DATA 0 Bit 7 is the most significant bit of the data byte Pull up resistors e g 4k7 Q should be connected to these inputs if External FIFO port 10 is not being used EXT10 IN FULL N FIFO ready signal for external input port one CMOS3V3 When high there is space in the FIFO so it can be written to When low the FIFO is full EXT10 IN WRITE N Asserted low to write to the external input CMOS3V3 port one FIFO A pull up resistor e g 4k7 Q should be connected to this input if External FIFO port 10 is not being used See section 6 1 for information on the operation of the external ports and section 10 3 for timing details 5 4 TIME CODE SIGNALS The time code interface signals are listed in Table 5 4 The timing of this interface is shown in Figure 6 3 and Figure 6 4 Table 5 4 Time Code Signals e EE EST TICK IN The rising edge of the EXT TICK IN signal is used CMOS3V3 to indicate when a time code is to be sent On the rising edge of the EXT TICK IN signal the SEL EXT TIME signal is sampled to determine if the time code value is to be provided by the internal time counter or by the external time input EXT TIME IN 7 0 The SEL EXT TIME and the EXT TIME IN 7 0 signals must be set up prior to the rising edge of EXT TICK IN and must be held static sometime afterwards See section 10 4 for timing details If the time code port is not being used this input 41 SpW 1 OX Ref U
48. DUNDEI Enable start on request Enable Self Addressing User Manual GH Austrian Aerospace Set by the input signal POR_START_ON_REQ_N Set by the input signal POR_ADDR_SELF_N SpaceWire Router Ref UoD SpW 10X UserManual Issue 3 5 Date 7 January 2015 the link using autostart or the link is started by configuration command then the port will not be disconnected on silence Events which cause the disconnect on silence timeout to be reset are e Input port data read e Output port data write When set the arbiter will request the SpaceWire output port to start up if the router receives a packet destined for the output port Note if the output port link disable bit is set then the link will not start When set input ports are permitted to address themselves If this bit is not set and a packet is to be routed through the same port then an address error is reported and the packet is discarded When this bit is not set and a group adaptive routing packet is received a packet which can be routed through two or more ports dependent on the group adaptive routing table contents which can be routed through the port it arrived on then the packet is routed through one of the other ports and not the port on which the packet arrived on An address error is not reported K 121 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual n SpaceWire Router K School of Computing Issue
49. E 8 18 DESTINATION NODE BLOCKED WATCHDOG MODE pi 99 FIGURE 8 19 DESTINATION NODE BLOCKED WATCHDOG MODE CH 100 FIGURE 8 20 DESTINATION NODE BLOCKED WATCHDOG MODE oi 100 FIGURE 8 21 SOURCE NODE STALLED A rririssossciniasii n enidan ne a a ai adada aiaia 101 FIGURE 8 22 SOURCE NODE STALLED E 101 FIGURE 6 25 SOURCE NODE STALLED sen 101 FIGURE 8 24 SOURCE NODE STALLEDOD 101 FIGURE 8 25 SOURCE NODE STALLED WATCHDOG MODE OO 102 FIGURE 8 26 SOURCE NODE STALLED WATCHDOG MODE OO 102 FIGURE 8 27 SOURCE NODE STALLED WATCHDOG MODE CH 102 FIGURE 8 28 SOURCE NODE STALLED WATCHDOG MODE i e 102 FIGURE 9 1 ROUTER INTERNAL MEMORY Map 105 PIGURE 9 2 GRETA NN 107 FIGURE 9 3 SPACEWIRE PORT CONTROL STATUS REGISTER bn 114 FIGURE 9 4 NETWORK DISCOVERY REGISTER FL ps 118 FIGURE 9 5 ROUTER CONTROL REGISTER FIELDS rorrrrrrrrronrrnnnnnnnrrrnnrnnnnnnnnnrnnnrnnnnnnnnsnnnrnnnnnnennnennnnnnnnnesssennsnnnnneee 119 FIGURE 9 6 ERROR ACTIVE REGISTER FIELDS sssnnnnnsossseeeeessssseeterosssssrereossssseereeossssseereossssseeerossssssreeeosssseeereess gt 122 FIGURE 9 7 TIME CODE REGISTER FIELDS rronrnrrnrnnnnnrrnnnnnnnnrnrnnnnnnrnnnnnnnnsrnnrnnnnnsnnnnnnessnnsnnnensnnnnnnessnnsnnnessensnnnessnnnnn 123 FIGURE 9 8 DEVICE MANUFACTURER AND CHIP ID REGISTER FIELDS ssnnesseensseeesseesssersseresssersseresssersseressseres 124 FIGURE 9 9 TIME CODE ENABLE REGISTER bs 125 FIGURE 9 10 TRANSMIT CLOCKCONTROLRPOISTER 127 FIGURE 10 1 DS MINIMUM CON
50. EC MIM sacar ieee ei le ec 149 E e FEN NNN 149 13 4 PARITY ERROR ANOMALY aannnannnnennsnnnnsnnnsrrrnrrrrsrrrrsrrrntrrrsrrretrrrsrrrrrrrrstrrrrrrrsrrrrsrrrenrrene 150 BON Wally ENN 150 13 4 2 Parity Error ANOMALY ccc ccccc cece cece eee ee cece cece ence neces essen eee ee dessa eesaeesa esse eeseeseneseneeseeesneees 150 17 FFO VTS 151 E TECHNICAL Te A WE 152 To DOCUMENT CHANGES eege 153 1541 ISSUE GA TO ISSUE e n E R 153 152 ISSUE 33 KE 153 BER TEEN 6 ene nene nen an enon none E 153 194 LE Ost TO ISSUE vvs 154 15 5 IGGUE20OTIOIGSUE T rrene 154 Bo BE TOER 155 Tod BLE NTE E 155 15 8 ISSUE 23 TOISSUE 24 wx serrcerssensssenoecesnonpsenctvesvousisuoisesenupsnesipenenensanevensmmptnentpenmunadenaenenenuads 155 199 BUE TC ISSUE 2 Leve jadsaede 156 15 10 ISSUE 21 TO ISSUE eegene 156 B l EE ZOTO UE a 156 TA P VET7F TAO eege gegen 156 AS BET BEL na 156 15 14 BLE TS TOISSUE 1 6 EE 156 15 15 ISSUE 14 TO ISSUE 1 eeen E EE 156 9 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 GH Austrian Aerospace 15 16 15 17 15 18 15 19 EI EC TOI UE Tie E E E E E E E E E E E geaeeutees E 157 ISSUE 1 2 TO ISSUE io senanima EN E ERRE 157 O GETT EOI UE Toe ree ere ere re ee ee 157 SSVE LIT DENN 157 10 SpW 10X Ref UoD_SpW 10X_ EADS ASTRIUM i UserManual e SpaceWire Router ER School of Computing Issue 3 5 Krag User Ma
51. Identifier LS rigselned FEh 00h Data Length MS Data Length Data Length LS 00h 00h 04h Header CRC Last byte transmitted Bits in Packet Type Command Source Path Address Length Byte LSB MSB Address Length Address Length _ Packet Type Se Command T Source Path Address Length Figure 7 9 Read Modify Write Reply Packet Format Table 7 13 Read Modify Write Reply Packet Fields Source Path Optional source path addresses specified in the command packet If no Address source path addresses are specified then the first byte will be the source logical address Source Logical The source logical address specified in the command packet If source 1 Address path addresses are not used then the source logical address is the address of the return packet Protocol Identifier The RMAP protocol identifier value 01h Command Byte Read Modify Write reply command byte The packet type bits in the 1 command byte indicate this packet is a response packet Status The command status is returned in this field The command status can be 1 command successful or an RMAP error code as defined in section 7 6 6 The destination logical address is set to the default value FEh as the 71 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual n SpaceWire Router K School of Computing Issue 3 5 omg User Manual Date 7 January 2015 Austrian Aerospace logical address SpaceWire router does not have a logical address
52. Instrument 3 Memory Unit A Figure 2 1 Stand Alone Router In Figure 2 1 an example of use of the SpW 10X device as a stand alone router is illustrated There are four instruments connected to the SoW 10X device along with a memory unit and processor The processor can communicate with all the instruments and memory unit to control them and is also able to configure the SpW 10X device The instruments can send data to the memory unit for storage or to the processor for immediate processing The processor can also read data from the memory for later processing writing the processed data back into memory pair of SoW 10X devices can be used to provide a redundant configuration 18 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 Pran User Manual Date 7 January 2015 GH Austrian Aerospace 2 2 NODE INTERFACE The SpaceWire Router has two external ports which enable the device to be used as a node interface The equipment to be connected to the SpaceWire network is attached to one or both external ports One or more SpaceWire ports are used to provide the connection into the SpaceWire network Unused SpaceWire ports may be disabled and their outputs deactivated to save power In this arrangement configuration of the routing tables and other parameters may be done by sending configuration packets from the local host via an external port or from a remote network manager via a Space
53. LY PACKET FIELDS sermnnnnnrnnnnnrrnnnnernnnnnernnnnenennnnernnnnnsnnnnnenennnnenennnnsennnnenennn ol TABLE 7 8 READ INCREMENTING ADDRESS CHARACTERISTICS remmrnnerrnnnnernnnnnrrnnnnerennnnernnnnsernnnnenennnnennnnnnesnnnnenenen 63 TABLE 7 9 READ INCREMENTING ADDRESS COMMAND PACKET bLDg 64 TABLE 7 10 READ INCREMENTING ADDRESS REPLY PACKET bp 66 TABLE 7 11 READ MODIFY WRITE COMMAND CHARACTERISTICS rerrnnnnerrnnnnrrnnnnerennnnernnnnnernnnnerennnnenennnnernnnnenennn 67 TABLE 7 12 READ MODIFY WRITE COMMAND PACKET FIELDS scccccsecceesseccceeseceeaeecceeueceeaeeecesaeeceesueeceeees 69 TABLE 7 13 READ MODIFY WRITE REPLY PACKET EIDA 71 TABLE 7 14 WRITE COMMANDCHARACTRRISTICR 72 TABLE 7 15 WRITE SINGLE ADDRESS COMMAND PACKET buppe 73 TABLE 7 16 WRITE SINGLE ADDRESS REPLY PACKET bIELDg 75 TABLE 7 17 CONFIGURATION PORT ERRORS SUMMARNY 76 TABLE 7 18 SOURCE PATH ADDRESS REFERENCE IABLE 79 TABLE 8 1 SETTING SPACEWIRE TRANSMIT DATA RATE 85 TABLE 9 1 TYPES OF REGISTER WITHIN CONFIGURATION PORT 106 TABLE 9 2 CONFIGURATION REGISTER ADDRESSES rarnnnnnnnnnrrnvnnnnnnnnnnnnnnnnnvnnnensnnnnnnnnnennnnnensnnnnnnensnnrnnnensennnnnensennnn 107 TABLE 9 3 GAR TABLE REGISTER DESCRIPTION ronnnrrnrrrnnrrnnnnnnnrnrnnrnnnnnnnnrrnnnrnnnnnennsrnnnnnnnnnennnnnnnnnnnnnessnennrnnnnneee 109 TABLE 9 4 CONFIGURATION PORT CONTROL STATUS REGISTER bn 110 TABLE 9 5 CONFIGURATION PORT CONTROL STATUS REGISTER FIELDS rorrrrrrnnnnrrrnrnnnnnrrnnnnnnerrnnnnnn
54. NOMALIES AND WARNINGS In this section a list of anomalies and warnings is provided 13 1 ANOMALIES The following anomalies are present in the prototype SpW 10X router device 1 Simultaneous transitions on data and strobe can occur during reset and power up This may be a problem when operating with legacy IEEE 1355 devices but is not a problem when operating with SpaceWire compliant devices See section 13 3for further details on this anomaly 2 When a parity error in a data character the following characters may be received before the link disconnects 13 2 WARNINGS Various warnings appear in boxes throughout this document They are all gathered in this section for convenience WARNING Simultaneous data strobe transitions can occur during reset and power up This is not a problem when connected to SpaceWire compliant devices but is a problem when connected to IEEE 1355 devices WARNING Since LVDS is based on a current loop it should not matter what the supply voltage is to an LVDS device connected to the SpW 10X router However there is a potential problem when connecting to devices with power supplies greater than 3 3 V which is the supply voltage of the SoW 10X device It should be emphasised that during normal operation there is no problem but if the LVDS device connected to the SpW 10X device can fail in such a way as to put a higher voltage than 3 3 V on to the pins of the SpW 10X device then this can cause a problem The
55. ON In this section the time code interface operation is defined EXT TICKIN TN gt SEL EXT TIME MM MM MA MM MM MAMA l 00000000000N000N l EXT_TIME_IN AA SAA AAA AAA MAMMA MAMMA Time code inputs Internal time code EXT TIME IN counter used for time code used for time code Figure 6 3 Time Code Input Interface Time codes can be generated by the router on request of the external system to which it is attached A time code is generated whenever the router detects a rising edge on the EXT TICK IN signal as illustrated in Figure 6 3 The value of the time code to be transmitted is either taken from the inputs or from the time code counter inside the router The time code source used depends on the value of the 50 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 Pran User Manual Date 7 January 2015 Austrian Aerospace SEL EXT TIME signal when EXT TICK IN signal has a rising edge If SEL EXT TIME is 1 then the EXT TIME IN 7 0 inputs are used to provide the contents of the time code If SEL EXT TIME is 0 then the internal time code counter provides the least significant 6 bits of the time code and the EXT TIME IN 7 6 inputs provide the most significant 2 bits When using the EXT TIME IN 7 0 inputs to provide the complete time code the time code is only broadcast if it is a valid time code i e if the count in bits 5 0 is one more
56. OX Ref UoD_SpW 10X_ ASTRIUM i UserManual e SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 Austrian Aerospace PORN No vDD LL Bond Decoupling Capacitors Figure 5 3 PLL with external components The PLL loop filter component values to be used are R 10kQ C 120 pF CO 3 3 pf The VCO bias resistor depends on the required VCO frequency range which is determined by the PLL feedback divider NF in Figure 5 3 The VCO bias resistor values to use are Rvco 4 7 kQ for 100 150MHz FEEDBDIV 0b000 0b001 or 0b010 Rvco 1 8 KQ for 150MHz 200MHz FEEDBDIV 06011 06100 06101 or 06110 or 0b111 See section 5 1 for information about the FEEDBDIV inputs A dedicated decoupling capacitors 100 nF and 1uF are required for the PLL power supply 48 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 GH Austrian Aerospace 6 INTERFACE OPERATIONS This section describes the operation of the external FIFO port time code interface and status power on configuration interface First a note on the terminology used Signals are given a name e g EXT IN FULL and a logic level e g N The term asserted is used when the signal state reflects the signal name e g EXT IN FULL is asserted when the external input FIFO is full The term de asserted is used when the signal state is the invers
57. Path Address Length Byte LSB MSB Se e e e o L Address Length Address Length je Packet Type EE Command gt Source Path Address Length Figure 7 11 Write Single Address Reply Packet Table 7 16 Write Single Address Reply Packet Fields AY D Source Optional source path addresses specified in the command packet If no source Path path addresses are specified then the first byte will be the source logical Address address Source The source logical address specified in the command packet If source path Logical addresses are not used then the source logical address is the address of the Address return packet Protocol The RMAP protocol identifier value 01h 1 Identifier 19 Command Write single address reply command byte The packet type bits in the command Byte byte indicate this packet is a reply packet Status The command status is returned in this field The command status can be command successful or an RMAP error code as defined in section 7 6 6 Destination The destination logical address is set to the default value FEh as the logical SpaceWire router does not have a logical address SpW 1 OX Ref UoD SpW 10X ASTRIUM i UserManual n SpaceWire Router K School of Computing Issue 3 5 omg User Manual Date 7 January 2015 Austrian Aerospace Transaction The transaction identifier identifies the command packet and reply packet with a 2 Identifier unique number The transaction identifier in th
58. Port Indicates that the Error Active bit in the R W Error Active configuration port is asserted A write to this register with bit 0 set will clear all the error flags in the configuration port control status register NW 10 1 SpaceWire and All bits Indicates that the Error Active bit in the R External Port Error set to corresponding number SpaceWire or External Active Zero port is asserted A write to this register with one or more of these bits set will clear all the error flags in the corresponding SpaceWire and External port control status registers When writing to this register with all bits set all error flags in all port control status registers are cleared Note only bits 10 1 are used in the SoW 10X router 31 11 Not used All bits Not used because there are a maximum of 30 set to SpaceWire External ports supported by the zero router design 9 5 5 Time Code Register The time code register address is 260 0x0000 0104 The time code register contains the current value of the internal time code register Its fields are shown in Figure 9 7 and described in Table 9 12 31 8 7 6 5 0 Time value Time code flags Not used Figure 9 7 Time Code Register Fields 123 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual n SpaceWire Router K School of Computing Issue 3 5 omg User Manual Date 7 January 2015 Austrian Aerospace Table 9 12 Time Code Register Fields Reset Value Read Write All bits set to
59. R sesssssesssssessossossesrossesresreseessessosrossosrese 151 LIST OF TABLES TABLE 1 1 APPLICABLE DOCUMENT 16 TABLE 1 2 REFERENCE DOCUMENTS ssscccsssszcacesevscanseansenobsaneoaeessnasannbanasansndinaenoesaesoasaniniganwiensonieedeignebaagesauniinsennseetses 17 dE ped Gt ee E 34 TABLE 5 2 DATA AND STROBE SPACEWIRE SIONALS 35 TABLE 5 3 EXTERNAL PORT INTERFACE SIGNALS rornnrrnrrrnnrnnnnnnnrrrrnrrnnnnnnnsrnnnrnnnnnnnnsennnnnnnnnnnnnnnnnnnnnnnnnssnnnnnnnnnnnnnenn 39 TABLE 5 4 TIME CODE SIGNALS siririna rennin reina EAEE E AAE A AEO 41 TABLE 5 5 LINK ERROR INDICATION SIGNALS ossnnnnrnnnnnnnnrrnnrrnnnnennnnnnnrnnnnnnnnennnrnnnnnennnnnnnnnnnnnennnennrnnnnnnnnnnennnnnnnnennnene 43 TABLE 5 0 RESET RO TER MR RTE 45 TABLE 5 7 POWER GROUND AND SPECIAL SIONALS 47 TABLE 6 1 MULTIPLEXED STATUS PINS BIT ASSIGNMENT rorrrrnrrrrnrrnnnnnnnrrnnnrnnnnnnnnsrnnnnnnnnnensnnnnrnnnnnnnnnennnnnnnnnnnnnene 52 TABLE 1 PACKET ADDRESS MAPPING is scininavsnnctennnddudapwisinactosesductevesansyysnidadapesstendeounssaddowessucypnwstadansevonshoneataliouosans 54 TABLE PACKET PRIORITY MAPPING ve 55 TABLE 7 3 PACKET HEADER DELETION Mapp 56 TABLE 7 4 SUPPORTED RMAP COMMAND CODES rornrrnnrrnnrrnnnnnnrrrrnrrnnnnnnnnrrnnrnnnnnnnnsnnnnnnnnnnensnennrnnnnnnnnssennrnnnnnsnnnene 58 TABLE 7 5 READ SINGLE ADDRESS CHARACTERISTICS prcrisiissirsrinsner sakane es eisso Ra PN ETEEN ESAR EEEE 59 TABLE 7 6 READ SINGLE ADDRESS COMMAND PACKET bs 60 TABLE 7 7 READ SINGLE ADDRESS REP
60. RD2 38 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual on SpaceWire Router K School of Computing Issue 3 5 Bam User Manual Date 7 January 2015 Austrian Aerospace 5 2 3 Operation with 5V Powered LVDS Devices WARNING Since LVDS is based on a current loop it should not matter what the supply voltage is to an LVDS device connected to the SpW 10X router However there is a potential problem when connecting to devices with power supplies greater than 3 3 V which is the supply voltage of the SpW 10X device It should be emphasised that during normal operation there is no problem but if the LVDS device connected to the SpW 10X device can fail in such a way as to put a higher voltage than 3 3 V on to the pins of the SpW 10X device then this can cause a problem The simplest way to overcome this potential problem is to ensure that the LVDS devices driving the SpW 10X device are all powered by 3 3V 5 3 EXTERNAL PORT DATA SIGNALS The External port signals are listed in Table 5 3 The timing of these signals is shown in Figure 6 1 External port write timing specification and Figure 6 2 External port read timing specification Table 5 3 External Port Interface Signals pono signs nem w EXT9 OUT DATA 8 Output data from external port number one CMOS3V3 EXT9 OUT DATA 7 FIFO Bit eight determines the type data EXT9 OUT DATA 6 EOP or EEP The encodings are defined as EXT9 OUT DATA 5 EXT9 OUT DATA 4 EXT9 OUT DA
61. Router 7 6 1 Supported Commands The RMAP Command set is listed in Table 7 4 and the supported RMAP commands are defined The commands which are not used are depicted with a grey background 57 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual on SpaceWire Router K School of Computing Issue 3 5 User Manual Date 7 January 2015 SEH Austrian Aerospace Table 7 4 Supported RMAP Command Codes RMAP Command Code Description Supported in SpaceWire Router 0000 Not used 0001 Not used 0010 Read single address Yes 0011 Read incrementing address Yes 0100 Not used 0101 Not used 0110 Not used 0111 Read modify write incrementing address Yes 1000 Write single address no verify no acknowledge No 1001 Write incrementing address no verify no No acknowledge 1010 Write single address no verify send O acknowledge 1011 Write incrementing address no verify send No acknowledge 1100 Write single address verify data no O acknowledge 1101 Write incrementing address verify data no N acknowledge O 1110 Write single address verify data send Yes acknowledge 1111 Write incrementing address verify data send No acknowledge 7 6 2 Read Command The read single address characteristics of the SpaceWire router are defined in Table 7 5 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire
62. SECUTIVE EDGE SEPARATION srorrnrrnrnnnnnrrnrnnnnnrnnrnnnenrrnvnnnenrnnrnnnennenrnnnennenrnnnennennnn 130 FIGURE 10 2 EXTERNAL PORT INPUT FIFO TIMING PARAMETERS sssnesseessseessseessseressresssrrsseresssereseresserreserrsseeees 131 FIGURE 10 3 EXTERNAL PORT OUTPUT FIFO TIMING PARAMETERS sssnssseensseesseeossersssresserrsserreserrsseresssrrsseeeos 131 FIGURE 10 4 TIME CODE INPUT INTERFACE nosseenneseeenssseeeossseteossseersssseressseerossseerossseerssseeerssseeeossseerossseeessseeeees 132 FIGURE 10 5 TIME CODE OUTPUT INTERPACE 133 FIGURE 10 6 TIME CODE TIME CIR RST DNTERPACR 133 FIGURE 12 1 PLL LAYOUT RGCOMMENDATIONS 144 FIGURE 13 1 RESET WAVEFORM ae Ga 148 FIGURE 13 2 RESET WAVEFORM WITH DATA AND STROBE BOTH Hcon 148 FIGURE 13 3 GLITCHES ON DATA OR STROBE DURING RESET ossoenseseoeessseeeosssetrosssetesssererssseerosssserosseeersssseeens 148 FIGURE 13 4 SIMULTANEOUS TRANSITION OF DATA AND STROBE DURINGRrSET 148 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual e SpaceWire Router K School of Computing Issue 3 5 emm User Manual Date 7 January 2015 GH Austrian Aerospace FIGURE 13 5 LINK DISCONNECT WAVEFORMS i ccssesssccscccsscscvcseccocctcoessecsevnessesgecdsecavsedovcbseecdbeenscesseseeedsessesesovcoanes 149 FIGURE 13 6 DATA AFTER PARITY ERROR ANOMALY sesesesesessesesereresesoenererereresesoerereresesrereresereseroeoereresesosrereresene 150 FIGURE 13 7 NO ERROR END OF PACKET INSERTED AFTER PARITY ERRO
63. SH Outputs Space Wire SpaceWire Control Interfaces Pons e ace Wire Porte k ace Wire Port 7 swaten Configuration gt Space Wire Port E Port 8 rd External Input FIFO Input Output a i External Port E External FIFO i apn Time Code Input Output Time Code l SW External Port Interface Opus Outputs Figure 3 1 SpaceWire router block diagram The following paragraphs define the SpaceWire router functional logic blocks in more detail 3 1 SPACEWIRE PORTS The SpaceWire router has eight bi directional SpaceWire links each conformant with the SpaceWire standard Each SpaceWire link is controlled by an associated link register and routing control logic Network level error recovery is performed when an error is detected on the SpaceWire link as defined in the SpaceWire standard Packets received on SpaceWire links are routed by the routing control logic to the configuration port other SpaceWire link ports or the external FIFO ports Packets with invalid addresses are discarded by the SpaceWire router dependent on the packet address The SpaceWire link status is recorded in the associated link register and error status is held by the router until cleared by a configuration command 3 2 EXTERNAL PORTS The SpaceWire router has two bi directional parallel FIFO interfaces that can be used to connect the router to an external host system The external port FIFO is two data characters deep Each FIFO is 24 SpW 1
64. SUE 1 7 Ref Change All rr Corrections added following validation 15 14 ISSUE 1 5 TO ISSUE 1 6 Change P RMAP section added 15 15 ISSUE 1 4 TO ISSUE 1 5 mee Change All Footer changed to indicate preliminary and a note added on the front page to indicate that section 8 6 is subject to change 156 SpW 1 OX Ref UoD SpW 10X ASTRIUM i UserManual n SpaceWire Router K School of Computing Issue 3 5 User Manual Date 7 January 2015 GH Austrian Aerospace 15 16 ISSUE 1 3 TO ISSUE 1 4 Section pg Change ooo a ae Latency and jitter specifications added 15 17 ISSUE 1 2 TO ISSUE 1 3 Section mer Change B Section on fill bytes added w Registers updated to 3 3 specification document 15 18 ISSUE 1 1 TO ISSUE 1 2 6 3 6 4 6 5 Table 6 3 FPGA timing data added Table 6 4 Table 6 5 15 19 ISSUE 1 0 TO ISSUE 1 1 Change Table 5 1 FEEDBDIV PLL clock settings section added Table 5 5 STAT_MUX_OUT changed to multi function pin Table 5 6 Power on reset signals mapped to STAT_MUX_OUT pins 8 1 6 Setting the data rate takes account of FEEDBDIV and transmit clock control register setting TXDIV 835 Packet blocking correction does not cause disconnection of links 157
65. SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual n SpaceWire Router K School of Computing Issue 3 5 eme User Manual Date 7 January 2015 1 GH Austrian Aerospace SpW 10X SpaceWire Router User Manual Ref UoD_SpW 10X_UserManual Atmel Part No AT 910E Document Revision Issue 3 5 Date 7 January 2015 Prepared by Chris McClements University of Dundee Steve Parkes University of Dundee Gerald Kempf Austrian Aerospace Checked by Steve Parkes University of Dundee ESA Manager Pierre Fabry ESTEC SpW 1 OX Ref UoD SpW 10X ASTRIUM i UserManual n SpaceWire Router K School of Computing Issue 3 5 User Manual Date 7 January 2015 Austrian Aerospace Document Change loo o Issue 1 0 Chris McClements Issue 1 2 Chris McClements Issue 1 3 Chris McClements 27 April 2004 Issue 1 4 Latency and Jitter Specifications Chris McClements added section 8 6 subject to change 2 May 2005 Issue 1 5 notice added to front page 21 December 2005 Issue 1 6 RMAP section added Chris McClements 19 July 2006 Issue 1 7 Corrections and clarifications Chris McClements 18 August 2006 Issue 2 0 Editorial changes and Steve Parkes Clarifications phase locked loop and 3 d July 2007 Issue 2 1 Added sections on ASIC pin Chris McClements anomalies placement ASIC power consumption bias resistors 28 September 2007 Issue 2 2 Modifications before handed to Chris McClements Atmel Gerald Kempf 4th Octobe
66. SpaceWire link Disconnect error The parity error bit is set when a parity error occurs on the SpaceWire link The escape error bit is set when ee Escape error an escape error occurs on the SpaceWire link Credit error The credit error bit is set when a credit error occurs on the SpaceWire link Character sequence error The character sequence error bit is set when a character sequence error occurs on the SpaceWire link The interface state bits indicate the state of the interface state machine in the SpaceWire link 10 8 Interface state 000 Error Reset 001 Error Wait 010 Ready 011 Started 100 Connecting 101 Run The running bit is set when the SpaceWire interface state machine is in the Run state AutoStart 1 When set the SpaceWire link will RAV autostart as defined in the SpaceWire standard AD1 the 115 11 2 1 SpW 1 OX Ref UoD SpW 10X ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 EH Austrian Aerospace SpaceWire port will wait until the other end of the link tries to make a connection and will then automatically start 13 Start When set then the SpaceWire link will initiate start up as defined in the SpaceWire standard AD1 the SpaceWire port will try to make a connection with the other end of the link 14 Disable When set then the SpaceWire link will be di
67. TA 3 EXT9 OUT DATA 2 EXT9 OUT DATA 1 EXT9 OUT DATA 0 Bits dddddddd XXXXXXX0 XXXXXXXI Data byte EOP 8 O L 1 EEP e p PA Bit 7 is the most significant bit of the data byte EXT9 OUT EMPTY_N FIFO ready signal for external output port CMOS3V3 zero When high the FIFO has data When low the FIFO is empty EXT9 OUT READ N Asserted low to read from the external output CMOS3V3 port zero FIFO A pull up resistor e g 4k7 Q should be connected to this input if External FIFO port 9 is not being used EXT9 IN DATA 8 Input data to external port number one FIFO CMOS3V3 EXT9 IN DATA 7 Bit eight determines the type data eop or EXT9 IN DATA 6 eep The encodings are defined as 39 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 Austrian Aerospace EXT9 IN DATA 5 EXT9 IN DATA 4 Bits EXT9 IN DATA 3 dddddddd Data byte EXT9 IN DATA 2 XXXXXXX0 EOP EXT9 IN DATA XXXXXXX1 EEP EXT9 IN DATA 0 Bit 7 is the most significant bit of the data byte Pull up resistors e g 4k7 Q should be connected to these inputs if External FIFO port 9 is not being used When high there is space in the FIFO so it can be written to When low the FIFO is full Asserted low to write to the external input CMOS3V3 port zero FIFO A pull up resistor e g 4k7 Q should be
68. TPUT 83 FIGURE 8 4 START ON REQUEST MODE esnosnevnnvnnvnnnnnnnnennnennvnnennsnnennnennnnnennsnnennnnnennnennennennennennneneeneennennennenneeneeneenneen 87 FIGURE 8 5 DISABLE ON SILENCE MODE uradel 88 FIGURE 8 6 ARBITRATION OF TWO PACKETS WITH MATCHING PRIORITY ccccccssecccessccccessccceesececeuecceeeecseueeeceeees 89 FIGURE 8 7 ARBITRATION OF THREE PACKETS WITH MATCHING PRIORITY 0sccccesceceseccesecceececesceeeneceeneceeeeceees 90 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual e SpaceWire Router K School of Computing Issue 3 5 emm User Manual Date 7 January 2015 GH Austrian Aerospace FIGURE 8 8 ARBITRATION OF TWO PACKETS WITH DIFFERENT PRIORITY OI 91 FIGURE 8 9 ARBITRATION OF TWO PACKETS WITH DIFFERENT PRIORITY OO 93 FIGURE 8 10 NORMAL GROUP ADAPTIVE ROUTING ssssssssssssssstrtttettesssssssttttttttttetesssssssstttrttttreeeeesssssserrrrrreeeeeesse 94 FIGURE 8 11 GROUP ADAPTIVE ROUTING WHEN OTHER PORTS BUS 95 FIGURE 8 12 GROUP ADAPTIVE ROUTING WHEN PORTS NOT RAD 95 FIGURE 8 13 PACKET SELF ADDRESSING MOD 96 FIGURE 8 14 DESTINATION NODE BLOCKpDOA 98 FIGURE 8 15 DESTINATION NODE BLOCKED B ccccccceecccesecccscceeecccusccecsccceecseuecseesssseecseecseeeceseuseeeaeseueceees 98 FIGURE 8 16 DESTINATION NODE BLOCKED C c cccccccsscccesecccseccceecceeucsceseceuecseecsseussseesseuecsseecsseesseeeseeueseues 99 FIGURE 8 17 DESTINATION NODE BLOCKED WATCHDOG MODE A 99 FIGUR
69. The status output STAT MUX OUT is driven on the fourth CLK cycle after RST is de asserted See section 6 3 for information on the operation of the status power on configuration interface and section 10 5 for timing details 5 6 RESET CONFIGURATION SIGNALS The Reset Configuration signals are listed in Table 5 6 These signals are input on STAT MUX OUT after reset to initialise the router They are not used at any other time except immediately after reset The Reset Configuration signals set relevant bits in the configuration registers see section 9 Following reset the values of these signals are synchronously loaded into the router The timing of the Reset Configuration signals is illustrated in Figure 6 7 44 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 Austrian Aerospace Table 5 6 Reset 0 Table86 Reset Configuration Signals Signals Description Signal Type STAT MUX OUT 2 0 Sets the transmitter maximum data rate after CMOS3V3 maps to gt POR_TX_RATE 2 0 reset The data rate can subsequently be changed during normal operation using port configuration commands The values are listed below 111 Full data rate after link start up 110 1 2 data rate after link start up 101 1 3 data rate after link start up 100 1 4 data rate after link start up 011 1 5 data rate after
70. UTER DATA PACKETS oosnnennnnnnnnnnrnnnrnnnnnnnsnrnnnnnnnnnnesnnnnnnnnnnnnssnnnnnnnnnnnnssnnnnnnnnnnnssnnnnnnnnnnnessnes 57 FIGURE 7 2 COMMAND PACKET FORMAT cccccsssssseeeccccccessseseccccsscaseeeecccssccasseseeccssecaaseeeseccssecansesececsseeaaseesseeeees 57 FIGURE 7 3 READ SINGLE ADDRESS COMMAND FORMAT 59 FIGURE 7 4 READ SINGLE ADDRESS REPLY PACKET FORMAT ol FIGURE 7 5 READ INCREMENTING ADDRESS COMMAND bORMAT 64 FIGURE 7 6 READ INCREMENTING ADDRESS REPLY PACKET FORMAT 66 FIGURE 7 7 READ MODIFY WRITE COMMAND PACKET FORMAT 68 FIGURE 7 8 READ MODIFY WRITE EXAMPLE OPERATION ss sssssensseessseessseeessrersseresserrsseressreesseressreesseressrersserenss 70 FIGURE 7 9 READ MODIFY WRITE REPLY PACKET FORMAT 71 FIGURE 7 10 WRITE SINGLE ADDRESS COMMAND BACKET 73 FIGURE 7 11 WRITE SINGLE ADDRESS REPLY PACKET sssnsssesssseessseensseersseressrersseresseresseressreesseressrresseresseeesseresss 75 FIGURE 7 12 SOURCE PATH ADDRESS FIELD DECODING s ssssoeessseeeessseerosssetrosssetrosssrrossssrrossssrrosseeerosserressseeress 80 FIGURE 7 13 SOURCE PATH ADDRESSES IN REPLY PACKT 80 FIGURE 7 14 NORMAL CONFIGURATION PACKET HEADER STRUCTURE sss ssseessseeesseersseressrersseressreesseressreesseresss 80 FIGURE 7 15 FILL BYTES CONFIGURATION HEADER STRUCTURE 80 FIGURE 8 1 DEACTIVATE DRIVER OPERATING MODE annnnnnnnnnnnnnnnnnnnrnnnnnnnnnnnnnnnnnrnnnnnnnnnnnnnnnnnnnnnnnnnnsennnnnnensnnnnnnensennnn 83 FIGURE 8 2 DEACTIVATED LDVS DRIVER OU
71. User Manual DUNDEI Q S Q Q 2 P x E A 3 x E 7 S OND OND ON omg ON JU DWAUIS SydwvX3 I S R tz Tz S Tz Tt Zz TZ TZ TZ Tz Tz JISY J81NOH XOI M S sozmrrad E090IWS E 990IKNS 090INS 990INS 090INS E090IWS E090IWS 090INS 0903AS E 090JKS E090 JIWS 090IWS 923 SCH 123 EZI 12 13 7 ED a 113 DS 6 1407 3407 3901 3005 3401 3401 3401 At et 3407 3407 3001 I I I I T T 1 i T T 1 4 a 4 1 EAE EAE Su J AOJ JO WOT UN BDI Bundnosag JISV Sud Jamod JO WIT UHM 3201d BuNndnorag JISV OND OND OND OND OND NI LT LAT jr 7NH ENY Ku 412L7 201 d9187 ST 41ZL7 201 d9187 la e EE L ASABREEEEARGERE AAi S GEESE ee ae RR eee ESEES EES ST IEP EL ZT rot ei 8 L 9 S 7 EJ Z T Sinti rot 6 9 LI 9 5 7 E
72. Wire port Active SpaceWire Links Disabled SpaceWire Links I I I I I I I I r FPGA I SpW 10X Ee gt S Router Processor e WE I I I I I I I I I SpaceWire Node Figure 2 2 Node Interface In Figure 2 2 a SpW 10X router is used as an interface to a user FPGA or processor which may be part of a SpaceWire enabled instrument control processor or other sub system The interface to the user FPGA or processor is via the external FIFO ports of the SoW 10X router Only three SpaceWire links are needed for this SpaceWire node so the other five links are disabled to save power 2 3 EMBEDDED ROUTER The SpaceWire Router device can also be used to provide a node with an embedded router In this case the external ports are used to provide the local connections to the node and the SpaceWire ports are used to make connections to other ports in the network The difference between this configuration and that of section 2 2 is just a conceptual one with the Node interface configuration normally using fewer SpaceWire ports than the Embedded Router configuration 19 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 Pran User Manual Date 7 January 2015 GH Austrian Aerospace SpaceWire Links Instrument Instrument Instrument Instrument I I I I I I SE i SpW 10X l p Processor Router PE I I I I I J SpaceW
73. X Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 User Manual Date 7 January 2015 Austrian Aerospace Table 7 12 Read Modify Write Command Packet Fields Packet Field Config Port Address Destination Logical Address Protocol Identifier Command Byte Destination Key Source Path Address Source Logical Address Transaction Identifier Extended RMW Description The configuration port address field routes the packet to the configuration port of the router The configuration port address is always present when configuring the SpaceWire Router The destination logical address is not used in the SpaceWire Router The SpaceWire router accepts packets which have the default destination logical address of 254h FEh The RMAP protocol identifier is 01h The command byte indicates a read modify write command The Source path address length fields are set to the number of source path addresses required as defined in section 7 6 9 The destination key identifier must match the contents of the destination key register see section 9 5 10 The source path address field is used to add source path addresses to the 0 4 8 16 head of the reply packet The expected number of source path addresses is specified in the command byte See section 7 6 9 for source path address decoding The source logical address should be set to the logical a
74. a packet is being received the packet is discarded and an error end of packet EEP is appended to the end of the packet 13 4 2 Parity Error Anomaly The SpaceWire CODEC in the SpW 10X router detects a parity error and then resets the link but it takes 167ns to reset the link after the parity error has been detected During this time any data characters EOPs or EEPs received after the parity error will be placed in the receive FIFO These characters following the parity error are not removed from the receive buffer when the link is reset An example of this anomaly is shown in Figure 13 6 Parity Error a Data into receiver with parity error on second byte Data out of Receiver lt DATA 1 DATA 3 DATA 4 DATA 5 EEP b Data with parity error is discarded Some trailing data characters are added to buffer Figure 13 6 Data after parity error anomaly The number of characters added to the buffer depends on the input bit rate higher input bit rates result in more received characters being appended to the buffer after the parity error The maximum time to reset the receiver after detecting the parity error is 167 ns Therefore if no data characters are input for 167 ns after the parity error no extra data characters are inserted to the receive buffer If the input link rate is below 24 Mbit s the anomaly will not occur as the smallest data character end of packet marker which is 4 bits long cannot be decoded within 167 ns Above 24 Mbi
75. a4 Kaes EK ECKE 3534 W 4S S 0 13J3UU0 e 4 tal SAS 0 4 J NISU Chen y1 zho sssssgsss 85555588 ser gefroht Kee eege ST TE EC ZT ot ei 8 L 9 S 7 2 I ST IE EC ZT Tr or 6 8 L 9 S 7 z I 4 Y EAE EAE EAE ENE oT 412 7 201 d9187 oT 31Z27 201 d9187 ZN TNB DO DO NY NY OND OND Eat EAE OND OND S OND 0900WS 1 dl x ic A Led nie E990IKS 090INS pe amp a amp 13 omg 7 EJ w le T VLINOSOT6OX E 4u0T e Ant p g 2 DA Wie S HL ZS x 3 zonon OWS TILST SOMIM ACE Orosa JL Z S TH S NY NY Haf EAE EAE JOJDIPSQ ZHWOE Sundnoz q OA Duusg1 Dun sug OIA Q3A0Udd IK NOI Ld YIS 30 Ald SNOISIAIY T Z E 7 S E090IWS 023 TO 9 OND 7 z TE i TT Tz E490INS O90IWS EO90IWS 090IWS 090IWS et Dei 119 91 SI 4970 TO TO TO TO H T T T T J CAE Sud JBAOg JO WIT WYNM 82014 Bundnorag JISV L OND M fr 1 5080INS BENEKE 5080JKS 8 LI 9 PL E inky H i T EA o 5 H 90ZTINS Si PL I EAE Sud Jam0d JO WIE UI 3d014 bundnorag JISV
76. address 80 is selected and its packet transferred to output port5 In the meantime a packet with high priority logical address 80 arrives at input port 4 At stage three the packet from input port 1 has been forwarded and the packet with HIGH priority at input port 4 is selected by the routing control logic as the next packet to be routed to output port 5 In the meantime a packet with low priority logical address 52 arrives at input port 4 At stage number four the high priority packet from input port 4 has been forwarded and the routing control logic arbitrates again for access to output port 5 There are no high priority packets waiting to use output port 5 so the low priority packets that are waiting are considered The previous low priority packet that was routed through output port 5 was from input port 1 therefore the next packet selected by the routing control logic is the one from input port 3 At stage number five the packet from input port 3 has completed and the low priority packet waiting at input port 1 gets its chance to access output port 5 and is forwarded Note that low priority packets will not be routed until there are no more high priority packets waiting to be routed to the same output port Therefore in the situation when there is a high volume of high priority traffic coming from multiple ports a low priority packet could never get the chance to be routed This low priority packet would never timeout even when timeout is enabl
77. ait to be transmitted is one data character The jitter is measured as Trcr 2 x Ts YSPERIOD 5 X I TXPERIOD 10 6 6 200M bits s Input and Output Bit Rate Example The following table defines the latency and jitter measurements when the transmit bit rate and receive bit rate are 200M bits s Table 10 6 SpaceWire Router Latency and Jitter Measurements Bit rate 200Mbits s Description Symbol Value f Unts Switching Latency TswiTCH Router Latency SpaceWire to SpaceWire port TssDATA Router Latency SpaceWire to External port TSEDATA Router Latency External to SpaceWire port TESDATA Router Latency External to External port TEEDATA Time code Latency SpaceWire to SpaceWire port Tsstc Time code Latency SpaceWire to External port Tsetc Time code Latency External to SpaceWire port Teste Time code Jitter Trout 1 Note all figures are worst case 137 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 Austrian Aerospace 11 ELECTRICAL CHARACTERISTICS The electrical characteristics for the SpaceWire router are defined in this section 11 1 DC CHARACTERISTICS The operating conditions are listed in Table 11 1 For a detailed list of the operating conditions see AD3 Table 11 1 Operating Conditions Supply voltage 3 0 to 3 6 V Total OFF power static and dynamic Reset active 1 6 max W pow
78. an Aerospace 31 8 7 4 3 0 Device Type Return Port Ports in run state Figure 9 4 Network Discovery Register Fields Table 9 8 Network Discovery Register Fields Description Reset Read Write Value Device Type 0001 The device type field indicates the type of device which is associated with this network discovery register At present there is only one device type defined the Router along with the unknown device type 0000 Unknown Device 0001 Router Ports in Run All bits Indicates the SpaceWire ports which are in the run state set to state Bit 8 corresponds to SpaceWire port 1 Zero The external ports are the highest numbered port and the corresponding register bits are set to one In this way a network manager can determine the number of ports and the active ports in one register read 7 4 Return Port All bits Indicates the input port number which accessed this set to network discovery register zero 9 5 2 Router Identity Register The router identity register address is 257 Ox0000 0101 The router identity register allows a network manager to assign a 32 bit ID to a SpaceWire router device by writing to this register It may also be used for other purposes The router identity register is described in Table 9 9 118 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 Pran User Manual Date 7 January 2015 GH Austria
79. anual Date 7 January 2015 10 5 ERROR STATUS INTERFACE TIMING PARAMETERS The timing parameters for the status multiplexer port are show below Table 10 5 Status Multiplexer timing parameters Status address change to status output change CLK rising edge to status output 134 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 Austrian Aerospace 10 6 LATENGY AND JITTER The timing parameters for the data and time code latency and the time code jitter are derived from the receive clock transmit clock and system clock period The worst case number of clock cycles required is used in each equation In the SpaceWire router the system clock is a known frequency and the transmitter and receiver frequency are derived from the input and output bit rates The clock frequencies are defined as follows Note All figures are worst case Due to the uncertainty of synchronisation between clock domains the measured time may be less than indicated In the following sections the clock periods are defined and the latency and jitter timing parameter definitions are detailed 10 6 1 Clock Periods System Clock Period TsysperRioD 33 333 ns Clock Frequency 30 MHz Transmit Clock Period Trxperiop Transmit bit rate period 2 Where Transmit bit rate period is the output bit rate selected by the user configuration Receive Clock Period
80. appropriate internal configuration registers of the router on the first rising edge of the system clock CLK after RSTN is de asserted To make sure that the POR configuration signal values are loaded properly STATMUXOUT inputs must be stable from end of reset rising edge of RSTN till 4 CLK periods after the end of reset 53 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual on SpaceWire Router K School of Computing Issue 3 5 User Manual Date 7 January 2015 Austrian Aerospace 7 SPACEWIRE ROUTER PACKET TYPES This section describes how the routing control logic interprets packets 7 1 PACKET ADDRESSES The routing control logic interprets the first byte of each received packet as the packet address The packet address defines the physical ports through which the routing control logic will use to route the packet towards its destination Packets which have a path address 0 31 as the first byte are always routed to the corresponding physical port number on the router Packets which have a logical address 32 255 are routed to physical ports dependent on the contents of the routing table The internal SpaceWire router routing table can be set up to assign logical addresses to the physical ports except the configuration port port 0 which can only be accessed by path addressing The physical port addresses for the SpaceWire router and the expected packet type is defined in the table below The packet types can be viewed
81. arrives with the logical address the routing table is checked for the set of output ports which the packet can use The routing control logic then checks the possible router output ports to determine if any of them are free and ready to use As soon as one of the possible output ports associated with the logical address of the packet is free and ready to use then the packet is routed through that output port If all the set of output ports which the logical address packet can use are free then the router chooses the lowest numerical output port number to route the packet Arbitration is performed on group adaptive routing packets as defined in section 8 3 2 The following sub section consider various situations that can occur during group adaptive routing 8 3 3 1 Normal Group adaptive routing In normal group adaptive routing the lowest numerical output port in the group that is ready to use is used to transfer the packet This is illustrated in Figure 8 10 Address 76 Routing table entr Header Deletion disabled Port 4 Port 5 Port 6 Group adaptive routing packet with address 76 arrives at port 1 Routing logic assigns port 4 to port 1 Group adaptive routing packet with address 76 arrives at port 3 And port 5 to port 3 Figure 8 10 Normal group adaptive routing 8 3 3 2 Group adaptive routing when busy The situation when some of the output ports in group are busy is illustrated in Figure 8 11 Logical address 76 has group adapti
82. atus Pins Bit Assignment Mux Status Register Address Configuration Port SpaceWire Ports 1 8 respectively External Ports 0 1 respectively Network Discovery Router Identity Status Output Bits Bits Status Signal Status Register Packet return address error Output port timeout error Checksum error Packet too short error Packet too long error Packet EEP termination Protocol byte error Invalid address data error Packet Address Error Output Port Timeout Disconnect Error Parity Error Escape Error State A State B State C Error Active Packet Address Error Output Port Timeout Input Buffer Empty Input Buffer Full Output Buffer Empty Output Buffer Full Return port Least significant 4 bits Router Control Timeout Enable ee pe e SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual e SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 GH Austrian Aerospace Timeout Selection Enable Disconnect on silence Enable Start on Request Enable Self Addressing Error Active Configuration Port Error SpaceWire Ports 1 5 Error External Ports 1 2 Error 7 d General Purpose Least Significant 8 bits 6 4 RESET CONFIGURATION INTERFACE OPERATION 1 2 3 4 5 6 7 8 9 BS eS A Jr d POR_SIGNALS ees i ale NAAMA Figure 6 7 Reset configuration interface timing specification The POR configuration signals POR SIGNALS listed above are loaded into the
83. atus register bits 31 24 are generic to all ports Register bits 23 0 are specific to the type of port to which the register is attached 9 4 1 Generic port control status register fields The configuration port control status fields are described in Table 9 4 Table 9 4 Configuration Port Control Status Register Fields 110 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 Austrian Aerospace Reset Description Read Write Value 28 24 Current port All bits The current port connection bits indicate the input connection set to port which this output port is currently connected one to Port number 31 bits 28 24 set to 11111 means that there is no port currently connected to the input port This is the reset condition 31 29 Port Type All bits Indicates the port type Possible port types are set to listed below lt a 000 Configuration port 001 SpaceWire port 010 External port 9 4 2 Configuration port control status register fields The configuration port control status fields specific to the configuration port are described in Table 9 5 Any errors occurring in the configuration port are reported via status bits in this register and the configuration command that caused the error is replied to with a NACK Error status bits are cleared by writing to the Error Active register see section 9
84. available if EXT_IN_WRITE_N is still asserted low Therefore the data EXT IN DATA must be valid at that time 49 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual D SpaceWire Router K School of Computing Issue 3 5 rn User Manual Date 7 January 2015 GH Austrian Aerospace 1 2 3 4 5 6 7 8 9 10 11 12 CLK IT EXT_OUT_DATAx Wm Dana ID Dune Vous Com EXT OUT EMPTY Nx read read read Figure 6 2 External port read timing specification Reading of the External port is illustrated in Figure 6 2 When data is available in the External port FIFO then it is placed on the EXT OUT DATA bus and the EXT OUT EMPTY NI signal is asserted to signal to the external system that data is available This is done synchronously to the SYSCLK signal e g clock cycle 2 in Figure 6 2 When it is ready the external system asserts the EXT OUT READ_N signal synchronously with the SYSCLK signal e g clock cycle 3 and the data is then read out of the external port on the next rising edge of the SYSCLK e g start of clock cycle 4 If there is no more data available in the FIFO then the EXT OUT EMPTY N is de asserted once the data has been read If the FIFO contains more data to transfer then the EXT OUT EMPTY N remains asserted the new data is placed on the EXT_OUT_DATA bus and the external system can read it as soon as it is ready The read access is ignored if there is no data available EXT_OUT_EMPTY_N is active 6 2 TIME CODE INTERFACE OPERATI
85. command 31 23 15 7 0 ofofofofofofofojofofofojofojofofofiftfofofoft t ofofojolo o o o command bat 31 23 15 7 0 ofofofofofofofofofofofofo ofofofrfiftfiftfift ifofofofofofolo o command mask 31 23 15 7 0 afrfiftfiftfiftjofofofofofojofoftfoftfofofi ofofofofofoltifo i o Register bata Returned to source Mask AND Command Data OR NOT Mask and Register Data 31 23 15 7 0 Figure 7 8 Read Modify Write example operation 70 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 Bam User Manual Date 7 January 2015 H Austrian Aerospace In Figure 7 9 the format of the reply to a Read Modify Write command is illustrated The first byte received by the SpaceWire router configuration logic is the port address followed by the destination logical address Fields which are depicted in bold text are expected values Fields which are shaded are optional Note that the reply is always sent out of the same port as the command was received on The Source Path Address should not include the output port of the router being commanded as the reply will be automatically sent out of the same port that the command arrived on See section 7 6 8 First byte transmitted Source Path Address Source Path Address Source Path Address Protocol Identifier Packet Type Command Source Logical Address Source Path Addr Len Status Pestnalon Logica Address Transaction Identifier MS Transaction
86. complete group adaptive routing table can be read in one command or all the status registers for the SpaceWire links can be read in one command 63 r SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 Bam User Manual Date 7 January 2015 Austrian Aerospace In Figure 7 5 the first byte received by the SpaceWire router configuration logic is the port address followed by the destination logical address Fields which are depicted in bold text are expected values Fields which are shaded are optional First Byte Received Config Port Address 00h i i Protocol Identifier Packet Type Command Destination K FEh 01h Source Path Addr Len poten Source Path Address Source Path Address Source Path Address Source Path Address Extended Read Add Source Logical Address Transaction Identifier MS Transaction Identifier LS Read Address MS Read Address 00h Read Address Read Address LS Data gr MS Data Length Data Length LS Header CRC Last Byte Received EI a 5 D 5 o e e D gt ea 2 o O Bits in Packet Type Command Source Path Address Length Byte MSB LSB TTT L Lee Address Length Address Length _ Packet Type DE Command Je Source Path Address Length Figure 7 5 Read Incrementing Address Command Format Table 7 9 Read Incrementing Address Command Packet Fields S ks Config Port The configuration port address field
87. data transfer If an external device starts the SpaceWire link or sends packet data to the router through the link then the link will not be disabled 8 3 CONTROL LOGIC AND ROUTING This section describes the operation of the SpaceWire routing logic and how packets are handled for different modes of operation of the router The following control bits in the router control register affect the router operating mode Timeout Enable Enable Disable on Silence Enable Start on Request and Enable self addressing 8 3 1 Packet address error When a packet with an invalid address see section 7 4 is received the packet is discarded by the router The router is ready to receive the next packet as soon as the invalid address packet has been spilt 8 3 2 Arbitration Arbitration is performed by the SpaceWire router when two or more packets are to be routed through the same destination port The router chooses the next packet to be routed to a particular output port 88 SpW 1 OX Ref UoD SpW 10X ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 Pran User Manual Date 7 January 2015 GH Austrian Aerospace dependent on the previous input port which had access to that output port The next input port to transfer data to an output port is the next highest port number modulo number of ports that has data to send Thus the input port which previously had access to the output port will be selected last by the router control
88. ddress is set to the default value FEh as the logical SpaceWire router does not have a logical address address Transaction The transaction identifier identifies the command packet and reply packet with a Identifier unique number The transaction identifier in the reply packet is copied from the command packet and returned in this field so that the command and the corresponding reply have the same transaction identifier value Data The data length field is the number of bytes read from the router as specified in Length the data length field of the command packet Header The header CRC used to detect errors in the header part of the command CRC packet See section 7 6 7 for CRC generation Data The data read from the registers in the device The data is returned in 32 bit words starting from the address specified in read address in the command packet Data CRC The data CRC used to detect errors in the data part of the reply packet See section 7 6 7 for CRC generation 7 6 4 Read Modify Write Command The read modify write command characteristics are defined in Table 7 8 Table 7 11 Read Modify Write Command Characteristics maton Supported Maximum number Non aligned access Not Supported of bytes accepted 8 bit read modify write 16 bit read modify write r SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 Bam User Manual Date 7 January 2015 Austrian A
89. ddress of the node which sent the command The transaction identifier identifies the command packet and reply packet with a unique number The extended read address is not used in the SpaceWire router and shall always be set to zero The read modify write address identifies the SpaceWire router register address to modify Valid RMW addresses are defined in section 9 RMW Address The data length of the read modify write command is 8 4 bytes for data and 1 1 1 1 1 1 2 1 Address A 3 69 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual n SpaceWire Router K School of Computing Issue 3 5 User Manual Date 7 January 2015 Austrian Aerospace Mask 4 bytes for the mask to modify a 32 bit register Length Header The header CRC used to detect errors in the header part of the command CRC packet Data and The data and mask values to write to the SpaceWire router The data is Mask written dependent on the mask as shown in Figure 7 8 Data and The data and mask CRC used to detect errors in the data part of the Mask CRC command packet A Read Modify Write command modifies the bits of a SpaceWire router register dependent on the contents of the register Register Data the command data Command Data and the command mask value Mask as follows Register Value Mask AND Command Data OR NOT Mask AND Register Data An example is shown below the highlighted bits are set or reset by the
90. ded read address is not used in the SpaceWire router and shall always be set to zero The read address identifies the register address to read from The valid read addresses are defined in section 9 The data length of a read single address command shall be set to 4 to read M 1 r r 1 r r 2 1 4 3 60 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 GH Austrian Aerospace Length one 32 bit register location Header The header CRC is the eight bit CRC code used to detect errors in the CRC command packet The CRC code is checked before the command is executed In Figure 7 4 the format of the reply to a read single address command is illustrated The first byte sent by the SpaceWire router configuration logic is the port address followed by the destination logical address Fields which are depicted in bold text are expected values Fields which are shaded are optional Note that the reply is always sent out of the same port as the command was received on The Source Path Address should not include the output port of the router being commanded as the reply will be automatically sent out of the same port that the command arrived on See section 7 6 8 First byte transmitted Source Path Address Source Path Address Source Path Address Protocol Identifier Packet Type Command Source Logical Address Source Path Addr Len Status De
91. e T TWIWONILX3 PYTON IX aNs 0 TV VONLLX3 T RK Caen gt EILER T EGY un rd NODS 7d NO O INTINSNILX3 HS TTN LXI Sv HILNDE MAS r Oo TNOV3YLNOL XS i 7y mum me e Se Ed 1N00 E TNA LANILNOLX3 DEER DO eee Ormana BHE Wwavo ino1x3 eines ENIMS V TV1V01N01X3 L Ir 1013 BAD ENNIS o 9 TV 1VOLNOLX3 gy rt erun RAD Ed NIS 3 S TVLIVOLNOLX3 EEE 1v1V0T1N0 1X3 EN EN NIQ O 7 TYIVOLNOIX3 TET DU 1 Da kd A Ed NIO 3 TVIVOLNOIX3 lte ug un euer tte tt dd 4 TTVIVQINOIX3 qT WU mr old LT iid j 5 MODS 01 Jayay 0 TV1VOLNOLX3 gdy V1V0710 1X3 Nm AMD FSB Ag dv panne SEH dag 0UISJKI Or WONG Er ster na CHE a L OVIVONLIX3 S dt ov vm Cd NIS 9 OWLVONLLX3 F Dr evs von I ZNNO Q EVLYINLDG Mt oi WI zd NIO 7 OVLVONLLX3 GUE OVIVIN 143 Td 1N00 gt OVLVON IX3 QI VIVA 1x3 TN 1NO0 T OVI VONLLX3 DOE td 1N0S Q PAE g FT vav va Wm S 0 OVLYONLLX3 GP VINEN IG NE lt p MAHANZI D UNNI taNs e ONTIN ANI LX TAYE OTIS NI LX INN O lt N LNO NG Ty px mu Td NIG ar ONA LAWSLNOLXS KU SIE O 2 od 1N00 EJ 8 OVIVOLNOIXS Z ov vor UNO 1x3 ON LNG HOLT 2 L OVLVOLNOIXS TIN Ova vor mer LAG SE 9 OV 1 VOLNOLX3 A evs var ug na r 5 OVLVOLND IX3 L Y ovava ug DG Z Q 7 OV1VOLNOIXS P ovvora T 4 NIS DIER OV1VOLNOLX3 Edt out ug 1x3 T ON NIG ces Z 0V1VOLNOIX cat ova WO UNO ai LT oN O T OVLVOLNOIX3 TOP ov 1v0100 1x3 8 OP ov IvOLNO IG Od ovv uno oa ape 9T8 YOHIAS 04 Japay opam sug a2UaveJ3Y SOA UO 0J8d0 ZHWNOOZ pwsad o4 Jos JSPINP yDDQpa
92. e destination port is a SpaceWire port and the port is not started the packet will only wait as long as the timeout period and then the router will spill the packet If group adaptive routing is being used and at least one of the output ports in the group is running then the packet will wait indefinitely until the running port is ready even if one or more of the other ports are not started In Watchdog Timer mode there are several possible cases which are considered below Output port not running If a packet arrives at an input port of the SoW 10X router and the output port that it is to be routed to is not running the router will wait for the output port to start for the watchdog timeout period and will then spill the packet if the link has not started If Start on Request has been enabled the router will wait for the watchdog timer timeout interval for the output port to start The packet will be routed to the output port as soon as it starts and a connection is made If the port does not start before the end of the timeout interval then the waiting packet will be spilt Output port running and not busy If a packet arrives at an input port on the SpW 10X router and the output port that it is to be router to is running but not currently sending a packet then the newly arrived packet will be routed immediately Output port running and busy If a packet arrives at an input port on the SpW 10X router and the output port that it is to be router to is
93. e of the signal name e g EXT IN FULL is de asserted when the external input FIFO is not full The logic level when a signal is asserted is indicated by the logic level extension to the signal name If there is no extension then when the signal is asserted it is logic 1 high If the _N extension is present then when the signal is asserted it is logic 0 low For example EXT IN FULL N asserted means that the physical signal is logic 0 low when the external input FIFO is full 6 1 EXTERNAL PORT INTERFACE OPERATION In this section the external port interface operation is described CLK EDA ee DATA W EXT IN FULL Nx Je ji EXT_IN_WRITE_Nx Figure 6 1 External port write timing specification The operation of the External port during write operations starts with the EXT_IN_FULL_N signals being de asserted going high by the router at clock cycle 2 in Figure 6 1 to indicate to the external system that the router has room for more data and is ready to receive it through the External port The External system then puts data onto the EXT_IN_DATA data lines and asserts EXT_IN_WRITE_N goes low to transfer data into the External port on the next rising edge of SYSCLK As long as there is room for new data EXT_IN_FULL_N is de asserted high the writer access is performed as long as EXT IN WRITE N is asserted low If no room is available the write access is ignored cycle 9 and 10 in Figure 6 1 and will be performed when room has become
94. e reply packet is copied from the command packet and returned in this field so that the command and the corresponding reply have the same transaction identifier value Header The header CRC used to detect errors in the header part of the command CRC packet See section 7 6 7 for CRC generation 7 6 6 Command Error Response A summary of the error conditions and the action taken is given in Table 7 17 The error conditions are recorded in the configuration port status register Table 7 17 Configuration Port Errors Summary Register Bits Description Reply Returned As Returned Packet RMAP Status Invalid Header The header CRC was invalid No Reply Packet CRC therefore the header is corrupted Unsupported The protocol byte is not the No Reply Packet Protocol Error RMAP protocol identifier Source Logical The source logical address is No Reply Packet Address Error invalid outside the range 20h FFh Source Path The source path address No Reply Packet Address sequence is invalid as sequence Error specified in section 7 6 9 Unused RMAP The command code is an Unused RMAP command or unused command code or the command or packet packet type packet type is invalid type Invalid The destination key in the Invalid Destination Key Destination Key command packet is invalid ve Data The Data CRC is invalid Invalid Data CRC therefore the data part of the SpW 10X ASTRIUM DUNDEI SpaceWire Router School of
95. e routing In group adaptive routing a packet can be routed to its destination through one of a set of output ports dependent on which ports in the set are free to use When a packet is received with a logical address the routing table is checked by the routing control logic and the packet is routed to the destination port when the port is ready Routing table locations are set to invalid at power on or at reset An invalid routing address will cause the packet to be spilled by the control logic The routing table logical addresses can also be set to support high priority and header deletion High priority packets are routed before low priority packets and header deletion of logical addresses can be used to support regional logical addressing see AD1 3 5 ROUTING CONTROL LOGIC AND CROSSBAR The routing control logic is responsible for arbitration of output ports group adaptive routing and the crossbar switching Arbitration is performed when two or more source ports are requesting to use the same destination port A priority based arbitration scheme with two priority levels high and low is used where high priority packets are routed before low priority packets Fair arbitration is performed on packets which have the same priority levels to ensure each packet gets equal access to the output port Group adaptive routing control selects one of a number of output ports for sending out the source packet 25 SpW 1 OX Ref UoD SpW 10X ASTRIUM i
96. ed thus blocking the link indefinitely If the tail of this packet goes through another SpW 10X router this other router will timeout and spill the tail of the router 92 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 EH Austrian Aerospace Addresses 80 HIGH Priority 52 LOW Priority Two packets waiting to use port 5 Packet from port 1 is selected Previous port which accessed port 5 4 HIGH priority packet arrives at port 4 Packet from port 1 completes Packet from port 4 completes HIGH priority packet from port 4 is selected Previous low priotity packet which accessed port 5 1 Port number 3 waits Therefore port 3 is selected Packet arrives on port 1 Packet on port 1 waits SCH ar Packet from port 3 completes Packet from port 1 completes Packet waiting on port 1 is selected Figure 8 9 Arbitration of two packets with different priority 2 93 SpW 1 OX Ref UoD SpW 10X ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 Austrian Aerospace 8 3 3 Group Adaptive Routing The SpaceWire router routing table can be set up to support group adaptive routing of packets Setting the routing table contents is described in section 9 3 In group adaptive routing a set of output ports can be assigned to a logical address When a packet
97. ed to it The SpW 10X SpaceWire router comprises the following functional logic blocks Eight SpaceWire bi directional serial ports Two external parallel input output ports each comprising an input FIFO and an output FIFO A crossbar switch connecting any input port to any output port An internal configuration port accessible via the crossbar switch from the external parallel input output port or the SpaceWire input output ports A routing table accessible via the configuration port which holds the logical address to output port mapping Control logic to control the operation of the switch performing arbitration and group adaptive routing Control registers than can be written and read by the configuration port and which hold control information e g link operating speed An external time code interface comprising tick_in tick_out and current tick count value Internal status error registers accessible via the configuration port Watchdog timers on all ports Internal status error registers accessible via the configuration port using the RMAP protocol 2 External status error signals A block diagram of the routing switch is given in Figure 3 1 23 SpW 1 OX Ref UoD SpW 10X ASTRIUM i UserManual ge SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 KP Austrian Aerospace ace Wire F Pool k Space Wire BR Port 2 MN Status Error gm ge mg Status ace Wire ES P
98. eout when watchdog timer mode set see section 8 3 5 and the packet will be spilt If the packet is a small packet it could continually circle around the loop A SpaceWire network architecture and configuration should be checked for possible loops for all logical addresses being used Unused logical addresses should NOT be configured in the SoW 10X routing tables so that a packet arriving at a router with an invalid unused logical address will be spilt immediately WARNING lf a SpaceWire port that is being used to configure a router has its transmit clock turned off then it will not be possible to configure the router using that port Unless there is another connection with an active clock and which is not disabled that can be used to perform configuration the router will have to be reset before it can be configured again 13 3 RESET ANOMALY This section describes the reset anomaly and suggests appropriate workarounds 13 3 1 Data Strobe Reset Waveform If a SpaceWire link is running when the SpW 10X device is reset part of a NULL pattern is present on the serial data strobe outputs of the running link when reset is released see Figure 13 1 Data and strobe outputs hold their previous values until reset is applied as seen in Figure 13 2 When reset is 147 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual Di SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 Austrian Aerospace se
99. er consumption CLK input with 30 MHz signal RSTN active Total operational power with all interfaces active 2 4 max at 10 Mb s W including external porte 3 0 max at 100 Mb s W 3 7 max at 200 Mb s 1 If a SpW IF is not active clock and LVDS drivers switched off assume a reduction of Pop by Pop Porr x 0 1 0 06 Example 2 SpW interfaces deactivated at 200 Mb s Operational power 3 7 3 7 1 6 x 0 1 0 06 x 2 3 16 W max 2 For the data rates lt 200 Mb s the setting for the lowest power consumption i e lowest PLL and Tx clock frequency is assumed 3 The actual data flow has a negligible influence on the power consumption i e very little difference if NULLs or SpW packets are transferred All power figures in Table 11 1 are for maximum conditions which means 3 6 V for the supply voltage If the supply voltage is lower the power consumption sinks as well The reduction fits to the power consumption with a resistive load l e at 3 0 V the power consumption is 69 4 of the power consumption at 3 6V The lowest power consumption at a certain data rate is achieved if the PLL is set to the lowest possible frequency setting of FEEDBDIV inputs and the SpW Tx clock to the lowest possible frequency setting of TXDIV in register for that SoW data rate 138 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual on SpaceWire Router K School of Computing Issue 3 5 Bam User Manual Date 7 January 2015
100. eration for Space Standarization Error end of packet used to denote an error occurred during packet transfer End of packet used to denote a normal end of packet in SpaceWire First in First out buffer used to transfer data between logic Field Programmable Gate Array Ground Low voltage differential signalling Negative acknowledge error acknowledge Phase Locked Loop Read Remote Memory Access Protocol Asynchronous reset to the SpaceWire router SpaceWire To be advised To be confirmed University of Dundee 15 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 Pran User Manual Date 7 January 2015 Austrian Aerospace VCO Voltage Controlled Oscillator VDD Drain Voltage power pin of SoW 10X device VSS Source Voltage ground pin of SpW 10X device WR Write 1 2 DOCUMENTS In this section the documents referenced in this document are listed Table 1 1 Applicable Documents Document Number Document Title dl ECSS E ST 50 12C SpaceWire links nodes routers and networks ECSS E ST 50 52C SpaceWire Remote Memory Access Protocol D3 Atmel SMD 5962 09A03 SpW 10X Standard Microcircuit Drawing http www atmel com Images smd_ 5962 O09A03 pdf AD1 AD2 A 16 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 Pran User Manual Date 7 January 2015 Austrian Aerospace Table 1 2 Reference
101. erified write command Note 2 a Read Modify Write Data Length error shall be returned when the data length is not 8 VA SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 GH Austrian Aerospace command The data length is not 8 in a read modify write command Invalid Register The address field is addressing Yes RMAP Command not Address an unknown register for a read implemented or not command or a read only authorised register in a write command Read Modify The read modify write data Yes RMW Data Length Error Write Data length is not 8 Length Error Invalid The destination logical address Yes Invalid Destination Destination is invalid The destination Logical Address Logical Address logical address is expected to be the default 254 value 7 6 7 Command Packet Cyclic Redundancy Check The header and data part of an RMAP packet are protected from errors by the use of an 8 bit CRC code The header and data CRC is formed using the CRC 8 code used in ATM Asynchronous Transfer Mechanism CRC 8 has the polynomial X X X 1 with a starting value of 00h Command packets received by the SpaceWire router which have an invalid header CRC are discarded and the Invalid Header CRC bit is set in the configuration port register 7 6 8 Local Source Path Address The configuration reply packet shall be routed out of the
102. erospace m bl E SF Accepted destination keys 0x20 at power on Accepted address ranges 0x00 0000 0000 0x00 0000 0109 The RMAP read modify write command is supported by the SpaceWire router The read modify write command is used to set or reset a single or number of bits in a router register The Read Modify Write command is useful when it is desirable to set a link register setting without upsetting the other settings in one command i e set the start bit without modifying the data rate In Figure 7 7 the first byte received by the SpaceWire router configuration logic is the port address followed by the destination logical address Fields which are depicted in bold text are expected values Fields which are shaded are optional First byte transmitted Config Port Address Destination Logical Address Protocol Identifier Packet Type Command S MS 00h Source Path Address Source Path Address Source Path Address Source Path Address Extended RMW Add Source Logical Address Transaction Identifier MS Transaction Identifier LS RMW Address MS RMW Address Data Mask Length MS Data Mask Length Data Mask Length LS Data Mask CRC Last byte transmitted Bits in Packet Type Command Source Address Path Length Byte MSB LSB A EREECHEN Address Length Address Length je Packet Type BE E Command er Source Path Address Length Figure 7 7 Read Modify Write Command Packet Format 68 SpW 1 O
103. errnnnnnneneennnn 112 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual D SpaceWire Router K School of Computing Issue 3 5 emm User Manual Date 7 January 2015 GH Austrian Aerospace TABLE 9 6 SPACEWIRE PORT CONTROL STATUS REGISTER FIELDS ccccccccssseeccecesseccceceeeeceecaueeceeeaueceeeeanes 115 TABLE 9 7 EXTERNAL PORT CONTROL STATUS FIELDS cccesesssecccssesscersnevssectesnssevcneaesssdsenseesssareserssececerssersnass 117 TABLE 9 8 NETWORK DISCOVERY REGISTER bn 118 TABLE 9 9 ROUTER IDENTITY REGISTER FIELD 4550c3icisnecsaosesaetitncpaceindureddioiesaenioiesseniatianesioiaonthivlionstiedaseeriemiuetoneds 119 TABLE 9 10 ROUTER CONTROL REGISTER te EE 120 TABLE 9 11 ERROR ACTIVE REGISTER bg 123 TABLE 9 12 TIME CODE REGISTER FIELDG sssccccssssecceccesseecccccasseccccaaseesccceasesteccaseeseccaasesseccaseesecsansessensass 124 TABLE 9 13 DEVICE MANUFACTURER AND CHIP ID REGISTER FIELDS rererennnneronnnnrrnnnnernnnnnerennnerennnnerrnnnnenennnenen 124 TABLE 9 14 TIME CODE ENABLE REGISTER bp 126 TABLE 9 15 TRANSMIT CLOCK CONTROL REGISTER BITS ccccccccssseseeccceeecesseeecccceeeauseeseccceeesaaaeeeecceseesaaeneeeees 128 TABLE 9 16 DESTINATION KpvRpoIsTER 129 TABLE 10 1 CLOCK AND RESET TIMING PARAMETERS eeseeronrrvnnrnnrrsvnnnnnvnsvnnnnnvesvnnnnnvennnnnnnvesnnnnnsvesnnnnnssesnnnnnsvessen 130 TABLE 10 2 SERIAL SIGNAL TIMING PARAMETERS errrrnrnnnnrnrrnvnnnnnrnnvnnnsnrnnvnnnensnnnnnnensrnnnnnnennen
104. eseeeseeeneees 92 8 3 3 Group Adaptive Routing 94 6331 Nord Group ANE UN 94 8 3 3 2 Group adaptive routing when busy 94 8 3 3 3 Group adaptive routing when ports not reach 95 8 3 4 Loop back with Get Addreseimg 95 8 3 5 Packet Blockmg nrn re nenne 97 8551 Bede 4 pr 97 8 3 5 2 Stalled SOUrce rrarnnnnnrnnnvnnnrnnnnnnnnrnnnvnnnrnnnnnnnnrnnnrnnnrnnnnnnnnrnnnsnnnsnnnnnnnnrannsnnnsnnnnnnnnnnnnnnnsnnnee 100 8 3 5 3 Waiting for an NNN 103 9 REGISTER EENEG 105 9 1 INTERNAL MEMORY MAb cece eeeeeeesee cess case eeseeeseeeesseeesaeeesaeeesaneesaes 105 9 2 REGISTER ADDRESSES SUMMARY srianan AEA EN AEA 106 9 3 GROUP ADAPTIVE ROUTING TABLE REGISTERS i mrrnernnrennnrernnrernnrennrrennrrrnnrrernrrernrernsrenn 107 94 PORT CONTRO TAU E eege 110 9 4 1 Generic port control status register fields ccccccceeccseeeceeeceeeceeeceeceseeeseeeseueeseeeseeeseeesaues 110 9 4 2 Configuration port control status regtsierfelde 111 9 4 3 SpaceWire port control status register bits rrrrrrrnrrrnrernrrrnnrrnnrrranrnnrrrnarrrnnrranennrnnnnnnnnennee 114 9 4 4 External port control status register bits rrrrrrnrrrnrrnnrrnrrvnnrnnrnnrrrnnrnnrrnrennnrnnrnnerrnnnnnnneennsnnn 117 9 5 ROUTER CONTROL STATUS REGISTERS rrerrrnvnnrrvnnnrrnnnrennnrrnnrrennnrernerennnrernerennerernrennsrennn 117 9 5 1 Network Discovery Hegtster 117 952 Router TEN FEE 118 953 Router Re geet 119 9 54 Error active RegiSt r ET 122 SpW 10X Ref UoD SpW 10X
105. f z 94666604 ood IT elen 5 NJ ISIL 95 UONIIS 01 J313Y LINOXNWLVLS z gdin xw 1VLS Payqoua 23915 UO aygosig 9 1NOXNALVIS v YLND xT ALS payqoua jsanba up Ups S1NOXNALVLS i T Inox jee SWE T 04 Jas PUD Payqoua nau T1NOXNALVLS I P 10 XI avs P31q0ua Burssauppo E INOXNWNLVIS Taino xw aves J pPIA 201 JWSUDYI B T TINOXNALVIS P avis sBuitas YOd au DI umop pannd 1NOXAWNLVIS TLNOXNWLWLS L Par Nw os OLNOXNWLVLS KI UK me EUDOVXNNLVLS ES vw eis 9 UOIJISS 04 J lgn lg innxgunvys seis asoding OSL ee yovauag HAD oy dn paynd YIOVXNALVIS CEET japava vis wang in 9 ZNISWILIXS ES KI ER ONISWILLX3 7 JIN IMDG Ld LAOS MIMI dm BHU EN E YNIAWIL 1X1 EJN au ei La NIS ENIIWILLX3 TYPEN ING e INi O o ZNISWILLX3 TJEN IMDG ta nnBg TNISWILLX3 OPNING 4x3 B L Mi 5 74 UONDES 04 43439 KERGER GENT BHU sig 94100 e nvjap Aq umop pannd sjndu jsog apoj awiy eee nl Tjjsrar an sph ER WIL 1XITIS LEM zs pre e LS E e NIWDILLX3 egy DL UX3 ous Fe an Q ND MALI XI HEES Bi zwet SCH V D LIND IN DA Di NN SANOIWILLXI od 9d NIO lt gt 103ML 1X3 LU s4 n00 T 4 TAO T1INDANIL IG Ti ioh Q EINOIILIXI Ela za ering eee ZINOIWILLX3 TND wen avis pr aon Oo TANOIWIL XI Taino A vo we Q HEES mg a na UNE O BTV 1VONILX3 1 TYP TV AVON 1x3 SN7NIQ O Q L TV1VONILXG p Emir Ed NI0 9 TVLVONILX3 6Y WIEN 1 Caen gt SVIND i item naw o 7 TWIVONILX LYVWIVON 1X3 Sange E TW1VONILX 7 Sq INOW xa TAS OO ZC Tee Eat INECC DNG me
106. g allowed mode the network path is blocked until the destination node starts to accept data again Packets waiting to use the network path will wait indefinitely In watchdog timer mode the router will timeout and the network path will be cleared so other packets can use the path Blockinq Allowed Mode What happens when Blocking Allowed mode is being used and a destination node becomes blocked is illustrated in Figure 8 14 to Figure 8 16 In this example two routing switches R1 and R2 are connected to form a network and only SpaceWire ports 1 to 6 are shown for clarity a A packet arrives at port 3 of routing switch R1 destined for port 4 and then port 5 of R2 as shown by the path address 4 5 at the head of the packet a Figure 8 14 Destination Node Blocked a b The packet is routed towards its destination but during packet transfer the destination stalls and does not accept any more data The network path is blocked and the packet waiting at R1 port 2 is also blocked b Figure 8 15 Destination Node Blocked b c The path between routing switch R1 port 4 and routing switch R2 port 1 is now blocked While the first packet is routed another packet arrives at port 2 on router R1 with destination port 4 on router R1 and destination port 4 on router R2 The packet must wait as the ports are currently busy and can only be routed if the downstream node starts receiving data again 98 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM
107. ged to deactivate mode Calculation of oe deactivated power consumption added Tri state mode changed to deactivated mode Description for time code flag mode bit added II Table 11 1 Power information updated Section added on reliability information pe Reference to further details on anomaly 1 in section 13 3 added Anomaly 2 tri state mode removed The text throughout the document related to tri state mode has been corrected to deactivated mode A warning that the deactivated mode is not true tri state has been added Section added to give more details on reset anomaly 15 5 ISSUE 3 0 TO ISSUE 3 1 EE EE EE Second warning clarified S gt 7 6 10 Note added explaining that command packet fill bytes is a TT L O ROGENER anano MAP 8 1 6 13 2 Warning on setting data rate to less than 2 Mbits s deleted The SpW 10X device will not allow a TXDIV and TXRATE to be set to give a transmit data rate below 2 Mbits s 8 3 2 4 Note added to further explain blocking of low priority packets by wi 8 3 5 3 Corrections made When output port not running or in a group 3 and not running the router will waits for the timeout period for 154 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router School of Computing Issue 3 5 User Manual Date 7 January 2015 the link to start If tt does not start in that time then the packet will be spilt mm P gt References to AD3 corrected 2a fo Exa
108. i UserManual SpaceWire Router K School of Computing Issue 3 5 weus User Manual Date 7 January 2015 Austrian Aerospace c Figure 8 16 Destination Node Blocked c Watchdog timer mode What happens when the routers are in Watchdog Timer mode and a destination becomes blocked is illustrated in Figure 8 17to Figure 8 20 Only SpaceWire ports 1 to 6 are shown for clarity a A packet arrives at port 3 of routing switch R1 destined for port 4 and then port 5 of R2 a Figure 8 17 Destination Node Blocked Watchdog Mode a b The packet is routed towards its destination but during packet transfer the destination stalls and does not accept further data The network path is blocked and the packet waiting at R1 port 2 is also blocked b Figure 8 18 Destination Node Blocked Watchdog Mode b c At routing switches R1 and R2 the watchdog timers detect the packet has blocked for the specified timeout period The packet is then discarded by the routers by spilling the data at the input port and appending an EEP to the data at the output ports Once the packet has been removed from the network an EEP is ready to be appended to routing switch R2 port 5 when buffer space is available and the network path between routing switch R1 port 4 and routing switch R2 port 1 is available 99 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 20
109. ian Aerospace 8 3 5 Packet Blocking The Time Out Enable bit bit 0 of the router control register enables the watchdog timers on the ports When this bit is set and the watchdog timers are enabled the router is in Watchdog Timer mode When it is clear and the watchdog timers are disable then the router is in the Blocking Allowed mode In Blocking Allowed mode packets wait indefinitely on other packets to complete An exception to this is when an output port that a packet is to be routed to is a SpaceWire port and that port is not started In this case the packet waits as long as the timeout period and is then discarded if the output port has not started If group adaptive routing is being used and at least one of the destination ports is running then the packet will wait indefinitely for that output port to become free or another one in the group to Start In Watchdog Timer mode watchdog timers on the ports are used to clear packets from the network if they become blocked either while being routed or while waiting on a port which is not granted to any other port The watchdog timers are restarted every time a data character is transferred They are stopped after an EOP and started again on the first data character of a packet In this way the time to transfer a complete packet is not checked but instead the watchdog timers check if a packet has blocked i e no data transfers A blocked packet is spilt by terminating the packet at the
110. ian Aerospace Note The recommended method for setting the POR signals is to use external pull up down resistors e g 4k7 Q in which case the timing of the POR signals is not critical See section 6 3 and 6 4 for further information on the operation of the status power on configuration interface and section 10 5 for timing details 5 7 POWER GROUND PLL AND LVDS SIGNALS 5 7 1 General The Power Ground and special signal connections are listed in Table 5 7 Table 5 7 Power Ground and Special Signals Description Signal Type Ground connection for the device ag VCOBias eege PLL VCO Bias VSSPLL PLL Supply 3V3 VDDPLL PLL Supply GND LoopFilter PLL Loop Filter LVDSref mm LVDS Buffer reference 5 7 2 Decoupling The power pins should be decoupled to the ground plane One 100 nF decoupling capacitor should be used for each power pin 5 7 3 LVDS Reference An external resistor is required to provide a reference for the LVDS buffers A resistor with a value between 16 3 kQ and 16 7 KQ must be connected between LVDSref and ground 5 7 4 PLL External Components An internal PLL is used to provide the base transmit clock signal for the SoaceWire interfaces from the CLK input External components are required to implement the PLL loop filter and to provide a bias for the PLL VCO These components are illustrated in Figure 5 3 Note that Rvco C and CO are all connected to a quiet common ground track 47 SpW 1
111. ield in the transmit clock register See section 9 5 9 and the TX10MbitDIV field also in the transmit clock register 85 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 Austrian Aerospace The columns header TXRATE give the SpaceWire transmit data rate obtained for various settings of the TXRATE field in a SpaceWire port control register The duty cycle of the SpaceWire data rate clock is given in the row immediately underneath the TXRATE values If the duty cycle is not 1 1 then one bit period will be shorter than the next as for the 10 Mbits s data rate Again permitting a maximum 10 variation in the bit periods allows a worst case duty cycle of 9 11 The valid transmit data rate values which have corresponding valid 10Mbits s data rate values have a white background in the table The TXRATE divider is actually a 7 bit field so there are many more possible columns under TXRATE All of these TXRATE columns would give valid transmit data rates The values for these additional columns can be calculated using the formulae given above The Initialisation Data Rate columns of the table give the frequency of the 10 Mbits s clock used during initialisation and the duty cycle of adjacent bit periods The data rate must be in the range 9 11 Mbits s The actual 10 Mbits s data rate is produced from a 5 MHz clock signal using double data rate outputs
112. ill bytes is shown in the Figure 7 15 Path Address Fill Byte Fill Byte Fill Byte RMAP Header 0 0 0 0 Figure 7 15 Fill Bytes Configuration Header Structure Note that the command packet fill bytes feature is specific to the SoW 10X router and is not part of the RMAP standard 80 SpW 1 OX Ref UoD SpW 10X ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 Austrian Aerospace 8 CONTROL LOGIC AND OPERATIONAL MODES In this section the SpaceWire router control logic and operational modes are defined The router control logic determines how the SpaceWire link ports operate how received packets are routed to their destination and how the timeout mechanism detects packet blockages in the router 8 1 SPACEWIRE LINK CONTROL Each of the eight SpaceWire links has an associated SpaceWire control register The register records status information from each link including link error information link state and run status see section 9 4 3 The SpaceWire link control bits determine how the SpaceWire link operates The link control bits are Auto start default Link Start Link Disable and Deactivate The SpaceWire link data rate divider can also be set in the link control register The following paragraphs define each of the link control functions 8 1 1 Default operating mode The default operating mode is Auto Start This is the mode setting for each link afte
113. input port 1 has a packet waiting with logical address 80 which is high priority input port 1 will be selected first and the packet with logical address 80 transferred to output port 5 At stage three the high priority packet with logical address from input port 1 has been transferred and the remaining low priority packet from input port 3 is selected by the router to be transferred to output port 5 Addresses 80 HIGH Priority 52 LOW Priority 52 Previous port which accessed port 5 2 Packet at port number 3 waits Packet from port 3 is selected Packet from port 3 completes Figure 8 8 Arbitration of two packets with different priority 1 91 SpW 1 OX Ref UoD SpW 10X ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 GH Austrian Aerospace 8 3 2 4 Arbitration of packets with different priority 2 In Figure 8 8 another example of arbitration of packets with different priority is illustrated Only router ports 1 5 are shown for clarity At stage one input ports 1 and 3 have packets with logical addresses 80 and 52 respectively which are both to be routed to output port 5 Logical address 80 is high priority and 52 low priority Input port 4 has just finished transferring a packet to output port 5 At stage two the previous port selected by output port 5 was input port 4 therefore the high priority packet waiting at input port 1 which has logical
114. ire Node with Embedded Router Instrument Memory Unit Instrument Figure 2 3 Embedded Router In Figure 2 3 a SpaceWire system similar to that shown in Figure 2 1 is shown with the SpW 10X router embedded in a SpaceWire node along with a processor The processor interfaces can interface to the SpW 10X router using the external FIFO ports saving some SpaceWire ports for connecting to additional instruments For redundancy a pair of the SpaceWire nodes with embedded routers may be used 2 4 EXPANDING THE NUMBER OF ROUTER PORTS If a routing switch with a larger number of SpaceWire or external ports is required then this can be accomplished by joining together two or more routers using some of the SpaceWire links For example using two SpaceWire links to join together two router devices would create an effective router with twelve SpaceWire ports and four external ports Note however that an extra path addressing byte is needed to route packets between the two routers and that there is additional routing delay 20 SpW 10X Ref ASTRIUM on SpaceWire Router K School of Computing Issue UNDE User Manual Date Austrian Aerospace SpW 10X Router SpaceWire Ports SpW 10X Router Figure 2 4 Expanding the number of SpaceWire Ports 1 UoD SpW 10X UserManual 3 5 7 January 2015 Figure 2 4 shows a pair of SpW 10X routers connected together using the external FIFO ports to provide a 16 port router A small am
115. ire port 3 LVDS N Side 55 DOUTPlus 4 Out Differential output pair data part of Data Strobe LVDS P Side 54 DOUTMinus 4 SpaceWire port 4 LVDS N Side 67 DOUTPlus 5 Out Differential output pair data part of Data Strobe LVDS P Side 66 DOUTMinus 5 SpaceWire port 5 LVDS N Side 77 DOUTPlus 6 Out Differential output pair data part of Data Strobe LVDS P Side 76 DOUTMinus 6 SpaceWire port 6 LVDS N Side 87 DOUTPlus 7 Out Differential output pair data part of Data Strobe LVDS P Side 86 DOUTMinus 7 SpaceWire port 7 LVDS N Side 97 DOUTPlus 8 Out Differential output pair data part of Data Strobe LVDS P Side 96 DOUTMinus 8 SpaceWire port 8 LVDS N Side 22 21 32 31 40 39 53 52 P Side SOUTMinus 1 SpaceWire port 1 LVDS N Side t SOUTPlus 1 Differential output pair strobe part of Data Strobe LVDS SOUTPlus 2 Differential output pair strobe part of Data Strobe LVDS P Side t t SOUTMinus 2 SpaceWire port 2 LVDS N Side SOUTPlus 3 Differential output pair strobe part of Data Strobe LVDS P Side SOUTMinus 3 SpaceWire port 3 LVDS N Side SOUTPlus 4 Differential output pair strobe part of Data Strobe LVDS P Side u SOUTMinus 4 SpaceWire port 4 LVDS N Side u 65 SOUTPlus 5 Out Differential output pair strobe part of Data Strobe LVDS P Side 64 SOUTMinus 5 SpaceWire port 5 LVDS N Side 75 SOUTPlus 6 Out Differential output
116. it data rate TX10MbitDIV Note The transmit clock should not be disabled when an output port is sending data or when the interface is in the run state The port control status registers can be used to determine if an output port is currently connected to an input port and therefore transferring data 126 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual on SpaceWire Router K School of Computing Issue 3 5 Bam User Manual Date 7 January 2015 GI Austrian Aerospace WARNING If a SpaceWire port that is being used to configure a router has its transmit clock turned off then it will not be possible to configure the router using that port Unless there is another connection with an active clock and which is not disabled that can be used to perform configuration the router will have to be reset before it can be configured again 20 16 15 8 32 21 7 2 1 0 TXDIV Not used Enable clock Tx10MbitDIV Not used Figure 9 10 Transmit clock control register 127 ASTRIUM K School of Computing Issue DUNDEI SpW 10X Ref SpaceWire Router User Manual Date Austrian Aerospace Table 9 15 Transmit Clock Control Register Bits UoD SpW 10X UserManual 3 5 7 January 2015 1 0 TXDIV 01 the transmit clock as follows 00 gt divide by 2 01 gt divide by 4 10 gt divide by 8 11 gt divide by 8 transmit data rate will be 100Mbit s Transmit clock internal PLL outpu
117. l be automatically sent out of the same port that the command arrived on See section 7 6 8 First byte transmitted SSES Last byte transmitted Bits in Packet Type Command Source Address Path Length Byte MSB LSB poo o o o 1 1 cs lath assess renan Address Length Address Length je Packet Type ET e Command 3 Source Path Address Length Figure 7 6 Read Incrementing Address Reply Packet Format Table 7 10 Read Incrementing Address Reply Packet Fields pee sd Source Optional source path addresses specified in the command packet If no source Path path addresses are specified then the first byte will be the source logical Address address Logical addresses are not used then the source logical address is the address of the Address return packet Protocol The RMAP protocol identifier value Oth Identifier Source The source logical address specified in the command packet If source path 66 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 Austrian Aerospace Command Read incrementing address reply command byte The packet type bits in the Byte command byte indicate this packet is a reply packet Status The command status is returned in this field The command status can be command successful or an RMAP error code as defined in section 7 6 6 Destination The destination logical a
118. length of a write single address command is expected to be 4 bytes to write to a 32 bit register location The header CRC is the eight bit CRC code used to detect errors in the command packet The CRC code is checked before the command is 1 1 1 2 1 A 3 1 executed 1 The write address identifies the register to write the RMAP data The valid N SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 Bam User Manual Date 7 January 2015 H Austrian Aerospace In Figure 7 11 the format of the reply to a write command is illustrated The first byte sent by the SpaceWire router configuration logic is the port address followed by the destination logical address Fields which are depicted in bold text are expected values Fields which are shaded are optional Note that the reply is always sent out of the same port as the command was received on The Source Path Address should not include the output port of the router being commanded as the reply will be automatically sent out of the same port that the command arrived on See section 7 6 8 First byte transmitted Source Path Address Source Path Address Source Path Address l Protocol Identifier Packet Type Command Source Logical Address Source Path Addr Len Status Destination Logical A PIENO E SSES Transaction Identifier MS Transaction Identifier LS Reply CRC Last byte transmitted Bits in Packet Type Command Source
119. lication it is important to include additional integrity checks in critical SpaceWire packets This approach should also be used to mitigate the effects of the Parity Error anomaly 151 SpW 1 OX Ref UoD SpW 10X ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 weus User Manual Date 7 January 2015 GH Austrian Aerospace 14 TECHNICAL SUPPORT Technical support for the SpW 10X Router is provided by STAR Dundee Ltd A range of SpW 10X evaluation boards is available along with other test equipment cables etc See www star dundee com for details Technical support is provided by STAR Dundee All requests for support should be submitted to the Atmel support hotline Email assp applab hotline nto atmel com 152 SpW 1 OX Ref UoD SpW 10X ASTRIUM i UserManual on SpaceWire Router K School of Computing Issue 3 5 User Manual Date 7 January 2015 Austrian Aerospace 15 DOCUMENT CHANGES 15 1 ISSUE 3 4 TO ISSUE 3 5 Ref Change bel VE Table 5 2 SOUTMinus 4 pin location is pin 52 as indicated in section 4 Table 9 10 Correction to the POR_SEL_TIMEOUT_N pin polarity when reset is applied 0 maps to 1 3 milliseconds and 1 maps to 60 100 microseconds 10 Table 10 1 TBC notes removed from clock and reset timing parameters a Preliminary notice removed from footer 15 2 ISSUE 3 3 TO ISSUE 3 4 Ref Change WWW 13 1 ES error Se added to the list of anomalies E Update
120. link start up 010 1 6 data rate after link start up 001 1 7 data rate after link start up 000 1 8 data rate after link start up Note POR_TX_RATE affects all SpaceWire ports in the router Note The data rate is dependent on FEEDBDIV at reset STAT_MUX_OUT 3 If asserted low after reset allows a router CMOS3V3 port to address itself and therefore cause an input packet to be returned through the same input port This mode may only be suitable for debug and test operations This signal is active low maps to gt POR ADDR SELF N Power on reset signal which determines if CMOS3V3 output port timeouts are enabled at start up When asserted low the port timeouts are enabled When de asserted high they are disabled This signal is active low An external pull down resistor e g 4k7 Q is recommended on this pin so to enable the watchdog timers Power on reset value which determines the CMOS3V3 initial timeout value The following values determine which timeout is selected at power STAT MUX OUT 4 maps to gt POH TIMEOUT EN NI STAT MUX OUT 5 maps to gt POR SEL TIMEOUTO Ni SpW 1 OX Ref UoD SpW 10X ASTRIUM i UserManual on SpaceWire Router K School of Computing Issue 3 5 Pe User Manual Date 7 January 2015 up T gt Timeout period is 60 80 us 0 gt Timeout period is 1 3 ms Timeout Period is 1 gt 200x 2 2 x 10 MHz clk period OU gt 200x 2
121. me code is propagated to all time code ports except the port on which the time code was received lf the time code received is not one plus the value of the time code register then the time code register is updated but the tick out is not performed In this way circular network paths do not cause a constant stream of time codes to be sent in a loop 3 7 CONTROL STATUS REGISTERS The control and status registers in the SpaceWire router provide the means to control the operation of the router set the router configuration and parameters or monitor the status of the device The registers are accessed using RMAP AD2 command packets received by the configuration port 26 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual on SpaceWire Router K School of Computing Issue 3 5 Bam User Manual Date 7 January 2015 Austrian Aerospace 4 PINLOCATIONS The SpaceWire router package Is a 196 pin MQFPF package Type definition DE EE EN 3 3 Volt power EE Ground PIL seer CMOS input ad DL ec ceeeceeeee es pull down resistor min 16kQ max 80kQ d E EE PLL pins gt PFIEVDSZP wiccesctecatccnncs LVDS cold sparing input PFILVDSZPB LVDS cold sparing input negative input PFOLVDS3372P LVDS output 3 3V PFOLVDS33ZPB LVDS output 3 3V negative output PFOLVDSREFZ LVDS reference gt POAAP semen 4x driving strength output fast minimum slew rate control d EE 2x driving strength
122. mple schematic changed to a format that is readable 15 6 ISSUE 2 5 TO ISSUE 3 0 Entire Major edit providing clarifications and additional application document details throughout document section added on Application Guidelines giving example circuit diagram and PCB layout guidelines section added on anomalies and warnings Section added on Technical Support 15 7 ISSUE 2 4 TO ISSUE 2 5 15 8 ISSUE 2 3 TO ISSUE 2 4 Section Ref Change me __ Change from data sheettousermanual Tile Ade Atmel par number asa referens 5 2 SpaceWire Rename data strobe lOs so the naming is consistent in the Signals document Note pin names should map to pin names in the data sheet therefore use Plus Minus notation BI Power Additional information on power pins and PLL power supply Ground PLL circuitry and LVDS Signals Group Adaptive Add mapping of SpaceWire Ports 1 to 8 and External ports 9 155 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual on SpaceWire Router K School of Computing Issue 3 5 _ User Manual Date 7 January 2015 L Austrian Aerospace 1 Routing Table and 10 to the physical interface to the device Reference to ET tent presto et oN All Move switching and electrical characteristics to end of tt TEST 15 11 ISSUE 2 0 TO ISSUE 2 1 Change 15 12 ISSUE 1 7 TOISSUE 2 0 Change rr Final updates and editorial corrections before release 15 13 ISSUE 1 6 TO IS
123. n Aerospace Table 9 9 Router Identity Register Field Description Reset Read Write Value 31 0 Router All bits set A 32 bit read write register which may be used to R W Identity to Zero hold a unique router identity code for each router in a network 9 5 3 Router Control Register The router control register address is 258 0x0000 0102 The router control register sets various control bits in the SpaceWire router Router functions which can be controlled are e Request an output port to initiate start up when an input packet addresses that output port but it is not ready to receive data e Disconnect a SpaceWire port when no activity is detected on the port for the timeout period duration e Enable output port timeouts which request the output port to flush when a packet becomes blocked for a timeout period e Enable the a router ports to address themselves i e provide a loop back capability The router control register fields are shown in Figure 9 5 and described in Table 9 10 31 7 6 5 4 3 1 0 Timeout enable Timeout selection Enable disconnect on silence Enable start on request Enable self addressing Not used Figure 9 5 Router Control Register Fields 119 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 Bam User Manual GH Austrian Aerospace Date 7 January 2015 Table 9 10 Router Control Table 8 10 Router Control Register Fields Fields
124. n Port Group Adaptive Allows the setting of group adaptive routing logical 32 255 Routing Table addresses by assigning the output ports which should be 0x20 OxFF Registers accessed when a packet is received with logical address Port Control Status Controls the Configuration SpaceWire and External 0 31 Registers Ports Provides the status of the ports 0x00 Ox1F Router Control Status Controls the overall operation of the router Reports the 256 265 Registers router status 0x100 0x109 9 2 REGISTER ADDRESSES SUMMARY Table 9 2 lists all the registers in the configuration memory space 106 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual on SpaceWire Router K School of Computing Issue 3 5 Bam User Manual Date 7 January 2015 Austrian Aerospace 31 0 0x0000 001F 0x0000 0000 255 32 0x0000 00FF 0x0000 0020 9 3 GROUP ADAPTIVE ROUTING TABLE REGISTERS The Group Adaptive Routing GAR table is accessed through configuration memory addresses 32 255 0x0000 0020 0x0000 OOFF The fields in the GAR registers are illustrated in Figure 9 2 31 30 29 28 11 10 1 0 RESERVED REQUEST NOT USED DEL_HEAD PRIORITY INVALID ADDR Figure 9 2 GAR Register Fields The GAR table holds the routing table information that maps logical addresses to one or more port addresses There is one entry register in the GAR table for each possible logical address The 107 SpW 1 OX Ref UoD SpW 1
125. nabled When an invalid address packet is received by the router then the routing control logic flags the error to the corresponding port status register spills the packet address data and end of packet marker and waits for the next packet 56 SpW 1 OX Ref UoD SpW 10X ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 Austrian Aerospace 7 5 DATA PAGKETS Packets which have addresses in the range 1 to 255 are routed to the SpaceWire ports and the external ports dependent on the packet address Data packets have an address header byte a cargo field and an end of packet marker The normal packet structure is show below de CARGO EOP EEP Figure 7 1 Normal router data packets 7 6 COMMAND PAGKETS Command packets are routed to the internal configuration port when the packet address is zero Command packets perform write and read operations to registers in the SpaceWire router Command packets accepted by the SpaceWire router are in the form shown in Figure 7 2 Configuration read packets are in the form a COMMAND EOP Figure 7 2 Command Packet Format The SpaceWire router supports the Remote Memory Access Protocol RMAP AD2 for configuration of the internal router control registers and monitoring of the router status The following sections define the RMAP commands which are supported and the format of the RMAP commands used by the SpaceWire
126. ning the SpW 10X will wait indefinitely to send the packet whether or not Start on Request is enabled When the busy output port finished sending its packet the waiting packet will be sent 103 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual n SpaceWire Router K School of Computing Issue 3 5 User Manual Date 7 January 2015 GH Austrian Aerospace WARNING Packets can timeout and be spilled in a SpaceWire network without the destination receiving any notification of this Packets with errors e g parity error can arrive at a destination terminated by an EEP In a very special case it is also possible to receive an error free packet terminated by an EEP It is important that the destination node is able to handle these cases 104 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 Austrian Aerospace 9 REGISTER DEFINITIONS This section describes the internal configuration registers of the SpW 10X Router The following subsections contain register bit description tables which hold the following information e The bit numbers of each field e A descriptive name for each field e The reset value for each field e A description of what the each field in the register is used for e An indication of whether the field is readable and or writeable by a configuration command The internal register size is 32 bits unless otherwise
127. nnnnsnnennnnnensennnnnennennnn 131 TABLE 10 3 EXTERNAL PORT TIMING PARAMETERS 132 TABLE 10 4 TIME CODE INTERFACE TIMING PARAMETERS erennnnnnerrnnnnrrnnnnerrnnnnerennnenennnnerennnnerennnenennnnenennnnenennnesee 133 TABLE 10 5 STATUS MULTIPLEXER TIMING PARAMETERS sssssssssseeerssserersssetersssrtrsssertrsssereressrrerssereressereressereeee 134 TABLE 10 6 SPACEWIRE ROUTER LATENCY AND JITTER MEASUREMENTS BIT RATE 200MBITS S 0 aaaaaen 137 TABLE 11 OPERATING CONDITIONS sms 138 TABLE 11 2 ABSOLUTE MAXIMUM RATINGS wisccsasdesacsnncssseranevansandecsnesakdbeses nuevamenasslenssakentsvewnevendcoieusesneinalaniertness 139 PET LS E ICTY INFORMA TION v re 139 14 DUNDEI School of omputing SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router Issue 3 5 User Manual Date 7 January 2015 GH Austrian Aerospace 1 INTRODUCTION This document is a technical reference for the implementation and operation of the SpW 10X SpaceWire Router device Atmel part number AT7910E Note Detailed timing information for the ASIC implementation will be available in 1Q08 1 1 TERMS ACRONYMS AND ABBREVIATIONS 3V3 AAe ACK AD CLK CRC DC ECSS EEP EOP FIFO FPGA GND LVDS NACK PLL RD RMAP RST SpW TBA TBC UoD 3 3 volt interface levels Austrian Aerospace GmbH Acknowledge Applicable Document Clock Input clock to the SpaceWire router Cyclic Redundancy Check Direct Current European Coop
128. nput dala EXTINDATAN me Extema FIFO por 9 inputaala EXTINDATAQ me Extema FIFO por 9 input dala o me me 7 LI kb kb PIC PIC PIC PIC PIC VSSE EXTOUTDATATOG aA ON men EXTOUTDATATOG 30 mg SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual n SpaceWire Router K School of Computing Issue 3 5 User Manual Date 7 January 2015 EXTOUTDATATO EXTINDATATOL EXTINDATATO 2 EXTINDATATOG EXTINDATATOG EXTTIMEIN O Time code input Time code input IC IC IC IC C EXTTIMEIN 1 EXTTIMEIN 2 EXTTIMEING EXTTIMEIN 4 EXTTIMEIN 5 Time code input EXTTIMEIN 6 Time code input EXTTIMEIN 7 Time code input Time code counter input selection EXTTIMEOUT EXTTIMEOUT 2 Time code output 31 N s Sr Nr Nr Vs Nr Nr Nr N ss Sr Nr SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual on SpaceWire Router K School of Computing Issue 3 5 Bam User Manual Date 7 January 2015 Austrian Aerospace STATMUXADDR STATMUXOUT 3 avs Power a 5 tri G STATMUXOUTE STATMUXOUT 7 32 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 weus User Manual Date 7 January 2015 GH Austrian Aerospace 5 DEVICE INTERFACE The device pins used by each interface are described in this section There is a table for each type of interface listing the
129. nter to CMOS3V3 be reset to zero The timing parameters used for EXT TICK IN also apply to the time code counter reset signal TIME CTR RST If the time code port is not being used this input should be pulled down e g 4k7 Q 169 EXT TICK OUT The falling edge of EXT TICK OUT is used to CMOS3V3 indicated the reception of a time code The value of this time code is place on the EXT TIME OUT 7 0 outputs and is valid on the rising edge of EXT TICK OUT EXT TIME OUT 7 Out Received time code value which is valid when CMOS3V3 EXT TIME OUT 6 EXT TICK OUT is asserted 8 EXT TIME OUT 5 EXT TIME OUT 4 The value of a received time code is output on the EXT TIME OUT 3 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual on SpaceWire Router K School of Computing Issue 3 5 Bam User Manual Date 7 January 2015 Austrian Aerospace EXT TIME OUT falling edge of EXT TICK OUT The EXT TIME OUT 1 EXT TIME OUT 7 0 value is held until the next EXT TIME OUT 0 time code is output See section 6 2 for information on the operation of the time code interface and section 10 4 for timing details 5 5 STATUS INTERFAGE SIGNALS The status interface signals are listed in Table 5 5 Table 5 5 Link error indication Signals Description Signal 183 STAT MUX ADDR 3 in Select the error indication status signals to be CMOS3V3 182 STAT MUX ADDR 2 output on STAT MUX OUT as defined in 181 STAT MUX ADDR 1 Table 6 1 180 STAT MUX ADDR
130. nual Date 7 January 2015 ey Austrian Aerospace LIST OF FIGURES PIGURE 2 STAND ALONE ROUTER vr 18 FIGURE 2 2 NODE INTERFACE siscccansiacenatoimneonnnianigatosndssaronenteaknnnes anani edhe aa On a iann a an ah isna ai a r sS 19 FIGURE 2 3 EMBEDDED ROUTER Lap 20 FIGURE 2 4 EXPANDING THE NUMBER OF SPACEWIRE PORTS lh 21 FIGURE 2 5 EXPANDING THE NUMBER OF SPACEWIRE PORTS 2 ccccccsscccseccesecccsecsecscccesscseecseecsseusseessceueseees 22 FIGURE 3 1 SPACEWIRE ROUTER BLOCK DIAGRAM errnrnnrnnnnnrrnnvnnnnnrnnnnnnnsrnnnnnnnsnnnnnnnnnnnnnnnnnnnnnnnnnensnnnnnnnssnnnnnnnsnnnnnn 24 FIGURE 5 1 LVDS RECEIVER FAIL SAFE RpsisrtOoRsg aT FIGURE 5 2 CONFIGURATION INTERFACE TIMING SPECIFICATION sssssnonnnnssseeeeeoosssseetrrosssseetreosrssseerreossssseereessssse Ad FIGURE 5 3 PLL WITH EXTERNAL COMPONDNTS 48 FIGURE 6 1 EXTERNAL PORT WRITE TIMING SPECIFICATION ssssnnnnnssssseeeeoossseeeeeoossssseterosssssetrrossssserereosssssreresssses 49 FIGURE 6 2 EXTERNAL PORT READ TIMING SPECIFICATION cccccccssseseeccccecceeeeeecccceeeaassseeecceeesaaseeecceseesaaeeeeeeeeeeas 50 FIGURE 6 3 TIME CODE INPUT INTERPACE 50 FIGURE 6 4 TIME CODE OUTPUT INTERFACE ooonnnnnnnnnnnnnnnnnnrnnnnnnnnnrnnnnnnnnnnnsnnnnrnnnnnnnssnnnnnnnnnnnnssnnnnnnnnnnesssennnnnnnnnessnee 51 FIGURE 6 5 TIME CODE RESET INTEBRPACE 51 FIGURE 6 6 STATUS MULTIPLEXER OUTPUT DNTERPACR 51 FIGURE 6 7 RESET CONFIGURATION INTERFACE TIMING SP CTIPICATION 53 FIGURE 7 1 NORMAL RO
131. oD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 Pran User Manual Date 7 January 2015 GH Austrian Aerospace should be pulled down e g 4k7 Q EXT TIME IN 7 0 provides the value of the time geg code to be distributed by the router when an external time code source is selected i e when SEL EXT TIME is high on the rising edge of EXT TICK IN When SEL EXT TIME is high on the rising edge of EST TICK IN the value of the time code counter is used for bits 5 0 of the time code and bits 7 6 of the EXT TIME IN 7 0 are used for the two control signals bits 7 6 of the time code If the time code port is not being used these inputs should be pulled down e g 4k7 Q 167 SEL EXT TIME lf SEL EXT TIME is high on the rising edge of CMOS3V3 EXT TICK IN the value on EXT TIME IN 7 0 is loaded into the internal time code register and propagated by the router lf SEL EXT TIME is low on the rising edge of EXT TICK IN the value to be sent in the time code will be taken from the internal time code counter in the router The two control bits bits 7 6 of the time code will come from bits 7 6 of the EXT TIME IN 7 0 input If the time code port is not being used this input should be pulled down e g 4k7 Q EXT TIME IN 7 EXT TIME IN 6 EXT TIME IN 5 EXT TIME IN 4 EXT TIME IN 3 EXT TIME IN 2 EXT TIME IN 1 EXT TIME IN 0 168 TIME CTR RST This signal causes the internal time code cou
132. oblem a small bias current can be passed through the termination resistor generating a small positive voltage across the bias resistor and forcing the output of the LVDS receiver to logic 1 Now any noise current smaller than this bias current will not cause the receiver to transition The bias current can be supplied by a pair of resistors connected to the power and ground rails as illustrated in Figure 5 1 Disconnected Inputs Figure 5 1 LVDS Receiver Fail Safe Resistors The current generator In represents any noise picked up by the disconnected SpaceWire cable or PCB tracks In Figure 5 1 In is shown as a negative current which causes a negative differential voltage across the termination resistor Rr The bias resistors Ri and Re cause a bias current In to flow through the termination resistor Provided that the bias current is greater than any negative noise current the output of the LVDS receiver will be logic 1 If the noise current is positive then the LVDS receiver output is logic 1 anyway The bias resistors must be chosen to give a bias current through the termination resistor greater than any expected noise current when the input is disconnected Note that careful PCB design can reduce electro magnetic interference and reduce the noise current 37 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 Austrian Aerospace The
133. ormal operation Internal pull down Tie to ground Set the output clock rate of the internal PLL as CMOS3V3 FEEDBDIV 1 follows Internal pull down FEEDBDIV 0 000 gt 100MHz 001 gt 120MHz 010 gt 140MHz 011 gt 160MHz 100 gt 180MHz 101 gt 200MHz 110 gt 200MHz 111 gt 200MHz See section 8 1 6 for setting the transmit rate See section 10 1 for timing details WARNING Simultaneous data strobe transitions can occur during reset and power up This is not a problem when connected to SpaceWire compliant devices but is a problem when connected to IEEE 1355 devices 5 2 SPACEWIRE SIGNALS 5 2 1 SpW 10X SpaceWire Signals The SpaceWire interface signals are listed in Table 5 2 For further details about SpaceWire see the SpaceWire standard AD1 The LVDS inputs and outputs are cold sparing RD3 34 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router School of Computing Issue 3 5 User Manual Date 7 January 2015 Table 5 2 Data and Strobe SpaceWire Signals a eege 24 DOUTPlus 1 Out Differential output pair data part of Data Strobe LVDS P Side 23 DOUTMinus 1 SpaceWire port 1 LVDS N Side 34 DOUTPlus 2 Out Differential output pair data part of Data Strobe LVDS P Side 33 DOUTMinus 2 SpaceWire port 2 LVDS N Side 46 DOUTPlus 3 Out Differential output pair data part of Data Strobe LVDS P Side 45 DOUTMinus 3 SpaceW
134. ort 3 waits until all of the packet from input port 1 has been transferred At stage three the complete packet has been transferred from input port 1 Now input port 3 is able to transfer its packet to output port 5 Two packets waiting to use port 5 Packet from port 1 is selected Previous port which accessed port 5 3 Packet from port 1 completes Packet from port 3 is completes Packet from port 3 is selected Figure 8 6 Arbitration of two packets with matching priority 89 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 GH Austrian Aerospace 8 3 2 2 Arbitration of packets with matching priority 2 In the Figure 8 7 another example of arbitrating between packets with the same priority is illustrated Again only router ports 1 5 are shown for clarity At stage one input ports 1 and 3 have packets to be routed to output port 5 The previous input port to use output port 5 was input port 3 therefore the next input port to be selected by output port 5 will be input port 1 assuming input ports 6 7 8 9 10 and O are not requesting to use the port At stage two the router selects the packet at input port 1 and a packet is routed to output port 5 Input port 3 waits until the complete packet has been transferred While the packet from input port 1 Is being transferred to output port 5 another packet arrives at input port 2 to be ro
135. ould be placed as close as possible to the output pins of the SpW 10X device Series termination resistors are also recommended on the devices driving the External FIFO port inputs if the tracks connected to the inputs are more than 4 cm in length The pull up down resistor recommendations provided in section 5 3 should be followed 12 2 8 Time code Interface The following recommendations apply to the Time code signals from the SpW 10X device 1 When the time code interface is used series termination resistors 83 ohm should be fitted to each output if the tracks on the outputs are more than 4 cm in length The series termination resistors should be placed as close as possible to the output pins of the SpW 10X device Series termination resistors are also recommended on the devices driving the time code inputs if the tracks connected to these inputs are more than 4 cm in length The pull up down resistor recommendations provided in section 5 4 should be followed 12 2 9 Status Power On Configuration Interface The pull up down resistor recommendations provided in section 5 6 should be followed for power on configuration 143 SpW 1 OX Ref UoD SpW 10X ASTRIUM i UserManual Di SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 Austrian Aerospace 12 2 10 PLL See Figure 12 1 the internal wiring of PLL block to better understand the external board recommended layout The Vol
136. ount of external logic is required to connect the external FIFO ports in this way Note that the bandwidth between the two SpW 10X devices is limited by the two external FIFO ports used to interconnect them Each FIFO port can handle one SpaceWire packet at a time in each direction SpW 10X Router SpaceWire User FPGA Ports a Processor SpW 10X Router 21 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 DUNDEI User Manual Date 7 January 2015 GH Austrian Aerospace Figure 2 5 Expanding the number of SpaceWire Ports 2 Figure 2 5 shows two SpW 10X router devices interconnected using two of the SpaceWire ports on each router This leaves twelve SpaceWire ports for connection to other SpaceWire nodes The External FIFO ports of each router are used to connect to user logic in an FPGA or to a processing device 22 SpW 1 OX Ref UoD SpW 10X ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 Austrian Aerospace 3 FUNCTIONAL OVERVIEW A SpaceWire routing switch comprises a number of SpaceWire ports and a routing matrix The routing matrix enables packets arriving at one SpaceWire port to be transferred to and sent out of another port on the routing switch A SpaceWire routing switch is thus able to connect together many SpaceWire nodes providing a means of routing packets between the nodes connect
137. output with tristate fast minimum slew rate control a Tage mm pen Chip test pr mmm mmm toen leen jam fam Power e mmm Pm PI dveri FEEDBDIV 2 PLL divider bit 2 MS Ground E PLL VCO bias vSSPLL put an DINPlus 1 PFILVDSZP SpW port 1 input data 2 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual n SpaceWire Router K School of Computing Issue 3 5 User Manual Date 7 January 2015 Sms en SOUT GND emeng pen Seen Ce 28 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router School of Computing Issue 3 5 User Manual Date 7 January 2015 o DINPusG ____ _ _ PFILVDSZP_ SpWpor Sinputdata e6 DOUTWinus 5 ____ PFOLVDSGS2P8 SpW por Soutputdata e fomus mme aset m DINMinus 6 _____ PFILVDSZPE__ SpW pone mouta PFOLVDSSS2P 80 aen PFILVDSZP_ SpWpor Tinputsivobe x me poum PFOLVDSGS2P8 SpW por Toutputdata mm DINWinus PFILVDSZPE_ SpW por 8 mpata 90 aen ze DOUTWinus _____ PFOLVDSGS2P8_ SpW por Boutputdata 29 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual on SpaceWire Router K School of Computing Issue 3 5 Pro User Manual Date 7 January 2015 me e Je Cron mm p fave Power EXTOUTDATASU EXTOUTOATAS EXTOUTOATAS A EN EXTOUTDATAS EXTOUTDATAS ms JEXnNDATANO me fEmemaififOpotdmpadda ms ExnNDATAN me Eemal FIFO por S input aala EXTINDATAN me Extemal FIFO por 9 i
138. pair strobe part of Data Strobe LVDS P Side 74 SOUTMinus 6 SpaceWire port 6 LVDS N Side 83 SOUTPlus 7 Out Differential output pair strobe part of Data Strobe LVDS P Side 82 SOUTMinus 7 SpaceWire port 7 LVDS N Side 95 SOUTPlus 8 Out Differential output pair strobe part of Data Strobe LVDS P Side 94 SOUTMinus 8 SpaceWire port 8 LVDS N Side 35 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router School of Computing Issue 3 5 User Manual Date 7 January 2015 17 DINPlus 1 Differential input pair data part of Data Strobe LVDS P Side 18 DINMinus 1 SpaceWire port 1 LVDS N Side DINPlus 2 MENE input pair data part of Data Strobe LVDS P SE MG DINPlus 3 EEE input pair data part of Data Strobe LVDS P 210e ommusa ease eneen DINPIus 4 Me input pair data part of Data Strobe LVDS P per 1 mn 1 eme een DINPlus 5 el input pair data part of Data Strobe LVDS P mice 1 men 1 eme sien DINPlus 6 EEE input pair data part of Data Strobe LVDS P DE co mm eme LS DINPlus 7 MENE input pair data part of Data Strobe LVDS P SE no omme 1 eme sien DINPlus 8 PENE input pair data part of Data Strobe LVDS P SIE eo mm eme LS SINPlus 1 eure input pair strobe part of Data Strobe LVDS P SE RRE eegent SINPlus 2 EE input pair strobe part of Data Strobe LVDS P ser a aen eme LS SINPlus 3 sl le input pair strobe part of Data Strobe LVDS P SE o
139. pins of the SpW 10X shall be directly connected to the ground plane using vias close to the SpW 10X ground pins 12 2 6 SpaceWire The following recommendations apply to all the SpaceWire signals from the SpW 10X device see also section 5 2 1 LVDS receiver termination resistor shall be as close as possible to the receiver inputs 142 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 Austrian Aerospace 2 LVDS fail safe resistors need not be adjacent to the termination resistor Their location is not critical but the stub lengths to the termination resistors should be less than 20 mm 3 LVDS tracks shall be 100 ohm differential impedance 4 Skew between the plus and minus sides of the LVDS differential pair shall be avoided and shall be less than 1 mm 5 Data and strobe track lengths shall be matched to 2 5 mm to keep skew to a minimum 6 There is no need to match input and output track lengths 7 Vias shall only be used at the SpaceWire connector and close to the SpW 10X device within 5 mm 12 2 7 External Ports The following recommendations apply to the External FIFO port signals from the SoW 10X device 1 When the External FIFO ports are used series termination resistors 33 ohm should be used on each output if the tracks on the outputs are more than 4 cm in length The series termination resistors sh
140. r 2007 Issue 2 3 Modifications to SpaceWire Chris McClements signal names Map pin 1 to 0 Gerald Kempf Steve Parkes Footer indicates Preliminary Steve Parkes 3 4 December 2007 Issue 2 4 Updates as user manual Chris McClements Changed document name to Gerald Kempf UoD_SpW_10X_UserManual doc 11 December 2007 Issue 2 5 Redistribute with PLL settings Chris McClements Gerald Kempf 18 January 2008 Issue 3 0 Major edit providing clarifications Steve Parkes and additional application details throughout document Section added on Application Guidelines giving example circuit diagram and PCB layout SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 GH Austrian Aerospace guidelines Section added on anomalies and warnings Section added on Technical Support 20 January 2008 Issue 3 1 Corrections and example Steve Parkes schematic improved 18 April 2008 Issue 3 2 Explanation of non blocking Steve Parkes cross bar switch added Cold sparing information added VCO bias resistor value corrected Section 5 7 4 Tri state mode changed to deactivate mode Description for time code flag mode bit added Reliability information added Anomaly 2 resolved Details and workarounds for reset anomaly provided RD 3 changed Steve Parkes Editorial corrections Correction to reset
141. r power on or reset 8 1 2 Auto Start In auto start mode the SpaceWire port will remain inactive until a connection attempt is made by the SpaceWire device at the other end of the SpaceWire link The port will then start up and make the connection The Auto Start mode in conjunction with the automatic Link Start and disable modes can help reduce power consumption by only activating SpaceWire links when packet data is transferred See section 0 8 1 3 Link Start The link start control bit commands the SpaceWire port to try to make a connection with a SpaceWire device at the other end of the link Assuming a SpaceWire device is connected to the other end of the link the SpaceWire port will move to state Run Data transfer can take place when the link is started and the Link state is Run 81 SpW 1 OX Ref UoD SpW 10X ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 Austrian Aerospace 8 1 4 Link Disable The SpaceWire port can be disabled therefore rendering the link unusable When a SpaceWire link which is running is disabled it will disconnect from the far end and refuse connection attempts by the far end of the link Caution should be used when using this command for a stand alone router as disabling all the links will leave the router unusable except through a reset operation WARNING If the link that is being used to configure the router is disabled then i
142. ransaction identifier identifies the command packet and reply packet with a unique number The extended read address is not used in the SpaceWire router and shall always be set to zero The read address identifies the start address for the read incrementing command The valid starting read addresses are defined in section 9 The data length defines the number of bytes to read from the router Valid data lengths are in the range 4 1064 1064 allows the all the router registers to be read in one command If the data length field is not a multiple of four bytes then the command is rejected by the SpaceWire router The header CRC is the eight bit CRC code used to detect errors in the command packet The CRC code is checked before the command is executed 65 KoT SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 H Austrian Aerospace In Figure 7 6 the format of the reply to a read incrementing address command is illustrated The first byte sent by the SpaceWire router configuration logic is the port address followed by the destination logical address Fields which are depicted in bold text are expected values Fields which are shaded are optional Note that the reply is always sent out of the same port as the command was received on The Source Path Address should not include the output port of the router being commanded as the reply wil
143. ress The early EOP bit is set when the command packet is terminated before the end of packet with an EOP The late EOP bit is set when the command Early EOP packet is not terminated correctly and trailing bytes are detected before the end of packet 0 Late EOP Early EEP Late EEP Verify Buffer Overrun Error sch The early EEP bit is set when the command packet is terminated before the end of packet with an EEP The late EEP bit is set when the command packet is not terminated correctly and trailing bytes are detected before the end of packet NO QD The verify buffer overrun error bit is set when a verified write command is performed and the data length is not 4 ech N SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 Austrian Aerospace Invalid Register Address 15 Unsupported protocol error The invalid register address bit is set when an unknown register address is given in the command packet or a write is attempted to a read only register The unsupported protocol error bit is set when a command packet is received with a protocol identifier which is not the RMAP protocol identifier of O1h This bit in the register is not used The RMAP command packet is too large The command code is an unused command code or the packet type is invalid Cargo too large 19 Unused RMAP command or
144. router output port with an EEP and spilling the remainder of the packet to be transmitted up to and including the EOP at the router input port If the router output port is blocked full and cannot accept data then the EEP is added after the port Is unblocked WARNING Blocking Allowed mode is not recommended and should be used with caution When Blocking Allowed mode is used Watchdog timers disabled then it is important that provision is made for a network manager to detect blocking situations and to reset the nodes or routers causing the problem The various ways in which an input port can become blocked and the resulting actions taken by the router are considered in the following sub sections 8 3 5 1 Blocked destination In a blocked destination scenario data cannot be transmitted to the destination port because there is no more transmit credit no more FCTs received in a SpaceWire port or an external port output FIFO has become full Since the destination node is blocked the packet data is left strung out across the SpaceWire network from the packet source to the blockage In this situation the tail of the packet is distributed across multiple routers and other network paths can become blocked waiting on the original blocked packet to complete 97 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 Austrian Aerospace In blockin
145. rrnrrsrrsrrsnrnnrrnrrurrsrrnrnnernrrnrrnrrerrnnnne 136 gt Wee e EE EE 137 10 6 6 200M bits s Input and Output Bit Rate Example rrrrnrrrnnrornnrernnrernnnennnnennnnennnnennnnennnnennnnr 137 11 ELECTRICAL CHARACTERISTICS nnnnnnnennnnennnnennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 138 l DOMMEN TERS ete pete ete epee ties tte eetees aces asin sen ates cee tee ite tee eee tes ieee teen ee 138 Tee ABSOLUTE MAX Ee 139 11 3 RELIABILITY INFORMATION 139 12 APPECGSTONGIDENNES 2 cs 140 SW ee RN EI CRAN E 140 22 PCOS DESIGN AND LAYOUT GUIDELINE Lue 142 EEN 142 EECHER RSEN e 142 22 CAP LoS ele 142 1222 Power nd Decoupling sisi cstrsstuostanetas cum terterudesabensdaieastumtuindanetidueadeidarudnaadindewdesneuens 142 den NN 142 12 2 6 DIM 142 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 Bam User Manual Date 7 January 2015 ER Austrian Aerospace Wesel EAN 143 12 250 EE 143 12 2 9 Status Power On Configuration Interface rnnnnnnnnnnnnnrnnnnnnnnnrnnnnnnnnnnnrennnnnrnnnnnennnnnnnnnnn 143 EEA E REN 144 13 ANOMALIES AND WARNINGS uunnnnvennnnnevnnnnennnnnennnnnennnnnennnnnennnnnernnnnnrnnnnernnnnnnnnnnnrnnnnnnnnnnnen 145 1 NOME e e 145 Ee 145 133 RESETANOMALY EN 147 13 3 1 Data Strobe Reset Waveform rrrrnnnrrnnnrrrnnrennnrrnnnrrnnnrennnrrnnnrennnrennnrennnrennnrennnsennnrennnsennnee 147 13 3 2 Data Strobe Disable WV AV C
146. running and currently sending a packet the newly arrived packet will wait indefinitely for the output port to finish sending is current packet The waiting packet will then be sent This approach is taken because it is clear that the output port is operational and not blocked so the newly arrived packet will wait for the current packet to complete transfer Output port in a group not running A packet arrives at an input port of the SoW 10 router and the packet has a logical address addressing a group of possible output ports If all of the ports in the group are not running the router will wait for an output port to start for the watchdog timeout period and will then spill the packet if one of the links has not started If Start on Request is enabled then the router will try to start all the ports in the group The packet will be router to whichever port starts first If none of the ports starts before the timeout interval has expired the packet will be spilt Output port in a group with one port running and not busy If a packet arrives at an input port with a group logical address and one of the output ports in the group is running and not currently busy sending a packet the newly arrived packet will be routed to that output port immediately Output port in a group with one port busy If a packet arrives with a group logical address and one of the output ports in the group is busy sending a packet and the other output ports in the group are not run
147. s ce Config Port Address Destination Logical Address Protocol Identifier Command Byte Destination Key Source Path Address Source Logical Address Transaction Identifier Extended Read Address Read Address The configuration port address field routes the packet to the configuration port of the router The configuration port address 00h is always present when configuring the SpaceWire Router The destination logical address field is not used in the SpaceWire Router The SpaceWire router accepts packets which have the default destination logical address of 254h FEh The RMAP protocol identifier is 01h The command byte indicates a read single address packet The Source path address length fields are set to the number of source path addresses required as defined in section 7 6 9 The destination key identifier must match the contents of the destination key register see section 9 5 10 The default power on destination key is 20h The source path address field is used to add source path addresses to the 0 4 8 12 head of the reply packet The expected number of source path addresses is specified in the command byte See section 7 6 9 for source path address decoding The source logical address should be set to the logical address of the node which sent the command The transaction identifier identifies the command packet and reply packet with a unique number The exten
148. sabled as defined in the SpaceWire standard AD1 the SpaceWire port will not start and will not respond to any attempt to make a connection by the other end of the link 15 Deactivate When set the DOUT and SOUT R W serial SoaceWire signals will be deactivated dependent on the state of the SpaceWire link interface The DOUT and SOUT deactivate output state mappings are listed below ErrorReset gt Deactivate ErrorWait gt Deactivate Ready gt Deactivate Started gt Enabled Connecting gt Enabled Run gt Enabled Note DOUT is deactivated one system clock cycle before SOUT to ensure simultaneous edges due to output port deactivation do not occur 22 16 Transmitter Bits 18 to 16 are set Allows the SpaceWire link data data signalling according to the signalling rate to be set rate POR TX RATE 2 0 pins TXRATE Bits 22 18 are set to zero See section 8 1 6 for details on how to set the TXRATE bits Note bits 22 16 must not be set to all ones Bits 22 16 must not be set to give a transmit rate of less than 2 Mbits s 116 SpW 1 OX Ref UoD SpW 10X ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 Austrian Aerospace 9 4 4 External port control status register bits The port control status fields specific to the External port are described in Table 9 7 Table 9 7 External Port Control Status Fields Reset Description Read Wri
149. simplest way to overcome this potential problem is to ensure that the LVDS devices driving the SoW 10X device are all powered by 3 3V 145 SpW 1 OX Ref UoD SpW 10X ASTRIUM i UserManual SpaceWire Router School of Computing Issue 3 5 User Manual Date 7 January 2015 WARNING The deactivate mode see also section 9 4 3 does not tri state the LVDS outputs The LVDS outputs are cold sparing and when disabled both outputs in an LVDS differential pair are pulled up to 3 3V and have an impedance of the order of 1 kohm Since they are differential outputs and are both are at the same voltage no current will flow If however external noise bias resistors are being used then a small current around 200 uA 0 7 mW power can flow This is substantially less than the normal operating current of LVDS outputs and hence saves power WARNING In most onboard applications it is recommended to have Stat_mux_out 4 pulled low by default in order to enable the watchdog timers on reset WARNING When the watchdog timers are not enabled the SpaceWire and external ports can block indefinitely if for example a source stops sending data in the middle of a packet If watchdog timers are not enabled then it must be possible for a network manager to detect blocking situations and to reset the router or node creating the problem WARNING If the link that is being used to configure the router is disabled then it will not be possible to configure
150. sms eme siet SINPlus 4 eee input pair strobe part of Data Strobe LVDS P Bice Mee Gr SINPlus 5 ee input pair strobe part of Data Strobe LVDS P SEN aen eme ies SINPlus 6 EHS input pair strobe part of Data Strobe LVDS P elec smal eens eines SINPlus 7 Peer input pair strobe part of Data Strobe LVDS P E er sne 1 eme siet SINPlus 8 SE input pair strobe part of Data Strobe LVDS g pe o Lomami eme ies See section 10 2 for timing details SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 Austrian Aerospace 5 2 2 SpaceWire Input Fail Safe Resistors If a SpaceWire input becomes disconnected then no current flows through the termination resistor The differential voltage across this resistor is then zero A small noise current induced by electro magnetic interference on PCB tracks or on any part of the SpaceWire cable still attached to the receiver will cause a small differential voltage across the termination resistor If this is positive the receiver output will be logic 1 and if it the noise current flows in the other direction giving a negative differential voltage the receiver output will be logic 0 Just a small amount of noise is sufficient to cause the output of the LVDS receiver to transition from 0 to 1 and back continuously This noise can sometime start a SpaceWire link erroneously To overcome this pr
151. specified in the register description There are 263 registers in the configuration port addresses Registers that are shorter than 32 bits or that have unused fields will return zero in all the unused bit positions when read The unused bit positions are ignored during writing but should in any case be set to Zero 9 1 INTERNAL MEMORY MAP The memory map for the SpaceWire Router is shown in Figure 9 1 255 255 GROUP ADAPTIVE ROUTING TABLE REGISTERS ROUTER CONTROL STATUS REGISTERS 32 31 PORT CONTROL STATUS REGISTERS 0 0 Address bit 8 0 Address bit 8 1 Figure 9 1 Router Internal Memory Map The Group Adaptive Routing GAR registers map SpaceWire logical addresses 32 255 to the physical ports SpaceWire ports or External ports The link control status registers are used to configure the ports and router functions and to report status information The router control status 105 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 GH Austrian Aerospace registers allow the router management control and status information to be accessed by a network manager using configuration commands Table 9 1 provides an overview of each of the different types of register within the configuration port Each register type is then described in detail in the following subsections Table 9 1 Types of Register within Configuratio
152. st bit of data out of transmitter Worst case where transmitter is sending a time code and FCT character before data TESDATA 4 x Ts YSPERIOD 23 X I TXPERIOD External port to External port External port write enable to external port not empty flag TEEDATA 5 x Ts YSPERIOD 10 6 4 Time code Latency The maximum time taken to propagate a time code through a routing switch SpaceWire port to SpaceWire port Last bit of time code into receiver to last bit of time code out of transmitter worst case where transmitter has started sending a before time code data character Tsstc 5 X TRxPERIOD 6 x Testen 1 6 x TTXPERIOD SpaceWire port to External port Last bit of time code into receiver to external port EST TICK OUT rising edge Tserc 5 X T RXPERIOD 8 x Ts YSPERIOD External port to SpaceWire port EXT_TICK_IN rising edge to last bit of time code out of transmitter worst case where transmitter has started sending a before time code data character Teste 6 x Tsyseriop H 6 x TTxPERIOD 136 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual n SpaceWire Router K School of Computing Issue 3 5 omg User Manual Date 7 January 2015 Austrian Aerospace 10 6 5 Time code Jitter The variation in time to propagate a time code through a routing switch Time code jitter occurs in the synchronisation handshaking circuits and the transmitter where the maximum delay time the time code has to w
153. sters In Figure 7 10 the first byte received by the SpaceWire router configuration logic is the port address followed by the destination logical address Fields which are depicted in bold text are expected values Fields which are shaded are optional La ae E Source Path Address Source Path Address Source Path Address Source Path Address E Write A Source Logical Address Transaction Identifier MS Transaction Identifier LS MENE AE Write Address MS Write Address Data Length MS Data Length Data Length LS Config Port Address 00h Destination Logical Address Protocol Identifier Packet Type Command Destination K FEh 01h Source Path Addr Len re 00h h h Bits in Packet Type Command Source Path Address Length Byte MSB LSB ee ae ee ee Address Length Address Length ee Packet Type p Command Source Path Address Length Figure 7 10 Write Single Address Command Packet Table 7 15 Write Single Address Command Packet Fields ed ac ee 1 Config Port The configuration port address field routes the packet to the configuration Address port of the router The configuration port address is always present when configuring the SpaceWire Router Address address of 254h FEh Protocol The RMAP protocol identifier is 01h Identifier Destination The destination logical address is not used in the SpaceWire Router The 1 Logical SpaceWire router accepts packets which have the default destination logical
154. stination Logical A SSC HEEN Ge ndress Transaction Identifier MS Transaction Identifier LS Data Length MS Data Length Data Length LS Last byte transmitted Bits in Packet Type Command Source Address Path Length Byte MSB LSB RECH Address Length Address Length Packet Type ee Command _ Source Path Address Length if Figure 7 4 Read Single Address Reply Packet Format Table 7 7 Read Single Address Reply Packet Fields pee Prem 0 Source The source logical address specified in the command packet If source path Logical addresses are not used then the source logical address is the address of the Address return packet Source Optional source path addresses specified in the command packet If no source gt Path path addresses are specified then the first byte will be the source logical Address address 61 SpW 1 OX Ref UoD SpW 10X ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 GH Austrian Aerospace Protocol The RMAP protocol identifier value Oth Identifier Command Read single address reply command byte The packet type bits in the Byte command byte indicate this packet is a response packet Status The command status is returned in this field The command status can be command successful or an RMAP error code as defined in section 7 6 6 Destination The destination logical address is set to the default value FEh
155. t R W divider Selects the divided output from Example If the PLL output frequency is 200MHz set by FEEDBDIV see section 5 1 and TXDIV 01 then the transmit clock frequency will be 50MHz and the Enable clock All bits set to 1 20 16 Tx10MbitDIV Dependent on FEEDBDIV at reset FEEDBDIV 000 gt 00100 FEEDBDIV 001 gt 00101 FEEDBDIV 010 gt 00110 FEEDBDIV 011 gt 00111 set as described in section 8 1 6 FEEDBDIV 100 gt 01000 FEEDBDIV 101 gt 01001 FEEDBDIV 110 gt 01001 FEEDBDIV 111 gt 01001 Enable the transmit clock trees Setting a R W bit to zero disables the transmit clock for the corresponding SpaceWire port i e clearing bit 8 causes the transmit clock for SpaceWire port 1to be stopped Set the default 10Mbit s data rate divider R W value The Tx10MbitDIV value should be 128 SpW 1 OX Ref UoD SpW 10X ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 Austrian Aerospace 9 5 10 Destination Key Register The Destination Key register address is 265 0x0000 0109 The destination key register fields are listed in the table below Table 9 16 Destination Key Register IT Tae Description Read Write Nome Value Wmd 20h The destination key is checked when a security key Is required for RMAP configuration packets to access the router registers
156. t a glitch may occur on data and strobe see Figure 13 3 A simultaneous transition or glitch on data and strobe may occur when reset is released Figure 13 4 RST_N DOUT i H H SOUT i i i Figure 13 1 Reset Waveform RST N DOUT i i i SOUT i i i Figure 13 2 Reset Waveform with Data and Strobe Both High RST N DOUT i H H SOUT i i i V Figure 13 3 Glitches on Data or Strobe during Reset RST N DOUT i H H SOUT i i i Figure 13 4 Simultaneous Transition of Data and Strobe during Reset 148 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 Austrian Aerospace 13 3 2 Data Strobe Disable Waveform If a SpaceWire link is disabled either by configuration command or a disconnect parity escape or credit error the final bit of strobe will be extended to a 100 ns period pulse No simultaneous transitions or glitches can occur during a disable operation This operation is as expected The reset anomaly has no effect on link disconnect operation The output waveforms during link disconnect are shown in Figure 13 5 DOUT H H SOUT i i i I I Leg I I 100ns Figure 13 5 Link Disconnect Waveforms 13 3 3 Reset Anomaly Workarounds The reset anomaly will not cause any problem when operating with any SpaceWire compliant device AD1
157. t from routing switch R1 port 3 is routed towards its destination but during packet transfer the source node stalls and does not supply any more data or the end of packet b Figure 8 26 Source Node Stalled Watchdog Mode b c The packet is blocked and the packet waiting at routing switch R1 port 2 cannot be routed The watchdog timers in routing switches R1 and R2 detect the packet has become blocked and spills data from the input port and appends an error end of packet to the output port This causes the network path from routing switch R1 port 4 to routing switch R2 port 1 to be cleared and the next packet can be routed c Figure 8 27 Source Node Stalled Watchdog Mode c d The packet waiting at R1 port 2 can now be routed d Figure 8 28 Source Node Stalled Watchdog Mode d 102 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 Pran User Manual Date 7 January 2015 GH Austrian Aerospace 8 3 5 3 Waiting for an output port When a packet arrives at an input port of the SpW 10X router is has to wait to be forwarded to an output port How long the packet waits will depend on whether the router is in Blocking Allowed or Watchdog Timer mode and on what the output ports are doing Various situations are considered below In Blocking Allowed mode packets will wait indefinitely to be granted access to an output port There is one exception to this if th
158. t s the number of characters inserted in the buffer depends on the type of character end of packet or normal data and the input bit rate For example at 100 Mbit s a maximum of one received data character can be added 100 ns per data character If the parity error occurs on the last byte of the packet before the end of packet and the bit rate is above 24 Mbit s the error is not recorded by an error end of packet The receive buffer detects the last data character written to the buffer is an end of packet and therefore does not insert an error end of packet to terminate the packet The operation is shown in Figure 13 7 150 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual Di SpaceWire Router K School of Computing Issue 3 5 User Manual Date 7 January 2015 Austrian Aerospace Into SpaceWire Pot DATA 68 DATA 69 DATA 70 DATA 71 EOP Parity Error a Data into receiver with parity error on last byte Data out of Receiver DATA 68 DATA 69 DATA 70 EOP b Data with parity error is discarded End of packet is added to buffer and no EEP is inserted Figure 13 7 No error end of packet inserted after parity error 13 4 3 Parity Error Workaround There is no specific workaround for this anomaly as a similar situation can occur in any case when an error on a link does not cause an immediate parity error but one is produced in a subsequence character To avoid this causing a problem with a SpaceWire app
159. t will not be possible to configure the router unless there is another not disabled connection that can be used 8 1 5 Automatic deactivate driver mode The SpaceWire port deactivate bit can be set to cause the data and strobe outputs for the link to be deactivated when the port is inactive The deactivate mode takes effect dependent on the state of the Auto start and the Link Disabled control bits in the SpaceWire port control register see section 9 4 3 and on the Enable Start on Request bit in the router control register see section 9 5 3 When Auto start is enabled and the deactivate bit is set then the data and strobe LVDS drivers are deactivated until the interface receives a connection attempt by an external SpaceWire device The drivers are then enabled until the external device disconnects the link or the SpaceWire link control bit setup is changed When Start on Request is enabled and the deactivate bit is set the LVDS drivers are deactivated until a request is made from within the router to send data out of the SpaceWire port with deactivated output drivers i e a packet arriving at another port is addressed to be routed out of the SpaceWire port with deactivated outputs The drivers are enabled and the SpaceWire port will attempt to make a connection with the other end of the SpaceWire link When Link disable is asserted and the deactivate bit is set then the data and strobe LVDS drivers are always deactivated as the link is not in
160. tage drop between PLL loop filter LF and the PVCOBIAS pads will be converted into a current Ivco which will determine the VCO frequency It is critical to avoid any disturbance of that voltage drop at this will translate directly to jitter in the VCO frequency Iep VSSPLL Clean VDD Rvco co e PE a w E E Dip o 01 p 3 E m HEEREHREEHEE amp BANE HEHEHE men Common Ground Plane anamanna Ground Plane specific to LF VCOBias components Figure 12 1 PLL Layout Recommendations The following layout recommendations apply to the PLL circuitry 1 To minimize voltage parasitic through ground the loop filter and VCO bias components will have a separate ground plane underneath all PLL pins and components 2 This PLL ground plane shall be connected at one point to the PLLVSS pad 3 To minimize other electromagnetic crosstalk effects SMD components should be used and placed as close as possible to the corresponding pads 4 The PLL has been designed to exhibit low sensitivity to power supply variation VDDPLL can be externally connected to the core array power supply but the cleaner that power supply the better the PLL performances is in terms of jitter Separate 100 nF and 1 uF decoupling capacitors shall be provided for VDDPLL 144 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual n SpaceWire Router K School of Computing Issue 3 5 omg User Manual Date 7 January 2015 GH Austrian Aerospace 13 A
161. te Value This bit is set to one when any of the error bits are set 1 Packet The packet address error bit is set when a packet is received with an incorrect address packet address error is also generated when an empty packet is input to the external port Address Error Output port timeout error The output timeout error bit is set when the output port has become blocked for a period of time Input Buffer The external port input buffer is full Full 5 The external output port buffer is empty Note The output buffer writes data to the external device connected to the external port Output The external output port buffer is full Buffer Full Note The Error status bits are cleared by writing to the Error Active register see section 9 5 4 im a 3 Input Buffer The external port input buffer is empty EMP Note The input buffer writes data to the SpaceWire router i IT 9 5 ROUTER CONTROL STATUS REGISTERS The router control status registers are described below 9 5 1 Network Discovery Register The network discovery register address is 256 0x0000 0100 The network discovery register allows a network manager to determine the layout of the network by reading the contents of the register Its fields are shown in Figure 9 4 and described in Table 9 8 117 SpW 1 OX Ref UoD SpW 10X ASTRIUM i UserManual n SpaceWire Router K School of Computing Issue 3 5 User Manual Date 7 January 2015 Austri
162. te of a SpaceWire port is to be changed frequently it should be done using the TXRATE divider Note that the SoW 10X device will not allow a TXDIV and TXRATE to be set to give a transmit data rate below 2 Mbits s 86 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 Austrian Aerospace 8 2 GLOBAL SPACEWIRE LINK CONTROL The following modes are global to all SoaceWire links The modes can be set in the SpaceWire router control register See section 9 5 3 8 2 1 Start on request mode The Start on Request mode is enabled by setting the CFG_START_ON_ REQ bit in the router control register The input signal POR_START_ON_REQ_N determines the power on or reset state of the CFG START ON REQ bit When a SpaceWire packet is received which is to be routed out of a SpaceWire port that is not running it would normally be discarded If the Start on Request mode is enabled instead of discarding the packet the SpaceWire port will attempt to make a connection with the other end of the link If a connection can be made then the packet is forwarded on towards its destination This is illustrated in Figure 8 4 This mode allows the SpaceWire ports to be started automatically when there is data to send This can be used together with output deactivate to save power 1 R1 2 1 R2 2 Auto Start default mode and Start on Request enabled in both routers R1
163. ter The least significant 8 bits of the general purpose register are available on the multiplexed status pins see section 6 3 9 5 8 Time Code Enable Register The time code enable register address is 263 0x0000 0107 The time code enable register enables the passing of time codes out of individual ports on the router Bits 1 to 8 of the time code enable register are used to enable time code distribution through SpaceWire ports 1 to 8 respectively If one of these bits is set to 1 then the corresponding SpaceWire port is enabled for time code distribution and will send out a time code when one is received by the router For example if bit 1 in the enable register is set to 1 time codes are passed to SpaceWire port 1 whereas if bit 1 is set to 0 time codes are not passed to SpaceWire port 1 Bit 9 of the time code enable register controls time code distribution to the external time code interface in a similar manner Note that there is only one external time code interface although there are two External ports The fields of the time code enable register are shown in Figure 9 9 and described in Table 9 14 31 13 12 11 10 9 8 1 0 Reserved Time code enable External time code interface enable Not used Time code flag mode Not used Figure 9 9 Time Code Enable Register Fields 125 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015
164. than the internal time register of the router see SpaceWire standard AD1 Note that only one router or node in a SpaceWire network should normally operate as a time master generating time codes see SpaceWire standard AD1 EXT TICK OUT Figure 6 4 Time Code Output Interface When a valid time code is received by the router the value of this time code flags plus time value will be placed on the EXT_TIME_OUT outputs and the EXT_TICK_OUT signal will be set to zero The EXT TICK OUT signal is set to one a short time later once the EXT TIME OUT outputs have stabilised to indicate that these outputs are valid They then remain valid until the next time code is received and the EXT_TICK_OUT signal will be set to zero TIME CTR AST So TIME _CTR Count Figure 6 5 Time code reset interface When a rising edge is detected on TIME_CTR_RST then the time code register is reset to zero 6 3 STATUS INTERFACE OPERATION The STAT_MUX_ADDR signal determines the output status on STAT_MUX_OUT as shown in Figure 6 6 and in Table 6 1 l R R Figure 6 6 Status Multiplexer output interface When STAT_MUX_ADDR is stable STAT_MUX_OUT is output from after each clock edge 51 ASTRIUM K School of Computing DUNDEI Austrian Aerospace SpW 1 OX Ref UoD_SpW 10X_ UserManual SpaceWire Router Issue 3 5 User Manual Date 7 January 2015 Table 6 1 Multiplexed St
165. the router unless there is another not disabled connection that can be used WARNING Blocking Allowed mode is not recommended and should be used with caution When Blocking Allowed mode is used Watchdog timers disabled then it is important that provision is made for a network manager to detect blocking situations and to reset the nodes or routers causing the problem 146 SpW 1 OX Ref UoD SpW 10X ASTRIUM i UserManual SpaceWire Router School of Computing Issue 3 5 User Manual Date 7 January 2015 WARNING Packets can timeout and be spilled in a SpaceWire network without the destination receiving any notification of this Packets with errors e g parity error can arrive at a destination terminated by an EEP In a very special case it is also possible to receive an error free packet terminated by an EEP It is important that the destination node is able to handle these cases WARNING Care must be taken when setting a the routing tables to avoid a possible infinite loop For example if there is a SpaceWire link made between two ports of a single router and a logical address routes a packet out of one of these ports then that packet will arrive back at the router and be routed back out of the port again Depending on the size of the packet it may block because it cannot get access to the output port the second time around as the tail of the packet is still being fed to the output port In this case the blockage will cause a tim
166. to save power The duty cycle column gives the duty cycle of the 5 MHz start up data strobe clock If this is not 1 1 then one data bit period will be shorter than the next data bit period This can reduce skew tolerance and hence the maximum operating speed of the SpaceWire ports Taking a limit of 10 of the bit period allows the use of 10Mbit s clocks with a duty cycle of 9 11 as the worst case The corresponding setting for the TX10MbitDIV field in the transmit clock register see section 9 5 9 is given in the third column Only the rows with valid Initialisation data rate and duty cycle should be used The following steps should be followed to set a particular transmit data rate using values from Table 8 1 1 Select the required SpaceWire transmit data rate from Table 8 1 Only values with a white background in the table should be used Values with a red shaded background should not be used 2 Set the FEEDBDIV pins on the SpW 10X device to the corresponding value in Table 8 1 3 Set the TXDIV and TX10MbitDIV fields in the transmit clock control register see section 9 5 9 using values from Table 8 1 Normally this would be done once after reset d Set the required transmit data rate of each link individually using the Transmit Rate TXRATE field of the SpaceWire port control registers see 9 4 3 The values to use for these fields should be taken from Table 8 1 corresponding to one of the white background entries If the transmit data ra
167. uted to output port 5 At stage three the packet from input port 1 has been forwarded and the packet from input port 2 is selected by the router to be routed through output port 5 Input port two is selected before input port 3 as it is the next input port to be considered by the routing control logic after input port 1 At stage four p the complete packet has been transferred from input port 2 Now input port 3 is able to transfer its packet to output port 5 Two packets waiting to use port 5 Packet from port 1 is selected Previous port which accessed port 5 3 Packet arrives on port 2 Packet from port 1 completes Packet from port 2 completes Packet from port 2 is selected Packet from port 3 is selected Packet from port 3 waits Figure 8 7 Arbitration of three packets with matching priority 90 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 Pran User Manual Date 7 January 2015 GH Austrian Aerospace 8 3 2 3 Arbitration of packets with different priority 1 In the Figure 8 8 arbitration of packets with different priority is illustrated Only router ports 1 5 are shown for clarity At stage one input ports 1 and 3 have packets with logical addresses 80 and 52 respectively which are both to be routed to output port 5 Logical address 80 is high priority and 52 low priority At stage two the previous input port selected by output port 5 was input port 2 but since
168. utput ports in the group that are not ready will attempt to make a connection The packet will be routed to the output port in the group that is ready first 8 3 4 Loop back with Self Addressing The Enable Self Addressing bit in the router control register determines if the router is to support loop back connections Loop back connections can be useful for debugging or ping operations where a packet is bounced of the router and returned to the source If the Enable Self Addressing bit is clear 95 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 Austrian Aerospace then a packet that that is addressed to go out of the same port that it arrived on will be discarded and a packet address error recorded Command reply packets which are returned through the same port they arrived on are not affected by the value of the Enable Self Addressing bit Figure 8 13 shows the Enable Self Addressing mode when enabled and when disabled Packet arrives at port 1 with address 1 Address self mode is enabled Packet arrives at port 1 with address 1 Packet is discarded by the routing control logic Address self mode is disabled Figure 8 13 Packet Self Addressing mode 96 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 run User Manual Date 7 January 2015 GH Austr
169. value of GAR table entry Correction to support email address Data after parity error anomaly Steve Parkes added 30 April 2008 Issue 3 3 11 July Issue 3 4 Detailed timing information Gerald Kempf added DC characteristics updated 11 January 2015 Correction to Table 5 2 Chris McClements SOUT Minus 4 pin location Issue 3 5 Correction to Table 9 10 ASTRIUM K School of Computing DUNDEI GH Austrian Aerospace SpW 1 OX Ref UoD_SpW 10X_ i UserManual SpaceWire Router Issue 3 5 User Manual Date 7 January 2015 POR_SEL_TIMEOUT_N reset value polarity Correction to Table 10 1 TBC removed ASTRIUM K School of Computing DUNDEI GH Austrian Aerospace SpW 10X SpaceWire Router User Manual Ref UoD SpW 10X UserManual Issue 3 5 Date 7 January 2015 CONTENTS EHNEN Eegen 5 ES Or EG RS LE 11 U EISTOF TABLES E A E 13 Te UNTO DUC TON EE NN 15 1 1 TERMS ACRONYMS AND ABBREVIAT TIONS nannnnnnnnnennnennesrrnnsnrrsrrersrrrnrrrrsrrrrsrrrsrrresrrrnee 15 2 reel CH KE 16 2 VER PP IG nei LE 18 2 1 STAND ALONE ROUTER emsonnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnennnnennnnennnnennnnennnnennnnennnnennnnennnsennunennnnennnnennnne 18 22 NODEINTERFACE re a 19 293 EMBEDDED REN 19 2 4 EXPANDING THE NUMBER OF ROUTER BORIS 20 3 FUNCTHONAL OVERVIEW irass E E 23 ol ENEE 24 e EATE RNAC POR KE 24 3 3 CONFIGURATION PORT E 25 3 4 ROUTING TABLE Lee 25 3 5 ROUTING CONTROL LOGIC AND
170. ve routing set up so that packets with that address can use output ports 4 5 or6 In Figure 8 11 output ports 4 and 5 are busy and port 6 is not being used When a packet with logical address 76 arrives at input port 1 it is routed immediately to output port 6 94 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual SpaceWire Router K School of Computing Issue 3 5 User Manual Date 7 January 2015 Austrian Aerospace Address 76 Routing table entr Header Deletion disabled Port 4 Group adaptive routing packet with address 76 arrives at port 1 Routing logic assigns ports 6 to packet at port 1 Ports 4 and 5 are busy routing packet data from ports 2 and 3 Figure 8 11 Group adaptive routing when other ports busy 8 3 3 3 Group adaptive routing when ports not ready A similar arrangement to that of section 8 3 3 2 is shown in Figure 8 12 In this scenario two of the output ports which address 76 can use are not ready for use i e the links are not running The packet is routed to output port 6 since it is running and not being used to route another packet Address 76 Routing table entr Header Deletion disabled Port 4 Port 5 Port 6 Group adaptive routing packet with address 76 arrives at port 1 Routing logic assigns ports 6 to packet at port 1 Ports 4 and 5 are not ready to accept packet data Figure 8 12 Group adaptive routing when ports not ready Note if the Start on Request mode is enabled the o
171. work on LVDS input Current can now flow from the 3 3 volt supply to ground When the bias resistors for 10mV noise margin are used the total current flowing out of the LVDS outputs is around 200 UA as illustrated in Figure 8 3 WARNING The deactivate mode see also section 9 4 3 does not tri state the LVDS outputs The LVDS outputs are cold sparing and when disabled both outputs in an LVDS differential pair are pulled up to 3 3V and have an impedance of the order of 1 kohm Since they are differential outputs and are both are at the same voltage no current will flow If however external noise bias resistors are being used then a small current around 200 uA 0 7 mW power can flow This is substantially less than the normal operating current of LVDS outputs and hence saves power 8 1 6 Setting the SpaceWire port transmit data rate The SpaceWire port transmit data rate is dependent on the input signal FEEDBDIV See section 5 1 the PLL output clock divider value TXDIV See section 9 5 9 and the data rate divider value TXRATE in each SpaceWire link control register See section 9 4 3 The resultant data rate is determined by the function ee 1 100MHz 20MHz FEEDBDIV d DataRate D TXRATE 1 The output of the PLL is also used to provide the 10 Mbits s transmit clock used during SpaceWire link initialisation 84 SpW 1 OX Ref UoD_SpW 10X_ ASTRIUM i UserManual Wi SpaceWire Router i K School of Computing Issue

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