PBMCUSLK
Contents
1. on BER BREO PBMCUSLK IN 28 E L 5 2355 AXM 392 REV B ZC o ssa A xiom m g vO a BE 02 Z ww axman com A 2 3 k 3 S Ouere 2 28 2 So D O O aNo a ES dz S s o O O AIddns 000 O Oleova H S OD O of ova N D O O 3ulm I N O 00 LNa99n2 a y o O OO Der e SIS o oO O O1739w110A S O Ou ne A OO Nim W O O 1no INNA lt a gt Ono 8 THO 224 u2 et aHo SZ EL A dE Eau 2 O O 9399181 SCH O O 3SN3SIV 2 2 2 OO 3 SZ oo Res E oc KI VH Ca a 2 0 olaaa o a p S o e ol ECG D a 2 7 S oo oo a L R IONOS BALI Dien 6917 VA 1NO 017 Di 308nos 919 17 S Dien 199 a 1NO Lo 3 D 3 09239 Ed ADN 5 5 M z a 6 2 m 3 ver 2 Ian OY U E l g8 f j l a 3 pes 0000 0000 gt ku E DH 5 31 225 la pe AAA H KEYPAD eS G era aL Z lt UE a OO BEER 2 i RS RI 12 ooje d Be E 2 TL H GL Tas ES C RI i 3 HI e G g ou Op 28 esos H rm dei S a Ee 7 2 3 2 a dA C26 C25 C24 FERES a ka ka cs al Fi g Q g von er l UI e Sl A K S ER KC Le lo O O s E zs o S d III P REES H S ay Se asgs sai L392 O SOT B 2 5 Ey gra 8 Coen 3 o o nm E g H E E c P G S El g 2 L J rea E S iren Freescale Semiconductor How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not List2. 6 Female DB9 connector that interfaces to the DCE serial port via an TXD 2 RS232 transceiver It provides simple 2 wire asynchronous serial 7 RTS communications without flow control A straight through serial cable may RXD 3 be used to a DTE device such a PC 8 CTS 4 S Pins 1 4 6 and 9 are routed to the User I O Signal Breakout connector GND Sl located adjacent to the breadboard RS 232 The PBMCUSLK also provides a single RS 232 communications port configured as a DCE device An RS 232 transceiver provides RS 232 signal level to TTL CMOS logic level translation services The COM EN option header illustrated in figure 13 allows data and handshake signals to be connected directly to the transceiver The RS 232 translator operates at either 3 3V or 5V Figure 13 COM_EN Option Header TXD MN The illustration to the left shows all signals enabled RXD O Remove shunts to isolate each signal individually RTS IR CTS IR The COM_SEL option header shown in figure 14 configures the transceiver to operate in MONO8 or RS 232 modes 22 Freescale Semiconductor Figure 13 COM SEL Option Header COM_SEL DESCRIPTION e S Z S Selects MONO8 communications COM_SEL e S gt Z S Selects RS 232 communications Translated RS 232 signals TX and RX are available to the user at the signal breakout header labeled COMM TXD and RXD located adjacent to the breadboard
3. 7 8 DBI R W Read Write pin set to 0 volts Read only DB2 9 10 DB3 EN LCD enable input 1 LCD enable LCD D4 11 12 LCD D5 CONTRAST LCD contrast input LCD D6 13 14 LCD D7 RS Register Select 0 LCD Command 1 LCD Data Connector J8 illustrated in figure 6 allows the use of alternate displays up to 20 char x 4 lines This header is not installed in default configurations Connector J8 is a mirror image of the LCD_PORT connector Figure 6 J8 Aux LCD Connector 5V 2 1 GND SPI data bit definitions to LCD Port RS 4 3 CONSTRAST LCD_D 7 4 LCD data bits D 3 0 EN 6 5 R w DB 3 0 Unused 10K ohm pull downs installed DB1 8 7 DBO R W Read Write pin set to 0 volts Read only DB3 10 9 DB2 EN LCD enable input 1 LCD enable LCD D5 12 11 LCD D4 CONTRAST LCD contrast input LCD D7 14 13 LCD D6 RS Register Select 0 LCD Command 1 LCD Data Connector J8 illustrated in figure 7 allows the use of alternate displays up to 20 char x 4 lines This header is not installed in default configurations Figure 7 J9 Aux LCD Connector GND 1 SPI data bit definitions to LCD Port SV M2 LCD_D 7 4 LCD data bits D 3 0 CONTRAST 3 DB 3 0 Unused 10K ohm pull downs installed RS 4 R W Read Write pin set to 0 volts Read only R w 5 EN LCD enable i
4. 21 22 23 24 25 26 O I gon 9 qRuIue1301g 2 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 45 46 47 48 49 50 51 52 53 54 55 56 ad 58 59 60 LATCH GLB_RESET ADDRESS 0 ADDRESS 1 ADDRESS 2 ADDRESS 3 VDD VDD DO 0 DO 1 DO 2 DO 3 DO 4 DO 5 DO 6 DO 7 GND DIO DI 1 DI2 DI 3 DI 4 DI 5 DI6 DI7 15 V 15V O T IRIS 27 TROUBLESHOOTING TIPS The following is a list of useful problem resolution tips to try before contacting Technical Support for assistance If the PBMCUSLK still fails to operate properly contact Axiom Manufacturing at Support axman com LED S on the PBMCUSLK dont light Ensure LED_EN jumper is installed Make sure JP1 PWR_SEL is set to source power from the appropriate source Verify input power is available If the transformer is connected to a power strip make sure the power strip is turned on Ensure 5VDC between pins VR1 2 and VR1 3 Measure 3 3VDC between pins VR2 2 and VR2 3 LED S on the MCU Development Module don t light Make sure the module is properly connected to the PBMCUSLK 2 Make sure a power cord is not connected to the module Make sure the MODULE POWER option jumpers are installed Make sure the PWR_SEL option header on the Development Module is setup properly No Prompt at the AxIDE Term
5. 24 AUX_OSC MONO8 TXD RXD RTS CTS DSUB 1 DSUB 2 DSUB 3 DSUB 4 DSUB 6 DSUB 7 DSUB 8 DSUB 9 KEYPAD 1 KEYPAD 2 KEYPAD 3 KEYPAD 4 KEYPAD 5 KEYPAD 6 KEYPAD 7 KEYPAD 8 VDD sv GND GND BNC BNC BANANA B BANANA A Cl EI LA 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 41 42 43 44 46 48 50 52 54 56 58 60 NOTE Signal DSUB 9 is connected directly to GND Freescale Semiconductor MCU_PORT A unique feature of the PBMCUSLK is the ability to interface directly with a line of MCU Development Boards from Axiom Manufacturing directly into the MCU_PORT or connect through a ribbon cable The signals originating at the MCU PORT connector are routed to two sets of dual row socket headers located at both ends of the breadboard All MCU_PORT signals are available at both signal breakout locations These development boards either plug This allows the user to easily prototype circuits at either end of the breadboard placement at these breakout locations is dependent on signal orientation at the MCU_PORT See the user manual for the specific MCU module for signal breakout Figure 16 MCU_PORT Signal Breakout J5 J6 J7 J5 io on IHA Nn WO NI Mi Go Re So M13 13 14 M15 15 16 M17
6. NI EL VIS Interface The NI ELVIS interface consists of a PCI style connector located at J1 and 3 dual row socket headers Connector J1 connects the PBMCUSLK directly to the NI ELVIS workstation All NI ELVIS signals are routed to a signal breakout connector conveniently located adjacent to the breadboard Refer to the NI ELVIS User Guide for details on the functioning of the NI ELVIS platform In the figure below all B pins are on the top layer of the project board and all A pins are on the bottom layer of the project board Figure 17 Edge Connector J1 15 V 15 V 5V_In 5V_In 5V_In GND DO 6 DO 4 DO 2 DOO GND PCI KEYWAY PCI KEYWAY DI6 DI 4 DI 2 DIO GND GND GND GND CONN_5V GND N C ADDRESS 2 ADDRESS 0 LATCH WR_ENABLE Proto Board Present PFI 5 PFI 2 26 Al A2 A3 A4 AS A6 A7 AN A9 Bl B2 B3 B4 B5 B6 B7 B8 B9 A10 B10 All Al2 A13 Al4 Al5 Al6 Al7 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 15 V 15 V GND GND GND GND DO7 DO 2 DO 3 DO 1 GND PCI KEYWAY PCI KEYWAY DI7 DI 5 DI 3 DI 1 GND GND GND GND GND GND ADDRESS 3 ADDRESS 1 GLB_RESET RD_ENABLE CONN_5V PFI 6 PFI 7 RESERVED SCAN CLK TRIGGER CTR1_GATE CTRO_SOURCE CRO_OUT GND VOLTAGE HI AIGND ACH7
7. Translated handshaking signals RTS and CTS are also available The user will need to configure hand shaking as required by the communications application used To ease application development communications signals TX and RX are connected the MCU_PORT connect at pins 5 amp 7 respectively This simplifies cable routing when using the PBMCUSLK and an attached module The MCU_COM option header is used to route these signals from the on board transceiver to the MCU_PORT headers To use the signals as general purpose I O simply remove the shunts at the MCU_COM option header as described in figure 15 Figure 14 MCU_COM Option Header RI TxD Enable RS 232 signals to e TXD Disable RS 232 signals to RXD MCU_ PORT e RXD MCU_PORT MCU_COM MCU_COM MONO08 MONO8 communications are also supported through the COM connector supporting serial monitor operation on HCO8 modules The COM_SEL shown in figure 14 selects between RS 232 operation and MONOS operation A single wire MONO8 interface is available to the user at the signal breakout header labeled COMM MONOS located adjacent to the breadboard A zener diode and resistor combination provides the high voltage VTST necessary to force MONO8 monitor mode This voltage is fixed at 8 2V and may be excessive for 3 3V HCO8 MCU s It is the users responsibility to reduce the VTST voltage level if necessary VTST is available when the board is powered either f
8. 17 18 M19 19 20 M21 21 22 M23 23 24 M25 25 26 M27 27 28 M29 29 30 M31 31 32 M33 33 34 M35 35 36 M37 37 38 M39 39 40 M41 41 42 M43 43 44 M45 45 46 M47 47 48 M49 49 50 M51 51 52 M53 53 54 M55 55 56 M57 57 58 M59 59 60 M2 M6 M8 M10 M12 M14 M16 M18 M20 M22 M24 M26 M28 M30 M32 M34 M36 M38 M40 M42 M44 M46 M48 M50 M52 M54 M56 M58 M60 Freescale Semiconductor J6 Ol Gl AJIN S 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 M2 M6 M8 M10 M12 M14 M16 M18 M20 M22 M24 M26 M28 M30 M32 M34 M36 M38 M40 M42 M44 M46 M48 M50 M52 M54 M56 M58 M60 J7 Ol Gl AJIN MO l AV NM GW re S 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 M2 M6 M8 M10 M12 M14 M16 M18 M20 M22 M24 M26 M28 M30 M32 M34 M36 M38 M40 M42 M44 M46 M48 M50 M52 M54 M56 M58 M60 Signal 25
9. Buttons PB_EN MCU_PORT 36 0 1 LED S LED EN MCU_PORT 34 0 1 POT POT EN MCU_PORT 32 1 0 NOTE Enable signal levels are not the same for all Feature Groups To prevent signal corruption each enable signal may be isolated from the MCU_PORT An option header at UFEA illustrated in table 9 allows each enable signal group to be isolated individually This allows the GPIO port signal applied to the Connected Feature Enable to be used for other purposes Table 9 UFEA Option Header SHUNT UFEA ON OFF BZ 1 2 ENABLE DISABLE PB 3 4 ENABLE DISABLE LED 5 6 ENABLE DISABLE POT 7 8 ENABLE DISABLE For project boards labeled MCU Project Board 2 AXM 0368 Rev C this jumper is labeled JP10 Freescale Semiconductor 21 COM Port The PBMCUSLK is both MONO8 and RS 232 serial communications ready Many of these user features are by default enabled but can be disconnected through jumper settings This section describes each of the features in detail and required jumper configurations DB9 Connector A single DB9 connector shown in figure 12 is provided to support communications applications development on the PBMCUSLK Signals from the DB9 connector are routed directly to the breakout connector labeled COMM DSUB 1 9 located adjacent to the breadboard This allows implementation of communication protocols not supported on the PBMCUSLK Figure 12 COM Port Connector
10. Exercise care when configuring power input and output selections to prevent damage to the project board or connected circuitry Input Sources The PBMCUSLK provides the user 4 discrete working voltage levels 5V 3 3V 15V and 15V The 5V and the 15V rails have multiple input sources while the 3 3V rail is derived from the 5V rail in all configurations Option headers JP1 P_SELA JP2 PSEL_B and JP3 VDD_SEL configure power routing on the project board See the Input Selection section below for details on setting up power configuration for the project board The 5V rail is driven from one of three input sources the barrel connector VIN the integrated USB BDM or the NI ELVIS workstation J1 The barrel connector input at VIN accepts a 2 1mm center positive barrel plug allowing power to be supplied by a transformer or desktop power supply Input voltage on VIN must be kept between 8V and 12V for proper operation Typical input is 9V Although VR1 will accept inputs to 20V increasing the input voltage will increase the voltage drop across the part This may lead to excessive temperatures causing the part to shut down The 5V rail is derived from the on board voltage regulator at VR1 VR1 supplies a maximum of 1A of current to the project board The regulator features over current and over temperature protection The regulator will automatically shut down if current or temperature exceeds rated specifications The integrated
11. MONDO ii ita ta 23 SIGNAL BREAKOU E 24 USER il IR E E E E e 24 MCU PORT cnt A A SA A A A ans eats 25 IER treier ideore ee ee etere eere ee e ere ere erei eet Ee 26 SIGNALBREAKOU EE 27 TROUBLESHOOTING UE 28 APPENDIX d aerarii ar paaa ae aeaaaee ia ae aa aaia aa eaaa aiaa aaa aa aria aae aandaa Vaia 29 FIGURES Figure Ie input Power Select E 10 Figure 2 VDD SEL Option Header iii A ie 11 Figure 3 MOD PWR Option Header sss sese 12 Figure 4 USB SPEED Option Header 13 Figure 57 LCD PORT JlB oscar 15 Figure 6 J8 Ee RRC EE 15 Figure 7 E Ee Reie EE 15 Figure 8 Contrast Select TE 16 Figure 9995 SELLO Ie AGE EEN 16 Figure 10 LCD EN Option Header ate stelteatctate e 17 Figure 11 Keypad Connector E 18 Figure 12 COM Port Connector 22 Figure 14 COM SEL Option Header cun ad 23 Figure 15 MCU COM Option Oe Ei ER Figure 16 USER I O Signal Breakout J10 JT 24 Figure 17 MCU_PORT Signal Breakout J5 JJ 25 Figure 18 Edge Connector I EE 26 Figure 19 NI ELVIS Signal Breakout J2 J3 Jd 27 Freescale Semiconductor 3 TABLES Table e DI s 21 Tani TTT 9 Table 2 15V EN Option Heads 11 Table 3 AMPL Option AA ir A A A A AA A ADA AL 17 Table 4 LED EN Option Headers escitas A de geg 18 Table 5 POT esl Tea 20 Table 6 PB Switch Connections e nro nn nn nn r nn rn rn nro nr nn erena nre naerenn 20 Table LED Connections its do do ds pda dd do dde o de o o do e de 20 Table 8 User Feature Enable nro rtnn rren nn
12. hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such
13. nnrnnnnnnnnnrnncnnnnns 21 Table Sc UFEA Option Header 2792 97202979 2R 2029222020202722 020 a 21 REVISION Date Rev Comments December 5 2006 0 Initial Release July 17 2007 1 Added LCD information part no and more info URLs Freescale Semiconductor CAUTIONARY NOTES Electrostatic Discharge ESD prevention measures should be used when handling this product ESD damage is not a warranty repair item Axiom Manufacturing does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under patent rights or the rights of others 3 EMC Information on the PBMCUSLK 1 This product as shipped from the factory with associated power supplies and cables has been verified to meet with requirements of CE and the FCC as a CLASS A product 2 This product is designed and intended for use as a development platform for hardware or software in an educational setting or a professional laboratory 3 In a domestic environment this product may cause radio interference In this case the user is required to take adequate prevention measures 4 Attaching additional wiring to this product or modifying the products operation from the factory default as shipped may effect its performance and cause interference with nearby electronic equipment If such interference is detected suitable mitigating measures should be taken TERMINOLOGY This prototypi
14. prevent signal corruption when using the SPI signals as GPIO the user should idle the SPI circuitry by removing the SS jumper For project boards labeled MCU Project Board 2 AXM 0368 Rev C this jumper is labeled SS Freescale Semiconductor LCD Enable The LCD EN option header illustrated in figure 10 allows module SPI signals to be used as general purpose lO if needed To use the SPI signals as general purpose UO simply remove the shunts at this option header Figure 10 LCD EN Option Header LCD_EN LCD_EN MH MOSI SPI signals connected to LCD e e MOSI SPI signals available as GPIO HA Miso Port e e MISO Mm SCK e e SCK Oscillator Socket The PBMCUSLK provides a socket for an optional clock oscillator The socket is configured to accept either 8 pin or 14 pin canned clock oscillators An AMPL option jumper described in table 3 allows the use of 5V oscillators to drive 3 3V circuits Removing the option jumper routes the clock output through a simple voltage divider thereby reducing the output amplitude Installing the option jumper allows a 5V peak clock output This output is routed to the signal breakout header located adjacent to the breadboard Table 3 AMPL Option Header Shunt Effect ON Oscillator Output at Full Amplitude 5Vpp OFF Oscillator Output at Reduced Amplitude 3 3 Y pp Switches The PBMCUSLK provides two types of
15. switches for use as input devices Eight normally open push button switches voltage level while in the inactive state PUSHBUTTON SWITCHES Each push button switch is configured for active low operation When pressed closed the associated signal line is pulled to GND through a 1 kQ current limit resistor A 10k ohm resistor pulls each signal line to VDD when the switch is released open Each push button switch output is routed to the signal breakout header labeled USER UO PB 1 7 located adjacent to the breadboard Four push button switches are connected directly to the MCU_PORT connector see Connected Features section below for details Not applicable for project boards labeled MCU Project Board Y For project boards labeled MCU Project Board 2 AXM 0368 Rev C this jumper is labeled OSC OPT Freescale Semiconductor 17 DIP SWITCHES Each DIP switch is configured for active high operation When ON closed each switch leg is individually pulled to VDD through a 100 Q series current limit resistor A 10k ohm resistor pulls each signal line to GND when the switch is OFF open Each DIP switch output is routed to the signal breakout header labeled USER I O SW 1 7 located adjacent to the breadboard LED s The PBMCUSLK provides 8 green LED s for use as output indicators Each LED is configured for active high operation Each LED is individually driven by an ACT buffer allowing either 5V or 3 3V inpu
16. the latest version of Freescale CodeWarrior software tools and how to create build and debug a simple application NOTE Install the CodeWarrior Development Studio tools and all applicable patches before attempting to connect the PBMCUSLK to a host PC OPERATION The PBMCUSLK allows quick and easy prototype of electronic circuits with or without MCU support A variety of commonly used circuits are pre installed configurable and ready for use Dual row header sockets placed around the prototyping area provide convenient access to all Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners Freescale Semiconductor Inc 2006 Document Number PBMCUSLKUG REV 1 k so freescale University Program on board features Connections between these signals and the breadboard are made using solid 22ga jumper wire connected to the proper socket header location A package of jumper wires is included with the project board The sections below describe in detail the functionality of the PBMCUSLK POWER The PBMCUSLK may be used as a stand alone prototyping platform or in conjunction with the NI ELVIS platform The project board will accept power input from the included wall plug transformer or from the NI ELVIS workstation The project board may also be powered from the integrated USB BDM CAUTION
17. to lighten or darken the contrast using the project board potentiometer The LCD setup does not support current cursor position read back LCD Port Connectors The LCD control and data signals can be directly connected to the MCU_PORT I O headers The signal arrangement is designed to coincide with the SPI port of Freescale line of plug in application modules designed by Axiom Manufacturing To provide maximum flexibility the select signal SS has been connected to both a dedicated SS output and to a GPIO signal on the MCU application module An option header at SS selects the select signal source An option header at LCD_EN allows the user to isolate the LCD module from the MCU_PORT signal lines To prevent signal corruption when using the SPI signals as general purpose UC the user should remove the shunts on LCD EN and SS option headers LCD is not included with older MCUSLK project boards which can be identified with the labeling MCU Project Board on the board The connections are available on this series of boards However to use one must separately purchase and LCD and connect it to the project board 14 Freescale Semiconductor Figure 5 depicts the pin out and signals for the LCD PORT connector Figure 5 LCD PORT J13 GND 1 2 VDD SPI data bit definitions to LCD Port CONTRAST 3 4 RS LCD_D 7 4 LCD data bits D 3 0 R W 5 6 EN DB 3 0 Unused 10K ohm pull downs installed DBO
18. unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners Freescale Semiconductor Inc 2006 All rights reserved E gt freescale semiconductor
19. ACH6 ACH5 ACH4 AIGND ACH3 ACH2 ACHI ACHO AISENSE PCI KEYWAY PCI KEYWAY N C SYNC OUT FUNC OUT GND N C CURRENT LO 3 WIRE N C DACO 2 GND SUPPLY A32 B32 A33 B33 A34 B34 A35 B35 A36 B36 A37 B37 A38 B38 A39 B39 A40 B40 A41 B41 A42 B42 A43 B43 A44 B44 A45 B45 A46 B46 A47 B47 A48 B48 A49 B49 A50 B50 A51 B51 A52 B52 A53 B53 A54 B54 A55 B55 A56 B56 A57 B57 A58 B58 A59 B59 A60 B60 A61 B61 A62 B62 PFI 1 CTR SOURCE CTR OUT CTRO GATE FREQ OUT GND VOLTAGE LO AIGND ACHT ACH6 ACHS ACH4 AIGND ACH3 ACH2 ACH1 ACHO N C PCI KEYWAY PCI KEYWAY N C FM IN AMIN CONN SN GND N C CURRENT HI N C DAC 1 GND SUPPLY Freescale Semiconductor Signal Breakout The following chart shows the signal breakout for the NI ELVIS signals These connectors are arranged from left to right above the breadboard All signals are grouped by function and arranged to provide convenient access to the breadboard Each signal group is labeled to ease signal identification and location To ease prototyping each signal is routed to two socket locations This allows the user to easily route each to signal to multiple locations if desired Th
20. Freescale Semiconductor PBMCUSLKUG User Guide Rev 1 7 2007 MCU PROJECT BOARD STUDENT LEARNING KIT PBMCUSLK Prototyping Board with Microcontroller Interface Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners Freescale Semiconductor Inc 2006 Document Number PBMCUSLKUG REV 1 A N Ke freescale University Program CONTENTS CAUTIONARY NOTES ai ade 5 TERMINOLOGY siii a A ennnen nnna 5 FEATURES lt a Rai 6 REFERENCES iia a A A An a T 7 GETTING STARTED coincida 7 OPERATION cnica cacas 7 POWER me ma ee AS E EAS AT IEA E ATI 8 INPUT Ee 8 INPUT SELECTION di is 10 VIED e IOI ita EE 10 415V POW EEE TTT 11 UE ee eegen A a 12 INTEGRATED USB OR 12 A egene eenegen eegener 13 TEE 13 USER O a dt A A E turin belnes Sith chet EAERI 14 PODPO EE UALS AMUN SN SOUR TE NN 14 ES RR NENT EE 14 WG COM e S EE A EEE A TA Add Oe load 16 ECOS ent da nd 16 TSC CB a Des sita std 17 OSCI ATOR SOG RE 17 Eeer 17 PUSHBUTTON SWITCHES ee 17 KEE lina 18 EE 18 TED insite EEE eit theses Gta se SA toca isnt EE EE E EE E E EET 18 POTENTIOMETER EE 19 BAN ZINA E Te EE 19 BNGIACIS EE 19 CONNECTED FEATURES A he a LA hale hs sd hated 19 POT A EE EE 20 PUSH BUOT TON lR Re lt T 20 LEDS o td a da abs 20 BOZZE R 0 EE 21 CONNECTED FEATURE ENABLE 21 COMPORTA RRL LO E E O DeL 22 2 Freescale Semiconductor ee EE 22
21. T 34 allowing the user enable or disable this feature under MCU control An option header at UFEA isolates this enable signal allowing the user to apply the GPIO signal for other uses Table 7 LED Connections FEATURE CONNECTION LED1 VALUE MCU_PORT 33 LED2 VALUE MCU_PORT 35 LED3 VALUE MCU_PORT 37 LED4 VALUE MCU_PORT 39 LED ENABLE MCU_PORT 34 OPTION JUMPER UFEA 3 LED 20 Freescale Semiconductor Buzzer The PBMCUSLK features an external drive buzzer for audible applications The buzzer is connected to a TIMER PWM port on all current MCU modules The buzzer is connected directly to the MCU PORT connector at MCU_PORT 13 and does not require an enable signal similar to the other Connected Features The buzzer is connected to the MCU_PORT through an option header at UFEA 2 PB Connected Feature Enable Each Connected Feature is enabled by applying the appropriate signal level to the enable line for that feature set Each connected feature group may be enabled or disabled independently of the other groups NOTE Enable signal logic levels are not the same for all feature groups Each Connected Feature is enabled as a group Le all push buttons are enabled or disabled all LED s are enabled or disabled the POT is enabled or disabled Table 8 User Feature Enable USER FEATURE ENABLE SIGNAL SIGNAL LEVEL ENABLE DISABLE Push
22. USB BDM drives the DV rail directly from the USB bus Note that when powering the project board from the integrated USB BDM total current drain must not exceed 500mA Total current drain includes the BDM circuit all enabled project board circuitry any attached MCU module and any additional prototype circuitry connected to the project board Excessive current drain will violate the USB specification and will cause the USB bus to shutdown 8 Freescale Semiconductor When attached to the NI ELVIS workstation the 5V rail is driven through connector J1 from the workstation Refer to the NI ELVIS workstation user manual for further details The 3 3V rail is supplied from an on board regulator located at VR2 The VR2 input is connected to the 5V input through selection header PSEL_B VR2 supplies a maximum of 500mA of current to the project board The 3 3V regulator also features over current and over temperature protection The 15V rails are supplied from either an on board boost regulator at PS1 or the NI ELVIS workstation through connector J1 The PS1 input is derived from VIN connector through the regulator at VR1 If powered from VIN and an external power supply current on the 15V rails is limited to 50 mA In this configuration PS1 will consume 500mA of current output from VR1 If powered from the NI ELVIS workstation the 15V rails are provided directly from the workstation The workstation will provide a maximum current on the 15V rai
23. allows the student to e 2 Banana Connectors carry the Project Board in a standard 3 Ring e 1 BNC Connector binder e 8 pin Keypad connector Specifications e 1 Single turn User Potentiometer Module Size 8 5 x 11 e Connected to MCU PORT connector w Power Input 9V 1 2A typical separate enable 6 Freescale Semiconductor REFERENCES Reference documents are provided on the support CD in Acrobat Reader format More information can be found in the Application Notes section of the Freescale Web site PBMCUSCHEMSLKREVB pdf PBMCUSLK Schematic Rev B PBMCUSLKUG pdf PBMCUSLK User Guide this document LCD Commands pdf Commands for use with Project Board LCD display Refer to http www femacorp com for the following LCD Data Sheet P N CM0826 Datasheet for use with the Project Board LCD display NOTE Quick Start Guides for using the project board in conjunction with Freescale Student Learning Kit microcontrollers can be found at the following URL www freescale com universityprogram or on the included support CD Visit www freescale com universityprogram for current product information reference materials and updates GETTING STARTED To get started quickly please refer to the Quick Start Guide of your microcontroller prefixed with PB included on the Support CD The quick start will show the user how to configure the board for use with the MCU application module The quick start will also show the user how to install
24. ated adjacent to the breadboard A bypass capacitor on the output provides minimal smoothing on the POT signal The POT is configured as a Connected Feature See Connected Features section below for details Banana Jack The PBMCUSLK provides two 4 0mm banana jacks for use as auxiliary l O These connectors may be used for auxiliary signal input or for signal output to test equipment The banana jacks are color coded red and black The center conductor of each jack is routed to the User I O Signal Breakout connector labeled USER UO BANANA A B located adjacent to the breadboard area BNC Jack The PBMCUSLK provides one BNC jack for use as auxiliary I O This connector may be used for auxiliary signal input or for signal output to test equipment The center conductor BNC and shield BNC are routed separately to the User I O Signal Breakout connector labeled USER UO BNC located adjacent to the breadboard area For proper operation both signals must be connected For most circuit configurations BNC should be connected to GND Connected Features To simplify circuit construction and emphasize software development several user features have been connected to the MCU_PORT through FET switches and jumpers The FET switches are controlled by enable signals that are also routed to the MCU_PORT header This setup allows the user to electronically connect and disconnect each connected feature group A 6 position jumper UFEA or JP10 al
25. ded by the integrated BDM is derived from the USB bus Total current consumption for the project board and connected circuitry must not exceed 500mA This is the current supplied by the USB cable to the BDM target board and any connected circuitry Excessive current drain will violate the USB specification causing the USB bus to shutdown 12 Freescale Semiconductor USB Speed The communications speed over the USB bus is controlled by the J301 USB_SPEED header illustrated in figure 4 When shipped from the factory the board is configured for high speed operation If the user encounters a communication failure or erratic behavior USB communication speed may be reduced by setting this option jumper to Full Slowing the communications rate often resolves any problem encountered Figure 4 USB_SPEED Option Header USD SPEED Configuration HIGH B e FULL Selects USB High speed communications USB SPEED HIGH e FULL Selects USB Full speed communications CAUTION Do not allow total current drain to exceed 500mA when powered from the USB BDM BDM Voltage The integrated BDM is designed to interface with either 5V or 3 3V circuits The VDD level selected on the PBMCUSLK is fed back to the BDM to set output drive levels The VDD level is selected by VDD_SEL JP3 option header Further details on operating voltage selection may be found in the POWER section above As noted above total current dra
26. der VDD_SEL JP3 shown in figure 2 allows the user to select the operating voltage routed to VDD The 5V selection routes 5VDC to on board logic while the 3 3V selection routes 3 3VDC to on board logic All voltage levels are conveniently arranged around the prototype area to allowing easy access 15V voltage inputs are diode OR ed and available at connector J4 Figure 2 VDD GEL Option Header JP3 JP3 A 5V Sets VDD to 5v e 5V Sets VDD to 3 3V e 3 3V A 3 3V CAUTION Exercise care to select the correct operating voltage when interfacing to on board logic to prevent damaging circuit elements 15V Power The PBMCUSLK includes a DC DC converter at PS1 to supply 15V for use in analog circuit construction and analysis PS1 provides a maximum of 50mA on each output PS1 draws its input from the 5V rail The option header 15V_EN JP11 shown in table 2 disables the output if not needed Disabling PS1 when not used conserves power and will prolong the life of the 5V LDO at VR1 Table 2 15V_EN Option Header Shunt Effect ON Enables PS1 output to the project board OFF Disables PS1 output to the project board For project boards labeled MCU Project Board 2 AXM 0368 Rev C this jumper is labeled PS EN Freescale Semiconductor 11 MCU Module Power The PBMCUSLK may optionally power modules attached to the MCU PORT connectors Two 2 pin jumpers MODULE POWER VDD JP4A a
27. e table below details the NI ELVS signal breakout connectors Figure 18 NI ELVIS Signal Breakout J2 J3 J4 J2 GOI Sa O AI N wj A 10 11 14 15 16 17 18 19 20 21 22 23 24 25 26 Zi 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 59 54 55 56 57 58 59 60 SUPPLY GND SUPPLY DACH DAC 1 3 WIRE CURRENT HI CURRENT LO VOLTAGE HI VOLTAGE LO AM IN FM IN FUNC OUT SYNC OUT CH A CH A CH B CH B TRIGGER AISENSE AIGND ACHO ACHO ACHI1 ACH1 ACH2 ACH2 ACH3 ACH3 ACH4 Freescale Semiconductor J3 ke 3 4 5 6 ae ES as 9 10 a S 13 14 Z 15 16 Z 17118 19 20 Ji ri Se 23 24 D e 25 26 27 28 29 30 o 31 32 g 33 34 8 35 36 37 38 39 40 gt 2 G Do El S ACH4 ACHS ACHS FREQ OUT CTRO_SOURCE CTRO_GATE CTRO_OUT CTR1_SOURCE CTRL GATE CTR1_OUT 5V 5V RESERVED SCAN CLK PFI 1 PFI 2 PFI 5 PFI 6 PFI 7 3 3 V 3opuy J4 3 3 V WR_ENABLE RD_ENABLE siayunod SIAJ Et O alul wj 10 11 14 15 16 17 18 19 20
28. ed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSeminconductor hibbertgroup com Design and or Manufacturing services for this product provided by Axiom Manufacturing 2813 Industrial Lane Garland Tx 75041 Phone 972 926 9303 Web www axman com PBMCUSLKUG Rev 1 07 2007 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted
29. in from the integrated BDM must not exceed 500mA Excessive current drain will violate the USB 2 0 specification causing the USB bus to shutdown Freescale Semiconductor 13 User LO The PBMCUSLK provides an array of User I O to allow connection of auxiliary components such as signal input test equipment Keypads or LCD displays Many of these user features are by default enabled but can be disconnected through jumper settings This section describes each of the features in detail for more information on configuring these features please view the Connected Features section LCD Display The PBMCUSLK includes an 8 char x 2 line LCD module to support application development requiring character display output The LCD display is manufactured by FEMA Electronics Corporation part number CM0826 LCD PORT The display is connected by default to the MCU PORT pins through jumpers allowing direct interface to Freescale line of plug in application modules designed by Axiom Manufacturing The PBMCUSLK also provide 2 additional LCD connectors to support larger displays To utilize an alternate display the installed display must be removed and the correct header installed The PBMCULSK supports STN Reflective displays up to 20 char x 4 lines The contrast is selectable by the user between either a Fixed Mode or Adjustable Mode The fixed mode is pre set to a contrast easily viewable in ambient indoor lighting The adjustable mode allows the user
30. inal 28 Make sure the Serial cable is connected to the HOST PC Make sure the correct serial port is selected in the AxIDE program Make sure the AxIDE program options setting are configured correctly Freescale Semiconductor APPENDIX A SILK SCREEN
31. isconnect signal lines e Provides all necessary signals to target processor e COM Port e USB port connection e 9 pin DSUB connector e 60 pin MCU Interface Connector break out on both e RS 232 Interface with option to isolate ends of prototype area transceiver e PCI Style Card Edge connector designed for use with e COM SEL jumper selects configuration National Instrument s NI ELVIS platform between e Signal Breakout arranged logically around e RS 232 signals to transceiver Breadboard Area e MONOS Interface Port e Power Input from included wall plug transformer e Access to COM signals at Signal Breakout integrated USB BDM or from NI ELVIS Connector workstation e Socket for Optional Crystal Oscillator e On board voltage regulators provide 4 different e User selectable output amplitude 5V or 3 3V voltage levels e 8 Active High Green LED s Buffered with enable e S5VDC 500mA s 4LED s connected to MCU_PORT connector wi e 3 3VDC Y 500mA separate enable e I5VDC 50mA e 8 Active Low Push Button Switches e 15VDC 50mA e 4 Push Button Switches connected to e NOTE 15V is not available when powered MCU PORT connector w separate enable from USB BDM e 8 Active High DIP Switches e LED indicators for each voltage level e 1 External drive Buzzer e User selectable voltage to on board logic devices e Connected to MCU PORT connector wi e Option jumper to enable voltage output to MCU separate enable Port Connector e Mounting hole placement
32. lows the user to disconnect the enable signal if applying the associated port to other uses Connected Features include a POT 4 push button switches and 4 LED s Each feature group function is more fully described elsewhere in this User Guide Freescale Semiconductor 19 POT The POT signal is routed to MCU_PORT 20 through a FET switch This feature is controlled by a GPIO port signal on MCU_PORT 32 allowing the user to enable or disable this feature under MCU control An option header at UFEA isolates this enable signal allowing the user to apply the GPIO signal for other uses Table 5 POT Connections FEATURE CONNECTION POT VALUE MCU_PORT 20 POT ENABLE MCU_PORT 32 OPTION JUMPER UFEA 4 POT PUSH BUTTON SWITCHES D I PB4 are connected the MCU PORT through a FET bus switch This feature is controlled by a GPIO port signal connected to MCU_PORT 36 allowing the user enable or disable this feature under MCU control An option header at UFEA isolates this enable signal allowing the user to apply the GPIO signal for other uses Table 6 PB Switch Connections FEATURE CONNECTION PB1 VALUE MCU_PORT 9 PB2 VALUE MCU_PORT 11 PB3 VALUE MCU_PORT 29 PB4 VALUE MCU_PORT 31 PB ENABLE MCU_PORT 36 OPTION JUMPER UFEA 2 PB LED S LED LED4 are connected the MCU PORT through a FET bus switch This feature is controlled by a GPIO port signal connected to MCU_POR
33. ls of 500 mA The PS1 voltages and the J1 voltages are diode OR ed to prevent component damage Total current available is dependent on the configuration chosen and the load placed on each voltage rail For instance consider the following setup The project board is powered from a transformer connected to VIN A 50mA load is placed on the 15V and the 15V rails for the analog portion of the circuit Additionally a 500mA load is placed on the 3 3V rail In this configuration any load placed on the 5V rail will cause an over current condition in regulator VR1 Table 1 below lists current limits for each voltage rail in different input configurations Each current limit shows the maximum provided except in the case of the USB input The USB input assumes the USB circuitry consumes 200mA of peak current It is the users responsibility to ensure current limits are not exceeded in any configuration Table 1 Current Limits 5V 300mA Total current drain from USB bus must not exceed 500 mA Excessive 3 3V 200mA current drain will violate the USB specification N A USB 5V 500mA 3 3V 500mA 15V SOMA VIN POWER LIMITS SV 500mA 3 3V 500mA 15V 500mA 12V 500mA DI NOTE 3 3V rail is derived from 5V rail for all inputs Total current available on 3 3V rail is limited by total current available on 5V rail Freescale Semiconductor 9 Input Selection The PBMCUSLK
34. nd GND JP4B enable or disable power and ground to the MCU_PORT pins as illustrated in figure 3 Installing shunts at positions labeled VDD and GND connects MCU_PORT pin 1 to VDD and MCU_PORT pin 3 to GND NOTE To complete the circuit both shunts must be installed If not used both shunts should be removed Figure 3 MOD PWR Option Header Je Placing a shunt on JP4A routes VDD to MCU_PORT 1 e e VDD H e GND TRAR Placing a shunt on JP4B routes GDN to MCU_PORT 3 CAUTION When using this option selection make sure the module connected to the MCU_PORT is not configured to source voltage to the project board Damage to both the project board and attached module may result Integrated USB BDM The PBMCUSLK board features an integrated USB Background Debug Mode BDM from P amp E Microcomputer Systems The integrated BDM possesses all the necessary signals to support application development and debugging A USB type B connector provides connection from the target board to the host PC Communication and control signals BGND RESET are connected directly to the MCU_PORT connections This arrangement allows the user to program and debug Freescale HCSO8 and HCS12 Application Modules Student Learning kits without the need for external wiring The integrated USB BDM provides 5V power and ground to the target board eliminating the need to power the board through VIN or J1 Power provi
35. ng module uses option selection jumpers to setup configuration Terminology for use of the option jumpers is as follows Jumper a plastic shunt that connects 2 terminals electrically Jumper on in or installed jumper is installed such that 2 pins are connected together Jumper off out or idle jumper is installed on 1 pin only It is recommended that jumpers be idled by installing on 1 pin so it will not be lost Freescale Semiconductor 5 FEATURES The PBMCUSLK is a full featured prototyping platform intended for interfacing and programming Freescale MCU development modules in an educational environment A line of HC S 12 X HC S 08 DSP and ColdFire modules plug directly into the project board Other MCU boards can be interfaced directly to the project board by ribbon cable The PBMCUSLK may also be used as an electronic circuit prototyping environment without MCU support The project board has been specifically designed for compatibility with the National Instruments Educational Laboratory Virtual Instrumentation Suite NI ELVIS An integrated USB BDM POD has been provided to allow the user to program erase and debug supported Freescale MCU modules Features include e Large Replaceable Solderless Breadboard Area e 8 character x 2 line LCD panel e Integrated HC S 12 X HCS08 Multilink BDM e Fixed and Variable Contrast e Allows debugging target processor via e Selectable Chip Select background debug mode e Option header to d
36. nput 1 LCD enable EN 6 CONTRAST LCD contrast input DBO 7 RS Register Select 0 LCD Command 1 LCD Data DBI 8 DB2 9 DB3 10 LCD_D4 11 LCD D5 12 LCD_D6 13 LCD_D7 14 Freescale Semiconductor 15 LCD Contrast The PBMCUSLK offers two methods for controlling the LCD panel contrast fixed or adjustable controlled through jumper CONTRAST JP12 as illustrated in figure 8 The fixed option provides near maximum contrast and supports all STN Reflective type LCD panels The fixed mode is pre set to a contrast easily viewable in ambient indoor lighting The adjustable option allows the use on the project board potentiometer to vary the contrast voltage applied to the LCD panel This allows the user to apply temperature or lighting compensation if needed Figure 8 Contrast Select JP12 JP12 MN ADJ Selects on board POT to allow adjustment of LCD contrast e e FIX voltage JP12 e e ADJ Selects fixed LCD contrast voltage C WP LCD Select To allow maximum flexibility the control signal used to transfer data to the LCD panel is selectable Option header SS_SEL described in figure 9 selects between the SPI port SS signal or the GPIO signal connected to MCU_PORT 25 Figure 9 SS_SEL Option Header JPS JPS ss A Selects dedicated SS SS e Selects GPIO signal on MCU_25 input source A GPIO e GPIO NOTE To
37. om the USB bus Care must be exercised not to draw too much power when connected to the USB bus USB2 0 specifications limit the total current drain from the bus to less than 500mA Exceeding this limit will cause the USB device to disconnect and may damage the project board or host PC VDD Selection The operating voltage level VDD supplies all on board logic devices on the PBMCUSLK An option header allows the user to set VDD at either 5V or 3 3V When the project board is connected to a wall plug transformer voltage regulator VR1 provides the 5V rail and regulator VR2 provides the 3 3V rail Regulator VR1 is rated for a For project boards labeled MCU Project Board 2 AXM 0368 Rev C these jumpers are labeled PSEL_A and PSEL_B respectively 10 Freescale Semiconductor maximum current output of 1A while regulator VR2 is rated for a maximum current output of 500mA In this configuration 15V is provided by the regulator at PS1 Both PS1 and VR2 derive their input from VR1 This setup may limit available current in mixed voltage applications Each regulator is internally current limited to prevent damage from inadvertent short circuits of short duration The regulator at PS1 is not protected from continuous short circuits on its output When connected to NI ELVIS the 5V rail is provided by the workstation This input also drives the 3 3V regulator at VR2 15V is available from the workstation and PS1 is not connected A 3 pin option hea
38. rom the VIN connector or from the NI ELVIS workstation Freescale Semiconductor 23 Signal Breakout An important feature of the PBMCUSLK is the large centrally located breadboard area Dual row socket headers strategically placed around the breadboard provide signal access to the on board circuits Signal breakouts may be grouped into 3 broad categories MCU Access Signals User I O Signals and NI ELVIS Signals USER LO User I O signal breakout connectors provide access to all on board components Each signal and signal group is labeled to ease signal identification and location To ease prototyping each signal is routed to two socket locations This allows the user to easily route each to signal to multiple locations if desired The table below details the USER UO Signal Breakout connectors Figure 15 USER UO Signal Breakout J10 J11 J10 PB 1 PB 2 PB 3 PB 4 PB 5 PB 6 11 12 PB 7 13 14 PB 8 15 16 LED 1 17 18 LED 2 19 20 LED 3 21 22 LED 4 23 24 LED 5 25 26 LED 6 27 28 LED 7 29 30 LED 8 31 32 5 V 33 34 GND 35 36 3 3 V 37 38 VTST 39 40 VDD 41 42 POT 43 44 SW1 1 45 46 SW1 2 47 48 SW1 3 49 50 SW1 4 51 52 SW2 1 53 54 SW2 2 55 56 SW2 3 57 58 SW2 4 59 60 Cl it G l NV Oi Goa ra SNOILYOINAWWOOD O I YASA AYdATA O I Yasna
39. sources power from the VIN barrel connector the USB BDM or connector J1 The barrel connector is situated on the project board to prevent connection of an external power supply while connected to the NI ELVIS workstation Two selection headers determine the source of input power to the project board These selection headers are situated to prevent selecting 2 input power sources at the same time Selection headers PWR_SEL JP1 and 5V_SEL JP2 illustrated in figure 1 select which input source to supply power to the project board PWR SEL selects either connector VIN or connector J1 as an input source 5V_SEL selects either the output of PWR_SEL JP1 or the USB BDM as an input source The output of PWR_SEL connects directly to pin 3 of 5V_SEL The output of 5V_SEL drives the 5V rail and the input of the 3 3V regulator VR2 Figure 1 Input Power Select PWR_SEL JP1 JP1 A Jl Selects Jl input source e JI Selects VIN input source e VIN E VIN 5V_SEL JP2 JP2 A USB Selects USB input e USB Selects JP1 input source to source to supply 5V rail A supply 5V rail e JPI JP1 Power input on the barrel connector is supplied by the included wall plug transformer or a desktop power supply Input voltage on this connector should be between 8V and 12V Higher input voltages may cause excessive heating and force VR1 into thermal shutdown Power input from the USB connector is drawn fr
40. t levels The input level is determined by VDD selection A 10K ohm resistor holds each buffer input low to prevent inadvertent LED activation The LED buffer driver may be disabled by removing the shunt at LED EN as illustrated in table A LED inputs are routed to the signal breakout header located adjacent to the breadboard Four LED s are connected directly to the MCU_PORT connector See the Connected Features section below for details Table 4 LED_EN Option Header Shunt Effect ON Enable LED Output OFF Disable LED Output Keypad The KEYPAD connector shown in figure 11 supports connection of a passive 12 key or 16 key keypad The KEYPAD connector is routed directly to the signal breakout header labeled KEYPAD located adjacent to the breadboard No current limit is provided on this connection and should be provided by the user if required Figure 11 Keypad Connector KEYPAD 8 KEYPAD 7 KEYPAD 6 KEYPAD 5 KEYPAD 4 KEYPAD 3 KEYPAD 2 KEYPAD 1 These signal connect directly to the User I O signal breakout connector located below the breadboard N WK A AIAN oo 18 Freescale Semiconductor Potentiometer The PBMCUSLK provides a single turn 5K ohm trim potentiometer for use in circuit prototyping Most commonly the POT may be used to provide analog input signals to the microcontroller This signal is routed to the signal breakout header labeled USER I O POT loc
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