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CDB47xxx User`s Manual

1. SMID uem I Serial Control Ports Wh traces going to both UM JPI U2 Veca voce enese N QU MCU_SDA ENCODER A gn 5 _ 54 BRA sus DBCK 3461 ENCODERS Prog Counter Array inputs 8 18 EAA PAR a RS ANA 00 T 5 external interrupts 1 2 cen be external interupts 1 Lil 222 36 BUTTONS un A CO Ree anaa 11 wre ari UB us pzs RA BELA Wy P27 SPOF COAX ST 10 EEUU B cBosiF340 c0 550 Hi AE TOFS M pa ed 8058340 00 108048 2 131 OSP CTR tai 5 cus aus 12 Pis HE AME XR SOUR x 1 uP E petam 44 Tow 5 M PS is low during reset bootloader will not application code am cm EJ p Ey Y 2223222382 m 2 x 9 to ma ARE swzaverz
2. nava 2 aouri gt 12 aout se AQUI 7e AQUT gast m Mkt mua St Cl gi aae E x gt 1 7 s nuuc 34007 2 in 34007 52 8 1 7 1 m 4001 87 wee 11 ANC m ana o EA d 1 aw oat m ane c Since a angs om Figure 6 26 47 48 Daughter Card Schematic JIDOT SMID pe gpOq xxx rgqO enuey sasn Obtaining Schematic Updates CDB47xxx User s Manual 1 CIRRUS LOGIC 6 5 Obtaining Schematic Updates Updates to the schematics for the CDB47xxx Development Board can be can be obtained from your local Cirrus Logic representative as part of a design package including the associated BOM and layout artwork The schematics are provided in Adobe
3. 1 3 1 2 3 Support Hardware 0 00000 a 1 3 1 2 4 Cabling Requirements a 1 3 1 3 CDB47xxx Board System Description 1 4 AU GIO 1 5 1 3 1 1 Analog Line level Inputs Single Ended CDB47xxxS only AINTA AIN5B AINGB 1 5 1 3 1 2 Analog Line level Inputs Differential CDB47xxxD only AINBB 1 5 1 3 1 3 Optical Digital Input 21 1 6 1 3 124 Coaxial Digital Input 4 tere E Rape dete teet den 1 6 1 3 1 5 Microphone Input 09 1 6 1 3 1 6 DSP Digital Audio Input DAI 718 or DAI 1 6 1 3 2 1 6 1 3 2 1 Main Analog Line level Outputs CDB47xxxS and CDB47xxxD 45 48 10 13 or AOUT_1 AOUT 8 1 6 1 3 2 2 Optical Digital 1 6 1 3 2 3 Coaxial Digital Output 9395 1 6 1 3 2 4 DSP Digital Audio Output DAO J24 DAO 1 7 1 3 3 DG Power Input 2 parrari ara aaea aa Ea 1 7 1
4. 6 27 Figure 6 23 CDB47xxD Differential Microcontroller Card Schematic 6 28 Figure 6 24 CDB47xxD Differential Microcontroller Card User Interface 6 29 Figure 6 25 CDB47xxx DC48 Daughter Card Block 6 31 Figure 6 26 CDB47xxx DC48 Daughter Card Schematic 6 32 Tables Table 1 1 CDB4 Kit Gontents erede tare 1 1 DS886DB4 Copyright 2009 Cirrus Logic CDB47xxx User s Manual 1 vii CDB47xxx User s Manual viii Copyright 2009 Cirrus Logic Inc DS886DB4 CDB47xxx Kit Contents CDB47xxx User s Manual Chapter 1 Kit Contents and Requirements 1 1 CDB47xxx Kit Contents Each CDB47xxx kit comes with the items listed in Table 1 1 Table 1 1 CDB47xxx Kit Contents CRD Kit Item Quantity CDB47xxxS DC48 CDB47xxxS DC28 CDB47xxxS DC24 CDB47xxxD DC48 CDB47xxxD DC28 CDB47xxxD DC24 CDB47xxxS DOxx CDB47xxxS Single Ended Development Board with integrated MCU amp USB interface with Daughter Card populated with either the CS47048 CS4028 or CS47024 DSP CDB47xxxD Differential Development Board with integrated MCU amp USB interface with Daughter Card populated with either the CS47048 CS4028 or CS47024 DSP CDB47xxxD DCxx Power Supply 9V 2A 100V 240V with AC Power
5. 4 6 4 2 5 2 Audio Out via S PDIF Oul a 4 6 4 2 5 3 12 Audio Input 4 7 4 2 6 Changing Serial Control Protocol 12 or SPI Flash 4 7 Chapter 5 Using DSP Composer or Micro Condenser Application to Create and Load a Flash Image 5 1 5 1 Programming a Serial Flash Device for Master or Slave Boot Operations 5 1 5 1 1 Using DSP Composer to Create and Load a Flash Image for Master Mode Operations uuu uuu cipio tee cea pe 5 1 5 1 2 Using Micro Condenser to Create and Load a Flash Image for Slave Mode Operations acce reet ett necu 5 3 5 1 2 1 Micro Condenser 5 3 5 1 2 2 Micro Condenser Restrictions Conventions 5 3 5 1 3 Using Micro Condenser to Create and Load a Flash Image into the 5 4 iv Copyright 2009 Cirrus Logic Inc DS886DB4 CDB47xxx User s Manual 5 1 3 1 Creating a Flash Image u 5 4 5 1 3 2 Programming the Flash Image into the Flash 5 4 Chapter 6 CDB47xxx Schematics l J J J 6 1 6 1 Introduction
6. 6 11 Figure 6 9 CDB47xxxS Sngle ended DAC Filters 0 6 12 Figure 6 10 CDB47xxxS Sngle ended Microcontroller Card Interface 6 13 Figure 6 11 CDB47xxxS Sngle ended Microcontroller Card User Interface 6 14 vi Copyright 2009 Cirrus Logic Inc DS886DB4 Figure 6 12 CDB47xxxS Sngle ended Microcontroller Card User Interface 6 15 Figure 6 13 CDB47xxD Differential Board Block 6 18 Figure 6 14 CDB47xxD Differential Board Schematic Index 6 19 Figure 6 15 CDB47xxD Differential Daughter Card Connectors sese 6 20 Figure 6 16 CDB47xxD Differential Digital Audio Control Connectors 6 21 Figure 6 17 CDB47xxD Differential Digital Serial 6 22 Figure 6 18 CDB47xxD Differential Mic Pre Amp a 6 23 Figure 6 19 CDB47xxxD Differential Power Connectors sse eere 6 24 Figure 6 20 CDB47xxD Differential ADC Filters 2 nre 6 25 Figure 6 21 CDB47xxD Differential Voltage Output Circuitry esses 6 26 Figure 6 22 CDB47xxD Differential Microcontroller Card Interface
7. c22 RI 560 aout AUT AQUI 1 R23 4 SF 2200 or 191 MUTE 28C3326 A TSL F T 55 RCJ 052 V RED R25 560 13 AOUT 2 C zona R26 47K g 87 2205 a2 t8 gt 2SC3326 A TSLF T m RCJ 053 V WHT C24 R28 560 31 ADUT 3 SEL R27 I 1985 8 T2200pF 19 MUTE K 2Sc3326 A T5L F T RCJ 052 V RED C25 R29 560 13 AQUT_4 C _ AQUT 4 47K ST 2200 R43 2K 19 gt Ay 28C3326 A TSL F T DAC WUTE 5VA AQUT S ans RCJ 053 V WHT 7 97 2SC3326 A T5L F T RCJ 052 V RED us 8 Em RCJ 053 V WHT R32 560 31 _5 3f 8 7 ST 220 2S03326 A T5L F T RCJ 052 V RED 31 AOUT_6 12 47 06 2803326 A TSL F T C28 R36 560 220 t3 AQUT 7 4 R35 17 8 22009r LM R37 560 t3 A0UT_8 1 t R38 47K 8220057 2803326 A TSL F T tg gt 33VA MWUN2WLTIG uurz 9 R39 10K 600 00358 21 RI 55 Ue DAC FILTERS 04 2007 E 9 Figure 6 9 CDB47xxxS Sngle ended DAC Filters 21 SMID DID suonduoseq
8. 6 1 6 2 CDB47xxS Single Ended Schematic 6 1 6 2 1 CDB47xxxS Block Diagram I a naa 6 1 6 2 2 Daughterboard Connectors n nensi nnn enne 6 1 6 2 3 Digital Audio and Control Connectors 2 2 00 0 0 6 1 6 2 4 6 2 6 2 5 Microphone esee ro 6 2 62 uolet l l u uu D 6 2 6 2 7 INPUT 6 2 5 2 8 Output Fillers 6 3 6 2 9 MCU Block Diagrami tone 6 3 6 2 10 MOU EE 6 3 6 2 11 User Interface D8vIg8s_ eren 6 3 6 3 CDB47xxD Differential Schematic 6 16 6 3 1 CDB47xxxD Block Diagram esses enne 6 16 6 3 2 Daughterboard nensi nnne 6 16 6 3 3 Digital Audio and Control Connectors eene 6 16 6 3 4 MOMON 6 16 6 3 5 Microphone 6 16 6 3 6 6 16 Input FIS Petit nie u u uyu E 6 16 6 3 8 OUTPUT 6 16 6 3 9
9. E 0 120 5 f ane t 27 uns t 12C gt DEBUG 4 m 1 wee 5 6 x z 3 1 8 0 803815 SCP MISO SDA itm WCUCTLASH CS jum SEF DEBUG H gt a sce mgus Un wcu SL iu SCP CLK Ed 13 4 SCP MIS SDA muse s FOLDS c be 7 0051 n XIR po 52 R MC SCRISE PTS E m 5 rese kG Serial Control Ports SCP Mos 13410 n i 22 8 PCA95170P ic SDA tm traces going to both U14 JP1 J2 MCU SCL au veca 3 6 if y 1121 1 um MCU SDA SDAA SDAB DBDA 3 4 TI ENCODER im 04 08 seia ENGOBER B Prog Counter Array inputs GND H i 116 i pes Heer ra SCP DEBUG 11 R DSE RESET FISSA A AS Bs 2 MCUCJP1_CTRL i i gt 7224 s s eee ee external interrupts 1 Hn 11 2 con be external interupts Ces 55 P2 3 USB vy P0 3 1 LI Pot us pas Be RIGS AAAS POETS 53 bey 81 pee C8051F340 6Q P3 0 2 Rr D D P3 1 PR 20 t n Doo 2 i EN BH 4 5 op cuo 2 1
10. 12S HDRs C Header will be available to probe bring in 12S signals EE 12S IN HDR D B 47 20 Pin HDR Standard 20 Pin Debug Header Serial Control amp Debug 1 Mic iqi Mic Input DSP Daughtercard Buffer Digital RETI sd lt The Chronos DSP Daughercard will have only DSP Diff d This allows us to easily swap out the DSP for different AUD Stereo 1 8 CS47xxx Family members 4 Analog 2 DAO Buttons LEDs 1 Digital 27 DAO pins on Chronos also GPIO These buttons LEDs 1 Stereo 1 8 Can be used by the new primitives being developed 5 2ch GPIO SPDIF HDR GPIO Rx ADC Digital 125 OUT Use gt SRC 5 HR 8 ch DaughterCard DAC SPDIF Tx SMALL my nao 20 PIN HDR Control z z 5 Eg E Diff 8ch ou 5 Digital N Amp 773 is OUT SPI HOLD SPI gt FLASH FLASH USB MCU GPIO Silicon Labs Control Parallel Port SPDIF OUT Buffer 5 1 LCD Panel Buttons SPDIF OUT P OPTICAL omposer Rotary Knob Wall Adapter Bi B2 B3 N Rotary Figure 1 4 CDB47xxxD Main Board Block Diagram 1 3 1 Audio Inputs 1 3 1 1 Analog Line level Inputs Single Ended CDB47xxxS only AIN1A AIN5B AINGB Analog line level inputs ha
11. COFUSRCRODS 146 14 1 lt FLASH_SCP_CLK 351 120 EEPROM E nm A U ATACSUBN SI Iw 38 rui sco gt EE RH 13 5 FLASH 34507508 CO SDA GND cus Jour ADDRESS 1010 A2 A1 12 ADDR 0 0 600 00357 21 REV A 971775 SERIAL FLASH 7 20 06 ser 9o 12 Figure 6 17 CDB47xxD Differential Digital Serial Flash enuey ses xxx Frgao UJ N 5 g 5 D 0 3 D 5 o radesssa 91607 50 49 6002 1u6u doo 55 9 20 mVpp Full Scale ADC Vin 4Vrms uc 1X 105K Kr r225 MIC INPUT ym PREAMP OUTPUT jor 168 1 8 3 5mm stereo Loser PE TO ADC E oun NE5532D ak aces R220 1K 68 gt gt um NE5532D ciet Heos 2709F NE55320 FILTER MIC POWER AGAIN SINCE POWER IS FED DIRECTLY TO HI GAIN OPAMP THROUGH 2 2K PULL UP sova sava 224 Y N sava uc 5 C165 0164 sva Tee 49 Sva UIB A 78 R231 R232 io 15 Vcc 908 gt
12. ro RM 1 4 R26 4000002226992720237727005 19 CDB47XXX DC48 94U 0 RZ 02 6H wiSO SDA Figure 2 4 CDB47xxx DC48 Daughter 2 2 3 1 CDB47xxx DC48 Daughter Card Components The circled numbers found in Figure 2 4 refer to the CDB47xxx DC48 Daughter Card components in the following list 1 Cirrus Logic CS47048 DSP Power LEDs 2 MCLK XTAL_OUT Header DSP GPIO Button DSP GPIO LED DSP GPIO LED DSP GPIO Switch 1 8VD Probe Point o AR 2 7 Copyright 2009 Cirrus Logic Inc DS886DB4 Identifying CDB47xxx Components CDB47xxx User s Manual 9 3 3 0 Probe Point 10 1 8VA Probe Point 11 3 3 Probe Point SS DS886DB4 Copyright 2009 Cirrus Logic Inc 2 8 Installation Setup and Running First Application 2 CDB47xxx User s Manual Ss CIRRUS LOGIC Chapter 3 Installation and Setup of Development Board Software 3 1 Installation Setup and Running First Application It is important to install the CDB47xxx Board software before connecting the USB cable from the PC to the USB port of the CDB47xxx Board Failure to install the evaluation software before the initial connection can result in an inability to communicate with the CDB47xxx 3 1 1 Evaluation Software Installation The DSP evaluation software installation will first install the Cirrus Logic DSP evaluation softwa
13. RCJ 052 V RED c25 R29 560 U7 8 55320 tl ul try 9VA us a 55320 KIR d cus XR Our U7 A ness320 XS Y U 5VA 9VA 0176 UB A XIR 55320 m d X 5VA cus ERI XIR 5VA 433A gt MMUN2ULTIG Cuurz 191 03 _5 O RILA AA amp B7K 34 13 AQUT_5 131 AOUT 6 3 AoUT_7 131 AQUT 7 8 AOUT B RS 8 JIDOT SMID NE5532D R31 5 n i 4700pF u 18 MUTE 2SC3326 A T5L F T gt 027 R33 560 AEE 55320 R34 MWY S 1 d 22uF RBLA AA ABK 19 MUTE 2SC3326 A T5L F T C24 4 826 1 4700F 2 c29 R37 560 j ub us B 55320 R3B 8 RCJ 052 V RED 25C3326 A T5L F T 181 MUTE 98 600 00357 21 REV BETTE DIFF VOUT 5 04 2007 45 9o 12 Figure 6 21 CDB47xxD Differential Voltage Output Circuitry suonduoseq enuey sasn xxx pg qO radesssa 91607 5
14. Sxx pgdo enuey sasn xxx Fgao radesssa 91607 50 19 6002 1 EL 9 User Interface IR LCD 1 0 5 01 Encoder 4 buttons MCU C8051F 340 MCU flash code application USB Bootloader Shared USBXpress API C2 debug SPI flash USB 9VDC input gt 9 3 3V regulator Control amp Interrupt Signals JP1 Customer Debug Port JP3 hdr for CRD CDB DSP boards 600 00358 21 REV A SHEET 5 MCU BLOCK DIAGRAM 4 18 07 10 12 Figure 6 10 CDB47xxxS Sngle ended Microcontroller Card Interface enuey sasn xxx Fgao UJ N x 0 5 9 5 0 3 m o o 5 o radesssa 7 80 10 eooz 1uBu doo 9160 32 MBit SPI FLASH 120 muxing 2 Ed 0 I2C SCP m i i E 1 I2C gt DEBUG TE jm Nc7sPUDaPsx vera 2 2 ssrsvros20 ss a sawr tm mr 8 1 oh nes Spee BE GND 21655 s 15 MOSI R ucu AA Sop cuk
15. CIRRUS LOGIC CDB47xxx Evaluation Kit CDB47xxx User s Manual Prelimi Product Inf ti This document contains information for a new product Froauct information Cirrus Logic reserves the right to modify this product without notice CIRRUS LOGIC Copyright 2009 Cirrus Logic Inc 2 http www cirrus com CIRRUS LOGIC CDB47xxx User s Manual Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative To find the one nearest to you go to www cirrus com IMPORTANT NOTICE Preliminary product information describes products that are in production but for which full characterization data is not yet available Cirrus Logic Inc and its subsidiaries Cirrus believe that the information contained in this document is accurate and reliable However the information is subject to change without notice and is provided AS 15 without warranty of any kind express or implied Customers are advised to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment including those pertaining to warranty indemnification and limitation of liability No responsibility is assumed by Cirrus for the use of this information inclu
16. 20 cus nm m 515 3 sx REM T MC_PREAWP_4908 our E38 20 ANSA 03 ane our yet m Danses c ANY Mese m f Hid 2 51 Lacie ium I n icm I 7 Jurycus lt x g moe m sour spss am LAC 2 07 ss 00 00357 21 REV A SSE DIFFERENTIAL ADC FILTERS 10 9 08 P ser Bo 12 Sc 9 Figure 6 20 CDB47xxD Differential ADC Filters suonduoseq 0 enuey ses xxx Frgao radesssa 7 80 10 eooz 1uBu doo 9160 92 9 Differential Voltage Output Circu RCJ 083 V WHT uri 3 5320 31 AQUT S a wr gt 2Sc3326 A T5LF T 5 RCJ 052 V RED t3 aout 2 AM R25 HE 5532 t3 Aout 2 ELEC ur 9 MUTE gt 2SC3326 A T5L F T exo E 1800p R 161 BAW m RCI 053 V WHT aour s u 5 2 me 580 s oF NE35320 aout ORAA _ Rios Task oss L 2006 E 18 gt 2SC3326 A T5L F T 31 AOUT_4 5 AOUT_4 8 C70
17. m 77122 E 12 pa02 us2 gt Isolate XTAL_OUT to use J mosmas alternate MCLK src 3143 40051 Bo pre mel me 6 5 5 Ws 18 B 88 EER Auxiliary H W Docs 21 sce eal d 8 ESAE ASSY 2 15 29 1075 Eca owe 240 00353 2 CE ios ae e SS W SCH DWG 600 00359 21 Vas 44 0 S vin par side m ix o B me di T0P SDE ot last 3 vis per side 1 s one B NUM CURRENT MEASURE T m 55 5 Bom n Pe D a 1 BjO FESES 12 DE LAE TQP SDE ot les 3 vios per side m m a o cm cm apa avs 2102 sce 121 pem CURRENT WEASURE PONT m L owm 4 un i sata NOTES UNLESS OTHERWISE SPECIFIE DEFAULT SPI amp I2C ADDR 0x80 1 sua 1 MODE FOR CS47xxx SELECTED DYNAMICALLY BY DRIVING HS 3 0 PINS L E 603 00359 21 REV Switch and LED for Primitives HEET TT PUT 0547048 DSP U 10 13 08 44 2 2 EE Ee Eu inet al 05
18. m SSS SSS ST CIRRUS LOGIC eters Manuel Snapshot 0 is the initial configuration that is generated by DSP Composer when the Go button is pressed and is stored in the file initial cfg 5 1 3 Using Micro Condenser to Create and Load a Flash Image into the DSP 5 1 3 1 Creating a Flash Image To use the Micro Condenser application to create and load a Flash image to the CS470xx DSP on the CDB47xxx Board follow these steps Follow these steps to create the Flash image 1 9 Complete examples are included with the evaluation kits C CirrusDSP micro condenser CS47XxXX example Use DSP Composer to create the desired Composer Project Archive cpa files If more than one setting of the DSP code is desired you must save the desired settings as snapshots using the snapshot manager Tools Snapshots This has been done in the cpa example files When you have created all the desired snapshots create the initial setting Note that the initial setting is only generated when you press Go This means you must change the configuration in DSP Composer and then press after that save your cpa file Generate Deliverables using the drop down menu option Tools Generate Deliverables Repeat steps 1 through 3 for each cpa file Specify the projects and snapshots that are to be included in the Flash image which is accomplished within an XML file for the included example refer to C
19. 2 7 Chapter 3 Installation and Setup of Development Board Software 3 1 3 1 Installation Setup and Running First 3 1 3 1 1 Evaluation Software Installation eene 3 1 3 1 2 Setting up the CDB47xxx Board with a DVD 3 1 3 1 3 Connecting 3 2 3 1 4 Running a Stereo SPDIF DAC Out Application on CDB47Xxxx 3 3 3 1 5 Running a Stereo ADC In DAC Out Application on CDB47XXX 3 3 Chapter 4 Programming the CDB47xxx 4 1 4 1 Introduction u Reg REX RE Oe Rx 4 1 4 2 Running the ADC In DAC Out Example 4 1 4 2 1 System C 4 2 4 2 2 Selecting Changing Audio Input 4 3 4 2 2 1 Audio IA 4 3 4 2 2 2 Audio In S PDIF 4 4 4 2 2 3 ZS Audio 4 4 4 2 3 Input Channel Remap 4 4 4 2 4 Output Channel RRemap uuu uuu uuu ettet 4 5 4 2 5 Selecting the Audio Output Configuration 4 5 4 2 5 Audio Out via
20. O 0 5 3 radesssa 7 80 10 eooz 1uBu doo 9160 65 9 am A un og 1 10 05 10 16 25 los cs Ie 2 wm oti 2 o E m Loom m Ls om DAUGHTERCARD ID REGISTER 0x00 0x07 Parallel load on 05 RESET Shift out ID on SCP_CLK when DSP_CS is low 121 58 AN 21 PC must drive release DSP reset ond then write 1 byte to DSP to get ID 4 mmm This procedure can be part of the normal slove boot E esses m m pack l 1 uta BA 8 ES NE IU M Place R13 R14 close under DSP Noor us mr lace close under Herd 2 bs d EHE Em H 7 xx m S 722 JEn m p qoum RW TES un dq ss 00 ca bur oT gt R20 AA S ROAD CLK 3 Default Boot Mode Master SPI3 111 PD 7 ra m m zu 5 al 89 SW 48 C mor pa og 80 SH m Cu 8 Sh
21. s Burtons y 330 A R206 E T ios Buttons 1V 3 4 6 mA PE Buttons 1 5V i 3 6mA Buttons 27 2 5 mA Buttons 2 5V 16mA R190 d I mci 00009 0 Buttons 0 6 Select 8 130 TH ae LCD LCD PANEL SOCKET T u Sues moa 29 uu uo yt 0 vse cm rm un tm an m PTE 600 00357 721 REV SHEET TLE USER INTERFACE me 04 2007 955 ser 12 12 Figure 6 24 CDB47xxD Differential Microcontroller Card User Interface 2 THAT FDOT 5 enuey sasn xxx pg qO ii suonduoseq 0 CDB47xxx DC48 Daughter Card Schematic CIRRUS LOGIC 0 6 4 CDB47xxx DC48 Daughter Card Schematic 6 4 1 CDB47xxx DC48 Block Diagram Figure 6 25 shows the CDB47xxx DC48 block diagram 6 4 2 CDB47xxx DC48 Schematic The schematic for the CDB47xxx DC48 daughter is shown in Figure 6 26 The CDB47xxx DC48 employs the CS47048 DSP The DSP is driven by an external crystal circuit This fixed 24 576 MHz clock is used to drive the
22. Ruz aens Xm 6 E Sw Deor Pono SENSE_1 8V 3 UNECOMP 70 NOPOP FEEDBACK PATH TO PROVIDE VOLTAGE SENSE WHEN RUNNING DSP FROM EXTERNAL POWER Sur F F REDUCE ESR BY PUTTING CAPS IN PARALLEL TO REDUCE RIPPLE POWER INDICATORS 3340 50 R237 R97 RNI 8720 300 536 787 24 LED BLUE GREEN YELLOW RED lt or Y gt Y sva 2SC3326 A T5L F T 600 00358 21 REV SET CONNECTORS POWER t 4 18 07 Z ser 7o 12 Figure 6 7 CDB47xxxS Single ended Power Connectors 59112 enuey sasn xxx Fgao suonduoseq Sxx pgdo radesssa 7 80 10 eooz 1uBu doo 9160 E RCJ 053 V WHT SINGI 10uF ye Rig ania as RCJ 052 V RED AN DM 22087 NOPOP 220pF 3 NOPOP ur yeu mal 38 AN BB 3 R52 3 36 53 e JAn ag K R96 s aK 51006 220 1 0 220pF _2 8 4 052 4 8 284 qu s
23. 6 19 gt Diagram Schematic INDEX DSP CONNECTORS DIGITAL AUDIO CTRL CONNECTORS FLASH MICROPHONE PREAMP POWER ADC FILTERS GQ Ww DAC FILTERS 10 MCU BLOCK DIAGRAM MCU 8051F340 12 USER INTERFACE Figure 6 14 CDB47xxD Differential Board Schematic Index Copyright 2009 Cirrus Logic Inc DS886DB4 radessesa 7 80 10 eooz 1 9160 02 9 J2 HOR40X2 BMM ML 3 5V0 52 C gt DC ID 111 171 SENSE 3 3V CJ 7 SENSE 1 8V lt 7 4 0 DSP RESET DBCK 4 117 DBDA 441 4 DAI LRCLK DAI SCLK 4 41 41 2 9 141 2 4 DAO_LRCLK 41 4 11 DAO2 HS2 3 4 lt JDAI3 SPDIF _RX 4 DAO_SCLK 41 H DAO0 HSO0 14 11 gt DA01 HS1 4 111 gt DA03 XMTA HS3 4 111 4 11 5 MOSI 2 4 14 111 SCP_MISO SDA 4 111 DSP CS 51 FLASH MISO SDA 51 FLASH_M0SI 5 SCP_CLK 4 11 4 111 DSP_IRQ L gt DSP_BSY7EE_CS 4 1 191 AQUT 54 9 A0UT_5 9 AOUT_7 191 AOUT_7 B _2 91 T AOUT 2 191 HO AQUT 44 9 AQUT 4 9 L C _6 19 t 1_ gt aouT_6 191 T AOUT 84 9 AOUT_8 191 8 8 AIN_6A 2 7 8 6A
24. synchronous In this configuration the SRC is bypassed for the DAO 1 6 Other Useful Information 1 6 1 Web Sites Cirrus Logic main web site www cirrus com 1 6 2 DSP Information The following information can be obtained from your Cirrus Logic representative CS470xx Data Sheet CS470xx Hardware User s Manual AN333 CS470xx Firmware User s Manual Copyright 2009 Cirrus Logic Inc DS886DB4 Other Useful Information CDB47xxx User s Manual IRRUS LOGIC 1 6 3 Board Information The following information can be obtained from your local Cirrus Logic representative Schematics BOM Artwork and PCB stackup 1 6 4 DSP Software Utility Information The following information can be obtained from your local Cirrus representative DSP Composer User s Manual DSP Composer Primitive Elements Reference The documents listed above are updated periodically and may be more up to date than the information in this document Contact your Cirrus Logic sales representative for the latest updates 882 2 The 58 symbol is used throughout this manual to indicate the end of the text flow in a chapter DS886DB4 Copyright 2009 Cirrus Logic Inc 1 18 IX Introducing the CDB47xxx Customer Development Kit CDB47xxx User s Manual It 1 CIRRUS LOGIC Chapter 2 Introduction to CDB47xxx Kit 2 1 2 1 Introducing the CDB47xxx C
25. 0 5 5 0 3 m o o 5 o radesssa 91607 50 49 6002 1 6 9 Full Scale Vin Full Scale ADC V 8226 1X 105K 7 90K R228 OUTPUT 1 8 3 5 stereo 228 ADC c16 ou A 3 V ELEC gt 6 MIC IN 5 gt _ _3308 gt Y C MIC_PREAWP_49DB 81 3 NE5532D 1 EX L 27005 FILTER MIC POWER AGAIN SINCE POWER IS FED DIRECTLY TO HI GAIN OPAMP THROUGH 2 2K PULL UP Yo t voe cus m 1 sva CAE aan d Vec cies 398 PART 600 00558 21 SHEET TITLE PREAMP DATE 4 18 07 MER SHEET Figure 6 6 CDB47xxxS Sngle ended Mic Pre Amp enuey sasn xxx Fgao suonduos q pepu3 ejBurs Sxx pgdo radesssa 91607 50 19 6002 1 01 9 7 TVS To Prevent Overvoltage From wrong wall wart REMOVE 21 TO USE EXTERNAL SUPPLY gt 9V DC Input Nominal 9V LM25576 for 3 3V 3106 ELEC 100uF CLEAN UP POWER FROM WALL WART 9 S000HM0100WHZ 5V FOR OPAMPS 50 50 LOW E
26. 181 _38 181 238 12 1 181 18418 lt lt AIN_3A 181 _ 181 I lt 5A 8 1 lt _5 8 lt 286 81 lt _28 81 I 1 81 AINT4B 18 t _68 8 I lt 68 81 600 00357 71 REV SEET ME DAUGHTER BOARD CONNECTORS ME 10 15 08 PE au 12 Figure 6 15 CDB47xxD Differential Daughter Card Connectors gt THAT 215 IOC enuey sasn xxx Frgao ii suonduoseq penuad 0 radesssa JIDOT SMID 7 SnO 600 1uBu doo 9160 SPDIF RX SPDIF TX I OPT SELECTED I E n 2 gt I m en WI spor 18 Henn Ovec tm gt Nt 3 She COAX SELECTED ge 48 kai w i 5 55 na 125 OUT ES m Bias around 0 65V on input to give jc ee tm r gt output swing of 0 3V 2 3V EGER for 0 5V signal in
27. Power Connectors JIDOT SMAI enuey ses xxx pg qO suonduoseq 0 radesssa 91607 50 19 6002 1 DIFFERENTIAL ADC INPUT FILTERS TNT E TTE m Aman m s Jews Exp Ii Baths 515 em 872289 m TET Raa yzsk oae cs E BSAA 235K In Tgp AN ane x x ants ASR came s2 s 8 1 27 lows 55 M x 7 lt as Ane c lour yeu 2 T as ur yer x P x p g m Lm MEET nour yee ax aman ses m 5 S pas g dasi T s A 5 eso lt m am E ws p ana im lees i uid ix T anse RAANG ades sa S azor s an ix e 7 ilm CU gua spr iz yt 2 SMID ans m K Cana re marg
28. Remap Rb LFE Configure Tx DAO 3 SPDIF Optical J1 op 10 OK Cancel 11 gt Figure 4 9 Selecting S PDIF Outputs 125 Outputs using Device Properties Dialog DS886DB4 Copyright 2009 Cirrus Logic Inc 4 6 Running the ADC In DAC Out Example Application CDB47xxx User s Manual CIRRUS LOG IC 4 2 5 3 S Audio Input Output To output audio data the DSP 25 drag the Audio In block canvas choose input combination that includes 12 as shown in Figure 4 10 Draw wires from the Output Remap block to the Audio Out block for the desired mappings Audio Out Properties Enable Analog Output Enable DAO 0 3 Lb Configure Tx DAO 2 125 OutputLFE Configure Tx DAO 3 125 Remap 2 10 2 Figure 4 10 Selecting 125 Outputs using Device Properties Dialog 4 2 6 Changing Serial Control Protocol IC or SPI Flash Type CDB47xxx is designed to communicate using either 12 or SPI protocols In order to change the communication mode in the DSP Composer application go to the menu bar and select File Properties which brings up the Project Properties dialog Click on the Advanced button as illustrated in Figure 4 11 in order to set the Master Boot Flash type or put a specified I O pin into a High Z state The Flash Type pull down menu is used to select which Flash will be used for a Master Boot
29. T 19 85 T wou se1 T i RUNE L 3 Figure 6 4 CDB47xxxS Sngle ended Digital Audio Control Connectors Foe FS p FOLOCAIFOLOCALI FDLOCALI FDLOCAL FDLOCALI FDLOCALI Auxiliary H W amp Docs JIDOT SMID SHUNT 2P 15 29 1025 ASSY DWG 603 00358 21 PCB DWG 240 00358 71 SCH DWG 600 00358 21 SCREW PHILIPS 4 40THR PH 5 16 PMSSS 440 0031 PH 600 00358 71 REV A SHEET ME DIGITAL AUDIO CTRL CON suonduoseq pepu3 ejBurs Sxx pgao enuey sasn xxx Fgao radesssa 91607 50 19 6002 1 8 9 SPI FLASH EXT ur STSVr0328 65 4 S2F 3 FUSCE 246 13 51 FLASH_MISO SDA so FLASH HOLD JP1 16 14 01 Hie sce FLASH_SCP _CLK 3 51 vss 4 sox pp pause 56 25 ER p wv I2C EEPROM E a ATACBZBN SH 8 8 free 3 5 FLASH SCP C aa gR 15 51 FLASH_MISO7SDA ISDA GND Tow ADDRESS 1010 A2 A1 AO I2C ADDR OxAO Figure 6 5 CDB47xxxS Sngle ended Serial Memory PART F 600 00358 21 REV SHEET TITLE SERIAL FLASH enuey sasn xxx rgao UJ N x
30. This 20 pin connector provides pins for the following functions Serial control interface for configuring the DSP Reset line for the DSP Proprietary serial debug interface Jumper J28 can be used to bypass the on board MCU and enable use of JP1 While this header is configured for MCU control pins 2 3 the MCU will continue to drive all control lines to the CS470xx 6 2 4 Memory Figure 6 5 shows the schematic for the SPI Flash and 2 EEPROM devices The CDB47xxxS is designed with 32Mbits of SPI Flash and 512 kBit on board The serial control port for each device is routed to the daughtercard connector J2 6 2 5 Microphone Preamplifier Figure 6 6 shows the microphone preamplifier for the CDB47xxxS which has a 1 8 microphone input jack to allow direct connection to an encapsulated condenser microphone ECM Because the output of the ECM is so small a pre amplifier is needed to boost the signal to a line level voltage These specifications for the amplifier are noted on the schematic page These parameters should be considered when choosing the microphone to be connected to the CDB47xxxS Too large of a signal on the ADC input will result in distortion of the sampled signal It is important to note that although the amplifier circuit shown is non inverting the input to U19 B is the same polarity as the output from U19 C the output of an ECM is inherently inverted since it acts as an open collector device Therefore the mi
31. 10 illustrates this clocking configuration Note that the incoming DAI data is passed out of the CS470xx at the Fs of the crystal connected to the ASOC Like the S PDIF clocking configuration this allows the DAI to be rate matched to another MCLK in the system through an SRC This means that the DAO can be run at a constant Fs that is independent of the incoming DAI Fs This is useful in systems with a digital amplifier that requires a fixed Fs The CS470xx can masters its output clocks or slave to clocks from another source DS886DB4 Copyright 2009 Cirrus Logic Inc Other Useful Information CDB47xxx User s Manual _ IRRUS LOGIC 1 5 4 Clock and Data Flow for DAI Input with Matched DAO Fs MCLK 125 Clocks and Data CS470xx DAI FS DAI Header YYvv DAO PS 2 Clocks and Data DAO Header ADC DAC Figure 1 11 DAI Clocking with fixed output Fs a A A A A A A A e Line Level Analog Output Connectors The DAI clocking architecture is used when any serial audio data source is connected to the DAI header Figure 1 11 illustrates this clocking configuration Note that the incoming DAI data is synchronized to the DAO using a common MCLK This is a more traditional clocking architecture for serial audio data where the DAI Fs and the DAO Fs are
32. 12290 0402 Force Beollooder 292304 1 ur ew If P3 0 is low during reset bootloader will not col application code C127 No 44 T fios T Karwasmasor e 82222222323 127 use 101 0917 HEC un u 25 Jy E t 929 Sag 333 snzauversarwe Place U5 near LCD MCU RST C2CK _ hor 3 _ DAD0 HSO 15 41 8 2Y DA01 HS1 15 41 1 75 DA02 HS2 t BAR ay Lt DA03 XWTA HS3 13 41 ircuit 289 1 Reset Circuit Si Possim 8 Tam 2 2 en I 52543 n tnw 9 LCD E 1 I 8165 A Lie BH EXTR copes 1 20086 1121 Ier _ ___ E PART 600 00357 21 URS 80512340 04 2007 545 12 82 9 Figure 6 23 CDB47xxD Differential Microcontroller Card Schematic suonduoseq enuey sasn xxx Frgao radesssa 91607 50 19 6002 1 62 9 E sodes
33. 21 REV past WE USER INTERFACE 04 2007 12 12 Figure 6 12 CDB47xxxS Sngle ended Microcontroller Card User Interface 2 21 S IIDC enuey sasn xxx pgqO ii suonduoseq pepu3 ejBurs Sxx pgdo CDB47xxD Differential Schematic Descriptions CIRRI JS LOGIC CDB47xxx User s Manual LO C J 5 6 3 CDB47xxD Differential Schematic Descriptions 6 3 1 CDB47xxxD Diagram Figure 6 13 shows the CDB47xxxD block diagram 6 3 2 Daughterboard Connectors Figure 6 15 shows the schematic for the daughterboard connectors on the CDB47xxxD board See section Section 6 2 2 for description of circuitry 6 3 3 Digital Audio and Control Connectors Figure 6 16 shows the schematics for the digital audio and control connectors on the CDB47xxxD board See section Section 6 2 3 for description of circuitry 6 3 4 Memory Figure 6 17 shows the schematic for the Flash memory devices See section Section 6 2 4 for description of circuitry 6 3 5 Microphone Preamplifier Figure 6 18 shows the microphone preamplifier for the CDB47xxxD See section Section 6 2 5 for description of circuitry 6 3 6 Power Figure 6 19 shows the schematics for power on the CDB47xxxD board See section Section 6 2 6 for description of circuitry 6 3 7 Input Filters Figure 6 20 shows the input CDB47xxxD Each channel of the CS470xx is differential and input has its own inp
34. 3 4 External Control Header JP1 nennen 1 7 1 3 5 USB Connector J25 1 7 1 3 6 On Board Voltage Selection Headers 1 1 7 1 3 7 Digital Audio Input Source Multiplexer 1 1 8 1 3 8 CS470xx Audio System On a Chip 5 1 8 1 3 9 CEOS Mem 1 9 1 3 10 MCU Input Push Buttons S1 S4 and Rotary Encoder 55 1 9 1 3 11 MCU Output LCD LCD1 1 9 1 3 12 Memory U17 UTS and 014 ie eren enne teenie 1 9 1 4 CDB47xxx Daughter Card System 1 10 1 4 1 A dio Inputs uu u 52816454 5 u 1 12 1 4 1 1 Analog Line level Inputs 93 1 12 1 4 1 2 Digital Audio Inputs DAI 2 1 12 1 4 2 Audio Outputs from the 5470 DSP n 1 13 1 4 2 1 Analog Line level Outputs 43 1 13 1 4 2 2 Digital Audio Outputs 9 1 13 1 4 3 Control Header amp J2 u Uu uuu a aaa S aaa ganagana nnne nnns ea 1 13 1 4 4 User Input S1 52 uuu u eir ee toe tete 1 13 1 4 5 User LED Output D1and D2 n 1 13 1 5 Audio Clocking 2 1 14 1 5 1 Clock and Data Flow for ADC 222 n 1 14 1 5 2 Clock and Data Flow for S PDIF 1 15 1 5
35. 47K am RCJ 053 V WHT ANA Nat als RTA 2 LN 28 0 47K _ 03 220pF NOPOP cuo 22087 AINSA 32 E RCJ 052 V RED Anse 28 AW e 3 RB 54508 8 4 8 Tazopr elo cos 22087 AIN3B 131 D ADC Place AIN amp C close to J3 PUT FILTERS RCJ 053 V WHT RCJ 052 V RED RIS E RCJ 083 V WHT RCJ 052 V RED AN SB 16 MIC 4908 220pF AN AB 031 cus AN SB E RCJ 052 V RED BRAA AN SA pen 5 Ecos 8 s 1181 coc ance e 63 a cise amp coc amp Lese 506 600 00358 21 REV SINGLE ENDED ADC FILTERS 10 9 08 E ser Bor 12 11 9 Figure 6 8 CDB47xxxS Sngle ended ADC Filters 03 SNR AID AN 03 suonduoseq Sxx pgdo enuey sasn xxx Fgao radesssa 7 6002 1 9160 21 9 SINGLE ENDED DAC FILTERS RCJ 053 V WHT
36. Cord 1 CDB47xxxS DCxx CDB47xxxD DCxx USB Cable 1 D De Document Card explaining how to get the latest board software 1 CDB47xxxD DCxx Figure 1 1 and Figure 1 2 show the kit contents for the CDB47xxxS DCxx Single ended and CDB47xxxD DCxx Differential development boards respectively DS886DB4 Copyright 2009 Cirrus Logic Inc 1 1 ILL CDB47xxx Kit Contents CDB47xxx User s Manual SSS CIRRUS LOGIC O O O O sa z R gt Eris dk ke id 4 lt 076060050 4 LJ a 2 aa 44 Figure 1 2 CDB47xxxD DCxx Kit Contents DS886DB4 Copyright 2009 Cirrus Logic Inc 1 2 Requirements CDB47xxx User s Manual sm r m HEB SS EEE CIRRUS LOGIC 1 2 Requirements 1 2 1 PC Requirements Microsoft Windows XP Operating System with Service Pack 2 or higher USB 2 0 Support 1 2 2 Software Requirements e Cirrus Evaluation Software Package available from your local Cirrus Logic representative 1 2 3 Support Hardware Requirements Digital or Analog Audio Source for example DVD player PC with a digital audio card device Amplified Speakers for audio playback for example powered PC speakers AVR amp speakers 1 2 4 Cabling Requirements Digital Audio Inputs S PDIF optical cables RCA audio cables Connect to digital audio card audio analyzer or DVD player
37. DAO DAI s Co hha Mo cS gt Line Level Analog I Line Level Analog poc I 1201 22 iO LO ape 4 DAC LO P pon d U NE E s Line Level Analog io Input Connectors Output Connectors Figure 1 8 ADC Clocking The ADC clocking architecture is used when the internal ADCs are used as the only audio input that is S PDIF is disabled and there are no serial audio signals connected to DAI or DAO In this scenario the CS470xx has all audio clocking self contained Figure 1 8 illustrates this clocking configuration The clock fed to of the CS470xx is MCLK for the system and the ASOC masters clocks to DAC and ADC The user need only route in analog signals and route out the processed analog signals DS886DB4 Copyright 2009 Cirrus Logic Inc 1 14 Audio Clocking CDB47xxx User s Manual EE ee n CIRRUS LOGIC 1 5 2 Clock and Data Flow for S PDIF Input 25 Clocks and Data CS470xx DAO Header S PDIF Input pico Connector S PDIF gt i gt SRC DAI T pico e PS io gt 25 io ol O Line Level Analog I 0 pid gt 44 D
38. DXC MUTE wet DAL 187 OALTRGLK En Bi 132 C I R GREEN 282 530 os 0 3 DATA MUX SPDIF_ TX 135 RCJ 057 V ORG AI XWTA_COAX SPDIF o NG TOTXM2LF ND 125 OUT a 13 DAO_SCLK 3 DAO_TRCLK DAOD HSO DAO HS1 DA03 XMTA HS3 SNTALVCI2SAPWR 1 1 DECUS dem m LL C ous spor xti TPO Coax 07 v m p e 31 TE eg DAOS XMTA HSS gt _ 41 vec oxo 107 Tes 2 8 l ca TERMINATION TO GIVE 500 SWING OND TEST FONTS pour COUNTS ON 75 OHM RX I EXTERNAL DSP CONTROL EX S tm 3 A00 HS0 LED is on when MCU 0 Git OSP BSYZEE CS 03 30 Bay 1 Dm PSP DA02 HS2 8 rcs 9 39 53 13 controls DSP on rag 2 001 hos 3 5 238 PERS HOCD mae GREEN SCP MIS0 SDA L
39. The CS470xx analog inputs register full scale for an input amplitude of 2VRMS with this input filter 6 2 8 Output Filters Figure 6 9 shows the output filters for the CDB47xxxS Each output of the CS470xx has an output filter that consists of an AC coupling cap 22 uF a pull down resistor to prevent the output from floating when not connected to a load a series resistor 560 Q to provide a voltage drop when the muting transistor is enabled a filter cap 2200 pF and a mute transistor that will pull the output low when the mute control signal is enabled The series resistor is small enough that it does not affect the signal in normal operation assuming a load of at least 5 is connected to the analog output of the board 6 2 9 MCU Block Diagram Figure 6 10 shows the MCU block diagram for the CDB47xxxS 6 2 10 MCU Figure 6 10 shows the MCU for the CDB47xxxS The USB connector J25 is connected directly to the MCU U15 All PC control must pass through the MCU since it has an integrated USB interface Due to the way the MCU multiplexes its serial control pins and the multiplexing of the pin functions on the CS470xx there are two 12 bus isolators 012 and U13 to prevent slave Comm ports from receiving commands not intended for them The MCU has its own 32 Mbit SPI Flash U14 for storing MCU firmware The LCD control port is multiplexed with other functions on the board so a buffer U20 is used to isolate those log
40. center pin 1 3 4 External Control Header JP1 The control header has the following characteristics Connector Type 2x10 0 100 inch Shrouded Male Absolute Maximum Signal Level 3 6V Absolute Minimum Signal Level 0 3V This connector is the interface between the CS470xx DSP and an external host This connector is used to control the DSP when the on board MCU is bypassed 1 3 5 USB Connector J25 The control header has the following characteristics Connector Type USB Connector Absolute Maximum Signal Level 5V Absolute Minimum Signal Level 0 3V 1 3 6 On Board Voltage Selection Headers P1 P3 The on board voltage selection headers have the following characteristics Connector Type 1x2 0 100 inch Stake Header The CDB47xxx is designed to operate from a single DC power input The 9V power supply provided with the kit is connected to the DC power input jack J22 and is regulated down to the system voltages 5V 3 3V 1 8V The power selection headers should be installed when using the DC wall supply This is the default mode of operation and should not need to be changed for most applications It is possible to bypass the regulated power supplies for any of the voltages by removing the jumper from the appropriate power selection header and connecting an external voltage supply to pin 2 of that selection header Pin 1 of each header is marked with a triangle and the word REG Pin 2 of each header is labeled with th
41. the CDB47xxxS board The digital connector J2 carries the following signals Serial Control signals for host control of the CS470xx Serial Control signals from CS470xx to the SPI Flash and 126 EEPROM Serial Audio Data and Clocks going to the DAI of the CS470xx Serial Audio Data and Clocks coming from the DAO of the CS470xx The analog connector J3 carries the following signals 8 channels of line level analog from the CS470xx DACs can support differential or single ended signaling e 12 channels of line level analog to the CS470xx ADCs can support differential or single ended signaling The microphone input is routed to AIN 6A The AIN 6B channel can be used for mono line level input 6 2 3 Digital Audio and Control Connectors Figure 6 4 shows the schematics for the digital audio and control connectors on the CDB47xxxS board The audio input connectors consist of the following 1 RCA jack for coaxial S PDIF input e 1 optical jack for optical S PDIF input 12x10 header for serial audio data 125 6 1 Copyright 2009 Cirrus Logic Inc DS886DB4 IR 5 CDB47xxS Single Ended Schematic Descriptions IRRUS LOGIC CDB47xxx User s Manual LAS AJI j The audio output connectors consist of the following e 1 jack for coaxial S PDIF output 1 optical jack for S PDIF output 12x10 header for serial audio data 125 There is one control connector JP1
42. 0 49 6002 1 20 9 User Inte rface IR LCD LED 3 0 Encoder buttons MCU C8051F340 MCU flash code application use Bootloader Shored USBXpress C2 debug SPI flash USB 9VDC input 9 gt 3 3 regulator Control amp Interrupt Signals JP1 Customer Debug Port JP3 hdr for CRD CDB DSP boards P 600 00357 21 REV FST MCU BLOCK DIAGRAM 418707 ser 108 12 Figure 6 22 CDB47xxD Differential Microcontroller Card Interface enuey sasn xxx pg qO UJ N 5 g 5 D 0 3 D 5 o radesssa 7 80 10 eooz 1uBu doo 9160 120 muxing P 32 MBit SPI FLASH JIDOT 59112
43. 009 Cirrus Logic Inc DS886DB4 Audio Clocking CIRRUS LOGIC CDB47xxx User s Manual 2p MAU LANIN 1 5 Audio Clocking Clocking architecture is one of the most important aspects of an audio system This can also be one ofthe most complicated parts of a system design to insure that clocking is valid and stable for all scenarios This is one of the major advantages of the CS470xx Audio System On a Chip ASOC Because of the integrated ADC and DAC along with the integrated SRCs The CS470xx makes audio clocking very simple For analog only systems the clocking architecture is as simple as a crystal feeding the CS470xx Traditionally the input and output clock domains of the DSP needed to be synchronous when delivering audio data in an isochronous fashion constant bitrate delivery even if the input output domains operate at different frequencies e g 48 kHz input 96 kHz output Systems utilizing serial audio data 12 delivery would thus use isochronous delivery The CS470xx s integrated SRCs remove this requirement because the CS470xx can rate match the input DAI Fs to any Fs on the output side DAO The examples below show configurations that support an Fs that is synchronized between DAI and DAO as well as an output Fs that is independent of the input Fs 1 5 1 Clock and Data Flow for ADC Input CS470xx
44. 3 Clock and Data Flow for DAI Input with Fixed Output 1 16 DS886DB4 Copyright 2009 Cirrus Logic 1 CDB47xxx User s Manual CIRRUS LO 1 5 4 Clock and Data Flow for DAI Input with Matched DAO Fs 1 17 1 6 Other Useful 1 17 1 6 1 Web SII8s 1 17 1 6 2 DSP Informatika edu 1 17 1 6 3 Cu k iieri ette 1 18 1 6 4 DSP Software Utility Information 1 18 Chapter 2 Introduction to CDB47xxx Kit 2 1 2 1 Introducing the CDB47xxx Customer Development 2 1 2 2 Identifying CDB47xxx 2 2 2 2 1 0 5 2 2 2 2 1 1 CDB47xxxS Board Single Ended Components 2 4 2 2 2 CDB47XXXD BO iet e e taber 2 4 2 2 2 1 CDB47xxxD Board Differential 2 6 2 2 3 CDB47xxx DCxx Daughter Card sse senem 2 6 2 2 3 1 CDB47xxx DC48 Daughter Card Components
45. 6 CDB47xxx DC28 Daughter Card Block Diagram 1 11 Figure 1 7 CDB47xxx DC24 Daughter Card Block Diagram I 1 12 Figure 1 8 ADO Clocklhg d dece add 1 14 Figure 1 9 S PDIF Clocking 1 15 Figure 1 10 DAI Clocking with fixed output Fs 1 16 Figure 1 11 DAI Clocking with fixed output Fs nennen nnns 1 17 Figure 2 1 CDB47xxx System Block Diagram 2 1 Figure 2 2 CDB47xxxS Single ended Top View sse 2 3 Figure 2 3 CDB47xxxD Top View Differential l nennen nnne 2 5 Figure 2 4 CDB47xxx DC48 Daughter Card 2 7 Figure 3 1 CDB47xxx Board with CDB47xxxD or S DC xx Daughter Card Attached 3 2 Figure 4 1 ADC In DAC Out Example 4 2 Figure 4 2 CDB47xxx System Properties 4 2 Figure 4 3 Selecting Audio In Source using Device Properties Dialog 4 3 Figure 4 4 ADC2 Device Properties 4 3 Figure 4 5 Selecting ADC2 input Terminals using Device Properties Dialog 4 4 Figure 4 6 Selecting Multi Channel 125 Input 4 4 Figure 4 7 Input Remap Device Pr
46. 7500 8 PI Channels 12S In Y 125 Out Analog Serial Control Connector S PDIF LED x 2 CS47028 Channels ie S PDIF Out 2A AIN 6B BUTTON Current Current Current Current Digital Measure Measure Measure Measure Point Point Point Point Connector 43 3VD 1 8VD 3 3 1 8 POWER CONNECTOR ii Figure 1 6 CDB47xxx DC28 Daughter Card Block Diagram Copyright 2009 Cirrus Logic Inc DS886DB4 xrrYa CDB47xxx Daughter Card System Description w ms CDB47xxx User s Manual Analog DB47XXX_DC24 Connector DC ID 5 1 AOUT_4 4 15 Channels Y 125 In Analog 12S Out Connector Serial Control 547024 10 ADC LED x2 Channels INPUTS S PDIF Out 1 gt 2A AIN 6B SWITCH BUTTON Current Current Current Current Digital Measure Measure Measure Measure Point Point Point Point Connector 3 3VD 1 8 3 3VA 1 8 POWER CONNECTOR Figure 1 7 CDB47xxx DC24 Daughter Card Block Diagram 1 4 1 Audio Inputs 1 4 1 1 Analog Line level Inputs J3 Analog line level in
47. AC gt 2 e Mi 1 i Line Level Analog Output Connectors Figure 1 9 S PDIF Clocking The S PDIF clocking architecture is used when any S PDIF RX is used as an audio source whether from the optical RX coaxial RX or brought in on the DAI header Figure 1 9 illustrates this clocking configuration The incoming S PDIF stream is always rate matched to another MCLK in the system through an SRC This means that the DAO can be run at a constant Fs that is independent of the incoming S PDIF Fs This is useful in systems with digital amplifiers and wireless audio transmitter modules that requires a fixed Fs The CS470xx can master its output clocks or slave to clocks from another source Copyright 2009 Cirrus Logic Inc DS886DB4 07 f IRRUS LOGIC Audio Clocking CDB47xxx User s Manual 1 5 3 Clock and Data Flow for DAI Input with Fixed Output Fs DAI Header 125 Clocks and Data CS470xx s SRC DAI FS e DAO FS 125 Clocks and Data DAO Header lt Y DAC Figure 1 10 DAI Clocking with fixed output Fs Line Level Analog Output Connectors The DAI clocking architecture is used when any serial audio data source is connected to the DAI header Figure 1
48. ASH MOSI lt FLASH_SCP_CLK 51 t53 FLASH CS 4 4 18 2 gt 81 58 L 1 AN AIN 68 FLASH SCP Figure 6 3 CDB47xxxS Sngle ended Daughter Card Connectors 9 tel 191 tl 18 1 tal t8 ta 181 ta tB tel 8 600 00358 21 REV A eer DAUGHTER BOARD CONNECTORS SMID DID suonduoseq pepu3 ejBurs Sxx pgao enuey sasn xxx Fgao radesssa 7 80 10 eooz 1uBu doo 9160 2 9 SPDIF RX OPT SELECTED _ _ IN SPDIF SPOIF OPT 41 ES ES i i XIR pru wv GREEN 717 2 soror 2129 rol pour 5 an r gt i 530 n J4 057 5 f e I E GREEN oss SPOIF COAX 14001 SPOF COAX SEL 7 50 RIS 3 10K MAX42156SA vec ijwe SPDIF_RX_COAX 41 VEE MC Rie CU 1 Bias around 0 65V on input to give output swing of 0 3V 2 3V for 0 5V signal input 48
49. BACK PATH E PROVIDE VOLTAGE SENSE WHEN RUNNING DSP FROM EXTERNAL POWER 3 i DE cog 6BpF wR 04706 i NEED GOOD COPPER POUR ON BOARD FOR HEAT SINK EX 18V 1 5A gus 33k LM25575WH NOPB 0 est HE posar 4 PRE 13 ev isa 7215786 s 739 HE BSSTAW15 F cui alens i 3 mus r uvas 2 24 RAMP Rut EXT PGND po PAD SKS 198 VECOMP Un 1 8V enabled when SD 1 225V ELEC XR 00 SENSE 18V 3 IRE RE 470 687 fov sov NOPOP FEEDBACK TO PROVIDE VOLTAGE SENSE WHEN RUNNING DSP FROM EXTERNAL POWER USVCAP l Lx REDUCE ESR BY PUTTING CAPS IN PARALLEL TO REDUCE RIPPLE EET 2 EXCML45ASTOR TANT INDICATORS rr es lus gu w S m Iw ED BLUE GREEN YELLOW 544 2 WlaWl 2 an 25C3326 A TSL F T PART l 600 00357 Z1 REV SET TTE CONNECTORS_POWER S 4 18 07 F 7 12 Figure 6 19 CDB47xxxD Differential
50. Board Differential Components CIRRUS LOGIC Identifying CDB47xxx Components CDB47xxx User s Manual The circled numbers found in Figure 2 3 refer to the CDB47xxxD board differential components in the following list D 9 23 k 9V Power Optical S PDIF Out Coax S PDIF Out Optical S PDIF In Coax S PDIF In 5V Header Line Level Analog Outputs CDB47xxD DC48 Daughter Card Connectors Mic Input Differential Line Level Inputs MCU Rotary Encoder MCU Buttons SPI Flash EEPROM LCD 16 17 18 19 20 21 22 23 24 25 26 DSP DAO Header IR Receiver Board Reset MCU Programming Header MCU Control Bypass Header USB Connector DSP External Control Header DSP DAI Header 1 8V Header Power LEDs 4 3 3 Header 2 2 3 CDB47xxx DCxx Daughter Card The layout for the daughter card shipped with the CDB47xxx is the same regardless of which type of main board differential or single ended the customer orders The daughter card can be ordered populated with either the CS47048 Cs47028 or CS47024 DSP Figure 2 4 shows the top side of the CDB47xxx DC48 daughter card The accompanying legend identifies the main components of the board DS886DB4 Copyright 2009 Cirrus Logic Inc 2 6 Identifying CDB47xxx Components CDB47xxx User s Manual CIRRUS LOGIC L 7 T d ake 99
51. C outputs are routed directly to the DAC filter circuitry on the CDB47xxx main board The ADC inputs are routed directly to the ADC filter circuitry on the CDB47xxx main board The Daughtercard ID register U2 is used to identify which CS470xx chip is populated on the board This register is read by the MCU or the PC in order to determine which DSP firmware is appropriate for the SOC DS886DB4 Copyright 2009 Cirrus Logic Inc 6 30 radesssa 91607 50 19 6002 1 16 9 DESCRIPTION 9 0ATE INTIAL DESIGN BILL DIEHL 11 03 08 CDB47XXX_DC48 Analog SHIFT REG DAC OUTPUTS GPIO 125 In 12 Out Serial Control S PDIF In LED x 2 CS47xxx S PDIF Out ET BUTTON Current Current Current Current Nm Pont Pont 3 3VD 1 8VD 3 3 1 8 POWER CONNECTOR Analog Connector ADC INPUTS BILL DEHL 1 03 08 600 00359 21 REV ser CDB47XXX DC48 Z SET mE BLOCK DIAGRAM E 10 13 08 1o 2 Figure 6 25 CDB47xxx DC48 Daughter Block Diagram enuey sasn xxx rgao g 00 g O c 5
52. CirrusDSP micro condenser projects sample flash_image xml Build the Flash image Open the Console window navigate to the example folder containing the file flash_image xml Run the file create _ flash _image bat which contains the statement flasher micro exe flash image xml which builds the Flash image Open flash image txt to see the new Flash image data 5 1 3 2 Programming the Flash Image into the Flash Device Cirrus provides the usb flash exe utility with the CDB47xxx Evaluation Kit and is used to program memory storage devices Run program mcu spi flash bat to program flash image txt into the microcontroller s external SPI Flash The program mcu spi flash bat file calls the usb flash exe utility to program the flash image txt into the SPI Flash Device DS886DB4 SS Copyright 2009 Cirrus Logic Inc 5 4 ll 1 SS SSS 3 ma CDB47xxx User s Manual RRUS LOGIC Chapter 6 CDB47xxx Schematics 6 1 Introduction The schematics included in this document are the original Revision A schematics of the CDB47xxx and reflects the board as it was manufactured Newer schematics may be available that incorporate feature additions or corrections and may not match Rev A hardware 6 2 CDB47xxS Single Ended Schematic Descriptions 6 2 1 CDB47xxxS Block Diagram Figure 6 1 shows the CDB47xxxS block diagram 6 2 2 Daughterboard Connectors Figure 6 3 shows the schematic for the daughterboard connectors on
53. D IN SUCH A MANNER IF THE CUSTOMER OR CUSTOMER S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITI CAL APPLICATIONS CUSTOMER AGREES BY SUCH USE TO FULLY INDEMNIFY CIRRUS ITS OFFICERS DIRECTORS EMPLOYEES DISTRIB UTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY INCLUDING ATTORNEYS FEES AND COSTS THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES Cirrus Logic Cirrus the Cirrus Logic logo designs and DSP Composer are trademarks of Cirrus Logic Inc All other brand and product names in this doc ument may be trademarks or service marks of their respective owners Microsoft Windows XP are registered trademarks of Microsoft Corporation Motorola and SPI are registered trademarks of Motorola Inc is a trademark of Philips Semiconductor Corp DS886DB4 Copyright 2009 Cirrus Logic 1 CDB47xxx User s Manual Contents CONTCINS iii Rex bee NOE NU v Tables O Rod vii Chapter 1 Kit Contents and Requirements 1 1 1 1 CDB47xxx Kit 1 1 1 2 Requirements tok ter 1 3 1 21 REQUIFEMEMIS 4 cea 1 3 1 2 2 Software Requirements
54. Digital Audio Output S PDIF Optical cable RCA audio cable Connect to digital audio card audio analyzer or AVR Analog Audio Inputs 1 8 stereo plug microphone cable Connect microphone to ADC RCA audio cables CDB47xxxS only 1 8 stereo plug differential cable CDB47xxxD only Analog Audio Outputs RCA audio cables Connect CDB47xxx line level outputs to powered speakers Copyright 2009 Cirrus Logic Inc DS886DB4 S SS CDB47xxx Main Board System Description CDB47xxx User s Manual SS CIRRUS LOGIC 1 3 CDB47xxx Main Board System Description A detailed block diagram of the CDB47xxxS Development Board is shown in Figure 1 3 The block diagram of the CDB47xxxD Development Board is shown in Figure 1 4 The sections that follow provide a detailed description of each block SPDIF IN SPDIF IN 5 I COAX OPTICAL 12S IN HDR DB47XXX Header will be available to probe bring in 12 signals 20 Pin HDR 1 gt Standard 20 Pin Debug Header Serial Control amp Debug D Mic Buffer Digital Pre Amp DSP Daught
55. ERS 10 MCU BLOCK DIAGRAM 11 MCU 80517340 12 USER INTERFACE Figure 6 2 CDB47xxS Sngle ended Board Schematic Index 6 5 Copyright 2009 Cirrus Logic Inc DS886DB4 radesssa 7 80 10 eooz 1uBu doo 9160 9 9 433VA E HOR40x2 8MM ML 1 lt gt ipe 181 AQUT i 2 E aout 2 AQUT 34 191 AOUT 4 E A0UT A 111 aout s CH 7 33 C 181 4001 5 2 3 DSP RESET DALLRCLK C Hl xau 2 C3 ul gt 6 E aout I ts AQUT 2 gt sour 0804 am gt AQUT 8 18 AW A 22 a t8 L AN 8 gt gt lt Joais sPoIr_RX 41 tB Cot 1 81 1 7 DAO0 HSO tm gt gt gt C 0A03 MTA NSS 4 111 S AN 54 sce gt Stags tB ansat scP MISG SDA lt gt tum ta C 1 7 aan 5 AIN 28 08 85 7 05 4 1 18 _ T5 FLASH MISO SDA C gt m 18 AN 38 t8 FL
56. Figure 4 4 Ain 2a and Ain 2b are active If the selection was Ain 3A instead the terminals would say Ain 3a and Ain 3b On the CDB47xxx board the microphone input is connected to terminal 6A 4 3 Copyright 2009 Cirrus Logic Inc DS886DB4 Running the ADC In DAC Out Example Application CIRRUS LOGIC CDB47xxx User s Manual 4 2 2 2 Audio In via S PDIF To deliver digital audio data to the DSP via the S PDIF receiver built into the CS47048 and CS47028 devices drag the Audio In block to the workspace and select an input option that includes S PDIF as shown in Figure 4 5 9 Audio In Properties x Input Select SPDIF Connect 125 signal before clicking GO ADC2 Ch3 4 Input Sel I2S SPDIF Data format 125 24 bit Figure 4 5 Selecting ADC2 input Terminals using Device Properties Dialog 4 2 2 3 PS Audio Input To deliver data to the DSP via 125 drag the Audio In block to the canvas and choose an input combination that includes 125 as shown in Figure 4 6 As stated in the dialog box you must connect 12 Signal before pressing GO Audio In Properties Input Select Multi Channel 125 Connect 25 signal before clicking GO ADC2 Ch3 4 Input Sel AIN_24 28 I2S SPDIF Data format FS Figure 4 6 Selecting Multi Channel 125 Input 4 2 3 Input C
57. In DSP Composer go to File Open and open C CirrusDSP CS47xxx projects adc_in_dacout cpa Note If the pop up window Project Out of Date appears click on Update Devices Press the Go button Provide analog audio input signals to inputs AIN_1A J14 and AIN_1B J15 of the CDB47xxx Full scale is approximately 4 3Vrms for a differential signal and approximately 2 15Vrms for single ended 4 You should now hear audio from the speakers SS 3 3 Copyright 2009 Cirrus Logic Inc DS886DB4 ii Installation Setup and Running First Application CDB47xxx User s Manual DS886DB4 Copyright 2009 Cirrus Logic Inc 3 4 Introduction CDB47xxx User s Manual IRRUS LOGIC Chapter 4 Programming the CDB47xxx Board 4 1 Introduction With the exception of the power selection jumpers the CDB47xxx is configured exclusively through software The DSP software is a graphical user interface GUI that is used to program the CS470xx DSP and to configure the CDB47xxx This chapter provides basic instructions for using the GUI to control the CDB47xxx Detailed information on using the DSP Composer can be found in the DSP Composer User s Manual Your local Cirrus Logic representative can assist you in obtaining both the DSP Composer software and the User s Manual for the software 4 2 Running the ADC In DAC Out Example Application 4 1 Follow the instructions in Chapter 3 in order to install the USB dri
58. Input Connectors Optical S PDIF Input Connector Coaxial S PDIF Input Connector DAI Header Audio output data from the ASOC can be sent to the following destinations Line Level Analog Audio Output Connectors Optical S PDIF Output Connector Coaxial S PDIF Input Connector DAO Header The CS470xx can be booted from external serial Flash for custom applications in which a host MCU is not desired The CDB47xxx also allows the PC to act as a host to boot and configure the DSP through the GUI software for real time configuration of the audio processing DS886DB4 Copyright 2009 Cirrus Logic Inc 1 8 SS CDB47xxx Main Board System Description CDB47xxx User s Manual CIRRUS LOGIC 1 3 9 C8051 MCU The C8051 U15 is a USB slave controller and general purpose MCU used to control the CDB47xxx Board in stand alone applications and also used to interface to the PC through the USB port DSP Composer Standalone applications can be as simple as using the MCU to configure the inputs on the board to feed the DSP and provide a power on reset POR to the DSP But standalone applications can also take advantage of the LCD display buttons and rotary encoder to provide a user interface that is managed by the C8051 When DSP Composer is needed to perform real time application development on the CS470xx the USB port should be used to connect the CDB47xxx Board to a PC that has DSP Composer installed 1 3 10 MCU Inpu
59. MCU Block Diagram 2 21 roodo te 6 16 6 3 10 pn 6 17 6 3 11 User Interface Devices U enne nennen ennt nennen nenas 6 17 6 4 CDB47xxx DC48 Daughter Card Schematic 6 30 6 4 1 CDB47xxx DC48 Block 6 30 6 4 2 CDB47xxx DC48 Schematic 6 30 6 5 Obtaining Schematic Updates 6 33 Chapter 7 Troubleshooting J 7 1 7 1 Troubleshooting 7 1 Power LEDS vis cece 7 1 7 1 2 Board not Recognized by PC eene nentes nnne enne 7 1 71 23 Audio Is not Heard u qusa 7 2 REVISION History 2 7 2 Figures Figure 1 1 CDB47xxxS DOxx Kit 1 2 Figure 1 2 CDB47xxxD DOxx Kit Contents 1 2 Figure 1 3 CDB47xxxS Board Block 1 4 Figure 1 4 CDB47xxxD Board Block Diagram 1 5 DS886DB4 Copyright 2009 Cirrus Logic 1 v CDB47xxx User s Manual IG Figure 1 5 CDB47xxx DC48 Daughter Card Block Diagram 2 1 10 Figure 1
60. Master Slave Boot Operations CDB47xxx User s Manual CIRRUS LOGIC li The two JP1 checkboxes allow the user to do one of the following 4 JP1 Pin 12 Check this box to three state JP1 Pin 12 signal mute which leaves the audio outputs unmuted on the CDB47xxx This actions allows the user to install an external mute control such as a DSP GPO JP1 Pin 16 Check this box to three state JP1 Pin 16 signal flash hold which releases the DSP SPI Flash U17 Check both boxes Leave both boxes unchecked Default Allows the microcontroller to control both JP1 Pin 12 and JP1 Pin 16 as necessary Finally Click the Go button and DSP Composer will compile the project into a binary image deploy the image to the Flash device and initiate a Master Boot of the CS470xx DSP on the CDB47xxx Board 5 1 2 Using Micro Condenser to Create and Load a Flash Image for Slave Mode Operations Cirrus Logic s Micro Condenser application allows the user to program the MCU SPI Flash U14 through the USB port Once the Flash device is programmed the user is able to control the CS470xx DSP in Slave mode while disconnected from the PC The user can then load and compile up to 20 DSP Composer projects with up to 20 snapshots for each project into the microcontroller Flash The user can then run any of the loaded projects snapshots onto the DSP running in Slave mode and control the operation of the firmware using the CDB47xxx on board navigation buttons and d
61. PLL inside the CS470xx for the core DSP clocks and for all internal audio clocks The DSP has a dedicated reset line DSP_RESET that must be driven by the host to initialize the CS470xx s communication mode and initiate the first boot sequence This signal is independent of any other reset on the board and can be used to sequence device power up The host communication protocol of the DSP is determined by the state of the HS 3 0 pins at the rising edge of reset The serial host control SCP_CLK SCP_MOSI SCP_MISO SDA SCP_CS SCP_IRQ SCP1 BSY is used by the host controller to boot and control the DSP Note that the pull up resistors on the SCP_IRQ and SCP_BSY pins are required for both SPI and control since these are open drain pins The pull ups on the SCP and SC1_SDA pins are required only for 12 operation The DSP has a debug port DBDA DBCK that allows a developer to debug the DSP during normal operation This is a slave port that can be connected to 12 master or it can be simply terminated with pull up resistors The DAI3 digital audio input pin of the CS470xx is driven by a multiplexer on the CDB47xxx main board that chooses between optical S PDIF RX coaxial S PDIF RX and DAI3 from the DAI header on the main board The remaining DAI pins are driven directly by the DAI header on the main board The DAO port of the CS470xx is driven directly to the DAO header on the main CDB47xxx Board The DA
62. SR TANTALUM FILTER 5VA SWITCHING TRANSIENTS FROM 5VD 2 less Tin us Tu _ 5 sva ur e ost Tes Eo UN OUT 5 Gk x ur Lx L r a Tar DANT 45V REG VIN 15 28 5 ale he See E ROUTE SVD BACK FROM LOAD NEED GOOD COPPER POUR ON BOARD FOR HEAT SINK 33VA 5 3 3v_REG SIOHMBTOOMHZ ES us cis ce LM25575MH NOP 3 0 022uF ELEC iw a an n sw HE A E rpe AAA ur S vB M 55 FB 91 coup ganar AALS n 7 853 20K 18 10 1 RT Pono PAD H 108 X R 06 NEED GOOD POUR BOARD FOR HEAT SINK Jin Sc Es A our our L3 wv SENSE_3 3V 3 s 1 EXCMLASASTON lg lew NOPOP FEEDBACK PATH TO PROVIDE VOLTAGE SENSE WHEN RUNNING DSP FROM EXTERNAL POWER 18V 1 5A P TI Hi 1 8V enabled when SD 1 225V m x 10v V IRE RE sync 50 BST 4 282 0 022UF 13 nee ki us 5 pr B330A 13 F 5
63. The checkbox when checked puts the corresponding pin into the high impedance state See Section 5 1 1 for more details 4 7 Copyright 2009 Cirrus Logic Inc DS886DB4 Running the ADC In DAC Out Example Application CDB47xxx User s Manual CIRRUS LOGIC Project Properties PRAM size Codebase Sample Rate KHz 48 Control poll rate 110 Advanced properties Board boot mode comm mode Flash Type Slave SPI Coefficient Ramp Time Constant s JP1 12 HiZ mute 0 001 JP1 16 HiZlflash_hold Clip Hold Ti Compile message level C Use customer board control header Figure 4 11 CDB47xxx Communication Modes Flash 88 DS886DB4 Copyright 2009 Cirrus Logic Inc Programming Serial Flash Device for Master Slave Boot Operations CDB47xxx User s Manual CIRRUS LOGIC Chapter 5 SSS CIRRUS Using DSP Composer or Micro Condenser Application to Create and Load a Flash Image 5 1 Programming Serial Flash Device for Master or Slave Boot Operations 5 1 1 5 1 The CDB47xxx is populated with 32 Mbit SPI U17 512 kbit 2 016 and 32 Mbit SPI 014 Flash devices The SPI Flash 017 and 2 Flash U16 devices can be used to store custom DSP firmware or run time firmware configuration files The SPI Flash U14 device is used to store microcontro
64. US LOGIC CDB47xxx User s Manual f 2 2 1 1 CDB47xxxS Board Single Ended Components The circled numbers found in Figure 2 2 refer to the CDB47xxxS board single ended components in the following list 1 49V Power In Optical S PDIF Out Coax S PDIF Out Optical S PDIF In Coax S PDIF In 5 Header Line Level Analog Outputs CDB47xxS DC48 Daughter Card Connectors Mac Input o 9 N i Single Ended Line Level Inputs MCU Rotary Encoder MCU Buttons SPI Flash i m 2 EEPROM LCD 16 DSP DAO Header 17 IR Receiver 18 Board Reset k 19 MCU Programming Header 20 MCU Control Bypass Header 21 USB Connector 22 DSP External Control Header 23 DSP DAI Header 24 1 8V Header 25 Power LEDs 4 26 3 3V Header 2 2 2 CDB47xxxD Board Figure 2 3 shows the top side of the CDB47xxxD Board Section 2 2 2 1 contains the legend for the reference points called out in red in Figure 2 3 DS886DB4 Copyright 2009 Cirrus Logic Inc 2 4 radaessesa 91607 8 6002 1 6 0 26 22 21 20 19 18 2 z Figure 2 3 CDB47xxxD Differential View T e 10 5 4 8 xxx Frgao 5 gt lt 5 UJ N x x x 3 5 5 2 2 2 1 CDB47xxxD
65. abled then the two drop down lists at the bottom of the dialog box allow for DAO2 and DAOS to be configured to output data in either 125 or S PDIF format 4 2 5 1 Audio Out via DAC To deliver data from the DSP via the Analog Out DAC outputs drag the Audio Out block to the workspace and check Enable Analog output See Figure 4 8 Notice that the terminal labels Aout_1 match those of the RCA output jacks on the board Draw wires from the Remap Audio Output block to the DAC block for the desired mappings Audio Out Properties L R Enable Analog Output i Enable DAO 0 3 hs I Qutput Lb Configure Tx DAD 2 125 Remap Rb LFE Configure Tx DAO 3 SPDIF Optical J1 _ e 9 Figure 4 8 Selecting DAC Outputs Only using Device Properties Dialog 4 2 5 2 Audio Out via S PDIF Out To output audio data from the DSP via a S PDIF output drag the Audio Out block to the workspace check the Enable DAO 0 3 checkbox and choose SPDIF Optical J1 from the DAO3 combo box See Figure 4 9 Note that the terminals for DAO3 are replaced by the spdif L and spdif R terminals Draw wires from the Remap Audio Out put block to the Audio Out block for the desired mappings DAO2 can also be configured to be a S PDIF output Audio Out Properties L c R Enable Analog Output lt Enable DAO 0 3 Output Lb gt Configure Tx DAO 2 125
66. crophone signal driven to the CS470xx should be considered an inverted signal for processing purposes 6 2 6 Power Figure 6 7 shows the schematics for power on the CDB47xxxS board The DC input connector 422 for the CDB47xxxS can accept 9 to 12 VDC and the power supply should be capable of supplying at least 2 amps of current The 4 voltage regulators on the CDB47xxxS generate the 1 8V 3 3V 5V and 5V necessary for powering all of the ICs on the board Note that the 5V 3 3V and 1 8V regulators run directly off the DC input supply connected to the CDB47xxxS Also notice that the 1 8 V regulator is dependent upon 3 3V power to enable it not necessarily the 3 3 V regulator The 3 power jumpers P1 P3 are used to choose between the on board regulators and an external source for 5V 3 3V and 1 8V This is a feature intended only for special applications so these jumpers should be left populated for normal operation 6 2 7 Input Filters Figure 6 8 shows the input CDB47xxxS Each input of the CS470xx has its own input filter that consists of a current limiter AC coupling capacitor 10 uF and an anti aliasing capacitor 2200 pF which is not DS886DB4 Copyright 2009 Cirrus Logic Inc 6 2 CDB47xxS Single Ended Schematic Descriptions CDB47xxx User s Manual Ss CIRRUS LOGIC populated The current limiter is scaled to make the CDB47xxxS capable of accepting analog signals of up to 2 VRMS
67. ding use of this information as the basis for manufacture or sale of any items or for infringement of patents or other rights of third parties This document is the property of Cirrus and by furnishing this information Cirrus grants no license express or implied under any patents mask work rights copyrights trademarks trade secrets or other intellectual property rights Cirrus owns the copy tights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus This consent does not extend to other copying such as copying for general distribution advertising or promotional purposes or for creating any work for resale CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS CIRRUS PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WAR RANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY AUTOMOTIVE SAFETY OR SECURITY DEVICES LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY EXPRESS STATUTORY OR IMPLIED INCLUDING THE IM PLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USE
68. e Master protocol option load the Flash image to the DSP Copyright 2009 Cirrus Logic Inc DS886DB4 Programming Serial Flash Device Master Slave Boot Operations C IRRUS LOGIC CDB47xxx User s Manual Project Properties PRAM size 8 Codebase Sample Rate KHz 48 Control poll rate 10 Board boot mode comm mode Slave SPl Slave SPI Slave l2C Master 120 Master SPI 2 Master SPI Mode 3 Compile message level none v C Use customer board control header JP1 customer board configuration batch file Figure 5 1 Project Properties Dialog Showing the Selection of the 2 Protocol for Loading the Flash Image 3 Click the Advanced button and choose one the supported Flash types that will be receiving the Flash image download When downloading a Flash image to a customer board customers should consult their schematics to determine the Flash type to select If downloading a Flash image to the CDB47xxx Board choose the appropriate I C or SPI Flash device noted in the Flash Type pull down menu Advanced properties Flash J JP1 12 HiZ mute 371 16 HiZ flash_hold Figure 5 2 Selecting Flash the Advanced Properties Dialog DS886DB4 Copyright 2009 Cirrus Logic Inc 5 2 Programming Serial Flash Device for
69. e input of the Audio Out block 4 2 4 Output Channel Remap All designs regardless of the output configuration chosen must include the Output Remap block which maps the internal channels of the DSP to the output channels Drag the Output Remap block to the workspace The Output Remap block has no Device Properties to edit Use the Composer Wire mode Ctrl and draw wires from the output terminals of the Output Remap block to the desired terminals of the Audio Output block discussed in the next section Selecting the Audio Output Configuration 4 2 5 Selecting the Audio Output Configuration Configure the audio outputs to the DSP by dragging and dropping the Audio Out block onto the workspace The dialog box shown in Figure 4 8 appears Choose from one of the supported output combinations as described in the subsections Section 4 2 5 1 to Section 4 2 5 3 DAC is selected by default The input configuration may be changed later by right clicking on the Audio Out block and selecting Device Properties The Device Properties dialog box allows the user to configure one or more of the following DAC 125 S PDIF Out 4 5 Copyright 2009 Cirrus Logic Inc DS886DB4 Running the ADC In DAC Out Example Application CDB47xxx User s Manual gt CIRRUS LOGIC Note that the Device Properties dialog box allows the user to select analog DAC outputs only digital outputs only or a mixture of the two If digital outputs are en
70. e regulator ouput to reach potentially damaging voltages Ensure that the D14 blue D7 green D8 yellow and D9 red power indicator LEDs on the CDB47xxx illuminate when power is applied to the board Copyright 2009 Cirrus Logic Inc DS886DB4 Installation Setup and Running First Application CIRRUS LOGIC CDB47xxx User s Manual 5 Make Audio Input connections to the CDB47xxx Board Connect one end of the digital audio S PDIF optical cable to J1 on the CDB47xxx Board Connect the other end of the optical cable to the optical output on the back of a DVD player or other digital audio source 6 Make Audio Output connections from the CDB47xxx Board From the main Analog Line level Outputs on the CDB47xxx connect powered speakers to J5 and J10 using RCA audio cables 6720 0 2 gt 4 2 29 L M 9 Figure 3 1 CDB47xxx Board with CDB47xxxD or S DC xx Daughter Card Attached 3 1 3 Connecting to a PC Follow these steps to connect the 1 Connect the B end of the USB cable to P1 on the USB Master daughter card 2 Connect the A end of the USB Cable to a USB 2 0 port on a notebook or PC running Windows operating system The Windows operating system should recognize that a new device has been attached and display a notice saying Found New Hardware Note In the Windows Device Manager the CDB47xxx appears as a Universal Serial Bus Controller cal
71. e voltage required for that pin 5V 3 3V or 1 8V Copyright 2009 Cirrus Logic Inc DS886DB4 CDB47xxx Board System Description C IRRU S LOGIC CDB47xxx User s Manual EWS N 1 3 7 Digital Audio Input Source Multiplexer U1 The audio input source multiplexer has the following characteristics Source 1 Optical S PDIF Input Source 2 Coaxial S PDIF Input Source 3 Digital Audio Input DAI Header This multiplexer is used to select which audio source feeds the CS470xx pin When the CS470xx has DAIS configured as a S PDIF receiver either Source 1 or Source 2 can be selected by the MCU When DAIS is configured as a standard 125 input Source 3 can be selected as the data source The CDB47xxx has been designed to indicate which input is currently selected by illuminating a specific LED for each Source as described below Source 1 selected D12 will be on Source 2 selected D51 will be on Source selected 05 will be on 1 3 8 CS470xx Audio System On a Chip ASOC The CS470xx are a family of ICs designed specifically for audio applications The CDB47xxx allows a designer to evaluate the CS470xx ASOCs in many different modes of multi channel input and output The 100 pin footprint on the daughtercard is compatible with any CS470xx chip that uses the LQFP100 package Audio input data to the ASOC can come from any of the following sources Line Level Analog Audio
72. ected to the analog daughterboard connector J3 The distinction between a differential system and single ended system is made on the main board where either the full differential pair is used or only the positive half of the pair A detailed block diagram of the CDB47xxxD or S DC48 daughter card for single ended or differential platforms is shown in Figure 1 5 The CDB47xxxD or S DC28 and CDB47xxxD or S DC24 daughter cards for single ended or differential platforms are shown in Figure 1 6 and Figure 1 7 respectively The sections that follow provide a detailed description of each block Analog CDB47XXX_DC48 Connector DC ID DAG OUTPUTS 1 AOUT 8 GPIO 8 125 In Y 125 Out Analog Serial Control Connector CS47048 ADC S PDIFIn IED x2 12 1 p 1A AIN 6B SWITCH 2 BUTTON Current Current Current Current Digital Measure Measure Measure Measure Point Point Point Point Connector 3 3VD 1 8VD 3 3 1 8 POWER CONNECTOR Figure 1 5 CDB47xxx DC48 Daughter Card Block Diagram DS886DB4 Copyright 2009 Cirrus Logic Inc 1 10 CDB47xxx Daughter Card System Description CDB47xxx User s Manual Analog CDB47XXX_DC28 Connector DC_ID DAC OUTPUTS AOUT 1 AOUT_8
73. ercard 4 Circuitry The Chronos DSP Daughercard will have only the DSP 0 HER This allows us to easily swap the DSP for different IN CS47xxx Famil bers P xxx Family members Analog 2 x4 DAOButtonsLEDs Digital pede CA ER LAC wa sassa sas ss sa mi sa CROCEICXOCILOCIULI Led CALL ILL ILL tl DAO pins on Chronos are also GPIO These buttons LEDs ROE aE ME NN Can be used by the new primitives being developed 2ch 7 GPIO SPDIF ff onc FSI U Digital 125 OUT aAa se ane CS47xxx HDR DaughterCard 2 1 jm DSP CORE Analog Control SPDIF Tx SMALL 20 PIN HDR Control 5 E m 5 8ch po 3 Digital eee 2 T OUT SPI HOLD FLASH FLASH USB MCU GPIO Silicon Labs Control Parallel Port Buffer US 27 LCD Panel Buttons USB B omposer Rotary Knob Wall Adapter el 2 2 Figure 1 3 CDB47xxxS Board Block Diagram DS886DB4 Copyright 2009 Cirrus Logic Inc 1 4 CDB47xxx Board System Description CDB47xxx User s Manual u
74. ge has been removed and power is applied to pin 2 of the appropriate header 7 1 2 Board not Recognized by PC Problem CDB47xxx is not Recognized by PC Possible cause DC power supply is not connected to CDB47xxx Solution The CDB47xxx is not a USB powered device Make sure the DC wall supply is connected to the DC power input jack J22 and the supply is plugged into a wall outlet Possible cause CDB47xxx USB Drivers not installed before connecting to PC Solution Follow these steps 1 Pull the DC power plug on the CDB47xxx 2 Openthe Windows Device Manager on the PC and search for the USBXpress Device under USB Controllers 3 If there is a question mark next to the device right click on it and open Properties Press the Update Driver button and let Windows operating system automatically find the driver 4 Wait 3 seconds and plug the DC power supply back into the power input jack 7 1 Copyright 2009 Cirrus Logic Inc DS886DB4 Revision History 7 1 3 Audio is not Heard Problem Audio cannot be heard Possible cause Wrong S PDIF Source is selected Revision History CDB47xxx User s Manual Solution Check to make sure that the LED next to the desired S PDIF source is ON If not use MCU to select the appropriate S PDIF input Revision Date Changes DB1 March 13 2009 Initial Release for CDB47xxx YSB User s Manual DB2 July 2 2009 Added new contents fo
75. hannel Remap All designs regardless of the input sources chosen must include the Input Remap block which maps the input sources to the internal channels of the DSP Drag the Input Remap block to the workspace right click on the Remap Audio Input block and choose Device Properties Figure 4 7 shows the channel map remap options that are available DS886DB4 Copyright 2009 Cirrus Logic Inc 4 4 T Running the ADC In DAC Out Example Application IL CDB47xxx User s Manual CIRRUS LOGIC Input Remap Properties Figure 4 7 Input Remap Device Properties After selecting the combination of channels to map or remap the channel wiring options appear in the Remap Audio Input block Channels that are not available now appear as No Connects NC By changing from an option with a smaller number of channels to map such as 2 0 L R to another option that maps more channels such as 3 4 L C Ls Rs Lb Rb all the NO Connects go away become available for wiring Enter the Wire Mode Ctrl w of DSP Composer to make the following wiring connections From the outputs of the Audio In block to the inputs of the Input Remap block From the output of the Input Remap block to the input of the MPM processing block From the output of MPM to the input of VPM From the output of VPM to the input of PPM From the output of PPM to the input of the Output Remap block From the output of the Output Remap block to th
76. ials 5 1 2 1 Micro Condenser Components flasher micro exe This PC tool builds the Flash image containing the DSP Composer deliverables This tool uses an XML file as input flash image xml This is the input file to flasher micro exe This file specifies the following The desired output format for example txt c Path and folder name of the DSP Composer deliverable dnput output Fs and display name of the project The snapshots that are to be built into the Flash image as well as the display name display name of the image can be displayed on the CDB47xxx Board LCD The start address of the Flash image Whether little or big endian format is used Optional addition of project or snapshot names to the Flash image 5 1 2 2 Micro Condenser Restrictions Conventions 5 3 The Micro Condenser application has the following restrictions conventions Only analog input is supported DSP Composer projects and snapshots currently are not identified by the name of the project or snapshot on the CDB47xxx LCD They are identified by a number that is derived from the order in which the project snapshot appears in the XML file used by Micro Condenser when it generates the Flash image A useful practice is to compile a list of the projects snapshots created and the number associated with them in the XML file Copyright 2009 Cirrus Logic Inc DS886DB4 1 Programming a Serial Flash Device for Master or Slave Boot Operations
77. ic lines from the LCD data when the MCU is refreshing the LCD display The button S6 is the board reset When the MCU is reset it reboots and re initializes the entire board according to the firmware stored in its internal Flash J36 is used only for updating the firmware in the MCU and has no function in relation to the CS470xx 6 2 11 User Interface Devices 6 3 Figure 6 12 shows the buttons LEDs and InfraRed receiver which comprise the standalone user interface for the CDB47xxxS The four momentary contact push button switches S1 S4 are routed to the ADC in the MCU U15 The rotary encoder with integrated push button switch S6 is also routed to the ADC in the MCU U15 The LCD LCD1 is the primary feedback device for the MCU user interface The LEDs D1 D4 are also part of the MCU feedback interface showing the MCU status LED D11 is used to indicate that the USB interface is active Copyright 2009 Cirrus Logic Inc DS886DB4 9885 91607 50 19 6002 1 7 9 EXT CTRL REV DESCRIPTION NC BY DATE CHK BY DATE gt INTIAL DESIGN 125 HDRs Header will available to probe bring 125 signals 20 Pin HDR Standard 20 Pin Debug Header Serial Control amp Debug DSP Daughtercard The Chronos DSP Daughercard will have only the DSP This allows us to easily swap out the DSP for different CS47xx
78. ing Modules MPM no Virtual Processing Modules VPM R Post Processing Modules PPM Spanning Modules Graphic Elements amp Blocks m 8 EEEEE 2 nc nc nc Input User Devices NElements Flyoffs _ Resutts 4 Find Resuts Figure 4 1 ADC In DAC Out Example 4 2 1 System Block All designs must contain the System block In DSP Composer when you drag the System block onto the workspace the dialog box shown in Figure 4 2 is displayed This dialog box provides options for selecting the Target chip associated with the development board the Firmware version memory map Core Speed Reference Clock Frequency Ref clock freq and the Autodetect Fs Note Leave the Autodetect Fs default value as None unless the application note for a specific firmware module used in a Composer project provides a setting that differs from the default value System Properties Target chip 211 v Ref clock freq 24 576 Core Speed 152 Firmware version Autodetect Fs 06 03 None Figure 4 2 CDB47xxx System Properties DS886DB4 Copyright 2009 Cirrus Logic Inc 4 2 Running the ADC In DAC Out Example Application CDB47xxx User s Manual CIRRUS LOGIC 4 2 2 Selec
79. itry Copyright 2009 Cirrus Logic Inc DS886DB4 9885 91607 50 19 6002 1 81 9 125 HDRs CDB47XXXD Header will be available to probe bring 12 signals 20 Pin HDR Standard 20 Pin Debug Header Serial Control amp Debug 7 DSP Daughtercard The Chronos DSP Daughercard will have only the DSP Mic J This allows us to easily swap out the DSP for different CS47xxx Family members DAO Buttons LEDs DAO pins on Chronos are also GPIO These buttons LEDs Can be used by the new primitives being developed GPIO HDR Use CS47xxx DaughterCard ES lt SPDIF Tx SMALL 5 Analog 20 PIN HDR Contal EXT CTRL SEL SPI HOLD USB MCU Silicon Labs Control Parallel Port LCD Panel Buttons Wall Adapter B1 B2 B3 B4 Rotary Knob LOGIC 600 00357 21 REV CDB 47xxx DIFFERENTIAL see TE BLOCK DIAGRAM DRAWN BY WED ENGINEER WBD 10 13 08 P sr 1o 12 Figure 6 13 CDB47xxD Differential Board Block Diagram IDO T SND jenuejy sasn xxxzpgqO suonduoseqg oneueuos jenuereyig qxvrado CDB47xxD Differential Schematic Descriptions CDB47xxx User s Manual
80. led USBXpressDevice The Device ID is CDB47 The Cirrus Device Manag CDM which is launched after the CDB47xxx Evaluation Kit is installed and thereafter whe the user s system is rebooted displays the Device name as CS47xxx board Look for the CDM icon at the bottom of the right side of the computer screen DS886DB4 Copyright 2009 Cirrus Logic Inc 3 2 Installation Setup and Running First Application CDB47xxx User s Manual a s IC p CIRRL IS LOC Caution The Cirrus Device Manager must be running in order for the board to operate correctly 3 1 4 Running a Stereo PCM SPDIF In DAC Out Application on CDB47xxx Launch DSP Composer Start Program Cirrus DSP CS47XXX DSPComposer 1 In DSP Composer go to File Open and open C CirrusDSP CS47xxx projects spdif_in_dacout cpa Note If the pop up window Project Out of Date apprears click on Update Devices 2 Press the Go button 3 Insert PCM material into the DVD player e g music CD If a DVD is being used as the audio source make sure that the DVD Player or other digital audio source is configured to output PCM data Note Press Play on the DVD player or other digital audio source You should now hear audio from the speakers 3 1 5 Running a Stereo ADC In DAC Out Application on CDB47xxx Launch DSP Composer Start Program Cirrus DSP CS47XXX DSPComposer 1
81. ller code and DSP firmware The CDB47xxx Board can be used to control the CS470xx DSP in Slave mode via the CDB47xxx on board microcontroller Or a Flash Image can be downloaded to a Flash device on either the CDB47xxx or a customer board from which the CS470xx DSP can boot itself and operate in Master mode This chapter describes the following topics Using DSP Composer to download an image to either the SPI Flash U17 or the I C Flash 016 device and initiate Master Boot Operations Using Cirrus Logic s Micro Condenser application to download an image containing multiple DSP Composer projects and snapshots to the SPI Flash U14 device and to control the DSP in Slave mode Using DSP Composer to Create and Load a Flash Image for Master Mode Operations The DSP Composer application allows the user to create a project compile it into a binary image deploy the binary image to the Flash device and to initiate a Master Boot of the CS470xx DSP To create and load a Flash image to the DSP on the CDB47xxx Board or a customer board follow these steps 1 Create a conventional Slave Boot DSP Composer project Click the Go button and check to see if the project performs in an acceptable manner when compiled 2 Open the Project Properties dialog by following the File Properties menu path Select one of the Master Boot options from the Board boot mode comm mode pull down menu In the example shown in Figure 5 1 the user has selected th
82. operties 4 5 Figure 4 8 Selecting DAC Outputs Only using Device Properties Dialog 4 6 Figure 4 9 Selecting S PDIF Outputs and 125 Outputs using Device Properties Dialog 4 6 Figure 4 10 Selecting 125 Outputs using Device Properties Dialog 4 7 Figure 4 11 CDB47xxx Communication Modes Flash 2 4 8 Figure 5 1 Project Properties Dialog Showing the Selection of the 12 Protocol for Loading the Flash Image 5 2 Figure 5 2 Selecting Flash Type via the Advanced Properties Dialog Box 5 2 Figure 6 1 CDB47xxxS Sngle ended Board Block Diagram 6 4 Figure 6 2 CDB47xxS Sngle ended Board Schematic Index sse 6 5 Figure 6 3 CDB47xxxS Sngle ended Daughter Card Connectors 6 6 Figure 6 4 CDB47xxxS Sngle ended Digital Audio Control Connectors 6 7 Figure 6 5 CDB47xxxS Sngle ended Serial Memory nnt 6 8 Figure 6 6 CDB47xxxS Sngle ended Mic 6 9 Figure 6 7 CDB47xxxS Sngle ended Power Connectors 6 10 Figure 6 8 CDB47xxxS Sngle ended ADC
83. or coaxial S PDIF Up to 4 channels of simultaneous analog audio input via the integrated ADCs of the CS470xx The 5 1 analog multiplexer integrated into one of the CS470xx ADCs Upto 8 channel analog output via the integrated DACs of the CS470xx Digital audio output of PCM data via optical or coaxial S PDIF e Multi channel digital audio input via the DAI serial audio 125 header Capability to support fixed output Fs that is independent of input Fs Copyright 2009 Cirrus Logic Inc DS886DB4 Identifying CDB47xxx Components CDB47xxx User s Manual Fast boot master boot of custom applications from 32 Mbit serial SPI Flash device or 512 kbit 2 Microphone input with integrated amplifier Supports all members of the CS470xx family in the 100 pin LQFP package Note Not all features of the CS470xx are exercised on the CDB47xxx 2 2 Identifying CDB47xxx Components 2 2 1 CDB47xxxS Board Figure 2 2 shows the top side of the CDB47xxxS Board Section 2 2 1 1 contains the legend for the reference points called out in red in Figure 2 2 CDB47xxxS Top View Single ended DS886DB4 Copyright 2009 Cirrus Logic Inc 2 2 radaessesa 91607 8 6002 1 c 26 25 24 23 22 21 20 19 18 Figure 2 2 CDB47xxxS Single ended View 11 10 5 4 8 xxx Frgao sjueuoduio xxx pgado Identifying CDB47xxx Components IRR
84. put S ones RSS SBS PES eg E COUNTS ON 75 OHM 6 RX 125 IN DAI3 DATA MUX 4 I SNTALVCIZSAPWR T I mers I a cs B am I esas mem mosyon FUP S n cone nti I 3 E E o 44 i 23 wur d l TERMINATION TO GIVE 500mV SWING WE TEM EOM 8999 EXTERNAL DSP CONTROL m meo mo Ps 29 ET Auxiliory 4 Docs LED is on when MCU 88 gam Bm k oa n RH cm controls DSP m stems 000 Be iw M BR pS E usss P 18 39 1025 00357 21 owo 240 00357 21 SCH DWG 600 00357 21 SSCREW PHILPS 4 AOTHR PH 5 J6 EUSSS 440 0031 PH B T 22 un RE 600 00357 Z1 REV ET DIGITAL AUDIO CTRL CON E 10 13 08 E 4o 12 12 9 Figure 6 16 CDB47xxD Differential Digital Audio Control Connectors suonduoseq 0 enuey ses xxx Frgao radesssa 91607 50 19 6002 1 20 9 SPI FLASH 3 FTS gt 3 51 FLASH MSO SDA
85. puts have the following characteristics Connector Type High Density High Speed Shrouded Female Connector Absolute Maximum Signal Level These signals should only be driven from the connectors on the main board Voltages should comply with the Max Signal Level specification for the main board circuitry 1 4 1 2 Digital Audio Inputs DAI J2 The DAI connector has the following characteristics Connector Type High Density High Speed Shrouded Female Connector Absolute Maximum Signal Level 3 6V Absolute Minimum Signal Level 0 3V This connector passes all serial audio data and clock signals up from the main CDB47xxx board DS886DB4 Copyright 2009 Cirrus Logic Inc 1 12 SS CDB47xxx Daughter Card System Description CDB47xxx User s Manual CIRRUS LOGIC 1 4 2 Audio Outputs from the CS470xx DSP 1 4 2 1 Analog Line level Outputs J3 Analog line level outputs have the following characteristics Connector Type High Density High Speed Shrouded Female Connector Maximum Signal Output Level These signals should only be driven from the connectors on the main board Voltages will comply with the Max Signal Level specification for the main board circuitry 1 4 2 2 Digital Audio Outputs DAO J2 The DAO connector has the following characteristics Connector Type High Density High Speed Shrouded Female Connector Absolute Maximum Signal Level 3 6V Absolute Minimum Signal Level 0 3V Thi
86. r Chapter 3 and 4 Added new Chapter 5 that was not in the DB1 release DB3 July 6 and 15 2009 Updated Chapters 1 2 3 and 4 Additional changes to the remaining chapters will be made in the next release Updated Chapter 4 Programming the CDB47xxx Board to include latest changes to DSP DB4 September 4 2009 Composer Added reference to the Cirrus Device Manager in the note in Section 3 1 3 and p added caution statement immediately after the Changed references to the board name from CDB470xx to CDB47xxx to match the silk screen of the name on the board DS886DB4 Copyright 2009 Cirrus Logic Inc 7 2
87. re followed by the USB drivers required to communicate with the CDB47xxx board 1 6 7 Run the latest DSP evaluation software installation executable CS47xxx_eval_kit_build exe or later This executable is supplied by your Cirrus Logic representative At the Welcome screen click Next At the Cirrus Logic Licensing Agreement window select the accept the agreement radio button to agree to the terms and then select Next Select the default destination directory suggested by the installer for downloading the evaluation kit files Select the default directory suggested by the Installer for storing the shortcuts to the programs and files you are downloading Clink the Install button to begin the installation process Click the Finish button to complete the installation process 3 1 2 Setting up the CDB47xxx Board with a DVD Player Follow these steps to set up the CDB47xxx Board 1 2 3 Place the CDB47xxx and the CDB47XXX DCxx daughter card on a static free surface If the boards are not connected connect them together as shown in Figure 3 1 Connect the power supply jack to the CDB47xxx Board at J2 and the adapter to a wall power socket or to a power strip Note Never connect the power supply without the daughter card being connected to the main board 4 3 1 switching regulators the main board rely voltage sensing paths provided by the daughter card Opening these paths will cause th
88. s connector passes all serial audio data and clock signals up from the main CS47xxx board 1 4 3 Control Header J2 The control header has the following characteristics Connector Type High Density High Speed Shrouded Female Connector Absolute Maximum Signal Level 3 6V Absolute Minimum Signal Level 0 3V This connector passes all serial control signals up from the main CS47xxx board 1 4 4 User Input S1 and S2 The CS470xx can be configured to accept user input through the slide switch and button on the daughtercard The button and switch are connected to GPIO pins on the ASOC which are monitored by the DSP This feature is firmware dependent and may not be available in all applications There is a slide switch S1 provided It can connect Pin 7 GPIOO of the DSP to either 3 3V or ground through a 10K resistor on the DSP There is a momentary contact push button S2 provided When pressed it connects Pin 19 GPIO3 to 3 3V through a pull up resistor 1 4 5 User LED Output D1and D2 The CS470xx can be configured to provide user feedback through LEDs on the daughtercard This feature is firmware dependent and will not be available in all applications There are 2 LEDs provided for user feedback These LEDs light up when their associated GPIO pin is driven low by the DSP The LEDs map to their pins as follows LED D1 is connected to pin 7 GPIO16 of the DSP LED D2 is connected to pin 15 GPIO6 of the DSP Copyright 2
89. s portable document format PDF and PADS format The schematics included in this document are the original Revision A schematics of the CDB47xxS and D boards and reflect the boards as they were manufactured Newer schematics may be available that incorporate feature additions or corrections and may not match Rev A hardware 58 6 33 Copyright 2009 Cirrus Logic Inc DS886DB4 Obtaining Schematic Updates CDB47xxx User s Manual DS886DB4 Copyright 2009 Cirrus Logic Inc 6 34 lll _ Troubleshooting Guide 3 CDB47xxx User s Manual IS 1 CIKNKUS LOGK Chapter 7 Troubleshooting 7 1 Troubleshooting Guide This section provides solutions to problems that users might experience when using the CDB47xxx 7 1 1 Power LEDs Problem Power LEDs are not illuminated Possible cause DC power supply is not connected to CDB47xxx Solution Ensure the DC wall supply is connected to the DC power input jack J22 and the supply is plugged into a wall outlet Possible cause Power selection headers P1 P3 are not populated Solution If you are using the DC wall supply provided with the CDB47xxx all jumpers should installed Possible cause Jumper settings when using an external power supply are set incorrectly Solution If you are using an external power supply for any of the system voltages 5V 3 3V 1 8V ensure that the jumper for that volta
90. sarwr Place U5 near LCD WGLFST c2cK i M vH DA00 HS0 4 7 4 TEES 2 DAO HSI ij wH 402 852 Die 12 DA03 XWTA HS3 341 RIBS 436 is Reset Circuit Si vee Qut 56 1 M bk intartacs prd 1 LcD RS 1 t i 00 RIBS 1 29 5 E L c cz PART 600 00358 21 REV mE 8051340 E 04 2007 SEC wn llo 12 vl 9 Figure 6 11 CDB47xxxS Sngle ended Microcontroller Card User Interface suonduoseq pepu3 ejBurs Sxx pgao enuey sasn xxx Fgao radesssa 91607 50 19 6002 1 91 9 m BUTTONS ELI Buttons iv 4 4 6 mA m TES Buttons 15V Uum 3 6mA ES Buttons 2V 4 Wo 2 5 Hosp Buttons 2 5V 1 6 08 Buttons 3V 0 6 8206 Ais RS Lco 084 10 085 10 007 LCD SOCKET cot 2 ee LCD PANEL Cum m v R201 23 1203 187 E RED GREEN _ A Cus m rm m se 600 00358
91. t Push Buttons S1 S4 and Rotary Encoder S5 The C8051 can accept user input through the buttons on the CDB47xxx when USB is not connected There are 4 momentary contact push buttons provided There is also a rotary encoder knob that can be used to scroll up and down through options provided through the MCU interface The rotary encoder has an integrated momentary contact push button that is activated by pushing down on the knob 1 3 11 MCU Output LCD LCD1 The C8051 can provide feedback to the user through the on board LCD when USB is not connected 1 3 12 Memory 017 016 U14 The CDB47xxx is assembled with a 32 Mbit SPI Flash U17 and a 512 kbit 2 Flash U16 which are dedicated for DSP firmware and configuration data The serial control lines are routed down from the DSP through the daughter card connectors There is an additional 32 Mbit SPI Flash component on the board U14 that is used only to store MCU firmware and it is not required by the DSP Copyright 2009 Cirrus Logic Inc DS886DB4 CDB47xxx Daughter Card System Description CDB47xxx User s Manual oy 1 4 CDB47xxx Daughter Card System Description CS470xx Audio SOC Daughter card is exactly the same for both the CDB47xxxS and CDB47xxxD evaluation kits All of the analog and digital audio signals are fed to the CS470xx U1 through the daughter board connectors J2 J3 All of the analog pins of the CS470xx are conn
92. ting Changing Audio Input Sources Configure the audio inputs to the DSP by dragging and dropping the Audio In block onto the workspace The dialog box shown in Figure 4 3 then appears Choose from one of the supported input combinations as described in the following sections ADC is selected by default The input configuration may be changed later by right clicking on the Audio In block and selecting Device Properties Audio In Properties R ne ne ne gt gt gt gt ne 4 input 125 5 Data format Multi Channel 125 ADC 9 Remap 10 12 4 Figure 4 3 Selecting Audio Source using Device Properties Dialog Note All designs must include the Input Remap block For details see Section 4 2 3 Input Channel on page 4 4 4 2 2 1 Audio In via ADC To deliver analog audio data to the DSP via the CS470xx ADCs drag the Audio In block to the workspace and select an input configuration that includes ADC The ADC2 input includes a 5 1 input multiplexer that is controlled by the pull down list ADC2 Ch 3 4 Input Sel shown in Figure 4 4 Audio In Properties Input Select ADC Connect 125 signal before clicking GO ADC2 Ch3 4 Input Sel AIN_24 2B Figure 4 4 ADC2 Device Properties The ADC2 block s terminal names will change to match the physical input terminals that are now active For the configuration shown in
93. ustomer Development Kit The CDB47xxx kit is composed of the CDB47xxxS or CDB47xxxD main board and a daughtercard that can support any member of the CS470xx Audio SOC ASOC family The CDB47xxx provides a practical platform for emulating a typical multi channel audio system application The system can be an independent evaluation platform controlled by the on board MCU or using the USB connector the CDB can be connected to a host PC which can configure and control the board using DSP Composer the Cirrus Proprietary GUI Figure 2 1 shows the relationship between the CDB47xxx and the optional PC OPTIONAL lt y CDB47xxx Figure 2 1 CDB47xxx System Block Diagram This document will concentrate on the features and basic operation of the 47 kit Detailed information regarding the operation and programming of the CS470xx Audio SOC is covered by the CS470xx Data Sheet CS470xx Hardware User s Manual and application note AN333 See Section 1 6 Other Useful Information page 17 for more details The CDB47xxx is a convenient and easy to operate evaluation platform It has been designed to demonstrate the majority of the CS470xx functions on a small base board These features include control of the CS470xx using the DSP Composer graphical user interface e Serial control of audio devices on CDB47xxx 12 or SPI protocols Digital audio input of PCM or compressed data via optical
94. ut filter that consists of a current limiter an AC coupling capacitor 10 uF and an anti aliasing capacitor 2200 pF which is not populated The current limiter is scaled to make the CDB47xxxD capable of accepting analog signals of up to 4VRMs differentially 6 3 8 Output Filters Figure 6 21 shows the output filters for the CDB47xxxD Each channel of the CS470xx is differential and is fed to an op amp that converts the differential signal into a single ended output with a maximum swing of 2 Vays Each output has a series resistor 560 Q to provide a voltage drop when the muting transistor is enabled and a mute transistor that will pull the output low when the mute control signal is enabled The series resistor is small enough that it does not affect the signal in normal operation assuming a load of at least 5 is connected to the analog output of the board DS886DB4 Copyright 2009 Cirrus Logic Inc 6 16 6 17 CDB47xxD Differential Schematic Descriptions CDB47xxx User s Manual RRI I lt Ir AKKUS LOGIC 6 3 9 MCU Block Diagram Figure 6 22 shows the MCU block diagram for the CDB47xxxD 6 3 10 MCU Figure 6 23 shows the MCU for the CDB47xxxD See section Section 6 2 10 for description of circuitry 6 3 11 User Interface Devices Figure 6 12 shows the buttons LEDs and InfraRed receiver which comprise the standalone user interface for the CDB47xxxD See section Section 6 2 11 for description of circu
95. v lt IDOT SN 2 600 00357 21 REV Al SHEET PREAMP Figure 6 18 CDB47xxD Differential Pre Amp penuad 0 enuey ses xxx pg qO radesssa 91607 50 19 6002 1 9 CLEAN FROM WALL E 49VA n 0 754 13 v 5V 1A of jaa s IE TANT 182662M NOPB SOIC8 2 5V FOR OPAMPS us 142662 usvec r 500 LOW ESR TANTALUM TO FILTER 5 SWITCHING TRANSIENTS FROM 5VD REG 18 QUT ac sn R5 5 2 gt 5V_REG pico TVS To Prevent L VIN 15V MAX 5 38 Overvoltage bd 4 1 From wrong wall wart Ed Sos 1 REMOVE 21 TO USE EXTERNAL SUPPLY gt 9V EY DC Input Nominal 9V NEED GOOD COPPER POUR ON BOARD FOR HEAT SINK LM25576 for 3 3V 3A us co gel sm pss 76 0 ciz 0 022uF is E T wok ui MN PRE LE 33V REG SCA bkn SY den 23 789 5 BSIOA 15 F 3 out Be ai Vn UW 100uF 0 tuF 16 SENSE_3 3V 131 557 RAMP COMP AA NOPOP FEED
96. ve the following characteristics Connector Type RCA Female Absolute Maximum Signal Level 8Vp p Full Scale Amplitude 2VRMS 1 3 1 2 Analog Line level Inputs Differential CDB47xxxD only AIN1A AIN5B AIN6B Analog line level inputs have the following characteristics Connector 3 5mm 1 8 Stereo Female Absolute Maximum Differential Signal Level 16Vp p 1 Reference designators are listed at the end of the heading for each board component listed in this chapter 1 5 Copyright 2009 Cirrus Logic Inc DS886DB4 CDB47xxx Board System Description CDB47xxx User s Manual 1 3 1 3 Optical Digital Input J21 Optical digital inputs have the following characteristics Connector Type Fiber Optic RX for Digital Audio JIS F05 TOSLINK 1 3 1 4 Coaxial Digital Input J4 Coaxial digital inputs have the following characteristics Connector Type RCA Female Input Impedance 750 Maximum Signal Level 1 5Vp p 1 3 1 5 Microphone Input J9 The microphone input has a stereo connector but only the LEFT channel is used for the microphone input This input has the following characteristics Connector 3 5mm 1 8 Stereo Female Absolute Maximum Signal Level 8Vp p Full Scale Amplitude 20mVp p 1 3 1 6 DSP Digital Audio Input DAI J18 or DAI The DAI connector has the following characteristics Connector Type 2x10 0 100 inch Male Header Absolute Maximum Signal Le
97. vel 3 6V Absolute Minimum Signal Level 0 3V 1 3 2 Audio Outputs 1 3 2 1 Main Analog Line level Outputs CDB47xxxS and CDB47xxxD J5 J8 J10 J13 or AOUT 1 AOUT 8 Analog line level outputs are RCA connectors on both the single ended and differential boards The CDB47xxxD board has a differential to single ended amplifier that feeds the RCA connectors The outputs have the following characteristics Connector Type RCA Female Full Scale Amplitude 2VRMS 1 3 2 2 Optical Digital Output J1 The optical digital output has the following characteristics Connector Type Fiber Optic TX for Digital Audio JIS F05 TOSLINK 1 3 2 3 Coaxial Digital Output J35 The coaxial digital output has the following characteristics Connector Type RCA Female Maximum Signal Output Level 1Vp p into 75Q load DS886DB4 Copyright 2009 Cirrus Logic Inc 1 6 SS CDB47xxx Main Board System Description CDB47xxx User s Manual w gt CIRRUS LOGIC 1 3 2 4 DSP Digital Audio Output DAO J24 or DAO The DAO connector has the following characteristics Connector Type 2x10 0 100 inch Male Header Absolute Maximum Signal Level 3 6V Absolute Minimum Signal Level 0 3V 1 3 3 DC Power Input J2 The DC power input has the following characteristics Voltage Range 9 TO 12 Minimum Power 18W supply 2A 9V Connector Type 2mm female barrel connector with a positive
98. vers on your PC and launch the DSP Composer software the GUI used to control the CDB47xxx After following the instructions in Running a Stereo ADC In DAC Out Application on CDB47xxx on page 3 3 the DSP Composer main window will appear as shown in Figure 4 1 The blocks shown in the main window of DSP Composer can be selected from the folders in the left hand window pane and then connected together by wires to indicate the processing path In this example the Audio In and Audio Out blocks represent the analog input ADC and output DAC ports These blocks can also be configured to represent various combinations of analog and digital I O such 2 and S PDIF This is explained later beginning with Section 4 2 2 The terminals on the Audio In and the Audio Out blocks represent the I O ports The MPM Matrix Processing Module VPM Virtualizer Processing Module and PPM Post Processing Module blocks are intended to implement signal processing In this example the MPM and VPM blocks are pass through blocks containing no internal processing Copyright 2009 Cirrus Logic Inc DS886DB4 Running the ADC In DAC Out Example Application CDB47xxx User s Manual CIRRUS LOGIC DSP Composer 547 adc dac out File Edit Mode Tools Windows Help 3 C Cp connect J Emulation a System block Remap Audio Input Remap Audio Output Audio In Audio Out ED E Matrix Process
99. x Family members DAO Buttons LEDs DAO pins on Chronos are also GPIO These buttons LEDs Can be used by the new primitives being developed GPIO HDR SMALL 20 PIN HDR SEL Control Use DaughterCard Control F SPI_HOLD CDB47XXXS Digital Digital CS47xxx DSP CORE SPDIF Tx Digital USB MCU Silicon Labs Wall Adapter Control Parallel Port GPIO LCD Panel Buttons 5 B1 B2 B3 B4 Mic Circuitry 2 gt Rotary Knob c 600 00358 21 REV CDB 47yyx Single Ended TE BLOCK DIAGRAM DRAWN BY WED ENGINEER WBD 10 13 08 Sze SHEET 1 12 Figure 6 1 CDB47xxxS Sngle ended Board Block Diagram SND sasn xxx rgao suonduoseq pepu3 ejDuis Sxx pgqO _____ CDB47xxS Single Ended Schematic Descriptions CDB47xxx User s Manual CIRRUS LOGIC 1 Block Diagram 2 Schematic INDEX 3 DSP CONNECTORS 4 DIGITAL AUDIO CTRL CONNECTORS 5 FLASH 6 MICROPHONE PREAMP 7 8 FILTERS 9 DAC FILT

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