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SH7751 CPU Board HS7751STC01H User`s Manual

1. 57 Figure 4 1 Monitor Setup Dialog 64 Figure 4 2 Breakpoints 9 een eene enne 66 Figure 4 3 Add Edit Breakpoint Dialog Box eene 68 Figure 4 4 System Status nem nnne 69 Figure 4 5 Run Time Count Condition 71 Figure 4 6 Cache Control Dialog 72 Figure 4 7 Simulated Window Window eese nennen nennen 74 Figure 5 1 Block Diagram of the CPU board 75 Figure 5 2 CPU Board Memory 79 Figure 5 3 Connection to Host 81 Figure 5 4 Serial Interface Connector Pin 82 Figure 5 5 User Expansion Board Interface Connector Pin Arrangement 87 Figure 5 6 Bus Release Timing 90 Figure 5 7 Bus Release Timing 2 nee terere bte enti tnit petere teo br tnn E kept bea 91 Figure 5 8 Example of CKIO Terminal Resistor 92 Figure 5 9 Configuration of User Expansion Board Interface Circuit CN1 1 93 Figure 5 10 Configuration of User Expansion Board Interface Circuit CNI1 2 94 Figure 5 11 Configuration of User Expansion Board Interface C
2. 80 Table 5 3 Serial Interface Specifications nn asr enne eene 81 Table 5 4 Pin Assignment of the EPROM Socket seen 83 Table5 5 LAN91C96 LAN Controller Register Specifications Bank 0 84 Table 5 6 LAN91C96 LAN Controller Register Specifications Bank 1 84 Table5 7 LAN91C96 LAN Controller Register Specifications Bank 2 85 Table 5 8 LAN91C96 LAN Controller Register Specifications Bank 3 85 Table 50 LAN91C96 LAN Controller Register Specifications Bank 4 86 Table 5 10 Pin Assignment of User Expansion Board Interface Connector 88 Table5 1 AG Specifications emite eese das 91 Table 5 12 Compact PCI Interface Connector CN19 Pin Assignments 97 Table 5 13 Compact PCI Interface J2 Connector CN20 Pin Assignments 98 Table 5 14 On Board Registers cece 101 Table 5 15 Hitachi UDI Port Connector CN23 Pin Assignment 107 Table 3 16 LED Functions 2 eres er RII OE DE EE REI aes eke 109 Table 5 17 List of Uninstalled nennen rennen 110 Table 5 18 Resource 114 Table 6 1 Watchdog Timer Register
3. 8 Table2 2 Switch Specifications 00 0 16 Table 2 3 Ape ieee 18 Table 3 1 Tutorial Program 23 Table 3 2 Check Items When HDI Cannot Be Initiated see 25 Table 3 3 Setting the Monitor Setup Dialog Box 28 Table 3 4 Contents of the System Status Window esee 37 3 5 IIS 43 Table 3 6 Items Set in Run Time Count Condition Dialog Box 55 Table 3 7 Selectable Measurement 45 55 Table 4 1 HDI Window Menus and Related Manual Entries eee 61 Table 4 2 Monitor Setup Dialog Box 65 Table 4 3 Breakpoints Window Display 67 Table 4 4 Breakpoints Window Pop up Menu Operation eee 67 Table 4 5 Add Edit Breakpoint Dialog Box Items eee 68 Table 4 6 System Status Window Display Items eene 70 Table 4 7 Run Time Count Condition Dialog Box 2 71 Table 4 8 Selectable Measurement 715 72 Table 4 9 Cache Control Dialog Box Items a 73 Table 5 1 External 76 Table 5 2 Pin Assignment of the Serial Interface
4. 127 Rev 1 0 09 00 page ix of x 6 2 7 1 7 2 7 3 7 4 7 5 Register Initial Value 129 Interrupt Causes and Branch Addresses for User Interrupt Handlers 131 HALT Break Destination 4 4 133 Sample Program Files rene erret rete Ere reor Lp 137 Sections for the Sample Program eese nennen en 137 Interrupt Processing in the Sample Program eee 138 Rev 1 0 09 00 page x of x RENESAS Section 1 Overview 11 Features The SH7751 CPU board hereafter referred to as the CPU board supports the evaluation of the functions and performance of the Hitachi SH7751 microcomputer and the development and evaluation of systems that incorporate the SH7751 The features of this CPU board are as follows e Supports user expansion boards Has an expansion connector for I O of signals conforming to the SH7751 external bus specifications to which an expansion board developed by the user to increase memory and I O can be connected and evaluated e Supports the maximum operating frequency Allows evaluation at 167 MHz and 83 5 MHz which are the maximum internal and external operating frequencies of the SH7751 respectively e Host Interface For interfacing with IBM PC compatible as the host computer one channel of serial interface
5. Power on reset switch Abort switch Manual reset switch Figure 2 11 Switch Location Rev 1 0 09 00 page 16 of 138 RENESAS 2 8 Jumpers The CPU board has 33 locations for jumpers J11 to J16 J21 to J31 to J36 and J41 to e JlltoJ16 Fortest in Hitachi No jumpers are mounted e J21to J21A For specifying the CPU board operating mode J21 J23 and J25 to J27 are mounted e J31 to J36 For specifying expansion functions J35 and J36 are mounted e J4 to For specifying the SH7751 modes J42 J46 149 and are mounted Table 2 3 shows jumper settings In the table the initial settings at shipment are shaded The reserved settings must not be used Figure 2 12 shows how to insert a jumper pin A WARNING Always switch OFF the CPU board and the user system before connecting or disconnecting any CABLES CONNECTORS or JUMPERS Failure to do so will result in FIRE HAZARD and will damage the user system and the CPU board or will result in PERSONAL INJURY The USER PROGRAM will be LOST Rev 1 0 09 00 page 17 of 138 RENESAS Table 2 3 Jumper Settings Symbol Function Setting Description J21 Base clock 1 2 closed Reserved must not be used 2 3 closed On board clock 27 8 MHz J23 Bus frequency Closed CPU internal frequency 167 MHz Bus frequency 55 7 MHz CPU on chip module frequency 27 8 MHz
6. 9 E10A User System Interface Cable Connection sassa 10 Serial Interface Cable Connection a 11 AC Adapter Connecti Ocenie deen oett ttt tote 11 User Expansion Board Connection CN 1 12 Compact PCI Backplane Connection esee 13 Spacer Removal engen RD ERI 14 Front Panel Attachment 15 Switch pa aaa 16 J mper sert oi 19 Power Supply Specifications 20 Power Supply Section Block Diagram 20 Front View of Power Supply Connector 2 AC Power Supply Adapter Connection 4 22 Start l u e 24 Select Session Dialog 24 Power Supply Confirmation Message 25 HDT Wat OW 26 Monitor Setup Dialog 27 Load Program Dialog 2 2 0000404040 29 HDI Message BOX 2 see reel a MEER 29 Dialog C 30 Program Window Displaying the Source Program
7. esee 31 Program Window Setting a Software Breakpoint 32 Registers Window acces eere R i ter 33 Register Dialog Box enne ener ener 34 Register Dialog Box SP 34 CUBE 35 Program Window Break Status nennen 35 System Status Window 36 Breakpoints ertet eei 38 Open Memory Window Dialog 39 Word Memory Window 2 2 20 12 77 002 000000000000000000000000000000000 0000000 39 Instant Watch Dialog Box u s 40 Watch Window Window Displaying the 41 Add Watch Dialog A Watch Window Window Displaying the Variable 42 Watch Window Window Displaying Array Elements 42 Rev 1 0 09 00 page vi of x RENESAS Figure 3 25 Program Window Step Execution eese enne 43 Figure 3 26 Step In Button innert tnnt tk tr Pte etin pedo eR nora 44 Figure 3 27 Program Window Step In aa 44 Figure 3 28 Step Out 2 2 22 tembitr ene eren tr bein senis 45 Fig
8. for SH7751 CPU board Online Services Documents ii Age b Settings gis c r HS7751EJH Find d Load 2 Run MS DOS Prompt amp Log Off Administrator sh7709 Shut Down 27750 1 3 Windows Explorer Favorites Figure 3 1 Start Menu The HDI window will open then the Select Session dialog box will appear Check that the setting shown in figure 3 2 is complete and click the OK button SH7751 GPU board Previous session file Figure 3 2 Select Session Dialog Box Rev 1 0 09 00 page 24 of 138 RENESAS The message box shown figure 3 3 will appear Check that the CPU board power is turned on click the OK button HDI Please power on the GPU board and press lt Enter gt key Figure 3 3 Power Supply Confirmation Message Box When Link up appears in the message box HDI startup is completed If Link up does not appear check the items listed in table 3 2 Table 3 2 Check Items When HDI Cannot Be Initiated Check Item Reference in this Manual Check that the power monitoring LED D22 on the CPU board is turned on Section 5 7 Check that the host computer and the CPU board are correctly connected through a serial cable Sections 2 4 and 5 4 1 Check that the port and baud rate are set correctly in the Monitor Setup dialog box Sections 3 5 and 4 2 1 Check t
9. FE b P wm R R F R h F P maaa F L Undetermined This register masks external interrupt input When an EXINT bit becomes 0 while the corresponding bit in this register is set to 1 the IRL2 signal is input to the CPU Bit 12 EXINTMASK4 0 Masks the user expansion board interface EXINT4 interrupt 1 Accepts the user expansion board interface EXINT4 interrupt Bit 11 EXINTMASK3 0 Masks the user expansion board interface EXINT3 interrupt 1 Accepts the user expansion board interface EXINT3 interrupt Bit 10 Reserved Always write 0 Bit 9 Reserved Always write 0 Bit 8 EXINTMASKO 0 Masks the serial interface DCD interrupt 1 Accepts the serial interface DCD interrupt Rev 1 0 09 00 page 104 of 138 RENESAS 51 NMI interrupt mask register NMIMASK Bi pum F j e me or ASK ASK R R w w E b b h bp b mw BR R F R F P E F L Undetermined This register masks the input from the abort switch and the NMI input from the user expansion board It also specifies whether the CS5 and CS6 areas are released to the user expansion bus Bit 10 CS56EN 1 Outputs CS5 and CS6 area accesses to the expansion bus 0 Does not output CS5 and CS6 area accesses to the expansion bus Bit 9 SWNMIMASK 1 When the SW4 abort switch is pressed an NMI signal is input to the CPU 0 When the SW4 is pressed no NMI signal is
10. o 2 a c o c When the characteristic impedance of the expansion board is needed to match with the CPU board terminal resister should be R1 1000 and R2 1600 Figure 5 8 Example of CKIO Terminal Resistor Connection Rev 1 0 09 00 page 92 of 138 RENESAS SH7751 Expansion bus M3 6 G28F640J5 U21 22 25 26 25 0 ALVCH16245 ALVCH16245 5 25 0 D 31 0 SHMD 31 0 STATUS 1 0 SHSTATUS 1 0 3 3 V 3 3 V 10 kQ 10 SHMRDWR SHMRD RD _WR RD CASS FRAME CKIO SHMCKIO SHCKIO EXBS SHMWE S 0 SHMWEO LVC16244 W SHMWE 1 0 U40 FPGA DSBCS2 DSBCS4 33V suMCs e 0 cso 10 1 52 SHMCSO SHMCS1 653654 SHMCS3 SHMCS5 CS5 CE1A SHMCS6 CS6 CE1B 45 MD3 CE2A MD4 _CE2B 05740573384 Figure 5 9 Configuration of User Expansion Board Interface Circuit CN1 1 Rev 1 0 09 00 page 93 of 138 RENESAS 7751 Expansion bus EXINT3 EXINT4 EBREQOA EBREQOB EBREQ2 EBREQ3 2 SHDRAKO SHDREQO _IRLI3 0 SHIRL 3 0 SHRDY BREQ BSACK BACK BSREQ RESET SHBREQ SHBACK SHRESET DX20M 36S CN23 U2 LVC240 10 KQ 10 KO 10 KQ 33 3 3V 3 3V EXMRST _ Logic on the board Figure 5 10 Configuration of User Expansion Board Interface Circuit CN1 2 Rev 1 0 09 00 page 94 of 138 RENESAS 7751 Expansion bus M3 6 G28F640J5 FLRDY
11. 72 4 2 7 Simulated Window 2 201 22 2 02 000000000000000000000000 73 4 2 8 Command Line 74 Section 5 CPU Board Specifications 75 3 1 Block Diagram ertet tiet tee etre t Pad eee EEE EEEE EAE EEEE E ETO 75 2 22 Specifications ssori 76 223 Memory E E s 78 34 External 80 341 Seral Interface enese 80 542 EPROM Socket Interface 20 050 05 82 343 BIET 83 5 4 4 User Expansion Board 86 545 96 5 5 On Board Registers 101 5 6 IQA Emulator 106 5 7 OnBoatd LEDS 108 5 8 dv 110 J9 VELVET 114 29 1 Iniahzing RESOULCES ere ttt iret E ebbe roe 114 5 9 2 Procedure for Making Initial Settings of the CPU Bus State Controller BSC 116 5 0 3 Initial Settings of CPU Bus State Controller BSC 117 Section 6 Notes and Troubleshoo
12. D long a 10 long j int i min max 0 000004 for 120 1 lt 10 i 0 00000 j rand 0 00001 0 0 000020 J 0 000024 0 0000406 Break 0 000050 0 000054 0000058 0 00005 0 000060 0 000070 02000074 000078 8 9 1 1 1 1 1 1 1 1 1 1 2 RCM Figure 3 15 Program Window Break Status The user can see the cause of the break that occurred last time in the System Status window Rev 1 0 09 00 page 35 of 138 RENESAS Select Status from the View menu The System Status window will appear Open the Platform sheet and check the status of Break Cause System Status Item Connected to CPU Node Cache Status 10 06 MMU Status 1 0 definition Clock Target DLL Version Monitor Version Run Status Break Cause Run Time Count Comm port baudrate Status SH4 Monitor SH 751 Big Endian Privileged Mode OFF OFF OFF CPU 167 MHz External Bus 83 5 MHz nm dd yyyy Breakpoint Oh Omin 05 Oms 0 043 57600 bit s N Session h Platform Memory Rev 1 0 09 00 page 36 of 138 Figure 3 16 System Status Window RENESAS System Status window displays the following items each page Table 3 4 Contents of the System Status Window Sheet Item Description Session Targ
13. 16245 CDC2509 u22 16245 16245 z HM5225165 SG8002CA HM5225165 FCT3805 Spacer locations 9 Spacer Removal 2 Figure Rev 1 0 09 00 page 14 of 138 RENESAS Figure 2 10 Front Panel Attachment Rev 1 0 09 00 page 15 of 138 RENESAS 2 7 Switches Table 2 2 lists the switches used in the CPU board and figure 2 11 shows where the switches are located on the CPU board Table 2 2 Switch Specifications Switch Symbol Type Function Power supply SW1 Rocker Turns on and off the 5 V power supplied to the switch switch CPU board Turn off this switch when connecting to the compact PCI backplane Manual reset SW2 Push button Forcibly initializes the system Use this switch switch red when the system does not operate correctly for example when the user program goes out of control The BSC settings are not initialized Power on reset SW3 Push button Forcibly initializes the system Use this switch switch white when the system does not operate correctly for example when the user program goes out of control The BSC settings are reset to the HDI initial settings Abort switch SW4 Push button Forcibly aborts the command currently being black executed When this button is pressed while the user program is being executed the CPU board stops execution and returns to the monitor program command wait state switch
14. LAN interface CN2 One channel 10BASE T Transfer rate 10 Mbit s max Controller LAN91C96 manufactured by Standard Microsystems Corporation Configuration ROM M93C46 manufactured by STMicroelectronics Connector on CPU board NT10 8SAG 10L9 manufactured by Japan Aviation Electronics Industry Ltd Rev 1 0 09 00 page 76 of 138 RENESAS Table 5 1 User expansion board interface CN1 External Specifications cont Specifications Expansion board connector Connector on CPU board 53481 1809 manufactured by Molex Incorporated Connector on user board 52760 1809 manufactured by Molex Incorporated Compact PCI interface CN19 and CN20 System board conforming to PICMG2 0 rev 2 1 Only J1 and J2 connectors are mounted Interface voltage 3 3 V PCI clock 33 MHz Data bus width 32 bits Supported expansion slots Up to four slots Interface connectors J1 connector CN19 27 8071 110 01 1 833 manufactured by Kyocera Elco Corporation J2 connector CN20 27 8071 110 010 833 manufactured by Kyocera Elco Corporation E10A emulator interface CN23 Connector on CPU board DX20M 36S manufactured by Hirose Electric Co Ltd Switches SW1 Power supply switch SW2 Manual reset switch SW3 Power on reset switch SW4 Abort switch External Board Width 233 35 mm Length 160 mm dimensions Product Width 236 mm Length 175 mm Height 42 mm Rev 1 0 09 00 page 77 of 138
15. Table6 1 Watchdog Timer Register Register Name Usage Register WTCSR W Write Watchdog timer control status register WTCNT W Write Watchdog timer counter WTCSR R Read Watchdog timer control status register WTCNT R Read Watchdog timer counter 7 Since the CPU board cannot use another HDI re install this HDI whenever another previously installed HDI is used If another HDI has been used initiate this HDI with Run as follows without using the session files Rev 1 0 09 00 page 127 of 138 RENESAS lt Directory path name which HDI is installed gt hdi RET n initiates the HDI without loading the recently used session files If there is another session file on a different debug platform the following error message is displayed invalid target system lt recently used debug platform name gt 8 When another HDI is uninstalled after installation of this HDI some functions may not work correctly In this case re install this HDI 9 For commands such as Fill Memory and Test Memory it may take a few minutes to complete command execution This depends on the size of data specified Since only 5 seconds is specified for the timeout time in the HDI of the CPU board the Command not ready error may occur In such cases the results of the command execution will not be guaranteed therefore specify a smaller size and execute the command again 10 The access size and target start and end a
16. SH7751 register definition install directory Sample Simio lolevel c SCIF driver program install directory Sample Simio Main c Main program install directory Sample Simio Resetprg src Start program SCIF relation definition install directory Sample Simio Stacksct src Global variable stack area install directory Sample Simio Vect inc Vector definition install directory Sample Simio Vecttbl src Vector table area install directory Sample Simio Vhandler src Interrupt handler install directory Sample Simio Simio hwp HEW HWP file install directory Sample Simio Syntax txt Syntax text install directory Sample Simio Big Simio abs ABS file for big endian install directory Sample Simio Little Simio abs ABS file for little endian install directory Sample Simio Make Big mak Make file for big endian install directory Sample Simio Serial h install directory Sample Simio Make Little mak Sections Make file for little endian Table 7 4 shows the sections for the sample program Table 74 Sections for the Sample Program Address Section Name H 0C000000 Start IntPRG P and H OCF7F000 Dataarea 0 H OCF7FFFF Stack 010000 INTHandler and INTTBL Rev 1 0 09 00 page 137 of 138 RENESAS Interrupt Handl
17. button The program runs and stops at the set breakpoint Rev 1 0 09 00 page 51 of 138 RENESAS 0 00012 gap gap 0 000140 0 000146 change um change long long 10 00001 0000152 0000174 00001 7 02000122 Figure 3 38 Program Window at Execution Stop Software Break Select Status from the View menu The System Status window displays the following contents The window confirms that execution was stopped at a breakpoint System Status Item Connected to CPU Node Cache Status 6 06 MMU Status 1 0 definition Clack Target DLL Version Monitor Version Run Status Break Cause Run Time Count Comm port baudrate Status SH4 Monitor 5H7751 Big Endian Privileged Mode OFF OFF OFF SH7751 CPU 167 MHz External Bus 83 5 MHz nm dd K Break Breakpoint Oh Omin 05 Oms 0 043 57800 bit s N Session h Platform Memo Figure 3 39 Displayed Contents of the System Status Window Software Break Rev 1 0 09 00 page 52 of 138 RENESAS 3 16 Run Time Count Function By enabling the run time count function and executing the user program the user program run time can be measured In the following example the run time of the sort function is measured e Select Delete All from the pop up menu in the Breakpoints window and double click the BP column on the 21st and 22nd lines in the Program window to
18. 10 93 412V 123 6 153 94 GND 124 5 6 154 STBY 95 1 8V 125 3 3V 155 FLRDY 96 GND 126 6 156 RXD2 5 97 43 3V 127 ASEBREAK 6 157 3 3V 98 WE0 128 50 158 5 99 WE1 129 CS1 159 CTS2 5 100 WE2 130 52 160 3 3V 101 131 CS4 161 RD 102 BS 132 CS5 162 RDWR 103 RXDO 133 3 3V 163 IRLO 104 TXD2 5 134 2 10 164 IRL1 105 43 3V 135 CS6 165 IRL3 106 5 6 136 CE2A 166 RDY 9 107 101516 137 BREQ 4 167 8 108 SCK2 138 168 RESET 8 109 3 3V 139 DREQO 169 3 3 110 CS3 11 140 3 3V 170 3 3V 111 RTS2 5 141 171 8 112 3 3V 142 1 172 GND 113 CE2B 143 DREQ1 173 114 EBREQ2 10 144 DACK1 174 3 3V 115 10 145 3 3V 175 5V 116 10 146 SCKO 176 GND 117 TXDO 147 3 3V 177 12 118 EXINT3 148 4 178 GND 119 EXINT4 149 10 179 1 8 120 TDI 6 150 RESETOUT 3 180 GND Note Some signals are converted and input to the CPU or output to the user expansion board interface connector as follows Rev 1 0 09 00 page 89 of 138 RENESAS 1 D 31 0 See figure 5 9 2 A 25 0 See figure 5 9 3 RESETOUT The reset signal input to the CPU is directly output Do not drive these signals from the user expansion board 4 and The CPU signals are directly connected to the connector
19. 7 8 9 Figure 5 3 Connection to Host Computer Rev 1 0 09 00 page 81 of 138 RENESAS Figure 5 4 Serial Interface Connector Pin Arrangement 5 4 2 EPROM Socket Interface A WARNING Always switch OFF the CPU board and the user system before connecting or disconnecting any CABLES or CONNECTORS Failure to do so will result in a FIRE HAZARD and will damage the user system and the CPU board or will result in PERSONAL INJURY The USER PROGRAM will be LOST The CPU board has an EPROM socket M7 for the HN27C4096 through which an ROM ICE can be connected to the CPU board Close the J25 and turn on the power to start the CPU board in the EPROM mode The EPROM socket area is allocated to the 512 kbytes from the start address of area 0 In the EPROM mode the bus width of area 0 is set to 16 bits In this mode the flash memory for monitor program is allocated to area 2 Table 5 4 lists the pin assignment for the EPROM socket Rev 1 0 09 00 page 82 of 138 RENESAS Table 5 4 Pin Assignment of the EPROM Socket Pin No Signal Name Pin No Signal Name Pin Signal Name Pin No Signal Name 1 VPP 11 Vss 21 31 9 2 12 1 07 22 A1 32 A10 3 1 015 13 1 06 23 A2 33 A11 4 1 014 14 1 05 24 A3 34 A12 5 1 013 15 1 04 25 A4 35 A13 6 1 012 16 1 03 26 A5 36 A14 7 1 011 17 1 02 27 A6 37 A15 8 1 010 18 1 01 28 A7 38 A16 9 1 09 19 1 00 29 A8 39 A17 10 1 08 20 OE 30 Vss 40 Vcc Some type
20. RENESAS 5 3 Memory map of the CPU board is shown in figure 5 2 Each area of the CPU is allocated as follows Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Monitor program area Allocated to flash memory Bus width is 32 bits for flash memory However when using the EPROM mode J25 is closed the bus width is set to 16 bits System register area The LAN controller LAN91C96 can be accessed in this area User expansion board interface area The user expansion board can be allocated Note that when the EPROM mode is used J25 is closed flash memory is allocated to this area In this case the user expansion board cannot be used in this area 64Mbyte SDRAM is allocated The first 63 5Mbyte area is assigned to the user area and the remaining 0 5Mbyte area is assigned to the monitor program work area Bus width is 32 bits fixed User expansion board interface area The user expansion board can be allocated User expansion board interface area The user expansion board can be allocated User expansion board interface area The user expansion board can be allocated Rev 1 0 09 00 page 78 of 138 RENESAS Physical address Normal mode EPROM mode H 0000 0000 PRR SS bum H 0000 0000 ash es H 01FF FFFF i d H 007F 32 Mbytes FFFF H 0400 0000 System FPGA 1 System FPGA 1 H 0400 0000 Int Status Int Mask
21. SCIF and Host Interface 1 The serial interface with the host uses the SCIF in the CPU For this reason the user cannot use the CPU s internal SCIF except for the standard I O processing using the Simulated I O Window For details refer to section 7 2 User Program Using SCIF Use SCI instead for a purpose other than standard I O processing If the SCIF interface register is accidentally overwritten the CPU board and HDI will become inoperable 2 If the interface is disconnected while a program is being down loaded through the serial interface the HDI will stop abnormally In this case connect the serial interface cable correctly and start up the CPU board and HDI 3 This HDI does not support Motorola S type files with only the CR code at the end of each record Load Motorola S type files with the CR and LF codes H 0DOA at the end of each record 4 The CPU board and the HDI do not limit the address range for downloading a program Be sure to download programs to RAM areas Otherwise operation cannot be guaranteed 5 When a Motorola S type file is down loaded two menus Load Program and Load Memory can be used but the Load Program is recommended because it can transfer data faster Rev 1 0 09 00 page 126 of 138 RENESAS 14 Compact PCI Interface This CPU board is not provided with a PCI driver When using the compact PCI interface please provide your own PCI driver 15 Emulator Interface I
22. SHDACKO RXDO TXDO SCK2 RXD2 TXD2 RTS2 CTS2 MDO SCK2 MD2 RXD2 MD1 TXD2 MD8 RTS2 MD7 CTS2 MD6 IOIS16 TCLK MD5 TRST TDI SHTRST SHTCI TCK TMS SHTCK SHTMS _ASEBRK_BRKAK SHASEBREAK TDO SHTDO Figure 5 11 Configuration of User Expansion Board Interface Circuit CN1 3 Rev 1 0 09 00 page 95 of 138 RENESAS 5 4 5 PCI Interface This board is provided with the compact PCI interface using the on chip PCI bridge in the SH7751 The 33MHz 32bit 3 3V PCI interface is supported This CPU board is not provided with PCI drivers When using the PCI interface you must provide your own driver software Figure 5 12 shows the pin arrangements for the compact PCI connectors Pin assignments for the compact PCI connectors are listed in tables 5 12 and 5 13 Refer to the CPU hardware manual for those pins that have no numbers in the pin function column The pin signal level is 3 3 V which is equivalent to that of the SH7751 CPU A WARNING 1 Always switch OFF the CPU board and the compact backplane before connecting or disconnecting any CABLES or CONNECTORS Failure to do so will result in a FIRE HAZARD and will damage the PCI system and the CPU board or will result in PERSONAL INJURY The USER PROGRAM will be LOST 2 Do not insert any other boards into the two slots next to the component side PCI connector side of the CPU board when the CPU board is inserted into the PCI backplane Failure to do so will resul
23. hdw The target session file stores the following information e Software breakpoint information e definition file information e Runtime count function information Note symbol or memory information is saved in the session files If changes to be used again in future they must be saved separately For details refer to the Hitachi Debugging Interface User s Manual Rev 1 0 09 00 page 58 of 138 RENESAS 3 18 What Next In this tutorial we have introduced as examples program debugging using the CPU board and the HDI Further details on the use of the HDI can be found in the Hitachi Debugging Interface User s Manual available in the supplied CD R Rev 1 0 09 00 page 59 of 138 RENESAS Rev 1 0 09 00 60 of 138 RENESAS Section 4 Descriptions of Windows 4 1 HDI Windows HDI window menu bars and the corresponding pull down menus are listed in table 4 1 A O mark and or the relevant section number is shown in the table when menu description is included in the Hitachi Debugging Interface User s Manual or in this manual Menu items shown in gray on the screen are not available Table 4 1 Menu Bar File Menu Pull Down Menu New Session HDI Window Menus and Related Manual Entries Hitachi Debugging Interface User s Manual This Manual Load Session Save Session Save Session As 3 17 Load Program 3 6 1 Initialize Exit Edit Men
24. loaded 0000000 02000123 0C0001CC 0C0001D7 Figure 3 7 HDI Message Box e Click the OK button to continue Rev 1 0 09 00 page 29 of 138 RENESAS 3 6 2 Displaying the Source Program The HDI allows the user to debug a program at the source level e Select Source from the View menu The Open dialog box is displayed e Select the C source file that corresponds to the object file the user has loaded Open MEI Look in a Tutorial 0 c File name Sort c Files of type Files c inl Cancel 2 Figure 3 8 Open Dialog Box Rev 1 0 09 00 page 30 of 138 RENESAS e Select Sort c and click the Open button The Program window is displayed Sort c Line Address Label Source 0 000000 main void main void long a 10 long i int i min max 0 000004 for 120 1 lt 10 i 00000 j rand 0 00001 0 0 4 0 000020 j j 0 000024 ali J 0 1 2 3 4 5 B 5 8 9 0 1 0 000040 sort 9 1 1 1 1 1 1 1 2 2 8 Figure 3 9 Program Window Displaying the Source Program e If necessary select the Font option from the Customize submenu on the Setup menu to select a clear font and size Initially the Program window shows the start of the main program but the user can use the scroll bar to scroll through the program to see the other statements Rev 1 0 09 00 page 31 of 138 RENESAS 3
25. s Manual Publication Date Ist Edition September 2000 Published by Electronic Devices Sales amp Marketing Group Semiconductor amp Integrated Circuits Hitachi Ltd Edited by Technical Documentation Group Hitachi Kodaira Semiconductor Co Ltd Copyright Hitachi Ltd 2000 All rights reserved Printed in Japan
26. 00 page 4 of 138 RENESAS 15 CD R Contents The supplied CD R includes software and user s manuals for the SH7751 CPU board as listed in table 1 2 Table 1 2 Directory Setup CD R Contents File Name Setup exe Contents HDI installer Remarks Manuals Japanese HS7751STC01HJ pdf SH7751 CPU Board PDF document in User s Manual Japanese Type HS7751STCO1HJ Manuals Japanese HS6400DIIW5SJ pdf Hitachi Debugging PDF document in Interface User s Japanese Manual Type HS6400DIIW5SJ Manuals English HS7751STCO01HE pdf SH7751 CPU Board PDF document in User s Manual English Type No HS7751STCO1HE Wanuals English HS6400DIIW5SE pdf Hitachi Debugging PDF document in Interface User s English Manual Type HS6400DIIW5SE WPdf read Japanese Ar40jpn exe Acrobat Reader installer Japanese version Pdf_read Englsih Ar40eng exe Acrobat Reader installer Note To read a PDF document use the Acrobat Reader RENESAS English version Rev 1 0 09 00 page 5 of 138 1 6 Environmental Conditions CAUTION Observe the conditions listed in tables 1 3 and 1 4 when using the CPU board Failure to do so will damage the user expansion board and the CPU board The USER PROGRAM will be LOST Table 1 3 Environmental Conditions Specifications Temperature Operating 10 C to 35 C Storage 10 to 50 C Humidity Operat
27. CPU board or will result in PERSONAL INJURY The USER PROGRAM will be LOST Figure 2 7 User Expansion Board Connection CN1 Rev 1 0 09 00 page 12 of 138 RENESAS 2 6 Connecting the Compact PCI Backplane Figure 2 8 shows how to connect the compact PCI backplane A WARNING Always switch OFF the CPU board and the user system before connecting or disconnecting any CABLES CONNECTORS or JUMPERS Failure to do so will result FIRE HAZARD and will damage the user system and the CPU board or will result in PERSONAL INJURY The USER PROGRAM will be LOST Compact PCI backplane commercially available System slot Expansion slots CPU board Commercially available PCI board Figure 2 8 Compact PCI Backplane Connection The CPU board can be used as a system board for compact PCI Install the CPU board in the system board slot of the backplane The 3 3V 33MHz and 32bit interface is supported Up to four expansion slots can be controlled Before installing the CPU board in the backplane remove the spacers and attach the front panel as shown in figures 2 9 and 2 10 Do not lose the spacers and screws removed Rev 1 0 09 00 page 13 of 138 RENESAS 5 e 19 2 5 Transformer 5556 9003 10 93 46 locations SW4 SW3 SW2 FPGA EPM7128 90000000909 909099000000 U43 J1 jumper 20 045 U44
28. Int Status Int Mask H 0600 0000 System FPGA 2 System FPGA 2 H 0600 0000 Exon 0000 power control NMI control power control NMI control H 07FF FFFF Ethernet control Ethernet control H 0700 0000 H 0800 0000 Flash memory 32 Mbytes 0800 0000 Expansion bus area 1 Flash memory expansion area H O9FF FFFF H OBFF FFFF 32 Mbytes H OBFF FFFF 0 00 0000 SDRAM 64 Mbytes H OFFF FFFF H 1000 0000 Expansion bus area H 1400 0000 Expansion bus area 2 Pel memory space 9 H 17FF FFFF H 0000 0000 H 1800 0000 inb 2 Expansion area xpansion bus area H 1BFF FFFF H OOFF FFFF 16 Mbytes H 1C00 0000 H 1CFF FFFF CPU on chip I O and control registers Cannot be used H FFFF FFFF H 1D00 0000 PCI memory space 16 Mbytes H 1DFF FFFF H 1E00 0000 PCI I O space 3 H 1E23 FFFF PCI local registers H 0000 0000 Expansion area AE a PCI VO space 256 kbytes 256 5 H 1E27 PCI space 256 kbytes 0003 y Cannot be used P chip HHFFF CPU on chip I O and control registers Figure 5 2 CPU Board Memory Map Control space Notes 1 When the EPROM mode is used flash memory is allocated to area CS2 In this case the expansion bus area cannot be accessed 2 Accesses to the CS5 and CS6 areas can be enabled or disabled by the setting of the CS56EN bit of NMIMASK 3 Address assignment to the PCI memory space and PCI
29. Masks the PCI INTB interrupt 1 Accepts the PCI INTB interrupt Bit 8 PINTMASKO 0 Masks the PCI INTA interrupt 1 Accepts the PCI INTA interrupt Rev 1 0 09 00 page 102 of 138 RENESAS 3 External interrupt source register EXINT R W Initial value w R R R FR RR masa F F F FE E E E Undetermined This register monitors the signal levels of the external interrupt lines When an IRL2 interrupt is requested to the CPU the source of the interrupt can be determined by reading this register To clear the interrupt source access to the corresponding resource that has generated the interrupt Bit 12 EXINT4 0 User expansion board interface EXINT4 signal driven low interrupt requested 1 User expansion board interface EXINT4 signal driven high interrupt not requested Bit 11 EXINT3 0 User expansion board interface EXINT3 signal driven low interrupt requested 1 User expansion board interface EXINT3 signal driven high interrupt not requested Bit 10 Reserved Always read as 1 Bit 9 Reserved Always read as 1 Bit 8 EXINTO 0 Serial interface DCD signal driven low interrupt requested 1 Serial interface DCD signal driven high interrupt not requested Rev 1 0 09 00 page 103 of 138 RENESAS 4 External interrupt mask register EXINTMASK Bit po na m 59 9 Not used Not used Not used EXINTM EXINTM Reserved Reserved EXINTM ASK4 ASK3 ASKO aw R CR C jw w w Fw
30. Measurable Time Closed 27 83 MHz 0 15 us Approximately 10 minutes 0 6 us Approximately 41 minutes 2 3 us Approximately 2 hours 45 minutes 9 2 us Approximately 11 hours Open 41 75 MHz 0 10 us Approximately 6 minutes 50 seconds 0 4 us Approximately 27 minutes 1 5 us Approximately 1 hour 45 minutes 6 1 us Approximately 7 hours 15 minutes Click the OK button to enable the run time count function Rev 1 0 09 00 page 55 of 138 RENESAS Click the Go button Execution will stop at the line following the sort function and the run time will be displayed in a message box Hitachi Debugging Interface sort SH7751 CPU board Sortc P 9 9 9 ea 2 Ea Ba El E Es pa 2 Source 0 000000 main void main void long a 10 long j f 0 000004 0 00000 0 00001 0 000020 0 000024 0 000040 0 000050 e 0 000054 0 000058 0 00005 0 000060 0 000070 0 000074 8 9 1 1 1 1 1 1 2 cO c Break Breakpoint Figure 3 43 Program Window Stopped at a Breakpoint after Run Time Count The time from the sort function call to the return to the caller be checked at Run Time Count on the Platform sheet in the System Status window Rev 1 0 09 00 page 56 of 138 RENESAS System Status Item Status Connected to SH4 Monitor CPU 5H7751 Big Endian Mo
31. No Signal Name Description 1 Reserved No connection 2 RXD Received serial data 3 TXD Transmitted serial data 4 DTR Data terminal ready connected to DSR on the board 5 SG Signal ground 6 DSR Data set ready connected to DTR on the board 7 RTS Request to send 8 CTS Clear to send 9 Reserved No connection Rev 1 0 09 00 page 80 of 138 RENESAS Table 5 3 Serial Interface Specifications ltem Specifications Synchronization method Asynchronous method Transfer rate 57600 or 115200 bit s can be switched with jumpers Bit configuration Start bit 1 bit Stop bit 1 bit Parity None Data length 8 bits Flow control RTS CTS control Controller On chip SCIF serial communication interface with FIFO in the SH7751 Driver LT1330CG manufactured by LINEAR TECHNOLOGY CORP Connector Connector on CPU board DELC J9PAF 20L9 manufactured by Japan Aviation Electronics Industry Ltd Figure 5 3 shows the wiring connection between the host computer IBM PC compatible machine serial interface connector and the CPU board interface connector Figure 5 4 shows the serial interface connector pin arrangement For details on serial interface cable connection refer to section 2 4 Connecting Cables IBM PC CPU board Serial interface connector Serial interface connector N C RXD TXD DIR 771 _ Pin 4 and 6 5 1 directly connected a on the CPU board RTS CTS N C 2 3 4 5 6
32. O register definition file can consist of up to nine characters This number does not include the file name s extension Rev 1 0 09 00 page 64 of 138 RENESAS Description The settings of the Monitor Setup dialog box are indicated below Table 42 Monitor Setup Dialog Box Page Option Setting Port COM1 COM2 COM3 or COM4 can be selected as the host computer serial port Baud Rate Sets the serial baud rate Select either 57600 bit s or 115200 bit s to match the setting of jumper J36 Connection is not possible at any other setting I O definition file Sets the register definition file Click the Browse button to select the SH7751 definition file When selecting a file the I O Registers window accessed from the View menu can be used to display register information Download with verify The CPU board does not support this function this box cannot be selected Delete breakpoints when program is reloaded When this box is checked all breakpoints are deleted when a program is reloaded Reset CPU when program has been downloaded When this box is checked registers are initialized when a program is loaded No reset signal is input to the CPU board Note Initialized as follows PC H AC000000 SR H 600000E0 and VBR H A0080000 big endian H A0100000 little endian Clicking the OK button sets the setup conditions If the Cancel button is clicked this d
33. Open CPU internal frequency 167 MHz Bus frequency 83 5 MHz CPU on chip module frequency 41 8 MHz J25 Resource for 0 Closed EPROM socket connected Flash memory is connected to area 2 Open Flash memory containing HDI connected J26 Expansion bus Closed Area 2 released to the user expansion board area 2 interface Open Area 2 cannot be used J27 Expansion bus Closed Area 4 released to the user expansion board area 4 interface Open Area 4 cannot be used J35 PCI clock 1 2 closed On board clock 33 MHz 2 3 closed Reserved must not be used J36 Serial interface Closed 57 600 bit s paui is Open 115 200 bit s J42 CPU clock mode Closed Clock mode 5 Open Reserved must not be used J46 CPU endian Closed Big endian Open Little endian J49 CPU clock source Closed Pulse input to EXTAL of CPU Open Reserved must not be used J4A CPU PCI clock Closed Input to PCICLK pin Open Reserved must not be used J4B CPU PCI function Closed PCI function enabled Open PCI function disabled Note When the EPROM is selected by J25 area 2 becomes the flash memory area regardless of the J26 setting and the expansion bus area cannot be accessed in area 2 The 50 bus width is switched between 32 bits flash memory is connected and 16 bits EPROM is connected by the J25 setting Rev 1 0 09 00 page 18 of 138 RENESAS pom udi e Figure 2 12 Jumper Insertion Rev 1 0 09 00 page 19 of 138 RENESAS 2 9 Power Supply 2 9 1 P
34. Simulated I O Window window on the host PC rather than with the actual SCIF directly As processing for interrupts of the CPU must be added to the user program a user interrupt handler must be created according to the directions in section 7 1 Creation of User Interrupt Handlers The HDI installer CD R supplied with the CPU board contains a sample program for the user interrupt handler and SCIF driver For details on the sample program refer to section 7 3 Sample Program 7 2 1 Creation of SCIF Driver Note the following when creating the SCIF driver e To receive serial data an interrupt must be used Create a SCIF RXI receive data full interrupt request processing routine e When the HALT button is pressed during serial receiving operation the HDI sends the HALT code H 12 to the CPU board When the HALT code is received execution must branch to the HALT break processing address in the CPU board Table 7 2 HALT Break Destination Address Endian HALT Break Destination Address Big endian H A00820E0 Little endian 01020 0 e The branch to HALT break processing is performed in the same interface as the branch to user interrupt handlers For details refer to section 7 1 Creation of User Interrupt Handlers Notes 1 The SCIF is used for communication between the CPU board and the host computer If the user uses the SCIF for a purpose other than the communication with the Simulated I O Window window correct operation
35. The items listed in table 4 7 can be set in the Run Time Count Condition dialog box The run time can be checked in a message box displayed at break or in the System Status window Table 4 7 Run Time Count Condition Dialog Box Items Item Description Enable Check this box to enable the run time count function The default setting is disable Measurement Mode Select a measurement unit here The setting is stored when the OK button is clicked The selectable measurement units depend on the jumper setting J23 bus frequency setting on the CPU board as shown in table 4 8 Rev 1 0 09 00 page 71 of 138 RENESAS Table 4 8 Selectable Measurement Units J23 Internal Peripheral Measurement Setting Module Operating Clock Unit Maximum Measurable Time Closed 27 83 MHz 0 15 us Approximately 10 minutes 0 6 us Approximately 41 minutes 2 3 US Approximately 2 hours 45 minutes 9 2 us Approximately 11 hours Open 41 75 MHz 0 10 us Approximately 6 minutes 50 seconds 0 4 us Approximately 27 minutes 1 5 us Approximately 1 hour 45 minutes 6 1 us Approximately 7 hours 15 minutes Note When the maximum measurable time shown in table 4 8 is exceeded the measured value will be invalid 4 2 6 Cache Control Dialog Box Function Specifies the cache functions This dialog is displayed on selecting Cache Control from the View menu Window che Control Instruction Cache Enabl Instruction Gac
36. a branch address from the user interrupt handler the values of RO and BANK1 must be saved on the stack In other words R15 8 at time of exception BANK1 R15 4 at time of exception BANK1 The following is an example of code which achieves this MOV L RO Q R15 save RO_BANK1 MOV L R1 R15 save BANK1 By this means register values can be displayed during debugging when an exception or interrupt occurs The values of control registers and general purpose registers other than RO and should be saved at the time of occurrence of an exception or interrupt The BL bit of the SR register should be kept as from the occurrence of an exception until branching to the branch address The values of the SSR SPC EXPEVT INTEVT and TRA registers should be saved at the time of occurrence of an exception Branching from a user interrupt handler should be performed with the RB and MD bits of the SR register both set to 1 the state of occurrence of an exception or interrupt Rev 1 0 09 00 page 132 of 138 RENESAS 7 2 User Program Using SCIF The user program cannot usually access the serial communication interface with FIFO SCIF in the SH7751 because the CPU board uses it to communicate with the host PC The CPU board provides the Simulated I O Window window to allow the user to use the SCIF When the SCIF is used from the user program the SCIF driver in the user program communicates with the
37. breakpoint is described below e Select Breakpoints from the View menu The Breakpoints window is displayed e Right click in the Breakpoints window to open a pop up menu and select the Del button to cancel all the breakpoints that have been set A dialog box will prompt you to confirm the deletion of breakpoints Click Yes to delete the breakpoints Breakpoints Enable File Line Address Figure 3 35 Breakpoints Window Before setting software break Rev 1 0 09 00 page 50 of 138 RENESAS Right click in the Breakpoints window to open a pop up menu and select Add The Add Edit Breakpoint dialog box is displayed Either an address or a symbol can be entered e Enter change and check the Enable checkbox Add Edit Breakpoint Breakpoint change Enable Cancel Figure 3 36 Add Edit Breakpoint Dialog e Click the OK button The software breakpoint that has been set is displayed in the Breakpoints window Breakpoints Enable File Line Symbol Type Sort c 55 _ 06000146 PC breakpoint Figure 3 37 Breakpoints Window Software Breakpoint Setting To stop the tutorial program at the breakpoint the following procedure must be executed Close the Breakpoints window e Set the program counter and stack pointer values that have been set in section 3 8 Setting Registers PC H 0C000000 R15 H AFF80000 in the Registers window Click the Go
38. cannot be guaranteed For such purposes use the SCI 2 If processing that branches execution to the HALT break when the HALT code is received is not prepared the program cannot be stopped by clicking the HALT button in the HDI 7 2 2 SCIF Related Register Settings The initial values of the SCIF related registers are shown below The shaded bits must not be modified Serial Communication Interface with FIFO SCIF Rev 1 0 09 00 page 133 of 138 RENESAS SCSMR2 H FFE80000 0000 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PE 5 CKS 5 1 0 Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCFCR2 H FFE80018 H 0008 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RST RST 100 RG2 RG1 IRG0 61 60 61 00 ST IST Initial 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 SCSCR2 H FFE80008 H 0033 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TIE RIE TE RE 1 0 Initial 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 No restrictions placed on accesses to the SCBRR2 SCFTDR2 SCFSR2 SCFRDR2 SCFDR2 SCSPTR2 and SCLSR2 Rev 1 0 09 00 page 134 of 138 RENESAS Interrupt Controller INTC For the interrupts used by the user program
39. cause a break 3 During single step execution the settings of the breakpoints are ignored 4 After 255 breakpoints the maximum number have been specified if Add Edit Breakpoint is selected in the Breakpoints window an error will occur In this case delete any unnecessary breakpoints and then add or edit breakpoints 5 After setting breakpoints the CPU board must not be manual reset while the user program is being executed Otherwise addresses where breakpoints have been specified will be overwritten with illegal instructions To continue debugging the user program download the user program again 6 A total of 255 breakpoints including temporary breakpoints can be set A temporary breakpoint cannot be set to the same address as an enabled breakpoint If a temporary breakpoint is set to the same address as a disabled breakpoint the breakpoint will be deleted from the breakpoints list after program execution have been completed 7 When the contents of a breakpoint address are modified during user program execution the breakpoint is disabled In this case if user program execution stops by any reason the modified Rev 1 0 09 00 page 124 of 138 RENESAS contents of the breakpoint address is lost and is replaced with the original contents before user program execution 8 When a breakpoint is set the block of the data cache that includes the breakpoint address is made invalid when the user program execution starts an
40. lt 10 i Jf 1 rand if j lt OI gt gt c cn 2 fa em e em E FH EJ H H H For Help press F1 Figure 3 29 Program Window Step Out The values of array a is sorted in ascending order To execute two steps use Step In twice Rev 1 0 09 00 page 45 of 138 RENESAS The value of max displayed the Watch Window window is changed to the maximum data value ging Interface sort SH7751 CPU board File Edit View Run Memory Setup Window Help STELLEN 8 eI 3 2 Source 0 000000 main vole main void long 10 long j int i min max for 120 lt 10 i fa fa ofa em E em Break Step Figure 3 30 Program Window Step In Step In Rev 1 0 09 00 page 46 of 138 RENESAS 3 13 3 Executing Step Over Command The Step Over executes a function call as a single step and stops at the next statement of the main program e Using Step In execute two steps to reach the change function statement step through all statements in the change function at a single step select Step Over from the Run menu or click the Step Over
41. only by Hitachi Ltd excluding all subsidiary products CPU board e Serial cable e AC power cable e AC power adapter The user system or a host computer is not included in this definition Purpose of the CPU Board This CPU board is a software and hardware development tool for systems employing the Hitachi microcomputer SH7751 Simple debugging functions such as debugging performance evaluation and development of the user system including the SH7751 are enabled by connecting the CPU board to a host computer In addition expansion boards can be installed in the slots therefore memory and I O can be expanded However this CPU board must not be installed in user products to be used as part of the user products it is limited to debugging and evaluation of user systems This CPU board must only be used for the above purpose Limited Applications This CPU board is not authorized for use in MEDICAL atomic energy aeronautical or space technology applications without consent of the appropriate officer of a Hitachi sales company Such use includes but is not limited to use in life support systems Buyers of this CPU board must notify the relevant Hitachi sales offices before planning to use the product in such applications Improvement Policy Hitachi Ltd including its subsidiaries hereafter collectively referred to as Hitachi pursues a policy of continuing improvement in design performance and safety of the CPU board Hita
42. status ECSR 00h 07000001 8 register Bank select register BSR R W 33XXh 0700000E 16 5 4 4 User Expansion Board Interface The CPU board has a user expansion board interface connector for the user expansion board interface The maximum currents that can be supplied through the expansion board interface are shown below When designing a user expansion board note that the following values must not be exceeded e 5 0V system 3 0 A e 3 3V system 1 2 A WARNING Always switch OFF the CPU board and the user system before connecting or disconnecting any CABLES or CONNECTORS Failure to do so will result in a FIRE HAZARD and will damage the user system and the CPU board or will result in PERSONAL INJURY The USER PROGRAM will be LOST Figure 5 5 shows the pin arrangement of user expansion board interface connector CN1 Table 5 10 lists the pin assignment of the user expansion board connector CN1 Refer to the CPU hardware manual for those pins that have no numbers in the pin function column The pin signal level is 3 3 V which is equivalent to that of the SH7751 CPU For details on expansion board connection refer to section 2 4 Connecting the User Expansion Board Rev 1 0 09 00 page 86 of 138 RENESAS CN1 top view Pin 180 Board end Figure 5 5 User Expansion Board Interface Connector CN1 Pin Arrangement Rev 1 0 09 00 page 87 of 138 RENESAS Table 5 10 Pin Assignment of User Expansion Board Interface Conn
43. time taken from the start of the program to the break is shown as the Run Time Count on the Platform sheet in the System Status window In this example the run time count function has not been enabled Omin Os Oms 0 0us is displayed e Select Run Time from the View menu The Run Time Count Condition dialog box will appear e Check the Enable check button select a measurement unit from Measurement Mode and click the OK button In this example 0 10us 6min50s is selected Run Time Count Condition Internal clock 41 75 MHz m Measurement Mode 010 50 044 Max 27 15 1h45min 61us Max 7h15min Figure 3 42 Run Time Count Condition Dialog Box The items listed in table 3 6 can be set in the Run Time Count Condition dialog box The run time can be checked in the System Status window Rev 1 0 09 00 page 54 of 138 RENESAS Table 3 6 Items Set in Run Time Count Condition Dialog Item Description Enable Check this box to enable the run time count function The default setting is disable Measurement Mode Select a measurement unit here The selectable measurement units depend on the jumper setting J23 bus frequency setting on the CPU board as shown in table 3 7 Table 3 7 Selectable Measurement Units J23 Internal Peripheral Measurement Setting Module Operating Clock Unit Maximum
44. under a license from the Japanese government and cannot be imported into a country other than the approved destination Any diversion or reexport contrary to the export control laws and regulations of Japan and or the country of destination is prohibited Please contact Renesas Technology Corporation for further details on these materials or the products contained therein SH7751 CPU Board 577515 User s Manual 5 5 ADE 702 225 Rev 1 0 09 22 00 Hitachi Ltd HS7751STCO1HE B Cautions Hitachi neither warrants nor grants licenses of any rights of Hitachi s or any third party s patent copyright trademark or other intellectual property rights for information contained in this document Hitachi bears no responsibility for problems that may arise with third party s rights including intellectual property rights in connection with use of the information contained in this document Products and product specifications may be subject to change without notice Confirm that you have received the latest product standards or specifications before final design purchase or use Hitachi makes every attempt to ensure that its products are of high quality and reliability However contact Hitachi s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodi
45. 00 H 00080008 Bit No Bit 15 14 13 12 11 10 9 8 7 6 5 4 S 2 1 0 Bit 5 5 4 4 2 2 1 1 name SZ 1 670 571 570 541 570 21 570 571 570 571 570 571 570 Initial 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 Rev 1 0 09 00 117 of 138 RENESAS Rev 1 0 09 00 118 of 138 RENESAS Register Values at 83 5 MHz e FRQCR H FFC00000 value Rev 1 0 09 00 page 119 of 138 RENESAS e MCR H FF800014 H 480923F4 6 5 4 3 2 1 0 AMX RFSH RMODE EDO EXT 2 1 0 MODE 1 1 0 1 0 0 Initial value Register Values at 55 7 MHz e FRQCR 00000 H OE13 Rev 1 0 09 00 page 120 of 138 RENESAS e WCRI 800008 H 77771714 Bit 1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 RMODE EDO MODE 0 Rev 1 0 09 00 page 121 of 138 RENESAS SDMR3 H FF940088 00 Rev 1 0 09 00 page 122 of 138 RENESAS Section 6 Notes Troubleshooting 6 1 Notes 1 2 3 User Program Execution 1 When executing a user program the following interrupts cannot be used This is because t
46. 09 00 page 125 of 138 RENESAS 10 Some of the port terminals on this board are also used as pins for other functions and so some pins cannot be used for port functions The pin functions that can be used are included as signal names in the pin names of the expansion connector pin assignments in table 5 10 in section 5 4 External Interface If signal name functions not included in the pin name are used correct operation is not guaranteed CPU Operating Mode The operating mode of this CPU is set at a clock mode 5 and area 0 bus width of 32 bits For other CPU operating mode setting only jumper J46 corresponding to the MD5 signal be used to modify the endian User Expansion Board Interface User Expansion Area 1 Areas available for use with the expansion bus The expansion bus can use areas 2 4 5 and 6 and cannot use area 0 1 or 3 Monitor flash memory is connected to area 0 on board I O is connected to area 1 and SDRAM is connected to area 3 2 Devices which cannot be connected to the expansion bus DRAM cannot be connected to the expansion bus This is because SDRAM on the CPU board is allocated to area 3 3 Interrupts The NMI and external interrupts should all be processed by interrupt handlers in the user program For details refer to section 7 Creation of User Interrupt Handlers Refresh Timer The refresh timer is used as an SDRAM refresh timer and so cannot be used as an interval timer
47. 138 RENESAS 3 10 Reviewing Breakpoints The user can see all the breakpoints set in the program in the Breakpoints window e Select Breakpoints from the View menu Breakpoints Enable File Line Type Sort c 21 06000040 breakpoint Figure 3 17 Breakpoints Window Right clicking in the Breakpoints window will open a pop up menu through which breakpoints can be set changed deleted enabled or disabled Rev 1 0 09 00 page 38 of 138 RENESAS 311 Viewing Memory The user can view the contents of a memory block in the Memory window For example to view the memory contents corresponding to the main in word size e Select Memory from the View menu enter main in the Address edit box and set Word in the Format combo box Open Memory Window Address main Format Word Figure 3 18 Open Memory Window Dialog Box Click the OK button The Memory window showing the specified area of memory is displayed Data Value 4F 20258 32712 E300 7424 1F32 7986 24554 0009 9 0264 818 0116 12004 2219 8729 426 17002 0118 12005 0103 259 0009 9 Figure 3 19 Word Memory Window Rev 1 0 09 00 page 39 of 138 RENESAS 312 Watching Variables As the user steps through a program it is possible to watch that the values of variables used in the user program are changed For example set a watch on the long type array a declared at the begin
48. 14 GND E14 AD32 A15 Reserve B15 GND 15 FAL D15 REQ5 E15 GNT5 A16 Reserve B16 Reserve C16 DEG D16 GND E16 Reserve A17 Reserve B17 GND C17 PRST D17 REQ6 E17 GNT6 A18 Reserve B18 Reserve C18 Reserve D18 GND E18 Reserve A19 GND B19 GND C19 Reserve D19 Reserve E19 Reserve A20 CLK5 20 GND 20 Reserve D20 GND E20 Reserve A21 CLK6 B21 GND C21 Reserve 021 Reserve E21 Reserve A22 4 B22 C22 GA2 D22 GA1 E22 Rev 1 0 09 00 page 98 of 138 RENESAS Note Some signals are converted and input to the CPU or output to the compact connectors and some pins do not work because part of the PCI functions is not supported by the CPU board as follows 1 to INTD The signals are connected to the IRL2 of the CPU through the logic the CPU board For details refer to section 5 5 On Board Registers 2 64bit bus signals NC on the CPU board If necessary deal with those signals appropriately on the expansion board Note that ACK64 and REQ64 are pulled up on the CPU board 3 Signals for slots 6 to 8 Pulled up No board can be connected to these slots 4 Signals for hot swapping Pulled up These pins do not work 5 PRST ORed with the related logic on the CPU board then input to the CPU Refer to figure 5 14 6 INTP INTS NC on the CPU board If necessary deal with those signals appropriately on the expansion board 7 The CPU board does not use this signal Note that a decoupling c
49. 4 2 4 System Status Window Function This window lists information such as conditions that have been set to the CPU board and execution results It is displayed by selecting the Status item on the View menu Window System Status Item Connected to CPU Node Cache Status 10 06 MMU Status 1 0 definition Clock Target DLL Version Monitor Version Run Status Break Cause Run Time Count Comm port baudrate Status SH4 Monitor SH7751 Biz Endian Privileged Mode OFF OFF OFF CPU 167 MHz External Bus 83 5 MHz nm dd XXX Break Breakpoint Oh Omin 05 Oms 0 043 57600 bit s Figure 4 4 System Status Window Rev 1 0 09 00 page 69 of 138 RENESAS Description The items listed in the following table are displayed in the System Status window Table 4 6 System Status Window Display Items Sheet Item Description Session Target System Indicates whether the CPU board is connected or not Session Name Displays the session file name Program Name Displays the load module file name Platform Connected to Displays the name of the connected CPU board monitor program CPU Displays the target CPU and endian setting Mode Displays the CPU processor mode privileged mode or user mode Cache Status IC OC Shows whether the cache is enabled or disabled MMU Status Shows whether the MMU is enabled or disable
50. 7 Setting the Software Breakpoint A breakpoint is one of the easy debugging functions The Program window provides a very simple way of setting a software breakpoint in a program For example to set a breakpoint at the sort function call e Select by double clicking the BP column on the line containing the sort function call Sort c Address BP Source 0 000000 mai main void long a 10 long j int i min max 05000004 1 0 1 lt 10 0 00000 rand 0 i 0 00001 j lt 0000020 j 0000024 c cn CO c 0000040 Break 0 000050 min 0 000054 0 000058 min 00005 0 000060 02000070 02000074 02000078 Figure 3 10 Program Window Setting a Software Breakpoint Break will be displayed on the line containing the sort function to show that a software breakpoint is set Note The software breakpoint cannot be set in the ROM area or the delay slots in the program Rev 1 0 09 00 page 32 of 138 RENESAS 3 8 Setting Registers Set values of the program counter and the stack pointer before executing the program e Select Registers from the View menu The Registers window is displayed Value 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
51. AFF80000 000000 P1 00000000 Figure 3 11 Registers Window Rev 1 0 09 00 page 33 of 138 RENESAS change the value of the program counter double click the value area in the Registers window with the mouse The following dialog box is then displayed and the value can be changed 02000000 Set As Whole Register 222222222 Cancel Figure 3 12 Register Dialog Box PC Enter 0C000000 in the Value edit box and click the OK button e To change the value of the stack pointer move the mouse pointer to the value area of R15 in the Registers window and enter a new value directly or double click the value area with the mouse to open the following dialog box AF F80000 Set As Whole Register 2222222 Cancel Figure 3 13 Register Dialog Box SP e Enter H AFF80000 in the Value edit box and click the OK button Rev 1 0 09 00 page 34 of 138 RENESAS 3 9 Executing the Program Execute the program as described in the following e To execute the program select Go from the Run menu or click the Go button on the toolbar zl Figure 3 14 Go Button The program will be executed up to the breakpoint that has been set and a statement will be highlighted in the Program window to show the position that the program has halted Break Breakpoint will appear on the status bar So rtc Address BP Label Source 0 000000 main IL main void r
52. AME C15 IRDY D15 GND E15 TRDY A16 DEVSEL B16 GND C16 7 016 STOP E16 LOCK A17 3 3V B17 SDONE C17 SBO D17 GND E17 PERR A18 SERR B18 GND C18 3 3V D18 PAR E18 C BE1 A19 3 3V B19 AD15 C19 AD14 D19 GND E19 AD13 A20 AD12 B20 GND C20 7 020 AD11 E20 AD10 A21 3 3V B21 AD9 C21 AD8 021 M66EN E21 A22 AD7 B22 GND C22 3 3V D22 AD6 E22 AD5 A23 3 3V B23 AD4 C23 ADS 023 5V E23 AD2 A24 AD1 B24 5V C24 V O 7 024 ADO E24 64 2 A25 5 B25 REQ64 2 C25 ENUM 4 D25 3 3V E25 5V RENESAS Rev 1 0 09 00 page 97 of 138 Table 5 13 Compact PCI Interface J2 Connector CN20 Pin Assignments Pin Pin Func Pin Pin Func Pin Pin Func Pin Pin Func Pin Pin No Name No Name No Name No Name No Name B1 GND C1 01 E1 REQ2 A2 2 B2 CLK3 C2 SYSEN D2 GNT2 E2 REQ3 4 GNT3 REQ4 4 4 7 4 Reserve 4 C BE7 D4 GND E4 C BE6 A5 C BE5 2 B5 GND 5 05 4 5 64 A6 063 2 B6 62 C6 AD61 D6 GND AD60 A7 59 2 7 GND C7 V IO D7 AD58 7 057 8 AD56 2 8 55 C8 AD54 GND E8 AD53 9 AD52 2 B9 GND C9 D9 AD51 AD50 A10 AD49 2 B10 AD48 C10 AD47 D10 GND E10 AD46 11 AD45 2 11 GND C11 V IO D11 AD44 11 AD43 A12 AD42 2 B12 AD41 C12 AD40 D12 GND E12 AD39 A13 AD38 2 B13 GND C13 V I O D13 AD37 E13 AD36 A14 AD35 2 B14 AD34 C14 AD33 D
53. Auto TX start register R W 00h 07000001 8 Packet number register PNR R W 00h 07000002 8 Allocation result register ARR R 80h 07000003 8 FIFO ports register FIFO R 8080h 07000004 16 Pointer register PTR R W 0000h 07000006 16 Data register DATA R W XXXXh 07000008 16 Data register DATA R W XXXXh 07000004 16 Interrupt status register IST R 03h 07000005 8 Interrupt acknowledge register ACK W XXh 0700000C 8 Interrupt mask register MSK R W 00h 07000000 8 Bank select register BSR R W 33XXh 0700000E 16 Table 5 8 LAN91C96 LAN Controller Register Specifications Bank 3 Initial Access BANK3 Register Abbrev R W Value Address Size bit Multicast table MT R W 00h 07000000 16 Multicast table MT R W 00h 07000001 16 Multicast table MT R W 00h 07000002 16 Multicast table MT R W 00h 07000003 16 Multicast table MT R W 00h 07000004 16 Multicast table MT R W 00h 07000005 16 Multicast table MT R W 00h 07000006 8 Multicast table MT R W 00h 07000007 8 Management interface MGMT R W 3X30h 07000008 16 Revision register REV R 3340h 0700000 16 Early RCV register ERCV R 331Fh 0700000 16 Bank select register BSR R W 33XXh 0700000E 16 Rev 1 0 09 00 page 85 of 138 RENESAS Table 5 9 LAN91C96 LAN Controller Register Specifications Bank 4 Initial Access BANK4 Register Abbrev R W Value Address Size bit Ethernet configuration option ECOR 40h 07000000 8 Ethernet configuration and
54. DANGER indicates an imminently hazardous situation which if not avoided will result in death or serious injury A WARNING WARNING indicates a potentially hazardous situation which if not avoided could result in death or serious injury CAUTION CAUTION indicates a potentially hazardous situation which if not avoided may result in minor or moderate injury CAUTION CAUTION used without the safety alert symbol indicates a potentially hazardous situation which if not avoided may result in property damage NOTE emphasizes essential information Rev 1 0 09 00 page IV of VI RENESAS WARNING Observe the precautions listed below Failure to do so will result in a FIRE HAZARD and will damage the user system and the CPU board or will result in PERSONAL INJURY The USER PROGRAM will be LOST 1 Always satisfy the power supply conditions which are described in the manual Ensure that there are no short circuits between VCC and GND Do not apply voltage that is outside the guaranteed range 2 Always switch OFF the CPU board and the user system before connecting or disconnecting any CABLES connectors or jumpers 3 When turning on the CPU board or the user system take care that conductive material does not touch the CPU board or the user system 4 Check that the pin numbers on the connectors of the CPU board and those on the user system are correctly aligned before connecting the CPU board and the user
55. E1602 107M 4 C79 C80 C88 C243 269M1602 226M 10 C61 C62 C64 C65 C70 C74 C87 C89 C101 C229 269M1602 335M 4 C68 C72 C429 C430 269M3502 475M 1 C153 GRMS9F1032Z50 2 C56 C427 GRM39F104Z25 51 C55 C67 C69 C73 C145 C237 C238 C239 C240 C241 C242 C409 C410 C411 C420 C421 C422 C423 C428 C63 C66 C71 C85 C86 C91 C97 C98 C99 C100 C160 C161 C162 C163 C164 C228 C231 C232 C233 C234 C235 C236 C412 C413 C414 C415 C416 C417 C418 C419 C425 C426 GRM39F 105210 6 C93 C96 C108 C109 C110 C111 GRM40F105Z16 3 C76 C78 C165 GRM39CH150J50 27 C120 C122 C124 C126 C128 C130 C133 C135 C137 C139 C141 C143 C144 C146 C147 C121 C123 C125 C127 C129 C131 C132 C134 C136 C138 C140 C142 GRM39CH181J50 17 C192 C193 C194 C195 C196 C197 C198 C199 C200 C201 C202 C203 C204 C205 C206 C207 C208 GRM39CH220J50 4 C166 C167 C168 C169 GRM39CH221J50 6 C75 C77 C102 C103 C118 C119 GRM39F224Z16 C152 GRM39F271J50 2 C94 C95 GRM39F333Z50 1 C90 GRM39F334Z10 2 C106 C107 GRM39CH470J50 4 C148 C149 C150 C151 GRM39F473Z25 1 92 GRM39CH560J50 6 C112 C113 C114 C115 C116 C117 GRM39CH561J25 2 C104 C105 GRM39F684Z10 2 C83 C84 MCR10EZH J000 13 R18 R19 R85 R87 R89 R91 R2 R5 R7 R119 R120 Rev 1 0 09 00 page 110 of 138 R137 R148 RENESAS Table 5 17 List of Uninstalled Parts cont Part Name MCR10EZH J100 MCR10EZH J101 MCR10EZH J102 MCR10EZ
56. ED locations on the CPU board and table 5 16 shows the LED functions 1 53481 1809 Jeuuojsue D1 3 LAN status Ef CN23 z uBGA g G28F640 F G28F640 489 BGA GesFe40 9 028 640 amp 5 29 Oel OJ Ds e o 7HIES ZZ VOZ0085S pf 018 21 CPU status 40861024 7950 2 voz0089S o Figure 5 16 LED Locations Rev 1 0 09 00 page 108 of 138 RENESAS Table 5 16 LED Functions Part No Color Function Name Status Indicated When Lit D1 Green LNK Valid link has been made through the LAN interface D2 Green RX The CPU board is receiving external data through the LAN interface D3 Green TX The CPU board is sending data through the LAN interface D18 Green Normal The CPU SH7751 is in normal operation state D19 Green SLEEP The CPU SH7751 is in sleep mode D20 Green STAND BY The CPU SH7751 is in standby mode D21 Green RESET The CPU SH7751 is in reset state D22 Red PWR 5 0V 3 3V and 1 8V power are all being supplied to the board correctly Rev 1 0 09 00 page 109 of 138 RENESAS 5 8 Parts Layout The parts layout of the CPU board is shown in figure 5 17 The shaded parts are uninstalled Uninstalled parts are listed in table 5 17 Table 5 17 List of Uninstalled Parts Part Name Quantity Part Number 281
57. H J103 MCR10EZH J104 MCR10EZH J105 MCR10EZH J153 MCR10EZH J200 MCR10EZH J220 MCR10EZH J270 MCR10EZH J392 MCR10EZH J432 MCR10EZH J470 MCR10EZH J473 MCR10EZH J512 MCR10EZH J750 MNR14 EOAB J000 MNR14 EOAB 103 MNR14 EOAB 220 MNR14 EOAB 221 MNR14 EOAB 472 RJ 6P 103 HSJ1003 01 010 IL G 2P S3T2 E DIC152 8P IL G 4P S3T2 E D02 M15SAG 13LQ HIF3F 40PA 2 54DSA MH11061 D2 10 245 15 Quantity Part Number 1 wo O O wo gt oO N R26 R83 R110 R111 R83 R27 R28 R82 R71 R72 R37 R77 R78 R79 R94 R131 R132 R80 R81 R93 R74 R86 R88 R90 R92 R84 R46 R48 R50 R52 R54 R56 R59 R61 R63 R65 R67 R69 R70 R47 R49 R51 R53 R55 R57 R58 R60 R62 R64 R66 R68 R44 R45 R24 R25 R33 R34 R35 R36 R73 R22 R23 R29 R30 R31 R32 R133 R38 R39 R40 R41 R42 R43 NR13 NR14 NR68 NR11 NR12 NR6 NR7 NR8 NR15 NR16 NR44 NR45 NR46 NR47 NR48 NR49 NR53 NR54 NR55 NR56 NR50 NR51 NR52 NR10 NR9 VR1 CN5 CN6 CN7 CN8 CN9 CN10 CN11 CN12 CN13 Rev 1 0 09 00 page 111 of 138 RENESAS Table 5 17 List of Uninstalled Parts cont Part Name UB1112C D1 DM11351 Z5 2 53553 1607 DM11351 Z5 3 410 96 202 310 93 103 310 93 101 310 93 103 HRF22 SML 210MT HSM221C CDRH62B 330 LQH3C471 BLA62B01 SMD150 2 LT1031 LTC1472 TDA1308T NJM386M AD1819AJST HD64465BP HD74LS04FP MQ 200 HD6473214F16
58. HD74HC164FP QS3245Q LT1330CG MAX471CSA LT1085CM HD74ALVC16834T EL CX5F 12 288MHz SG8002CA 12MHz SG8002CAPCCB_22MHZ Rev 1 0 09 00 page 112 of 138 Quantity Part Number 1 MIN a Of P N 14 17 CN21 CN22 J11 J12 J13 J14 415 J16 J22 J24 J28 J29 J2A J2B J41 J43 J44 J45 J47 J48 J31 J32 J33 J34 D4 D5 D6 D7 D8 D9 D10 D11 D13 D14 D15 D16 D17 L1 L2 L3 L4 L5 L6 L7 L13 L14 L15 L16 L8 L9 L10 L11 L12 F2 U12 U13 U14 U15 U16 U17 U18 U29 030 031 033 034 035 038 039 050 053 X1 OSC2 OSC5 RENESAS e tO z Transformer 5556 9003 10 93 46 500 T RUE uBGA G28F640 uBGA uBGA G28F640 uBGA M3 SH7751 G28F640 G28F640 3 12 288MHz 90 000 000000000000 HM5225165 HM5225165 SG8002CA SG8002CA 22MHz 27 83MHz sw4 SW3 SW2 SML210 D13 16 J2 jumper e 16834 Od 4 039 99000 000000000000000 90 000000 09 000 00000000090 12 2 SG8002CA 53806 1604 Side ing 5 17 Parts Layout Mount Figure Rev 1 0 09 00 page 113 of 138 RENESAS 5 9 Initialization 5 9 1 I
59. I O space in this CPU board can be modified by setting the respective SH7751 registers Rev 1 0 09 00 page 79 of 138 RENESAS 5 4 External Interface 5 4 1 Serial Interface A WARNING Always switch OFF the CPU board and the user system before connecting or disconnecting any CABLES or CONNECTORS Failure to do so will result in a FIRE HAZARD and will damage the user system and the CPU board or will result in PERSONAL INJURY The USER PROGRAM will be LOST The CPU board has a serial interface 1 channel that conforms to RS 232C and can be used as an interface with the host computer This interface is implemented by using an on chip serial communication interface SCIF serial interface with FIFO in the CPU Therefore when the user wants to directly use the SCIF in the CPU the user must create an interrupt handler and use the Simulated I O window For details refer to section 7 Creation of User Interrupt Handlers The connector is a 9 pin D sub connector and the interface cable is supplied with the CPU board A baud rate of 57600 bit s or 115200 bit s can be selected To set the baud rate refer to section 2 8 Jumpers Table 5 2 lists the pin assignment for the serial interface connector Table 5 3 shows the serial interface specifications For details on serial interface cable connection refer to section 2 4 Connecting Cables Table 5 2 Pin Assignment of the Serial Interface Connector Pin
60. IN INCLUDING WITHOUT LIMITATION THEREOF WARRANTIES AS TO MARKETABILITY MERCHANTABILITY FITNESS FOR ANY PARTICULAR PURPOSE OR USE OR AGAINST INFRINGEMENT OF ANY PATENT IN NO EVENT SHALL HITACHI BE LIABLE FOR ANY DIRECT INCIDENTAL OR CONSEQUENTIAL DAMAGES OF ANY NATURE OR LOSSES OR EXPENSES RESULTING FROM ANY DEFECTIVE CPU BOARD THE USE OF ANY CPU BOARD OR ITS DOCUMENTATION EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES EXCEPT AS EXPRESSLY STATED OTHERWISE IN THIS WARRANTY THIS CPU BOARD IS SOLD AS 15 AND YOU MUST ASSUME ALL RISK FOR THE USE AND RESULTS OBTAINED FROM THE CPU BOARD Rev 1 0 09 00 page of VI RENESAS State Law Some states do not allow the exclusion or limitation of implied warranties or liability for incidental or consequential damages so the above limitation or exclusion may not apply to you This warranty gives you specific legal rights and you may have other rights which may vary from state to state The Warranty is Void in the Following Cases Hitachi shall have no liability or legal responsibility for any problems caused by misuse abuse misapplication neglect improper handling installation repair or modifications of the CPU board without Hitachi s prior written consent or any problems caused by the user system All Rights Reserved This user s manual and CPU board are copyrighted and all rights are reserved by Hitachi No part of this user s manual all or part may be reproduced o
61. Installation Directory HEW Program Default Installation Directory HEW has not been installed C Hdi5_cb 7751 HEW has been installed C Hew Hdi5 Cb 7751 in this example Backup File If another version of HDI has already been installed a message The HDLINI file has already existed Can it be overwritten will be displayed Clicking Yes will make a backup of the existing file in the Backup directory of the installation directory When installation is complete HDI for SH7751 CPU board can be selected from the start menu Rev 1 0 09 00 page 8 of 138 RENESAS 2 3 Recycle Bin HDI m Windows Update Favorites lt Documents Settings Find 3 Run amp Log Off Administrator ij Shu own Hitachi Embedded Workshop Internet Explorer Microsoft Input Devices fE HDI for SH7751 CPU board Online Services 53 5 7750 StartUp HS7751EJH Kci 4tm Load MS DOS Prompt sh7709 sh7750 1 3 Windows Explorer HDI for SH7751 CPU board Figure 2 3 Start Menu HDI Uninstallation Uninstall the HDI for the SH7751 CPU board as follows 1 2 3 4 confirmation message will be displayed and the uninstallation procedure will start Select Settings from the Start menu then select Control Panel Select Add Remove Programs Select HDI for SH7751 CPU board from the application
62. Memnioty sete iet tetti 39 3 12 Watching Variables iue Ail he are aes aide dina OE RU eee aks 40 3 13 Stepping Through a Program nennen nennen eene een rennen 43 3 13 1 Executing Step In 44 3 13 2 Executing Step Out Command sese 45 Rev 1 0 09 00 page iii of x RENESAS 3 13 3 Executing Step Over Command 47 3 14 Displaying Local Varilables cseescssnsespesenssissssnsespessnsecnsssasvenesoebbovacenseepsbeesncenssasnanes 49 3 15 Software Break 50 3 16 Run Time Count Function eret ebrii etr eee ertet eoa riae eae pede inei 53 3 17 Saving d Session see eee ee tease ce kun Edu ovis dhe 58 3 18 What Next kausa hal RE eo ER eed ep Fes 59 Section 4 Descriptions of Windows 61 IDI Windows M 61 4 2 Descriptions of Each Window een eene ener nennen 64 4 2 1 Monitor Setup Dialog Box seen 64 4 23 Add Edit Breakpoint Dialog Box eee 68 4 2 4 System Status Window nennen nennen nennen nene 69 4 2 5 Run Time Count Condition Dialog 71 4 2 6 Cache Control Dialog Box
63. To all our customers Regarding the change of names mentioned in the document such as Hitachi Electric and Hitachi XX to Renesas Technology Corp The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003 These operations include microcomputer logic analog and discrete devices and memory chips other than DRAMs flash memory SRAMs etc Accordingly although Hitachi Hitachi Ltd Hitachi Semiconductors and other Hitachi brand names are mentioned in the document these names have in fact all been changed to Renesas Technology Corp Thank you for your understanding Except for our corporate trademark logo and corporate statement no changes whatsoever have been made to the contents of the document and these changes do not constitute any alteration to the contents of the document itself Renesas Technology Home Page http www renesas com Renesas Technology Corp Customer Support Dept April 1 2003 5 Renesas Technology Corp Cautions Keep safety first in your circuit designs 1 Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable but there is always the possibility that trouble may occur with them Trouble with semiconductors may lead to personal injury fire or property damage Remember to give due consideration to safety when making your circuit designs with appropria
64. U board Check the components against the component list __ liei Turn on the host computer Procedure when the CPU Install the HDI Section 2 2 board is used first Turn off the host computer Connect the CPU board to the host computer and AC power supply adapter and when necessary to a Compact back plane or user expansion board Also be sure to set the jumper on the CPU board Turn on the host computer Procedure when the CPU board is used Turn on the CPU board Section 3 for second time or later Section 2 3 to 2 8 Start the HDI Figure 2 1 CPU Board Preparation Flow Chart Rev 1 0 09 00 page 7 of 138 RENESAS 2 2 HDI Installation An example of installing the HDI on an IBM PC compatible machine is described in this section Start Setup exe in the Setup directory of the HDI installer CD R If any other application is running close it before starting the HDI installer Figure 2 2 Setup exe Icon This runs the HDI installer A dialog box will first prompt you to select a language for the installation process Select a language then continue according to the instructions displayed by the installer Note Under Windows 4 0 install the HDI in the administrator mode HDI Installation Directory The default directory for installing the HDI depends on whether the Hitachi Embedded Workshop HEW has been installed in the host computer as shown in table 2 1 Table 2 1 Default
65. any interrupt level from 0 to 14 can be set but interrupt level 15 must not be used except for the SCIF IPRA H FFD00004 H 0000 Bit 15 14 3 12 11 10 9 8 7 6 5 4 3 2 1 0 TMUO TMU1 TMU2 RTC Initial O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 value IPRB H FFD00008 H 0000 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 110 WDT REF 5 Initial 0 0 0 0 0 0 0 0 0 010 0 0 0 0 0 value IPRC H FFD0000C Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO DMAC SCIF H UDI Initial 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 value IPRD H FFD00010 H 0000 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 IRL1 IRL2 IRLS Initial O 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 value ICR H FFD00000 Undefined Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IRL IB Initial 04 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 value No restrictions are placed on accesses to the INTPRIOO INTREQOO 5 00 INTMSKCLROO Rev 1 0 09 00 page 135 of 138 RENESAS 7 3 Sample Program This section describes how to create user interrupt handlers and the SCIF driver by using sample programs The sample program files were created in C lan
66. apacitor is inserted between this pin and GND Rev 1 0 09 00 page 99 of 138 RENESAS SH7751 CPU board Power connector 5V On board logic Expansion 3 3 V bus PCI connector connector 3 3 V LT1084 D 5V gt 33 Regulator SW1 1 and SW1 2 are included in one component They are turned on or off at the same time Figure 5 13 CPU Board Power Supply Lines SH7751 CPU board E10A emulator connector From connector PRST Noise reduction circuit From ROM ICE RESET ICE_RESET SYS RES U1 MB3771 SH7751 Power on Expansion bus connector reset circuit RESETOUT RESET MRESET Figure 5 14 Reset Signal Lines Rev 1 0 09 00 page 100 of 138 RENESAS 5 5 On Board Registers The CPU board has on board registers to control interrupts from the external interface These register contents can be modified by user program Table 5 14 lists the on board registers Table 5 14 On Board Registers Register Name Formal Name R W Address PINT PCI interrupt source register R H 04000000 PINTMASK PCI interrupt mask register RAN H 04000002 EXINT External interrupt source register H 04000004 EXINTMASK External interrupt mask register RAN H 04000006 NMIMASK NMI mask register R W H 04000008 1 PCI interrupt source register PINT mw j RB BR j F F F F F FE FE F E mw j RB j j RB P F F maa EE Undetermined This r
67. button in the toolbar P Figure 3 31 Step Over Button ag Jmterface sort 5 7751 GPU board File Edit View Run Memory Setup Window Help Sach tsi EJ Ed l ES PJ w Sortc Address Source 0 000000 mai fand main void long 10 long i int i min 004 for i 0 1 lt 10 i 00 Ole 020 024 040 Break 050 054 058 05c 060 070 074 078 1 r r d c n3 co c cn n2 ri e e Break Step Figure 3 32 Program Window Before Step Over Execution Rev 1 0 09 00 page 47 of 138 RENESAS Hitachi Debugging interface sort 5 7751 CPU board File Edit View Run Memory Setup Window Help EEM stum El Tl Sort c Watch Window Line Address BP Source Valu 0 000000 nal void main void xaf TF dd w co long 10 long j int i min for 150 1 lt 10 i 21 P x CO c 3498 0 D cO co c me Break fa em Lx e Eh m E EJ For Help pres
68. chi reserves the right to change wholly or partially the specifications design user s manual and other documentation at any time without notice Target User of the CPU Board This CPU board should only be used by those who have carefully read and thoroughly understood the information and restrictions contained in the user s manual Do not attempt to use the CPU board until you fully understand its mechanism It is highly recommended that first time users be instructed by users that are well versed in the operation of the CPU board Rev 1 0 09 00 page of VI RENESAS LIMITED WARRANTY Hitachi warrants its CPU board to be manufactured in accordance with published specifications and free from defects in material and or workmanship Hitachi at its option will repair or replace any CPU board returned intact to the factory transportation charges prepaid which Hitachi upon inspection determine to be defective in material and or workmanship The foregoing shall constitute the sole remedy for any breach of Hitachi s warranty See the Hitachi warranty booklet for details on the warranty period This warranty extends only to you the original Purchaser It is not transferable to anyone who subsequently purchases the CPU board from you Hitachi is not liable for any claim made by a third party or made by you for a third party DISCLAIMER HITACHI MAKES NO WARRANTIES EITHER EXPRESS OR IMPLIED ORAL OR WRITTEN EXCEPT AS PROVIDED HERE
69. d definition Displays the selected I O register definition file Clock Displays the clock frequency CPU operating frequency and external bus frequency being used Target DLL Version Indicates the version of the target DLL for connection to the CPU board Monitor Version Displays the monitor program version Run Status Displays the user program execution status Run Being executed Break Stopped Break Cause Displays the cause of the program stopping at break Run Time Count Shows the time from the start of the user program to the break When the run time count function is disabled Oh Omin Os Oms 0 0us is displayed Comm port baudrate Indicates the data baud rate for the serial interface Memory Target Device Configuration supported by this CPU board System Memory Resources Not supported by this CPU board Loaded Memory Areas Shows the area where the load module is loaded Events Resources Shows the number of breakpoints set Rev 1 0 09 00 page 70 of 138 RENESAS 4 2 5 Run Time Count Condition Dialog Function Specifies the condition for measuring the run time It is displayed by selecting Run Time from the View menu Window Run Time Count Condition Internal clock 41 75 MHz Iv Enable m Measurement Mode Q10us 50 C Max 27min 15us Max 1h45min C 61us Max 7hl5min Figure 4 5 Time Count Condition Window Description
70. d after a break occurs 9 When a breakpoint is set all the entries of the instruction cache is made invalid immediately before user program execution starts and after a break occurs 5 When a power on reset or manual reset is input the dialog box shown in figure 6 3 and figure 6 4 respectively is shown At this time general purpose registers and control registers are not reset Either settings should be changed as necessary or the HDI should be restarted And the run time count function availability also be reset so must be enabled again by the Run Time Count Condition dialog box if necessary Message received from monitor Power on reset is detected Figure 6 3 Power on Reset Input Message Box Message received from monitor Manual reset is detected Figure 6 4 Manual Reset Input Message Box 6 If the power is turned on while pressing and holding the manual reset switch the CPU board and HDI will not be started When turning on power do not operate the manual reset switch 7 In some cases I O register values may not be correctly displayed in the memory window This is because the HDI reads all areas in byte units In order to display the correct I O register values select Register Window from the View menu 8 The monitor program sets and uses some of the BSC registers When rewriting these registers refer to section 5 9 3 Initial Settings of CPU Bus State Controller BSC 9 I O Ports Rev 1 0
71. ddresses can be specified in the Fill Memory dialog box If the access size does not match the specified start address the HDI will treat them as follows e Fill size end address start address e The fill size is decreased to the nearest integer multiple of the access size e The start address is decreased to the nearest integer multiple of the access size e If the fill size is smaller than the access size the fill size is increased to the nearest integer multiple of the access size After the above processing the HDI performs the memory fill operation 17 Watch 1 Local variables at optimization Depending on the generated object code local variables in a C source file that is compiled with the optimization option enabled will not be displayed correctly Check the generated object code by displaying the Disassembly window If the allocation area of the specified local variable does not exist the following is displayed Example The variable name is asc asc target error 2010 2 Variable name specification When a name other than a variable name such as a symbol name or function name is specified no data is displayed Example The function name is main main 3 Array display When the number of array elements exceeds 1000 the number exceeding 1000 will not be displayed 18 Run Time Count Function Rev 1 0 09 00 page 128 of 138 RENESAS 19 1 The CPU board uses channel 4 of the interna
72. de Privileged Mode Cache Status IC OC OFF OFF MMU Status OFF 1 0 definition SH7751 Clack CPU 167 MHz External Bus 83 5 MHz Target DLL Version nm dd vyyy Monitor Version A X Run Status Break Break Cause Breakpoint Run Time Count Oh Omin 05 Oms 194 Comm port baudrate 57600 bit s N Session Platform Memory Figure 3 44 System Status Window Run Time Count Result Notes 1 The run time will vary depending on the execution environment 2 The run time can be measured by executing with Go but cannot be measured by Step In Step Out or Step Over Rev 1 0 09 00 page 57 of 138 RENESAS 347 Saving a Session If a program has been downloaded the corresponding source file is displayed and numerous windows are opened it can take some time to restore this setup the next time the program is downloaded The HDI is able to save the current settings for retrieval the next time the program is loaded in order to reduce setup time In order to save a session which has already been named or to save the session with the same name as the current object file select Save Session from the File menu To save the current settings as a session with a new name select the Save Session As command from the File menu A dialog box is displayed enter the new name for the session Three files are saved the HDI session file hds the target session file hdt and the watch session file
73. e box is displayed However in this case the CPU general registers and control registers are not initialized Change settings as necessary or restart the HDI RENESAS Rev 1 0 09 00 page 115 of 138 5 9 2 Procedure for Making Initial Settings of the CPU Bus State Controller BSC Figure 5 18 is a flowchart of the procedure for initial settings of the bus state controller BSC For information on the settings of each BSC register please refer to section 5 9 3 Initial Settings of CPU Bus State Controller BSC MCR 10xxxxxx MCR 50xxxxxx SDMR3 SDMR3 Note RTCOR A503 RTCNT temporary setting RTCOR depends RFCR on frequenc RTCSR Bron Note Auto refresh x eight times Y WCR3 Figure 5 18 Procedure for BSC Settings Rev 1 0 09 00 page 116 of 138 RENESAS 5 9 3 Initial Settings of CPU Bus State Controller BSC The clock mode is set to 5 in the CPU board In the bus state controller BSC registers bits corresponding to areas 0 1 and 3 must not be modified because these areas are assigned to resources of the CPU board If these bits are modified the CPU board will not operate The following shows the initial BSC register values set by the monitor program In the figures the shaded bits must not be modified Separate figures are used to show the register values that depend on the operating frequency CKIO Register Values at 83 5 MHz and 55 7 MHz H FF8000
74. ector CN1 Pin Pin Pin Pin Pin Pin Pin No Name Function No Name Function No Name Function 1 5V 31 GND 61 GND 2 GND 32 20 2 62 019 1 3 12V 33 A21 2 63 D20 1 4 GND 34 A22 2 64 D21 1 5 1 8V 35 A23 2 65 D22 1 6 GND 36 A24 2 66 D23 1 7 GND 37 GND 67 GND 8 2 38 25 2 68 D24 1 9 1 2 39 DO 1 69 D25 1 10 2 2 40 01 1 70 D26 1 11 2 41 02 1 71 027 1 12 4 2 42 D3 1 72 028 1 13 GND 43 GND 73 GND 14 5 2 44 04 1 74 029 1 15 2 45 05 1 75 030 1 16 A7 2 46 06 1 76 031 1 17 8 2 47 07 1 77 STATUSO 18 9 2 48 08 1 78 STATUS1 19 GND 49 GND 79 GND 20 10 2 50 09 1 80 GND 21 All 2 51 010 1 81 12 22 12 2 52 011 1 82 GND 23 A13 2 53 012 1 83 12 24 14 2 54 013 1 84 GND 25 GND 55 GND 85 5V 26 15 2 56 014 1 86 GND 27 16 2 57 015 1 87 12 28 17 2 58 016 1 88 GND 29 18 2 59 017 1 80 1 8 30 19 2 60 018 1 90 GND Rev 1 0 09 00 page 88 of 138 RENESAS Table 5 10 Pin Assignment of Expansion Connector 1 cont Pin Pin Pin Pin Pin Pin Pin Pin Pin No Name Function No Name Function Name Function 91 5V 121 3 3V 151 EBREQOAs 10 92 GND 122 IRL2 7 152 EBREQOB
75. egister monitors the signal levels of the compact PCI interface interrupt lines When an IRL2 interrupt is requested to the CPU the source of the interrupt can be determined by reading this register To clear the interrupt source access to the corresponding expansion board controller Bit 11 PINT3 0 PCI INTD signal driven low interrupt requested 1 PCI INTD signal driven high interrupt not requested Bit 10 PINT2 0 PCIINTC signal driven low interrupt requested 1 PCI INTC signal driven high interrupt not requested Bit 9 PINTI 0 PCIINTB signal driven low interrupt requested 1 PCI INTB signal driven high interrupt not requested Rev 1 0 09 00 page 101 of 138 RENESAS Bit 8 PINTO 0 PCI INTA signal driven low interrupt requested 1 PCI INTA signal driven high interrupt not requested 2 PCI interrupt mask register PINTMASK Bit p que cm Not used Not used Not used Not used PINTMA PINTMA PINTMA SK3 SK2 SK1 SKO aw R R jw pp h Undetermined This register masks interrupt input from the compact PCI interface When a PINT bit becomes 0 while the corresponding bit in this register is set to 1 the IRL2 signal is input to the CPU Bit 11 PINTMASK3 0 Masks the PCI INTD interrupt 1 Accepts the PCI INTD interrupt Bit 10 PINTMASK2 0 Masks the PCI INTC interrupt 1 Accepts the PCI INTC interrupt Bit 9 PINTMASK1 0
76. er specifications of the LAN91C96 LAN controller For details of the LAN controller refer to the documents released by Standard Microsystems Corporation Table 5 5 LAN91C96 LAN Controller Register Specifications Bank 0 Initial Access BANKO Register Abbrev R W Value Address Size bit Transmit control register TCR R W 0XX0h 07000000 16 EPH status register EPHSR R 0000h 07000002 16 Receive control register RCR R W 0000h 07000004 16 Counter register ECR R 0000h 07000006 16 Memory information register MIR R 1818h 07000008 16 Memory configuration register MCR R W 3300h 0700000 16 Bank select register BSR R W 33XXh 0700000E 16 Table 56 LAN91C96 LAN Controller Register Specifications Bank 1 Initial Access BANK1 Register Abbrev R W Value Address Size bit Configuration register CR RAN XXXXh 07000000 16 Base address register BAR R 1867h 07000002 16 Individual address register IAR RAN XXXXh 07000004 16 Individual address register IAR R W XXXXh 07000006 16 Individual address register IAR R W XXXXh 07000008 16 General address register GPR R W 0000h 07000004 16 Control register CTR R W OXXXh 0700000 16 Bank select register BSR R W 33XXh 0700000E 16 Rev 1 0 09 00 page 84 of 138 RENESAS Table 5 7 LAN91C96 LAN Controller Register Specifications Bank 2 Initial Access BANK2 Register Abbrev R W Value Address Size bit MMU command register MMUCR W 00h 07000000 8
77. ers The interrupt sources and their processing are shown in table 7 5 If an interrupt that is not listed in table 7 5 occurs a sleep instruction will be executed Table 7 5 Interrupt Processing in the Sample Program Interrupt Source Code Processing UBC trap EXPEVT 1E0 Branches the CPU board This processing is used by Step execution Unconditional trap FF EXPEVT 160 Branches to the CPU board This processing is used by breakpoint function Reserved instruction code EXPEVT 180 Branches to the CPU board and informs the exception occurrence of a reserved instruction code exception Slot illegal instruction exception EXPEVT 1A0 Branches to the CPU board and informs the occurrence of a slot illegal instruction exception CPU address error load 0 0 Branches to the CPU board and informs the occurrence of a CPU address error exception CPU address error store EXPEVT 100 Branches to the CPU board and informs the occurrence of a CPU address error exception NMI INTEVT 1CO Branches to the CPU board This processing is used when execution is stopped by using the abort switch SCIF RXI INTEVT 720 Buffers the characters received through the SCIF When the HALT code H 12 is received execution branches to the CPU board This processing is used when execution is stopped by the HAL T button Rev 1 0 09 00 page 138 of 138 RENESAS 5 7751 CPU Board HS7751STC01H User
78. et System Indicates whether the CPU board is connected or not Session Name Displays the session file name Program Name Displays the load module file name Platform Connected to Displays the name of the connected CPU board monitor program CPU Displays the target CPU and endian setting Mode Displays the CPU processor mode privileged mode or user mode Cache Status IC OC Shows whether the cache is enabled or disabled MMU Status Shows whether the MMU is enabled or disabled I O definition Displays the selected I O register definition file Clock Displays the clock frequency CPU operating frequency and external bus frequency being used Target DLL Version Indicates the version of the target DLL for connection to the CPU board Monitor Version Displays the monitor program version Run Status Displays the user program execution status Run Being executed Break Stopped Break Cause Displays the cause of the program stopping at break Run Time Count Shows the time from the start of the user program to the break When the run time count function is disabled Oh Omin Os Oms 0 0us is displayed Comm port baudrate Indicates the data baud rate for the serial interface Memory Target Device Configuration supported by this CPU board System Memory Resources Not supported by this CPU board Loaded Memory Areas Shows the area where the load module is loaded Events Resources Shows the number of breakpoints set Rev 1 0 09 00 page 37 of
79. f the monitor is used with the E10A emulator connected correct operation is not guaranteed Moreover with the E10A emulator connected the port functions of the Hitachi UDI and AUD interface signal pins cannot be used 16 Host Interface Software HDI 1 In this HDI the Command Line menu can be selected but operation of the command entered from the command line cannot be guaranteed Do not use the command line 2 When using this CPU board always use the included Hitachi Debugging Interface HDI If other host interface software is used the operation of the CPU board and of user programs is not guaranteed 3 User can set default radix value with Radix menu from Setup but this setting doesn t take effect at line assemble operation input values are assumed as decimal value Specify or Ox as the radix for a hexadecimal input 4 This HDI does not support software breakpoint setting in the Select Function dialog box described in section 10 Selecting Functions in the Hitachi Debugging Interface User s Manual 5 If the following memory contents are displayed in the Memory window they should be incorrect e Word access from address 2n 1 Longword access from address 4n 1 4n 2 or 4n 3 The font size used in the memory window must be 4 or larger In one window up to 32768 bytes can be displayed 6 For each Watchdog Timer register there are two registers to be used separately for write and read
80. g Array Elements Rev 1 0 09 00 page 42 of 138 RENESAS 3 13 Stepping Through Program The HDI provides a range of step menu commands that allow efficient program debugging Table 3 5 Step Option Menu Command Description Step In Executes each statement including statements within functions Step Over Executes a function call in a single step Step Out Steps out of a function and stops at the statement following the statement in the program that called the function Step Steps the specified times repeatedly at a specified rate Use the Go described in section 3 9 Executing the Program to confirm that the program is executed up to the sort function statement at address H 0C000040 0 000040 Break 0 000050 0 000054 0 0000 0 0000 0 0000 0 0000 0 0000 0 0000 1 020000 sort void sort long long t int i j gap 0 00008 0 000090 while gt 0 1 0 000094 for 0 k lt gap 0 00009 for i ktgap 1 lt 10 i itgap 1 0 0000 9 for jzi gap j j zap l 0c0000b4 if alj 1 1 El Figure 3 25 Program Window Step Execution Rev 1 0 09 00 page 43 of 138 RENESAS 3 13 1 Executing Step In Command The Step In steps into the called function and stops at the first statement of the called function e To step through the sort function select Step In from the Run menu or click the Step In butto
81. guage and in SH series assembly language by the work space of the HEW This program performs echo back of the characters input from the Simulated I O Window window line by line by using the SCIF The sample program files including source and object files are automatically copied to the Sample directory under the HDI installation directory Load the compiled load module Simio abs set the program counter and stack pointer values PC H 0C000000 R15 H AFF80000 and click the Go button to execute the program Simulated L O Window Test Start gt ABCDEFGHIJKLMN Figure 7 1 Executing the Sample Program Note HEW work space supplied by this sample program was created by HEW Version 1 1 Release 3 The program cannot be opened by version earlier than 1 1a For details refer to the Hitachi Embedded Workshop User s Manual Rev 1 0 09 00 page 136 of 138 RENESAS File Configuration Table 7 3 shows the files that compose the sample program Table 73 Sample Program Files File Name install directory Sample Simio hws Description HEW work space file install directory Sample Simio hww HEW HWW file install directory Sample Simio Brkaddr inc Branch address definition install directory Sample Simio Env inc EXPEVT INTEVT register definition install directory Sample Simio Intprg src Interrupt processing program install directory Sample Simio lodefine h
82. hat the jumper pins are correctly inserted into the jumpers on the CPU board Section 2 8 RENESAS Rev 1 0 09 00 page 25 of 138 3 3 HDI Window Hitachi Debugging Jnterface sort 5 7751 CPU board D File Edit View Run Memory Setup Window Help 2508 ERO hw 2 N Source void main void long 10 long j int i min 0 000004 for 120 1 lt 10 i 0 00000 j rand 0 00001 ifGi lt Of 0 000020 02000024 0 000040 0 000050 0 000054 0 000058 0 00005 For Help press F1 Figure 3 4 HDI Window The key features of the HDI are described in section 4 Descriptions of Windows Numbers in figure 3 4 indicate the following Menu bar Gives the user access to the HDI commands for using the HDI debugger Toolbar Provides convenient buttons as shortcuts for the most frequently used menu commands 1 2 3 Program window Displays the source program being debugged 4 Status bar Displays the status of the CPU board and progress information about downloading 5 Help button Activates on line help about any features of the HDI user interface Rev 1 0 09 00 page 26 of 138 RENESAS 3 4 Setting up the CPU Board The following conditions can be set up on the CPU board before downloading the program e Connection method e I O definition file Op
83. he monitor program is using the following CPU functions for debugging purposes User Break Controller UBC Serial Communication Interface with FIFO SCIF 255 Trap instruction 2 If a single step execution is performed for an illegal instruction the program counter will not increment the count do not perform single step executions for illegal instructions 3 When a multiple step execution is performed for a program that contains the SLEEP instruction from the Step menu the execution speed RATE must be set to 6 in the Step Program dialog box Otherwise an error Command not ready error will occur when the SLEEP instruction is executed and execution from then on cannot be accepted In such case press the abort switch SW4 and start execution again 4 The abort switch SW2 input is ORed with the NMI input from the expansion board then input to the NMI pin in the CPU Therefore if the NMI is fixed to low level on the user expansion board the abort switch will not work 5 During single step execution standard C libraries are also executed To return to a higher level function use Step Out In a for statement or a while statement executing a single step does not move execution to the next line To move to the next line execute two steps The monitor program uses NMI and SCIF interrupts so the user can use interrupts of mask level 14 or lower If an interrupt is set to mask level 15 correct operatio
84. he Flush Operand Gache Enable Cache Flush Disable P1 Area write mode PO UO P3 Area write mode Write Through Write Through C Write Back Write Back cancel Figure 4 6 Cache Control Dialog Box Rev 1 0 09 00 page 72 of 138 RENESAS Description The items listed in table 4 9 are displayed and set in the Cache Control dialog box The cache control register settings are displayed when the dialog box is opened When the OK button is clicked the settings are sent to the cache control registers Operation can be specified separately for the instruction cache and operand cache Table 49 Cache Control Dialog Box Items Item Description Instruction Cache Enables or disables the instruction cache Check the Instruction Cache Flush check box then click the OK button to flush all entries from the instruction cache Operand Cache Enables or disables the operand cache Check the Operand Cache Flush check box then click the OK button to flush all entries from the operand cache P1 Area write mode Specifies the operating mode write through or write back for the P1 area P0 UO P3 Area Specifies the operating mode write through or write back for the PO UO write mode and P3 areas 4 2 7 Simulated I O Window Window Function This window displays data input to or output from the serial line during user program execution It is valid only during execution of a
85. ialog box is closed without setting the conditions Rev 1 0 09 00 page 65 of 138 RENESAS 4 2 2 Breakpoints Window Function This window lists all break conditions that have been set This window can be displayed by selecting Breakpoints on the View menu Window Breakpoints Enable File Line Symbol a Sort c 55 change 06000146 PC breakpoint Figure 4 2 Breakpoints Window Rev 1 0 09 00 page 66 of 138 RENESAS Description The Breakpoints window displays breakpoint setting information The items listed in table 4 3 are displayed Table 4 3 Breakpoints Window Display Items Item Description Enable Displays whether the break condition is enabled or disabled The e indicates that the breakpoint is enabled File Line Displays the file name and line number where the breakpoint is set Symbol Displays the symbol corresponding to the breakpoint address If no symbol has been defined for the address a blank is displayed Address Displays the address where the breakpoint is set Type Displays PC breakpoint Right clicking in the Breakpoints window will open a pop up menu through which breakpoints can be set changed deleted enabled or disabled The pop up menu functions are described in table 4 4 Table 44 Window Pop up Menu Operation Menu Description Add Sets break conditions Selecting this menu will disp
86. ing 35 RH to 80 RH no condensation Storage 35 RH to 80 RH no condensation Vibration Operating 2 45 m s max Storage 4 9 5 max Transportation 14 7 m s max Ambient gases Table 1 4 Item Host computer There must be no corrosive gases present Operating Environments Description Built in Pentium or higher performance CPU 200 MHz or higher recommended IBM PC or compatible machine OS Windows 95 Windows 98 or Windows NT Minimum memory capacity 32 Mbytes or more double of the load module size recommended Hard disk capacity Installation disk capacity 5 Mbytes or more Prepare an area at least double the memory capacity four times or more recommended as the swap area CD ROM drive Required to install the HDI Pointing device such as mouse Connectable to the host computer compatible with Windows 95 Windows 98 and Windows NT Power voltage AC power supply adapter Input 100 to 240 VAC 50 60 Hz 0 6 A max Output 5 VDC 5A Rev 1 0 09 00 page 6 of 138 RENESAS Section 2 Preparation before Use 2 1 CPU Board Preparation A WARNING READ the reference sections shaded in figure 2 1 before using the CPU board product Incorrect operation will damage the CPU board and the user expansion board The USER PROGRAM will be LOST Unpack the CPU board and prepare it for use as follows Reference Unpack the CP
87. input to the CPU execution cannot be aborted Bit 8 EXNMIMASK 1 Enables the NMI signal to be input from the EXNMI expansion bus and ICE_NMI the test pin for ROM ICE 0 Masks the NMI signal from the EXNMI and ICE_NMI Rev 1 0 09 00 page 105 of 138 RENESAS 5 6 E10A Emulator Interface The CPU board is equipped with a Hitachi UDI port connector CN23 to which an SH7751 E10A emulator can be connected SH7751 H UDI and AUD signals are connected directly to this connector Figure 5 15 shows the pin arrangement of the Hitachi UDI port connector CN23 Table 5 15 shows the pin assignment for the Hitachi UDI port connector CN23 Hitachi UDI port connector top view Figure 5 15 Hitachi UDI Port Connector CN23 Pin Arrangement Rev 1 0 09 00 page 106 of 138 RENESAS Table 5 15 Hitachi UDI Port Connector CN23 Pin Assignment Pin No Signal Name Input Output Pin No Signal Name Input Output Q1 2 GND 20 GND 3 AUDATAO 21 TRST 4 GND 22 GND 5 AUDATA1 23 TDI 6 GND 24 GND 7 AUDATA2 25 8 GND 26 GND 9 27 10 GND 28 GND 11 AUDSYNC 29 12 GND 30 GND 13 NC 31 RESET 14 GND 32 GND 15 NC 33 GND 16 GND 34 GND 17 TCK 35 18 GND 36 GND Rev 1 0 09 00 page 107 of 138 RENESAS 5 7 On Board LEDs The CPU board has eight LEDs to indicate the operating status such as power or CPU status Figure 5 16 shows the L
88. ircuit CN1 3 95 Figure 5 12 Compact PCI interface CN19 and CN20 Pin Arrangements sss 96 Figure 5 13 CPU Board Power Supply 100 Figure 5 14 Reset Signal Lines uua i erbe cbe SER 100 Figure 5 15 Hitachi UDI Port Connector CN23 Pin 106 Figure5 16 LED Locations erae nente tette teret eee SAB eben epe node oo va spe Ue pase reason 108 Figure 5 17 Parts Layout Mounting Side essere 113 Figure 5 18 Procedure for Setting BSC 116 Rev 1 0 09 00 page vii of x RENESAS Figure 6 1 Figure 6 2 Figure 6 3 Figure 6 4 Figure 7 1 Error Message Displayed at Exception Instruction TLB Miss Exception 124 Dialog Box Indicating Breakpoint Cannot Be 2 402222 2 124 Power on Reset Input Message 125 Manual Reset Input Message 125 Executing the Sample 2 136 Rev 1 0 09 00 page viii of x RENESAS Table Table 1 1 CPU Board Component List 4 12 CD R Contents see ertet E RT 5 Table 1 3 Environmental Conditions 2 nen enne nre 6 Table 1 4 Operating Environments orna tent see oen o 6 Table 2 1 Default Installation Directory
89. l timer of the SH7751 to implement run time count functions So the user program cannot use channel 4 of the timer 2 The run time count function is only valid when user program execution has been started by selecting Go from the Run menu The run time is not measured during single step execution 3 The overhead due to run time measurement is about 10 us per execution For example the execution time of one NOP instruction measured is about 10 us The values displayed as Cache Status and MMU Status in the Status window are the values for the last break that occurred during user program execution Values as updated in the I O Registers window are not displayed in the Status window 6 2 Troubleshooting On starting the HDI the Link up message does not appear Check the following The power on monitor LED LED22 on the CPU board should be lit The host computer and CPU board should be properly connected by a serial cable The port settings and transfer rate in the Monitor Setup dialog box should be correct The CPU board jumper settings should be correct Ilegal general instruction appears on the HDI status bar and program execution is halted This is displayed when a general exception occurs This message appears when the EXPEVT register value is 180 It is caused by use of a privileged instruction in user mode by use of an undefined instruction or for similar reasons For further information refer t
90. lay the Add Edit Breakpoint dialog box enabling break conditions to be set Edit Changes break conditions Select break conditions to be changed and select this menu The Add Edit Breakpoint dialog box will be displayed enabling the break condition to be changed Disable Enables or disables break conditions Select break conditions to be Enable enabled or disabled and select this menu Delete Clears break conditions Select break conditions to be cleared and select this menu Del Clears all break conditions Go to Source Jumps to the break address in the Source window Rev 1 0 09 00 page 67 of 138 RENESAS 4 2 3 Add Edit Breakpoint Dialog Function Sets a breakpoint This dialog box is displayed when the Add or Edit is selected in the pop up menu in the Breakpoints window which is displayed by selecting the Breakpoints item on the View menu Window Add Edit Breakpoint x Breakpoint address change Enable Figure 4 3 Add Edit Breakpoint Dialog Box Description The Add Edit Breakpoint dialog box is made up of the components listed in the table below Table 4 5 Add Edit Breakpoint Dialog Box Items Item Description Breakpoint address Enter the address or symbol for which a breakpoint is to be set Enable The breakpoint is enabled when this box is checked After clicking OK the breakpoint is set Rev 1 0 09 00 page 68 of 138 RENESAS
91. list then click Add Remove Rev 1 0 09 00 page 9 of 138 RENESAS 2 4 Connecting Cables Figures 2 4 to 2 6 show how to connect interface cables to the CPU board A WARNING Always switch OFF the CPU board and the user system before connecting or disconnecting any CABLES CONNECTORS or JUMPERS Failure to do so will result in a FIRE HAZARD and will damage the user system and the CPU board or will result in PERSONAL INJURY The USER PROGRAM will be LOST user system interface cable Connect to CN23 CPU board Figure 2 4 E10A User System Interface Cable Connection Rev 1 0 09 00 page 10 of 138 RENESAS gt TN Connect to CN15 interface cable Figure 2 5 Serial Interface Cable Connection A WARNING Always switch OFF the CPU board and the user system before connecting or disconnecting any CABLES Failure to do so will result in a FIRE HAZARD and will damage the user expansion board and the CPU board or will result in PERSONAL INJURY The USER PROGRAM will be LOST Figure 2 6 AC Adapter Connection Rev 1 0 09 00 page 11 of 138 RENESAS 2 5 Connecting the User Expansion Board Figure 2 7 shows how to connect the user expansion board A WARNING Always switch OFF the CPU board and the user system before connecting or disconnecting any CABLES CONNECTORS or JUMPERS Failure to do so will result in a FIRE HAZARD and will damage the user system and the
92. ly injury such as aerospace aeronautics nuclear power combustion control transportation traffic safety equipment or medical equipment for life support Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating operating supply voltage range heat radiation characteristics installation conditions and other characteristics Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges Even within the guaranteed ranges consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail safes so that the equipment incorporating Hitachi product does not cause bodily injury fire or other consequential damage due to operation of the Hitachi product This product is not designed to be radiation resistant No one is permitted to reproduce or duplicate in any form the whole or part of this document without written approval from Hitachi Contact Hitachi s sales office for any questions regarding this document or Hitachi semiconductor products IMPORTANT INFORMATION READ FIRST READ this user s manual before using this CPU board KEEP the user s manual handy for future reference Do not attempt to use the CPU board until you fully understand its mechanism CPU Board Throughout this document the term CPU board shall be defined as the following products produced
93. m of the CPU board is shown in figure 5 1 ca SH7751 FLASH Expansion 32 5 bus J IDE FPGA EPROM interface CPU Crm sc Cte Cre Comey TO por RU PCI connector User expansion User Compact PCI bus TOBASES connector Micro ribbon Debug Serial Product Seria ort Port Figure 5 1 Block Diagram of the CPU board Rev 1 0 09 00 page 75 of 138 RENESAS 5 2 Specifications Table 5 1 lists the components of the CPU board Table 5 1 External Specifications Item Specifications Microcomputer U1 SH7751 name HD6417751F 167 Package 256 pin QFP Operating frequency CPU internal clock 167 MHz Bus clock 83 5 or 55 7 MHz switchover by jumpers Endian Little or big endian switchover by jumpers Memory RAM SDRAM Capacity 64 Mbytes M1 M2 Bus width 32 bits Type number HM5225165TT A60 x 2 ROM EPROM only the socket is Capacity 512 kbytes 7 mounted Bus width 16 bits Type number HN27C4096A x 1 ROM Flash memory monitor Capacity 32 Mbytes M3 M6 program Bus width 32 bits Serial interface CN15 Type number G28F640J5 150 x 4 One channel Conforms to RS 232C Transfer rate 57600 or 115200 bit s switchover by jumpers Connector 9 pin D sub connector Connector on CPU board DELC J9PAF 20L9 manufactured by Japan Aviation Electronics Industry Ltd Cable length 1 5 m use the supplied cable
94. n cannot be guaranteed The default mask level is set to 14 Interrupt and Exception Display 1 The following interrupts and exceptions are displayed on the status bar during user program execution e Address error Illegal general instruction Illegal slot instruction e NMI 2 When an exception occurs on the CPU board while the user program is not being executed the HDI will display the EXPEVT code that corresponds to the cause of the exception and the monitor program will enter the reset input wait state In this case turn the power to the CPU board off and on or input a reset and start the HDI to initiate link up processing Rev 1 0 09 00 page 123 of 138 RENESAS ed from monitor Exception occured 0 00000040 Please reset the GPU board Figure 6 1 Error Message Displayed at Exception Instruction TLB Miss Exception 4 Breakpoints 1 Breakpoints cannot be set in a delay slot of a user program If an attempt is made to set such a breakpoint the following message appears Gannot set a breakpoint at the specified address Figure 6 2 Dialog Box Indicating Breakpoint Cannot Be Set For the above reason a breakpoint may not be set if the initial data in the RAM is invalid when a user program is loaded by specifying a session file In this case reload the program by respecifying the session file 2 If a breakpoint is set within an interrupt or exception handler of a user program it will not
95. n in the toolbar m Figure 3 26 Step In Button Sort c 21 0000040 Break sort 22 0 000050 min 0 23 0000054 9 24 0000058 min 0 25 0 00005 0 26 05000060 27 02000070 min 9 28 0 000074 0 29 0 000078 30 31 0000088 sort sort long 32 33 long t 34 int i j gap 35 36 0 00008 gap 5 37 0 000090 gap gt 38 0 000094 for 0 k lt gap 39 0 00009 for izk zap 1 lt 10 izitgap 40 0 0000 9 for jzi gap j gt k j j gap 41 DcD000b4 if alj gt aljt gap 1 Figure 3 27 Program Window Step In e The highlighted line moves to the first statement of the sort function in the Program window Rev 1 0 09 00 page 44 of 138 RENESAS 3 13 2 Executing Step Out Command The Step Out steps out of the called function and stops at the next statement of the calling statement in the main function e To step out of the sort function select Step Out from the Run menu or click the Step Out button in the toolbar LM Figure 3 28 Step Out Button interface sort SH 751 CPU board File Edit Miew 5n Memory Em Window Help F GE cm e TERAS WEB fine i Sortec Watch Window Line Address Label Source 0 000000 main p main void o long 10 long j int i min max for 120 1
96. ning of the program by using the following procedure e Click the left of displayed array a in the Program window to position the cursor Click the Program window with the right mouse button and select Instant Watch from pop up menu The following dialog box will be displayed Instant Watch Add Watch Figure 3 20 Instant Watch Dialog Box Rev 1 0 09 00 page 40 of 138 RENESAS e Click Add Watch button to add a variable to the Watch Window window Watch Wind ow m x Value 4 1 Figure 3 21 Watch Window Window Displaying the Array The user can also add a variable to the Watch Window window by specifying its name Click the Watch Window window with the right mouse button and select Add Watch from the pop up menu The following dialog box will be displayed Add Watch Figure 3 22 Add Watch Dialog Box Rev 1 0 09 00 page 41 of 138 RENESAS e Input variable max and click the OK button The Watch Window window will now also show the long type variable max Watch Window LE EE Value xaff ffd4 max 070 Figure 3 23 Watch Window Window Displaying the Variable The user can double click the symbol to the left of array a to watch the all elements in array a Watch Window o 0 1 2 3 4 5 8 7 8 9 Figure 3 24 Watch Window Window Displayin
97. nitializing Resources Table 5 18 shows which CPU board resources are initialized Table 5 18 Resource Initialization Cause of Initialization Start up or Power On Reset Manual Reset Switch Switch Pressed Pressed Interrupt Monitor Monitor Resource Hardware Program Hardware Program Remarks SH7751 CPU MMU m TLB UBC WDT 5 TMU m RTC SCI SCIF Used by monitor PCIC PORT AUD Initialized by TRST H UDI mE Initialized by TRST ASERAM Initialized by TRST Rev 1 0 09 00 page 114 of 138 RENESAS Table 5 15 Resource Initialization cont Cause of Initialization Start up or Power On Reset Manual Reset Switch Switch Pressed Pressed Interrupt Monitor Monitor Resource Hardware Program Hardware Program Remarks Interrupt controller On board register SDRAM Monitor program work area SDRAM User program area Notes 1 Initialized Not initialized 2 When during HDI and CPU board operation a power on reset occurs due to a power supply voltage drop or for other reasons a Power on reset is detected messag
98. no responsibility for any damage liability or other loss rising from these inaccuracies or errors Please also pay attention to information published by Renesas Technology Corporation by various means including the Renesas Technology Corporation Semiconductor home page http www renesas com When using any or all of the information contained in these materials including product data diagrams charts programs and algorithms please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products Renesas Technology Corporation assumes no responsibility for any damage liability or other loss resulting from the information contained herein Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes such as apparatus or systems for transportation vehicular medical aerospace nuclear or undersea repeater use The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials If these products or technologies are subject to the Japanese export control restrictions they must be exported
99. o the SH7751 Hardware Manual When a privileged instruction has been used in user mode please take the following steps In the register window change the SR status register MD bit to privileged mode Or execute the Reset CPU command on the Run menu and set the register values to the following initial values Table 6 2 Register Initial Value Settings Register Initial Value Description PC 000000 User program area start address SR H 600000E0 Privileged mode mask level 14 R15 SP H AFF80000 Final address of user program area VBR H A0080000 big endian Monitor VBR different from actual chip H A0100000 little endian 3 Step command execution is slow Rev 1 0 09 00 page 129 of 138 RENESAS When the watch window and register window are open the data these windows must rewritten each time a step is executed and so execution speed will be reduced Decrease the sizes of these windows to speed execution Rev 1 0 09 00 page 130 of 138 RENESAS Section 7 Creation of User Interrupt Handlers 7 1 Creation of User Interrupt Handlers Cases where exceptions and interrupts are not used in the user program no user interrupt handlers are created Set the value of VBR to the initial value big endian A0080000 little endian 0100000 doing so step execution breaks and other debugging functions can be used when an exception or interrupt occur
100. ower Supply Specifications Figure 2 13 shows the power supply specifications and figure 2 14 shows the block diagram of the power supply section Power on reset_N Figure 2 13 Power Supply Specifications Power connector 5V On board logic Expansion 3 3 V m bus PCI connector connector LT1084 8 3 V 5V gt 3 3V LT1084 VCCIO Regulator 3V 18V Regulator vec GND SW1 1 SW1 2 are included one component They are switched on or off at the same time Figure 2 14 Power Supply Section Block Diagram Rev 1 0 09 00 page 20 of 138 RENESAS 2 9 2 Connecting the Power Supply Cable Power should always be supplied to the CPU board using the provided AC power supply adapter and AC power supply cable The method of connection is shown in figures 2 15 and 2 16 A WARNING Observe the precautions listed below Failure to do so will result FIRE HAZARD and will damage the user system and the CPU board or will result in PERSONAL INJURY The USER PROGRAM will be LOST 1 Always use the provided AC power supply adapter 2 Always switch OFF the CPU board and the user system before connecting or disconnecting any CABLES CONNECTORS or JUMPERS Figure 2 15 Front View of Power Supply Connector Rev 1 0 09 00 page 21 of 138 RENESAS CPU board top view Figure 2 16 AC Power Supply Adapter Connection Rev 1 0 09 00 page 22 of 138 RENESAS Section 3 Tutorial 3 1 Introd
101. pins Do not drive these signals from the user expansion board To obtain the bus mastership use the EBREQx and EBACKx signals b SCIF related signals The HDI uses these signals to communicate with the host computer Do not drive these signals from the user expansion board 6 H UDl related signals The E10A emulator uses these signals Do not drive these signals from the user expansion board 7 IRL2 The CPU signal is directly connected to the connector pin Do not drive this signal from the user expansion board To request external interrupts use the IRLO IRL1 IRL3 and EXINT4 signals 8 RESET MRESET NMI ORed with the related logic on the CPU board then input to the CPU Refer to figure 5 9 9 RDY Pulled down on the CPU board Control the signal so that it goes high at wait cycle insertion and enters the high impedance state in other cases 10 Bus release signals These signals go through the related logic on the CPU board and are used to generate the BREQ signal for the CPU For the bus release timing refer to figures 5 6 and 5 7 11 CS3 Signal for monitoring the status on the CPU board This signal is used by the CPU board do not drive this signal from the user expansion board 12 CKIO and B CKIO As the CKIO output from the CPU is output to the user expansion board interface through an external PLL no phase error is guaranteed 150 ps max As the output from the CPU is outpu
102. ponent list after unpacking the CPU board 2 Never place heavy objects on the CPU board 3 Protect the CPU board from excessive impacts and stresses For details refer to section 1 6 Environmental Conditions 4 Do not connect any cable or connector other than specified ones to the CPU board 5 When moving the host computer or user expansion board take care not to vibrate or damage the CPU board 6 After connecting the cable check that it is connected correctly For details refer to section 2 Preparation before Use 7 Supply power to the connected equipment after connecting all cables Cables must not be connected or removed while the power is on Rev 1 0 09 00 page 3 of 138 RENESAS 1 4 Components Table 1 1 lists the components of the CPU board Check all components after unpacking Table 1 1 Board Component List Item View Quantity Remarks CPU board 1 One printed circuit board AC power 1 supply adapter K 1 supply cable ety t Serial interface 1 cable A Jumper 4 Front panel 1 For use in a compact PCI rack Debug Serial Port LAN I F C MRST PRSTABORT provided with handles CD R 1 One CD R HDI installer lt Model number HS7751STC01SR contains CPU board manual and HDI manual SH7751 CPU 2 One Japanese Board version and one Installation English version Guide Japanese E HS7751STC01HJ P English HS7751STC01HE P Rev 1 0 09
103. r duplicated in any form in hard copy or machine readable form by any means available without Hitachi s prior written consent Other Important Things to Keep in Mind 1 Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi s semiconductor products Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein 2 No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi Figures Some figures in this user s manual may show items different from your actual system Limited Anticipation of Danger Hitachi cannot anticipate every possible circumstance that might involve a potential hazard The warnings in this user s manual and on the CPU board are therefore not all inclusive Therefore you must use the CPU board safely at your own risk Rev 1 0 09 00 page III of VI RENESAS SAFETY PAGE READ FIRST READ this user s manual before using this CPU board KEEP the user s manual handy for future reference Do not attempt to use the CPU board until you fully understand its mechanism DEFINITION OF SIGNAL WORDS A This is the safety alert symbol It is used to alert you to potential personal injury hazards Obey all safety messages that follow this symbol to avoid possible injury or death DANGER
104. register information Download with verify The CPU board does not support this function this box cannot be selected Delete breakpoints Unchecked When this box is checked all breakpoints are deleted when when program is a program is reloaded reloaded Reset CPU when Unchecked When this box is checked registers are initialized when a program has been downloaded Note program is loaded No reset signal is input to the CPU board Initialized as follows PC H AC000000 SR 600000 0 and VBR H A0080000 big endian or H A0100000 little endian Click the OK button Rev 1 0 09 00 page 28 of 138 RENESAS 3 6 Downloading the Tutorial Program 3 6 1 Downloading the Tutorial Program Download the object program to be debugged e Select Load Program from the File menu The Load Program dialog box is displayed Enter the offset and file name in the Offset edit box and File name list box as shown in figure 3 6 and click the Open button Load Program x Offset Open wo Verify Cancel File name C Hew Hdi5 Cb47751 ST utorial S ort abs v Load only debugging information Load stack information file SNI file Figure 3 6 Load Program Dialog Box When the file has been loaded the following message box displays information about the memory areas that have been filled with the program code HDI A Module name C HewSHdi5 Cb47751 Tutorial S ort abs
105. s Cases where exceptions and interrupts are used in the user program user interrupt handlers are created Set the value of VBR to the start address of the user interrupt handler By doing so execution will branch to the user interrupt handler when an exception or interrupt occurs Add a routine to branch to the following addresses to the user interrupt handler this will enable step execution breaks and other debugging functions when an exception or interrupt occurs Table 7 1 lists the branch addresses for different interrupt causes Table 7 1 Branch Address Interrupt Causes and Branch Addresses for User Interrupt Handlers Branch Address Interrupt Cause Code Big Endian Little Endian UBC trap EXPEVT 1E0 H A0082000 H A0102000 Unconditional trap FF EXPEVT 160 H A0082020 H A0102020 Reserved instruction code 180 H A0082040 H A0102040 exception Slot illegal instruction EXPEVT 1A0 H A0082060 0102060 exception CPU address error load EXPEVT 0E0 H A0082080 0102080 CPU address error store EXPEVT 100 H A0082080 H A0102080 NMI 1 0 H A00820C0 H A01020C0 SCIF RXI INTEVT 720 H A00820E0 H A01020E0 Note When the SCIF is not used a program to branch to the SCI RXI destination address must be prepared RENESAS Rev 1 0 09 00 page 131 of 138 Attention should be paid to the following when creating an interrupt handler 1 When branching to
106. s F1 Figure 3 33 Program Window Step Over When the last statement of the change function is executed the datas of array a which is displayed in the Watch Window window is sorted in descending order Rev 1 0 09 00 page 48 of 138 RENESAS 3 14 Displaying Local Variables The user can display local variables in a function using the Locals window For example we will examine the local variables in the main function which declares five local variables a j i min and max e Select Locals from the View menu The Locals window is displayed If no local variable exists none is displayed on the Locals window e Select Step In from the Run menu to execute another step The local variables and the corresponding values are displayed in the Locals window Locals ue X ffiffd4 Figure 3 34 Locals Window Double click the symbol in front of array a in the Locals window to display the elements of array a e When the elements of the array a are referenced before and after executing the sort function in the program the random data should be sorted in descending order This confirms that the program 18 operating normally Rev 1 0 09 00 page 49 of 138 RENESAS 3 15 Software Break Function The CPU board has software break function With the HDI a software breakpoint can be set using the Breakpoints window The CPU board can set up to 255 software breakpoints Setting a software
107. s of ROM ICE use the NMI and RESET signals of the CPU to implement debugging functions In this CPU board these signals are assigned to TP56 and TP57 TP56 Reset input ORed with the logic on the board to create the _RESET signal for the CPU TP57 NMI input ORed with the logic on the board to create the signal for the CPU This input can be masked by using the on board register NMIMASK 5 4 3 LAN Interface WARNING Always switch OFF the CPU board and the user system before connecting or disconnecting any CABLES or CONNECTORS Failure to do so will result in a FIRE HAZARD and will damage the user system and the CPU board or will result in PERSONAL INJURY The USER PROGRAM will be LOST The CPU board has one channel of LAN interface to which the user application program can access The LAN91C96 LAN controller manufactured by Standard Microsystems Corporation is used to support interface The MAC address and configuration information are stored in the EEPROM M93C46 manufactured by STMicroelectronics on the CPU board Be careful not to modify the contents of the EEPROM accidentally The MAC address in the EEPROM is also displayed on the board Rev 1 0 09 00 page 83 of 138 RENESAS Note that the monitor program of the CPU board does not include the LAN interface driver the driver software must be prepared as part of the user program to use the LAN interface Tables 5 5 to 5 9 list the regist
108. set breakpoints e Set the program counter and stack pointer values that have been set in section 3 8 Setting Registers PC H 0C000000 R15 H AFF80000 in the Registers window Click the Go button The program runs and stops at the breakpoint Line Address Source 0000000 mai TIT main void long a 10 long j int i min max 0 000004 1 0 1410 i 0 00000 j PR 0 00001 itU 0 0000020 j j 0 000024 ali J 0 000040 Break 0 000050 e Break 0 000054 02000058 0 00005 0 000060 0 000070 0 000074 0 000078 0 1 2 3 4 5 B 1 8 9 0 T II tiga l ott tt li m ws 7 Figure 3 40 Program Window Break before Run Time Count e Select Status from the View menu The System Status window will appear Rev 1 0 09 00 page 53 of 138 RENESAS System Status Item Connected to CPL Node Cache Status IC OC MMU Status 1 0 definition Clock Target DLL Version Monitor Version Run Status Break Cause Run Time Count Comm port baudrate Status SH4 Monitor SH7751 Biz Endian Privileged Mode OFF OFF OFF CPU 167 MHz External 83 5 MHz mm dd Break Breakpoint Oh Omin 05 Oms 0 0 57600 bit s h Session Platform Memory 4 Events i Figure 3 41 System Status Window Run Time Count Disabled The
109. system Rev 1 0 09 00 page V of VI RENESAS Rev 1 0 09 00 VI of VI RENESAS Preface Thank you for purchasing the CPU board for Hitachi s SH7751 microcomputer The CPU board is an efficient development tool for software and hardware of systems based on Hitachi s SH7751 microcomputer This manual explains the functions and method of operation of the CPU board Section 1 Overview describes the hardware system configuration and explains environment settings to enable board use Section 2 Preparations Before Use explains procedures for using the CPU board HDI installation various connections and the power supply specifications Section 3 Tutorial introduces the major HDI features while demonstrating methods for loading and debugging a C language program Section 4 Descriptions of Windows describes each of the windows used in the HDI Section 5 CPU Board Specifications explains the specifications of the CPU board the memory map interfaces with external equipment and CPU board initialization Section 6 Notes and Troubleshooting explains important information regarding use and gives suggestions for troubleshooting Section 7 Creation of User Interrupt Handlers explains how to create an original interrupt handler routine Please read this manual completely in order to gain a thorough understanding of this product s functions and performance The text appearing in the various windows of
110. t in a FIRE HAZARD due to contact between the CPU board and another board and will damage the PCI system and the CPU board or will result in PERSONAL INJURY The USER PROGRAM will be LOST Note Before connecting the CPU board to the compact PCI backplane turn off SW1 to separate the 3 3V generator on the CPU board In this case the CPU board receives the 5 3 3V power from the backplane and operates with the 3 3V interface see figure 5 13 Figure 5 12 Compact PCI interface CN19 and CN20 Pin Arrangements Rev 1 0 09 00 page 96 of 138 RENESAS Table 5 12 Compact PCI Interface J1 Connector CN19 Pin Assignments Pin Pin Pin Pin Pin Pin Func Pin Pin Func Pin Pin Func Pin Pin Func Pin Pin Func tion No tion No Name tion No Name tion tion A1 5V B1 12V C1 TRST 01 12V E1 5V A2 TCK B2 5V C2 TMS D2 TDO E2 TDI INTA 1 INTB 1 C3 INTC 1 5 INTD 1 A4 Reserve B4 GND V O 7 D4 6 E4 INTS 6 A5 Reserve B5 Reserve c5 RST D5 GND E5 GNT A6 REQ B6 GND 3 3V D6 CLK E6 AD31 A7 AD30 B7 AD29 C7 D7 GND E7 AD27 8 AD26 B8 GND V O 7 08 AD25 024 A9 B9 IDSEL 9 AD23 D9 GND E9 AD22 A10 AD21 B10 GND C10 3 3V D10 AD20 E10 AD19 A11 AD18 B11 AD17 C11 AD16 D11 GND E11 C BE2 A12 B12 C12 D12 E12 A13 B13 C13 D13 E13 A14 B14 C14 D14 E14 A15 3 3V B15 FR
111. t to the user expansion board interface through a bus buffer the signal has a high drivability but a large delay 3 6 ns max expansion bus lt r q BREQ tBREQS CPU BACK 1 tCOFF1 A RD CSn RD WR CAS RAS WEn g expansion bus tCOFF2 D expansion bus Figure 5 6 Release Timing 1 Rev 1 0 09 00 page 90 of 138 RENESAS expansion bus 4 tBREQH tBACKD expansion bus BACK CPU tCBACKD BACK expansion bus A RD RD WR CAS RAS WEn expansion bus D expansion bus Figure 5 7 Bus Release Timing 2 Table 511 Specifications Parameter Minimum Maximum tBREQH 1 5 ns tBREQS 6 0 ns tBACKD tCBACKD 10 0 ns tCOFF1 8 0 ns tCOFF2 17 0 ns tCON1 8 0 ns tCON2 17 0 ns Note Equivalent to CPU AC specifications Rev 1 0 09 00 page 91 of 138 RENESAS SH7751 CPU board User expansion board 3 3 V Characteristic impedance Zo 540 100 the line between the expansion bus 2 LVT series connector and receiver VHC series loh 12 lol 12 mA as short as possible etc B output buffer 74ALVCH16245 100 mm or shorter loh 24 lol 24 mA gt output buffer 74CDC2509B 5 9
112. te measures such as 1 placement of substitutive auxiliary circuits ii use of nonflammable material or 111 prevention against any malfunction or mishap Notes regarding these materials 1 These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer s application they do not convey any license under any intellectual property rights or any other rights belonging to Renesas Technology Corporation or a third party Renesas Technology Corporation assumes no responsibility for any damage or infringement of any third party s rights originating in the use of any product data diagrams charts programs algorithms circuit application examples contained in these materials All information contained in these materials including product data diagrams charts programs and algorithms represents information on products at the time of publication of these materials and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons Itis therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein The information described here may contain technical inaccuracies or typographical errors Renesas Technology Corporation assumes
113. that conforms to RS 232C is provided The Hitachi Debugging Interface HDI is also provided as host interface software e Enables user program evaluation Up to 63 5 Mbytes of a user program can be loaded into the user memory and be evaluated e Support for compact PCI interface The SH7751 provides PCI interface functions The CPU board outputs the on chip PCI bus interface signals through the compact PCI connector This interface conforms to the PICMG2 0 rev 2 1 and the CPU board functions can be easily expanded by connecting to a standard backplane Figure 1 1 CPU Board External View Rev 1 0 09 00 page 1 of 138 RENESAS 1 2 System Configuration The system configuration of the CPU board is shown in figure 1 2 The following items are required to use the CPU board e IBM PC compatible machine One for the monitor command input and output One serial interface cable Use the provided cable One AC power supply adapter Use the provided adapter One AC power supply cable Use the provided power cable AC power supply adapter rJ E PC compatible Figure 1 2 CPU Board System Configuration Rev 1 0 09 00 page 2 of 138 RENESAS 1 3 Warnings CAUTION READ the following warnings before using the CPU board Incorrect operation will damage the user system and the CPU board The USER PROGRAM will be LOST 1 Check all components against the com
114. the HDI may differ from those appearing in this manual depending on the language of the OS being used The figures appearing in this manual are for the Microsoft Windows 98 Related Manuals e SH7751 Hardware Manual e SH4 Programming Manual e SH Series Cross Assembler User s Manual e SH Series C Compiler User s Manual e SH Series Simulator Debugger User s Manual e Hitachi Debugging Interface User s Manual available in the CD R supplied with this CPU board When connecting an E10A emulator to the CPU board the following manual should also be read Rev 1 0 09 00 page i of x RENESAS SH7751 E10A Emulator User s Manual Notes 1 IBM PC is a registered trademark of International Business Machines Corporation the United States 2 Microsoft Windows and WindowsNT are registered trademarks of Microsoft Corporation in the United States and or other countries Rev 1 0 09 00 page ii of x RENESAS Contents EVE M 1 TIME 1 1 2 2 22 KESA 2 1539 dei GO E 3 1 4 Components seron e 4 TS CD R Contents 5 1 6 Environmental 1801 6 Section 2 Preparation before Use 7 2 CPU Board Prepara
115. ting 123 OL 123 6 2 Proubleshoot inp aio eae ere ere ono ea pae 129 Section 7 Creation of User Interrupt Handlers 131 71 Creation of User Interrupt Handlers 220242 0 011 000 eene 131 7 4 UserProgram Using SCIF aaa err err rr epe a perenne aue 133 121 Creation of Diver x a nr eere ee caver cho Poco theses 133 Rev 1 0 09 00 page iv of x 722 SCIF Related Register 133 7 3 Sample Program ee rtr 136 Rev 1 0 09 00 page v of x RENESAS Figure Figure 1 1 Figure 1 2 Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 Figure 2 5 Figure 2 6 Figure 2 7 Figure 2 8 Figure 2 9 Figure 2 10 Figure 2 11 Figure 2 12 Figure 2 13 Figure 2 14 Figure 2 15 Figure 2 16 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 3 8 Figure 3 9 Figure 3 10 Figure 3 11 Figure 3 12 Figure 3 13 Figure 3 14 Figure 3 15 Figure 3 16 Figure 3 17 Figure 3 18 Figure 3 19 Figure 3 20 Figure 3 21 Figure 3 22 Figure 3 23 Figure 3 24 CPU Board External 1 CPU Board System 2 CPU Board Preparation Flow Chatrt 7 Setup exe 8 Start
116. tion 7 220 HDFinstallatiOn 8 2 3 HDI Uninst llation a a nn S 9 244 Connecting Cables iei eerie 10 2 5 Connecting the User Expansion Board esses 12 2 6 Connecting the Compact PCI Backplane eee 13 2 1 16 28 I C vnm 17 295 Power Supply su uya E PEE RU DU e D cipe ipe rie et eed 20 2 9 1 Power Supply eene enne 20 2 9 2 Connecting the Power Supply 21 T fofal Q u unn H 23 MMO AU Ct OM ERREUR 23 3 2 Ruining the A m S nhi CREE IPS 24 2 27 26 34 Setting CPU UR ERE MER tete 27 3 5 Setting the Monitor Setup Dialog Box esee 27 3 6 Downloading the Tutorial Program 29 3 6 1 Downloading the Tutorial Program 29 3 6 2 Displaying the Source Program 30 3 7 Setting the Software sess rennen 32 3 8 Setting ioo Ge ERR NS GEHE HE s 33 29 Ex cutine the M 35 3 10 Reviewing 38 3 11 VAC WINE
117. tions on program load The following describes how to set up the CPU board for the tutorial programs 3 5 Setting the Monitor Setup Dialog Box e Select Configure Platform from the Setup menu to set configuration The Monitor Setup dialog box is displayed Monitor Setup Download with werte Delete breakpoints when program is reloaded Reset CPU when program has been downloaded Figure 3 5 Monitor Setup Dialog Box Notes 1 The I O register definition file can be selected in this dialog box Be sure to select a file within the HDI installation directory Otherwise the I O register window will not operate correctly 2 The name of the I O register definition file can consist of up to nine characters This number does not include the file name s extension Rev 1 0 09 00 page 27 of 138 RENESAS e Set options as follows Table 33 Setting the Monitor Setup Dialog Box Option Default Value Comms Port 1 Select from among 1 2 as the host computer serial port Baud Rate 115200 Sets the serial baud rate Select either 57600 bit s or 115200 bit s to match the setting of jumper J36 Connection is not possible at any other setting I O definition file SH7751 Sets the register definition file The SH7751 definition file is set as default On selecting a file the Registers window accessed from the View menu can be used to display
118. u Cut Copy Paste Find Evaluate Rev 1 0 09 00 page 61 of 138 RENESAS 4 1 View Menu HDI Window Menus and Related Manual Entries cont Pull Down Menu Breakpoints Hitachi Debugging Interface User s Manual This Manual 3 10 3 15 4 2 2 Command Line Disassembly Area Labels Locals 3 14 Memory 3 11 Performance Analysis Profile List Profile Tree Registers 3 8 Source 3 6 2 Status 3 9 4 2 4 Trace Watch Cache Control 4 2 6 Run Time 3 16 4 2 5 Localized Dump Simulated I O Window 4 2 7 Run Menu Reset CPU Go 3 9 Reset Go to Cursor Set PC To Cursor Run Step In 3 13 1 Step Over 3 13 3 Step Out 3 13 2 Step Halt Rev 1 0 09 00 page 62 of 138 OF OF RENESAS 4 1 Pull Down Menu Refresh Hitachi Debugging Interface User s Manual HDI Window Menus and Related Manual Entries cont This Manual Load Save Verify Test Fill Copy Compare Configure Map Configure Overlay Setup Men
119. u Status bar Options Radix Customise Configure Platform Window Menu Cascade Tile Arrange Icons Close Help Menu Notes Index Using Help Search for Help on About HDI Function not supported Only CPU board ROM and RAM information display is supported User program is executed after setting PC to H AC000000 Function for test use Correct operation cannot be guaranteed PC SR and VBR are initialized The reset signal is not sent to the CPU OO O O CO OC O OO OO O O RENESAS Rev 1 0 09 00 page 63 of 138 4 2 Descriptions of Each Window This section describes each window 4 2 1 Monitor Setup Dialog Box Function Specifies the setup conditions for the CPU board This dialog can be displayed by selecting Configure Platform from the Setup menu Window Monitor Setup Target Monitor Comms Settings Comms Port Baud Rate 115200 1 0 definition file SH7751 Download with veny Delete breakpoints when program is reloaded Reset CPU when program has been downloaded Figure 4 1 Monitor Setup Dialog Box Notes 1 The I O register definition file can be selected this dialog box Be sure to select a file within the HDI installation directory Otherwise the I O register window will not operate correctly 2 The name of the I
120. uction The following describes the main features of the HDI by using a tutorial program The tutorial program is based on the C program that sorts ten random data items in ascending or descending order The tutorial program is included in the Sort c file in the HDI installer CD R The compiled load module is provided in the SYSROF format and is included in the Sort abs file The tutorial program is automatically installed when the HDI is installed Table 3 1 lists the tutorial program configuration Table 31 Tutorial Program Configuration Item Contents Tutorial file load module install directory Tutorial Sort abs Tutorial file source file install directory Tutorial Sort c This sample program uses the RAM area starting from address 0 000000 The MMU function is not used Notes 1 Sort abs operates in big endian Sort abs must be recompiled to operate in little endian 2 The work space for this tutorial program was created using Version 1 1a Release 3 of Hitachi Embedded Workshop HEW Hitachi SH compiler version 5 1B Hitachi SH IM OptLinker version 1 1B Rev 1 0 09 00 page 23 of 138 RENESAS 3 2 Running HDI To run the HDI select the HDI for SH7751 CPU Board from the Start menu eme EN unus Hdd 2 Hitachi Embedded Workshop Recycle Bin HDI for Internet Explorer Windows Update Microsoft Input Devices r 7 f for SH7751 CPU board
121. ure 3 29 Program Window Step Out a 45 Figure 3 30 Program Window Step In Step 46 Figure 3 31 Step Over Button eee eerie tee peret terere lena rece asus 47 Figure 3 32 Program Window Before Step Over Execution 47 Figure 3 33 Program Window Step 48 Figure 3 34 Locals Window 49 Figure 3 35 Breakpoints Window Before setting software break 50 Figure 3 36 Add Edit Breakpoint Dialog Box esee 51 Figure 3 37 Breakpoints Window Software Breakpoint 2 2 4 2 4 51 Figure 3 38 Program Window at Execution Stop Software Break 52 Figure 3 39 Displayed Contents of the System Status Window Software Break 52 Figure 3 40 Program Window Break before Run Time Count 53 Figure 3 41 System Status Window Run Time Count Disabled 54 Figure 3 42 Run Time Count Condition Dialog Box seen 54 Figure 3 43 Program Window Stopped at Breakpoint after Run Time Count 56 Figure 3 44 System Status Window Run Time Count Result
122. user program Serial data output by the user program is displayed in this window Data input from the keyboard of the host computer is displayed in this window in addition to being sent to the CPU board This window 15 displayed on selecting the Simulated I O Window item from the View menu Right clicking the mouse on this window displays the following pop up menu Copy Copies the text appearing in highlighted to the Windows clipboard Paste Pastes the contents of the Windows clipboard to the Simulated I O Window and sends the same contents to the CPU board Clear Window Clears the contents of the Simulated I O Window window Rev 1 0 09 00 page 73 of 138 RENESAS Window Simulated I O Window Test Start gt ABCDEFGHIJKLMN Figure 4 7 Simulated I O Window Window The above is the window displayed when the sample program supplied with this CPU board is used For details on the sample program refer to section 7 3 Sample Program Note When using the Simulated I O Window window an interrupt handler must be prepared in the user program For details on the interrupt handler refer to section 7 Creation of User Interrupt Handler 4 2 8 Command Line Window The SH7751 CPU board does not guarantee the Command Line window operation do not use the Command Line window Rev 1 0 09 00 page 74 of 138 RENESAS Section 5 CPU Board Specifications 5 1 Block Diagram A block diagra

SH7751 CPU Board HS7751STC01H User`s Manual

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