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2. 400 401 490 491 Manual October 1989 TABLE OF CONTENTS CHAPTER TITLE PAGE 3 4 2 2 Time Constant Examples 3 7 3 5 Serial Channel Clock Configurations 3 9 3 6 Module Reset Operation 3 9 3 7 General Programming Considerations 3 10 3 7 1 Asynchronous Operation Initialization 3 10 3 7 2 Synchronous Operation Initialization 3 11 3 8 Programming Example 3 12 VMEbus DESCRIPTION QUICK REFERENCE GUIDE SCHEMATICS DIAGRAMS LIST OF FIGURES FIGURE TITLE PAGE 1 1 XVME 400 and X VME 490 Operational Block Diagrams 1 3 1 2 401 and XVME 491 Operational Block Diagrams 1 4 2 1 Jumper Connector Locations on the X VME 400 Module 2 2 2 2 Jumper Connector Locations on the X VME 401 Module 2 3 2 3 Jumper Connector Locations on the X VME 490 Module 2 4 2 4 Jumper Connector Locations on the X VME 491 Module 2 5 2 5 400 401 Front edge Connector 2 10 LIST OF TABLES TABLE TITLE PAGE 1 1 XVME 400 401 490 491 Module Specifications 1 5 2 1 400 and XVME 490 Jumper List 2 6 2 2 401 and XVME 491 Jumper List 2 6 2 3 Base Address Jumper Options 2 7 2 4 Addressing Options 2 8 2 5 Interrupt Level Jumper Positions 2 8 2 6 5V Jumpers X VME 401 Only 2 9 2 7 Module Connector Locations 2 10 2 8 400 Front Edge Connector Pin Definitions 2 12 2 9 401 Front Edge Connector Pin Definitions 2 13 ii 400 401 490 491 Manual October 1989 L
3. KKK KKK 400 40 1 490 49 1 Sample Program Polled mode Asynchronous Operation kk k k eb e e e ke ke kkk afe ake k kkk kkk a ae ake ab ae ake af ale ake af ake af a afe ake ake ak ae ake ake ab oe ab aje ale afe afe ake af a ake ake a ale ake ake ok ake ake a ake afe ae ake ake ae ake ake ak ae ake ake afe ake ake oko ake ake ak ae ke ake ak af ae ake ke ak a ae ake ake ae ake ake ake afe ae ake ae ake EQUATES BASE EQU 00FF0000 ST CK EQU SA00 SCCIAC EQU BASE 13 ORG 800000 START MOVEA L STACK A7 5 MOVE W 2000 SR t Configure cha nnel A of SCC 41 LEA L SCCIAC AO 5 MOVE W 000 7 ki BSR S _ INIT Base address of module Start of stack 5 41 control register Load stack pointer Load status register Load address of module 9600 baud time constant Initialize channel A 5 Read a character from channel A of SCC 41 LOOP LEA L SCCIAC A3 Load address of SCC control reg BSR RPOLA 5 Get character Write a charac ter to channel A of SCC 41 LEA L SCC 1 AC A2 Load address of SCC control reg BSR TPOLA BSR S LOOP 3 12 Echo the character 400 401 490 491 Manual October 1989 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk eee This subroutine will initial
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5. 9 THE LEADER IN INDUSTRIAL 400 401 490 491 4 Channel Serial Modules USER S MANUAL ACROMAG INCORPORATED Tel 248 295 0885 30765 South Wixom Road Fax 248 624 9234 P O BOX 437 Email xembeddedsales acromag com Wixom MI 48393 7037 U S A Copyright 2012 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 970C _ _ _______ _ __ ____ __ ____ ______ ____ ____ __ 2 22 22 222 2225 722222222271 Revision Record Revision Description Manual Released Manual Updated Manual Updated Trademark Information Brand or product names are registered trademarks of their respective owners Windows is registered trademark of Microsoft Corp in the United States and other countries Copyright Information This document is copyrighted by Xycom Incorporated Xycom and shall not be reproduced or copied without expressed written authorization from Xycom The information contained within this document is subject to change without notice Xycom does not guarantee the accuracy of the information and makes no commitment toward keeping it up to date IXycom xycom Technical Publications Department 750 North Maple Road Saline MI 48176 1292 400 401 490 491 Manual October 1989 TABLE OF CONTENTS CHAPTER TITLE PAGE 1 INTRODUCTION
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8. Overview 1 1 Manual Structure 1 2 Module Operational Description 1 3 Module Specifications 1 5 2 INSTALLATION Introduction System Requirements Jumper Connector Locations XVME 400 401 490 491 Module Jumper List Base Address Jumpers JA10 JA15 Address Modifier Jumper 71 17 Interrupt Level Selection Jumpers JA1 JA3 5V Power Supply J1 J2 XVME 401 Only Tri stating the Serial Channels J3 J6 XVME 401 491 Only Daisy Chain Signals Module Connectors 1 1 and JK2 Connectors and JK2 Connector Pinouts on the X VME 400 RS 232C JK1 and JK2 Connector Pinouts on the 401 RS 485 422A and 2 Connectors 2 Connector Pinouts on the X VME 490 RS 232C P2 Connector Pinouts on the X VME 491 RS 485 422A Module Installation CO CO CO 2 02 02 1 D kan ON ke m ne bh KRA N NNNN NNNN RW Duuu RRRRARAUD 3 MODULE PROGRAMMING Introduction Module Addressing Module Interrupt Sources Receive Character Available Interrupts Transmit Buffer Empty Interrupts External Status Interrupts Clocking Options Hardware Configuration Baud Rate Generator Programming the Baud Rate Generator wie to to to 62 02
9. 491 Figure 1 2 401 and 491 Operational Block Diagrams 1 4 400 401 490 491 Manual October 1989 1 4 MODULE SPECIFICATIONS The following is a list of the operational and environmental specifications for the XVME 400 401 490 491 Modules Table 1 1 400 401 490 491 Module Specifications Characteristic Specification Number of Channels 4 Serial Device Zilog 28530 Level Compatibility XVME 400 490 RS 232C XVME 401 49 RS 485 422A Maximum Baud Rate Internal async 57 6 Kbytes Internal sync 500 Kbytes External async 57 6 Kbytes External sync 500 Kbytes Modem Control Signals Available XVME 400 40 1490 RTS CTS DCD DTR XVME 49 RTS CTS DCD Power Requirements 400 490 5 11 A op 1 3 A max 42V 0 100 110 mA max 40 1 49 1 0 1 4 A typ 1 6 A max Temperature Operating 0 to 65 C 32 to 149 F Non operating 40 859 4010158 Humidity _ 5 to 95 non condensing Extremely lo
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11. 06 05 D2 Di VMEbus Data Bit J X X X X 0 0 0 X X 0 0 0 X X X X 1 or 3 Transmit Buffer Empt X X X X 0 0 X X 1 0 0 X X X X Ch lor 3 External Status Change X X X X 0 10 X X 01 0 X X X X Ch 1 or 3 Receive Character X X X X 0 1 1 X X 1 X X X X Ch or 3 Special Receive 4 Condition X X X X 1 0 0 X X 00 1 X X X X ChO or 2 Transmit Buffer Empt X X X 0 1 X X 10 1 X X X X ChOor2 External Status Change X X X X 1 1 0 X 01 1 Ch 0 or 2 Receive Character Available X X X X 1 1 1 X 1 X X 1 1 X X X Ch 0 or 2 Special Receive Condition X Status bit returned from the SCC s IACK Vector Register WR2 Table 3 3 shows the vectors for a single SCC The vector written to SCC 1 s WR2 register Channel 0 or 1 will be used for serial channels 0 and 1 The vector written to SCC 2 s WR2 register Channel 2 or 3 will be used for serial channels 2 and 3 The interrupt daisy chain feature of the SCC is used to arbitrate IACK cycles between the two SCCs SCC 1 has its IEO pin connected to SCC 2 s IEI pin It is suggested that the DLC bit WR9 D2 be set to zero to enable the IEO output pin The MIE bit WR9 D3 can then be used as a master interrupt enable for the individual SCCs This mode of operation keeps the operation of both SCCs symmetric At the end of the ISR routine the Reset Highest IUS command must be issued to enable lower priority interrupts
12. 23 DCD2 NC DCD2 24 GND NC GND 25 TXD3 NC TXD3 26 TXC3 NC TXC3 27 RTS3 NC RTS3 28 RXD3 Ch 3 NC RXD3 29 RXC3 NC RXC3 30 CTS3 NC CTS3 31 DCD3 GND DCD3 32 GND GND pz Te 401 signal names are in the form XXNZ where N is the channel number 7 is based on which half of the signal it is and XX is the name of the signal A 8 400 401 490 491 Manual October 1989 AND JK2 CONNECTORS The XVME 400 and XVME 401 have JKI and JK2 connectors which are 50 pin connectors consisting of three rows of 32 pins each Table A 5 identifies the RS 232C signals carried by and JK2 connectors on the XVME 400 Table A 6 shows the RS 485 422A signals carried by the JKI and JK2 connectors on the 401 Table 5 JKI and JK2 Signal Identification for XVME 400 5232 Pin JKI JK2 Number Signal Signal Signal Direction Transmit Data Receive Data Request To Send Receiving Clock Clear To Send Ground Data Terminal Ready Data Carrier Detected Transmitting Clock Transmit Data Receive Data Request To Send Receiving Clock Clear To Send Ground Data Terminal Ready Data Carrier Detected Transmitting Clock All XVME 400 signal names are in the form XXXN where N is the serial channel number and XXX is the name of the signal All JKI and JK2 pin numbers not referenced are not connected The pinouts of JKI and
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16. 3 3 1 Receive Character Available Interrupts Each of the four channels has its own receive character available IE IP and IUS internal bits The IE bit is set by writing to WR1 D4 D3 and D2 If interrupts are enabled the IP bit will be set whenever a received character is in the receive FIFO The state of this bit can be read from RR3 D2 D5 The IP bit is reset by reading the channel s data register Special Receive Conditions There are two different IACK vectors for the receive character available interrupts the Receive Character Available IACK vector and the Special Receive Condition IACK vector When there are no special conditions associated with the received character on top of the 3 4 400 401 490 491 Manual October 1989 the Receive Character Available IACK vector will be acquired there is a special receive condition associated with the character on top of the FIFO the Special Receive Condition IACK vector will be acquired There are four special receive conditions 1 Receive overrun 2 Framing error ASYNC only 3 End of frame SLDLC only 4 Parity error if WRI D2 1 For interrupt driven operation it is suggested that an interrupt on all receive characters or special conditions be programmed alone with programming parity errors as a special condition When programmed in this mode and the receive character available ACK vector is acquired it is guaranteed that no special conditions exist fo
17. 31 5 VDC STANDBY This line supplies 5 VDC to devices requiring battery backup 45v s 5 VDC POWER Used by system logic circuits 1 32 2B 1 13 32 12v 1C 31 12 VDC POWER Used by system logic circuits 12v 1 31 12 VDC POWER Used by system logic circuits 5 400 40 1 490 49 1 Manual October 1989 Table A 2 PI Signal Identification Row A Pin Signal Number Mnemonic DOO DO2 DO3 DO4 DOS DO6 DO7 GND SYSCLK GND DSI DSO WRITE GND DTACK GND AS GND IACK IACKIN IACKOUT AMA A07 A06 A05 A04 A03 A02 A01 12v 5 coc r2 A igna Mnemonic BBSY BCLR ACFAIL BGOIN BGOOUT BGIIN BGIOUT BG2IN BG20OUT BG3IN BG30UT BRO BRI SERCLK 1 SERDAT 1 GND IRQ7 IRQ6 IRQ5 TRQ4 IRQ3 IRQ2 IRQI 5V STDBY 5v Row C Signal nemonic DO8 DO9 DIO Dil D12 D13 14 15 GND SYSFAIL BERR SYSRESET LWORD 5 23 22 21 20 19 18 17 16 15 14 13 12 10 09 08 12v 5v XVME 400 401 490 491 Manual October 1989 BACKPLANE CONNECTOR P2 The XVME 490 and XVME 49 have the rear edge connector P2 which is a 96 pin bus connector consisting of three rows of 32 pins each Row A is MUT closest to the board Table A 3 identifies the RS 232C P2 signals for the XVME 490 while Table A 4 shows the RS 485 422A signals for the XVME 491 Table
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19. JK2 allow a 50 conductor flat cable to be connected split into two 25 conductor sections and have 25 pin D type connectors installed on the two 25 conductor sections The position of the signals relevant to the 25 pin D type connectors will be in accordance with the RS 232C definition no line Transitions are required TXD Pin 2 DCD Pin 8 RXD Pin 3 RXC_ Pin 17 RTS Pin 4 DTR Pin 20 CTS Pin 5 TXC Pin 24 GND Pin 7 A 9 XVME 400 401 490 491 Manual October 1989 Table 6 JKI and JK2 Signal Identification for the XVME 401 RS 485 422A Pin JKI JK2 Number Signal Signal Signal Direction Transmit Data OUT 2 Transmit Data OUT 5 Receive Data IN 6 Receive Data IN 1 Request Send OUT 8 Request Send OUT 9 Receive Clock IN 10 RTIA Ch 1 Receive Clock IN 11 Clear Send IN n CSIA Clear To Send IN 16 TRIB Data Terminal Ready OUT 17 TRIA Data Terminal Ready OUT 18 RRIB Data Carrier Detect IN 19 RRIA Data Carrier Detect IN 20 TTIB Transmit Clock OUT 21 TTIA Transmit Clock OUT 24 SCI Logic Ground GND 25 SGI Logic Ground GND 26 SD3B Transmit Data OUT 27 SD3A Transmit Data OUT 30 RD3B Receive Data IN 31 RD3A Receive Data IN 32 RS3B Request To Send OUT 33 RS3A Request To Send OUT 34 RT3B Receive Clock IN 35 RT3A Receive Clock IN 36 CS3B Ch 3 Clear To Send IN 37 CS3A Clear To Send IN 41 TR3B Data Terminal Ready OUT 42 TR3A Data Terminal Ready OUT 43 RR3B Data Carrier Detect IN 44 RR3A Data Carri
20. Pin Definitions Ping Row A Signal Row B Signal Row C Signal 1 vcc 2 GND 3 NC 4 NC 5 NC 6 NC 7 NC 8 9 10 11 12 GND 13 vcc 14 NC 15 NC 16 NC 21 XVME 400 401 490 491 Manual October 1989 Table 2 10 XVME 490 Rear Edge P2 Connector Pin Definitions Cont d Row A Signal Row B Signal Row C Signal NC NC NC NC GN NC NC NC NC NC NC NC NC GN P2 signal names are of the form XXXN where N is the serial channel number and XXX is the name of the signal Signals with a XXX function identically with respect to the particular channe 2 15 400 40 490 491 Manual October 1989 2 5 2 2 P2 Connector Pinouts the 491 RS 485 422A Table 2 11 shows the 491 pinouts for connector P2 These signals meet the RS 485 422A and VMEbus specifications T able 2 11 491 Rear Edge P2 Connector Pin Definitions tora St oe Sint tA 5 XVME 401 signal names in the form XXNZ where is the channel number Z is or based on which half of the signal it is and XX is the name of the signal XVME 400 401 490 491 Manual October 1989 2 6 MODULE INSTALLATION XYCOM XVME modules are designed to comply with all physical and electrical VMEbus backplane specifications The
21. XVME 400 401 Modules single high and single wide and as such only require the backplane The 490 491 Modules are double high and single wide and use the PI and P2 backplane CAUTION Never attempt to install or remove any boards before turning off the power to the bus and all related external power supplies Prior to installing a module determine and verify all relevant jumper configurations and all connections to external devices or power supplies Check the jumper configuration against the diagrams and lists m this manual To install a board in the cardcage perform the following steps 1 Make certain that the particular cardcage slot which you are going to use is clear and accessible 2 Center the board on the plastic guides in the slot so that the handle on the front panel is towards the bottom of the XVME 400 401 only 3 Push the card slowly toward the rear of the chassis until the connectors engage the card should slide freely in the plastic guides 4 Apply straight forward pressure to the handle located on the front panel of the module until the connector is fully engaged and properly seated NOTE Do not use excessive pressure or force to engage the connectors If the board does not properly connect with the backplane remove the module and inspect all connectors and guide slots for possible damage or obstructions E Once the board is properly seated secure
22. h JO h 12346 5132419455 TOK JWAX 5512 lt z lt coxa z 2 1512 C 2 1 2 lt ex lt lt 635 ss 125 195 vesy sy vou vcas acos AS 91 58 8154 sivi 9111 8111 9105 8105 Cer es zur Cez Ces Qe 230 Czv 230 CTED 99 Cr 237 Q 92 237 Tu 4 2 Cowra _ 230 Ce 230 CEED 91 12 230 Cse 2 zw Czy 5 29 cso 0 23 8652 69 24 Ev 2X0 Gc 24 vriy 65 2 c 23 62 23 scou 61 230 9152 1 29 8 52 61 239 viyy 61 239 suu 61 290 viy 6 23 sus 6 23 230 8108 C cua lt C C sisiy lt ua etaxi C tou NNN NN NN 6861 1940190 16 06 0 00 JO 12245 NEWS 06 5801953439 l1gd BN831NI saq3wn ges 2 t C DO 0 123135 I 130431 L1df 8BN31NI 300930 13531 p 632974 T2 7482 SU 0319 581530 389 ONY 0058 3017 389 5492 5598 8 xS Mb T SHHO NI 550151535 31382510 119 eLOYI 812 9031 52 819 saaa evONI HILY 82 919 553 0809 62 819 0 6 4 GTS
23. it to the chassis by tightening the two machine screws at the top and bottom of the board 2 17 XVME 400 401 490 491 Manual October 1989 Chapter 3 MODULE PROGRAMMING 31 INTRODUCTION This chapter will discuss the addressing and initialization procedures for programming the XVME 400 401 490 491 Modules In order to demonstrate the correct sequence of initialization for the serial channels contained in the SCC chips two programming examples with comments have been incorporated in this chapter For a complete explanation of how to program and maximize the functionality of the SCC chip refer to the accompanying SCC Manual Each module contains four serial communication channels designated as channels 0 1 2 and 3 Each SCC has two serial channels designated by Zilog as channels A SCC channels map into the module channels as follows Module Channel Number SCC Channel Priority 0 SCC 1 Channel A Highest SCC 1 Channel 2 SCC 2 Channel A 3 SCC 2 Channel B Lowest Throughout this document the module channel number 0 1 2 3 will be referenced For interrupt operation the serial channels are prioritized with channel 0 having the highest priority and channel 3 having the lowest priority Therefore for a given application the serial links running at higher data rates should be assigned to module channels with higher interrupt priority 32 MODULE ADDRESSING The XVME 400 401 490 491 Modules are des
24. module will respond to supervisory or supervisory and non privileged short I O VMEbus cycles refer to Section 2 4 2 Selects module base address on any one of the 64 1 Kbyte boundaries within the short I O address space refer to Section 2 4 1 Selects the VMEbus interrupt level for the module refer to Section 2 4 3 2 4 1 Base Address Jumpers JA10 JA15 The XVME 400 401 490 491 Module can be configured to be addressed at any one of the 64 1 Kbyte boundaries within the VME Short I O address space by using jumpers JAIO through 5 see Figures 2 1 2 2 2 3 and 2 4 for the location of the jumpers on the board as shown above Table 2 3 shows the Base Address Jumper Options 2 6 400 401 490 491 Manual October 1989 Table 2 3 Address Jumper Options 3 15 JA13 JA12 JA10 Base Address of Module 55500005555 9552955 ad 5500550 5555555555555555 8 5553909955550000 2557909559955905 8 995599552955295500955090955 55 8 In In In In In In In In In In In In In In In In In In In In In In In In In In In In In In In In Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out 38 8 8 999999pgsssssssspgggggggssssssssQoggogggssssssss 999999999999999955555s5sssssssss a 0955 2 an 400 40 I 490 49 1 Manual October 1989 2 4 2 Addre
25. out In In 9000 out In In out In out 9400H out In In out out In 9800H out In In out out out 9COOH out In out In In In AOOOH out In out In In out A400H B 3 XVME 400 401 490 491 Manual October 1989 Table B 6 VMEbus Address Options Cont d umpers VME Base Address in VME Short Address Space B 4 400 401 490 491 Manual October 1989 1 SCHEMATICS DIAGRAMS Block Diagram X VME 400 and 490 VMEbus INTERFACE C 1 400 401 490 491 Manual October 1989 Block Diagram 401 and 491 VMEbus INTERFACE VMEbus INTERFACE 401 491 400 401 490 491 Manual October 1989 400 Assembly Drawing C ra A Q um m b uz p v CBP core RN 1 u _ 07 Q TR CksP C12 Te 01 R7 gt e HHR Oade urs p ur Je 02 122 525 Ca R12 RN2 P1 o TL TL TL TEL TE TE TE TE TE TE TE TE le 400 401 490 491 Manual October 1989 XVME 401 Assembly Drawing E E E a E E E E E E a LO XVME 400 401 490 491 Manual October 1989 XVME 490 Assembly Drawing 5 400 401 490 491 Manual October 1989 XVME 491 Assembly Drawing C43 30193394399 L1dnHH3l1NI JO 19246 LWS 00
26. own baud rate generator The VMEbus interface directly maps the SCC into the short WO address space starting on a jumper selected 1 Kbyte boundary e modules can also be jumpered 10 generate an interrupt on any of the seven bus interrupt levels two SCC chips can generate a total of 16 different interrupt vectors Some features of the 400 401 490 491 modules include e Four independent full duplex serial WO channels e RS 232C or RS485 422A operation e Serial channels independently configurable for asynchronous monosynchronous bisynchronous HDLC SDLC message formats e Independent baud rate generators for each serial channel e Modem control e Receivers are quadruply buffered transmitters double buffered e Complete VMEbus interrupter jumper selectable to any interrupt level Programmable JACK vector with vector alteration based on source of interrupt Line drivers for each channel tri stateable controlled by software to allow multidrop operation 401 and 491 only 400 401 490 491 Manual October 1989 12 MANUAL STRUCTURE The chapters in this manual are structured as follows Chapter One eneral description of 400 401 490 491 modules uding complete functional and environmental specifications VMEbus compliance information and block diagrams Chanter Two Module installation information covering module specific system requirements jumper
27. 01 490 491 Module are shown in Figures 2 1 2 2 2 3 and 2 4 JA10 JA15 JA1 7 Figure 2 1 Jumper Connector Locations on the 400 Module 2 2 400 401 490 491 Manual October 1989 JA10 JA15 1 Figure 2 2 Jumper Connector Locations the 401 Module 2 3 400 401 490 491 Manual October 1989 Figure 2 3 Jumper Connector Locations on the 490 Module 2 4 400 401 490 491 Manual October 1989 Figure 2 4 Jumper Connector Locations on the 491 Module 2 5 XVME 400 401 490 491 Manual October 1989 2 4 XVME 400 401 490 491 MODULE JUMPER LIST JAIO JAIS JAI JA3 J7 JAIO JAIS JAI JA3 Table 2 1 XVME 400 and XVME 490 Jumper List Determines whether the module will respond to supervisory or supervisory and non privileged short VMEbus cycles refer to Section 2 4 2 of this manual Selects module base address on any one of the 64 1 Kbyte boundaries within the short I O address space refer to Section 2 4 1 of this manual Selects the VMEbus interrupt level for the module refer to Section 2 4 3 of this manual Table 2 2 XVME 401 and 491 Jumper List Brings the 45V supply to front edge connectors JKI and JK2 respectively XVME 401 only refer to Section 2 4 4 Allows tri stating of any of the channels refer to Section 2 4 5 Determines whether the
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31. A 3 P2 Signal Identification for XVME 490 Row Signal Row B Signal Row C Signal TXDO vcc GND 2 RXDO GND GND 3 RTSO NC GND 4 RXCO Ch 0 NC GND 5 CTSO NC GND 6 DTRO NC GND 7 DCDO NC GND 8 TXCO NC GND 9 TXDI NC GND 10 RXDI NC GND 11 RTSI NC GND 12 RXCI Ch GND GND 13 CTSI vcc GND 14 DTR 1 NC GND 15 DCDI NC GND 16 TXCI NC GND 17 TXD2 NC GND 18 RXD2 GND 19 RTS2 NC GND 20 RXC2 Ch 2 NC GND 21 CTS2 NC GND 22 DTR2 GND GND 23 DCD2 NC GND 24 TXC2 NC GND 25 TXD3 NC GND 26 RXD3 NC GND 27 RTS3 NC GND 28 RXC3 Ch 3 NC GND 29 CTS3 NC GND 30 DTR3 NC GND 31 DCD3 GND GND 32 TXC3 vec GND P2 signal names are in the form XXXN where is the serial channel number and XXX is the signal name Signals with the same function identically with respect to the particular channel 400 401 490 491 Manual October 1989 Table A 4 2 Signal Identification for the XVME 491 Row A Signal Row B Signal Row C Signal TXDO TXDO 2 GND TXCO 3 RTSO NC RTSO 4 RXDO Ch 0 NC RXDO 5 RXCO NC RXCO 6 CTSO NC CTSO 7 DCDO NC DCDO 8 GND NC GND 9 TXDI NC TXDI 10 RTSI NC RTSI 12 RXDI Ch GND RXDI 13 1 vec RXCI 14 CTSI NC CTSI 15 DCDI NC DCDI 16 GND NC GND 17 TXD2 NC TXD2 18 TXC2 NC TXC2 19 RTS2 NC RTS2 20 RXD2 Ch 2 NC RXD2 21 RXC2 NC RXC2 22 CTS2 GND CTS2
32. BTST 0 DO Is a character available BEQ S RXPOLL No then try again RXCHA MOVE B 2 A3 D3 Get the character RXIT MOVEM L SP DOD 1 A1 Restore registers RTS END 3 15 XVME 400 401 490 491 Manual October 1989 ae ake ake ke afe ae ake ake ke ake afe ae ake ake ake ake ake ake ake ake ake ake ake ake afe ake ake kk k k kk k kk oe oe be be he ke ke bebe oe kr HF F This routine will initialize the specified SCC channel to asynchronous operation A hardware reset is assumed before code is executed IN A04 SCC Control Register Address OUT D7 W WR13 12 Baud Rate Time Constant Transmitter and receiver enabled channel interrupts disabled IACK Vector Register set to 40 MIE bit set DLC bit reset Variable IACK Vector enabled low status X16 Clock mode stop bit odd parity enabled Transmitter and receiver set to bits character No auto enables DTR TR and RTS RS asserted Receive clock transmit clock and programed for BRG Output BRG clock PCLK e e e e tt ti ASYNC INIT MOVE B 4 0 Set WR4 XI6 clock 1 stop bit MOVE B 9 01000101 0 Odd enabled MOVE B 3 0 Set WR3 8 RX bits MOV
33. E 400 and 490 Jumper List Determines whether the module will respond to supervisory supervisory and non privileged short VMEbus cycles refer to Sec on 2 4 2 of this manual JAIO JAIS Select module base address on any one of the 64 IK boundaries viu gt short I O address space refer to Section 2 4 1 of this manual JAI JA3 Select the VMEbus interrupt level for the module refer to Section 2 4 3 of this manual Table B 2 401 and 491 Jumper List JI and J2 Bring the 5V Up to front edge connectors and JK2 respectively XVME 401 only refer to Section 2 4 4 J3 J6 Allows tri stating of any of the channels refer to Section 2 4 5 J7 Determines whether the module will respond to supervisory or supervisory and non privileged short VMEbus cycles refer to Section 2 4 2 JAIO JAIS Select module base address on any one of the 64 boundaries within the shot address space refer to Section 2 4 1 JAI JA3 Select the VMEbus interrupt level for the module refer to Section 2 4 3 1 400 401 490 491 Manual October 1989 Table B 3 Addressing Options Jumper Address Modifier to which the XVME 400 401 490 491 Module will respond JI XVME 400 490 or 401 491 2DH Supervisory only 2DH Supervisory or 29H Non privileged Table B 4 Interrupt Level Jumper Positions Lm Interrupt Level Selected None VMEbus Interrup
34. E B 1 1000000 A0 No auto enable disabled MOVE B 5 0 Set WR5 amp RTS asserted MOVE B 89511100010 0 8 TX bits TX disabled MOVE B TM Set WRI DMA WAIT pins MOVE B 4001000100 0 TX EXT INT disabled Parity Special condition MOVE B 2 A0 WR2 MOVE B 40 A0 IACK Vector 40 MOVE B 9 A0 Set WR9 Status Low MIE set MOVE B 00001001 0 DLC O IACK Vector variable MOVE B 0 0 Set WRIO to NRZ 10 A0 MOVE B 1 A0 t Set WRI XTAL MOVE B 010101 10 0 TX Clock BRG 3 16 XVME 400 401 490 491 Manual October 1989 ROR W MOVE B MOVE B ROL W MOVE B MOVE B MOVE B MOVE B MOVE B MOVE B MOVE B MOVE B MOVE B MOVE B MOVE B MOVE B RTS 8 D7 13 D7 AO 8 D7 12 AO D7 AO 14 A0 2 A0 14 A0 3 A0 15 A0 0 A0 3 A0 11000001 5 A0 11101010 A0 3 17 Set WR13 High order Time constant Set 12 Low Order Time constant Set WR14 BRG source PCLK Enable BRG Set WR15 Disable all external Interrupts Enable receiver Enable transmitter XVME 400 401 490 491 Manual October 1989 Appendix A VMEbus CONNECTOR PIN DESCRIPTIONS PI BACKPLANE CONNECTOR All the modules have the rear edge connector PI which is 96 bus connector consisting of three rows of 32 pins each Row A is physic
35. I2B Transmit Clock OUT 46 2 Transmit Clock OUT 41 2 5v 5v OUT 49 SC2 SC3 Logic Ground GND 50 502 503 Logic Ground GND 2 13 400 401 490 491 Manual October 1989 XVME 401 signal names are in the form XXNZ where is the channel number 7 is A based on the polarity of the differential signal as defined RS 485 is the name of the signal Also see Section 2 4 4 All JKI and JK2 pin numbers not referenced are not connected 2 5 2 PI and P2 Connectors The PI and P2 connectors are the same physical type and have the same number of pins Both are 96 pin connectors consisting of three rows of 32 pins each Like PI is mounted at the rear edge of the module The pins for contain the standard address data and control signals necessary for the operation of VMEbus defined modules The signal definitions and pin outs for connector Pl are found in Appendix A of this manual The PI connector is designed to mechanically interface with a VMEbus defined P 1 backplane The P2 connector XVME 490 491 only is a standard VMEbus P2 backplane connector It is designed to interface with a bus defined P2 backplane 2 5 2 1 P2 Connector Pinouts on the 490 RS 232C Table 2 10 shows the 490 pinouts for connector P2 signals meet the RS 232C and VMEbus specifications Table 2 10 XVME 490 Rear Edge P2 Connector
36. IST TABLES Cont d TABLE TITLE 2 10 XVME 490 Rear Edge P2 Connector Pin Definitions 2 11 XVME 491 Rear Edge P2 Connector Pin Definitions 3 1 Register Offsets 3 2 Priority of Local Interrupt Sources 3 3 IACK Vector Containing the Status 3 4 Typical Time Constraints for Synchronous X1 Clock 3 5 Typical Time Constraints for Asynchronous X16 Clock iii 400 401 490 491 Manual October 1989 Chapter 1 INTRODUCTION 11 OVERVIEW The 400 401 490 and 491 are Quad Serial I O VMEbus compatible modules which provide a system with four serial communications channels XVME 400 and 401 are single high while the XVME 490 and 491 are double high XVME 400 and XVME 401 access the I O through the JKI and JK2 connectors on the module front panel whereas the XVME 490 and 491 route their I O to the VMEbus P2 connector The XVME 400 and XVME 490 each provide four RS 232C serial ports while the XVME 401 and XVME 49 each provide four RS 485 422A serial ports Differences among these modules are further detailed in Chapter 2 notably in Tables 2 1 and 2 2 Each module contains two 8530 Serial Communication Controller SCC chips designated SCC and SCC 2 The two SCC serial chips provide a variety of communication modes including asynchronous byte synchronous and bit oriented protocols Each channel is independently programmable and has its
37. LK Enable BRG Set WRI5 Disable all external interrupts Enable receiver Enable transmitter e Se ee ee ee ee ee ee ee ee ee ee ee cde de ee ee ee Je eee Je ee e cce c cde ee ee ee ee ee ee ee eee On entry This routine will transmit a byte in polled mode A2 contains the address of the command register of the SCC channel used for transmitting D2 B contains the byte to be transmitted MOVEML 1 A 1 SP TXPOLL A2 DO BTST BEQ S TXBFE TXIT MOVEML 5 173 1 RTS 2 DO TXPOLL MOVE B D3 2 A2 3 14 Save registers Read the contents of RRO Is TX buffer empty No then poll again Yes move character to transmit data register Restore registers 400 401 490 491 Manual October 1989 eee ce ce ce ecce ce ce oe KKK KKK D3 B contains the byte which was received This routine will receive a of data in polled mode 5 On entry 5 A3 contains the address of the command 2 register of the SCC channel used for t receiving ki On exit RPOLA MOVE M L 1 1 SP Save registers RXPOLL MOVE B A3 DO Read the contents of RRO
38. O Set WR5 as follows state of and CTS in D7 DI number of transmit bits character D6 D5 transmitter disable D3 0 Set WRIO for NRZ D6 D5 0 0 Set interrupt or polled operation refer to Section 3 3 Set clocking options refer to Section 3 4 Enable receiver WR DO and transmitter WR5 D3 as required 3 10 XVME 400 401 490 491 Manual October 1989 3 7 2 Synchronous Operation Initialization This section describes the steps required to set up the SCCs for synchronous operation These steps apply to any channel and should be followed in the specified order 1 Issue the Channel Reset command WR9 D7 6 2 Set WR4 as follows X 1 clock mode D7 D6 0 0 type of sync 0504 sync mode enabled D3 D2 0 0 parity odd even enable in D1 DO 3 Set WRIO as required 4 Set WR6 and WRT to the sync character or SDLC address as required 5 Set WR3 as follows number of receive bits character in D7 D6 D5 D4 D3 D2 D as required receiver disabled DO O 6 Set WR5 as follows state of DTR and CTS in D7 Dl number of transmit bits character in D6 D5 D4 D2 DO as required and transmitter disabled D3 0 7 Set WRI4 as required 8 Set interrupt or polled operation refer to Section 3 3 9 Set clocking options refer to Section 3 4 10 Enable receiver WR3 DO and transmitter WR5 D3 required 3 1 XVME 400 401 490 491 Manual October 1989 3 8 PROGRAMMING EXAMPLE e e e
39. There are twelve sources of interrupts the XVME 400 401 490 491 three sources from each serial channel When enabled each of these sources can generate VMEbus interrupts on the level specified by jumpers JAI JA3 The interrupt sources are prioritized during the VMEbus IACK cycle as shown in Table 3 2 Table 3 2 Priority of Local Interrupt Sources ume Receive Character Available Highest Transmit Buffer Empty External Status Change Receive Character Available Transmit Buffer Empty External Status Change Receive Character Available Transmit Buffer Empty External Status Change Receive Character Available Transmit Buffer Empty External Status Change Lowest 0 0 0 2 2 2 3 3 3 When the module responds to VMEbus IACK IACK vector is acquired from the appropriate SCC chip and driven onto the VMEbus Since each SCC can produce 8 vectors SCC IACK vector register WR2 must be initialized before interrupts are enabled When programmed to include status in the IACK vector 9 the status high low bit WR9 D4 determines whether IACK vector bits 3 2 1 or bits 4 5 6 will contain status information The status information returned in JACK vector is shown in Table 3 3 on the following page 3 3 400 401 490 491 Manual October 1989 Table 3 3 IACK Vector Containing the Status IACK Vector WR9 D4 0 IACK Vector WR9 D4 1 D5 D4 D2 Di
40. XC Pin24 GND Pin 7 400 401 490 491 Manual October 1989 2 5 1 2 and JK2 Connector Pinouts on XVME 401 RS 485 422A Table 2 9 shows the 401 pinouts for connectors JKI and JK2 These signals meet RS 485 422A specifications Table 2 9 XVME 401 Front Edge Connector Pin Definitions Pin Number JK2 Signal Signal Signal Direction SDOB SDIB Transmit Data OUT 2 SDOA SDIA Transmit Data OUT 5 RDOB RDIB Receive Data IN 6 RDOA RDIA Receive Data IN 7 RSOB RSIB Request To Send OUT 5 RSOA RSIA Request To Send OUT 9 RTOB RTIB Receive Clock IN 10 RTOA Ch 0 Ch 1 Receive Clock IN 11 CSOB CSIB Clear To Send IN 12 CSOA CSIA Clear Send IN 16 TROB TRIB Data Terminal Ready OUT 17 TROA TRIA Data Terminal Ready OUT 18 RROB RRIB Data Carrier Detect IN 19 RROA RRIA Data Carrier Detect IN 20 TTOB TTIB Transmit Clock OUT 21 TTOA TTIA Transmit Clock OUT 24 SCO 501 Logic Ground GND 25 00 SGI Logic Ground GND 26 SD2B SD3B Transmit Data OUT 27 SD2A SD3A Transmit Data OUT 30 RD2B RD3B Receive Data IN 31 RD2A RD3A Receive Data IN 32 RS2B RS3B Request Send OUT 33 RS2A RS3A Request To Send OUT 34 RT2B RT3B Receive Clock IN 35 2 Receive Clock IN 36 CS2B Ch 2 CS3B Ch 3 Clear Send IN 37 CS2A CS3A Clear To Send IN 4 TR2B TR3B Data Terminal Ready OUT 42 TR2A TR3A Data Terminal Ready OUT 43 RR2B RR3B Data Carrier Detect IN 44 RR2A RR3A Data Carrier Detect IN 45 T
41. a VMEbus backplane Included in this chapter is information on module base address selection jumpers module interrupt level selection jumpers 5V tri state jumpers connector pinouts and a brief outline of the physical installation procedure 2 2 SYSTEM REQUIREMENTS The XVME 400 40I Modules single high or the XVME 490 491 Modules double za VMEbus compatible modules operate each must be properly installed VMEbus backplane The minimum system requirements for the operation of an XVME 400 401 490 491 Module are one of the following A host processor properly installed on the same backplane A properly installed system controller module which provides the following functions Data Transfer Bus Arbiter System Clock Driver System Reset Driver Bus Timeout Module OR host processor which incorporates the system controller functions on board An example of such a controller subsystem is the XYCOM XVME 010 System Resource Module SRM Prior to installing the 400 401 490 491 Module it will be necessary to configure several jumper options These options are 1 Module base address within the short I O address space 2 Address modifier codes to which the module will respond 3 Interrupt level 4 5 tri state jumpers XVME 401 only 2 1 400 401 490 491 Manual October 1989 2 3 JUMPER CONNECTOR LOCATIONS The jumpers and connectors relevant to the installation of the X VME 400 4
42. able the baud rate generator WRI4 DO I WN 3 4 2 2 Time Constant Examples The following tables show the time constants required for popular baud rates when PLCK is used as the baud rate generator input Two tables are shown one for synchronous IX clock and one for asynchronous 16X clock These particular constants are shown for illustration only Any time constant may be used 3 7 XVME 400 401 490 491 Manual October 1989 Table 3 4 Typical Time Constraints for Synchronous xl Clock Time Constant WR13 Value WR12 Value Baud Rate Base 10 H ex Table 3 5 Typical Time Constraints for Asynchronous x16 Clock Time Constant WR13 Value WR12 Value Baud Rate Base 10 Hex 3 8 XVME 400 401 490 491 Manual October 1989 35 SERIAL CHANNEL CLOCK CONFIGURATIONS The receiver and or transmitter can be independently programmed to accept their clock source from any of the following the RXC RT signal the baud rate generator or the digital phase locked loop see the SCC manual TXC TT may not be programmed as a The receiver option is specified in WRI 1 D6 D5 the transmitter in The TXC TT output signal may be programmed to output any of the following the baud rate generator the digital phase lock loop or the transmitter s clock This is selected via WRI 1 D1 DO Any combination of clock rate and baud rate options may be used in synchronous or asynchronous modes Four typical examples ar
43. ally closest to the board See Table A 2 The signals carried by connector Pl are the standard address data and control signals required for a Pl backplane interface as defined by the VMEbus specification Table 1 identifies and defines the signals carried by the connector Table PI VMEbus Signal Identification Connector Signal and Mnemonic Pin Number Signal Name and Description ACFAIL 1B 3 AC FAILURE Open collector driven signal which indicates that the AC input to the power supply is no longer being provided or that the required input voltage levels are not being met IACKIN 1 21 INTERRUPT ACKNOWLEDGE Totem pole driven signal IACKIN and signals form daisy chained acknowledge The IACKIN signal indicates to the VME board that an acknowledge cycle is in progress IACKOUT 1 A 22 INTERRUPT ACKNOWLEDGE OUT Totem pole driven signal IACKIN and IACKOUT signals form a daisy chained acknowledge The IACKOUT signal indicates to the next board that an acknowledge cycle is in progress 0 5 1 23 ADDRESS MODIFIER bits 0 5 Three state driven lines 1B 16 17 that provide additional information about the address bus 18 19 such as size cycle type and or DTB master identification 1C 14 AS ADDRESS STROBE Three state driven signal that indicates a valid address is on the address bus 1 XVME 400 401 490 491 Manual October 1989 Table VMEbus Signal Id
44. e given below 1 Asvnchronous Operation The baud rate generator is used as the transmitter and receiver clocks The master clock Staal received on the pin PCLK is used for the generator s input The external clock s C RT and TXC are not used 2 Svnchronous Operation External Transmitter Receiver Timing Definition The RXC RT clock input is used for the transmitter and receiver clocks TXC SD output will be synchronized to the clock input on RXC RT RXD RT input will be sampled by clock input RXC RT The baud rate generator is not used 3 Svnchronous Operation Internal Transmitter and Receiver Timing Definition The baud rate generator is used for the transmitter and receiver clocks TXC TT output signal is programmed to output the baud rate generator TXC SD output will be synchronized to the clock output TXC TT RXD input will be sampled by clock output TXC TT 4 Svnchronous Operation External Receiver Timing Definition and Internal Transmitter Timing Definition Ihe baud rate generator is used for the transmitter clock and is sent out on the TXC TT line The RXC RT signal is used for the receiver clock TXD SD output will be synchronized to the clock output TXC TT RXD RD input will be sampled by clock input RXC RT 36 MODULE RESET OPERATION The module is reset by the assertion of VMEbus signal SYSRESET In response the module will reset its bus interface and the SCCs Refer to the SCC technical manual for SCC r
45. e output can be used as internal timing sources e baud rate generator s clock input may be programmed to connect to either RXC RT signal or PCLK WRI4 16 bit time constant can be programmed into WRI3 most significant byte and WRI2 least significant byte to select the baud rate generator s output frequency The following equations show the baud rate generator s output frequency as a function of the time constant and vice versa If baud rate generator input is RXC or RT WRI4 DI O Time Constant guene of 2 CM Baud Rate 2 Baud Rate Frequency of 2 CM Time Constant 2 If baud rate generator input is PCLK 1405 PCLK 3 6864 Time Constant 1 8432 MHz CM Baud Rate 2 Baud Rate 1 8432 MHz CM Time Constant 2 In the above equations CM is the clock multiplier used by the transmitter and receiver 1 e 1 6 for X 16 clock multiplier The output of the baud rate generator can be used as the transmitter clock source and or the receiver clock source and it may also be sent to the TXC TT output Any combination of these three may be used 3 4 2 1 Programming the Baud Rate Generator The following steps should be followed in the specified order to program the baud rate generator Disable the baud rate generator WR14 D0 0 Load WRI2 and WRI3 with the desired time constant Select baud rate generator clock source 14 01 0 for RXC RT WRI4 DI 1 for En
46. ed with that channel will be enabled regardless of the state of the SCC output RTS The jumper numbers related to the serial channel numbers are shown below and are all shipped in the B position J3 Channel 3 J4 Channel 2 J5 Channel 1 J6 Channel 0 2 4 6 Daisy Chain Signals Each slot in the VME backplane must propagate the Daisy Chain signals to the next backplane slot This occurs automatically if boards are installed in the slots Where boards are not installed the appropriate backplane jumpers must be installed to continue the signal path NOTE Boards and jumpers should never both be installed in any one slot XVME 400 401 490 491 Manual October 1989 25 MODULE CONNECTORS The location of the module connectors is shown in Table 2 7 connector pinouts for PI are shown in Appendix A Table 2 7 Module Connector Locations Front Edge Rear Edge JK1 amp JK2 XVME 400 amp 401 XVME 490 amp 491 2 5 1 JK1 and JK2 Connectors The XVME 400 and XVME 401 have two 50 pin connectors designated as JK 1 and JK2 which are accessible through the front panel see Figure 2 5 510 401 Figure 2 5 400 401 Front edge Connector 2 10 400 401 490 491 Manual October 1989 On the XVME 400 401 connector carries the signals for Channels 0 and 2 while connector JK2 car
47. entification cont d Connector Signal and Mnemonic Pin Number Signal Name and Description 01 23 1 24 30 ADDRESS BUS bits 1 23 Three state driven address lines 1C 15 30 that specify a memory address A24 A3 1 2B 4 11 ADDRESS BUS bits 24 31 Three state driven bus expansion address lines BBSY 1B 1 BUS BUSY Open collector driven signal generated by the current DTB master to indicate that it is using the bus BCLR IB2 BUS CLEAR Totem pole driven signal generated by the bus arbitrator to request release by the DTB master if a higher level is requesting the bus BERR BUS ERROR Open collector driven signal generated by slave It indicates that an unrecoverable error has occurred and the bus cycle must be aborted BGOIN 1 4 6 BUS GRANT 0 3 IN Totem pole driven signals generated BG3IN 8 10 by the Arbiter or Requesters Bus Grant In and Out signals form a daisy chained bus grant The Bus Grant In signal indicates to this board that it may become the next bus master BGOOUT 18 5 7 BUS GRANT 0 3 OUT Totem pole driven signals BG30UT 9 generated by Requesters These signals indicate that a DTB master in the daisy chain requires access to the bus A 2 400 401 490 491 Manual October 1989 Table 1 VMEbus Signal Identification cont d Connector Signal and M nemonic Pin Number Signal Name and Description BRO BR3 1B 12 15 BUS REQUEST 0 3 Open collector driven sig
48. er Detect IN 45 Transmit Clock OUT 46 Transmit Clock OUT 47 2 5v OUT 49 SC3 Logic Ground GND 50 503 Logic Ground GND NOTE XVME 40 1 signal names are in the form XXNZ where is the channel number Z is A or based on the polarity of the differential signal defined by RS 485 and is the name of the signal All JKI and JK2 pin numbers not referenced are not connected A 10 XVME 400 401 490 491 Manual October 1989 Sources of JKI JK2 or P2 Connector Output Signals one set for each serial channel TXD SD SCC output pin TXD drives a line driver Driver output is sent to this pin RTS RS SCC output pin RTS drives a line driver Driver output is sent to this pin TXC TT SCC output pin TRXC drives a line driver Driver output is sent to this pin DTR TR SCC output pin DTR drives a line driver Driver output is sent to this pin Destinations of JK 1 JK2 or P2 Connector Input Signals one set for each serial channel RXD RD This input pin is buffered by a line receiver and is driven to the SCC input pin CTS CS This input pin is buffered by a line receiver and is driven to the SCC input pin CTS RXC RT This input pin is buffered by a line receiver and is driven to the SCC input pin RTXC DCD RR D input pin is buffered by a line receiver and is driven to the SCC input pin XVME 400 401 490 491 Manual October 1989 Appendix B QUICK REFERENCE GUIDE Table XVM
49. ernal Status Interrupt command WRO 3 5 400 401 490 491 Manual October 1989 3 4 CLOCKING OPTIONS This section describes the transmit and receive clocking options for the serial channels It applies to all four independently configurable serial channels 3 4 1 Hardware Configurations The SCC receive clock input pin RTXC is driven from line receivers which are connected to the JK RT input see Section 2 5 Therefore the frequency of SCC pin RTXC is determined by the external clock connected to the RXC RT input pin This clock input signal will be referred to as RXC RT in this section The crystal oscillator feature of the SCC is not used The SCC transmit clock pin TRXC is used as an output It is buffered by line drivers and driven to a TXC TT output on a front edge connector The SCC pin TRXC must be programmed as an output WRI 1 and must not be selected as an internal SCC clock source is clock output signal is referred to as TXC IT in this section In all possible clocking combinations the polarities of the clock signals TXC IT and RXC RT are in accordance with the RS 232C or RS 485 standards The SCC s clock pin PCLK is connected to a 3 6864 MHz clock This frequency allows the baud rate generator to produce most of the popular baud rates used for serial communications 3 6 XVME 400 401 490 491 Manual October 1989 3 4 2 Baud Rate Generator The SCC contains a programmable baud rate generator whos
50. eset operation 3 9 XVME 400 401 490 491 Manual October 1989 3 7 GENERAL PROGRAMMING CONSIDERATIONS This section outlines programming rules which apply to all modes of operation These constraints WRI WR4 WR9 WRII WRL4 are dictated by hardware configurations Set D7 D6 D5 to 0 1 0 This will disable the DMA and WAIT features of the SCCs Polled or interrupt operation must be used D5 D4 must not be programmed for external sync modes of operation Set DI to 0 This will enable the interrupt vector feature of the SCC There are no other sources of vectors on the module Set D7 to 0 This will disable the external crystal oscillator feature of the SCC The SCC pin TRXC must not be programmed as a clock source for the receiver D6 D5 or the transmitter 04 03 Set D2 to 1 to select the TRXC pin as an output Set D2 to 0 to program the DTR REQ pin to the DTR function Asynchronous Operation Initialization This section describes the steps required to set up the SCCs for asynchronous operation These steps apply to any channel and should be followed in the specified order vc 72022 Issue the Channel Reset command WR9 D7 6 Set WR4 as follows clock mode in D7 D6 16X is suggested number of stop bits in D3 D2 and parity odd even enable in DI DO Set WR3 as follows number of receive bits character in D7 D6 auto enables as required in 05 receiver disable DO
51. ignal For modem control lines a will be read from the SCC read control register bit when the input is asserted For RXD RD and T the polarity defined by RS 232C or RS 485 is provided 2 11 XVME 400 401 490 491 Manual October 1989 2 5 1 1 JKI and JK2 Connector Pinouts on the XVME 400 RS 232C Table 2 8 shows the XVME 400 pinout connectors and JK2 These signals meet the RS 232C specifications Table 2 8 XVME 400 Front Edge Connector Pin Definitions Pin JKI JK2 Number Signal Signal Signal Direction Transmit Data Receive Data Request To Send Receiving Clock Clear To Send Ground Data Terminal Ready Data Carner Detected Transmitting Clock Transmit Data Receive Data Request To Send Receiving Clock Clear To Send Ground Data Terminal Ready Data Carrier Detected Transmitting Clock NOTE All XVME 400 signal names are in the form XXXN where N is the serial channel number and is the name of the signal All JKI and JK2 pin numbers not referenced are not connected The pinouts of JKI and JK2 allow 50 conductor flat cable to be connected split into two 25 conductor sections and have 25 pin D type connectors installed on the two 25 conductor sections The position of the signals relevant to the 25 pin D type connectors will be in accordance with the RS 232C definition no line transitions are required TXD Pin2 DCD Pin 8 RXD Pin RXC Pin 17 RTS Pin4 DTR Pin 20 CTS Pin5 T
52. igned to be addressed within the VMEbus defined 64 Kbyte short I O address space When the XVME 400 401 490 491 Module 18 installed in the system it will occupy a 1 Kbyte block of the short I O address space The base address decoding scheme for the XVME I O modules is such that the starting address for each board resides on a 1 Kbyte boundary Thus there are 64 possible locations 1 Kbyte boundaries in the short I O address space which could be used as the base address for the XVME 400 401 490 491 Module Refer to Section 2 4 1 for the list of base addresses and their corresponding jumper configurations All register locations within the SCC devices are given specific addresses which are offset from the module base address Thus a specific register address in one of the SCC chips can be accessed by adding the specific register offset to the module base address For example the offset specified for the Serial Channel 2 Data Register is 07 and if the module base address is jumpered to 1000H the register can be accessed at 1007 3 1 XVME 400 401 490 491 Manual October 1989 M odule Base Address Register Offset Serial Channel 2 Data Register 1000H 07 1007 The 400 401 490 491 15 an odd byte only slave and as such the module will not respond to even address single byte accesses However word accesses may be used with the understanding that only the odd byte of the word is used to exchange data If wo
53. installed to ensure that a programming bug will not generate a VMEbus interrupt 400 40 1 490 491 Manual October 1989 2 4 4 Power Supply Jl J2 401 only On the XVME 401 jumpers and J2 control whether the 5V supply is brought out to front edge connectors JKI and JK2 Table 2 6 indicates the functions of these jumpers Table 2 6 5V Jumpers XVME 401 only If is installed 5V will be connected to pin 47 JI is removed JKI 47 will float If J2 is installed 5V will be connected to JK2 pin 47 If J2 is removed JK2 47 will float The 45 signals on the tront oda connector could be used to provide external line termination by being used as a pull up voltage or for biasing 2 4 5 Tri stating the Serial Channels J3 J6 XVMIE 401491 only To facilitate multidrop configurations all drivers associated with a particular communication channel may be tri stated or enabled via SCC output pin RTS Each channel has its own jumper to determine how the RTS output affects line driver enabling When a channel s jumper is in the A position the line drivers associated with that channel for TT RS SD and will be controlled by RTS When RTS is negated high voltage all line drivers associated with that channel will be tri state When RTS is asserted all line drivers associated with that channel will be enabled When a channel s jumper is in the B position the line drivers associat
54. ize the specified SCC channel for asynchronous operation On entry A0 L SCC control register address D7 W WR13 WRI2 baud rate time constant On exit ASYNC INIT MOVE B MOVE B MOVE B MOVE B MOVE B MOVE B MOVE B MOVE B MOVE B MOVE B MOVE B MOVE B MOVE B MOVE B MOVE B MOVE B MOVE B MOVE B ROR W MOVE B MOVE B D 80 AO 1000101 3 0 11000000 A0 100010 A0 1 AO 01000100 A0 2 A0 40 AO 9 A0 00001001 10 0 AO 11 A0 01010110 A0 8 D7 13 AO D7 AO 3 13 Set WR9 5 Reset channe A SCC 1 Set WR4 X16 clock stop bit Odd parity enabled Set WR3 8 RX bits disabled No auto enable Set WR5 DTR and RTS asserted 8 TX bits TX disabled Set WRI DMA WAIT pins Set RX TX ext int disabled Parity special condition Set WR2 IACK vector 40 Set WR9 status low MIE set DLC2O IACK vector variable Set WRIO to NRZ Set WRII XTAL RX TX clock BRG TRXC BRG Set WRI3 High order Time constant XVME 400 401 490 491 Manual October 1989 ROL W MOVE B MOVE B MOVE B MOVE B MOVE B MOVE B MOVE B MOVE B MOVE B MOVE B MOVE B MOVE B RTS 8 D7 n 3 A0 15 A0 0 A0 3 A0 11000001 5 AO 11101010 0 Set WRI2 Low order Time constant Set WRI4 source PC
55. nals enerated by Requesters ese signals indicate that a TB master in the daisy chain requires access to the bus DSO 13 DATA STROBE 0 Three state driven signal that indicates during byte and word transfers that a data transfer will occur on data buss lines 000 007 DSI 12 DATA STROBE 1 Three state driven signal that indicates during byte and word transfers that a data transfer will occur on data bus lines D0 D15 DTACK 1A 16 DATA TRANSFER ACKNOWLEDGE _ Open collector driven signal generated by DTB slave The falling edge of this signal indicates that valid data is available on the data bus during a read cycle or that data has been accepted from the data bus during a write cycle D00 D15 1A 1 8 DATA BUS bits 0 15 Three state driven bi directional 1 1 8 data lines that provide data path between the master and slave GND 1 9 11 GROUND 15 17 19 1B 20 23 IC 9 2B 2 12 22 31 A 3 XVME 400 401 490 491 Manual October 1989 Signal Mnemonic IACK IRQI IRQ7 LWORD RESERV ED SERCLK SERDAT SYSCLK Table Pin Number 1A 20 1 24 30 1C 13 2B3 1B 21 1B 22 1A 10 VMEbus Signal Identification cont d Signal Name and Description INTERRUPT ACKNOWLEDGE Open collector or three state driven signal from any master processing an interrupt It is routed via the backplane to slot 1 where it is looped back to become slot 1 IACKIN in orde
56. r the received byte on top of the FIFO Therefore RR1 does not have to be checked after every receive byte This eliminates two VMEbus cycles from the receive character interrupt service routine When a special receive condition IACK vector is acquired the following sequence should be executed in the specified order 1 Read to determine the source of special condition 2 Issue reset error command in WRO to clear errors 3 Read the data register 3 3 2 Transmit Buffer Empty Interrupts Each of the four channels has its own Transmit Character available IE IP and IUS internal bits The IE bit is set ie transmit buffer interrupts are enabled by setting WRI DI If these interrupts are enabled two events can cause this IP to become set when the transmit buffer is ready to receive a byte RRO D2 1 and after the CRC is sent in synchronous modes RRO D2 0 IP is reset by writing to the data register or by issuing the Reset TxINT Pending command WRO 3 3 3 External Status Interrupts There are six sources of interrupts that share this IP 1 Break Abort 2 Underrun EOM 3 CTS 4 DCD 5 Sync Hunt 6 Zero Count Each of these sources has a separate enable bit in WRIS and has a separate status bit in RRO The master external status interrupt enable bit is WRI DO In general when a status bit changes state and is enabled the external status IP will be set and cause an interrupt The IP is reset by issuing the Reset Ext
57. r to start the interrupt acknowledge daisy chain INTERRUPT REQUEST 1 7 Open collector driven signals generated by interrupter which carry prioritized interrupt requests Level seven is the highest priority LONGWORD Three state driven signal indicates that the current transfer is a 32 bit transfer RESERVED Signal line reserved for future VMEbus enhancements This line must not be used A reserved signal which will be used as the clock for a serial communication bus protocol which is still being finalized A reserved signal which will be used as the transmission line for serial communication bus messages SYSTEM CLOCK A constant 16 MHz clock signal that is independent of processor speed or timing It is used for general system timing use 4 XVME 400 401 490 491 Manual October 1989 Table VMEbus Signal Identification cont d Connector Signal and M nemonic Pin Number Signal Name and Description SYSFAIL 1 10 SYSTEM FAIL Open collector driven signal that indicates that a failure has occurred in the system It may be generated by any module on the VMEbus SYSRESET 12712 SYSTEM RESET Open collector driven signal which when low will cause the system to be reset 1A 14 WRITE Three state driven signal that specifies the data transfer cycle in progress to be either read or write A high level indicates a read operation a low level indicates a write operation 5V STDBY 1B
58. rd accesses are used the register offsets listed in Table 3 1 would all be decremented by 1 Table 3 1 lists the offsets for the internal registers of all four serial channels on the XVME 400 two channels per SCC serial chip Table 3 1 Register Offsets Off set Address Hex Module Register Channel Control Register SCC 2 Channel B Channel Data Register SCC 2 Channel B Channel Control Register SCC 2 Channel A Channel Data Register SCC 2 Channel Channel Control Register SCC 1 Channel B Channel Data Register SCC 41 Channel B Channel Control Register SCC 1 Channel A Channel Data Register SCC 1 Channel A me HO In Cn o2 3 5 7 9 B D F The registers in the 8530 are accessed in a two step process The first step is to write a pointer to one of the four control registers listed in Table 34 After the pointer is written to a control register the next read or write to the same control register will access the desired 8530 register Refer to the 8530 Manual for a description of the 8530 registers and their pointers Single step access of a data is performed by reading writing to any of the four data registers 400 401 490 491 will automatically set D C high and will access the 8530 registers RRS or WRS directly independent of the state of the pointer bits 3 2 400 401 490 491 Manual October 1989 3 3 MODULE INTERRUPT SOURCES
59. ries the signals for Channels and 3 On the XVME 490 491 the signals for all four channels are carried on connector P2 All channels on all modules are configured as DTE Sources of JKI JK2 or P2 Connector Output Signals one set for each serial channel TXD SD SCC output pin TXD drives a line driver Driver output is sent to this pin RTS RS SCC output pin RTS drives a line driver Driver output is sent to this pin TXC TT SCC output pin TRXC drives a line driver Driver output is sent to this pin DTR TR SCC output pin DTR drives a line driver Driver output is sent to this pin NOTE The RS232C names XVME 400 490 are given to the left of the RS 485 422A signal names to the right the slash an 401491 line drivers invert the signal For modem control lines _writing a l to the a aye SCC writer register bit will cause the output to be asserted For TXD SD and the polarity defined by RS 232C or RS 485 is provided Destinations of JK JK2 or P2 Connector Input Signals one set for each serial channel RXD RD This input pin is buffered by a line receiver and is driven to the SCC input pin RXD CTS CS This input pin is buffered by a line receiver and is driven to the SCC input pin CTS RXC RT This input pin is buffered by a line receiver and is driven to the SCC input pin RTXC DCD RR_ This input pin is buffered by a line receiver and is driven to the SCC input pin DCD line receivers invert the s
60. s and connector pinouts Chapter Three Details covering functional addressing interrupt enabling and programming considerations and requirements Appendix A VMEbus connector and pin descriptions Appendix B Quick reference guide with jumper configurations Appendix C Block diagrams assembly drawings and schematics NOTE This manual XYCOM pe 74400 002 is part of a manual kit XYCOM a 74400 001 that is being shipped with the XVME 400 401 490 491 Modules The kit also contains an 8530 Manual referenced as XYCOM part 74400 003 This manual discusses module base addressing register access offsets interrupt control handshake control and operational mode programming constraints To better understand these topics is it recommended that you first read the 8530 Manual 78030 78530 SCC Serial Communications Controller Technical Manual Zilog January 1983 1 2 400 401 490 491 Manual October 1989 13 MODULE OPERATIONAL DESCRIPTION Figure 1 1 shows an operational block diagram of the X VME 400 and 490 and Figure 1 2 shows the block diagram for the X VME 401 and 491 kin Level Translation Scc 2 400 490 Figure 1 1 400 and 490 Operational Block Diagrams 1 3 400 401 490 491 Manual October 1989 E 221 RS 422 485 Translation RS 422 485 Translation Interrupter Control 401
61. ss Modifier Jumper JI or 7 Each 400 401 490 491 Module has one jumper that determines which address modifier codes it will respond to This jumper is on the XVME 400 490 and 7 on the XVME 401 491 see Figures 2 1 2 2 2 3 and 2 4 for the jumper location When this jumper is in the module will respond to supervisory short I O bus cycles only When this jumper is out the module will respond to both non privileged and supervisory short I O bus cycles Table 2 4 shows the relationship between this jumper and the address modifiers Table 2 4 Addressing Options Jumper Address odifier to which the XV M E 400 401 490 491 J1 XV M E 400 490 or Module will respond J7 XVME 401 491 Supervisory only QDH Supervisory or 29H Non privileged 2 4 3 Interrupt Level Selection Jumpers XVME 400 401 490 491 Module can either be configured to generate VMEbus interrupts at levels 1 7 or the module interrupt capability can be compile disabled Table 2 5 shows how jumpers JAI JA3 are used to determine the interrupt level status for the X VME 400 401 490 49 1 Module Table 2 5 Interrupt Level Jumper Positions In In In None VMEbus Interrupter disabled Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 The module is shipped from the factory with jumpers JA2 installed NOTE If the module is never required to generate interrupts JAI JA2 and JA3 should be
62. ter disabled Level Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 is installed 5V will be connected to pin 47 18 removed JKI 47 will float JI J2 is installed 5V will be connected to JK2 47 J2 is removed 247 will float If If If If B 2 XVME 400 401 490 491 Manual October 1989 Table 6 VMEbus Base Address Options ja jais janz jaio Short Address Space In In In In In In 0000H In In In In In out 0400H In In In In out In 0800H In In In In out out 0 00 In In In out In In 1000H In In In out In out 1400H In In In out out In 1800 In In In out out out 1COOH In In out In In In 2000H In In out In In out 2400 In In out In out In 2800H In In out In out out 2COOH In In out out In In 3000H In In out out In out 3400H In In out out out In 3800H In In out out out out 8 00 In out In In In In 4000H In out In In In out 4400H In out In In out In 4800H In out In In out out 4 00 In out In out In In 5000H In out In out In out 5400H In out In out out In 5800H In out In out out out 5 00 In out out In In In 6000 In out out In In out 6400H In out out In out In 6800 In out out In out out 6COOH In out out out In In 7000H In out out out In out 7400H In out out out out In 7800H In out out out out out 7COOH out In In In In In 8000H out In In In In out 8400H out In In In out In 8800H out In In In out out 8COOH out In In
63. w humidity may require protection against static discharge Altitude Operating _ Sea level to 10 000 ft 3048 m Non operating ri Sea level to 50 000 ft 15240 m 1 5 XVME 400 401 490 491 Manual October 1989 Table 1 1 400 40 1 490 49 1 Module Specifications cont Characteristic Specification Vibration Operating 5 to 2000 Hz 0 0 15 peak to peak displacement 2 5 g peak acceleration Non operating 5 to 5000 Hz 0 030 peak to peak displacement 5 0 g peak acceleration Shock Operating 30 g peak acceleration 11 msec duration Non operating 50 g peak acceleration 11 msec duration VMEbus Compliance Complies with VMEbus Specification IEEE 1014 A16 D8 0 Slave Interrupt vector D08 0 DYN 17 interrupter STAT ROAK XVME 400 401 Single form factor XVME 490 491 Double form factor VMEbus Timing Typ ns Max ns DSO Asserted to DTACK Asserted Read 650 800 DSO Asserted to DTACK Asserted Write 650 800 IACKIN Asserted to DTACK Asserted 1100 1200 DSO Negated to DTACK Negated All 60 100 IACKIN Asserted to IACKOUT Asserted 300 400 400 401 490 491 Manual October 1989 Chapter 2 INSTALLATION 2 1 INTRODUCTION This chapter explains how to configure an XVME 400 401 490 491 prior to installation in

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