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P89LPC930/931 8-bit microcontroller with two-clock core 4 KB

1. 2e S Slave Address R A DATA A DATA A 2e g MES L Data Transferred 1 Read n Bytes Acknowledge A Acknowledge SDA low From Master to Slave Not Acknowledge SDA high From Slave to Master S START condition Figure 8 Format of Master Receiver Mode After a repeated START condition 12C may switch to the Master Transmitter Mode S SLA R A DATA A DATA A RS SLA W A DATA A P Data Transferred n Bytes Acknowledge A Acknowledge SDA low A Not Acknowledge SDA high S START condition P STOP Condition SLA Slave Address RS Repeat START condition From Master to Slave From Slave to Master Figure 9 A Master Receiver switches to Master Transmitter after sending Repeated Start 2003 Dec 8 70 User s Manual Preliminary P89LPC930 931 Philips Semiconductors I C INTERFACE Slave Receiver Mode In the Slave Receiver Mode data bytes are received from a master transmitter To initialize the Slave Receiver Mode the user should write the slave address to the Slave Address Register I2ADR and the I C Control Register ICON should be configured as follows 7 6 5 4 3 2 1 0 2 D8h I2EN STA STO SI AA CRSEL 1 0 0 0 1 CRSEL is not used for slave mode I2EN must be se
2. 53 SFR Spate MET 54 Baud Rate Generator and selection 54 Updating the BRGR1 and BRGRO 5 54 Framing a c ueque tees et ees att et ge gu petu etd Ded Er E 55 Break Rust e al e EUR bU Op HO NU END 55 More about UART Mode oer s EM EE ad 57 More aboul UART bate iate i due 58 More about UART Modes 2 and 3 59 Framing Error and RI in Modes 2 and 3 with SM2 1 59 Break Deteob ui oti Dicen fof orb Reti pi rU Dee d e D d DEUS QE ad eue 59 Double TTS cer cT 60 Double buffering in different modes eee eene tnn 60 Transmit interrupts with double buffering enabled Modes 1 2 and 3 60 The 9th bit bit 8 in double buffering Modes 1 2 and 3 61 Multiprocessor communications 62 Automatic address recognition eae cceeeeeeeee 62 QUNM esci M MEET 65 lac Dala tegisiei totes nota turo e creel rah ete a ede 66 I2C Slave Address register c cceeseeeeeceeeeeeeecneceeceeeceeeeeteensnssensnntetenseecencecenseeneees 66 12C Control register r
3. INSTRUCTION SET PIEP Description Bytes Cycles Hex code ACALL addr 11 Absolute jump to subroutine 2 2 116F1 LCALL addr 16 Long jump to subroutine 3 2 12 RET Return from subroutine 1 2 22 RETI Return from interrupt 1 2 32 AJMP addr 11 Absolute jump unconditional 2 2 016E1 LJMP addr 16 Long jump unconditional 3 2 02 SJMP rel Short jump relative address 2 2 80 JC rel Jump on carry 1 2 2 40 JNC rel Jump on carry 0 2 2 50 JB bit rel Jump on direct bit 1 3 2 20 JNB bit rel Jump on direct bit 0 3 2 30 JBC bit rel Jump on direct bit 1 and clear 3 2 10 JMP A DPTR Jump indirect relative DPTR 1 2 73 JZ rel Jump on accumulator 0 2 2 60 JNZ rel Jump on accumulator 0 2 2 70 CJNE A dir rel Compare A direct jne relative 3 2 B5 CJNE A d rel Compare A immediate jne relative 3 2 B4 CJNE Rn d rel Compare register immediate jne relative 3 2 B8 BF CJNE Ri d rel Compare indirect immediate jne relative 3 2 B6 B7 DJNZ Rn rel Decrement register jnz relative 2 2 D8 DF DJNZ dir rel Decrement direct byte jnz relative 3 2 D5 MISCELLANEOUS NOP No operation 1 1 00 2003 Dec 8 126 Philips Semiconductors User s Manual Preliminary REVISION HISTORY SSL PC930 931 18 REVISION HISTORY 2003 Dec 8 Initial release 2003 Dec 8 127 Philips Semiconductors User s Manual Preliminary REVISION HISTORY P89LPC930 931 2003 Dec 8 128 Philips Sem
4. 21 High speed oscillator OpLUOro 21 Clock Fes yak bu 21 On chip oscillator ect bos Ouod De laco aaa emet os erosut 22 Watchdog oscillator option Iso otto mtd riter dnte mdt 22 External clock input ODllOIazu reno CHER CEPR p US eR ri o Fe Ra n FRU Dada fec D 22 Oscillator Clock OSCCLK wakeup delay 23 CPU Clock CCLK modification DIVM 24 LOW DOWBF dc Out be Medo S po sa Oud e 24 SUN TUS RUNS ries NES 25 Interrupt priority structure ces terae Rama SER 25 External Interrupt ia aseo roce inso ba ara PER pete quoa Da vate ove seta bn evt For FER UE 2D O dor se 26 External Interrupt pin glitch suppression eese 27 A VO POLS p 29 POTEGORTIQUEGUOTIS eun ssi ta and Gace tad tacet o alae 29 Quasi bidirectional output configuration 29 Open drain output configuration 30 em T 30 Push pull output configulaliQDi uass sociata mu aede quita rae eatin iu ES 31 Port 0 Ania lOG MUP CHOMS saei c
5. 00 50d ede cee ee eee ee eene 57 Serial Port Mode 0 double buffering must be 58 Serial Port Mode 1 only single transmit buffering case is shown 58 Serial Port Mode 2 or only single transmit buffering case is shown 59 FE and RI when SM2 1 in Modes 2 3 59 Transmission with and without double buffering 61 2003 Dec 8 6 Philips Semiconductors User Manual Subject to Change List of Figures P89LPC930 931 l2C bus configuration v aeos etes o et ea td ei hoo ta ne aes ene See 65 I2C Data Tegister 3 pH eae oan Re eae al A Was 66 I2C Slave Address register A SSE be 66 2 Control register cea iuter rar eror See aw Ee tod Ses hg 67 I2C Salus TegisIel orbi tees cee ARRAS A SRL LRL bee Sk TEE ERE 68 12C clock rates Selection o c iow Mek aes Ip ed wh aha A E C ra uu 68 2 Gonlrel Tegistel sese cre OP Even eue suns qux Wale edi meni eee 69 Format in the Master Transmitter Mode 70 Format of Master Receiver Mode 0 ccc cece eee eee eee 70 A Master Receiver switches to Master Transmitter after sending Repeated Start 70 Format of Slave Receiver Mode 71 Fo
6. AND FUNCTION TSSOP28 PLCC28 P2 0 P2 7 1 2 13 14 1 0 Port 2 Port 2 is a 8 bit I O port with a user configurable output type During reset Port 15 16 27 2 latches are configured in the input only mode with the internal pullup disabled The 28 operation of port 2 pins as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to the section on I O port configuration and the DC Electrical Characteristics for details All pins have Schmitt triggered inputs Port 2 also provides various special functions as described below 1 2 0 Port 2 bit 0 2 2 1 Port 2 bit 1 13 2 2 Port 2 bit 2 MOSI SPI master out slave When configured as master this pin is output when configured as slave this pin is input 14 y o P2 3 Port 2 bit 3 MISO SPI master in slave out When configured as master this pin is input when configured as slave this pin is output 15 2 4 Port 2 bit 4 ss SPI Slave select 16 1 0 P2 5 Port 2 bit 5 I O SPICLK SPI clock When configured as master this pin is output when configured as slave this pin is input Not available in 20 pin package 27 y o P2 6 Port 2 bit 6 28 2 7 Port 2 bit 7 P3 0 P3 1 9 8 Port 3 Port 3 is 2 bit I O port with a user configurable output type During reset Port 3 latches are configured in the input only mode with the internal pullup disabled The operation of port 3 pin
7. Figure 12 2 Comparator input and output connections Internal reference voltage An internal reference voltage Vref may supply a default reference when a single comparator input pin is used Please refer to the Datasheet for specifications Comparator interrupt Each comparator has an interrupt flag CMFn contained in its configuration register This flag is set whenever the comparator output changes state The flag may be polled by software or may be used to generate an interrupt The two comparators use one common interrupt vector The interrupt will be generated when the interrupt enable bit EC in the IEN1 register is set and the interrupt system is enabled via the EA bit in the IENO register If both comparators enable interrupts after entering the interrupt service routine the user will need to read the flags to determine which comparator caused the interrupt When a comparator is disabled the comparator s output COx goes high If the comparator output was low and then is disabled the resulting transition of the comparator output from a low to high state will set the the comparator flag CMFx This will cause an interrupt if the comparator interrupt is enabled The user should therefore disable the comparator interrupt prior to disabling the comparator Additionally the user should clear the comparator flag CMFx after disabling the comparator Comparators and power reduction modes Either or both comparators may remain enabl
8. A number of user configurable features of the P89LPC930 931 must be defined at power up and therefore cannot be set by the program after start of execution These features are configured through the use of an Flash byte UCFG1 shown in Figure 16 5 UCFG1 7 6 5 4 3 2 1 0 Address xxxxh WDTE RPE BOE WDSE FOSC2 FOSC1 FOSCO Unprogrammed value 63h BIT SYMBOL FUNCTION UCFG1 7 WDTE Watchdog timer reset enable When set 71 enables the watchdog timer reset When cleared 0 disables the watchdog timer reset The timer may still be used to generate an interrupt Refer to Table for details UCFG1 6 RPE Reset pin enable When set 1 enables the reset function of pin P1 5 When cleared P1 5 may be used as an input pin NOTE During a power up sequence the RPE selection is overriden and this pin will always functions as a reset input After power up the pin will function as defined by the RPE bit Only a power up reset will temporarily override the selection defined by RPE bit Other sources of reset will not override the RPE bit UCFG1 5 BOE Brownout Detect Enable see section Brownout Detection on page 35 UCFG1 4 WDSE Watchdog Safety Enable bit Refer to Table for details UCFG1 3 Reserved should remain unprogrammed at zero UCFG1 2 0 FOSC2 FSOCO CPU oscillator type select See section Clocks on page 21 for additional information Combinations other than those shown below should not be used Th
9. Block Diagram User s Manual Preliminary P89LPC930 931 High Performance Accelerated 2 clock 80C51 4KB 8KB Code Flash Internal Bus Port 3 Configurable I Os Port 2 Configurable I Os Port 1 Configurable I Os Port 0 Configurable I Os Keypad Interrupt Watchdog Timer and Oscillator Programmable Oscillator Divider Configurable Oscillator Crystal or Resonator 2003 Dec 8 CPU 256 byte Data RAM Real Time Clock System Timer TimerO Timer1 Analog Comparators Power Monitor On Chip Power On Reset RC Brownout Reset Oscillator 11 Philips Semiconductors User s Manual Preliminary General Description P89LPC930 931 Pin Descriptions MNEMONIC PIN NO for AND FUNCTION TSSOP28 PLCC28 0 P0 7 3 26 25 Port 0 Port 0 is 8 bit I O port with a user configurable output type During reset 24 23 22 Port 0 latches are configured in the input only mode with the internal pullup disabled 20 19 The operation of port 0 pins as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to the section on I O port configuration and the DC Electrical Characteristics for details The Keypad Interrupt feature operates with port 0 pins All pins have Schmitt triggered inputs Port 0 also provides various special functions as described
10. SFR Bit Functions and Addresses Reset Value Name Description Address MSB LSB Hex Binary WDCON Watchdog Control Register PRE2 PRE1 PREO z x WDRUN WDTOF WDCLK Notes 3 5 WDL Watchdog Load FFH 11111111 WFEED1 Watchdog Feed 1 C2H WFEED2 Watchdog Feed 2 C3H Notes SFRs are bit addressable SFRs are modified from or added to the 80C51 SFRs Reserved bits must be written with 0 s 5 BRGR1 and BRGRO must only be written if BRGEN in BRGCON SFR is 0 If any of them is written if BRGEN 1 result is unpredictable Unimplemented bits in SFRs labeled are X unknown at all times Unless otherwise specified ones should not be written to these bits since they may be used for other purposes in future derivatives The reset values shown for these bits are 0 s although they are unknown when read 1 All ports are in input only high impendance state after power up 2 The RSTSRC register reflects the cause of the LPC930 931 reset Upon a power up reset all reset source flags are cleared except POF and BOF the power on reset value is xx110000 3 After reset the value is 111001x1 i e PRE2 PREO are all 1 WORUN 1 and WDCLK 1 WDTOF bit is 1 after watchdog reset and is 0 after power on reset Other resets will not affect WDTOF 4 On power on reset the TRIM SFR is initialized with a factory preprogrammed value Other resets will not cause initialization of the
11. 107 ISP and IAP capabilities of the P89LPC930 931 107 Spec al th id tesa Pin imb ete e eer iad ned ate 108 Power On reset code execution 2 eese ke enn einn 108 Hardware activation of the Boot Loader ceca 108 In System Programming ISP ciue ener entente tonne dern rers 109 Using the In System Progrartnimirg ern ardiente e Det eis 109 In Application Programming method 114 IAP Authorization ode Ieod ps Len taper t Ac 114 User configuration DY LOS cce ates tee teet e 119 User security Dytes entice tesis aorta ae 120 2003 Dec 8 4 Philips Semiconductors User Manual Subject to Change Table of Contents P89LPC930 931 Boot GAYA ee 121 BOOUS TALUS neto il ee teres 121 T Set reco vete riga dete 123 18 Revision PIISIOTV oscuras e EEKK E quu ede detta reads 127 19 NAER ee e e Luo EE dote cid cese ded da dad 129 2003 Dec 8 5 Philips Semiconductors User Manual Subject to Change List of Figures P89LPC930 931 List of Figures P89LPC930 931 Memory 22 3 o duele ad Rr Ra Ro P One as we ex 19 On chip data memory
12. Erasing programming of a single byte or multiple bytes in code memory is accomplished using the following steps Write the LOAD command to The LOAD command will clear all locations in the page register and their corresponding update flags Write the address within the page register to FMADRL Since the loading the page register uses FMADRL 5 0 and since the erase program command uses FMADRH and FMADRL T 6 the user can write the byte location within the page register FMADRL 5 0 and the code memory page address FMADRH and FMADRL T7 6 at this time Write the data to be programmed to FMDATA This will increment FMADRL pointing to the next byte in the page register Write the address of the next byte to be programmed to FMADRL if desired Not needed for contiguous bytes since FMADRL is auto incremented All bytes to be programmed must be within the same page Write the data for the next byte to be programmed to FMDATA Repeat writing of FMADRL and or FMDATA until all desired bytes have been loaded into the page register Write the page address in user code memory to FMADRH and FMADRL 7 6 if not previously included when writing the page register address to FMADRL 5 0 Write the erase program command 68H to FMCON starting the erase program cycle 2003 Dec 8 104 Philips Semiconductors User s Manual Preliminary FLASH MEMORY P89LPC930 931 Read FMCON to check status If aborted repeat starting
13. 2003 Dec 8 98 Philips Semiconductors User s Manual Preliminary WATCHDOG TIMER P89LPC930 931 WDL C1H MOV WFEED1 0A5H MOV WFEED2 05AH Watchdog v Oscillator mE PRESCALER LJ 8 Bit Down RESET Counter Watchdog reset can also be caused 1 by an invalid feed sequence or by writing to WDCON not immediately EI E 4 followed by a feed sequence i SHADOW control register __ REGISTER FOR 1 WDCON A A A A A PRE2 PRE1 PREO WDRUN WDTOF WDCLK WDCON A7H Figure 14 3 Watchdog Timer in Watchdog Mode WDTE 1 Watchdog Timer in Timer Mode Figure 14 4 shows the Watchdog Timer in Timer Mode In this mode any changes to WDCON are written to the shadow register after one watchdog clock cycle A watchdog underflow will set the WDTOF bit If IENO 6 is set the watchdog underflow is enabled to cause an interrupt WDTOF is cleared by writing a 0 to this bit in software When an underflow occurs the contents of WDL is reloaded into the down counter and the watchdog timer immediately begins to count down again A feed is necessary to cause WDL to be loaded into the down counter before an underflow occurs Incorrect feeds are ignored in this mode 2003 Dec 8 99 Philips Semiconductors User s Manual Preliminary
14. Disclaimers Life support These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application Rightto make changes Philips Semiconductors reserves the right to make changes in the products including circuits standard cells and or software described or contained herein in order to improve design and or performance When the productis in full production status Production relevant changes will be communicated viaa Customer Product Process Change Notification CPCN Philips Semiconductors assumes no responsibility or liability for the use of any of these products conveys no license or title under any patent copyright or mask work right to these products and makes no representations or warranties that these products are free from patent copyright or mask work right infringement unless otherwise specified Contact information Koninklijke Philips Electronics N V 2003 For additional information please visit All rights reserved Printed in U S A http www semiconductors philips com Fax 431 40 27 24825 Date of release 12 03 Document order number 9397 750 12493 45 make things beter ness S PH
15. Note FE BR or OE is often accompanied by a RI which will generate an interrupt regardless of the state of STINT Note that BR can cause a break detect reset if EBRR AUXR1 6 is set to 1 Figure 9 4 Serial Port Status register SSTAT More about UART Mode 0 In Mode 0 a write to SBUF will initiate a transmission At the end of the transmission SCON 1 is set which must be cleared in software Double buffering must be disabled in this mode Reception is initiated by clearing RI SCON 0 Synchronous serial transfer occurs and RI will be set again at the end of the transfer When RI is cleared the reception of the next character will begin Refer to Figure 9 5 for timing 2003 Dec 8 57 Philips Semiconductors User s Manual Preliminary UART P89LPC930 931 s1 st6 s1 ste st te s1 516 s1 516 s1 516 s1 s16 st st6 st 16 s1 516 s1 516 s1 516 s1 516 Write to SBUF TI Transmit Write to SCON Clear RI RI Shift Receive RxD T Data In TxD Shift Clock l Figure 9 5 Serial Port Mode 0 double buffering must be disabled More about UART Mode 1 Reception is initiated by detecting a 1 to 0 transition on RxD RxD is sampled at a rate 16 times the programmed baud rate When a transition is detected the divide by 16 counter is immediately reset Each bit time is thus divided int
16. WATCHDOG TIMER P89LPC930 931 WDL C1H MOV WFEED1 0A5H MOV WFEED2 05 A Watchdog v Oscillator PRESCALER LJ 8 Bit Down i Counter Interrupt CLK SHADOW control register __ REGISTER FOR 1 WDCON v PRE2 PRE1 PREO WDRUN WDTOF WDCLK WDCON AT7H Figure 14 4 Watchdog Timer in Timer Mode WDTE 0 Power down operation The WDT oscillator will continue to run in power down consuming approximately 50uA as long as the WDT oscillator is selected as the clock source for the WDT Selecting PCLK as the WDT source will result in the WDT oscillator going into power down with the rest of the device see section Watchdog Clock Source on page 98 Power down mode will also prevent PCLK from running and therefore the watchdog is effectively disabled Periodic wakeup from Power down without an external oscillator Without using an external oscillator source the power consumption required in order to have a periodic wakeup is determined by the power consumption of the internal oscillator source used to produce the wakeup The Real time clock running from the internal RC oscillator can be used The power consumption of this oscillator is approximately 300uA Instead if the WDT is u
17. P1M1 0 11x1xx11 P1M2 Port 1 Output Mode 2 92H P1M2 7 P1M2 6 P1M2 4 P1M2 3 P1M2 2 P1M2 1 P1M2 0 00H 00x0xx00 P2M1 Port 2 Output Mode 1 P2M1 7 P2M1 6 P2M1 5 P2M1 4 P2M1 3 P2M1 2 P2M1 1 P2M1 0 FFH 11111111 P2M2 Port 2 Output Mode 2 A5H 2 2 7 2 2 6 P2M2 5 P2M2 4 P2M2 3 2 2 2 2 2 1 2 2 0 00H 00000000 P3M1 Port 3 Output Mode 1 B1H P3M1 1 P3M1 0 03H 11 P3M2 Port 3 Output Mode 2 B2H P3M2 1 P3M2 0 00H 00 2003 Dec 8 16 Philips Semiconductors User s Manual Preliminary General Description P89LPC930 931 SFR Bit Functions and Addresses Reset Value Name Description Address MSB LSB Hex Binary PCON Control Register 87H SMOD1 SMODO BOPD BOI GF1 PMOD1 PMODO 00H 00000000 PCONA Control Register A B5H RTCPD VCPD I2PD SPPD SPD 00H 00000000 D7 D6 D5 D4 D3 D2 D1 DO PSW Program Status Wword DOH FO RS1 RSO OV F1 P 00H 00000000 PTOAD PPortO Digital Input Disable F6H PTOAD 5 PTOAD 4 PTOAD 3 PTOAD 2 PTOAD 1 OOH xx00000x RSTSRC Reset Source Register DFH BOF POF R BK R WD R SF R EX Note 2 RTCCON Real Time Clock C
18. SPI Clock Genera tor SPICLK SS SPICLK E SS User s Manual Preliminary P89LPC930 931 Slave Master ISO k MISO Dx 8 Bit Shift Register SPI Clock Genera tor Figure 11 6 SPI dual device configuration where either can be a master or a slave Figure 11 6 shows a case where two devices are connected to each other and either device can be a master or a slave When no SPI operation is occuring both can be configured as masters MSTR 1 with SSIG cleared to 0 and P2 4 SS configured in quasi bidirectional mode When a device initiates a transfer it can configure P2 4 as an output and drive it low forcing a mode change in the other device see section Mode change on SS to slave 8 Bit Shift Register 8 Bit Shift Register SPICLK SPICLK SPI Clock Genera tor 8 Bit Shift Register Figure 11 7 SPI single master multiple slaves configuration In Figure 11 7 SSIG SPCTL 7 bits for the slaves are 0 and the slaves are selected by the corresponding SS signals The SPI master can use any port pin including P2 4 SS to drive the SS pins 2003 Dec 8 84 Philips Semiconductors User s Manual Preliminary SERIAL PERIPHERAL INTERFACE SPI P89LPC930 931 CONFIGURING THE SPI Table 11 1 shows configuration for the master slave modes as well a
19. Status Bus Status Decoder I2STAT Status Register Figure 12 I C bus serial interface block diagram 2003 Dec 8 73 Philips Semiconductors I C INTERFACE Table 2 Master Transmitter Mode User s Manual Preliminary P89LPC930 931 Status Application software response code Status of the Next action taken by 25 I2C bus hardware to from I2DAT to I2CON hardware STA STO SI A START condition SLA W will be transmitted ACK bit will be 08H has been Load SLA W x 0 0 received transmitted A repeat START Load SLA W As above SLA W will be transmitted 10H condition has been x 0 0 12C switches to Master Receiver Mode F Load SLA R transmitted Load data byte or 0 0 0 Data byte will be transmitted ACK bit will be received I2DAT action or 1 0 0 Repeated START will be transmitted SLA W has been EE ish transmitted ACK no I2DAT action or 0 4 0 condition will be transmitted has been received ag will be reset no I2DAT action 4 4 0 STOP condition followed by a START condition will be transmitted STO flag will be reset Load data byte or 0 0 0 Data byte will be transmitted ACK bit will be received SLA W has been no I2DAT actionor 1 0 0 Repeated START will be transmitted 20h transmitted NOT STOP condition will be transmitted STO ACK has been I2DAT action or 0 1 0 wall reet received ST
20. control register but a feed sequence is required to load from the WDL SFR to the 8 bit down counter before a time out occurs WDCON 7 6 5 4 3 2 1 0 PRE2 PRE1 PREO WDRUN WDTOF WDCLK Address A7h Not bit addressable Reset Source s See reset value below Reset Value 111xx1 1B Note WDCON 7 6 5 2 0 set to 1 any reset WDCON 1 cleared to 0 on Power on reset set to 1 on watchdog reset not affected by any other reset BIT SYMBOL FUNCTION WDCON 7 5 PRE2 PREO Clock Prescaler Tap Select Refer to Table for details WDCON 4 3 Reserved for future use Should not be set to 1 by user program WDCON 2 WDRUN Watchdog Run Control The watchdog timer is started when WDRUN 1 and stopped when WDRUN 0 This bit is forced to 1 watchdog running and cannot be cleared 0 if both WDTE and WDSE are set to 1 WDCON 1 WDTOF Watchdog Timer Time Out Flag This bit is set when the 8 bit down counter underflows In watchdog mode a feed sequence will clear this bit It can also be cleared by writing O to this bit in software WDCON O WDCLK Watchdog input clock select When set the watchdog oscillator is selected When cleared PCLK is selected If the CPU is powered down the watchdog is disabled if WDCLK 0 see section Power down operation Note If both WDTE and WDSE are set to 1 this bit is forced to 1 Refer to section Watchdog Clock Source on page 98 for details Figu
21. erased by the user Users who wish to use this loader should take cautions to avoid erasing the last 1KB sector on the device Instead the page erase function can be used to erase the eight 64 byte pages located in this sector A custom boot loader can be written with the Boot Vector set to the custom boot loader if desired FLASH END SIGNATURE BYTES sector PAGE PRE PROGRAMMED DEFAULT TRA Size SIZE SIZE BOOT ADDRESS MFG 1 1 1 2 SERIAL LOADER VECTOR P89LPC931 8Kx8 1FFF 15H DDH 09H 1Kx8 64x8 1E00H 1FFFH 1FH P89LPC930 4Kx8 OFFF 15H DDH 19H 1Kx8 64x8 OFH Table 16 1 Boot Loader Address and Default Boot Vector Hardware activation of the Boot Loader The boot loader can also be executed by forcing the device into ISP mode during a power on sequence see Figure 16 4 This is accomplished by powering up the device with the reset pin initially held low and holding the pin low for a fixed time after VDD rises to its normal operating value This is followed by three and only three properly timed low going pulses Fewer or more than three pulses will result in the device not entering ISP mode Timing specifications may be found in the datasheet for this device This has the same effect as having a non zero status bit This allows an application to be built that will normally execute the user code but can be manually forced into ISP operation If the factory default setting for t
22. see text Timer 1 in this mode is stopped 100 Reserved User must not configure to this mode 101 Reserved User must not configure to this mode 110 PWM mode see section Mode 6 111 Reserved User must not configure to this mode Figure 7 2 Timer Counter Auxiliary Mode Control register TAMOD Mode 0 Putting either Timer into Mode 0 makes it look like an 8048 Timer which is an 8 bit Counter with a divide by 32 prescaler Figure 7 4 shows Mode 0 operation In this mode the Timer register is configured as a 13 bit register As the count rolls over from all 1s to all Os it sets the Timer interrupt flag TFn The count input is enabled to the Timer when TRn 1 and either 0 or INTn 1 Setting TRGATE 1 allows the Timer to be controlled by external input INTn to facilitate pulse width measurements TRn is a control bit in the Special Function Register TCON Figure 7 3 The bit is in the register The 13 bit register consists of all 8 bits of THn and the lower 5 bits of TLn The upper 3 bits of TLn are indeterminate and should be ignored Setting the run flag TRn does not clear the registers Mode 0 operation is the same for Timer 0 and Timer 1 See Figure 7 4 There are two different GATE bits one for Timer 1 TMOD 7 and one for Timer 0 TMOD 3 Mode 1 Mode 1 is the same as Mode except that all 16 bits of the timer register THn and TLn are used See Figure 7 5 2003
23. 0 s to enable the digital functions 2003 Dec 8 31 Philips Semiconductors PORTS User s Manual Preliminary P89LPC930 931 Configuration SFR bits Port pin Alternate usage Notes PxM1 y PxM2 y P0 0 POM1 0 POM2 0 KBIO CMP2 1 1 1 2 1 KBI1 CIN2B SE POMA pve Refer to section Port 0 analog functions for usage as P0 3 POM1 3 POM2 3 KBI3 CIN1B analog inputs CIN2B CIN2A CIN1B CIN1A and P0 4 POM1 4 POM2 4 KBI4 CIN1A P0 5 POM1 5 POM2 5 KBI5 CMPREF P0 6 POM1 6 POM2 6 KBI6 CMP1 P0 7 POM1 7 POM2 7 KBI7 T1 P1 0 P1M1 0 P1M2 0 TxD P1 1 P1M1 1 P1M2 1 RxD P1 2 P1M1 2 P1M2 2 TO SCL input only or open drain P1 3 P1M1 3 P1M2 3 INTO SDA input only or open drain P1 4 P1M1 4 P1M2 4 INT RI Input only Usage as general purpose input or RST is P1 5 not configurable RST determined by User Configuration Bit RPD UCFG1 6 Always a reset input during a power on sequence P1 6 P1M1 6 P1M2 6 P1 7 P1M1 7 P1M2 7 P2 0 P2M1 0 P2M2 0 P2 1 P2M1 1 P2M2 1 P2 2 P2M1 2 P2M2 2 MOSI P2 3 P2M1 3 P2M2 3 MISO P2 4 P2M1 4 P2M2 4 ss P2 5 P2M1 5 P2M2 5 SPICLK P2 6 P2M1 6 P2M2 6 P2 7 P2M1 7 P2M2 7 P3 0 P3M1 0 P3M2 0 XTAL2 CLKOUT P3 1 P3M1 1 P3M2 1 XTAL1 Table 4 3 Port output configuration Additional port features After power up all pins are in Input Only mode Please note that this is differen
24. 0A Security Byte 2 0B Security Byte 3 0C Security Byte 4 00 Security Byte 5 Security Byte 6 OF Security Byte 7 Return parameter s R7 register data if no error else error status set on error clear on no error Input parameters ACC 04 R7 00H erase page or 01H erase sector R4 sector page address MSB Erase Sector Page requires key R5 sector page address LSB Return parameter s R7 status set on error clear on no error 2003 Dec 8 117 Philips Semiconductors User s Manual Preliminary FLASH MEMORY P89LPC930 931 Table 16 4 IAP function calls IAP function IAP call parameters Input parameters ACC 05h R7 sector address Return parameter s R4 CRC bits 31 24 Read Sector CRC R5 CRC bits 23 16 R6 CRC bits 15 8 R7 CRC bits 7 0 if no error R7 error status if error set on error clear on no error Input parameters ACC 06h Return parameter s R4 CRC bits 31 24 Read Global CRC R5 CRC bits 23 16 R6 CRC bits 15 8 R7 CRC bits 7 0 if no error R7 error status if error set on error clear on no error Input parameters ACC 07h R4 address MSB Read User Code R5 address LSB Return parameter s R7 data 2003 Dec 8 118 Philips Semiconductors User s Manual Preliminary FLASH MEMORY P89LPC930 931 User configuration bytes
25. 2 0 This bit contains a hard wired 0 Allows toggling of the DPS bit by incrementing AUXR1 without interfering with other bits in the register AUXR1 1 Not used Allowable to set to a 1 AUXR1 0 DPS Data Pointer Select Chooses one of two Data Pointers Figure 15 1 AUXR1 register Software reset The SRST bit in AUXR1 gives software the opportunity to reset the processor completely as if an external reset or watchdog reset had occurred If a value is written to AUXR1 that contains a 1 at bit position 3 all SFRs will be initialized and execution will resume at program address 0000 Care should be taken when writing to AUXR1 to avoid accidental software resets Dual Data Pointers The dual Data Pointers DPTR adds to the ways in which the processor can specify the address used with certain instructions The DPS bit in the AUXR1 register selects one of the two Data Pointers The DPTR that is not currently selected is not accessible to software unless the DPS bit is toggled Specific instructions affected by the Data Pointer selection are INC DPTR Increments the Data Pointer by 1 JMP A DPTR Jump indirect relative to DPTR value MOV DPTR data16 Load the Data Pointer with a 16 bit constant 2003 Dec 8 101 ADDITIONAL FEATURES P89LPC930 931 MOVCA A DPTR Move code byte relative to DPTR to the accumulator MOVXA DPTR Move data byte the accumulator to data memory relative to DPTR MOVX DPTR A Move data byte
26. 20 On chip RC oscillator TRIM 22 Using th he crystal oscilator 5 5 is ninnan bese wa Rar sehe 23 Block diagram of oscillator Controls se scenes Rex eV EI REG Re tx 23 Interrupt priority levelsg 3 055 Via reuse uma RR eke bo dd RC ro Pede oe 25 Summary of Intermupls v2 da hod cetur acte eal ks de pde ad este le de t 26 Interrupt sources interrupt enables and power down wake up sources 27 Number of I O pins available 5 2 2 2 a data wes Gag Feed Dia SBS cule es eae 8 29 Port output configuration 5 29 Quasi bidirectional Outputs 5 a t certs ii Bae Eres eias Re 30 Oper 13 35 nr cand o B Ra ba dar Sn a AR Ru o LT Vt on 30 Iri pill SONNY a eoi S BY sag verfio ste telis cR DLE EU ee AES daa 31 Pushspalloilpub ula aie ecd Nh e oc Mea ure 31 Portoutp bconfigiralio sarei rede es Sent ed sod e bip epic 32 Brownout options cla qt hehe os 36 Power reduction modes ev REESE ERASILELELERURRERAG ETE ee E es 37 Power Control register 38 Power Control register 39 Block diagram of Reset ato deed ib be Sieh dade dred Sued ech sas Sa
27. 4 KBMASK 3 KBMASK 2 KBMASK 1 KBMASK 0 BIT SYMBOL FUNCTION KBMASK 7 When set enables 7 as a cause of a Keypad Interrupt KBMASK 6 When set enables P0 6 as a cause of a Keypad Interrupt KBMASK 5 When set enables P0 5 as a cause of a Keypad Interrupt KBMASK 4 When set enables P0 4 as a cause of a Keypad Interrupt KBMASK 3 When set enables 3 as a cause of a Keypad Interrupt KBMASK 2 When set enables P0 2 as a cause of a Keypad Interrupt KBMASK 1 When set enables 1 as a cause of a Keypad Interrupt KBMASK 0 When set enables P0 0 as a cause of a Keypad Interrupt Note the Keypad Interrupt must be enabled in order for the settings of the KBMASK register to be effective Figure 13 3 Keypad Interrupt Mask register KBM 2003 Dec 8 94 Philips Semiconductors User s Manual Preliminary WATCHDOG TIMER P89LPC930 931 14 WATCHDOG TIMER The watchdog timer subsystem protects the system from incorrect code execution by causing a system reset when it underflows as a result of a failure of software to feed the timer prior to the timer reaching its terminal count The watchdog timer can only be reset by a power on reset Watchdog Function The user has the ability using the WDCON and UCFG 1 registers to control the run stop condition of the WDT the clock source for the WDT the prescaler value and whether the WDT is enabled to reset the device on underflow In addition there is
28. 75 MOV Ri A Move A to indirect memory 1 1 F6 F7 MOV Ri dir Move direct byte to indirect memory 2 2 A6 A7 MOV Ri data Move immediate to indirect memory 2 1 76 77 MOV DPTR data Move immediate to data pointer 3 2 90 MOVC A A DPTR Move code byte relative DPTR to A 1 2 93 MOVC A A PC Move code byte relative PC toA 1 2 94 MOVX A Ri Move external data A8 to A 1 2 E2 E3 MOVX A DPTR Move external data A16 to A 1 2 EO MOVX Ri A Move A to external data A8 1 2 F2 F3 MOVX DPTR A Move A to external data A16 1 2 FO PUSH dir Push direct byte onto stack 2 2 CO POP dir Pop direct byte from stack 2 2 DO XCH Exchange A and register 1 1 C8 CF A ir Exchange A and direct byte 2 1 C5 XCH A Ri Exchange A and indirect memory 1 1 C6 C7 XCHD A QRi Exchange A and indirect memory nibble 1 1 D6 D7 BOOLEAN Mnemonic Description Bytes Cycles Hex code CLR C Clear carry 1 1 C3 CLR bit Clear direct bit 2 1 C2 SETBC Set carry 1 1 D3 SETB bit Set direct bit 2 1 D2 CPL C Complement carry 1 1 B3 CPL bit Complement direct bit 2 1 B2 ANL C bit AND direct bit to carry 2 2 82 ANL C bit AND direct bit inverse to carry 2 2 BO ORL C bit OR direct bit to carry 2 2 72 ORL C bit OR direct bit inverse to carry 2 2 AO MOV C bit Move direct bit to carry 2 1 A2 MOV bit C Move carry to direct bit 2 2 92 2003 Dec 8 BRANCHING 125 Philips Semiconductors User s Manual Preliminary
29. Command data function Erase Sector Page 03 04 Where XXXX required field but value is a don t care aaaa address ss 01 erase sector 00 erase page cc checksum Example 03000004010000F8 Read Sector CRC 01xxxx05aacc Where XXXX required field but value is a don t care aa 7 sector address high byte cc checksum Example 0100000504F6cc Read Global CRC 00xxxx06cc Where 06 XXXX required field but value is a don t care cc checksum Example 00000006FA Direct Load of Baud Rate 02xxxx07 HHLLcc Where XXXX required field but value is a don t care HH high byte of timer LL low byte of timer cc checksum Example 02000007FFFFcc 2003 Dec 8 113 Philips Semiconductors User s Manual Preliminary FLASH MEMORY P89LPC930 931 Table 16 2 In System Programming ISP hex record formats Record type Command data function Reset MCU 00xxxx08cc Where XXXX required field but value is a don t care cc checksum Example 00000008F8 In Application Programming method Several In Application Programming IAP calls are available for use by an application program to permit selective erasing and programming of Flash sectors pages security bits configuration bytes and device id All calls are made through a common interface PGM_MTP The programming functions are selecte
30. Dec 8 22 Philips Semiconductors User s Manual Preliminary CLOCKS P89LPC930 931 Quartz crystalor ceramic resonator P89LPC930 931 The oscillator must be configured in one of the following modes Low Frequency Crystal al XTALI Medium Frequency Crystal High Frequency Crystal 1 T XTAL2 A series resistor may be required to limit E crystal drive levels This is especially important for low frequency crystals see E text Figure 2 2 Using the crystal oscillator RTCS1 0 XTAL1 High freq RTC XTAL2 Low freq FOSC2 0 DIVM CPU RC Oscillator 7 3728MHz WDT Watchdog Oscillator PCLK 400KHz Peripheral Clock Baud Rate UART Timer 0 amp 1 c Generator Figure 2 3 Block diagram of oscillator control Oscillator Clock OSCCLK wakeup delay The P89LPC930 931 has an internal wakeup timer that delays the clock until it stabilizes depending to the clock source used If the clock source is any of the three crystal selections the delay is 992 OSCCLK cycles plus 60 100us If the clock source is either the internal RC oscillator or the Watchdog oscillator the delay is 224 OSCCLK cycles plus 60 100us 2003 Dec 8 23 Philips Semiconductors User s Manual Preliminary P89LP 1 CLOCKS 89LPC930 93 CPU Clock CCLK modification DIVM register The OSCCLK frequency can
31. Functions 02xxxx02ssddcc Where XXXX required field but value is a don t care ss subfunction code dd data cc checksum Subfunction codes 00 UCFG1 01 reserved 02 Boot Vector 03 Status Byte 04 reserved 02 05 reserved 06 reserved 07 reserved 08 Security Byte 0 09 Security Byte 1 0A Security Byte 2 0B Security Byte 3 0C Security Byte 4 0 Security Byte 5 Security Byte 6 OF Security Byte 7 Example 020000020347cc 2003 Dec 8 111 Philips Semiconductors FLASH MEMORY Table 16 2 In System Programming ISP hex record formats User s Manual Preliminary P89LPC930 931 Record type Command data function Miscellaneous Read Functions 01xxxx03sscc Where XXXX required field but value is a don t care ss subfunction code cc checksum Subfunction codes 00 UCFG1 01 reserved 02 Boot Vector 03 Status Byte 04 reserved 05 reserved 06 reserved 03 07 reserved 08 Security Byte 0 09 Security Byte 1 0A Security Byte 2 0B Security Byte 3 0C Security Byte 4 0 Security Byte 5 Security Byte 6 OF Security Byte 7 10 Manufacturer Id 11 Device Id 12 Derivative Id Example 0100000312cc 2003 Dec 8 112 Philips Semiconductors User s Manual Preliminary FLASH MEMORY P89LPC930 931 Table 16 2 In System Programming ISP hex record formats Record type
32. STOP condition has been received and it switches to not addressed Slave Receiver Mode The STO flag is cleared by hardware automatically I2CON 3 SI 2 Interrupt Flag This bit is set when one of the 25 possible 12 states is entered When EA bit and EI2C IEN1 0 bit are both set an interrupt is requested when SI is set Must be cleared by software by writing O to this bit I2CON 2 AA The Assert Acknowledge Flag When set to 1 an acknowledge low level to SDA will be returned during the acknowledge clock pulse on the SCL line on the following situations 1 The own slave address has been received 2 The general call address has been received while the general call bit GC in I2ADR is set 3 A data byte has been received while the I C interface is the Master Receiver Mode 4 A data byte has been received while the I C interface is in the addressed Slave Receiver Mode When cleared to 0 an not acknowledge high level to SDA will be returned during the acknowledge clock pulse on the SCL line on the following situations 1 A data byte has been received while the I C interface is in the Master Receiver Mode 2 A data byte has been received while the I C interface is in the addressed Slave Receiver Mode I2CON 1 Reserved for future use Should not be set to 1 by user programs I2CON O CRSEL SCL clock selection When set 1 Timer1 overflow generates SCL when cleared 0 the internal SCL generator is used base on values
33. a START condition afterwards If it is in slave mode an internal STOP condition will be generated but it is not transmitted to the bus I2CON Address D8h 7 6 5 4 3 2 1 0 Bit addressable I2EN STA STO SI AA CRSEL Reset Source s Any reset Reset Value x00000x0B BIT SYMBOL FUNCTION I2CON 7 Reserved for future use Should not be set to 1 by user programs I2CON 6 I2EN 12C Interface Enable When set enables the 12C interface When clear the I C function is disabled I2CON 5 STA Start Flag STA 1 12 enters master mode checks the bus and generates a START condition if the bus is free If the bus is not free it waits for a STOP condition which will free the bus and generates a START condition after a delay of a half clock period of the internal clock generator When the 12C interface is already in master mode and some data is transmitted or received it transmits a repeated START condition STA may be set at any time it may also be set when the interface is an addressed slave mode STA 0 no START condition or repeated START condition will be generated I2CON 4 STO STOP Flag STO 1 In master mode a STOP condition is transmitted to the I2C bus When the bus detects the STOP condition it will clear STO bit automatically In slave mode setting this bit can recover from an error condition In this case no STOP condition is transmitted to the bus The hardware behaves as if a
34. a safety mechanism which forces the WDT to be enabled by values programmed into UCFG1 either through IAP or a commercial programmer The WDTE bit UCFG1 7 if set enables the WDT to reset the device on underflow Following reset the WDT will be running regardless of the state of the WDTE bit The WDRUN bit WDCON 2 can be set to start the WDT and cleared to stop the WDT Following reset this bit will be set and the WDT will be running All writes to WDCON need to be followed by a feed sequence see section Feed Sequence on page 96 Additional bits in WDCON allow the user to select the clocksource for the WDT and the prescaler When the timer is not enabled to reset the device on underflow the WDT can be used in timer mode and be enabled to produce an interrupt IENO 6 if desired The Watchdog Safety Enable bit WDSE UCFG1 4 along with WDTE is designed to force certain operating conditions at power up Refer to the Table for details Table 14 1 Watchdog timer configuration WDTE WDSE UCFG1 7 UCFG1 4 FUNGTION 0 n The watchdog reset is disabled The timer can be used as an internal timer and can be used to generate an interrupt WDSE has no effect 4 0 The watchdog reset is enabled The user can set WDCLK to choose the clock Source The watchdog reset is enabled along with additional safety features 4 4 1 WDCLK is forced to 1 using watchdog oscillator 2 WDCON and WDL register can only be written once 3 WDRU
35. accessed as part of program execution and via the MOVC instruction The P89LPC930 931 has 4 KB 8 KB of on chip Code memory 2003 Dec 8 19 Philips Semiconductors General Description DATA RAM ARRANGEMENT The 256 bytes of on chip RAM is organized as follows User s Manual Preliminary P89LPC930 931 Type Data RAM Size Bytes DATA Memory that can be addressed directly and indirectly 128 IDATA Memory that can be addressed indirectly includes DATA 256 Table 1 1 On chip data memory usage 2003 Dec 8 20 Philips Semiconductors User s Manual Preliminary CLOCKS P89LPC930 931 2 CLOCKS Enhanced CPU The P89LPC930 931 uses an enhanced 80C51 CPU which runs at 6 times the speed of standard 80C51 devices A machine cycle consists of two CPU clock cycles and most instructions execute in one or two machine cycles Clocks Clock definitions The P89LPC930 931 device has several internal clocks as defined below OSCCLK Input to the DIVM clock divider OSCCLK is selected from one of four clock sources see Figure 2 3 and can also be optionally divided to a slower frequency see section CPU Clock CCLK modification DIVM register Note fosc is defined as the OSCCLK frequency CCLK CPU clock output of the DIVM clock divider There are two CCLK cycles per machine cycle and most instructions are executed in one to two machine cycles two or four CCLK cycles RCCLK The
36. action 4 0 0 x A START condition will be transmitted when the bus becomes free Table 3 Master Receiver Mode Status Application software response code Status of the Next action taken by 2 125 2 5 hardware to from I2DAT to I2CON hardware STA STO SI AA A START condition SLA R will be transmitted 08H has been Load SLA R x 0 0 x ACK bit will be received transmitted Load SLA R or X 0 0 x As above STARTcondition 10H nas been SLA W will be transmitted transmitted Load SLA W x 0 0 x I C will be switches to Master Transmitter Mode no I2DAT action or 0 0 0 x I C will be released it will enter a XEM slave mode 38H Arbitration lost in TART am SR NOT ACK bit conaition WI e no I2DAT action 1 0 0 x transmitted when the bus becomes free Data byte will be received aoh S9LA Rhasbeen l2DAT action or 0 0 NOT ACK bit will be returned transmitted ACK ae has been received no I2DAT action or 0 0 0 4 Data byte will be received ACK bit will be returned 2003 Dec 8 75 Philips Semiconductors User s Manual Preliminary I C INTERFACE P89LPC930 931 Table 3 Master Receiver Mode Continued Status Application software response code Status of the Next action taken by 2 I2STAT I C bus hardware to from I2DAT to I2CON hardware STA STO SI AA No I
37. be recognized if IZADR O 1 addressed with own Switched to not addressed SLA mode no 88H SLA address Data read data byte 0 0 recognition of own SLA or General call has been received or address A START condition will be NACK has been transmitted when the bus becomes free returned Switched to not addressed SLA mode Own slave address will be recognized General read data byte 1 0 0 call address will be recognized if IZADR 0 1 A START condition will be transmitted when the bus becomes free Previously Read data byte or x 0 0 Data byte will be received and NOT ACK will addressed with be returned goH General call Data byte will be received and ACK will be Datahas been rat mtd received ACK has read data byte X 0 0 been returned 2003 Dec 8 77 Philips Semiconductors I C INTERFACE Table 4 Slave Receiver Mode Continued User s Manual Preliminary P89LPC930 931 Status Application software response code Status of the Next action taken by 2 I2STAT I C bus hardware to from I2DAT to I2CON hardware STA STO SI Read data bvt Switched to not addressed SLA mode no 0 0 0 recognition of own SLA or General call address Switched to not addressed SLA mode Own read data byte 0 0 0 slave address will be recognized General call address will be recognized if I2ADR 071 Previously addressed with Switched to not addressed SLA mode no Ge
38. below 3 P0 0 Port 0 bit 0 O CMP2 Comparator 2 output KBIO Keyboard Input 0 26 P0 1 Port 0 bit 1 CIN2B Comparator 2 positive input KBI1 Keyboard Input 1 25 P0 2 Port 0 bit 2 CIN2A Comparator 2 positive input KBI2 Keyboard Input 2 24 P0 3 Port 0 bit 3 CIN1B Comparator 1 positive input B Keyboard Input 3 23 y o 0 4 Port 0 bit 4 CIN1A Comparator 1 positive input A Keyboard Input 4 22 0 5 Port 0 bit 5 CMPREFComparator reference negative input KBI5 Keyboard Input 5 20 y o 0 6 Port 0 bit 6 CMP1 Comparator 1 output KBI6 Keyboard Input 6 19 y o P0 7 Port 0 bit 7 1 Timer counter 1 external count input overflow output KBI7 Keyboard Input 7 2003 Dec 8 Philips Semiconductors General Description User s Manual Preliminary P89LPC930 931 MNEMONIC PIN NO for AND FUNCTION TSSOP28 PLCC28 P1 0 P1 7 18 17 12 l O for Port 1 Port 1 is an 8 bit I O port with user configurable output type except for three 11 10 6 5 P1 0 P1 4 pins as noted below During reset Port 1 latches are configured in the input only mode 4 P1 6 P1 7 with the internal pullup disabled The operation of the configurable port 1 pins as inputs for P1 5 and outputs depends upon the port configuration selected Each of the configurable port pins are programmed
39. clears page register MOV FMADRH R4 get high address OV FMADRL R5 get low address OV A R7 MOV RO A get pointer into RO LOAD PAGE OV FMDAT RO write data to page register INC RO point to next byte DJNZ R3 LOAD PAGE do until count is zero OV FMCON EP else erase amp program the page OV R7 FMCON copy status for return OV A R7 read status ANL A 0FH Save only four lower bits JNZ BAD CLR C clear error flag if good RET and return BAD SETB Set error flag RET and return Figure 16 2 Assembly language routine to erase program all or part of a page 2003 Dec 8 106 Philips Semiconductors User s Manual Preliminary FLASH MEMORY P89LPC930 931 tinclude lt REG931 H gt nsigned char idata dbytes 64 data buffer nsigned char Fm_stat status result bit PGM USER unsigned char unsigned char bit prog fail oid main prog fail PGM USER Ox1F O0xC0 bit USER unsigned char page hi unsigned char page lo define LOAD 0x00 clear page register enable loading fdefine EP 0x68 erase amp program page unsigned char i loop count FMCON LOAD load command clears page reg FMADRH page hi FMADRL page 10 write my page address to addr regs for 1 0 1 lt 64 1 1 FMDATA dbytes i FMCON EP erase amp prog page command Fm stat FMCON cead the result status if Fm stat amp Ox0F 0 prog fail 1 else prog fail 0
40. configuration 28 Pin TSSOP Package P2 0 P2 1 KBIO CMP2 P0 0 P1 7 P1 6 RST P1 5 VSS XTAL1 P3 1 CLKOUT XTAL2 P3 0 INTI P1 4 SDA INTO P1 3 SCL TO P1 2 MOSI P2 2 MISO P2 3 P2 7 P2 6 P0 1 CIN2B KBII P0 2 CIN2A KBI2 P0 3 CINIB KBI3 P0 4 CIN1A KBI4 P0 5 CMPREF KBIS VDD P0 6 CMP1 KBI6 P0 7 T1 KBI7 P1 0 TXD P1 1 RXD P2 5 SPICLK P2 4 SS 2003 Dec 8 User s Manual Preliminary P89LPC930 931 Philips Semiconductors General Description User s Manual Preliminary P89LPC930 931 28 Pin PLCC Package P2 0 KBIO CMP2 P0 0 4 PI 7 7 P2 1 28 P2 7 27 P2 6 26 PO 1 CIN2B KBII 1 6 P0 2 CIN2A KBI2 RST P1 5 PO 3 CINIB KBI3 VSS PO A CINIA KBIA P0 S CMPREF KBI5 CLKOUT XTAL2 P3 0 VDD INTI P1 4 P0 6 CMP1 KBI6 SDA INTO P1 3 P0 7 T1 KBI7 eX E aa LEB x ag a g Ss 5 5 5 on v N Logic symbol Voo Vss KBIO y KBI2 KBI3 p KB4 y KBIb CLKOUT CMP2 CIN2B ___ CIN2A CIN1B CIN1A CMPREF PORTO CMP1 4 XTAL2 4 PORT3 XTALI o e o o n l o co 2003 Dec 8 10 Philips Semiconductors General Description
41. double buffering is enabled the Tx interrupt is generated when the double buffer is ready to receive new data The following occurs during a transmission assuming eight data bits The double buffer is empty initially The CPU writes to SBUF The SBUF data is loaded to the shift register and a Tx interrupt is generated immediately If there is more data go to 6 else continue on 5 If there is no more data then If DBISEL is 0 no more interrupts will occur If DBISEL is 1 and INTLO is 0 a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter which is also the last data If DBISEL is 1 and INTLO is 1 a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter which is also the last data 6 Ifthere is more data the CPU writes to SBUF again Then If INTLO is 0 the new data will be loaded and a Tx interrupt will occur at the beginning of the STOP bit of the data cur rently in the shifter If INTLO is 1 the new data will be loaded and a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter Go to 3 Note that if DBISEL is 1 and the CPU is writing to SBUF when the STOP bit of the last data is shifted out there can be an uncertainty of whether a Tx interrupt is generated already with the UART not knowing whether there is any more data following RON 2003 Dec 8 60 Philips Sem
42. each successive serial byte If the SPDAT register is written while SS is active low a write collision error results The operation is undefined if CPHA is 0 and SSIG is 1 When equals one SSIG may be set to 1 If SSIG 0 the ss pin may remain active low between successive transfers can be tied low at all times This format is sometimes preferred in systems having a single fixed master and a single slave driving the MISO data line ADDITIONAL CONSIDERATIONS FOR A MASTER In SPI transfers are always initiated by the master If the SPI is enabled SPEN 1 and selected as master writing to the SPI data register by the master starts the SPI clock generator and data transfer The data will start to appear on MOSI about one half SPI bit time to one SPI bit time after data is written to SPDAT 2003 Dec 8 85 Philips Semiconductors User s Manual Preliminary SERIAL PERIPHERAL INTERFACE SPI P89LPC930 931 Note that the master can select a slave by driving the ss pin of the corresponding device low Data written to the SPDAT register of the master is shifted out of the MOSI pin of the master to the MOSI pin of the slave at the same time the data in SPDAT register in slave side is shifted out on MISO pin to the MISO pin of the master After shifting one byte the SPI clock generator stops setting the transfer completion flag SPIF and an interrupt will be created if the SPI interrupt is enabled ESPI or IEN1
43. independently Refer to the section on I O port configuration and the DC Electrical Characteristics for details P1 2 P1 3 are open drain when used as outputs P1 5 is input only All pins have Schmitt triggered inputs Port 1 also provides various special functions as described below 18 1 0 Port 1 bit 0 TxD Transmitter output for the serial port 17 y o P1 1 Port 1 bit 1 RxD Receiver input for the serial port 12 VO P1 2 Port 1 bit 2 Open drain when used as an output TO Timer counter 0 external count input or overflow output Open drain when used as outputs I O SCL 2 serial clock input output 11 P1 3 Port 1 bit 3 Open drain when used as an output INTO External interrupt 0 input I O SDA C serial data input output 10 1 4 Port 1 bit 4 INT1 External interrupt 1 input 6 1 5 Port 1 bit 5 Input only RST External Reset input during power on or if selected via UCFG1 When functioning as a reset input a low on this pin resets the microcontroller causing I O ports and peripherals to take on their default states and the processor begins execution at address 0 Also used during a power on sequence to force In System Programming mode 5 I O P1 6 Port 1 bit 6 4 y o P1 7 Port 1 bit 7 2003 Dec 8 13 Philips Semiconductors General Description User s Manual Preliminary P89LPC930 931 PIN NO for
44. mode on any reset SCON 6 SM1 With SMO defines the serial port mode see table below SMO SM1 UART Mode UART 0 Baud Rate 00 0 shift register CCLK 16 default mode on any reset 01 1 8 bit UART Variable see Table 9 2 10 2 9 bit UART CCLK 32 or CCLK 16 11 3 9 bit UART Variable see Table 9 2 SCON 5 SM2 Enables the multiprocessor communication feature in Modes 2 and 3 In Mode 2 or 3 if SM2 is set to 1 then RI will not be activated if the received 9th data bit is 0 In Mode 0 SM2 should be 0 In Mode 1 SM2 must be 0 SCON 4 REN Enables serial reception Set by software to enable reception Clear by software to disable reception SCON 3 TB8 The 9th data bit that will be transmitted in Modes 2 and 3 Set or clear by software as desired SCON 2 RB8 The 9th data bit that was received in Modes 2 and 3 In Mode 1 SM2 must be 0 RB8 is the stop bit that was received In Mode 0 RB8 is undefined SCON 1 TI Transmit interrupt flag Set by hardware at the end of the 8th bit time in Mode 0 or at the the stop bit see description of INTLO bit in SSTAT register in the other modes Must be cleared by software SCON 0O RI Receive interrupt flag Set by hardware at the end of the 8th bit time in Mode or approximately halfway through the stop bit time in Mode 1 For Mode 2 or Mode 3 if SMODO it is set near the middle of the 9th data bit bit 8 If SMODO 1 itis set near the middle of the stop bit see SM2 SCON 5 f
45. of 25 and I2SCLL Figure 4 Control register 2003 Dec 8 67 Philips Semiconductors User s Manual Preliminary 2 INTERFACE P89LPC930 931 Status register This is a read only register It contains the status code of interface The least three bits are always 0 There are 26 possible status codes When the code is F8H there is no relevant information available and SI bit is not set All other 25 status codes correspond to defined I C states When any of these states entered the SI bit will be set Refer to Table 2 to Table 5 for details I2STAT Address D9h Not bit addressable 1 S S 4 3 2 1 2 Reset source s Any reset STA4 STA 3 STA2 STA 1 0 0 0 0 Reset Value 11111000B BIT SYMBOL FUNCTION I2STAT7 3 STA 4 0 12C the status code I2STAT2 0 These three bits are not used and always set to 0 Figure 5 Status register SCL Duty Cycle registers I2SCLH and I2SCLL When the internal SCL generator is selected for the interface by setting CRSEL 0 in the I2CON register the user must set values for registers I2SCLL and I2SCLH to select the data rate I2SCLH defines the number of PCLK cycles for SCL high I2SCLL defines the number of PCLK cycles for SCL low The frequency is determined by the following formula Bit Frequency fpc 2 IZSCLH I2SCLL Where fpc is the frequency of PCLK The values for I2SCLL and I2S
46. on reset both POF and this bit will be set while the other flag bits are cleared RSTSRC 4 POF Power on Detect Flag When Power on Detect is activated the POF flag is set to indic ate an initial power up condition The POF flag will remain set until cleared by software by writing a 0 to the bit Note On a Power on reset both BOF and this bit will be set while the other flag bits are cleared RSTSRC 3 R_BK Break detect reset If a break detect occurs and EBRR AUXR1 6 is set to 1 a system reset will occur This bitis setto indicate that the system reset is caused by a break detect Cleared by software by writing a 0 to the bit or on a Power on reset RSTSRC 2 R WD Watchdog Timer reset flag Cleared by software by writing a 0 to the bit or a Power on reset NOTE UCFG1 7 must be 1 RSTSRC 1 R SF Software reset Flag Cleared by software by writing a 0 to the bit or a Power on reset RSTSRC 0 R EX External reset Flag When this bitis 1 itindicates external pin reset Cleared by software by writing a 0 to the bit or a Power on reset If RST is still asserted after the Power on reset is over R EX will be set Figure 6 2 Reset Sources register Reset vector Following reset the P89LPC930 931 will fetch instructions from either address 0000h or the Boot address The Boot address is formed by using the Boot Vector as the high byte of the address and the low byte
47. one which may be read in a register and or routed to a pin when the positive input one of two selectable pins is greater than the negative input selectable from a pin or an internal reference voltage Otherwise the output is a zero Each comparator may be configured to cause an interrupt when the output value changes Comparator configuration Each comparator has a control register CMP1 for comparator 1 and CMP2 for comparator 2 The control registers are identical and are shown in Figure 12 1 The overall connections to both comparators are shown in Figure 12 2 There are eight possible configurations for each comparator as determined by the control bits in the corresponding CMPn register CPn CNn and OEn These configurations are shown in Figure 12 3 When each comparator is first enabled the comparator output and interrupt flag are not guaranteed to be stable for 10 microseconds The corresponding comparator interrupt should not be enabled during that time and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service CMPn Address ACh CMP1 ADh CMP2 7 6 5 4 3 2 1 0 Not bit addressable CEn CPn CNn OEn COn CMFn Reset Source s Any reset Reset Value xx000000B BIT SYMBOL FUNCTION CMPn 7 6 Reserved for future use Should not be set to 1 by user programs CMPn 5 CEn Comparator enable When set the corresponding co
48. return prog fail Figure 16 3 C language routine to erase program all or part of a page In Circuit Programming ICP In Circuit Programming is a method intended to allow commercial programmers to program and erase these devices without removing the microcontroller from the system The In Circuit Programming facility consists of a series of internal hardware resources to facilitate remote programming of the P89LPC930 931 through a two wire serial interface Philips has made in cir cuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area The ICP function uses five pins Vdd Vss P0 5 P0 4 and RST Only a small connector needs to be available to inter face your application to an external programmer in order to use this feature ISP and IAP capabilities of the P89LPC930 931 An In Application Programming IAP interface is provided to allow the end user s application to erase and reprogram the user code memory In addition erasing and reprogramming of user programmable bytes including UCFG1 the Boot Status Bit and the Boot Vector is supported As shipped from the factory the upper 512 bytes of user code space contains a serial In System 2003 Dec 8 107 Philips Semiconductors User s Manual Preliminary FLASH MEMORY P89LPC930 931 Programming ISP loader allowing for the device to be programmed in circuit through the serial port This ISP boot loader w
49. set again and the possible status codes are 18h 20h or 38h for the master mode or 68h 78h or OBOh if the slave mode was enabled setting AA 7 Logic 1 The appropriate action to be taken for each of these status codes is shown in Table 2 2003 Dec 8 69 User s Manual Preliminary Philips Semiconductors 2 INTERFACE P89LPC930 931 5 Slave Address R W A DATA A DATA P e Q is Data Transferred 1 Read n Bytes Acknowledge A Acknowledge SDA low From Master to Slave Not Acknowledge SDA high From Slave to Master S START condition P STOP Condition Figure 7 Format in the Master Transmitter Mode Master Receiver Mode In the Master Receiver Mode data is received from a slave transmitter The transfer started in the same manner as in the Master Transmitter Mode When the START condition has been transmitted the interrupt service routine must load the slave address and the data direction bit to I C Data Register I2DAT The SI bit must be cleared before the data transfer can continue When the slave address and data direction bit have been transmitted and an acknowledge bit has been received the SI bit is set and the Status Register will show the status code For master mode the possible status codes are 40H 48H or 38H For slave mode the possible status codes are 68H 78H or BOH Refer to Table 3 for details
50. written by user software but has no effect on operation PCON 2 GFO General Purpose Flag 0 May be read or written by user software but has no effect on operation PCON 1 0 PMOD1 PMODO Power Reduction Mode see section Power reduction modes Figure 5 1 Power Control register PCON 2003 Dec 8 38 Philips Semiconductors User s Manual Preliminary POWER MONITORING FUNCTIONS Address B5H 7 6 5 2 1 0 Not bit addressable RTCPD VCPD I2PD E SPD i Reset Source s Any reset Reset Value 00000000B BIT SYMBOL FUNCTION PCONA 7 RTCPD Real time Clock Power down When 1 the internal clock to the Real time Clock is disabled PCONA 6 Not used Reserved for future use PCONA 5 VCPD Analog Voltage Comparators Power down When 1 the voltage comparators are powered down User must disable the voltage comparators prior to setting this bit PCONA 4 Not used Reserved for future use PCONA 3 I2PD 12C Power down When 1 the internal clock to the I C is disabled Note that in either Power down mode or Total Power down mode the I C clock will be disabled regardless of this bit PCONA 2 Not used Reserved for future use PCONA 1 SPD Serial Port UART Power down When 1 the internal clock to the UART is disabled Note that in either Power down mode or Total Power down mode the UART clock will be disabled rega
51. 0 ock Cycle PICLK CPOL 0 PICLK CPOL 1 MOSI input MISO output SS if SSIG bit 0 Not defined Figure 11 9 SPI slave transfer format with CPHA 1 2003 Dec 8 87 Philips Semiconductors User s Manual Preliminary SERIAL PERIPHERAL INTERFACE SPI P89LPC930 931 ock Cycle PICLK CPOL 0 PICLK CPOL 1 MOSI output DORD 0 X DORD 1 LSB 1 MISO input DORDU y n Pi DORD 1 N SS if SSIG bit 0 Figure 11 10 SPI master transfer format with CPHA 0 Clock Cycle SPICLK CPOL 0 SPICLK CPOL 1 MOSI output MISO input SS if SSIG bit 0 Figure 11 11 SPI master transfer format with CPHA 1 SPI CLOCK PRESCALER SELECT The SPI clock prescalar selection uses the SPR1 SPRO bits in the SPCTL register see Figure 11 2 2003 Dec 8 88 Philips Semiconductors User s Manual Preliminary ANALOG COMPARATORS P89LPC930 931 12 ANALOG COMPARATORS Two analog comparators are provided on the P89LPC930 931 Input and output options allow use of the comparators in a number of different configurations Comparator operation is such that the output is a logical
52. 1 1 1 CINnB CINnB COn COn 7 cMPn Vref 1 23V Vref 1 23V Figure 12 3 Comparator configurations Comparator configuration example The code shown below is an example of initializing one comparator Comparator 1 is configured to use the CIN 1A and CMPREF inputs outputs the comparator result to the pin and generates an interrupt when the comparator output changes CMPINIT MOV PTOAD 030h Disable digital INPUTS on pins that are used for analog functions CIN1A CMPREF ANL POM2 0CFh Disable digital OUTPUTS on pins that are used ORL POM1 030h for analog functions CIN1A CMPREF MOV CMP1 024h Turn on comparator 1 and set up for Positive input on CIN1A Negative input from CMPREF pin Output to CMP1 pin enabled CALL delay10us The comparator has to start up for at least 10 microseconds before use ANL CMP1 0FEh Clear comparator 1 interrupt flag SETB EC Enable the comparator interrupt The priority is left at the current value SETB EA Enable the interrupt system if needed 2003 Dec 8 91 User s Manual Preliminary P89LPC930 931 ANALOG COMPARATORS Return to caller RET The interrupt routine used for the comparator must clear the interrupt flag CMP1 in this case before returning 92 2003 Dec 8 Philips Semiconductors User s Manual Preliminary P89LPC930 931 KEYPAD INTERRUPT 13 KEYPAD INTERRUPT KBI The Keypad Interrupt fun
53. 2 bytes DPH Data Pointer High 83H 00H 00000000 DPL Data Pointer Low 82H 00H 00000000 FMADRH Program Flash Address High E7H 00H 00000000 FMADRL Program Flash Address Low E6H 00H 00000000 Program Flash Control Read BUSY HVA HVE SV Ol 70H 01110000 FMCON E4H FMCMD FMCMD FMCMD FMCMD FMCMD FMCMD FMCMD Program Flash Control Write 7 6 5 4 3 2 1 0 FMDATA Program Flash Data E5H 00H 00000000 I2ADR IC Slave Address Register DBH I2ADR 6 IADR 5 I2ADR 4 I2ADR 3 IZADR 2 I2ADR 1 I2ADR 0 GC 00H 00000000 DF DE DD DC DB DA D9 D8 I2CON 2 Control Register D8H I2EN STA STO SI AA CRSEL 00H x00000x0 I2DAT 2 Data Register DAH I28CLH amp Serial Clock Generator SCL Duty DDH 00H 00000000 Cycle Register High 2003 Dec 8 15 Philips Semiconductors User s Manual Preliminary General Description P89LPC930 931 SFR Bit Functions and Addresses Reset Value Name Description Address MSB LSB Hex Binary I2SCLL Serial Clock Generator SCL Duty DCH 00H 00000000 Cycle Register Low I2STAT 12 Status Register D9H STA4 STA3 STA2 STA 1 STA O 0 0 0 F8H 11111000 AF AE AD AC AB AA AQ A8 IENO Interrupt Enable 0 A8H EA EWDRT j ES ESR
54. 2DAT action or 1 0 0 x Repeated START will be transmitted SLA R has been E STOP condition will be transmitted 48h transmitted NOT no I2DAT action or 0 1 0 x STO flag will be reset ACK has been received STOP condition followed by a no I2DAT action or 1 1 0 START condition will be transmitted STO flag will be reset Read data byte Data byte will be received NOT ACK Data byte has been g O bit will be returned 50h received ACK has ene wile SONDAGE been returned read data byte 0 0 0 1 DN will be returned Read data byte or 1 0 0 x Repeated START will be transmitted Data byte has been read data byte or 0 1 0 x transmitted 58h received NACK has 9 been returned STOP condition followed by a read data byte 1 1 0 x START condition will be transmitted STO flag will be reset Table 4 Slave Receiver Mode beenreceived ACK has been returned Status Application software response code Status of the Next action taken by 2 I2STAT I C bus hardware to from I2DAT to I2CON hardware STA STO SI AA no I2DAT action or x 0 0 0 Data byte will be received and NOT ACK will Own SLA W has be returned 60H been received ACK has been received no I2DAT action x 0 0 Data byte will be received and ACK will be returned Arbitration lost in No I2DAT action or Data byte will be received and NOT ACK will SLA R Was x 0 0 be returned 68H master Own SLA W has been received Data byte wi
55. 3 1 The two shift registers in the master CPU and slave CPU can be considered as one distributed 16 bit circular shift register When data is shifted from the master to the slave data is also shifted in the opposite direction simultaneously This means that during one shift cycle data in the master and the slave are interchanged MODE CHANGE ON SS If SPEN 1 SSIG 0 and MSTR 1 the SPI is enabled in master mode The SS pin can be configured as an input P2M2 4 P2M1 4 00 or quasi bidirectional P2M2 4 P2M1 4 01 In this case another master can drive this pin low to select this device as an SPI slave and start sending data to it To avoid bus contention the SPI becomes a slave As a result of the SPI becoming a slave the MOSI and SPICLK pins are forced to be an input and MISO becomes an output The SPIF flag in SPSTAT is set and if the SPI interrupt is enabled an SPI interrupt will occur User software should always check the MSTR bit If this bit is cleared by a slave select and the user wants to continue to use the SPI as a master the user must set the MSTR bit again otherwise it will stay in slave mode WRITE COLLISION The SPI is single buffered in the transmit direction and double buffered in the receive direction New data for transmission can not be written to the shift register until the previous transaction is complete The WCOL SPSTAT 6 bit is set to indicate data collision when the data register is written during t
56. CLH do not have to be the same the user can give different duty cycle s for SCL by setting these two registers However the value of the register must ensure that the data rate is in the data rate range of 0 400 kHz Thus the values of I2SCLL and I2SCLH have some restrictions and values for both registers greater than PCLKs are recommended Table 1 I C clock rates selection Bit data rate Kbit sec at fosc I2SCLL CRSEL 7 373 MHz 3 6865 MHz 1 8433 MHz 12 MHz 6 MHz I2SCLH 6 0 307 154 7 0 i 263 132 8 0 230 115 375 9 0 205 102 333 10 0 369 184 92 300 15 0 246 123 61 400 200 25 0 147 74 37 240 120 30 0 123 61 31 200 100 50 0 74 37 18 120 60 60 0 61 31 15 100 50 2003 Dec 8 68 Philips Semiconductors User s Manual Preliminary 2 INTERFACE P89LPC930 931 Table 1 I C clock rates selection Bit data rate Kbit sec at fosc I2SCLL CRSEL 7 373 MHz 3 6865 MHz 1 8433 MHz 12 MHz 6 MHz I2SCLH 100 0 37 18 9 60 30 150 0 25 12 6 40 20 200 0 18 9 5 30 15 1 3 6 922 Kbps 1 8 461 Kbps 0 9 230 Kbps 5 86 1500 Kbps 2 93 750 Kbps timer1 in mode2 timer1 in mode 2 timer1 in mode 2 timer1 in mode 2 timer1 in mode 2 operation mode Master Transmitter Mode In this mode data is transmitted from master to slave Before the Master Transmitter Mode can be entered I2CON must be initia
57. DBISEL is 0 no more interrupt will occur If DBISEL is 1 and INTLO is 0 a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter which is also the last data If DBISEL is 1 and INTLO is 1 a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter which is also the last data 7 fthere is more data the CPU writes to TB8 again oohom2 2003 Dec 8 61 Philips Semiconductors User s Manual Preliminary UART P89LPC930 931 8 The CPU writes to SBUF again Then If INTLO is 0 the new data will be loaded and a Tx interrupt will occur at the beginning of the STOP bit of the data cur rently in the shifter If INTLO is 1 the new data will be loaded and a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter Go to 4 Note that if DBISEL is 1 and the CPU is writing to SBUF when the STOP bit of the last data is shifted out there can be an uncertainty of whether a Tx interrupt is generated already with the UART not knowing whether there is any more data following Multiprocessor communications UART modes 2 and 3 have a special provision for multiprocessor communications In these modes 9 data bits are received or transmitted When data is received the 9th bit is stored in RB8 The UART can be programmed such that when the stop bit is received the serial port interrupt wil
58. Dec 8 44 Philips Semiconductors User s Manual Preliminary TIMERS 0 AND 1 P89LPC930 931 Mode 2 Mode 2 configures the Timer register as an 8 bit Counter TLn with automatic reload as shown in Figure 7 6 Overflow from TLn not only sets TFn but also reloads TLn with the contents of THn which must be preset by software The reload leaves THn unchanged Mode 2 operation is the same for Timer 0 and Timer 1 Mode 3 When Timer 1 is in Mode 3 it is stopped The effect is the same as setting TR1 0 Timer 0 in Mode 3 establishes TLO and THO as two separate 8 bit counters The logic for Mode 3 on Timer 0 is shown in Figure 7 7 TLO uses the Timer 0 control bits TOC T TOGATE TRO INTO and TFO THO is locked into a timer function counting machine cycles and takes over the use of TR1 and TF1 from Timer 1 Thus THO now controls the Timer 1 interrupt Mode 3 is provided for applications that require an extra 8 bit timer With Timer 0 in Mode 3 an P89LPC930 931 device can look like it has three Timer Counters Note When Timer 0 is in Mode 3 Timer 1 can be turned on and off by switching it into and out of its own Mode 3 It can still be used by the serial port as a baud rate generator or in any application not requiring an interrupt Mode 6 In this mode the corresponding timer can be changed to a PWM with a full period of 256 timer clocks see Figure 7 8 Its structure is similar to mode 2 except that TFn n 0 and 1
59. EST to CPU SI EI2C SPIF ESPI Figure 3 1 Interrupt sources interrupt enables and power down wake up sources 2003 Dec 8 27 Philips Semiconductors User s Manual Preliminary INTERRUPTS P89LPC930 931 2003 Dec 8 28 Philips Semiconductors User s Manual Preliminary PORTS P89LPC930 931 4 PORTS The P89LPC930 931 has 1 0 ports Port 0 Port 1 Port 2 and Port 3 Ports 0 1 and 2 are 8 bit ports and Port is a 2 bit port The exact number of I O pins available depends upon the clock and reset options chosen see Table 4 1 Clock source Reset option Number of I O pins On chip oscillator or watchdog No external reset except during power up 26 oscillator External RST pin supported 25 No external reset except during power up 25 External clock input External RST pin supported 24 Low medium high speed oscillator No external reset except during power up 24 external crystal or resonator External RST pin supported 23 Table 4 1 Number of I O pins available Port configurations All but three I O port pins on the P89LPC930 931 may be configured by software to one of four types on a pin by pin basis as shown in Table 4 2 These are quasi bidirectional standard 80C51 port outputs push pull open drain and input only Two configuration registers for each port select the output type for each p
60. ET1 EX1 ETO EXO 00H 00000000 EF EE ED EC EB EA E9 E8 IEN1 Interrupt Enable 1 E8H EST ESPI EC EKBI EI2C 00x00000 BF BE BD BC BB BA B9 B8 IPO Interrupt Priority O B8H PWDRT PBO PS PSR PT1 PX1 PTO PXO x0000000 IPOH Interrupt Priority O High B7H PWDRT PBOH E RE PT1H PX1H PTOH PXOH x0000000 FF FE FD FC FB FA F9 F8 IP 1 Interrupt Priority 1 F8H PST PSPI PC PKBI PI2C 00 00000 IP1H Interrupt Priority 1 High F7H PSTH PSPIH PCH PKBIH 2 00 00000 PATN 1 KBCON Keypad Control Register 94H SEL KBIF 00H 00 KBMASK Keypad Interrupt Mask Register 86H 00H 00000000 KBPATN Keypad Pattern Register 93H FFH 11111111 87 86 85 84 83 82 81 80 CMP1 CIN1A CIN1B CIN2A CIN2B CMP2 FS Porto 80H TVKB7 5 KB2 KB1 Note 97 96 95 94 93 92 91 90 T INT INTO P1 Port 1 90H RST INT1 SDA TO SCL RxD TxD Note 1 AT A6 A5 A4 A3 A2 A1 AO P2 Port 2 AOH SPICLK ss MISO MOSI Note 1 B7 B6 B5 B4 B3 B2 B1 BO P3 Port 3 BOH XTAL1 XTAL2 Note 1 POM1 Port 0 Output Mode 1 84H POM1 7 POM1 6 POM1 5 POM1 4 POM1 3 POM1 2 POM1 1 POM1 0 FFH 11111111 POM2 Port 0 Output Mode 2 85H 2 7 POM2 6 POM2 5 POM2 4 POM2 3 POM2 2 POM2 1 POM2 0 OOH 00000000 P1M1 Port 1 Output Mode 1 91H P1M1 7 P1M1 6 P1M1 4 P1M1 3 P1M1 2 P1M1 1
61. Figure 8 1 The Real time Clock is a 23 bit down counter The clock source for this counter can be either the CPU clock CCLK or the XTAL1 2 oscillator provided that the XTAL1 2 oscillator is not being used as the CPU clock If the XTAL1 2 oscillator is used as the CPU clock then the RTC will use CCLK as its clock source regardless of the state of the RTCS1 0 in the RTCCON register There are three SFRs used for the RTC RTCCON Real time Clock control RTCH Real time Clock counter reload high bits 22 15 RTCL Real time Clock counter reload low bits 14 7 RTC Reset 7 bit prescaler MM 23 bit down counter CCLK Int Osc s Wake up from Power down n s T Interrupt RTC underflow flag RTC Enable RTC clk select if enabled shared w WDT Figure 8 1 Real time Clock System Timer block diagram The Real time Clock System Timer can be enabled by setting the RTCEN RTCCON 0 bit The Real time Clock is a 23 bit down counter initialized to all 05 when RTCEN 0 that is comprised of a 7 bit prescaler and a 16 bit loadable down counter When RTCEN is written with 1 the counter is first loaded with RTCH RTCL 1111111 and will count down When it reaches all 0 s the counter will be reloaded again with RTCH RTCL 1111111 and a flag RTCF RTCCON 7 will be set Any write to RTCH and RTCL in between the Real time Clock reloading will not cause reloading of the counter When the c
62. ILIPS For sales offices addresses send e mail to sales addresses www semiconductors philips com
63. INTEGRATED CIRCUITS USER MANUAL P89LPC930 931 8 bit microcontroller with two clock core 4 KB 8 KB 3 V low power Flash with 256 Byte RAM 2003 Dec 8 Philips PHILIPS Semiconductors DH LI p Philips Semiconductors User Manual Subject to Change Table of Contents P89LPC930 931 Table of Contents 1 General Descripti N e ET 9 MERIT EET 9 Pin configurations riw 9 28 PiN TSSOP Package me m 9 Kole Jeano EER PEE E AEE A EA 10 Pin Descriptions eade 12 Special Function Registers c c ccccseeeeeneeeeeeeeeeeseeeensesseccecceeeeaseceeneeseeeeeenensees 15 Special Function Registers 15 Memory organization ccce tue sce ed incon ete m b patentes 19 Data RAM knee ena nnne tenere 20 Zi simi reeoos D sa EIL nmi A EM LAE 21 Enhanced CPUN ico dirae nh Er dE EHE eae epee sac ms pede 21 ale i E ee Ea NC Pee eee eee ee 21 Clock CSUN ares Ore ter E ede ae tte ee EE euo id 21 Oscillator clock OSCOLK 5 niei ice ele etek ee et 21 Low speed oscillator option nt rnrnneteeeereenn 21 Medium speed oscillator option
64. N is forced to 1and cannot be cleared by software Figure 14 3 shows the watchdog timer in watchdog mode It consists of a programmable 13 bit prescaler and an 8 bit down counter The down counter is clocked decremented by a tap taken from the prescaler The clock source for the prescaler is either PCLK or the watchdog oscillator selected by the WDCLK bit in the WDCON register Note that switching of the clock sources will not take effect immediately see section Watchdog Clock Source on page 98 The watchdog asserts the watchdog reset when the watchdog count underflows and the watchdog reset is enabled When the watchdog reset is enabled writing to WDL or WDCON must be followed by a feed sequence for the new values to take effect If a watchdog reset occurs the internal reset is active for at least one watchdog clock cycle PCLK or the watchdog oscillator clock If CCLK is still running code execution will begin immediately after the reset cycle If the processor was in Power down mode the watchdog reset will start the oscillator and code execution will resume after the oscillator is stable 2003 Dec 8 95 Philips Semiconductors User s Manual Preliminary WATCHDOG TIMER P89LPC930 931 Watchdog Oscillator 5 322 gt 2 2 2 2 2 2 2 o 32 64 128 256 512 1024 2048 4096 WDCLK after watchdog fee
65. O RTCCON 6 IRTGCON 5 UCFG1 2 UCFG1 1 UCFG1 0 RTC clock source CPU clock source x x 0 0 0 CCLK High frequency crystal x x 0 0 1 CCLK Medium frequency crystal x x 0 1 0 CCLK Low frequency crystal 0 0 High frequency crystal 0 1 Medium frequency crystal 0 1 1 Internal RC oscillator 1 0 Low frequency crystal 1 1 CCLK 0 0 High frequency crystal 0 1 Medium frequency crystal 1 0 0 Watchdog oscillator 1 0 Low frequency crystal 1 1 CCLK X X 1 0 1 undefined undefined X X 1 1 0 undefined undefined x x 1 1 1 CCLK External clock input 2003 Dec 8 50 Philips Semiconductors User s Manual Preliminary REAL TIME CLOCK SYSTEM TIMER P89LPC930 931 RTCCON Address D1h 7 6 5 4 3 2 1 0 Not bit addressable RTCF RTCS1 RTCSO ERTC RTCEN Reset Source s Power up only Reset Value 011xxx00B BIT SYMBOL FUNCTION RTCCON 7 RTCF Real time Clock Flag This bit is set to 1 when the 23 bit Real time Clock reaches a count of 0 It can be cleared in software RTCCON 6 5 RTCS1 0 Real time Clock source select see Table RTCCON 4 2 Reserved for future use Should not be set to 1 by user programs RTCCON 1 ERTC Real time Clock interrupt enable The Real time Clock shares the same interrupt as the watchdog timer Note that if the user configuration bit WDTE UCFG1 7 is 0 the watchdog timer can be enabled to generate an interrupt Users can read th
66. OP condition followed by a START no I2DAT action 1 1 0 condition will be transmitted STO flag will be reset Data byte will be transmitted eee ee 48 294 9 ACK bit will be received Data byte I2DAT no I2DAT action 1 0 0 Repeated START will be transmitted has been STOP condition will be transmitted STO flag 28h transmitted ACK no I2DAT action 0 1 0 has been received STOP condition followed by a START no I2DAT action 1 1 0 condition will be transmitted STO flag will be reset 2003 Dec 8 74 Philips Semiconductors User s Manual Preliminary I C INTERFACE P89LPC930 931 Table 2 Master Transmitter Mode Continued Status Application software response code Status of the Next action taken by 2 I2STAT I C bus hardware to from I2DAT to I2CON hardware STA STO SI AA Data byte will be transmitted Data byte in I2DAT 989 detabyteor 0 0 0 X ack pit will be received has been no 2 action or 1 0 0 x Repeated START will be transmitted transmitted NOT T 30h ACK hasbeen no I2DAT action or 0 4 0 z STOP condition will be transmitted STO flag received will be reset STOP condition followed by a START no I2DAT action 1 1 0 X condition will be transmitted STO flag will be reset FEN No I2DAT action 0 0 0 I C bus will be released not addressed Arbitration lost in or slave will be entered 38H SLA R W or data bytes No I2DAT
67. OV WFEED1 0A5h do watchdog feed part 1 MOV WFEED2 05Ah do watchdog feed part 2 SETB EA enable interrupt This sequence assumes that the P89L PC901 902 903 interrupt system is enabled and there is a possibility of an interrupt request occuring during the feed sequence If an interrupt was allowed to be serviced and the service routine contained any SFR writes it would trigger a watchdog reset If it is known that no interrupt could occur during the feed sequence the instructions to disable and re enable interrupts may be removed In watchdog mode WDTE 1 writing the WDCON register must be IMMEDIATELY followed by a feed sequence to load the WDL to the 8 bit down counter and the WDCON to the shadow register If writing to the WDCON register is not immediately followed by the feed sequence a watchdog reset will occur For example setting WDRUN 1 MOV ACC WDCON get WDCON SETB ACC 2 set WD_RUN 1 MOV WDL ZOFFh New count to be loaded to 8 bit down counter CLR EA disable interrupt MOV WDCON ACC Write back to WDCON after the watchdog is enabled a feed must occur immediately 2003 Dec 8 96 Philips Semiconductors User s Manual Preliminary WATCHDOG TIMER P89LPC930 931 MOV WFEED1 0A5h do watchdog feed part 1 MOV WFEED2 05Ah do watchdog feed part 2 SETB EA enable interrupt In timer mode WDTE 0 WDCON is loaded to the control register every CCLK cycle no feed sequence is required to load the
68. PERIPHERAL INTERFACE SPI The P89LPC930 931 provides another high speed serial communication interface the SPI interface SPI is a full duplex high speed synchronous communication bus with two operation modes Master mode and Slave mode Up to 3 Mbit s can be supported in either Master or Slave mode It has a Transfer Completion Flag and Write Collision Flag Protection CPU clock 8 Bit Shift Register Divider by 4 16 64 128 Read Data Buffer Select Pin Control Logic SPI clock Master SPI Control SPI Internal interrupt Data request Bus SPI Status Register Figure 11 1 SPI block diagram The SPI interface has four pins SPICLK MOSI MISO and SS SPICLK MOSI and MISO are typically tied together between two or more SPI devices Data flows from master to slave on the MOSI Master Out Slave In pin and flows from slave to master on the MISO Master In Slave Out pin The SPICLK signal is output in the master mode and is input in the slave mode If the SPI system is disabled i e SPEN SPCTL 6 0 reset value these pins are configured for port functions SSisthe optional slave select pin In a typical configuration an SPI master asserts one of its port pins to select one SPI device as the current slave An SPI slave device uses its SS pin to determine whether it is selected The SS is ignored if any of the following conditions are true If the SPI system is disabled i e SPEN SPCTL 6 0 reset
69. REN 1 Reception is initiated in the other modes by the incoming start bit if REN 1 2003 Dec 8 53 Philips Semiconductors User s Manual Preliminary UART P89LPC930 931 SFR space The UART SFRs are at the following locations Table 9 1 SFR Locations for UARTs Register Description SFR Location PCON Power Control 87H SCON Serial Port UART Control 98H SBUF Serial Port UART Data Buffer 99H SADDR Serial Port UART Address A9H SADEN Serial Port UART Address Enable B9H SSTAT Serial Port UART Status BAH BRGR1 Baud Rate Generator Rate High Byte BFH BRGRO Baud Rate Generator Rate Low Byte BEH BRGCON Baud Rate Generator Control BDH Baud Rate Generator and selection The P89LPC930 931 enhanced UART has an independent Baud Rate Generator The baud rate is determined by a value programmed into the BRGR1 and BRGRO SFRs The UART can use either Timer 1 or the baud rate generator output as determined by BRGCON 2 1 see Figure 9 2 Note that Timer T1 is further divided by 2 if the SMOD1 bit PCON 7 is set The independent Baud Rate Generator uses CCLK Updating the BRGR1 and BRGRO SFRs The baud rate SFRs BRGR1 and BRGRO must only be loaded when the Baud Rate Generator is disabled the BRGEN bit in the BRGCON register is 0 This avoids the loading of an interim value to the baud rate generator CAUTION If either BRGRO or BRGR1 is written when BRGEN 1 the re
70. TN 93 PCON 38 PCONA 39 PTOAD 31 RSTSRC 42 RTCCON 51 SCON 56 SPCTL 82 SPDAT 83 SPSTAT 83 SSTAT 57 TAMOD 44 TCON 46 2003 Dec 8 132 Philips Semiconductors User Manual Subject to Change INDEX P89LPC930 931 TMOD 43 TRIM 21 22 105 UCFG1 119 WDCON 97 SFRs undefined locations use of 15 Special Function Registers SFR table 15 SPI additional considerations for the master 85 additional considerations for the slave 85 clock prescalar select 88 configurations 83 configuring 85 data mode 86 mode change on SS 86 write collision 86 Timer counters mode 0 44 mode 1 44 mode 2 8 bit auto reload 45 mode 3 seperates TLO amp THO 45 mode 6 8 bit PWM 45 toggle output 48 TRIM SFR power on reset value 18 U UART 53 automatic address recognition 62 baud rate generator 54 BRGR1 and BRGRO updating 54 double buffering in 9 bit mode 61 double buffering in different modes 60 framing error 55 59 mode 0 57 mode 0 shift register 53 mode 1 58 mode 1 8 bit variable baud rate 53 mode 2 59 2003 Dec 8 133 Philips Semiconductors User Manual Subject to Change INDEX P89LPC930 931 mode 2 9 bit fixed baud rate 53 mode 3 59 mode 3 9 bit variable baud rate 53 multiprocessor communications 62 SFR locations 54 status register 57 transmit interrupts with double buffering enabled modes 1 2 and 3 60 User Configuration Byte UCFG1 119 120 W Watchdog timer 95 feed sequen
71. TO0 Pin P1 2 Gate ENTO open drain INTO Pin AUXR1 4 THO Overfl Osc 2 8 bits ee gt gt Interrupt Control Toggle o T1 Pin P0 7 ENT1 AUXR1 5 TR1 2003 Dec 8 Figure 7 7 Timer Counter 0 Mode 3 two 8 bit counters 47 Philips Semiconductors User s Manual Preliminary TIMERS 0 AND 1 P89LPC930 931 PCLK a TRn Gate INTn Pin Figure 7 8 Timer Counter 0 or 1 in Mode 6 PWM auto reload Timer overflow toggle output Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer overflow occurs The same device pins that are used for the TO and T1 count inputs and PWM outputs are also used for the timer toggle outputs This function is enabled by control bits ENTO and ENT in the AUXR1 register and apply to Timer 0 and Timer 1 respectively The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on In order for this mode to function the C T bit must be cleared selecting PCLK as the clock source for the timer 2003 Dec 8 48 Philips Semiconductors User s Manual Preliminary REAL TIME CLOCK SYSTEM TIMER P89LPC930 931 8 REAL TIME CLOCK SYSTEM TIMER The P89LPC930 931 has a simple Real time Clock System Timer that allows a user to continue running an accurate timer while the rest of the device is powered down The Real time Clock can be an interrupt or a wake up source see
72. TRIM register 5 The only reset source that affects these SFRs is power on reset 2003 Dec 8 18 Philips Semiconductors User s Manual Preliminary General Description P89LPC930 931 Memory organization The P89LPC930 931 memory map is shown in Figure 1 1 FFOOh Read protected FFEFR IAP calls only De 1FFFh p 2 l FF1Fh 1E00h 5 e 1c00h FFOOh 1BFFh 1FFFh 1800h 17FFh 1400h Data Memo 1 3 Flexible choices DATA IDATA as supplied UART eae Philips libraries user defined d ERE Note ISP code is located at the end of Sector 3 on the LPC930 at the end of Sector 7 on the on the LPC931 0800h 07FFh 0400h 03FFh 0000n Flash Code Memory Space Figure 1 1 P89LPC930 931 memory map The various P89LPC930 931 memory spaces are as follows DATA 128 bytes of internal data memory space 00h 7Fh accessed via direct or indirect addressing using instructions other than MOVX and MOVC All or part of the Stack may be in this area IDATA Indirect Data 256 bytes of internal data memory space 00h FFh accessed via indirect addressing using instructions other than MOVX and MOVC All or part of the Stack may be in this area This area includes the DATA area and the 128 bytes immediately above it SFR Special Function Registers Selected CPU registers and peripheral control and status registers accessible only via direct addressing CODE 64 KB of Code memory space
73. User must NOT attempt to access any SFR locations not defined 2 Accesses to any defined SFR locations must be strictly for the functions for the SFRs 3 SFR bits labeled 0 1 can ONLY be written and read as follows Unless otherwise specified MUST be written with 0 but can return any value when read even if it was written with 0 It is a reserved bit and may be used in future derivatives 0 MUST be written with O and will return a 0 when read 1 MUST be written with 1 and will return a 1 when read SPECIAL FUNCTION REGISTERS TABLE SFR Bit Functions and Addresses Reset Value Name Description Address MSB LSB Hex Binary E7 E6 E5 E4 E3 E2 E1 EO ACC Accumulator 00H 00000000 AUXR1 Auxiliary Function Register A2H CLKLP EBRR ENT1 ENTO SRST 0 DPS 000000 0 F7 F6 F5 F4 F3 F2 F1 FO B B Register FOH 00H 00000000 BRGRO Baud Rate Generator Rate Low BEH 00H 00000000 BRGR1 Baud Rate Generator Rate High BFH 00H 00000000 BRGCON Baud Rate Generator Control BDH SBRGS BRGEN 00H 00 CMP1 Comparator 1 Control Register ACH CE1 CP1 CN1 OE1 CO1 CMF1 00H xx000000 CMP2 Comparator 2 Control Register ADH CE2 CP2 CN2 OE2 2 2 00H xx000000 DIVM CPU Clock Divide by M Control 95H 00H 00000000 DPTR Data Pointer
74. a brownout is detected regardless of whether a reset or an interrupt is enabled BOF will stay set until it is cleared in software by writing 0 to the bit Note that if BOE is unprogrammed BOF is meaningless If BOE is programmed and a initial power on occurs BOF will be set in addition to the power on flag POF RSTSRC 4 For correct activation of Brownout Detect certain Vpp rise and fall times must be observed Please see the datasheet for specifications 2003 Dec 8 35 Philips Semiconductors User s Manual Preliminary POWER MONITORING FUNCTIONS OISU BOE PMOD1 0 BOPD BOI EBO EA UCFG1 5 PCON 1 0 PCON 5 PCON 4 IENO 5 IENO 7 Description 0 erased XX x X X X 11 Brownout disabled Vpp operating range is 2 4 V 3 6 V total power X X X X down 1 brownout Brownout disabled Vpp operating range is 2 4 V 3 6 V detect X X X However BOPD is default to 0 upon power up powered down 0 brownout Brownout reset enabled Vpp operating range is 2 7 V detect X X 3 6 V Upon a brownout reset BOF RSTSRC 5 will be set to indicate the reset source BOF can be cleared by z 11 1 programmed unm uid writing 0 to the bit other than total power 0 1 1 down brownout enable global Brownout interrupt enabled Vpp operating range is 2 7 V detect 1 brownout interrupt 3 6 V Upon a brownout interrupt BOF RSTSRC 5 will active brownout inter
75. are two bits are affected by hardware the SI bit and the STO bit The SI bit is set by hardware and the STO bit is cleared by hardware determines the SCL source when the 12 is in master mode In slave mode this bit is ignored and the bus will automatically synchronize with any clock frequency up to 400 kHz from the master 2 device When CRSEL 1 the IC interface uses the Timer1 overflow rate divided by 2 for the I C clock rate Timer 1 should be programmed by the user in 8 bit auto reload mode Mode 2 Data rate of I C Timer overflow rate 2 PCLK 2 256 reload value If fosc 12 MHz reload value is 0 255 so I C data rate range is 11 72 Kbit sec 3000 Kbit sec When CRSEL 0 the 12C interface uses the internal clock generator based on the value of I2SCLL and I2CSCLH register The duty cycle does not need to be 50 2003 Dec 8 66 Philips Semiconductors User s Manual Preliminary 2 INTERFACE P89LPC930 931 The STA bit is START flag Setting this bit causes the I C interface to enter master mode and attempt transmitting a START condition or transmitting a repeated START condition when it is already in master mode The STO bit is STOP flag Setting this bit causes the interface to transmit a STOP condition in master mode or recovering from an error condition in slave mode If the STA and STO are both set then a STOP condition is transmitted to the I2C bus if it is in master mode and transmits
76. ator as its clock source This allows external devices to synchronize to the P89LPC930 931 This output is enabled by the ENCLK bit in the TRIM register The frequency of this clock output is 1 2 that of the CCLK If the clock output is not needed in Idle mode it may be turned off prior to entering Idle saving additional power Note on reset the TRIM SFR is initialized with a factory preprogrammed value Therefore when setting or clearing the ENCLK bit the user should retain the contents of bits 5 0 of the TRIM register This can 2003 Dec 8 21 Philips Semiconductors User s Manual Preliminary CLOCKS P89LPC930 931 be done by reading the contents of the TRIM register into the ACC for example modifying bit 6 and writing this result back into the TRIM register Alternatively the ANL direct or ORL direct instructions can be used to clear or set bit 6 of the TRIM register On chip RC oscillator option The P89LPC930 931 has a 6 bit TRIM register that can be used to tune the frequency of the RC oscillator During reset the TRIM value is initialized to a factory pre programmed value to adjust the oscillator frequency to 7 373 MHz 1 Note the initial value is better than 196 please refer to the datasheet for behavior over temperature End user applications can write to the TRIM register to adjust the on chip RC oscillator to other frequencies Increasing the TRIM value will decrease the oscillator frequency TRIM Addres
77. ature Using the In System Programming The ISP feature allows for a wide range of baud rates to be used in your application independent of the oscillator frequency It is also adaptable to a wide range of oscillator frequencies This is accomplished by measuring the bit time of a single bit ina received character This information is then used to program the baud rate in terms of timer counts based on the oscillator fre quency The ISP feature requires that an initial character an uppercase U be sent to the P89LPC930 931 to establish the baud rate The ISP firmware provides auto echo of received characters Once baud rate initialization has been performed the ISP firmware will only accept Intel Hex type records Intel Hex records consist of ASCII characters used to represent hexadecimal values and are summarized below NNAAAARRDD DDCC lt crif gt In the Intel Hex record the NN represents the number of data bytes in the record The P89LPC930 931 will accept up to 64 40H data bytes The AAAA string represents the address of the first byte the record If there are zero bytes in the record this field is often set to 0000 The string indicates the record type A record type of 00 is a data record A record type of 01 indicates the end of file mark In this application additional record types will be added to indicate either commands or data for the ISP facility The maximum number of data bytes in a record is limit
78. be divided down by an integer up to 510 times by configuring a dividing register DIVM to provide CCLK This produces the CCLK frequency using the following formula CCLK frequency fosc 2N Where fosc is the frequency of OSCCLK N is the value of DIVM Since N ranges from 1 to 255 the CCLK frequency can be in the range of fosc to 510 For N 20 CCLK fosc This feature makes it possible to temporarily run the CPU at a lower rate reducing power consumption By dividing the clock the CPU can retain the ability to respond to events other than those that can cause interrupts i e events that allow exiting the Idle mode by executing its normal program at a lower rate This can often result in lower power consumption than in Idle mode This can allow bypassing the oscillator start up time in cases where Power down mode would otherwise be used The value of DIVM may be changed by the program at any time without interrupting code execution Low power select The P89LPC930 931 is designed to run at 12 MHz CCLK maximum However if CCLK is 8 MHz or slower the CLKLP SFR bit AUXR1 7 can be set to a 1 to lower the power consumption further On any reset CLKLP is 0 allowing highest performance This bit can then be set in software if CCLK is running at 8 MHz or slower 2003 Dec 8 24 Philips Semiconductors User s Manual Preliminary INTERRUPTS P89LPC930 931 3 INTERRUPTS The P89LPC930 931 uses a four prior
79. c ccn 66 register Em 68 I2C SCL Duty Cycle registers IZSCLH and 25 68 2C operation TOUS siea nen qid e Ese Ce ena dos coe aras et tenui 69 Master Transmitter 69 Master Receiver Eq idee oti kw Rb a e ut QUE D Rd edo dpa 70 Slave Receiver Seeded 71 2003 Dec 8 3 Philips Semiconductors User Manual Subject to Change Table of Contents P89LPC930 931 Slave Transmitter 71 11 Serial Peripheral Interface 81 Typical SPI config realtloris routed b Emo Vade ee o asa i cete 83 COMMOUPING NG PT i eer c 85 Additional considerations for a 5 85 Additional considerations for a 5 85 Mode change 01 59 m se ete teat ot eee eld antec 86 WIRES COMMISION teste or 86 ALA AIO NC ex epa To si ml epum etam f Ores 86 SPIclock prescaler oo cn a Dus on nt 88 12 Analog comparators core bee pd oO Ow Gu gd 89 ie adit d ace eoo ee 89 Internal reference voltage eicere eeeeeee 90 COR ppAraterd
80. ce 96 timer mode 99 watchdog function 95 WDCLK 0 and CPU power down 100 2003 Dec 8 134 Philips Semiconductors User s manual Preliminary P89LPC930 931 Purchase of Philips 12C components conveys a license under the Philips 12C patent to use the components the I C system provided the system conforms to the 12C specifications defined by Philips This specification can be ordered using the code 9398 393 40011 Definitions Short form specification The data in a short form specification is extracted from a full data sheet with the same type number and title For detailed information see the relevant data sheet or data handbook Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System IEC 60134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied Exposure to limiting values for extended periods may affect device reliability Application information Applications that are described herein for any of these products are for illustrative purposes only Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification
81. ction is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern This function can be used for bus address recognition or keypad recognition The user can configure the port via SFRs for different tasks There are three SFRs used for this function The Keypad Interrupt Mask Register 5 is used to define which input pins connected to Port 0 are enabled to trigger the interrupt The Keypad Pattern Register KBPATN is used to define a pattern that is compared to the value of Port 0 The Keypad Interrupt Flag KBIF in the Keypad Interrupt Control Register KBCON is set when the condition is matched while the Keypad Interrupt function is active An interrupt will be generated if it has been enabled by setting the EKBI bit in IEN1 register and EA 1 The PATN SEL bit in the Keypad Interrupt Control Register KBCON is used to define equal or not equal for the comparison In order to use the Keypad Interrupt as an original KBI function like in the 87LPC76x series the user needs to set KBPATN OFFH and PATN SEL 0 not equal then any key connected to PortO which is enabled by KBMASK register is will cause the hardware to set KBIF 1 and generate an interrupt if it has been enabled The interrupt may be used to wake up the CPU from Idle or Power down modes This feature is particularly useful in handheld battery powered systems that need to carefully manage power consumption yet al
82. ctors These SFRs are FMCON Flash Control Register When read this is the status register When written this is a command register Note that the status bits are cleared to 0 s when the command is written FMDATA Flash Data Register Accepts data to be loaded into the page register FMADRL FMADRH Flash memory address low Flash memory address high Used to specify the byte address within the page register or specify the page within user code memory The page register consists of 64 bytes and an update flag for each byte When a LOAD command is issued to FMCON the page register contents and all of the update flags will be cleared When FMDATA is written the value written to FMDATA will be stored in the page register at the location specified by the lower 6 bits of FMADRL In addition the update flag for that location will be set FMADRL will auto increment to the next location Auto increment after writing to the last byte in the page register will wrap around to the first byte in the page register but will not affect FMADRL 7 6 Bytes loaded into the page register do not have to be continous Any byte location can be loaded into the page register by changing the contents of FMADRL prior to writ ing to FMDATA However each location in the page register can only be written once following each LOAD command Attempts to write to a page register location more than once should be avoided FMADRH and FMADRL T 6 are used t
83. cy clock when the Real time Clock is running during Power down Table 5 2 Power reduction modes 2003 Dec 8 Philips Semiconductors User s Manual Preliminary POWER MONITORING FUNCTIONS Poet 890 93 PCON 7 6 5 4 3 2 1 0 Address 87h SMOD1 SMODO BOPD BOI GF1 GFO PMOD1 PMODO Not bit addressable Reset Source s Any reset Reset Value 00000000B BIT SYMBOL FUNCTION PCON 7 SMOD1 Double Baud Rate bit for the serial port UART when Timer 1 is used as the baud rate source When 1 the Timer 1 overflow rate is supplied to the UART When 0 the Timer 1 overflow rate is divided by two before being supplied to the UART See Figure 9 2 PCON 6 SMODO Framing Error Location When 0 bit 7 of SCON is accessed as SMO for the UART When 1 bit 7 of SCON is accessed as the framing error status FE for the UART This bit also determines the location of the UART receiver interrupt RI see description on RI in Figure 9 3 PCON 5 BOPD Brownout Detect Power down When 1 Brownout Detect is powered down and therefore disabled When 0 Brownout Detect is enabled Note BOPD must be 0 before any programming or erasing commands can be issued Otherwise these commands will be aborted PCON 4 Brownout Detect Interrupt Enable When 1 Brownout Detection will generate a interrupt When 0 Brownout Detection will cause a reset PCON 3 GF1 General Purpose Flag 1 May be read or
84. d sequence al T oe A m M TO i i WATCHDOG 000 i i i DOWN PL b 4 4 t COUNTER et icu AELA i i after one PRE2 PH Maas iini Seu pee EET a prescaler DECODE 9977 i count delay PRE1 HOLE Ces ee Pee pee esa d 410 RS EE MEE Zl eur igen RM 1 PREO 1 DU OA NOU gt NG Bly tan ERE Figure 14 1 Watchdog Prescaler Feed Sequence The watchdog timer control register and the 8 bit down counter Figure 14 3 are not directly loaded by the user The user writes to the WDCON and the WDL SFRs At the end of a feed sequence the values in the WDCON and WDL SFRs are loaded to the control register and the 8 bit down counter Before the feed sequence any new values written to these two SFRs will not take effect To avoid a watchdog reset the watchdog timer needs to be fed via a special sequence of software action called the feed sequence prior to reaching an underflow To feed the watchdog two write instructions must be sequentially executed successfully Between the two write instructions SFR reads are allowed but writes are not allowed The instructions should move A5H to the WFEED1 register and then 5AH to the WFEED2 register An incorrect feed sequence will cause an immediate watchdog reset The program sequence to feed the watchdog timer is as follows CLR EA disable interrupt M
85. d by setting up the microcontroller s registers before making a call to PGM_MTP at FFOOH The IAP calls are shown in Table 16 4 IAP Authorization Key IAP functions which write or erase code memory require an authorization key be set by the calling routine prior to performing the IAP function call This authorization key is set by writing 96H to RAM location FFH For example MOV RO ZOFFH MOV RO 96H CALL PGM_MTP After the function call is processed by the IAP routine the authorization key will be cleared Thus it is necessary for the authori zation key to be set prior to EACH call to PGM_MTP that requires a key If an IAP routine that requires an authorization key is called without a valid authorization key present the MCU will perform a reset It is not possible to use the Flash memory as the source of program instructions while programming or erasing this same Flash memory During an IAP erase program or CRC the CPU enters a program idle state The CPU will remain in this program idle state until the erase program or CRC cycle is completed These cycles are self timed When the cycle is completed code exe cution resumes If an interrupt occurs during an erase programming or CRC cycle the erase programming or CRC cycle will be aborted so that the Flash memory can be used as the source of instructions to service the interrupt An IAP error condition will be flagged by setting the carry flag and status information returned The statu
86. d dra su Soe ee 41 Reset Sources register suere iip bed bee RU 42 Timer Counter Mode Control register TMOD 43 Timer Counter Auxiliary Mode Control register 44 Timer Counter Control register 46 Timer Counter 0 1 in Mode 0 13 bit 46 Timer Counter 0 or 1 in Mode 1 16 bit 47 Timer Counter 0 or 1 in Mode 2 8 bit 47 Timer Counter 0 Mode two 8 bit 47 Timer Counter 0 or 1 in Mode 6 PWM 48 Real time Clock System Timer block diagram 49 Real time Clock System Timer clock sources 50 RECCONIRCOISICh ve oua a vae e ou od eh esae uf sug 51 SFR Locations Tor UART So ies pw 22 3 eium ge at Pee e428 4 54 Baud rate generation for UART gt 2 20 5 ise RR RR REESE ERE EE ERE 54 bre i Ren rs iN oe eee ar pisi 55 Baud rate generation for UART Modes 1 3 55 Serial Port Control register SCON 56 Serial Port Status register SSTAT
87. d if I2ADR 071 POTEET AION I TER A START condition will be transmitted when the bus becomes free 2003 Dec 8 79 Philips Semiconductors User s Manual Preliminary I C INTERFACE P89LPC930 931 Table 5 Slave Transmitter Mode Continued Status code I2STAT Status of the I2C bus hardware Application software response to from I2DAT to l2CON STA STO SI Next action taken by 2 hardware C8H Last data byte in I2DAT has been transmitted AA 0 ACK has been received No I2DAT action or Switched to not addressed SLA mode no recognition of own SLA or General call address I2DAT action or 0 0 0 Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if IZADR 0O 1 no I2DAT action or 1 0 0 Switched to not addressed SLA mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free no I2DAT action 1 0 0 Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if IJADR 071 A START condition will be transmitted when the bus becomes free For more information about the 12 interface please refer to the 2 specification 2003 Dec 8 80 Philips Semiconductors User s Manual Preliminary SERIAL PERIPHERAL INTERFACE SPI P89LPC930 931 11 SERIAL
88. diate to A 2 1 44 ORL dir A OR A to direct byte 2 1 42 ORL dir data OR immediate to direct byte 3 2 43 XRL A Rn Exclusive OR register to A 1 1 68 6F XRL A dir Exclusive OR direct byte to A 2 1 65 XRL A Ri Exclusive OR indirect memory to A 1 1 66 67 XRL A data Exclusive OR immediate to A 2 1 64 XRL dir A Exclusive OR A to direct byte 2 1 62 XRL dir Zdata Exclusive OR immediate to direct byte 3 2 63 CLR A Clear A 1 1 E4 CPL A Complement A 1 1 F4 SWAP Swap Nibbles of A 1 1 C4 RLA Rotate A left 1 1 23 RLC A Rotate A left through carry 1 1 33 RRA Rotate A right 1 1 03 RRCA Rotate A right through carry 1 1 13 DATA TRANSFER MOV A Rn Move register to A 1 1 E8 EF MOV Air Move direct byte to A 2 1 E5 MOV A Ri Move indirect memory to A 1 1 E6 E7 MOV A data Move immediate to A 2 1 74 MOV Rn A Move A to register 1 1 F8 FF MOV Move direct byte to register 2 2 A8 AF MOV Rn data Move immediate to register 2 1 78 7F MOV dir A Move A to direct byte 2 1 F5 MOV dir Rn Move register to direct byte 2 2 88 8F MOV dir dir Move direct byte to direct byte 3 2 85 MOV dir Ri Move indirect memory to direct byte 2 2 86 87 2003 Dec 8 124 Philips Semiconductors User s Manual Preliminary INSTRUCTION SET PIEP Description Bytes Cycles Hex code MOV dir data Move immediate to direct byte 3 2
89. dress which has bit 0 0 for slave 0 and bit 1 0 for slave 1 Thus both could be addressed with 1100 0000 In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0 2003 Dec 8 62 Philips Semiconductors User s Manual Preliminary UART P89LPC930 931 Slave 0 SADDR 1100 0000 SADEN 1111 1001 Given 1100 OXX0 Slave 1 SADDR 1110 0000 SADEN 1111 1010 Given 1110 OXOX Slave 2 SADDR 1110 0000 SADEN 1111 1100 Given 1110 00XX In the above example the differentiation among the 3 slaves is in the lower 3 address bits Slave 0 requires that bit O 0 and it can be uniquely addressed by 1110 0110 Slave 1 requires that bit 1 0 and it can be uniquely addressed by 1110 and 0101 Slave 2 requires that bit 2 0 and its unique address is 1110 0011 To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100 since it is necessary to make bit 2 1 to exclude slave 2 The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN Zeros in this result are treated as don t cares In most cases interpreting the don t cares as ones the broadcast address will be FF hexadecimal Upon reset SADDR and SADEN are loaded with Os This produces a given address of all don t cares as well as a Broadcast address of all don t cares This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard UART drive
90. dtert H JEG as vasco Cod ores den enfant eter 90 Comparators and power reduction modes 90 Comparator configuration example 91 13 Keypad Interrupt e Eae reae Rug tds sb oae etitm o eor era eddie epos 93 WV ALCMOOG aa weve uae nba 95 Watchdog UG OM a doc eerte 95 Feed Sequence Soi uoi 96 5 AGL Bee dee 98 Watchdog Timer in Timer eee 99 lower dowm a E E aig ES 100 Periodic wakeup from Power down without an external oscillator 100 15 Additonal Features ernenek Ceessasadeacerss 101 Software TOSel ntl 101 Dual Data Pointers 101 Flash 103 General description sd qx Co ad e Gd bbs iid ova ant 103 pg eU 103 Flash programming and 56 103 Using Flash as data storage 103 In Circuit Programming 1
91. e If set 1 the SPI is enabled If cleared 0 the SPI is disabled and all SPI pins will be port pins SPI Data ORDer 1 The LSB of the data word is transmitted first 0 The MSB of the data word is transmitted first Master Slave mode Select see Table 11 1 SPI Clock POLarity see Figures 11 8 11 11 1 SPICLK is high when idle The leading edge of SPICLK is the falling edge and the trailing edge is the rising edge 0 SPICLK is low when idle The leading edge of SPICLK is the rising edge and the trailing edge is the falling edge SPI Clock PHAse select see Figures 11 8 11 11 1 Data is driven on the leading edge of SPICLK and is sampled on the trailing edge 0 Datais driven when SS is low SSIG 0 and changes on the trailing edge of SPICLK and is sampled on the leading edge Note If SSIG 1 the operation is not defined SPI Clock Rate Select SPI Clock Rate 00 0 1 10 11 CCLK 4 CCLK 16 CCLK 64 CCLK 128 2003 Dec 8 Figure 11 2 SPI Control register 82 Philips Semiconductors User s Manual Preliminary SERIAL PERIPHERAL INTERFACE SPI P89LPC930 931 SPSTAT Address E1h 7 6 5 4 3 2 1 0 Not bit addressable SPIF WCOL a 3 Reset Source s Any reset Reset Value 0 BIT SYMBOL FUNCTION SPSTAT 7 SPIF SPI Transfer Completion Flag When a serial transfer finishes the SPIF bit is set and an interrupt is generated i
92. e RTCF RTCCON 7 bit to determine whether the Real time Clock caused the interrupt RTCCON O RTCEN Real time Clock enable The Real time Clock will be enabled if this bit is 1 Note that this bit will not Power down the Real time Clock The RTCPD bit PCONA 7 if set will Power down and disable this block regardless of RTCEN Figure 8 2 RTCCON Register 2003 Dec 8 51 Philips Semiconductors User s Manual Preliminary REAL TIME CLOCK SYSTEM TIMER P89LPC930 931 2003 Dec 8 52 Philips Semiconductors User s Manual Preliminary UART P89LPC930 931 9 UART The P89LPC930 931 has an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source The P89LPC930 931 does include an independent Baud Rate Generator The baud rate can be selected from the oscillator divided by a constant Timer 1 overflow or the independent Baud Rate Generator In addition to the baud rate generation enhancements over the standard 80C51 UART include Framing Error detection break detect automatic address recognition selectable double buffering and several interrupt options The UART can be operated in 4 modes Mode 0 Serial data enters and exits through RxD TxD outputs the shift clock 8 bits are transmitted or received LSB first The baud rate is fixed at 1 16 of the CPU clock frequency Mode 1 10 bits are transmitted through TxD or received throu
93. e a processor reset However it may alternatively be configured to generate an interrupt by setting the BOI PCON 4 bit and the EBO IENO 5 bit Enabling and disabling of Brownout Detection is done via the BOPD PCON 5 bit bit field PMOD1 0 PCON 1 0 and user configuration bit BOE UCFG1 5 If BOE is in an unprogrammed state brownout is disabled regardless of PMOD1 0 and BOPD If BOE is in a programmed state PMOD 1 0 and BOPD will be used to determine whether Brownout Detect will be disabled or enabled PMOD1 0 is used to select the power reduction mode If PMOD1 0 11 the circuitry for the Brownout Detection is disabled for lowest power consumption BOPD defaults to 0 indicating brownout detection is enabled on power on if BOE is programmed If Brownout Detection is enabled the operating voltage range for Vpp is 2 7 V 3 6 V and the brownout condition occurs when Vpp falls below the Brownout trip voltage see D C Electrical Characteristics and is negated when Vpp rises above If Brownout Detection is disabled the operating voltage range for Vpp is 2 4 V 3 6 V If the P89LPC930 931 device is to operate with a power supply that can be below 2 7 V BOE should be left in the unprogrammed state so that the device can operate at 2 4 V otherwise continuous brownout reset may prevent the device from operating If Brownout Detect is enabled BOE programmed PMOD1 0 11 BOPD 0 BOF RSTSRC 5 will be set when
94. e cycle The Timer or Counter function is selected by control bits TnC T x 0 and 1 for Timers 0 and 1 respectively in the Special Function Register Timer 0 and Timer 1 have five operating modes modes 0 1 2 and 6 which are selected by bit pairs TnM1 TnMO in and TnM2 in TAMOD Modes 0 1 2 and 6 are the same for both Timers Counters Mode is different The operating modes are described later in this section TMOD 7 6 5 4 3 2 1 0 Address 89h TIGATE T1C T T1M1 T1MO TOGATE TOC T TOM1 TOMO Not bit addressable Reset Source s Any source Reset Value 00000000B BIT SYMBOL FUNCTION TMOD 7 T1GATE Gating control for Timer 1 When set Timer Counter is enabled only while the INT1 pin is high and the TR1 control pin is set When cleared Timer 1 is enabled when the TR1 control bit is set TMOD 6 T1C T Timer or Counter Selector for Timer 1 Cleared for Timer operation input from CCLK Set for Counter operation input from T1 input pin TMOD 5 4 T1M1 T1MO Mode Select for Timer 1 These bits are used with the T1M2 bit in the TAMOD register to determine the Timer 1 mode see Figure 7 2 TMOD 3 TOGATE Gating control for Timer 0 When set Timer Counter is enabled only while the INTO pin is high and the TRO control pin is set When cleared Timer 0 is enabled when the TRO control bit is set TMOD 2 TOC T Timer or Counter Selector for Timer 0 Cleared for Timer operation input from CCLK Set for C
95. ed to 64 decimal ISP commands are summarized in Table 16 2 As a record is received by the P89LPC930 931 the information in the record is stored internally and a checksum calculation is performed The operation indicated by the record type is not performed until the entire record has been received Should an error occur in the checksum the P89LPC930 931 will send an X out the serial port indicating a checksum error If the checksum calculation is found to match the checksum in the record then the command will be executed In most cases successful reception of the record will be indicated by transmitting a character out the serial port 2003 Dec 8 109 Philips Semiconductors User s Manual Preliminary FLASH MEMORY P89LPC930 931 Table 16 2 In System Programming ISP hex record formats Record type Command data function Program User Code Memory Page nnaaaa00dd ddcc Where nn number of bytes to program 00 aaaa page address data bytes cc checksum Example 100000000102030405006070809cc Read Version Id 00xxxx01cc Where 01 XXXX required field but value is a don t care cc checksum Example 00000001cc 2003 Dec 8 110 Philips Semiconductors FLASH MEMORY Table 16 2 In System Programming ISP hex record formats User s Manual Preliminary P89LPC930 931 Record type Command data function Miscellaneous Write
96. ed when Power down or Idle mode is activated but both comparators are disabled automatically in Total Power down mode If a comparator interrupt is enabled except in Total Power down mode a change of the comparator output state will generate an interrupt and wake up the processor If the comparator output to a pin is enabled the pin should be configured in the push pull mode in order to obtain fast switching times while in Power down mode The reason is that with the oscillator stopped the temporary strong pull up that normally occurs during switching on a quasi bidirectional port pin does not take place 2003 Dec 8 90 User s Manual Preliminary P89LPC930 931 Philips Semiconductors ANALOG COMPARATORS Comparators consume power in Power down and Idle modes as well as in the normal operating mode This should be taken into consideration when system power consumption is an issue To minimize power consumption the user can Power down the comparators by disabling the comparators and setting PCONA 5 to 1 or simply putting the device in Total Power down mode CPn CNn OEn 000 CPn CNn OEn 0 0 1 CINnA CINnA COn COn 7cMPn CMPREF CMPREF CPn CNn OEn 2010 CPn CNn OEn 0 1 1 CINnA CINnA COn COn Vref 1 23V Vref 1 23V CPn CNn OEn 100 CPn CNn OEn 10 1 CINnB CINnB COn COn CPn CNn OEn 110 CPn CNn OEn
97. ede qoos dest om eter itu talent ect est eriseu ea eet 31 Additional port featules ou oe towed eee aet at neca do a aa M ee ER 32 5 Power Monitoring 35 BrownodbetecllOEi3 a 35 Powerom DELG COM 36 Power reduction 36 BR Soe les cM lcs 41 2003 Dec 8 2 Philips Semiconductors User Manual Subject to Change Table of Contents P89LPC930 931 Reset eio MER MER 42 Ta Mimers 0and Mu TT 43 Mode O DNO exui ES Da DCN La eec 44 Mouse T ordeo bete adole D doeet ciu e wri ene fe Cof 44 MOS 2 cote e uad c rs c e E A M DM dE 45 MR 45 NOG etes AA hat cedat eit nate punit eun 45 Timer overflow toggle output enit erbe aut aedug 48 8 Real Time Clock System 49 Real time Clock SOUFICO RENS BUM 49 Changing RCS t O C 49 Real time Clock interrupt wake 50 Reset sources affecting the Real time Clock see 50 tU ERE 53 Mode Ucet tL cuia dee es ET 53 Vers e x 53 ona EIU M 53 lise PM
98. eiver mode 71 slave receiver states 76 IAP programming 103 Interrupts 29 arbitration ranking 25 edge triggered 26 external input pin glitch suppression 27 external inputs 26 keypad 26 priority structure 25 ISP programming 103 2003 Dec 8 130 Philips Semiconductors User Manual Subject to Change INDEX P89LPC930 931 m Low power CLKP 24 M Memory Code 19 Data 19 FLASH code 103 IDATA 19 organization 19 O Oscillator high speed option 21 low speed option 21 meduim speed option 21 RC option 22 watchdog WDT option 22 law Pin configuration 28 pin TSSOP package 9 Pin configuration 10 28 pin PLCC 10 Port 0 12 Port 1 13 Port 2 14 Port 3 14 Ports additional features 32 input only configuration 30 open drain output configuration 30 Port 0 analog functions 31 push pull output configuration 31 quasi bidirectional output configuration 29 Power reduction modes 36 normal mode 37 2003 Dec 8 131 Philips Semiconductors User Manual Subject to Change INDEX P89LPC930 931_ power down mode partial 37 Power down mode total 37 Power on detection 36 R Real time clock clock sources 49 interrupt wake up 50 Reset enabling the external reset input pin 41 119 software reset 101 sources 41 UART break detect ISP entry 42 un Serial Peripheral Interface SPI 81 SFR AUXR1 101 BRGCON 55 CMPn 89 I2ADR 66 I2CON 67 I2DAT 66 IZSCLH 68 IZSCLL 68 I2STAT 68 KBCON 93 KBMASK 94 KBPA
99. ers ACC 00h R3 number of bytes to program R4 page address MSB R5 page address LSB Program User Code Page requires key R7 pointer to data buffer in RAM F1 00h Return parameter s R7 status Carry set on error clear on no error Input parameters ACC 01h Read Version Id Return parameter s R7 IAP code version id 2003 Dec 8 115 Philips Semiconductors User s Manual Preliminary FLASH MEMORY P89LPC930 931 Table 16 4 IAP function calls IAP function IAP call parameters Input parameters ACC 02h R5 data to write R7 register address 00 UCFG1 01 reserved 02 Boot Vector 03 Status Byte 04 reserved 05 reserved 06 reserved Misc Write requires key 07 reserved 08 Security Byte 0 09 Security Byte 1 0A Security Byte 2 0B Security Byte 3 0C Security Byte 4 0D Security Byte 5 Security Byte 6 OF Security Byte 7 Return parameter s R7 status set on error clear on no error 2003 Dec 8 116 Philips Semiconductors User s Manual Preliminary FLASH MEMORY P89LPC930 931 Table 16 4 IAP function calls IAP function IAP call parameters Input parameters ACC 03h R7 register address 00 UCFG1 01 reserved 02 Boot Vector 03 Status Byte 04 reserved 05 reserved 06 reserved 07 reserved Misc Read 08 Security Byte 0 09 Security Byte 1
100. etected when 11 consecutive bits are sensed low and is reported in the status register SSTAT For Mode 1 this consists of the start bit 8 data bits and two stop bit times For Modes 2 amp 3 this consists of the start bit 9 data bits and one stop bit The break detect bit is cleared in software or by a reset The break detect can be used to reset the device and force the device into ISP mode This occurs if the UART is enabled and the the EBRR bit AUXR1 6 is set and a break occurs 2003 Dec 8 59 Philips Semiconductors User s Manual Preliminary UART P89LPC930 931 Double buffering The UART has a transmit double buffer that allows buffering of the next character to be wriiten to SBUF while the first character is being transmitted Double buffering allows transmission of a string of characters with only one stop bit between any two characters provided the next character is written between the start bit and the stop bit of the previous character Double buffering can be disabled If disabled DBMOD i e SSTAT 7 0 the UART is compatible with the conventional 80C51 UART If enabled the UART allows writing to SnBUF while the previous data is being shifted out Double buffering in different modes Double buffering is only allowed in Modes 1 2 and 3 When operated in Mode 0 double buffering must be disabled DBMOD 0 Transmit interrupts with double buffering enabled Modes 1 2 and 3 Unlike the conventional UART when
101. ey are reserved for future use FOSC2 FOSCO Oscillator Configuration 111 External clock input on XTAL1 100 Watchdog Oscillator 400 kHz 20 30 tolerance 011 Internal RC oscillator 7 373 MHz 2 5 010 Low frequency crystal 20 kHz to 100 kHz 0 0 1 Medium frequency crystal or resonator 100 kHz to 4 MHz 000 High frequency crystal or resonator 4 MHz to 12 MHz Factory default value for UCFG1 is set for watchdog reset disabled reset pin enabled brownout detect enabled and using the internal RC oscillator Figure 16 5 Flash User Configuration Byte 1 UCFG1 2003 Dec 8 119 Philips Semiconductors User s Manual Preliminary FLASH MEMORY P89LPC930 931 User security bytes This device has three security bits associated with each of its eight sectors as shown in Figure 6 SECx Address xxxxh Unprogrammed value 00h BIT SYMBOL SECx 7 3 SECx 2 EDISx SECx 1 SPEDISx SECx 0 MOVCDISx 7 6 5 4 3 2 1 0 2 z EDISx SPEDISxMOVCDISK FUNCTION Reserved should remain unprogrammed at zero Erase Disable x Disables the ability to perform an erase of sector x in ISP or IAP mode When programmed this bit and sector x can only be erased by a global erase command using a commercial programmer This bit and sector x CANNOT be erased in ISP or IAP modes Sector Program Erase Disable x Disables program or erase of all or part of sector x This bit and
102. f both the ESPI IEN1 3 bit and the EA bit are set If SS is an input and is driven low when SPI is in master mode and SSIG 0 this bit will also be set see section Mode change on SS The SPIF flag is cleared in software by writing 1 to this bit SPSTAT 6 WCOL SPI Write Collision Flag The WCOL bit is set if the SPI data register SPDAT is written during a data transfer see section Write collision The WCOL flag is cleared in software by writing 1 to this bit SPSTAT 5 0 Reserved for future use Should not be set to 1 by user programs Figure 11 3 SPI Status register definition SPDAT Address E3h 7 6 5 4 3 2 1 0 Not bit addressable MSB LSB Reset Source s Any reset Reset Value 00000000B BIT SYMBOL FUNCTION SPD 7 0 Bit 7 0 of data transferred Figure 11 4 SPI Data register TYPICAL SPI CONFIGURATIONS Master 8 Bit Shift Register 8 Bit Shift Register SPICLK SPICLK SPI Clock Genera tor Figure 11 5 SPI single master single slave configuration In Figure 11 5 SSIG SPCTL 7 for the slave is 0 and SS is used to select the slave The SPI master can use any port pin including P2 4 SS to drive the SS pin 2003 Dec 8 83 Philips Semiconductors SERIAL PERIPHERAL INTERFACE SPI Master Slave 8 Bit Shift Register
103. f programming this device are available Parallel programming with industry standard commercial programmers In Circuit serial Programming ICP with industry standard commercial programmers IAP Lite allows individual and multiple bytes of code memory to be used for data storage and programmed under control of the end application Internal fixed boot ROM containing low level In Application Programming IAP routines athat can be called from the end application in addition to IAP Lite A factory provided default serial loader located in upper end of user program memory providing In System Programming ISP via the serial port Using Flash as data storage IAP Lite The Flash code memory array of this device supports IAP Lite in addition to standard IAP functions Any byte in a non secured sector of the code memory array may be read using the MOVC instruction and thus is suitable for use as non volatile data stor age IAP Lite provides an erase program function that makes it easy for one or more bytes within a page to be erased and pro 2003 Dec 8 103 Philips Semiconductors User s Manual Preliminary FLASH MEMORY P89LPC930 931 grammed in a single operation without the need to erase or program any other bytes in the page IAP Lite is performed in the application under the control of the microcontroller s firmware using four SFRs and an internal 64 byte page register to facili tate erasing and programing within unsecured se
104. figured via UCFG1 Power on Detect Brownout Detect Watchdog Timer Software reset UART break detect reset For every reset source there is a flag in the Reset Register RSTSRC The user can read this register to determine the most recent reset source These flag bits can be cleared in software by writing a 0 to the corresponding bit More than one flag bit may be set During a power on reset both POF and BOF are set but the other flag bits are cleared For any other reset any previously set flag bits that have not been cleared will remain set RPE UCFG1 6 RST Pid WDTE UCFG1 7 Watchdog Timer Rese Software Reset SRST AUXR1 3 Chip Reset Power on Detect UART Break Detec EBRR AUXR1 6 Brownout Detect Reset BOPD 5 Figure 6 1 Block diagram of Reset 2003 Dec 8 41 Philips Semiconductors User s Manual Preliminary RESET P89LPC930 931 RSTSRC Address DFH 7 6 5 4 3 Not bit addressable R_BK R_WD R_SF R_EX Reset Sources Power on only Reset Value xx110000B This is the power on reset value Other reset sources will set corresponding bits BIT SYMBOL FUNCTION RSTSRC 7 6 Reserved for future use Should not be set to 1 by user programs RSTSRC 5 BOF Brownout Detect Flag When Brownout Detect is activated this bit is set It will remain set until cleared by software by writing a 0 to the bit Note On a Power
105. for Timers 0 and 1 respectively is set and cleared in hardware The low period of the TFn is in THn and should be between 1 and 254 and The high period of the TFn is always 256 THn Loading THn with OOh will force the Tx pin high loading THn with FFh will force the Tx pin low Note that interrupt can still be enabled on the low to high transition of TFn and that TFn can still be cleared in software like in any other modes 2003 Dec 8 45 Philips Semiconductors User s Manual Preliminary TIMERS 0 AND 1 P89LPC930 931 TCON 7 6 5 4 3 2 1 0 Address 88h TF1 TR1 TFO TRO IE1 IT1 IEO ITO Bit addressable Reset Source s Any reset Reset Value 00000000B BIT SYMBOL FUNCTION TCON 7 TF1 Timer 1 overflow flag Set by hardware on Timer Counter overflow Cleared by hardware when the interrupt is processed or by software except in mode 6 see above when it is cleared in hardware TCON 6 TR1 Timer 1 Run control bit Set cleared by software to turn Timer Counter 1 on off TCON 5 TFO Timer 0 overflow flag Set by hardware on Timer Counter overflow Cleared by hardware when the processor vectors to the interrupt routine or by software except in mode 6 see above when it is cleared in hardware TCON 4 TRO Timer 0 Run control bit Set cleared by software to turn Timer Counter 0 on off TCON 3 IE1 Interrupt 1 Edge flag Set by hardware when external inter
106. from data memory relative to DPTR to the accumulator Also any instruction that reads or manipulates the DPH and DPL registers the upper and lower bytes of the current DPTR will be affected by the setting of DPS The MOVX instructions have limited application for the P89LPC930 931 since the part does not have an external data bus However they may be used to access Flash configuration information see Flash Configuration section Bit 2 of AUXR1 is permanently wired as a logic 0 This is so that the DPS bit may be toggled thereby switching Data Pointers simply by incrementing the AUXR1 register without the possibility of inadvertently altering other bits in the register 2003 Dec 8 102 Philips Semiconductors User s Manual Preliminary FLASH MEMORY P89LPC930 931 16 FLASH MEMORY General description The P89LPC930 931 Flash memory provides in circuit electrical erasure and programming The Flash can be read and written as bytes The Sector and Page Erase functions can erase any Flash sector 1 KB or page 64 bytes The Chip Erase operation will erase the entire program memory Five Flash programming methods are available On chip erase and write timing generation contribute to a user friendly programming interface The P89LPC930 931 Flash reliably stores memory contents even after 100 000 erase and program cycles The cell is designed to optimize the erase and programming mechanisms The P89LPC930 931 uses Vpp as the supp
107. gh RxD a start bit logical 0 8 data bits LSB first and a stop bit logical 1 When data is received the stop bit is stored in RB8 in Special Function Register SCON The baud rate is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator see Baud Rate Generator and selection section Mode 2 11 bits are transmitted through TxD or received through RxD start bit logical 0 8 data bits LSB first a programmable 9th data bit and a stop bit logical 1 When data is transmitted the 9th data bit TB8 in SCON can be assigned the value of 0 or 1 Or for example the parity bit P in the PSW could be moved into TB8 When data is received the 9th data bit goes into RB8 in Special Function Register SCON and the stop bit is not saved The baud rate is programmable to either 1 16 or 1 32 of the CCLK frequency as determined by the SMOD bit in PCON Mode 3 11 bits are transmitted through TxD or received through RxD a start bit logical O 8 data bits LSB first a programmable 9th data bit and a stop bit logical 1 Mode 3 is the same as Mode 2 in all respects except baud rate The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator see Baud Rate Generator and selection section In all four modes transmission is initiated by any instruction that uses SBUF as a destination register Reception is initiated in Mode 0 by the condition RI 0 and
108. he Boot Vector is changed it will no longer point to the factory pre programmed ISP boot loader code If this happens the only way it is possible to change the contents of the Boot Vector is through the parallel or ICP programming method provided that the end user application does not contain a customized loader that provides for erasing and reprogramming of the Boot Vector and Boot Status Bit After programming the Flash the status byte should be programmed to zero in order to allow execution of the user s application code beginning at address 0000H 2003 Dec 8 108 Philips Semiconductors User s Manual Preliminary FLASH MEMORY P89LPC930 931 Figure 16 4 Forcing ISP Mode In System Programming ISP In System Programming is performed without removing the microcontroller from the system The In System Programming facil ity consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the P89LPC930 931 through the serial port This firmware is provided by Philips and embedded within each P89LPC930 931 device The Philips In System Programming facility has made in circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area The ISP function uses five pins Vdd Vss TxD RxD and RST Only a small connector needs to be available to interface your application to an external circuit in order to use this fe
109. hese conditions the external device has to sink enough current to overpower the weak pull up and pull the port pin below its input threshold voltage 2003 Dec 8 29 Philips Semiconductors User s Manual Preliminary PORTS P89LPC930 931 The third pull up is referred to as the strong pull up This pull up is used to speed up low to high transitions on a quasi bidirectional port pin when the port latch changes from a logic 0 to a logic 1 When this occurs the strong pull up turns on for two CPU clocks quickly pulling the port pin high The quasi bidirectional port configuration is shown in Figure 4 1 Although the P89LPC930 931 is a 3 V device most of the pins are 5 V tolerant If 5 V is applied to a pin configured in quasi bidirectional mode there will be a current flowing from the pin to Vpp causing extra power consumption Therefore applying 5 V to pins configured in quasi bidirectional mode is discouraged A quasi bidirectional port pin has a Schmitt triggered input that also has a glitch suppression circuit Please refer to the P89LPC930 931 datasheet AC Electrical Characteristics for glitch filter specifications Vpp 2 clock delay strong d very d Weak Mea e e e por pin port latch data gt o V input data lt 1 e od glitch rejection Figure 4 1 Quasi bidirectional output Ope
110. hould remain unprogrammed at zero BOOTVEC 4 0 Boot Vector If the Boot Vector is selected as the reset address the P89LPC930 931 will start execution at an address comprised of OOH in the lower eight bits and this BOOTVEC as the upper bits after a reset See section Reset vector on page 42 Figure 16 7 Boot Vector BOOTVEC Boot Status BOOTSTAT 7 6 5 4 3 2 1 0 Address xxxxh BSB Factory default value 01h BIT SYMBOL FUNCTION BOOTSTAT 7 1 BOOTSTAT 0 BSB Reserved should remain unprogrammed at zero Boot Status Bit If programmed to 1 the P89LPC930 931 will always start execution at an address comprised of 00H in the lower eight bits and BOOTVEC as the upper bits after a reset See section Reset vector on page 42 2003 Dec 8 Figure 16 8 Boot Status BOOTSTAT 121 Philips Semiconductors User s Manual Preliminary FLASH MEMORY P89LPC930 931 2003 Dec 8 122 Philips Semiconductors User s Manual Preliminary INSTRUCTION SET indict 17 INSTRUCTION SET Table 1 Instruction set summary Mnemonic Description Bytes Cycles Hain ARITHMETIC ADD A Rn Add register to A 1 1 28 2F ADD Add direct byte to A 2 1 25 ADD A Ri Add indirect memory to A 1 1 26 27 ADD A data Add immediate to A 2 1 24 ADDC A Rn Add register to A with carry 1 1 38 3F ADDC A dir Add direct byte t
111. iconductors User s Manual Preliminary UART P89LPC930 931 o Tx Interrupt t t t 1 Single Buffering DBMOD SSTAT 7 0 Early Interrupt INTLO SSTAT 6 0 is Shown sour 1 Tx Interrupt t t i Double Buffering DBMOD SSTAT 7 1 Early Interrupt INTLO SSTAT 6 0 is Shown No End ing Tx Interrupt DBISEL SnSTAT 4 0 CE E f Double Buffering DBMOD SSTAT 7 1 Early Interrupt INTLO SSTAT 6 0 is Shown With Ending Tx Interrupt DBISEL SSTAT 4 1 Figure 9 8 Transmission with and without double buffering The 9th bit bit 8 in double buffering Modes 1 2 and 3 If double buffering is disabled DBMOD i e SSTAT 7 0 TB8 can be written before or after SBUF is written provided TB8 is updated before that TB8 is shifted out TB8 must not be changed again until after TB8 shifting has been completed as indicated by the Tx interrupt If double buffering is enabled TB8 MUST be updated before SBUF is written as TB8 will be double buffered together with SBUF data The operation described in the section Transmit interrupts with double buffering enabled Modes 1 2 and 3 becomes as follows The double buffer is empty initially The CPU writes to TB8 The CPU writes to SBUF The SBUF TB8 data is loaded to the shift register and a Tx interrupt is generated immediately If there is more data go to 7 else continue on 6 If there is no more data then If
112. iconductors User Manual Subject to Change INDEX P89LPC930 931_ 19 INDEX A Analog comparators 31 configuration 89 configuration example 91 enabling 89 internal reference voltage 90 interrupt 90 power reduction modes 90 91 Analog comparators and power reduction 31 is Block diagram 11 BRGCON writing to 18 Brownout detection 35 enabling and disabling 35 operating range 35 options 36 rise and fall times of Vdd 35 C Capture Compare Unit 53 CLKLP 24 Clock CPU clock 21 CPU divider DIVM 24 definitions 21 external input option 22 output 21 PCLK 21 RCCLK 21 wakeup delay 23 2003 Dec 8 129 Philips Semiconductors User Manual Subject to Change INDEX P89LPC930 931 D Data EEPROM block fill 9 21 25 29 35 41 43 49 53 65 89 93 95 101 103 123 127 hardware reset 9 21 25 29 35 41 43 49 53 65 89 93 95 101 103 123 127 Dual Data Pointers 101 F FLASH 9 21 25 29 35 41 43 49 53 65 89 93 95 101 103 123 127 Boot Status 121 Boot Vector 121 Bootrom 108 features 103 hardware activation of the boot loader 108 in application programming IAP 114 ISP 107 109 ISP IAP capabilities 107 power on reset code execution 108 programming and erasure 103 sector size 107 E I2C serial interface clock rate selection for common frequencies 68 master receiver mode 70 master receiver states 75 master transmitter mode 69 master transmitter states 74 slave rec
113. ill in turn call low level routines through the same common entry point that can be used by the end user application Boot ROM When the microcontroller contains a a 256 byte Boot ROM that is separate from the user s Flash program memory This Boot ROM contains routines which handle all of the low level details needed to erase and program the user Flash memory A user program simply calls a common entry point in the Boot ROM with appropriate parameters to accomplish the desired operation Boot ROM operations include operations such as erase sector erase page program page CRC program security bit etc The Boot ROM occupies the program memory space at the top of the address space from FF00 to FFFF hex thereby not conflicting with the user program memory space This function is in addition to the IAP Lite feature Power On reset code execution The P89LPC930 931 contains two special Flash elements the BOOT VECTOR and the Boot Status Bit Following reset the P89LPC930 931 examines the contents of the Boot Status Bit If the Boot Status Bit is set to zero power up execution starts at location 0000H which is the normal start address of the user s application code When the Boot Status Bit is set to a va one the contents of the Boot Vector is used as the high byte of the execution address and the low byte is set to OOH The factory default settings for these devcies are show in Table 16 1 below The factory pre programmed boot loader can be
114. inate Idle mode Power down mode The Power down mode stops the oscillator in order to minimize power consumption m The P89LPC930 931 exits Power down mode via any reset or certain interrupts external pins INTO INT1 brownout Interrupt keyboard Real time Clock System Timer watchdog and comparator trips Waking up by reset is only enabled if the corresponding reset is enabled and waking up by interrupt is only enabled if the corresponding interrupt is enabled and the EA SFR bit IENO 7 is set In Power down mode the internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock AND the RTC is enabled In Power down mode the power supply voltage may be reduced to the RAM keep alive voltage Vram This retains the RAM contents at the point where Power down mode was entered SFR contents are not guaranteed after Vpp has been lowered to Vram therefore it is recommended to wake up the processor via Reset in this situation Vpp must be raised to within the operating range before the Power down mode is exited When the processor wakes up from Power down mode it will start the oscillator immediately and begin execution when the oscillator is stable Oscillator stability is determined by counting 1024 CPU clocks after start up when one of the crystal oscillator configurations is used or 256 clocks after start up for the internal RC or external clock input configurations Some chip functions c
115. ing errors can be made available in SCON 7 If SMODO is 0 SCON 7 is SMO It is recommended that SMO and SM1 SCON 7 6 are programmed when SMODO is 0 Break Detect A break detect is reported in the status register SSTAT A break is detected when any 11 consecutive bits are sensed low Since a break condition also satisfies the requirements for a framing error a break condition will also result in reporting a framing error Once a break condition has been detected the UART will go into an idle state and remain in this idle state until a stop bit has been received The break detect can be used to reset the device and force the device into ISP mode by setting the EBRR bit AUXR1 6 2003 Dec 8 55 Philips Semiconductors User s Manual Preliminary UART P89LPC930 931 SCON Address 98h 7 6 5 4 3 2 1 0 Bit addressable SMO FE SM1 SM2 REN TB8 RB8 TI RI Reset Source s Any reset Reset Value 00000000B BIT SYMBOL FUNCTION SCON 7 SMO FE The use of this bit is determined by SMODO in the PCON register If SMODO 0 this bit is read and written as SMO which with SM1 defines the serial port mode If SMODO 1 this bit is read and written as FE Framing Error FE is set by the receiver when an invalid stop bit is detected Once set this bit cannot be cleared by valid frames but is cleared by software Note UART mode bits SMO and SM1 should be programmed when SMODO is 0 default
116. internal 7 373 MHz RC oscillator output PCLK Clock for the various peripheral devices and is CCLK 2 Oscillator clock OSCCLK The P89LPC930 931 provides several user selectable oscillator options This allows optimization for a range of needs from high precision to lowest possible cost These options are configured when the FLASH is programmed and include an on chip watchdog oscillator an on chip RC oscillator an oscillator using an external crystal or an external clock source The crystal oscillator can be optimized for low medium or high frequency crystals covering a range from 20 kHz to 12 MHz Low speed oscillator option This option supports an external crystal in the range of 20 kHz to 100 kHz Ceramic resonators are also supported in this configuration Medium speed oscillator option This option supports an external crystal in the range of 100 kHz to 4 MHz Ceramic resonators are also supported in this configuration High speed oscillator option This option supports an external crystal in the range of 4 MHz to 12 MHz Ceramic resonators are also supported in this configuration Clock output The P89LPC930 931 supports a user selectable clock output function on the XTAL2 CLKOUT pin when the crystal oscillator is not being used This condition occurs if a different clock source has been selected on chip RC oscillator watchdog oscillator external clock input on X1 and if the Real time Clock is not using the crystal oscill
117. ity level interrupt structure This allows great flexibility in controlling the handling of the P89LPC930 931 s 13 interrupt sources Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IENO or IEN1 The IENO register also contains a global enable bit EA which enables all interrupts Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IPO IPOH IP1 and IP1H An interrupt service routine in progress can be interrupted by a higher priority interrupt but not by another interrupt of the same or lower priority The highest priority interrupt service cannot be interrupted by any other interrupt source If two requests of different priority levels are received simultaneously the request of higher priority level is serviced If requests of the same priority level are pending at the start of an instruction cycle an internal polling sequence determines which request is serviced This is called the arbitration ranking Note that the arbitration ranking is only used for pending requests of the same priority level Table 3 2 summarizes the interrupt sources flag bits vector addresses enable bits priority bits arbitration ranking and whether each interrupt may wake up the CPU from a Power down mode Interrupt priority structure There are four SFRs associated with the four interrupt le
118. ken by 2 125 I C bus hardware to from I2DAT to I2CON hardware STA STO SI Last data byte will be transmitted and ACK Own SLA Rhas Load data byteor x 0 0 bit will be received A8h been received ACK UE has been returned load data byte x 0 0 Data byte will be transmitted ACK will be received Arbitration lost in Last data byte will be transmitted and ACK SLA R W as Load data x 0 0 bit will be received BOh master Own SLA R has been received Data byte will be transmitted ACK hasbeen load data byte x 0 ACK bit will be received returned Tir Last data byte will be transmitted and ACK Data byte in I2DAT oad data byteor o o bit will be received has been B8H transmitted ACK has been received load data byte 0 0 Data byte will be transmitted ACK will be received Switched to not addressed SLA mode no No IZDA Taction or 0 0 0 recognition of own SLA or General call address Switched to not addressed SLA mode Own I2DAT action or 0 0 0 slave address will be recognized General call address will be recognized if IZADR 0 1 Data byte in IZ2DAT Switched to not addressed SLA mode no has been recognition of own SLA or General call COH ansmitted nacK I2DAT action or 1 0 0 address A START condition will be hasbeen received transmitted when the bus becomes free Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognize
119. l be activated only if RB8 1 This feature is enabled by setting bit SM2 in SCON One way to use this feature in multiprocessor systems is as follows When the master processor wants to transmit a block of data to one of several slaves it first sends out an address byte which identifies the target slave An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte With SM2 1 no slave will be interrupted by a data byte An address byte however will interrupt all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave will clear its SM2 bit and prepare to receive the data bytes that follow The slaves that weren t being addressed leave their SM2 bits set and go on about their business ignoring the subsequent data bytes Note that SM2 has no effect in Mode 0 and must be 0 in Mode 1 Automatic address recognition Automatic address recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port This feature is enabled by setting the SM2 bit in SCON In the 9 bit UART modes mode 2 and mode 3 the Receive Interrupt flag RI will be automatically set when the received byte contains either the Given addre
120. lized as follows 7 6 5 4 3 2 1 0 I2CON D8h I2EN STA STO SI AA CRSEL 1 0 0 0 x bit rate Figure 6 Control register CRSEL defines the bit rate I2EN must be set to 1 to enable the 12C function If the AA bit is 0 it will not acknowledge its own slave address or the general call address in the event of another device becoming master of the bus and it can not enter slave mode STA STO and SI bits must be cleared to O The first byte transmitted contains the slave address of the receiving device 7 bits and the data direction bit In this case the data direction bit R W will be logic 0 indicating a write Data is transmitted 8 bits at a time After each byte is transmitted an acknowledge bit is received START and STOP conditions are output to indicate the beginning and the end of a serial transfer The 2 will enter Master Transmitter Mode by setting the STA bit The 2 logic will send the START condition as soon as the bus is free After the START condition is transmitted the SI bit is set and the status code in I2STAT should be 08h This status code must be used to vector to an interrupt service routine where the user should load the slave address to I2DAT Data Register and data direction bit SLA W The SI bit must be cleared before the data transfer can continue When the slave address and R W bit have been transmitted and an acknowledgment bit has been received the SI bit is
121. ll be received and ACK will be ACK returned no I2DAT action X 0 0 returned Data byte will be received NOT ACK will General call No I2DAT action x 0 0 be returned 70H address 00H has no I2DAT action x 0 0 Data byte will be received and ACK will be returned 2003 Dec 8 76 Philips Semiconductors I C INTERFACE Table 4 Slave Receiver Mode Continued User s Manual Preliminary P89LPC930 931 Status Application software response code Status of the Next action taken by 2 I2STAT 2 5 hardware to from I2DAT to I2CON hardware STA STO SI Arbitration lost in I2DAT acti Data byte will be received and NOT ACK will SLA RIW as ACION OEN 0 0 be returned master General call ren dd has b See ee Data byte will be received and ACK will be received ACK bit no I2DAT action x 0 0 returned has been returned Previously Read data Data byte will be received and NOT ACK will addressed with own x 0 0 be returned SLA address Data 80H hasb ied Data byte will be received ACK bit will be ACK has been read data byte X 0 0 returned returned Read data byte or Switched to not addressed SLA mode no 0 0 0 x recognition of own SLA or general address d data bvt Switched to not addressed SLA mode Own rga bA yte 0 0 0 SLA will be recognized general call address Previously will
122. ly voltage to perform the Program Erase algorithms Features Parallel programming with industry standard commercial programmers In Circuit serial Programming ICP with industry standard commercial programmers IAP Lite allows individual and multiple bytes of code memory to be used for data storage and programmed under control of the end application Internal fixed boot ROM containing low level In Application Programming IAP routines that can be called from the end application in addition to IAP Lite Default serial loader providing In System Programming ISP via the serial port located in upper end of user program memory Boot vector allows user provided Flash loader code to reside anywhere in the Flash memory space providing flexibility to the user Programming and erase over the full operating voltage range Read Programming Erase using ISP IAP IAP Lite Any flash program operation in 2 ms 4ms for erase program Programmable security for the code in the Flash for each sector gt 100 000 typical erase program cycles for each byte 10 year minimum data retention Flash programming and erase The P89LPC930 931 program memory consists 1 KB sectors Each sector can be further divided into 64 byte pages In addition to sector erase and page erase a 64 byte page register is included which allows from 1 to 64 bytes of a given page to be programmed at the same time substantially reducing overall programming time Five mthods o
123. mparator function is enabled Comparator output is stable 10 microseconds after CEn is set CMPn 4 CPn Comparator positive input select When 0 CINnA is selected as the positive comparator input When 1 CINnB is selected as the positive comparator input CMPn 3 CNn Comparator negative input select When 0 the comparator reference pin CMPREF is selected as the negative comparator input When 1 the internal comparator reference Vref is selected as the negative comparator input CMPn 2 OEn Output enable When 1 the comparator output is connected to the CMPn pin if the comparator is enabled CEn 1 This output is asynchronous to the CPU clock CMPn 1 COn Comparator output synchronized to the CPU clock to allow reading by software CMPn 0 CMFn Comparator interrupt flag This bit is set by hardware whenever the comparator output COn changes state This bit will cause a hardware interrupt if enabled Cleared by software Figure 12 1 Comparator control registers CMP1 and CMP2 2003 Dec 8 89 Philips Semiconductors User s Manual Preliminary ANALOG COMPARATORS P89LPC930 931 E Comparator 1 P0 4 PE P0 3 CINTB 7 CO1 P0 6 P0 5 CMPREF __ Vref Change Detect CN1 zi gt Interrupt Change Detect 2 2 2 ciN24 P0 1 ciN28 an P0 0 i 2 CN2
124. n drain output configuration The open drain output configuration turns off all pull ups and only drives the pulldown transistor of the port pin when the port latch contains a logic O To be used as a logic output a port configured in this manner must have an external pull up typically a resistor tied to Vpp The pulldown for this mode is the same as for the quasi bidirectional mode The open drain port configuration is shown in Figure 4 2 An open drain port pin has a Schmitt triggered input that also has a glitch suppression circuit Please refer to the P89LPC930 931 datasheet AC Electrical Characteristics for glitch filter specifications port pin port latch data 0 input data eg glitch rejection Figure 4 2 Open drain output Input only configuration 2003 Dec 8 30 Philips Semiconductors User s Manual Preliminary PORTS P89LPC930 931 The input port configuration is shown in Figure 4 3 It is a Schmitt triggered input that also has a glitch suppression circuit Please refer to the P89LPC930 931 datasheet AC Electrical Characteristics for glitch filter specifications input data g e io glitch rejection Figure 4 3 Input only Push pull output configuration The push pull output configuration has the same pulldown structure as both the open drain and the quasi bidirectional outpu
125. ned Serial Port UART Tx and Rx interrupt SSTAT 5 1 selects Serial Port Rx interrupt only Tx interrupt will be different see Note 3 below 2 This interrupt is used as Serial Port UART Tx interrupt if and only if SSTAT 5 1 and is disabled otherwise 3 If SSTAT O 1 the following Serial Port additional flag bits can cause this interrupt FE BR OE Table 3 2 Summary of interrupts External Interrupt inputs The P89LPC930 931 has two external interrupt inputs in addition to the Keypad Interrupt function The two interrupt inputs are identical to those present on the standard 80C51 microcontrollers These external interrupts can be programmed to be level triggered or edge triggered by clearing or setting bit IT1 or ITO in Register TCON If Tn 0 external interrupt n is triggered by a low level detected at the INTn pin If ITn 1 external interrupt n is edge triggered In this mode if consecutive samples of the INTn pin show a high level in one cycle and a low level in the next cycle interrupt request flag IEn in TCON is set causing an interrupt request Since the external interrupt pins are sampled once each machine cycle an input high or low level should be held for at least one machine cycle to ensure proper sampling If the external interrupt is edge triggered the external source has to hold the request pin high for at least one machine cycle and then hold it low for at least one machine cycle This is to ensure that
126. neral call Data recognition of own SLA or General call 98H has been received ead data byte 1 0 0 address A START condition will be NACK has been transmitted when the bus becomes free returned Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if I2ADR 0 1 Ld byte 9 lt 0 A START condition will be transmitted when the bus becomes free Switched to not addressed SLA mode no No I2DAT action 0 0 0 recognition of own SLA or General call address I2DAT acti Switched to not addressed SLA mode Own ne ean 0 0 0 slave address will be recognized General call address will be recognized if I2ADR 071 A STOP condition or repeated START Switched to not addressed SLA mode no condition has been recognition of own SLA or General call HON Netter acca It ee ga Ge 89 address A START condition will be addressed as SLA transmitted when the bus becomes free REC or SLA TRX Switched to not addressed SLA mode Own slave address will be recognized General no I2DAT action 4 0 0 call address will be recognized if I2ADR 071 A START condition will be transmitted when the bus becomes free 2003 Dec 8 78 Philips Semiconductors User s Manual Preliminary I C INTERFACE Table 5 Slave Transmitter Mode P89LPC930 931 Status Application software response code Status of the Next action ta
127. o 16 counter states At the Tth 8th and 9th counter states the bit detector samples the value of RxD The value accepted is the value that was seen in at least 2 of the 3 samples This is done for noise rejection If the value accepted during the first bit time is not 0 the receive circuits are reset and the receiver goes back to looking for another 1 to 0 transition This provides rejection of false start bits If the start bit proves valid it is shifted into the input shift register and reception of the rest of the frame will proceed The signal to load SBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated RI 0 and either SM2 0 or the received stop bit 1 If either of these two conditions is not met the received frame is lost If both conditions are met the stop bit goes into RB8 the 8 data bits go into SBUF and RI is activated TX Clock Write to SBUF Transmit Start BitX X Di X D2 X D3 X X DS X De X D7 TI INTEO 0 INTLO 1 RX Clock RxD 16 Reset gt start BitX DO X Di X 55 X D3 X X D5 X 07 y Sop Bi Receive Figure 9 6 Serial Port Mode 1 only single transmit buffering case is shown 2003 Dec 8 58 Philips Semiconductors User s Manual Preliminary UART P89LPC930 931 More about UART Mode
128. o A with carry 2 1 35 ADDC A Ri Add indirect memory to A with carry 1 1 36 37 ADDC A data Add immediate to A with carry 2 1 34 SUBB A Rn Subtract register from A with borrow 1 1 98 9F SUBB A dir Subtract direct byte from A with borrow 2 1 95 SUBB A QRi Subtract indirect memory from A with borrow 1 1 96 97 SUBB A data Subtract immediate from A with borrow 2 1 94 INC A Increment A 1 1 04 INC Rn Increment register 1 1 08 0F INC dir Increment direct byte 2 1 05 INC Ri Increment indirect memory 1 1 06 07 DECA Decrement A 1 1 14 DEC Rn Decrement register 1 1 18 1F DEC dir Decrement direct byte 2 1 15 DEC Ri Decrement indirect memory 1 1 16 17 INC DPTR Increment data pointer 1 2 A3 MUL AB Multiply A by B 1 4 A4 DIV AB Divide A by B 1 4 84 DAA Decimal Adjust A 1 1 D4 LOGICAL ANL A Rn AND register to A 1 1 58 5F ANL A dir AND direct byte to A 2 1 55 ANL A Ri AND indirect memory to A 1 1 56 57 ANL A data AND immediate to A 2 1 54 2003 Dec 8 123 Philips Semiconductors User s Manual Preliminary INSTRUCTION SET PIEP Description Bytes Cycles Hex code ANL dir A AND A to direct byte 2 1 52 ANL dir data AND immediate to direct byte 3 2 53 ORL A Rn OR register to A 1 1 48 4F ORL A dir OR direct byte to A 2 1 45 ORL A Ri OR indirect memory to A 1 1 46 47 ORL A data OR imme
129. o select a page of code memory for the erase program function When the erase pro gram command is written to FMCON the locations within the code memory page that correspond to updated locations in the page register will have their contents erased and programmed with the contents of their corresponding locations in the page register Only the bytes that were loaded into the page register will be erased and programmed in the user code array Other bytes within the user code memory will not be affected Writing the erase program command 68H to FMCON will start the erase program process and place the CPU in a program idle state The CPU will remain in this idle state until the erase program cycle is either completed or terminated by an interrupt When the program idle state is exited FMCON will contain status information for the cycle If an interrupt occurs during an erase programming cycle the erase programming cycle will be aborted and the OI flag Opera tion Interrupted in FMCON will be set If the application permits interrupts during erasing programming the user code should check the OI flag FMCON 0 after each erase programming operation to see if the operation was aborted If the operation was aborted the user s code will need to repeat the process starting with loading the page register The erase program cycle takes 4ms 2ms for erase 2ms for programming to complete regardless of the number of bytes that were loaded into the page register
130. ocked from either the watchdog oscillator or from PCLK refer to Figure 14 1 by configuring the WDCLK bit in the Watchdog Control Register WDCON When the watchdog feature is enabled the timer must be fed regularly by software in order to prevent it from resetting the CPU After changing WDCLK WDCON O switching of the clock source will not immediately take effect As shown in Figure 14 3 the selection is loaded after a watchdog feed sequence In addition due to clock synchronization logic it can take two old clock cycles before the old clock source is deselected and then an additional two new clock cycles before the new clock source is selected Since the prescaler starts counting immediately after a feed switching clocks can cause some inaccuracy in the prescaler count The inaccuracy could be as much as 2 old clock source counts plus 2 new clock cycles Note When switching clocks it is important that the old clock source is left enabled for 2 clock cycles after the feed completes Otherwise the watchdog may become disabled when the old clock source is disabled For example suppose PCLK WCLK 0 is the current clock source After WCLK is set to 1 the program should wait at least two PCLK cycles 4 after the feed completes before going into Power down mode Otherwise the watchdog could become disabled when CCLK turns off The watchdog oscillator will never become selected as the clock source unless CCLK is turned on again first
131. of the address 00h The Boot address will be used if a UART break reset occurs or the non volatile Boot Status bit BOOTSTAT 0 1 or the device has been forced into ISP mode Otherwise instructions will be fetched from address 0000H 2003 Dec 8 42 Philips Semiconductors User s Manual Preliminary TIMERS 0 AND 1 P89LPC930 931 7 TIMERS 0 AND 1 The P89LPC930 931 has two general purpose counter timers which are upward compatible with the 80C51 Timer 0 and Timer 1 Both can be configured to operate either as timers or event counters see Figure 7 1 An option to automatically toggle the Tx pin upon timer overflow has been added In the Timer function the register is incremented every PCLK In the Counter function the register is incremented in response to a 1 to 0 transition on its corresponding external input pin TO or T1 The external input is sampled once during every machine cycle When the pin is high during one cycle and low in the next cycle the count is incremented The new count value appears in the register during the cycle following the one in which the transition was detected Since it takes 2 machine cycles 4 CPU clocks to recognize a 1 to 0 transition the maximum count rate is 1 4 of the CPU clock frequency There are no restrictions on the duty cycle of the external input signal but to ensure that a given level is sampled at least once before it changes it should be held for at least one full machin
132. ontinue to operate and draw power during Power down mode increasing the total power used during Power down These include Brownout Detect Watchdog Timer if WDCLK WDCON 0 is 1 Comparators Note Comparators can be powered down separately with PCONA 5 set to 1 and comparators disabled Real time Clock System Timer and the crystal oscillator circuitry if this block is using it unless RTCPD i e PCONA 7 is 1 Total power down mode This is the same as Power down mode except that the Brownout Detection circuitry and the voltage comparators are also disabled to conserve additional power Note that a brownout reset or interrupt will not occur Voltage comparator interrupts and Brownout interrupt cannot be used as a wakeup source The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock AND the RTC is enabled The following are the wakeup options supported Watchdog Timer if WDCLK WDCON 0 is 1 Could generate Interrupt or Reset either one can wake up the device External interrupts INTO INT1 Keyboard Interrupt Real time Clock System Timer and the crystal oscillator circuitry if this block is using it unless RTCPD i e PCONA 7 is 1 Note Using the internal RC oscillator to clock the RTC during Power down may result in relatively high power consumption Lower power consumption can be achieved by using an external low frequen
133. ontrol D1H RTCF RTCS1 RTCSO ERTC 60H 9 011xxx00 RTCH Real Time Clock Register High D2H OOH 00000000 RTCL Real Time Clock Register Low D3H 00H 00000000 SADDR Serial Port Address Register A9H 00H 00000000 SADEN Serial Port Address Enable B9H 00H 00000000 SBUF Serial Port Data Buffer Register 99H XXXXXXXX 9F 9E 9D 9C 9B 9A 99 98 SCON Serial Port Control 98H SMO FE SM1 SM2 REN TB8 RB8 TI RI 00H 00000000 SSTAT RU Extended Status INTLO CIDIS DBISEL FE BR OE STINT 00000000 SP Stack Pointer 81H 07H 00000111 SPCTL SPI Control Register E2H SSIG SPEN DORD CPOL SPR1 SPRO 04H 00000100 SPSTAT SPI Status Register E1H SPIF WCOL 00H 0 SPDAT SPI Data Register E3H 00H 00000000 TAMOD 0 and 1 Auxiliary Mode 8FH T1M2 TOM2 00H 8F 8b 8D 8C 8B 8A 89 88 TCON Timer 0 and 1 Control 88H TF1 TR1 TFO TRO IE1 IT1 IEO ITO 00H 00000000 THO Timer 0 High 8CH 00H 00000000 TH1 Timer 1 High 8DH 00H 00000000 TLO Timer 0 Low 8AH 00H 00000000 TL1 Timer 1 Low 8BH 00H 00000000 TMOD Timer 0 and 1 Mode 89H 1 T1C T T1M1 TOGATE TOC T TOM1 TOMO 00H 00000000 TRIM Internal Oscillator Trim Register 96H ENCLK TRIM 5 TRIM 4 TRIM 3 TRIM 2 TRIM 1 TRIM O Notes 4 5 2003 Dec 8 17 Philips Semiconductors User s Manual Preliminary General Description P89LPC930 931
134. oot 108 Oring ISP Mode C ies ute abes tee Aer Ri Me LI le eri si Cle he Ne ak 109 In System Programming ISP hex record 110 IAP error Status queis Sen Ses Gb OE etui rte odii oes que 115 IAP Tunelion sched ec atv Ri Pee Seed ee eee es 115 Flash User Configuration Byte 1 1 119 User sector Security Bytes SECO 7 120 Effects of Security Bits 1 or e i och sur ded ata bd e eoe e aide Iowa eed 120 Boot Vector BOOTVEG DER e nx bates 121 Boot Stat s BOO PS TAN eh iat eux RE IMPRESS dE qe LE 121 Irisiruction set summary serer arne ds etd 34 058889 Saw es ES Bla BEES es 123 2003 Dec 8 8 Philips Semiconductors General Description 1 General Description The P89LPC930 931 is a single chip microcontroller designed for applications demanding high integration low cost solutions over a wide range of performance requirements The P89LPC930 931 is based on a high performance processor architecture that executes instructions in two to four clocks six times the rate of standard 80C51 devices Many system level functions have been incorporated into the P89LPC930 931 in order to reduce component count board space and system cost Pin
135. or exceptions Must be cleared by software Figure 9 3 Serial Port Control register SCON 2003 Dec 8 56 Philips Semiconductors User s Manual Preliminary UART P89LPC930 931 SSTAT Address BAh 7 6 5 4 3 2 1 0 Not bit addressable DBMOD INTLO CIDIS DBISEL FE BR OE STINT Reset Source s Any reset Reset Value 00000000B BIT SYMBOL FUNCTION SSTAT 7 DBMOD Double buffering mode When set 1 enables double buffering Must be 0 for UART mode 0 In order to be compatible with existing 80C51 devices this bit is reset to 0 to disable double buffering SSTAT 6 INTLO Transmit interrupt position When cleared 0 the Tx interrupt is issued at the beginning of the stop bit When set 1 the Tx interrupt is issued at end of the stop bit Must be 0 for mode 0 Note that in the case of single buffering if the Tx interrupt occurs at the end of a STOP bit a gap may exist before the next start bit SSTAT 5 CIDIS Combined Interrupt Disable When set 1 Rx and Tx interrupts are separate When cleared 0 the UART uses a combined Tx Rx interrupt like a conventional 80C51 UART This bit is reset to 0 to select combined interrupts SSTAT 4 DBISEL Double buffering transmit interrupt select Used only if double buffering is enabled This bit controls the number of interrupts that can occur when double buffering is enabled When set one transmit interrupt is genera
136. ort pin P1 5 RST can only be an input and cannot be configured P1 2 SCL TO and P1 3 SDA INTO may only be configured to be either input only or open drain PxM1 y PxM2 y Port output mode 0 0 Quasi bidirectional 0 1 Push Pull 1 0 Input Only High Impedance 1 1 Open Drain Table 4 2 Port output configuration settings Quasi bidirectional output configuration Quasi bidirectional outputs can be used both as an input and output without the need to reconfigure the port This is possible because when the port outputs a logic high it is weakly driven allowing an external device to pull the pin low When the pin is driven low it is driven strongly and able to sink a large current There are three pull up transistors in the quasi bidirectional output that serve different purposes One of these pull ups called the very weak pull up is turned on whenever the port latch for the pin contains a logic 1 This very weak pull up sources a very small current that will pull the pin high if it is left floating A second pull up called the weak pull up is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level This pull up provides the primary source current for a quasi bidirectional pin that is outputting a 1 If this pin is pulled low by an external device the weak pull up turns off and only the very weak pull up remains on In order to pull the pin low under t
137. ounter operation input from TO input pin TMOD 1 0 TOM1 TOMO Mode Select for Timer 0 These bits are used with the TOM2 bit in the TAMOD register to determine the Timer 0 mode see Figure 7 2 Figure 7 1 Timer Counter Mode Control register TMOD 2003 Dec 8 43 Philips Semiconductors User s Manual Preliminary TIMERS 0 AND 1 P89LPC930 931 TAMOD 7 6 5 4 3 2 1 0 Address 8Fh T1M2 TOM2 Not bit addressable Reset Source s Any reset Reset Value BIT SYMBOL FUNCTION TAMOD 7 5 Reserved for future use Should not be set to 1 by user programs TAMOD 4 T1M2 Mode Select bit 2 for Timer 1 It is used with T1M1 and T1MO in the TMOD register to determine Timer 1 mode TAMOD 3 1 Reserved for future use Should not be set to 1 by user programs TAMOD 0 TOM2 Mode Select bit 2 for Timer 0 It is used with TOM1 and TOMO in the TMOD register to determine Timer 0 mode TnM2 TnMO Timer Mode 000 8048 Timer TLn serves as 5 bit prescaler 001 16 bit Timer Counter THn and TLn are cascaded there is no prescaler 010 8 bit auto reload Timer Counter THn holds a value which is loaded into TLn when it overflows 011 Timer 0 is a dual 8 bit Timer Counter in this mode TLO is an 8 bit Timer Counter controlled by the standard Timer 0 control bits THO is an 8 bit timer only controlled by the Timer 1 control bits
138. ransmission In this case the data currently being transmitted will continue to be transmitted but the new data i e the one causing the collision will be lost While write collision is detected for both a master or a slave it is uncommon for a master because the master has full control of the transfer in progress The slave however has no control over when the master will initiate a transfer and therefore collision can occur For receiving data received data is transferred into a parallel read data buffer so that the shift register is free to accept a second character However the received character must be read from the Data Register before the next character has been completely shifted in Otherwise the previous data is lost WCOL can be cleared in software by writing 1 to the bit DATA MODE Clock Phase Bit CPHA allows the user to set the edges for sampling and changing data The Clock Polarity bi CPOL allows the user to set the clock polarity Figures 11 8 11 11 show the different settings of Clock Phase bit CPHA 2003 Dec 8 86 Philips Semiconductors User s Manual Preliminary SERIAL PERIPHERAL INTERFACE SPI P89LPC930 931 Clock Cycle SPICLK CPOL 0 SPICLK CPOL 1 ins CUM ER EX GN m Em E um dE m GE SS if SSIG bit 0 Not defined Figure 11 8 SPI slave transfer format with
139. rdless of this bit 0 Not used Reserved for future use NOTE Brownout Detect Power down is located in PCON 5 Figure 5 2 Power Control register A PCONA 2003 Dec 8 39 Philips Semiconductors User s Manual Preliminary POWER MONITORING FUNCTIONS 890099 2003 Dec 8 40 Philips Semiconductors User s Manual Preliminary RESET P89LPC930 931 6 RESET The P1 5 RST pin can function as either an active low reset input or as a digital input P1 5 The RPE Reset Pin Enable bit in UCFG1 when set to 1 enables the external reset input function on P1 5 When cleared P1 5 may be used as an input pin NOTE During a power on sequence The RPE selection is overriden and this pin will always functions as a reset input An external circuit connected to this pin should not hold this pin low during a Power on sequence as this will keep the device in reset After power on this input will function either as an external reset input or as a digital input as defined by the RPE bit Only a power on reset will temporarily override the selection defined by RPE bit Other sources of reset will not override the RPE bit NOTE During a power cycle Vpp must fall below Vpog see DC electrical characteristics in the datasheet before pwoer is reapplied in order to ensure a power on reset Reset can be triggered from the following sources see Figure 6 1 External reset pin during power on or if user con
140. re 14 2 Watchdog Timer Control Register The number of watchdog clocks before timing out is calculated by the following equations tclks 2 5 PRE WDL 1 1 where PRE is the value of prescaler PRE2 PREO which can be the range 0 7 and WDL is the value of watchdog load register which can be the range of 0 255 The minimum number of tclks is tclks 2 5 0 00 1 1 33 The maximum number of tclks is tclks 2 5 7 255 1 1 1 048 577T 2003 Dec 8 97 Philips Semiconductors User s Manual Preliminary WATCHDOG TIMER P89LPC930 931 The following table show sample P89LPC930 931 timeout values Table 14 2 P89LPC930 931 Watchdog Timeout Values Timeout Period Watchdog Clock Source PRE2 PREO WDL in decimal in watchdog clock 499KHz Watchdog Oscillator Clock 12MHz CCLK 6MHz CCLK 2 cycles Nominal Watchdog Clock 0 33 82 5us 5 50us 000 255 8 193 20 5ms 1 37ms 0 65 162 5us 10 8us 001 255 16 385 41 0ms 2 73ms 0 129 322 5us 21 5us 010 255 32 769 81 9ms 5 46ms 0 257 642 5us 42 8us 011 255 65 537 163 8ms 10 9ms 0 513 1 28ms 85 5us 100 255 131 073 327 7ms 21 8ms 0 1 025 2 56ms 170 8us 101 255 262 145 655 4ms 43 7ms 0 2 049 5 12ms 341 5us 110 255 524 289 1 315 87 4ms 0 4097 10 2ms 682 8us 111 255 1 048 577 2 62s 174 8ms Watchdog Clock Source The watchdog timer system has an on chip 400KHz oscillator The watchdog timer can be cl
141. rmat of Slave Transmitter Mode 0 00 cc eee eee eee eee eens 72 I2C bus serial interface block diagram 73 Master Transmitter Mode x XA a ear eek es oa Oran T 74 Master Receiver Mode ve Teretere lt GU IR EE ea RR E RR 75 Slave Receiver Mode 76 Slave Transmitter MIOGB sous n Co eR OE OS Pa shal O alr EOE 79 SPI blocek diagram Side oe Bb nb OIL GEL dee eee RT nb G big bathe eos 81 SPi Controlitegisters ffs ln ha ws dew Set ae d bake bce EE 82 SPI Status register definition veu eur Rib eae IE E Ee 83 SP Dalal vto Se WO gef EMT uud 284 8 Sade Be Ge PPE Sak oH 83 SPI single master single slave 83 SPI dual device configuration where either can be a master oraslave 84 SPI single master multiple slaves configuration 84 SPI master and slave 85 SPI slave transfer format with 20 87 SPI slave transfer format with CPHA T 35925 X PREPARES ERGO Ye EE 87 SPI master transfer format with 0 88 SPI master transfer format with 1 202000 88 Comparator control register
142. rs which do not make use of this feature 2003 Dec 8 63 Philips Semiconductors User s Manual Preliminary UART P89LPC930 931 2003 Dec 8 64 Philips Semiconductors User s Manual Preliminary 2 INTERFACE P89LPC930 931 10 I2C INTERFACE The I C bus uses two wires serial clock SCL and serial data SDA to transfer information between devices connected to the bus and has the following features Bidirectional data transfer between masters and slaves Multimaster bus no central master Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allows devices with different bit rates to communicate via one serial bus Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer The 2 5 may be used for test and diagnostic purposes A typical 12C bus configuration is shown in Figure 1 Depending on the state of the direction bit R W two types of data transfers are possible on the 12C bus Data transfer from a master transmitter to a slave receiver The first byte transmitted by the master is the slave address Next follows a number of data bytes The slave returns an acknowledge bit after each received byte Data transfer from a slave transmitter to a master receiver The first byte the slave address is transmitted by the master The slave then returns an acknowledge bit Next follo
143. rupt enable be set BOF can be cleared by writing 0 to the bit detect generates 0 X Both brownout reset and interrupt disabled Vpp m operating range is 2 4 V 3 6 V However BOF interrupt RSTSRC 5 will be set when Vpp falls to the Brownout X 0 Detection trip point BOF can be cleared by writing 0 to the bit Table 5 1 Brownout options Power on Detection The Power On Detect has a function similar to the Brownout Detect but is designed to work as power initially comes up before the power supply voltage reaches a level where the Brownout Detect can function The POF flag RSTSRC 4 is set to indicate an initial power on condition The POF flag will remain set until cleared by software by writing 0 to the bit Note that if BOE UCFG1 5 is programmed BOF RSTSRC 5 will be set when POF is set If BOE is unprogrammed BOF is meaningless Power reduction modes The P89LPC930 931 supports three different power reduction modes as determined by SFR bits PCON 1 0 see Table 5 2 2003 Dec 8 36 Philips Semiconductors POWER MONITORING FUNCTIONS peel 09 User s Manual Preliminary PMOD1 PCON 1 0 PMODO PCON 0 0 Description Normal mode default no power reduction 0 Idle mode The Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated Any enabled interrupt source or reset may term
144. rupt 1 edge is detected Cleared by hardware when the interrupt is processed or by software TCON 2 IT1 Interrupt 1 Type control bit Set cleared by software to specify falling edge low level triggered external interrupts TCON 1 IEO Interrupt 0 Edge flag Set by hardware when external interrupt 0 edge is detected Cleared by hardware when the interrupt is processed or by software TCON O ITO Interrupt O Type control bit Set cleared by software to specify falling edge low level triggered external interrupts Figure 7 3 Timer Counter Control register TCON Overflow PCLK C T 0 E d Tn Interrupt 5 bits 8 bits Tn Pin e C T 24 Control TRn Gate o o _ Tn Pin INTR Pin ENTn Figure 7 4 Timer Counter 0 or 1 in Mode 0 13 bit counter 2003 Dec 8 46 Philips Se miconductors User s Manual Preliminary TIMERS 0 AND 1 P89LPC930 931 Overflow PCLK C T 0 8 bits 8 bits MEUR Tn Pin e C T 1 Control TRn Gate Tn Pin INTn Pin Figure 7 5 Timer Counter 0 or 1 in Mode 1 16 bit counter PCLK Ov rilow TFn gt Interrupt Tn Pin CIT 4 Control TRn Gate j o Tn Pin INTn Pin ENTn Figure 7 6 Timer Counter 0 or 1 in Mode 2 8 bit auto reload PCLK C T 0 Re m TLO Overflow 8 bits TFO We Interrupt TO Pin e C T 21 Control Toggle na e 1
145. s 96h Not bit addressable Reset Source s Power up only ENCLK TRIM 5 TRIM 4 TRIM 3 TRIM 2 TRIM 1 TRIM O Reset Value On power up reset ENCLK 0 and TRIM 5 0 are loaded with the factory programmed value BIT SYMBOL FUNCTION TRIM 7 Reserved TRIM 6 ENCLK When ENCLK 1 CCLK 2 is output on the XTAL2 pin P3 0 provided that the crystal oscillator is not being used When ENCLK 0 no clock output is enabled TRIM 5 0 Trim value Note on reset the TRIM SFR is initialized with a factory preprogrammed value When setting or clearing the ENCLK bit the user should retain the contents of bits 5 0 of the TRIM register This can be done by reading the contents of the TRIM register into the ACC for example modifying bit 6 and writing this result back into the TRIM register Alternatively the ANL direct or ORL direct instructions can be used to clear or set bit 6 of the TRIM register Figure 2 1 On chip RC oscillator TRIM register Watchdog oscillator option The watchdog has a separate oscillator which has a frequency of 400 kHz This oscillator can be used to save power when a high clock frequency is not needed External clock input option In this configuration the processor clock is derived from an external source driving the XTAL1 P3 1 pin The rate may be from 0 Hz up to 12 MHz The XTAL2 P3 0 pin may be used as a standard port pin or a clock output 2003
146. s CMP1 and 2 89 Comparator input and output connections 90 Comparator configurations 91 Keypad Pattern register scsi n Kcu Ta EO ES SUED 93 Keypad Control register xx rete nce it eee be Ue ee eter eto ea e 93 Keypad Interrupt Mask register 94 Watchdog timer 95 VWatelidog PIescalgr tat costo oun da aN a ddagger eg mia inue E pote els e 96 Watchdog Timer Control 97 P89LPC930 931 Watchdog Timeout 98 Watchdog Timer in Watchdog Mode WDTE 1 99 Watchdog Timer in Timer Mode WDTE 0 100 AUXRT register 25 56 Me Sova mek Bana Pons 101 Flash Memory Control 5 105 Assembly language routine to erase program all or part of a 106 C language routine to erase program all or part of a 107 2003 Dec 8 7 Philips Semiconductors User Manual Subject to Change List of Figures P89LPC930 931 Boot Loader Address and Default B
147. s 2 and 3 Reception is the same as in Mode 1 The signal to load SBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated a RI 0 and b Either SM2 0 or the received 9th data bit 1 If either of these conditions is not met the received frame is lost and RI is not set If both conditions are met the received 9th data bit goes into RB8 and the first 8 data bits go into SBUF TX Clock Write to SBUF INTEO 0 INTLO 1 rx clock D m nm m nm m nm m n m m m 16 Reset gt Start BitK_DO X 01 X D2 X D3 X D4 X 05 X D6 X D7 X Stop Bit s _ n mmn n RI x SMODO 0 SMODO 1 Figure 9 7 Serial Port Mode 2 or 3 only single transmit buffering case is shown Transmit Receive Framing Error and RI in Modes 2 and 3 with SM2 1 If SM2 1 in modes 2 and 3 RI and FE behaves as in the following table PCON 6 Mode SMODO RB8 RI FE 0 No RI when RB8 0 Occurs during STOP bit 2 0 Similar to Figure 9 7 with SMODO 0 RI 1 occurs during RB8 one bit before FE Occurs during STOP bit 0 No RI when RB8 0 Will NOT occur 3 1 Similar to Figure 9 7 with SMODO 1 RI 1 occurs during STOP bit Occurs during STOP bit Table 9 3 FE and RI when SM2 1 in Modes 2 and 3 Break Detect A break is d
148. s as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to the section on I O port configuration and the DC Electrical Characteristics for details All pins have Schmitt triggered inputs Port 3 also provides various special functions as described below 9 yo P3 0 Port 3 bit 0 XTAL2 Output from the oscillator amplifier when a crystal oscillator option is selected via the FLASH configuration CLKOUTCPU clock divided by 2 when enabled via SFR bit ENCLK TRIM 6 It can be used if the CPU clock is the internal RC oscillator watchdog oscillator or external clock input except when XTAL1 XTAL2 are used to generate clock source for the Real Time clock system timer 8 P3 1 Port 3 bit 1 XTAL4 Input to the oscillator circuit and internal clock generator circuits when selected via the FLASH configuration It can be a port pin if internal RC oscillator or watchdog oscillator is used as the CPU clock source AND if XTAL1 XTAL2 are not used to generate the clock for the Real Time clock system timer Vss 7 Ground 0 V reference Vpp 21 Power Supply This is the power supply voltage for normal operation as well as Idle and Power down modes 2003 Dec 8 14 Philips Semiconductors User s Manual Preliminary General Description P89LPC930 931 Special Function Registers Note Special Function Registers SFRs accesses are restricted in the following ways 1
149. s information returned is shown in Table 16 3 If the application permits interrupts during erasing programming or CRC cycles the user code should check the carry flag after each erase programming or CRC operation to see if an error occurred If the operation was aborted the user s code will need to repeat the operation 2003 Dec 8 114 Philips Semiconductors User s Manual Preliminary FLASH MEMORY P89LPC930 931 Description Operation Interrupted Indicates that an operation was aborted due to an interrupt occuring during a program or erase cycle Security Violation Set if program or erase operation fails due to security settings Cycle is aborted Memory contents are unchanged CRC output is invalid High Voltage Error Set if error detected in high voltage generation circuits Cycle is aborted Memory contents may be corrupted Verify error Set during IAP programming of user code if the contents of the programmed address does not agree with the intended programmed value IAP uses the MOVC instruction to perform this verify Attempts to program user code that is MOVC protected can be programmed but will generate this error after the programming cycle has been completed unused reads asa 1 unused reads as 1 unused reads asa 1 unused reads as a Table 16 3 IAP error status Table 16 4 IAP function calls IAP function IAP call parameters Input paramet
150. s of shifting a byte Thus this register should only be accessed when the SI bit is set Data in I2DAT remains stable as long as the SI bit is set Data in I2DAT is always shifted from right to left the first bit to be transmitted is the MSB bit 7 and after a byte has been received the first bit of received data is located at the MSB of I2DAT I2DAT Address DAH 7 6 5 4 3 2 1 0 Not bit addressable I2DAT 7 I2DAT 6 I2DAT 5 I2DATA I2DAT3 I2DAT2 I2DAT 4 I2DAT O Reset Source s Any reset Reset Value 00000000B Figure 2 2 Data register Slave Address register I2ADR register is readable and writable and is only used when the 12C interface is set to slave mode In master mode this register has no effect The LSB of I2ADR is general call bit When this bit is set the general call address 00h is recognized I2ADR Address DBH Not bit addressable E z x d Reset Sourbe g UAnvitesel IDADR 6 I2ADR 5 I2ADRA I2ADR3 I2ADR2 I2ADR 1 I2ADR O GC Reset Value 00000000B BIT SYMBOL FUNCTION I2ADRT 1 I2ADR 6 0 7 bit own slave address When in master mode the contents of this register has no effect I2ADR7 0 GC General call bit When set the general call address 00H is recognized otherwise it is ignored Figure 3 I C Slave Address register Control register The CPU can read and write this register There
151. s usages and directions for the modes Table 11 1 SPI master and slave selection SPEN SSIG FT MSTR SPCTL S9 spert Masteror Miso mosi SPICE Remarks Pin Slave Mode K 6 7 4 0 X 41 X SPI p2 31 p22 pas SPI disabled P2 2 P2 3 P24 P2 5 Disabled are used as port pins 1 0 0 0 Slave output input input Selected as slave Not selected MISO is high 8 1 9 slave Hiz input input impedance to avoid bus contention P2 4 SS is configured as an input or quasi bidirectional pin SSIG is 0 Selected externally as slave if SS is 9 p TEZO Save output input input selected and is driven low The MSTR bit will be cleared to 0 when SS becomes low MOSI and SPICLK are at high impedance to avoid bus contention when the MAster is idle The Master idle Hi Z Hi Z application must pull up or pull 1 0 1 1 input down SPICLK depending on CPOL SPCTL 3 to avoid a floating SPICLK Master cumit MOSI and SPICLK are push pull active when the Master is active 1 1 P2 41 0 Slave output input input 1 1 2 4 1 Master input output output 1 Selected as a port function E 2 The MSTR bit changes to 0 automatically when SS becomes low in input mode and SSIG is O ADDITIONAL CONSIDERATIONS FOR A SLAVE When CPHA equals zero SSIG must be 0 and the SS pin must be negated and reasserted between
152. sector x are erased by either a sector erase command ISP IAP commercial programmer or a global erase command commercial programmer MOVC Disable Disables the MOVC command for sector x Any MOVC that attempts to read a byte in a MOVC protected sector will return invalid data This bit can only be erased when sector x is erased SPEDISx MOVCDISx Figure 6 User sector Security Bytes SECO SEC7 Effects on Programming 0 0 None Security violation flag set for sector CRC calculation for the specific sector Security violation flag set for global CRC calculation if any MOVCDISx bit is set Cycle aborted Memory contents unchanged CRC invalid Program erase commands will not result in a security violation Security violation flag set for program commands or an erase page command Cycle aborted Memory contents unchanged Sector erase and global erase are allowed Security violation flag set for program or erase commands Cycle aborted Memory contents unchanged Global erase is allowed Table 16 5 Effects of Security Bits 2003 Dec 8 120 Philips Semiconductors User s Manual Preliminary FLASH MEMORY P89LPC930 931 Boot Vector BOOTVEC Address xxxxh Factory default value 1Fh 7 6 5 4 3 2 1 0 BOOTVA BOOTV3 BOOTV2 BOOTV1 BOOTVO BIT SYMBOL FUNCTION BOOTVEC 7 5 Reserved s
153. sed to generate interrupts the current is reduced to approximately 50uA Whenever the WDT underflows the device will wake up 2003 Dec 8 100 Philips Semiconductors User s Manual Preliminary ADDITIONAL FEATURES P89LPC930 931 15 ADDITIONAL FEATURES The AUXR1 register contains several special purpose control bits that relate to several chip features AUXR1 is described in Figure 15 1 AUXR1 7 6 5 4 3 2 1 0 Address A2h CLKLP EBRR ENT1 ENTO SRST 0 DPS Not bit addressable Reset Source s Any reset Reset Value 000000x0B BIT SYMBOL FUNCTION AUXR1 7 CLKLP Clock Low Power Select When set reduces power consumption in the clock circuits Can be used when the clock frequency is 8 MHz or less After reset this bit is cleared to support up to 12 MHz operation AUXR1 6 EBRR UART Break Detect Reset Enable If 1 UART Break Detect will cause a chip reset and force the device into ISP mode AUXR1 5 ENT1 When set the 7 pin is toggled whenever Timer1 overflows The output frequency is therefore one half of the Timer1 overflow rate Refer to the Timer Counters section for details AUXR1 4 ENTO When set the P1 2 pin is toggled whenever TimerO overflows The output frequency is therefore one half of the TimerO overflow rate Refer to the Timer Counters section for details AUXR1 3 SRST Software Reset When set by software resets the P89LPC930 931 as if a hardware reset occurred AUXR1
154. so need to be convenient to use In order to set the flag and and cause an interrupt the pattern on Port 0 must be held longer than 6 CCLKs KBPATN Address 93h Not bit addressable Reset Source s Any reset Reset Value 11111111B BIT SYMBOL FUNCTION KBPATN 7 0 Pattern bit 7 bit O 7 6 5 4 3 2 1 0 KBPATN 7 KBPATN 6 KBPATN 5 KBPATN 4 KBPATN 3 KBPATN 2 KBPATN 1 KBPATN O Figure 13 1 Keypad Pattern register KBCON Address 94h Not bit addressable Reset Source s Any reset 7 6 5 4 3 2 1 0 PATN SEL KBIF Reset Value xxxxxx00B BIT SYMBOL FUNCTION KBCON 7 2 Reserved KBCON 1 PATN SEL Pattern Matching Polarity selection When set Port 0 has to be equal to the user defined Pattern in KBPATN to generate the interrupt When clear Port 0 has to be not equal to the value of KBPATN register to generate the interrupt KBCON O KBIF Keypad Interrupt Flag Set when Port 0 matches user defined conditions specified in KBPATN KBMASK and PATN SEL Needs to be cleared by software by writing O Figure 13 2 Keypad Control register 2003 Dec 8 93 Philips Semiconductors User s Manual Preliminary KEYPAD INTERRUPT ad KBMASK Z Address 86h Not bit addressable Reset Source s Any reset Reset Value 00000000B KBMASK 7 KBMASK 6 KBMASK 5 KBMASK
155. ss and the general call address If one of these addresses is detected an interrupt is requested When the microcontrollers wishes to become the bus master the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted If bus arbitration is lost in the master mode I C switches to the slave mode immediately and can detect its own slave address in the same serial transfer 2003 Dec 8 71 User s Manual Preliminary Philips Semiconductors 2 INTERFACE P89LPC930 931 m S Slave Address R DATA A DATA A P P Data Transferred ate n Bytes Acknowledge 1 Read From Master to Slave From Slave to Master Acknowledge SDA low Not Acknowledge SDA high S START condition P STOP Condition 2003 Dec 8 Figure 11 Format of Slave Transmitter Mode 72 Philips Semiconductors User s Manual Preliminary 2 INTERFACE P89LPC930 931 wa Poe a 1 P1 3 Address Register I2ADR Input Comparator Filter Shift Register P1 3 SDA I2DAT 2 Bit Counter Arbitration amp Input Sync Logic ae P1 2 SCL Filter Control Logic Interrupt Internal Bus Serial Clock Generator Timer 1 i eom Overflow j I2CON Control Register amp SCL Duty ERN ES EIS I2SCLH Cycle Registers I2SCLL
156. ss or the Broadcast address The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses All of the slaves may be contacted by using the Broadcast address Two special Function Registers are used to define the slave s address SADDR and the address mask SADEN SADEN is used to define which bits in the SADDR are to be used and which bits are don t care The SADEN mask can be logically ANDed with the SADDR to create the Given address which the master will use for addressing each of the slaves Use of the Given address allows multiple slaves to be recognized while excluding others The following examples will help to show the versatility of this scheme Slave 0 SADDR 1100 0000 SADEN 1111 1101 Given 1100 00X0 Slave 1 SADDR 1100 0000 SADEN 1111 1110 Given 1100 000X In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves Slave 0 requires a 0 in bit O and it ignores bit 1 Slave 1 requires a 0 in bit 1 and bit 0 is ignored A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1 A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0 Both slaves can be selected at the same time by an ad
157. sult is unpredictable yes pev 3 Receive transmit baud rate for UART 0 0 X X CCLK 16 0 0 CCLK 256 TH1 64 0 1 1 0 CCLK 256 TH1 32 X 1 CCLK BRGR1 BRGRO 16 0 X CCLK 32 i 1 X CCLK 16 0 0 CCLK 256 TH1 64 1 1 1 0 CCLK 256 TH1 32 X 1 CCLK BRGR1 BRGRO 16 Table 9 2 Baud rate generation for UART 2003 Dec 8 54 Philips Semiconductors User s Manual Preliminary UART P89LPC930 931 BRGCON Address BDh 7 6 5 4 3 2 1 0 Not bit addressable Reset Source s Any reset Reset Value xxxxxx00B BIT SYMBOL BRGCON 7 2 BRGCON 1 SBRGS BRGCON O BRGEN z SBRGS BRGEN FUNCTION Reserved for future use Should not be set to 1 by user programs Select Baud Rate Generator as the source for baud rates to UART in modes 1 amp 3 see Table 9 2 for details Baud Rate Generator Enable Enables the baud rate generator BRGR1 and BRGRO can only be written when BRGEN 0 Figure 9 1 BRGCON register Timer 1 Overflow PCLK based Baud Rate Generator CCLK based SMOD1 1 SBRGS 0 Baud Rate Modes 1 and 3 SMOD1 0 y SBRGS 1 Framing Error Figure 9 2 Baud rate generation for UART Modes 1 3 A Framing error occurs when the stop bit is sensed as a logic 0 A Framing error is reported in the status register SSTAT In addition if SMODO PCON 6 is 1 fram
158. t 1 to enable I C function AA bit must be set 1 to acknowledge its own slave address or the general call address STA STO and SI are cleared to 0 After I2ADR and I2CON are initialized the interface waits until it is addressed by its own address or general address followed by the data direction bit which is O W If the direction bit is 1 R it will enter Slave Transmitter Mode After the address and the direction bit have been received the SI bit is set and a valid status code can be read from the Status Register I2STAT Refer to Table 4 for the status codes and actions S Slave Address W A DATA A DATA A P RS Data Transferred Ui n Bytes Acknowledge 1 Read A Acknowledge SDA low From Master to Slave Not Acknowledge SDA high From Slave to Master S START condition P STOP Condition RS Repeated START condition Figure 10 Format of Slave Receiver Mode Slave Transmitter Mode The first byte is received and handled as in the Slave Receiver Mode However in this mode the direction bit will indicate that the transfer direction is reversed Serial data is transmitted via P1 3 SDA while the serial clock is input through P1 2 SCL START and STOP conditions are recognized as the beginning and end of a serial transfer In a given application 2 may operate as master and as a slave In the slave mode the 12C hardware looks for its own slave addre
159. t modes but provides a continuous strong pull up when the port latch contains a logic 1 The push pull mode may be used when more source current is needed from a port output The push pull port configuration is shown in Figure 4 4 A push pull port pin has a Schmitt triggered input that also has a glitch suppression circuit Please refer to the P89LPC930 931 datasheet AC Electrical Characteristics for glitch filter specifications Vpp strong port latch data gt o input data t d 1 glitch rejection Figure 4 4 Push pull output Port 0 analog functions The P89LPC930 931 incorporates two Analog Comparators In order to give the best analog performance and minimize power consumption pins that are being used for analog functions must have both the digital outputs and digital inputs disabled Digital outputs are disabled by putting the port pins into the input only mode as described in the Port Configurations section see Table 4 2 Digital inputs on Port 0 may be disabled through the use of the PTOAD register Bits 1 through 5 in this register correspond to pins 1 through 5 of Port 0 respectively Setting the corresponding bit in PTOAD disables that pin s digital input Port bits that have their digital inputs disabled will be read as 0 by any instruction that accesses the port On any reset PTOAD bits 1 through 5 default to
160. t from the LPC76x series of devices After power up all I O pins except P1 5 may be configured by software Pin P1 5 is input only Pins P1 2 and P1 3 are configurable for either input only or open drain Every output on the P89LPC930 931 has been designed to sink typical LED drive current However there is a maximum total output current for all ports which must not be exceeded Please refer to the P89LPC930 931 Datasheet for detailed specifications 2003 Dec 8 Philips Semiconductors User s Manual Preliminary P89LPC930 931 I O PORTS All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals The slew rate is factory set to approximately 10 ns rise and fall times 33 2003 Dec 8 Philips Semiconductors User s Manual Preliminary PORTS P89LPC930 931 2003 Dec 8 34 Philips Semiconductors User s Manual Preliminary POWER MONITORING FUNCTIONS PORER SAIN 5 POWER MONITORING FUNCTIONS The P89LPC930 931 incorporates power monitoring functions designed to prevent incorrect operation during initial power on and power loss or reduction during operation This is accomplished with two hardware functions Power on Detect and Brownout Detect Brownout Detection The Brownout Detect function determines if the power supply voltage drops below a certain level The default operation for a Brownout Detection is to caus
161. ted after each character written to SBUF and there is also one more transmit interrupt generated at the beginning INTLO 0 or the end INTLO 1 of the STOP bit of the last character sent i e no more data in buffer This last interrupt can be used to indicate that all transmit operations are over When cleared 0 only one transmit interrupt is generated per character written to SBUF Must be 0 when double buffering is disabled Note that except for the first character written when buffer is empty the location of the transmit interrupt is determined by INTLO When the first character is written the transmit interrupt is generated immediately after SBUF is written SSTAT 3 FE Framing error flag is set when the receiver fails to see a valid STOP bit at the end of the frame Cleared by software SSTAT 2 BR Break Detect flag A break is detected when any 11 consecutive bits are sensed low Cleared by software SSTAT 1 OE Overrun Error flag is set if a new character is received in the receiver buffer while it is still full before the software has read the previous character from the buffer i e when bit 8 of a new byte is received while RI in SCON is still set Cleared by software SSTAT O STINT Status Interrupt Enable When set 1 FE BR or OE can causean interrupt The interrupt used vector address 0023h is shared with RI CIDIS 1 or the combined TI RI CIDIS 0 When cleared 0 BR OE cannot cause an interrupt
162. the transition is detected and that interrupt request flag IEn is set IEn is automatically cleared by the CPU when the service routine is called If the external interrupt is level triggered the external source must hold the request active until the requested interrupt is generated If the external interrupt is still asserted when the interrupt service routine is completed another interrupt will be generated It is not necessary to clear the interrupt flag IEn when the interrupt is level sensitive it simply tracks the input pin level If an external interrupt is enabled when the P89LPC930 931 is put into Power down or Idle mode the interrupt occurance will cause the processor to wake up and resume operation Refer to the section on Power Reduction Modes for details 2003 Dec 8 26 Philips Semiconductors User s Manual Preliminary INTERRUPTS P89LPC930 931 External Interrupt pin glitch suppression All of the P89LPC930 931 1 0 pins except SDA INTO P1 3 and SCL TO P1 2 have glitch suppression circuits to reject short glitches please refer to the P89LPC930 931 datasheet AC Electrical Characteristics for glitch filter specifications Therefore INT1 has glitch suppression while INTO does not IEO EX1 BOPD EBO RTCF KBIF Wakeup if in em amp J Power down RTCCON 1 gt ew CMF2 5 CMF1 EC EA IEO 7 TF1 ET TI amp ES ES TI LF
163. urrent count terminates the contents of RTCH and RTCL will be loaded into the counter and the new count will begin An immediate reload of the counter can be forced by clearing the RTCEN bit to 0 and then setting it back to 1 Real time Clock source RTCS1 0 RTCCON 6 5 are used to select the clock source for the RTC if either the Internal RC oscillator or the internal WD oscillator is used as the CPU clock If the internal crystal oscillator or the external clock input on XTAL 1 is used as the CPU clock then the RTC will use CCLK as its clock source Changing RTCS1 0 RTCS1 0 cannot be changed if the RTC is currently enabled RTCCON 0 71 Setting RTCEN and updating RTCS1 0 may be done in a single write to RTCCON However if RTCEN 1 this bit must first be cleared before updating RTCS1 0 2003 Dec 8 49 Philips Semiconductors User s Manual Preliminary REAL TIME CLOCK SYSTEM TIMER P89LPC930 931 Real time Clock interrupt wake up If ERTC RTCCON 1 EWDRT IEN1 0 6 and EA IENO 7 are set to 1 RTCF can be used as an interrupt source This interrupt vector is shared with the watchdog timer It can also be a source to wake up the device Reset sources affecting the Real time Clock Only power on reset will reset the Real time Clock and its associated SFRs to their default state Table 8 1 Real time Clock System Timer clock sources FOSC2 FOSC1 FOSC
164. value If the SPI is configured as a master i e SPCTL 4 1 and P2 4 is configured as an output via the P2M1 4 and P2M2 4 SFR bits Ifthe SS pin is ignored i e SSIG SPCTL 7 bit 1 this pin is configured for port functions Note that even if the SPI is configured as master MSTR 1 it can still converted to a slave by driving the SS pin low if P2 4 is configured as input and SSIG 0 Should this happen the SPIF bit SPSTAT 7 will be set see section Mode change on SS Typical connections are shown in Figures 11 5 11 7 The 89LPC913 does not have the slave select pin SS The SPI interface is set to Master mode and an I O pin may be used to implement the SS function Typical connections are shown in Figure 11 5 and Figure 11 7 2003 Dec 8 81 Philips Semiconductors User s Manual Preliminary SERIAL PERIPHERAL INTERFACE SPI P89LPC930 931 SPCTL Address E2h Not bit addressable Reset Source s Any reset Reset Value 00000100B BIT SYMBOL SPCTL 7 SSIG SPCTL 6 SPEN SPCTL 5 DORD SPCTL 4 MSTR SPCTL 3 CPOL SPCTL 2 CPHA SPCTL 1 0 SPR1 SPRO SPR1 SPRO SSIG SPEN DORD CPOL SPR1 SPRO FUNCTION SS IGnore If set 1 MSTR bit 4 decides whether the device is a master or slave If cleared 0 the SS pin decides whether the device is master or slave The SS pin can be used as a port pin see Table 11 1 SPI Enabl
165. vels IPOH IP1 IP1H Every interrupt has two bits in IPx and IPXH x 0 1 and can therefore be assigned to one of four levels as shown in Table 3 1 Priority bits Interrupt priority level IPxH IPx 0 0 Level 0 lowest priority 0 1 Level 1 1 0 Level 2 1 1 Level 3 highest priority Table 3 1 Interrupt priority level 2003 Dec 8 25 Philips Semiconductors User s Manual Preliminary INTERRUPTS P89LPC930 931 Description Interrupt Vector Interrupt Interrupt Arbitration Power down flag bit s address enable bit s priority ranking wakeup External Interrupt 0 IEO 0003h IENO O IPOH O 1 highest Yes Timer 0 Interrupt TFO 000Bh ETO IENO 1 IPOH 1 IPO 1 4 No External Interrupt 1 IE1 0013h EX1 IENO 2 IPOH 2 IPO 2 7 Yes Timer 1 Interrupt TF1 001Bh ET1 IENO 3 IPOH 3 IPO 3 10 No ais ae e ae 0023h ENS IPOH 4 IPO 4 13 No Brownout Detect BOF 002Bh EBO IENO 5 IPOH 5 IPO 5 2 Yes eae i peal pesada 0053h ERO IPOH 6 IPO 6 3 Yes Interrupt SI 0033h EI2C IEN1 0 IP1H 0 IP1 0 5 No KBI Interrupt KBIF 003Bh EKBI IEN1 1 IP1H 1 IP1 1 8 Yes Comparators 1 2 interrupt CMF1 CMF2 0043h EC IEN1 2 IP1H 2 IP1 2 11 Yes SPI interrupt SPIF 004Bh ESP IEN1 3 IP1H 3 IP1 3 14 No Reserved 0063h EN1 5 IP1H 5 IP1 5 9 Yes Serial Port Tx TI 006Bh EST IEN1 6 P1H 6 IP1 6 12 No 1 SSTAT 5 0 selects combi
166. with the LOAD command An assembly language routine to load the page register and perform an erase program operation is shown in Figure 16 2 A similar C language routine is shown in Figure 16 3 FMCON 7 6 5 4 3 2 1 0 Address E4h j _ HVA HVE SV Ol Not bit addressable Reset Source s Any reset Reset Value BIT SYMBOL FUNCTION FMCON 7 4 Reserved FMCON 3 HVA High voltage abort Set if either an interrupt or a brown out is detected during a program or erase cycle Also set if the brown out detector is disabled at the start of a program or erase cycle FMCON 2 HVE High voltage error Set when an error occurs in the high voltage generator FMCON 1 SV Security violation Set when an attempt is made to program erase or CRC a secured sector or page FMCON O Ol Operation interrupted Set when cycle aborted due to an interrupt or reset Figure 16 1 Flash Memory Control Register 2003 Dec 8 105 Philips Semiconductors User s Manual Preliminary FLASH MEMORY P89LPC930 931 Inputs RE R3 number of bytes to program byte R4 page address MSB byte EAS R5 page address LSB byte m PN R7 pointer to data buffer in RAM byte Outputs 7 status byte as C clear on no error set on error EQU 00H EP EQU 68H PGM USER OV FMCON f LOAD load command
167. ws the data bytes transmitted by the slave to the master The master returns an acknowledge bit after all received bytes other than the last byte At the end of the last received byte a not acknowledge is returned The master device generates all of the serial clock pulses and the START and STOP conditions A transfer is ended with a STOP condition or with a repeated START condition Since a repeated START condition is also the beginning of the next serial transfer the I C bus will not be released The P89LPC930 931 device provides a byte oriented interface It has four operation modes Master Transmitter Mode Master Receiver Mode Slave Transmitter Mode and Slave Receiver Mode SDA I2C bus SCL P1 3 SDA P1 2 SCL Other Device with 12 Other Device with 2 P89LPC930 931 Interface Interface Figure 1 I C bus configuration The P89LPC930 931 CPU interfaces with the I C bus through six Special Function Registers SFRs I2CON Control Register I2DAT 2 Data Register 25 2 Status Register IZADR 2 Slave Address Register 25 SCL Duty Cycle Register High Byte and I2SCLL SCL Duty Cycle Register Low Byte 2003 Dec 8 65 Philips Semiconductors User s Manual Preliminary 2 INTERFACE P89LPC930 931 Data register I2DAT register contains the data to be transmitted or the data received The CPU can read and write to this 8 bit register while itis not in the proces

P89LPC930/931 8-bit microcontroller with two-clock core 4 KB

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