Home

T-Engine SH7760 Development Kit User Manual

Contents

1. 1 2 4 5 6 7 CPU BOARD INTERFACE CONNECTOR 2 2 A250 202 36 pas 71 CTS amp 1 cis 5 7 107 Duc 38 psi 202 EPROMCE 198 ASEMDO 39 ACC a 19 GND 9 m 5 4 19 GND 41 055 287 m 1 ARWR 207 TNS 112 rus ABS g 207 TRST 113 79 2 7 TDI 114 45 27 TDO 15 46 2 C32 CA 81 27 ASEBRKAK 116 ASEBRKAK 47 82 117 284 m WEO sven m 33VSB 7 m
2. 78 LOL gt 96 gt CLS 8896 7 9L LL 9L QV CN2 T AKA MAKARANI KAKA 40 1 1 Uu U N z CN11 IICN8 CMT 5 gt Y Y y Y Th H z CN10 5 896 HCANO m EA 5 CN9 CE CN HCAN1 xd x e En Ole M eo m o N NIN o O o 1 alia 00 St ooo 2 15 40 un TeTelerererereTererererer e N 519191919191919191969 lt VV Y V PO NX 9L OL 8L 7 88 66 e 5 9609 GEQ lt lt 99 cS 96 gt LOL GS6 E6 lt lt 9609
3. 75 gt 3 69 3 35 2 gt gt 63 57 un 375 15 11 7 ENT 2 m m 2 e 15 l1 543 gt 4 2 Q 1 N HL ex CN3 Il gt 21 e VV RE Bs 4 S ups x E ph N id 35 4 NU 5 oo CN13 un A Ie 1 Juge E pec z cos 1 7 al D di nn Ni Mee 1042 7 gt mx 29 N 4 15 8281 37 5 10 9 72 25 44 23 44 gt lt 72 MS7760DBG01 2 MS7760DBG01 1
4. 1 2 3 4 5 7 8 PC CARD I F USB I F amp LCD I F SIM CARD 6c4 0 15 0 52 CN3 35 GND 36 2 2 2 42 37 on 3 8 2 8 5 KEY INO 3 KEY INO PDi2 38 4 E 4 828605 KEY INi KEY Epis 39 os 5 8 2 8 5 KEY 5 KEY 40 1A6 LCDD 15 0 6 8F28 C5 KEY INA KEY IN3 6 04 DIS 41 7 8IF2 8 C5 KEY 7 KEY INA 42 n 8 5 KEY 8 KEY 6 04 POE 43 9 8 5 9 KEY OUTI 44 8 5 KEY OUT2 10 KEv 00 2 45 uou 4 47 4 PAD CS 13 PAD A19 48 Tao 8 2 8 2 14 PAD 6 4 PWE 49 os SIEZSICZBEAB ATSICO 8 TXD1 15 PAD DIN eE 50 Lcops 16 Heos BETBCZBEABIAT 1 16 PAD DOUT 6 4 6 87 7 83 CARD m 6 4 6 87 7 82 51 wc LCDD9 1 8 E7 8 B7 8 E4 8 A7 9 C2 H8_SCK1 17 PAD CLK 6 7 7 83 CARD VPP 6 C7 7 B2 52 303 RSTI 18 RESET 100010 18 53 19 cos 8 2802 LCD FLON 19 Lcb 54 20 8E28 D2 LCD PWRDY 2 icp pwrbv pam ss 21 Ll LCDDi3 21 P 56 LCD13 2
5. 1 2 5 1 5 6 7 8 CPLD AEG 5 025 2 6 2 ADSO 01 0 VAZAESSIC2S ASC2 a aN aN m Uti un un 01310 1042 un un 100 88 228 1048 _ gt ________ 6 1096 10144 P4 4 101 oa S 3 E6 1097 10145 6 4 AN 55 5 gt 5 gt md 55 jog 7 a 655 1050 6 1098 10146 vcco 294 Bsa 91 51 81 4 2 9 cu L5 D11 al OT 9 a9 a 7 5 CS 1051 48 ____ ips 6 1099 10147 Bit 4 csi 187 1052 6 10100 10148 voca E e 105 a FLASHCE 5 2 1053 a ips 10101 10149 vccs GND 106 7 1054 2 114 462 10102 10150 voce 97 4 107 86 RDWR 1 8751 5 5 8 1 D4 4 E2 10103 10151 910 jog 6 2 1 D4 4 E2 1056 10104 10152 vecs 913 amp 1 C4 4 E2 1057 HH 10105 10153 vcco Hi 4 010 85 1058 10 C5 10 E2 10106 10154 8 1059 10 E2 10 C5 10107 10155 9 2 6 1 87 5 2 5 2 5 5 6 02 1060 10108 10156 vcci2 8 4 a PC RDY 1061 10 85 10 2 10109 10157 vccia 9 4 a POIROT 4E26 E2 1062 10 85 10 02 10110 10158 veci 4 1015 9 a wes 187 565 1063 10 85 1002 10111 1
6. M3 Mt M2 22 13 pausa 45 015 16 21 ga pars 031 16 21 gai 58 015 21 10 20 14 43 D14 A15 20 0914 51 030 15 20 00914 51 014 20 9 pois 2 013 14 36 50 D29 m 36 2 pars _50 013 19 16 por 39 D12 35 48 028 35 por 48 D12 A18 17 17 pati 36 011 12 22 pati 47 27 12 22 pati 47 011 17 48 paio 34 D10 An a paio 45 D26 An a ig pao 45 16 rn as pos 22 D9 33 pos 44 D25 pos D9 15 5 _30 08 2 22 D24 32 22 08 m sis 4 07 8 13 023 8 13 07 4 m2 42 D6 A 30 i 022 a 5 i D6 12 5 pos 4 05 6 2 pos 10 D21 6 pos 0 05 An 6 Doa 38 D4 5 26 pas 8 D20 5 pas 8 71 Dos D3 5 pos LZ 019 25 pos 7 D3 8 Doo 2 23 24 ay 5 D18 L5 2 8 18 pat L3 Di pat 4 017 2 pat 4 Di 19 22 Do 2 D16 2 Do 6 20 5 cs 194 cs 5 2 184 M 22 17 as 17 as 23 38 we 16 We 24 39 unam aay IR 510 5 15 41 2 ds 38 38 FLASHCE mik 37 37 1 B7 4 B2 5 E2 5 C5 6 D2 R
7. 35 5 2 3 35 5 3 UAR E Saw cet 36 5 31 65 EUER 36 5 8 2 EE 37 5 9 9 Hegister 38 39 5 4 1 39 5 4 2 40 5 4 3 5 41 5 5 REM 42 5 5 Block 5 E 42 5 5 2 CONNECTION PINS 43 5 5 9 Hegister Cbr dua 44 5 6 e TRON IMEA HRS 45 5 6 1 45 I mAgieudiis 46 5 63 Register 47 CE x ccc 48 5 7 1 Block 48 5 7 2 Connector Through Hole Pin Assignments
8. G4 G4 G4 CE2A 2 CM Be CE2B 11 c H S u2 Ba 11 84 11 82 FRB 2 805 1 89 2 17 16 ANN T i 33V 21 94 4 64 c R23 94 1 2 4 go 104 504 TXB 13 HZ 2 TD 1 B 2R K 9 RISE 12 s 69 3 Di 104 504 RTSE RxD 3 E6 6 F2 MD5SW B2 21 15 MD5 104 4 4 and 1 88 19 15 16 04 5 104 504 RIOUT C RTS 23 504 CTSB 19 R20uT 9 STATUS BX EN STATUS D 2158 4188 TCK 1 3 3 ou 9 3 D3 MDSEL BE SHUTDOWN OTS PE SN74CBTLV3383DGV ONLINE 4 e 30 Tus 0603 St y uo pLa 21588 1 2 3 w H2 4 821 8 21 12 C 0 1UF 9 9 13 VEV Ziv 33 33V we 2 SP3223ECY oT Gs GND GND GND GND 15 aav ur RMC EA15MY OM15 MC1 BSD7SAABATiZIA7 RES 1 104 48 ADREG 10 510 2 GND 16080603 L GRD 2 103 57 ADACKO 1065 46 DRAG 107 102 ADRAKO 1065 GND ISP 4 TDI 101 5 2 22 2 EXTAL 5 100 58 ISP 8 43 3103468 ISP TMS 7 2
9. eun 07 05 D4 D3 Di om R R R R R R R The X position dot register indicates the dot position of a pen touched X position on the touch panel Use the output value of this register after calibration The output value is not settled without calibration 6 4 7 Y Position Dot Register YPDR Address 0x002A Initial value 0x0000 Di5 Dii w w R R R R R L 07 ps 2 a R m mm R The Y position dot register indicates the dot position of a pen touched Y position on the touch panel Use the output value of this register after calibration The output value is not settled without calibration 7760 01 Users Manual Power Supply Controller 6 4 8 XA Position Dot Register XAPDR Address 0 002 Initial value 0 0000 05 Dit w XAD D15 XAD D14 XAD D13 XAD D12 XAD 011 XAD D9 XAD D8 o 11 06 BE w The position dot register indicates the X dot position of point A when calibration takes place 6 4 9 YA Position Dot Register YAPDR Address 0 002 Initial value 0 0000 Di5 Di YAD D15 YAD D14 YAD D13 YAD D12 YAD D11 YAD D10 YAD D9 YAD D8 qe
10. gt 143 ROP7760TH001TRK Users Manual User Registration User Registration When you have purchased the product presented in this manual please register your name and address Your registered information is used for only after sale services and not for any other purposes Without user registration you will not be able to receive maintenance services such as a notification of field changes or trouble information So be sure to register your name and address To get reference information about user registration please visit the Web site shown below Renesas Tools Homepage http www renesas com en tools Inquiries regist_tool renesas com ROP7760THO01TRK Users Manual Outline 1 Outline This chapter describes the package components the system configuration and the preparation for using this product for the first time 1 1 Package Components The ROP7760THO01TRK package consists of the following items When unpacking it check to see if your ROP7760THO01TRK contains all of these items Table 1 1 Package components T Engine Board ACadapter T Engine Board User s Manual This Manual T Kernel and other software and various documentation Personal Media Corporation RS 232C cable Please keep the ROP7760THO001TRK s packing box and cushion material in your place for reuse at a later time when sending your product for repair or other purposes Always use these packing box an
11. AUDOCODEC unwwers Rre ooo Transceiver seExk Headphone ampli Was lvotage montor _____ filter BLM18PG300SN1 lt D gt CN NN eo SLF6028 lt T gt 100M1R3 SLF10145 lt T gt 100M2R5 aonn 7760 01 Users Manual Attached Documents CPU Board Parts List 2 hip continuous resistance INA SEORP J103 ROHV 5 Chip resistance 1005 MCRO1MZS J000 ROHM 12 R45 to R50 R59 R60 R84 R121 Chip resistance 1005 01 25 102 ROHM 20 R17 R19 to R23 R26 R28 to R33 R37 R52 R54 to R56 R77 and R78 Chip resistance 1005 MCRO01MZS J103 ROHM 37 R4 to R14 R16 R18 R24 R27 R34 to R36 R39 R51 R53 R57 R58 R67 R74 R79 R80 R82 R86 R87 R90 R91 R94 R95 R98 R109 R111 and R114 Chip resistance 1005 MCRO1MZS J104 ROHM 12 R88 R89 R107 R115 8116 R118 and R124 to R128 Chip resistance 1005 01 28 151 ROHM R96 and R97 Chip resistance 1005 MCRO1MZS J153 ROHM R100 R104 R113 and R120 Chip resistance 1005 MCRO1MZS J164 ROHM R119 R81 Chip resistance 1005 MCRO1MZS J202 ROHM Chip resistance 1005 MCRO1MZS J222 ROHM 5
12. 1 2 3 6 7 VDD VGOFF CNS CNS GND 1 A6 XR 1 xR 3 B2 VSP 2 vsP 1 A6 YD 2 vp 3 1 A6 XL 3 3 B2 VOE 4 VOE 1 A6 YU 4 vU 5 VGOFF SFW4R 1STE1 3 B2 VCK 6 7 VDD 3 A2 DR 5 0 8 VBAT DR5 9 pos 10 poa 2 DR3 11 m M Q2 DR2 12 3 DR1 13 poi Ey EY 2 u 2 DG 5 0 DRO 14 Doo Si3443DV L3 SD6 065 15 pis e mm 2p 4 v2 004 16 f 4 DTC143ZE T u5 L 10UH CRS03 04FLH SM1 TB DG3 17 ECO 5 1 gt D13 1 B3 LCD FLON 198 5 sw 4155 DG2 18 pi2 SES 4 SHDN OT un DG1 19 2 GND DB 5 0 DGO 20 7 D10 GND LT1615ES5 m E 025 GND GND GND 188 254 GND D24 Too DB3 23 023 lt DB2 24 poo DB1 25 021 GND GND DBO 26 pag 2 4 2 GND 3 B5 HSP 28 HSP 3 B5 HCK 29 HCK 30 vcc 3 B5 31 ap 3 B5 STB 32 srB 3 B5 POL 33 POL 3 B5 INV 34 INv 35 VDD C6 __ N C 112 36 R6 R7 1 2 1 2 4 7UF 37 R8 aset so va R 100 40 v2 41 GND MET 42 vg 43 NC 44 45 GND FH12 45S 05SH GND VGON VDD T D gt D gt D gt D gt 11 11 11 GND GND GND GND MS7727LCD01 4 PAGE 4
13. 2 2 gt GND GRD AC97 903 16V 16V 0 01 UF 50V 0 01 UF 50 0 1UF 0 1UF Y Y 2 C 2 C 2 XTAL R E B 8 IR 2 B 2 2 2 2 0603 0603 0603 0603 55 ANA 10 5 AAA 10 55 ANA 10 5 AWN 10 1608 1 1608 1 1608 1 1608 1 16V C71 16V 16V 16V 0 01 UF 50 0 01 UF 50V 0 01 UF 50V 0 1UF 0 1UF 0 1UF 0 01 UF 50V m 5 C66 C78 0 1UF Y Y Y Y o 2 C 2 2 2 2 2 2 2 w 5 x 2 921 5 S GND 11 03 11 03 11 03 113 HD6417760BP200D R35 AY 2 2 5 ADTRG D 262 SH7760 7 8 AC97 2B5 DREGT 2 4 UsB DM 819 __ uss DM vss 27 D14 ADTRG 24 usg pp TIE2 vsse P44 4 R 10K 617 vsss 017 4 USB penc USB TIE2 _ 17 4 USB ove 0020 vssa vss2 07 e vssi P s m Ei 3 1444 G4 33V 550
14. 07 D6 05 04 03 02 EEPDR D1 EEPDR DO This register consists of 512 8 bit data in the above format EEPDR address 00100 Ox0000 oxo2FE oxo2FF 84 EEPROM address corresponds to an EEPDR address When read write operation is performed on the EEPROM the EEPDR address must be specified for the operation 7760 01 Users Manual Power Supply Controller 6 10 3 Serial EEPROM Operation Procedure Initial Setting 1 The START bit of the EEPCR register is set to 1 For a read write operation to the serial EEPROM 1 An EEPDR address corresponding to an EEPROM address must be specified for a read write operation CAUTION Q When the START bit of the EEPCR register is 0 read write data is not guaranteed 7760 01 Users Manual Power Supply Controller 6 11 Electronic Volume Control This section describes the electronic volume control functions Table 6 11 summarizes the electronic volume control registers For details of each register refer to 6 11 1 and 6 11 2 1 An electronic volume value can be set An electronic volume value can be set within a range from 0x00 minimum sound volume to OxFF maximum sound volume 2 Two electronic volume values can be set An electronic volume value can be set for the right or left speaker Table 6 11 Electronic
15. 12 H HD74LV1GOOACM Title MS7760CP01P 1 Circuit Diagram GRD 12 33VSB 5 GND 3 Date 7 29 2003 14 52 Sheet 9 of 1 2 3 4 5 6 7 8 BASE BOARD INTERFACE CONNECTOR 5 A 250 5 DRIO 2 CN2 5V 36 pog AM 2 SCIF2 CTS m 196 scir crs 37 30 25 wine 5V 38 psi 403 EPROMCE 108 5V 39 GND CS2 19 GND DO CS4 4 19 end Di 41 403 CS5 11 7 10 2 HDI 11 D2 1 403 ARDWR RDWR 4 C7 10E2 HDI TMS mw 112 rus D3 ABS BS
16. Decided EN R R R R R R This register stores the bit pattern of the application switch SW1 to SW3 key input status 1 SWn 0 Application switch key input OFF Initial value Application switch key input ON 7760 01 Users Manual Power Supply Controller 6 5 7 Key Input Status Register Address 0x0062 Initial value 0x00 07 D5 a 02 m DO p me R RW RW 1 _ KEY ONF bit An application switch key has not been turned on Initial value a 1 An application switch key has been turned on At this time if the 1 KEY bit is set to 1 a key ON interrupt occurs Clear condition 0 is written with the KEY ONF bit set to 1 2 KEY OFFF KEY OFFF bit An application switch key is ON or OFF Initial value MEE RENI An application switch key has changed from ON to OFF Initial value At time if the KEY bit is set to 1 a key OFF 1 interrupt occurs Clear condition 0 is written with the KEY OFFI bit set to 1 3 ARKEYF The same application switch key is not ON for the time specified in the key auto repeat time register Initial value The same application switch key is not ON for the time specified in the key auto repeat time register At this time if the ARKEYI 1 bit is set to 1 repeat interrupt occurs Clear
17. 18 2 2 AC Adapter CL 19 2 3 Turning or OFF the T Engine 20 2405 Debug RR 20 2 4 4 Debug Board Function conii eni eai rero ego tea eddie 20 2 4 2 Debug Board Connection roseo ctp buco dede ees beau dedi rau cau 21 2 4 3 Debug Board Jumper Switches 22 2 4 4 8bit LEDs on the Debug 22 245 16 bit SWs on the Debug Board 22 2 4 6 H UDI Debugger enne nh 23 3 SWINGS 24 S Board 24 3 2 LGD ERERT 26 4 usato 27 4 1 Memory Map for the T Engine Board 27 4 2 Memory Map during Debug Board 28 5 e RUE 30 elei E 30 5 1 1 Desai pU pec 30 5 1 2 PINS 31 5 1 9 33 5 2 USB HOSE eM LC 34 5 2 1 Block MEE 34 512 2 PINS
18. 2 49 ROP7760TH001TRK Users Manual Contents 6 Power Supply 51 6 1 Power Supply Controller 51 6 2 Serial Communications between SH7760 and the Power Supply Controller 52 6 221 56 52 6 2 2 Power Supply Control Register Read 52 6 2 3 Read 53 6 2 4 Normal Response during Read 54 6 2 5 Error Response during a read Operation 54 6 2 6 Power Supply Control Register Write Procedure 55 6 2 7 Write 55 6 2 8 Normal Response during Write Operation 56 6 2 9 Error Response during a Write 57 6 3 Real time Clock FUNCTIONS ta EE dede e verant dei 58 6 34 Control Register dine d Rar Ed 59 6 3 2 RTC Status Register 60 6 9 3 5econd 5
19. 70 6 4 4 X Position A D Register 70 5 4 5 Y Position A D Register YPAR vend dde 71 6 4 6 X Position Dot Register 71 6 4 7 Position Dot Register 71 6 4 8 Position Dot Register XAPDR 72 6 4 9 YA Position Dot Register 72 6 4 10 XB Position Dot Register 0400 72 6 4 11 Position Dot Register 4 4 4 22 ntn trennt nnne 73 6 4 12 XC Position Dot Register 73 6 4 13 YC Position Dot Register 0 73 6 4 14 XA Position A D Register 74 6 4 15 YA Position A D Register YAPAR dre 74 6 4 16 XB Position A D Register XBPAR 74 6 4 17 YB Position A D Register YBPAR 75 6 4 18 XC Position A D Register XCPAR 75 6 4 19 Position A D Register YCPAR 75 6 4 20 DX Dot Register DXDRY n ese cda senec bu
20. R 1 SPOWER SPOWER bit System power supply OFF System power supply ON Initial value 6 6 2 System Power Control Register 2 SPOWCR2 Address 0x0071 Initial value 0x01 R m m HB RW 2 SFPOWER 0 TEngine is turned OFF by SH7760 control T Engine is turned OFF by pressing the power on switch Initial value 6 6 3 RTC Touch Panel Key Input Power Supply Status Register RTKISR This status register indicates the RTC touch panel or key input status Below is a brief description of the status bits for power control Address 0x0090 Initial value 0 00 07 D4 2 D DO __ RTCIF R R R Rw RW RW RW RW 1 POWERIF This bit will be functionally enhanced in the future Don t access this register When read this bit is always 0 7760 01 Users Manual Power Supply Controller 6 7 LCD Front Light Control This section describes the LCD light control functions In addition Table 6 7 summarizes the front light control registers 1 Controlling the ON OFF state of the LCD front light Table 6 7 LCD front light register n S LCD front light register LCDR 0x00A1 perl byte 6 7 1 LCD Front Light Register LCDR Address 0x00A1 Initial value 0x01
21. D2 D1 D0 1 1 0 Saturday 6 3 7 Day Counter Address 0x0006 Initial value OxXX defined R R Rnw Rw Rw Rw Rw WW The counter value is a BCD Binary Coded Decimal value Counting takes place within a range from 1 to 31 January March July August October and December 1 to 30 April June September and November 1 to 28 February in normal year or 1 to 29 February in leap year 6 3 8 Month Counter MONCNT Address 0x0007 Initial value OxXX Not defined a a R RW RW RW Rw RW The counter value is a BCD Binary Coded Decimal value Counting takes place within a range from 1 to 12 When the counter value changes from 12 to 1 a carry is generated in the year counter 7760 01 Users Manual Power Supply Controller 6 3 9 Year Counter Address 0x0008 Initial value OxXX T T 10 years ear oe The counter value is a BCD Binary Coded Decimal value Counting takes place within a range from 0 to 99 In this range 00 04 92 and 96 are leap years 6 3 10 Alarm Register Each alarm register corresponds to the relevant counter as shown below If the AR bit 07 of each alarm is set to 1 counters will be compared with alarm registers This comparison is performed only for alarm registers with the AR bit D7 set to 1 and an alarm interrupt is generated only at correct corr
22. 1 54 2 1 AND 5 2 R 100 zca 1 2 100 zca R 100 15 5 81 ST 415 21 5 97 97 LASS Title MS7760CP01P 1 Circuit Diagram Date 7 29 2003 14 52 Sheet 11 of 12 1 2 3 4 5 6 7 8 8 SOFT RES VBAT pc 022 TE 2 3d WR vec 4 4 DC ADP IN BRE CES 1 RES 1 89 2 H8 RES 3C28D78 MBIAT HEC3600 010020 5 GRD p My X MAXB1IREUS T LL VRES 2 63V L 1 2 GRD C 0 1UF ADPIN 8E28D2 16 GRD VBAT VBAT 33v 552 552 2 Do not stuff SEDE X pe 1 2 20 nr 1 3225 1210 160000609 15 CURE Do not stuff m m POWER SW amp E28 C2 FSEL VINO m lese d 1 2 18 10 GND GND ei 1 m 2 17 BIAS P acc E T cw 33VSB EE 2 o GND PWRGD PHO OTT e 16000603 L 10UH RESET SW 8 2 8 02 3 uc Boot 5 1 2 33 T C 47000PF 94154 L 2 19 Q2 12 33V 2
23. 8 84 6 5 4 Key Control Register 85 6 5 5 Key Auto Repeat Time Register 86 6 5 6 Key Bit Pattern Register KBIPR enne then nennen nen 86 6 5 7 Key Input Status Register 87 6 5 8 RTC Touch Panel Key Input Power Supply Status Register 89 6 6 Power Supply Corittol 22 ict Latt ces otro 89 6 6 1 System Power Control Register 1 1 90 6 6 2 System Power Control Register 2 5 2 4000 000 90 6 6 3 RTC Touch Panel Key Input Power Supply Status Register 90 6 7 LOD Front Eight COMO lsc Tt 91 6 7 1 LCD Front Eight Register 91 6 8 Reset 92 6 8 1 RESTCR Register 5 92 5 9 Infrared Bere rico em 93 6 9 1 Infrared Remote Control Register 94 6 9 2 Infrared Remote Control Status Register 95 6 9 3 Receive Data Count Register for I
24. m Nc 4 Ten onl cal caf caf ca cal 6 end 187 17 215 18 slt 187 TNS 19 rus 4 36 9 20 B 7 187 TRST 21 55 E 71 13 187 TDI 23 1 B52 CA al 12 M27C160F1 9 m 187 TDO 25 8 26 1B52C3 187 ASEBRKAK 27 ASEBRK 116 HD74LV1G32ACM T 29 Noo 33 5 HD74LVC245AT 30 GND 3 GND SRD 1 5 ARST OUT 31 nRESET 145 A Tend HD74LVC139T 4 3 ESI 4 3 GND 8 35 Nc 9319 36 end ADIS 2 8 DX10M 36SE 014 3 17 Mach UDI port A D13 16 012 5 15 US im A Dii 615 14 1312 LN 2 1 2 010 7 6 B6 13 4 2D 20 5 D9 12 7 6 LN 2 1 2 A D8 9 11 8 13 1212 EPA 2 4 2 194 14 15 6D 1 3 20 17 16 R4 2 1 2 DIR GND 10 70 18 19 HD74LVC245AT 8D ns mE A 1452 1 2 07 2 18 Bi LEDs A D6 3 17 oc 1 2 1 2 2 HD74LV1G32ACM 7 ADS 4 16 E 05 8S HD74LVC374AT LED7 04 mE E D4 M 2 1 03
25. 25 1 25 voc 1 82 CMT CTR3 g 4 185 26 wins 26 voc FFC 4AMEP1B 27 gt Do not stuff 185 LCD DON 5 FFC 26BMEP1B 28 T Ll Do not stuff 2 1 7 2 RESET 28 RSTOUT 1C2 SCIFi TXD SCIF TXD 30 LC 1 2 RXD sar SCIFi RTS scri ars ao SCIFi CTS g 4 3 ao 162 SCIFi g sort ax 4 5 ao 35 Do not stuff 33V 36 som 37 voc 1 2 SCIFO TXD m mb 38 voc 1 2 SCIFO RXD gt 5 39 3 aise gee vec m 40 voc not Si FFC 40BMEP1B Do not stuff L 1C2 2C1_SCL 1 M C2 201 SDA 2 aci sa FFC 2AMEPIB Do not stuff Title MS7760DBG01 2 1 Circuit Diagram Date 7 29 2003_14 58 Sheet 2 of 2 MS7760CP01
26. 5 6V Supply voltage generation Power supply control Sound generator Chip UDA1342TS H8 3048B 5 7760 UART 2Ch 5V 33V L5V INTC 8bit CLK SH Local Bus 16bit 32bit 16bit Adress Flash Bus USB PC Card Extension bus interface Figure 1 2 T Engine Block Diagram ROP7760THO01TRK Users Manual Outline 1 3 T Engine Appearance T Engine Board consists of four boards CPU LCD debug and boards Figure 1 3 is an external view the T Engine Figures 1 4 to 1 7 show the appearances of the respective boards LCD CPU debug and boards LCD Board CPU Board gt Board Debug Board Figure 1 3 T Engine External View ROP7760TH001TRK Users Manual Outline LCD interface connectorl LCD interface connector2 Contrast control volume LCD interface connector3 CPU board interface connector2 CPU board interface connectorl Rear view Infrared remote control reception Push button switch3 Cursor switchl Push button switch2 Front view Figure 1 4 LCD Board External View ROP7760THO01TRK Users Manual Outline System reset switch H8 3048 ONE write connector Infrared remote control transmission LED Extension slot 8 bit DIP switch Serial interface connector po board interface SIM card connector I O board interface connector2 Rear view Earphones microphones connection connector LCD board interf
27. De Ds 208 o The X position dot calculation A D value 2 register XPARDOT2 holds XPARDOT value before sampling 7760 01 Users Manual Power Supply Controller 6 4 25 X Position Dot Calculation A D Value Address 0 004 Initial value 0x0000 2 07 De 05 ps 07 06 ps o The X position dot calculation A D value register XPARDOTS holds an XPARDOT value before sampling 6 4 26 X Position Dot Calculation A D value 4 Address 0x0050 Initial value 0x0000 015 Dt o E HB mu ME RH BE BE E The X position dot calculation A D value 4 register XPARDOTA holds an XPARDOT value before sampling 7760 01 Users Manual Power Supply Controller 6 4 27 Y Position Dot Calculation A D Value YPARDOT Address 0x0052 __hitial value 0x0000 08 pz J 07 vo 66 vo os V vomas The position dot calculation A D value register YPARDOT holds A D value of position dot calcula
28. Chip resistance 1005 MCRO01MZS J224 ROHM 1 UC NNNM M RE and R106 M O R112 R117 and R122 Chip resistance 1005 MCRO1MZS J473 ROHM Chip resistance 1005 MCRO1MZS J681 ROHM Chip resistance 1608 MCRO3MZH J100 ROHM R38 R83 R85 and R93 Chip resistance 3216 MCR18EZH J101 ROHM 7760 01 Users Manual Attached Documents CPU Board Parts List 3 Chip ceramic capacitor 1005 Chip ceramic capacitor 1005 GRP155F11H103ZA01 E Murata Manufacturing C8 C58 C60 C65 C67 C69 C76 C77 C83 C84 Chip ceramic capacitor 1005 GRP155F11C104ZA01 E Murata Manufacturing 51 C5 C6 C10 C14 to C21 C24 C26 C28 C32 to C34 C41 C42 C53 C59 C61 C63 C66 C70 to C72 C74 C75 C78 to C82 C88 to C91 C94 to C99 C101 C102 C104 C108 C115 and C116 C22 C4 C11 to C13 C49 C51 C37 C92 C93 C105 and C110 to C112 C9 C27 C47 and C50 hip ceramic capacitor 1005 GRP155F10J105ZD02 E Murata Manufacturing 1 Chip ceramic capacitor 1608 GRM188B11E104KA01 D Murata Manufacturing hip ceramic capacitor 1608 GRM188B11E473KA01 D Murata Manufacturing Chip ceramic capacitor 1608 LMK107BJ105MA T TAIYO YUDEN Chip ceramic capacitor 3225 LMK325BJ106MN T TAIYO YUDEN 4 hip ceramic capacitor 4532 EMK432BJ226MM T TAIYO YUDEN ROHM ROHM 5 T ROHM 2 2012 POSCAP D4 4TPB470M Sanyo Electronic 1 Component
29. dona AE 61 6 3 4 Minute Counter 61 635 Hour Counter 61 6 3 6 Day of the Week Counter n nnne nennen nnn 62 56 97 Day Gounter iiia eciam ise dae emet tix 62 6 3 8 Month Counter 62 6 3 0 Year Counter 63 SEE NIC 63 6 311 Second Alarm Register 5 63 6 3 12 Minute Alarm Register 63 6 3 13 Hour Alarm Register 4 64 6 3 14 Day of the Week Alarm Register WKAR 64 5 3 15 Day Alarm Register DAYAR cene 65 6 3 16 Month Alarm Register nnne nennen nnn 65 6 3 17 RTC Touch Panel Key Input Power Supply Status Register 5 65 6 4 Touch Panel FUnCHorns 66 6 4 1 Touch Panel Control Register 68 6 4 2 Touch Panel Status Register 69 6 4 3 Touch panel Sampling Control Register 5
30. soa 2 ggaage 8 A4 9 C2 VOLTS 9 10 i5 15 88655 lt 49 9 5 28 4 VOCON ANNOS 2 5 amp PATE UE m zi E E E E g 5 8588 8 4 12 02 922332850 ON g ogoocooOooOo0rcruganaaag sccrcaays aas 4 225532025 iw ce FR H8 g ef amp ol EEFFREEFFE eww 8 7B78A4 ANN R 10K R27 L ses 8021283 ADPIN GN o 33 158 865 2 2 S 1 2 7IBz8 D2 LCD FLON oT eu rx 865 VOUTI 67 R 10K 787 82 LCD PWRDY RA 8021207 NMI SW 885 H8 SW2 8 02121 RESET SW i B M bade RE RE 885 2 GND 40 8 C242 B7 POWER SW 5 5 E zB 6666 8E38A7 E 2 o o SC78 C2 RTC_INTR a E o Lco 82 787862 5 To 25 B B 9 oO M ul ul 8 4 12 2 VCC5 ON 5 5 5 7 78 5 KEY INA 5 55 IAF 5 8 555 TIATBCS KEY 3 Pon B 9 5 TIAT
31. 285 ADC ape 33V 7 ao 4 L 2 A32 c2 RESET 7 RESET 8 ADC SRD 8 uc H8 SCK1 8 PAD 9 VCPWC 9 vcewc H8 RXD1 9 PAD DOUT 285 NERR 10 VEPWC m 10 Vepwo H8 TXD1 10 PAD DIN 285 NERR FH12 10S 0 5SH 262 FLM 1 RM PAD 11 pap 285 12 262 12 M DISP PAD CS 12 PAD csr 2 B5 13 LCD DON 13 4 3 2 85 CANO TX 14 cawo TX 262 CL2 285 TX 15 Tx 262 15 KEY OUT2 15 KEY OUT2 5 ao GND 6 KEY OUT 16 KEY 2 C5 CMT m 17 2IA32 A2 LCDD 15 0 KEY 17 KEY OUTO 265 CMT 18 cur crm LCDDiS 18 cpis KEY 18 V KEY 4 265 CMT CTR2 19 LCDDi4 19 KEY IN3 19 KEY IN3 205 20 cms LCDD13 20 KEY 20 KEY 21 Leppi2 21 C12 KEY 21 KEY INI 265 1 22 scri LCDDi 21 KEY INO 22 KEY 265 CTS 23 sar LCDD10 23 cpio 265 SCIFi RTS 24 Sor mms LCDD9 24 2 265 SCIFi RXD 25 sari mo LCDD8 25 Tepe FH12 24S 0 5SH 265 SCIFi TXD 26 s
32. 4 74 jo 40 75 GND GND O 113 TRST Gub mi w 115 117 118 33 68 120 sevse 126 AUDCK 127 aw NMLIN 128 RST_IN 129 33V RST_OUT 130 33V 131 33v 132 133 veat nes oMsEL 134 100 BAsER 2 135 136 IN 5 JIN a 2 o o o o ID JPM IN 5 6 EX 35 105 Indicates the address bus data bus control signals and serial signals of the 5 7760 Supply voltage is 3 3V 1 5 0V typ is supplied when the SH7760 is turned on 2 If this pin is set to Low output takes place from the SH7760 extension to the extension slot 8 typ is supplied when the battery is provided or the AC adapter is connected 4 3 3 typ is supplied when the SH7760 is turned on Pin for power supply 4 2V to 3 6 be powered via the extension slot ROP7760T
33. DTC143ZE TL GND7 2 2 5 5 m 3 mE ANN 1 25K2980 u21 3VSB 1 5 GND 807844 VOLTS R 470 GND upra vozAT R69 1 2 osca 33v 3 21 42 RA SG 8002JF 22 579200M PCCB 0 cne 1 vec He 4 C 0 1UF ae 2 3 1 R61 2 16 112 Aer GND OUT AN CLKO 245 C 0 1UF 3 ay R OUT F 22 579200MHZ aby 4 Mic IN S25 5 zea VDDA HP SENSE 7 HSJ1602 011010 33V VDDD VDDA 1 817 2 R 470 R3 1 2 VDDA a CNB 2 VDDA 1 54 4 5 24 8005 002 100 867 LED wy NE Do not stuff STATUS 1 CEN gd 2 AGND LEDI GATE 024 STATUSO 1 2e A 15 LEDS m AGND 1 6 2 K 1 1 2 Y EN o 85190 AGND 8 TS TRI 3216 1206 oT GL ES IR DOUT g ep 2 1 2 8E3 HD74LVIGOBACM S BLMIGPGSUQSNT D mle lt 33VSB 5 274279 GN GN GN AGND AGND asi 827 4 GRD Un 9 8 GND GND gt 33VSB 14 115 705 Ls 2 IR DIN 802 va 11 10 HD74LV1G08ACM Hs 33VSB 5 107 ae HD74LVOTAT NEZ Un 5 IR
34. 102 SCIF2 103 Scir TxD GND 34 A 22 69 102 SCIF2 RXD 104 SciE RxD GND 35 pos 23 70 102 SCIFZ RTS 105 SciF RTS GND 24 5603 14 0101 861 24 5603 14 0101 861 24 5603 14 0101 861 24 5603 14 0101 861 GRD GRD GRD GRD GND GND 4 83 10 85 4 83 10 85 4JB3 10 C5 4 B3 10 C5 3021065 3 02 10 25 3 C3 10 C5 4 B3 10 C5 4 B3 10 C5 1 C7 10 87 1 C7 10 87 1 C7 10 87 1 C7 10 87 1 C7 10 87 4 83 10 85 Title MS7760CP01P 1Circuit Diagram Date 7 29 2003 14 52 Sheet 10 of 12 1 PORT INTERFACE 6 15 2 gt ao 165 FCE 3 165 m 4 rax 165 FSC 5 165 FOE roe 6 3 A2 11 BA FRB 7 E 7 aw 8 8 NC 115 SDA 9 soa 91 115 SCL 10 ory 4 ao FH12 10S 0 5SH SCIFO TXD m 12 mo 4 E2 11 B4 SCIFO RXD 13 mo 1 2 11 84 SCIFO m 14 102 SCIF1_TXD 15 scri mo 5 2
35. Figure 7 1 Interrupt Signal Mechanism Table 7 1 Interrupt Levels for Interrupt Signals No Remarks Interrupt level 14 Interrupt level 10 PCMClAcontroller SIRQ1 Interrupt level 7 Interrupt level 5 Interrupt level 9 6 UARTcontolerchB IRL S0 RL 30 O01 _ Interrupt level 12 Interrupt level 13 Extension slot IRQ2 IRL 3 0 IRL 3 0 0100 Interrupt level 11 Extension slot IRQ1 IRL 3 0 IRL 3 0 0111 Interrupt level 8 8 Extension slot IRQ3 IRL 3 0 IRL 3 0 0000 Interrupt level 15 Extension slot IRQO IRL 8 0 IRL 8 0 1001 Interrupt level 6 ROP7760TH001TRK Users Manual T Engine Extension Slot 8 T Engine Extension Slot 8 1 Extension Slot Specifications Connector number CN2 T Engine connector model 20 5603 14 0101 861 Kyocera Elco Adaptable connector model 10 5603 14 0101 861 Kyocera Elco Figure 8 1 shows the location of an extension slot 3 00mm 75 00mm Center of 3mm x 3mm CNI Serial interface connector B23 Clearance 120 00mm 0 58 Side pin 220 98 Side pin Extension slot 37 50mm Extension slot magnified Figure 8 1 Extension Slot Position 7760 01 Users Manual T Engine Extension Slot 8 2 Extension Slot Signal Assignment Table 8 1 shows the assignment of extension slot signals Table 8 1 Extension Slot Signals Pos w 60 HE xe 3 sv 38 73 EPROMCE
36. 07 Ds 2 Dt e 6 uw p LR R R R j R j R RW 1 FRONTL FRONTL bit The LOD front light is turned ON 1 The LCD front light is turned OFF Initial value 7760 01 Users Manual Power Supply Controller 6 8 Reset Control This section describes the reset control functions Table 6 9 summarizes the reset control registers 1 T Engine reset is controlled Table 6 9 Reset Registers RESTCR 2 mw 6 8 1 RESTCR Register RESTCR Address 0x00A2 Initial value 0x02 07 D4 D3 2 m SWRES sores O R R R RW RW 1 SORES SORES bit T Engine is not restarted by reset Initial value T Engine is restarted by reset If this bit is set to 1 T Engine is restarted 2 SWRES Devices other than the power supply controller are reset with the reset switch SW2 1 All the devices covering the power supply controller are reset with the reset switch SW2 Initial value 7760 01 Users Manual Power Supply Controller 6 9 Infrared Remote Control This section describes the infrared remote control functions Table 6 9 summarizes the infrared remote control functions For details of each register refer to 6 9 1 to 6 9 8 1 Support of formats for two kinds of infrared remote control signal
37. 1 D2 1 B4 5 1 RXD 16 mo 3 A2 11 B2 FRB 1 102 SCIFLRTS 17 Sort 1 D241 C4 SCIFi CTS m 18 5 4 E241 B2 SCIFO RXD g 1 D241 CA SCIF1_CLK 19 ax 1 E2 1 B2 SCIF g 20 ao 1 02 11 82 SCIFi RXD m y 1211 54 CMT 21 a cms 1 D2 1 B2 SCIFi w 11 2 11 4 CMT CTR2 22 1 D241 B2 CLK g 02164 CMT 23 aw cmi 1 D241 CA m 24 E 25 1 89 5 1211 62 CMT 5 4 2841087 TX 26 1 C241 C2 CMT CTR2 2 B4 10 B7 CANO TX 27 1 C241 C2 CMT CTR g 2 BA 10 B7 11 CA 28 1 D241 C2 2 B4 10 B7 11 CA CANO 29 2 B4 10 B7 11 C2 g 8 2 84 10 87 11 4 NERR 30 NERR 2 B4 10 B7 11 C2 CANO 1 2 CA40 C7 1 CA 31 NERR 2 B4 00 B7 11 C2 S nang 32 2 CA40 C7 1 C2 33 34 ADC 35 AND 36 37 AN2 38 39 avec ADC 40 ADC 12 405 056 GRD 11202 a SH AVCC 204
38. 33VSB 50 75 E 85 WEZ 120 51 E 88 WES AUDATAO 321 AUDATAO 52 4 7 287 AUDATAi 122 AUDATAI 53 4 8 287 AUDATA2 123 2 54 59 287 AUDATAS 124 AUDATAS 55 A10 287 AUDSYNC 125 AUDSYNC 56 Ar ARO 91 iRa2 27 AUDCK m 126 AUDCK 57 12 1803 92 127 58 A3 1 2 93 NMLin aav 59 Ald 1 2 ARST 94 RESn 2 aav ADIs 5 60 Ais 207 A RST OUT 55 RES out 0 av ADI 96 pREQO eei D20 27 62 ADRAKO 57 DRAKO 1 132 aav A D21 28 16 63 A16 98 133 Ape 2 94 AIT 102 ROMSEL 39 ROMSEL H 023 18 65 300 eer 135 vmar 3 Loa A 19 66 is 101 136 ear aps 3 20 67 102 137 oND a 026 33 poe mE 68 TXD 103 np 138 027 34 par 69 104 4 99 ap 35 pos 70 RTS 35 10 5603 14 0101 861 10 5603 14 0101 861 10 5603 14 0101 861 10 5603 14 0101 861 GND GND GND GND 105 ROMSEL GRD TPi A NMI IN 1 at 15 1 65 ARTN g To reset mo 105 On 105 RTS YA
39. COEE _ CN2 M RN xv 2 2 1 an S BE 3 TP1 5 m aaa TP2 ec 225 AN bi gt un EE G 0 2 1 Hell R N NC x 9 Ka n 15 99 o oo Ani pu 40 ban NS S z LED8 ve LED7 LN gt pu Eu LED6 N e p rH LEDS f lt ER 1 04 NS lt LED3 S He wh om LED2 x Eu LED1 Ka 26 gt SN o V Vm N 120 75 24320 22 118 6 2 3 33 23 20 34 25 70 44 5 MS7727LCD01 4 ERIE YAN SH7760 T Engine User s Manual ROP7760THO01TRK Publication Date Aug 2004 Rev 1 00 Published by Renesas Solutions Corp Microcomputer Tool Marketing Department Renesas Solutions Corp Edit by Microcomputer Tool Marketing Department 2004 Renesas Technology Corp and Renesas Solutions All rights reserved Printed in Japan ROP7760TH001TRK Users Manual 434 NE SAS
40. DXdotregister 00044 RW bytes DYdotregister 0006 RW j2byes X position ADvalue i 0x004A R W 2 A D value3 0 004 RW 2bytes X position A Dvalue4 7 XPARDOT4 RW 28 position dot calculation A D value YPARDOT oxoo52 RW j 2byes YpositionA Dvaluet 26 Y position A D vaue2 2 56 RW 2bytes position A D value4 R W RTC Touch Panel Key Input Power Supply RTKISR 0x0090 R W 1 byte Status Register 7760 01 Users Manual Power Supply Controller 6 4 1 Touch Panel Control Register TPLCR Address 0x0020 Initial value 0x00 D7 D5 D 2 o o PEN OFFI PEN TP STR LR Be Tq BW BW BW mw 1 TP STR TP STR bit 0 The touch panel is disabled Initial value The touch panel is enabled 2 PEN ONI ___ pen touch ON interrupt is not generated Initial value A pen touch ON interrupt is generated 3 PEN OFFI OFFI bit ___ pen touch OFF interrupt is not generated Initial value A
41. YCA Dio 09 D8 oR R R mw 67 De 05 w Dt position A D register indicates the Y position A D conversion result of point C subject to calibration This register will be functionally enhanced in future Don t access this register 7760 01 Users Manual Power Supply Controller 6 4 20 DX Dot Register DXDR Address 0x0044 Initial value 0 0000 Di5 04 Di Dto DX1 D15 DX1 D14 DX1 D13 DX1 D12 DX1 D11 DX1 D10 DX1 D9 DX1 D8 L Dr w pr The DX dot register holds value obtained by multiplying the number of dots per data X position A D conversion result at calibration by 1 000 The power supply controller outputs a dot position of the X position to be stored in the X position dot register XPDR from the values set in the DX dot register DXDR XA position dot register XAPDR and XA position A D register XAPAR When the DX dot register DXDR has been set to 0 the dot position is not calculated 6 4 21 DY Dot Register DYDR Address 0 0046 Initial value 0 0000 Di5 02 Dit pr p amp Dti DY1 07 DY1 06 DY1 D5 DY1 D4 DY1 03 DY1 02 DY1 D1 DY1 DO The DY dot register DY1DR holds a value obtained by multiplying the n
42. when others gt RdDatas lt RegRDO end case else RdDatas lt RegRDO end if end process Interrupt control register process RegWr WrDatas Rst begin if Rst 1 then IrqEnaReg lt 0000 elsif RegWr event and RegWr 0 then IrqEnaReg lt WrDatas end if end process end RTL 0x5950 0x4135 0x3031 0x3000 5 1 0 0 Null 7760 01 Users Manual 5 ldReg_r0 vhd module name ID register entity IdReg file name IdReg 0 rev 0 2003 01 15 Initial release library IEEE use IEEE std logic 1164 all use IEEE std logic unsigned all entity ldReg rO is port IdRegCs in std logic Rd x in std logic IdDatas in std_logic_vector 5 downto 0 RdDatas out std_logic_vector 15 downto 0 end IdReg r0 Architecture RTL of IdReg rO is begin process IdRegCs Rd x IdDatas begin if IldRegCs 1 and Rd 0 then RdDatas lt X 00 amp B 00 amp IdDatas DIP SW Read MDSW 5 0 else RdDatas lt X 0000 end if end process end RTL Attached Documents MODE setting 7760 01 Users Manual Attached Documents 6 SLAddr_r0 vhd SH Local Address Control Bus Interface in Extend Connector SLAddr SLAddr_r0 vhd module name entity file name library IEEE use IEEE std logic 1164 all use IEEE std logic unsigned all entity
43. Only the custom code and data code are specified for transmission data and the leader stop bit frame space and trailer are automatically added When the number of write data items is larger than that of the remaining transmission data 255 byte transmission data count register IRRSDNR a data length error occurs When the IRRRFDR register has become full during a read operation the buffer full error bit is set to 1 and the data received later is discarded The IRRIF bit of the RTKISR register is cleared when 0 is written with the IRRIF bit set to 1 7760 01 Users Manual Power Supply Controller 6 10 Serial EEPROM Control This section describes the EEPROM control functions Table 6 10 summarizes the serial EEPROM control registers For details of each register refer to 6 10 1 to 6 10 3 1 Serial EEPROM 512 bytes can be read and written Table 6 10 Serial EEPROM Control Registers EEPROM control register EEPCR 0 00 0 EEPROM data register EEPDR 0x0100 0x02FF 1 byte x 512 6 10 1 EEPROM Control Register EEPCR Address Initial value 0x00 07 w Di _ o o o o o starr Pp R R R R R R R RW 1 START 0 The serial EEPROM is disabled Initial value 6 10 2 EEPROM Data Register EEPDR Address 0x0100 to 0x02FF Initial value Not defined ps
44. pe D 07 De 05 m 07 06 05 3 The Y position dot calculation A D value 4 register holds YPARDOT value before sampling 6 4 32 RTC Touch Panel Key Input Power Supply Status Register RTKISR This status register indicates the RTC touch panel or key input status Below is a brief description of the status bits related to the touch panel Address 0x0090 Initial value 0 00 o o R R R RW RW RW RW TPIF bit The PEN ONIF PEN OFFIF CAIF and CAEF bits of the touch panel status registered are all set to 0 Initial value One of the PEN ONIF PEN OFFIF CAIF and CAEF bits of the 1 touch panel status register is set to 1 Clear condition 0 is written with the TPIF bit set to 41 7760 01 Users Manual Power Supply Controller 6 4 33 Touch Panel Calibration Method 2 point System The power supply controller supports 2 point touch panel calibration Figure 6 11shows the points of the drawing coordinates and A D conversion coordinates that are necessary for calibration Origin of drawing coordinates T Engine Board Drawing coordinates x axis Point B e 5 5 n SIX A S9 EUID1OOO 0015191
45. 402 3 LCDD1 4 wp 1 2 A LCDD2 5 pe 12 FRB x 5 mvausve 1 2 ANO 5 FFC 4BMEP1B LCDD3 6 6 6 Ponge MADS 102 FSC sc 182 AVSS ADC Avss ADC LCDD4 7 una 1 2 FOE 7 og FFC 6AMEP1B Do not stuff LCDDS LCDD8 S os LCDD6 9 06 LCDD9 9 101 CN6 HCAND 2 33V 12007 10 LCDD10 97 182 TX g TX LCDDii 182 RX 12 LCDDi2 12 182 CANO ot 13 100013 13 Do not stuff 1 009 14 1 1 0010 15 100015 15 gt poe i35 LCDDi 16 yg on 1 2 16 182 TX et cavi gt ao LCDDi2 17 102 17 182 2 ao LCDDi3 18 wg pi 102 18 182 g 3 cai LCDDI4 19 not a not 1 0015 20 20 4 ao 21 uc cur 4 2 ao 22 ne 182 CMT our cmo 1 85 23 un 23 Reserved 182 CMT CTRi g 2 1 85 FLM 24 RWRD 24 Reserved 1B2 CMT CTR2 g 1 85
46. CARD 6 87 783 7 82 1 87 4 82 5 05 91 CARD Vcc2 43 4 02 6 05 a 3 XRESET CARD amp 25 5 25 MR SHPC 01V2T STR GRD 90 100 121 131 140 B SIR A S t en Title MS7760CP01P 1 Circuit Diagram GND GND GND Date 7 29 2003 14 52 Shet 66 of 12
47. Don t put heavy things on the AC adapter cord To avoid the risk of electric leakage fire or electric shock don t damage or modify the AC adapter cord To avoid the risk of dectric shock don t unplug the AC adapter cord with wet hands To avoid the risk of cord damage electric shock or fire don t pull on the AC adapter cord rather grasp and pull the plug to disconnect the AC adapter cord When connecting the AC adapter to the receptacle check the polarity and connection beforehand to avoid the risk of electric shock fire or fault 2 3 Turning ON or OFF the T Engine Board To turn the T Engine board ON or OFF press the power on switch SW1 on the CPU board To turn ON the T Engine board press and hold the switch for 0 5 seconds or more To turn it OFF press and hold this switch for 2 seconds or more while the T Engine board is powered 2 4 Using the Debug Board 2 4 1 Debug Board Function When the debug board has been connected to the T Engine the following functions can be implemented 1 Run the program stored in the EPROM on the debug board to refresh the flash memory on the T Engine board H8 3048F One firmware be refreshed For details on flash memory refresh refer to 10 Flash Memory Refresh 2 The amp bit LEDs on the debug board be turned on or off from the SH7760 The software execution state can be monitored by controlling the ON OFF state of these LEDs 3 The 16 bit SWs on the debug
48. LR R R RW RW RW RW RW 1 RTCIF The ARF 1secF ad 0 5secF bits of the RTC register are all set to 0 Initial value One of the ARF 1secF ad 0 5 secF bits of the RTC register is set to 41 1 Clear condition 0 is written with the RTCIF bit set to 1 7760 01 Users Manual Power Supply Controller 6 4 Touch Panel Functions This section describes the touch panel functions In addition Table 6 4 summarizes the touch panel registers For details of each register refer to 6 4 1 to 6 4 32 1 2 The A D conversion value of the X or Y position sensed by pen touch is output Pen touch ON OFF interrupt function Sampling takes place at intervals of 20msec to 100msec When the results A D conversion value of the X or Y position obtained three times from sampling are approximate to each other a pen touch ON interrupt is generated for SH7760 addition when the touch panel is turned off pen touch OFF interrupt is generated To keep the pen touch ON sampling is performed at intervals of 20msec to 100msec and a pen touch ON interrupt is generated if the results obtained from sampling are approximate to each other Calibration function Calibration is performed when two points on the touch panel are touched with the pen After completion of calibration the X and Y positions are converted into the LCD drawing dot positions for output 7760 01 Users Manual P
49. RFU REG BVD2 UJ lt 66 7760 01 Users Manual Functional Blocks 5 1 3 Register Map Table 5 2 shows a map for the PCMCIP controller registers Each of the controller registers must be accessed in words Table 5 2 PCMCIA Control Registers Register name Mode register Option register Card status register Interrupt factor register Interrupt control register Card voltage control register Control register 1 Control register 1 Control register 1 Control register 2 Control register 2 Control register 2 H B8SFFFFC H 0000 Card control register 5333 Chip information register 7760 01 Users Manual Functional Blocks 5 2 USB Host 5 2 1 Block Description Figure 5 2 shows the USB host control block As shown in Figure 5 2 the SH7760 contains the internal USB host controller This internal controller supports USB Versions 1 10penHCl has the following features Compatibility with the Version 1 0a register set Conforms to the USB Version 1 1 Provides a route hub function Supports the low speed 1 5Mbps and full speed 12MB modes Supports an overcurrent detection function Supports a maximum of 127 endpoints Capable of using the shared memory 8K for transfer data and descriptors For details refer to the pertinent SH7760 Hardware Manual SH7760 USB A co
50. uss 520 e _4 vssais 09 2 AVCC SHAVCC 1103 vssarz 011 vssaie 213 4 55 vssais 015 4 ge vssaia LEZ 4 vssai3 174 vssa usa C19 4 e vssai2 M17 AVss Apc 17 a SH AVSS 1UES vssani NT HD6417760BP200D vssato W129 SHT760 6 8 vssog u12 ws vec He 1 Uto Us GND OUT a EXTAL 2 2 3 2 VSSQ5 9 u5 F 16 6MHZ VSSQ4 2 4 M4 4 vesci s vssao P4 HD6417760BP200D SH7760 8 8 EN 0 01 UF 50V Y 0 01 UF 50V Y 2 2 V 2 2 0861 E SG 8002JF 16 666700M PCCB vssas 1 2 o OSC2 SG 8002JF 48 000000M PCCB 1 vec He GND OUT UCLK 2 4 F 48 0MHZ Title MS7760CP01P 1 Circuit Diagram Date 7 29 2003_14 52 Sheet 2 of 12 1 2 3 4 5 6 7 8 SH7760 MODE CONTROL amp SIRIAL I F
51. 2 HDITRST 113 D4 1 GND 1 C7Z10 E2 HDI TDI 114 TDI D5 45 1 7 10 2 115 06 46 D 81 1 2 ASEBRK 116 ASEBRK D7 47 82 WAIT 117 D8 48 83 118 D9 4 M 84 dq 119 010 50 5 85 WEZ 120 Dii 51 86 284 112 TX 121 AUDATAO D12 52 DAT 9 284 112 TX 122 53 4 8 2 BA CA C2 123 2 A fe 54 4 B3 10 D2 89 2 411 4 1 2 124 AUDATAS 20 55 4831002 2 411 4 1 2 NERR 125 AUDSYNC 2 56 4831002 91 2ICAj CAj C2 NERR 126 AUDCK 4 2 m 57 f 12 4831002 ARG 92 127 aav 23 A A13 58 3021002 A NMIN x 93 NMLin 128 sav 24 59 3021002 ARST 94 RESin 50 303 RST2 35 RES out ad HH aav 26 4 8 3 C3 10E2 DREQO 96 pREQO 4 27 4 8 97 DRAKO 132 28 A 16 63 A16 33 ADACKO 98 IN 29 64 10 2 ROMSEL 99 ROMSEL IN 30 A18 65 AB3 10 E2 BASE 100 BASE VBAT IN 31 66 AI9 4 4 A20 57 102 GND 33 68
52. 76 6 4 21 DY Dot Register DY DR 76 6 4 22 X Position Dot Calculation A D Value XPARDOT 77 6 4 23 X Position Dot Calculation A D Value 1 77 6 4 24 X Position Dot Calculation A D Value 2 77 6 4 25 X Position Dot Calculation A D Value 78 6 4 26 X Position Dot Calculation A D value 4 4 78 ROP7760THO001TRK Users Manual Contents 6 4 27 Y Position Dot Calculation A D Value 5 79 6 4 28 Position Dot Calculation A D Value 1 1 79 6 4 29 Y Position Dot Calculation A D Value 2 2 79 6 4 30 Y Position Dot Calculation A D Value 80 6 4 31 Y Position Dot Calculation A D Value 4 nenne 80 6 4 32 RTC Touch Panel Key Input Power Supply Status Register RTKISR 80 6 4 33 Touch Panel Calibration Method 2 point 81 6 5 Key Switch mc 83 6 5 1 CPU Board Switch Comtrol 84 6 5 2 LCD Board Switch Control Application 84 6 5 3 Key Switch
53. DATAI Reh input mini jack SYSCLK L3CLOCK 22 5792MHz Power supply controller H8 3048F ONE Figure 5 8 Sound Generator Control Block ROP7760THO001TRK Users Manual Functional Blocks 5 5 2 Connector Pins Figure 5 9 shows the pins of the sound generator mini jack CN9 CN10 Tables 5 9 and 5 10 list the signals of the sound generator mini jack CN9 CN10 CN9 CN10 Sound generator mini jack 22 5 Model name HSJ1602 010011 Maker Hoshiden Corporation Figure 5 9 Sound Generator Mini jack CN9 CN10 Pins Table 5 9 Sound Generator Mini jack CN9 Signals 1 2 3 ROU __4 5 SENSE Table 5 10 Sound Generator Mini jack CN10 Signals Signal Name GND ek PROT 4 ROP7760THO001TRK Users Manual Functional Blocks 5 5 3 Register Table 5 11 shows a register map for the SH7760 SSI registers Table 5 11 SSI Controller Register Resister Address R W Initial Value Access Size Abbreviation SSICRO H FE680000 H 0000 0000 SSISRO H FE680004 H 0200 0003 SSITDRO H FE680008 R H 0000 0000 SSIRDRO HFEe8000C 0000000 52 SSITDR HFEe9008 0000000 32 ssiRDR HrEesooc 000000 32 ROP7760THO001TRK Users Manual Functional Blocks 5 6 eTRON Interface 5 6 1 Block Description Figure 5 11 shows an eTRON interface control block As shown in Fi
54. Front view NMI switch Figure 3 1 CPU Board Switches SW1 to SW5 1 Power on Switch SW1 This switch turns on or off To turn on T Engine press and hold down this switch for 0 5 seconds or more To turn it off press and hold down this switch for 2 seconds or more when T Engine is being powered 2 Reset Switch SW2 This switch resets T Engine To reset devices other than the H8 3048 ONE press this switch To reset and restart T Engine release this switch this case the values of H8 3048 ONE internal registers are not initialized Among the control registers the values of those that can be accessed by SH7760 are initialized but the others are not i e their values are retained For more details refer to 6 13 Initial Values of the Power Supply Controller Register ROP7760TH001TRK Users Manual Switches 3 NMI Switch SW3 This switch controls the SH7760 NMI pin Press this switch and the SH7760 NMI pin will go Low Release this switch and the NMI pin will go High 4 8 bit DIP Switch SW5 Figure 3 2 shows the setting of an 8 bit DIP switch This DIP switch is connected to pins IDO to ID5 and to MD5 of the SH7760 Be sure to turn off the power on switch before setting the DIP switch a Switches SW5 1 to SW5 6 are connected to pins IDO to ID5 input pins ON The input pin goes Low OFF The input pin goes High Factory setting b The SW5 7 switch is used to set the power on con
55. o RDE START CR BW 1 START is disabled Initial value Infrared remote control is enabled to start data transmission reception 2 FORMAT FORMAT bit Setting ___ The NEC format is set Initial value The Home Appliance Manufacturer s Association format is set 3 RDIE RDIE bit Setting An interrupt is disabled upon completion of receiving a frame of infrared remote control signal Initial value An interrupt is enabled upon completion of receiving a frame of infrared remote control signal 4 TDIE TDIE bit Setting An interrupt is disabled upon completion of transmitting a frame of infrared remote control signal Initial value 1 An interrupt is enabled upon completion of transmitting a fame of infrared remote control signal 7760 01 Users Manual Power Supply Controller 6 9 2 Infrared Remote Control Status Register IRRSR Address 0 0081 Initial value 0 00 MAMMA gt A a 1 RDBFER A buffer full error has not occurred during a receive operation EU P IEEE S value buffer full error has occurred buffer full error has occurred during a receive operation a receive operation 2 RDI A frame of data has not been received Initial value A frame of data has been received Clear condition 0 is written with the RDI bit
56. 3 3VSB 3 3VSB 2 U6 T 3 3V E 1 3 3VSB 1 16 PAD DCLK 1 B3 eo DUE 4 2 13 3V gg 2 13 3VSB 2 cs pi PAD CS 1 B3 9 3 33V YU 3 DIN 14 PAD DIN 1 B3 4 13 3V 1 GND XR 4 13 1 6 5 IR IN LCD PWRDY 5 PWR RDY YD 5 12 PAD DOUT 1 B3 GND 4 B4 LCD_FLON F LED ON GND PENIROO 1 83 0 RESET e 7 RESET 1 19 1 A8 PAD DCLK 8 PAD CLK 8 9 2 A2 VCPWCm 9 VCPWC PAD DOUT 9 PAD DOUT 057843 2182 4 10 vEPwC DIN 10 PAD DIN GND 11 11 FLM 4 z FLM 1 88 PAD PAD IRQ 33VSB 33VSB 3 C5 DISP 4 12 DISP CS 12 CS 3 C5 DON 13 13 oa 3 C5 CL2 4 14 4 4 GND 16 Fe FB 15 1 C5 KEY OUT2 15 KEY 2 9 a a 16 GND 1 65 KEY OUTiw 16 KEY OUT S 3 D2 LCD 15 0 GND 1 C5 KEY OUTO 17 KEY ouro reps 18 1 5 1105 KEY INA 18 KEY GND GND GND LCD14 19 LCD14 1 05 KEY IN3w 19 KEY IN3 LCD13 20 Cp13 105 KEY_IN2 20 KEY IN2 LCD12 21 LCp12 105 KEY INim 21 KEY IN1 1 B3 KEY OUT2w LCD11 22 105 KEY INO 22 KEY INO 1 83 KEY OUT LCD10 23 LCD10
57. 4 1 11 AGND PGNDO TPS54316PWP S13443DV 1 VOUT 33V dl GRD GRD SW 8 28 02 L a GND 858 GND VOLT x D 858 822 L 10UH yis 11 sw sw2 4 VBAT NA 302 GRD 7 vouT typ 5 002V cMsos 1608 0603 E 1 R32 Es 5055 FB Rio SS 9 a 8 1 8F28E4 5 ON 1 HA 5 28 MDSYNC SIGN 802 Do stuff Iu RT GND zz m dic 34401 t8 8 1 zS 8 42 8585 8 5 sleek 335 8575 58 TH 59 91 5 esi 2595 8 gt ge 8 d 25 Bs 07 BEI E 8 E GRD GRD Title MS7760CP01P 1 Circuit Diagram Date 7 29 2003_14 52 Sheet 12 of 12 1 2 4 6 7 8 CPU BOARD I F PAD I F amp KEY I F 3 3V 3 3VSB
58. 4 5 6 7 8 CPU SH7760 2 u7 07 EXTALI AL EXTAL 22 32 5511 SDATA AC97 50 8510 SDATA AC97 SD SSI1 SCK AC97 SD 55 0 SCK AC97 SD INUBS2 551 WS AC97 SYNCI 550 WS AC97 SYNCO ACS7 me o AC97_BIT_CLKO 33V AC97 RE 97 RE 22 T 33V 33V 33V 33V 33V 33V 33V 33V vopai7 C DREGT DREGT 4 n H W d DREGO DREQO Ci3 4 VDD CPG 4 H E 5 A 4 DACKo 418 8 4 VDD PLL2 DRAK1 H8 4 VDD PLLI eu DRAKO 18 4 120 TX 10 B7 11 C2 16 4 TX 119 TX 10 87 11 C2 vonas 12 4 VSS CPG cani px _________________ RX 10 87 11 C4 11 C2 4 vss PLL3 18 819 ________________ 10 87 11 4 11 2 19 4 vss PLL2 C NERRO NERR 1087 1 4 1 2 vonas 5 e B4 CANO NERR 9 10 C71 C4 1 C2 VDDQ4 5 4 HD6417760BP200D vppa3 4 SH7760 5 8 vec vec vec vec SSH 9 2 4 550 SDATA 942 Elt 4 SSI SCK vons 618 4 P184 ssi ws 9 7
59. 6 14 E D3 d BS 33V LEDS 02 LARES mE 02 NE 01 8 E Di 00 9 11 E Do 33 20 1 GND 10 SRD HD74LVC139T NI 33V 16 GRD a umm Title MS7760DBG01 1 1 Circuit Diagram Date 7 29 2003_14 55 Sheet 2 of 2 1 4 5 7 1 e eo 9 41 245 AVCC EL Aves 2 2 ssvsB 285 me fM M 55 3 wc 9 3 sav 245 o Eu 1 4 aav 2 5 ANT i 5 IR IN gg IR IN LCD PWRDY 5 Lcp PWRDY 2 5 ANO Ii 5 uc 6 LCD FLON 6 LCD
60. 72 PANSI oEN 29 3 E2 3 E2 PANSO 73 PANSO TESTEN2 28 4 74 27 M DISP 1 82 3 E2 INVSE 75 INVSE GND3 6 4 4 1 HDRES DCK 25 CL2 1 B2 GND2 4 4 4 18 TESTEN RIO 23 4 479 22 LCD11 80 GND10 21 4 2 5 2 gt 0 gt 5 N St N oj o N e e e e e e ej el ej ej A e Ld Ld Ld d j lo gt gt gt gt gt gt gt gt a A aA aj aja O N 9 o oN N a a a a 3 a a a a a 4 a a a a cO Ww oO 1 B2 LCD 15 0 e e e d vec GND r 9 9 9 NNN Nw 592 42484 ME nin 3 85 3 22 PANS1 3 C5 OEN x 3 C2 PANSOm 352 INVSEx MS7727LCD01 4 3
61. FPGA Logic 11 2 1 CPU Board U11 FPGA Logic 1 ypa5010 vhd module name CPLD YPA5010 Top module entity YPA5010 file name YPA5010 vhd rev 0 2003 01 15 Initial release Library library IEEE use IEEE std_logic_1164 all use IEEE std logic unsigned all Entity entity 5010 is port SH7760 ShDatas inout std logic vector 31 downto 0 ShAddrs in std logic vector 25 downto 0 ShCkio in std logic ShCs x in std logic vector 6 downto 0 ShRdWr in std logic ShBs x in std logic ShRd x in std logic ShWe x in std logic vector 3 downto 0 from Syetem Rst_x in std logic from PCIC PcicCs x out std logic PcicRst x outstd logic PcicRdy x in std logic PcSirq x in std logic vector 3 downto 0 from UART UartCsA x out std_logic UartCsB_x out std_logic UartlntA in std logic UART ChA UartlntB in std logic UART ChB from H8 3048 H8lrq x in std logic from Extend Connector ExWait x in std logic Exlrq x in std logic vector 3 downto 0 Attached Documents 7760 01 Users Manual from Debug Extend Board RomSel in std logic Base x in std logic from ID Switch IdDatas std_logic_vector 5 downto 0 to pheliphe x out std_logic EpCe_x out std_logic to SH7760 ShRdy_x out std_logic Irl x out std_logic_vector 3 downto 0 to etc ExAddrs out std logic vector 25
62. R16 18 Chip resistance 1608 MCROSEZH J124 ROHM Chip resistance 1608 MCROSEZH F1004 ROHM R11 and Chip resistance 1608 Chip resistance 1608 Chip resistance 1608 Chip ceramic capacitor 1608 GRM188F11E104ZA01 D Murata Manufacturing C1 4 C9 C13 C15 C18 19 and C21 Chip ceramic capacitor 3216 GMK316BJ105ML TAIYO YUDEN Chip ceramic capacitor 2125 LMK212F475ZG TAIYO YUDEN 7 C5 6 C11 C20 C23 and C25 26 Chip ceramic capacitor 3216 TMK316BJ105ML TAIYO YUDEN 4 7 2 14 16 17 Tantalum electric capacitor TCFGB1C226M8R ROHM C8 B 3528 4 FPC connector FH12 40S 0 5SH PC connector FH12 248 0 58H 3 A FPC connector 12 455 0 55 connector 04FLH SMI TB FPC connector SFW4R 1STE1 FCI 7760 001 Users Manual Attached Documents 11 1 3 Debug Board Parts List Debug Board Parts List U4 and 96 M EPROM onnector CN2 For J1 SW1 and SW2 1 3 LED Manufacturing C15 1 24 11 1 4 Board Parts List Board Parts List Quantity Chip ceramic capacitor GRM188F11E104ZA01 D Murata 5 C1 5 1608 Manufacturing C6 10 Tantalum capacitor 3216 TCFGA1A106M8R ROHM FPC connector FH12 40S 0 5SH Hirose Electric CN1 and CN3 FPC connector 12 245 0 55 Hirose Electric FPC connector 12 105 0 55 Hirose Electric 7760 01 Users Manual 11 2 T Engine
63. Register for Infrared Remote Control Signals IRRRFDR Address OxOOBA Initial value 0x00 07 IRRRDR_ aR IRRRDR IRRRDR_D4 IRRRDR D3 IRRRDR D2 01 IRRRDR_ aR This register is an 8 bit FIFO register for storing received data All the received data can be obtained from this register until it is emptied For details refer to 6 9 8 Infrared Remote Control Data Structure 6 9 6 Transmit FIFO Data Register for Infrared Remote Control Signals IRRSFDR Address 0x00B5 Initial value 0x00 De p po IRRSDR D7 IRRSDR D6 IRRSDR D5 IRRSDR 04 IRRSDR_D3 IRRSDR D2 IRRSDR 01 IRRSDR DO This register is an amp bit FIFO register that stores transmission data Transmission data can be stored until this register is filled with data For details refer to 6 9 8 Infrared Remote Control Data Structure 7760 01 Users Manual Power Supply Controller 6 9 7 RTC Touch Panel Key Input Power Supply Status Register RTKISR This status register indicates the touch panel or key input status Below is a brief description of the status bits for infrared remote control signals Address 0x0090 Initial value 0x00 07 De 05 m os Di o o IRRF POWERIF KEYIF TPIF RTCIF R R RW RW RW RW IRRIF bit A frame of data has not been transmitted or received Initial value A frame of da
64. SLAddr is from Extend Connector port from SH side ShAdr std logic vector 25 downto 0 ShCkio in std logic ShCs2 x in std logic ShOCs4 x in std logic ShOCs5 x std logic ShRdWr in std logic ShBs x in std logic ShRd x in std logic ShWe x in std logic vector 3 downto 0 ExAddrs outstd logic vector 25 downto 0 ExCkio out std_logic ExCs2_x out std_logic 54 out std_logic 55 out std_logic ExRdWr out std_logic ExBs_x out std_logic ExRd_x out std_logic ExWe_x outstd logic vector 3 downto 0 from Controler BusEn Base x in std logic in std logic end SLAddr_r0 Architecture RTL of SLAddr is begin ExAddrs lt ShAdr when BusEn 11 else 00000000000000000000000000 ExCkio lt ShCkio when Base 0 else 1 52 x lt ShCs2 x when Base 07 else 1 7760 01 Users Manual Attached Documents ExOs4 x lt ShCs4 x when Base x 0 else 1 ExCs5 x lt ShCs5 x when Base x 0 else 1 ExRdWr lt ShRdWr when Base_x 0 else 1 ExBs_x lt ShBs_x when Base_x 0 else 1 ExRd_x lt ShRd x when Base_x 0 else 1 ExWe_x lt ShWe x when Base_x 0 else 1111 end RTL 7760 01 Users Manual 7 SLData_r0 vhd module name SH Local Data Bus Interface in Extend Connector entity SLData nam
65. Supported format NEC format and Home Appliance Manufacturer s Association format 2 Function for receiving infrared remote control signals maximum of 255 bytes of the infrared remote control signal can be stored Receive data can be read from the receiving FIFO data register IRRRFDR Infrared remote control signals of a specified format can be received When a frame signal has been received a receiving interrupt may be generated 8 Function for transmitting infrared remote control signals maximum of 255 bytes of the infrared remote control signal can be transmitted Transmit data can be written to the transmitting FIFO data register IRRSFDR Infrared remote control signals of the specified format are transmitted Table 6 9 Infrared Remote Control Registers Infrared remote control register IRRCR 0 00 0 Infrared remote status register IRRSR 0x00B1 Receive data count register for infrared IRRRDNR 0x00B2 1 byte remote control signals Transmit data count register for infrared IRRSDNR 0x00B3 1 byte remote control signals Receive FIFO data register for infrared IRRRFDR 0x00B4 1 byte remote control signals Transmit FIFO data register for infrared IRRSFDR 0x00B5 1 byte remote control signals 7760 01 Users Manual Power Supply Controller 6 9 1 Infrared Remote Control Register IRRCR Address Initial value 0x00 05 2 DO __ o
66. Volume Control Registers register for the right EVRDR 0 0000 Electronic volume data speaker Electronic volume data resister for the left speaker EVLDR 0x00D1 1 byte 6 11 1 Electronic Volume Data Register for the Right Speaker EVRDR Address OxOODO Initial value 0x00 D7 D Ds B 2 Di DO R W R W R W R W R W R W R W R W Values from 0x00 to OxFF can be set 6 11 2 Electronic Volume Data Register for the Left Speaker EVLDR Address 0 0001 Initial value 0x00 07 D ps w m R W R W R W R W R W R W R W R W Values from 0x00 to OxFF can be set 7760 01 Users Manual Power Supply Controller 6 12 Power Supply Controller Initial Values The register values for the power supply controller vary depending on the following conditions Under condition A all the power supply controller registers are initialized The initial value of each register is given in the description of each register in this manual For register values under conditions A to D refer to the following table of RTC registers Condition Condition A The power is turned ON The hard reset switch SW4 is pressed Condition B The power is turned ON The RESTCR SORES bit has been set to 1 The RESTCR SWRES bit has been set to 1 and the reset switch SW2 has been pressed Condition C The RESTCR SWES bit has been cleared to zero and the reset switch SW2 has be
67. board can be read from the SH7760 Various operating conditions can be controlled through these SWs 4 The H UDI debugger to be connected to the H UDI and AUD pins of the SH7760 can be used ROP7760TH001TRK Users Manual Installation 2 4 2 Debug Board Connection Figure 2 4 shows a debug board connection method Connect the debug board to the extension slot CN2 on the T Engine board T Engine Board Connection Extension slot CN1 Figure 2 4 Debug Board Connection CAUTION Turn off the T Engine before connecting the debug board or detaching the EPROM When reattaching the EPROM check the connecting direction as shown in Figure 2 5 00000000 a n D a Q 9 Q Q 9 o o 4 b n 9 9 9 9 9 Figure 2 5 EPROM Connection ROP7760TH001TRK Users Manual Installation 2 4 3 Debug Board Jumper Switches Table 2 2 describes a method for setting the EPROM selection jumper switch J1 on the debugger board For details of a memory map during debug board connection refer to 4 Memory Map Table 2 2 Setting the EPROM Selection Jumper Switch J1 Jumper Setting Description switch J1 Debug board resources are assigned to area 0 on the SH7760 board as shown below Factory setting The flash memory on the TEngine board is assigned to an address range from h 00000000 to h O07FFFFF The EPROM mounted on the debug board is assigned t
68. gt gt lt 5 gt gt 5 gt 79 5 38 EX 34 GND 7760 01 Users Manual Functional Blocks Table 5 1 2 PC Card Interface Connector Signal Pins Memory card card name Ground Carddetection O Carddetection D11 D12 012 013 VO Data bit 13 D13 014 014 D15 VO D15 VO 2 1 Cardenabe vsi Voltagesense vs Volagesene Reseved Reeved 00 1 Addressbii7 7 1 Addressbiti7 Addressbitis 1 Addessbiti8 1 Addressbitio Ato I Addresbit20 20 1 Addresbit21 21 Suppyvotage Programmed supply voltage 2 1 Addressbit2e2 22 NES 23 aa 24 25 NE a R R A17 A18 A19 2 2 A A A A Vi Vi VPP2 A A A A VS2 RESE WAIT INPACK REG SPKR STSCHG D10 Data bit 10 D10 Data bit 10 CD2 Carddetecion ________ CD2 Card detection Ground p Ground 7 Address bit 24 EM EN EM EN Addessbit26 EN em U U 0 1 CC 2 3 4 5 2 A 2 A 2 A 2 A Audio digital waveform Card status change VS2 RESET WAIT
69. gt 8 u gt 1054 05 12C0_SDA L3DATA 1 53 AGNDS SB AGND 2 ibn 1 R80 2 9 3 1 R70 2 a a 2 s SEL AW 2 AGND m 1 R9 2850 23 1 aly QMUTE s 16080603 res 24 8005 002 100 867 1 8 2R 0 21 _ 25 EST gt i Rook 51 82789 AGND AGND 20 TESTI alo 1 1 14M 2 1 R121 2 2 5 14M 2 2 AGND VSSA e e o VIN H L 12 svscik C 47UF Fg gt 10 407 vapcp 7 UM HP A HP SENSE 2 RS F 4 5 4 2 Se 5469 AVCCS voL AVCCS 221 4 vines Boy 82789 026 BYPASS T AVCCS HSJ1602 011010 vn al 67 8 13 T HP OUT ann 8 won 5 ee e 9 wa H2 58 55 AGND A We 14 5 amp 5T n x cs LA 8 gt ass 182 10 vooo pac 22 1 2 mom TON E NY E NY AVCCS ds 1608 0608 7 5 gt 1908008 HB D eo 4 2 88 8 a 52756 418 AGND a AGND 9 re 5 y tives al 97 AGND i 1 53 AVCCS 11 vssD VSSA DAC MAX5413ECD 1 TRS UDA1342TS AG aly L 1 RU s 3 ix AGND 5 K 822 Q1 1 R102 2 3 1
70. main unit Be careful not to apply a mechanical shock Do not touch the connector pins of the product main unit and the target MCU connector pins directly Static electricity may damage the internal circuits Excessive flexing or force of the flexible cable for connecting this product to the emulation probe may break connector Cautions to Be Taken for System Malfunctions If the product malfunctions because of interference like external noise do the following to remedy the trouble 1 Press the RESET button on the board 2 If normal operation is not restored after step 1 shut OFF the product once and then reactivate it ROP7760THO001TRK Users Manual Contents Content Precautions Tor EE P QM RR ddan YR 1 8 Dee a 9 1 1 Package 9 1 2 System 10 1 231 Features acce eto t dx e steer oe Ee deuda a tan i 10 1 2 2 ConfIguratiOl 10 1 3 TsEngine Appeatarice oett Do ee t sue e do 12 1 4 T Engine 16 2 c 18 2 1 HOST SYSTEM
71. of and host system with an RS 232C interface cable accessory Start communication software on the host system and make the following settings Baud rate 115200bps Data length 8 bits Parity bit None Stop bit 1 bit Flow control Xon Xoff After making the above settings turn on the power of T Engine and the title screen screen indicating the execution status of the program stored in the EPROM will be displayed on the communication software as shown below Display Screen 5 7760 Self Debugger Ver x xL C Copyright 2002 2005 Hitachi Ltd rights reserved Ready gt H elp for help messages ROP7760THO01TRK Users Manual Flash Memory Refresh 10 2 T Engine Flash Memory 10 2 1 Refresh Method Figure 10 1 shows how the T Engine flash memory is refreshed As shown in Figure 10 1 the T Engine flash memory is refreshed in such a way that flash memory data is copied to SDRAM and the data transferred from the host system is written to the flash memory H 00000000 H 001FFFFF 01000000 H 017FFFFF H 0C000000 H OC7FFFFF H ODFFFFFF Transfer from the host system Motorola S format object file Figure 10 1 Flash Memory Refresh Below is a description of the T Engine flash memory refresh method 1 As shown on the following screen type FL 0 and hit the Enter key after the title screen appears on the communication software Displa
72. power supply controller refer to 6 2 Serial Communications between SH7760 and the Power Supply Controller 7760 01 Users Manual Power Supply Controller 6 2 Serial Communications between SH7760 and the Power Supply Controller This section describes how serial communications take place between SH7760 and the power supply controller 6 2 1 Serial Format This subsection describes a format for serial communications between SH7760 and the power supply controller 1 Mode Start stop 2 Baud rate 38400 bits second 3 Stop bit 1 bit 4 Start bit 1 bit 5 Parity bit None 6 LSB first 6 2 2 Power Supply Control Register Read Procedure This subsection describes a procedure for reading the power supply control registers 1 SH7760 issues a read command to a power supply controller 2 The power supply controller returns a response to SH7760 A CAUTION Don t issue multiple commands continually from SH7760 that the next command must be issued after a response to the preceding command has been returned from the power supply controller 7760 01 Users Manual Power Supply Controller 6 2 3 Read Command Figure 6 2 shows a read command format SH7760 sends a start code a function code and a register address in this order as a read command 1 Start code 1 byte 2 Function code 1 byte or 2 bytes 3 Register address 2 bytes Figure6 2 Read Command 1 Start code Th
73. set to 1 TDI bit Setting A frame of data has not been transmitted Initial value A frame of data has been transmitted Clear condition 0 is written with the TDI bit set to 1 6 9 3 Receive Data Count Register for Infrared Remote Control Signals IRRRDNR Address 0x00B2 Initial value 0x00 07 De 05 2 Dt IRRRD IRRRD IRRRD_ IRRRD_ IRRRD_ IRRRD D IRRRD_D D7 D6 D5 D4 D3 D2 1 0 R R R R R R R R This register indicates the number of received data items infrared remote control signals stored in the receive FIFO register When this register is 0x00 it indicates that there is no data When the value of this register is OxFF it indicates that the receive FIFO register is full of data 7760 01 Users Manual Power Supply Controller 6 9 4 Transmit Data Count Register for Infrared Remote Control Signals IRRSDNR Address Initial value 0x00 gt De os po IRRSD D7 IRRSD D6 IRRSD D5 IRRSD D4 IRRSD_D3 IRRSD D2 IRRSD 01 IRRSD DO This register indicates the number of data items not transmitted infrared remote control signals stored in the transmit FIFO register When the value of this register is 0x00 it indicates that there is no data When the value of this register is it indicates that the transmit FIFO buffer is full of data 6 9 5 Receive FIFO Data
74. switches SW2 and SW3 on the LCD board Thecursor switch and push button switches are subject to sampling at intervals of 10msec When consecutive three samplings indicate that the same key is being pressed key bit pattern data of the cursor switch and push button switches are output Ifthe switch is turned ON a key ON interrupt occurs If the switch is turned OFF a key OFF interrupt occurs When the same switch is pressed and held an auto repeat interrupt occurs at intervals of 100 to 450msec unit 50msec 6 5 3 Key Switch Registers Table 6 5 summarizes the key switch registers For details of each register refer to 6 5 4 to 6 5 8 Table 6 5 Key Switch Registers KEYCR 0 0060 R W Key auto repeat time register KATIMER 0x0061 RW ibye _____ Key bit pattern register KBITPR 0x0064 IRW 2bytes Key input status register KEYSR 0x0062 R W libyte RTC Touch panel key input Power supply RTKISR 0 0090 R W status register 7760 01 Users Manual Power Supply Controller 6 5 4 Key Control Register Address 0 0060 Initial value 0x20 D7 05 2 Dt o L Rm HW WW RW RW RW 1 KEY STR ___ An application switch key input is disabled Initial value An application switch key input is enabled 2 KEY KEY ONI bit ___ An application switch ON interrupt is disabled Initial value A
75. to the T Engine board and the jumper switch J1 on the debug board is short circuited Table 4 2 Memory Map during Debug Board Connection J1 Open Bus width Area0 16 bits h 00000000 8MB WooFFFEFF 257 memory area 640 90 Fujitsu x 1 01000000 iiid h 013FFFFF M27C800 100F1 STMicro x1 h 01400000 Debug LED area 1B th h 017FFFFF 8 bit debug LED esources 2B 01800000 debug board h 01 BFFFFF 8 bit switch x 2 h 01Cc00000 Switch area Unused area h 01FFFFFF h 02000000 Unused area h O3FFFFFF 1 16bits 04000000 Board control 16B h O7FFFFFF register area Board control register Area2 8 16 32 bits 08000000 Extension area 64MB Extension slot h oBFFFFFF 92 Extension slot CS2 area CS2 asserted Area3 32bits h 0C000000 64MB Po EDS2516APTA 75 ELPIDA x 2 Area4 8 16 32 bits 1 9090009 Extension area 64MB Extension slot h13FFFFFF 94 Extension slot CS4 area CS4 asserted 114000000 Areas 8 16 32 bits Extension area 64MB Extension slot hd47FFFFFF CS5 Extension slot CS5 area 55 asserted Area 6 16 bits h 18000000 Card controller ee PCMCIA area Model name MR SHPC 01 V2T Marubun D TEE Pee This device is simply called SH PCIC h 1A000000 TET i user h 1A7FFFFF UART area ChA 5 16 2550 048 1590 Or Ier ace ER with H8 3048F This device is simply called UART ONE h 1A
76. 0 1 94 L 10UH C 1UF CRS03 U4 V 25V e 22 5 1 e gt gt SW Le Din 27 0 2585 OT ds 2 GND FB 3 EUN lt LT1615ES5 GND GND x N ze HE GND MS7727LCD01 4 2 2 3 4 5 6 7 8 1 LCD CONTROLLER 4 C2 DB 5 0 4 2 5 0 ff 5885 8 lo q al A aj ajaja 4 2 DR 5 0 5 38101519 ew o A aja aja cc 0 10 v st 4 gt gt 4 6 vppe GND5 50 4 DR4 62 39 4 C2 DRS 63 GND4 38 4 4 64 GND8 HsP 37 4 C2 4 2 VCK 65 36 4 2 4 A2 VOE 66 vog DLP 35 STB 4 C2 4 A2 VSP 67 INV 34 INV 4 D2 68 33 3 E2 69 Pc 32 POL 4 C2 DSE U2 31 4 9 S1L50282F23K100 30 DON 1 2 1
77. 002 C V A D conversion A D conversion coordinates x axis cgordinates Figure 6 11 Points of the Drawing Coordinates and A D Conversion Coordinates 7760 01 Users Manual Power Supply Controller Calibration Method 050 060 The SH7760 writes the dot points of points A and B to the registers XAPDR YAPDR XBPDR and YBPDR When point A is pen touched it is signaled by a pen touch interrupt A D conversion result of the pen touched point A is written to the registers XAPAR and YAPAR Next when point B is pen touched it is signaled by a pen touch interrupt The A D conversion result of the pen touched point B is written to the registers XBPAR and YBPAR Calibration takes place according to data in the above steps 1 to 3 Using the following expression the SH7760 calculates the number of dots per data of the X position A D conversion result and that of the Y position A D conversion result Number of dots per data of the X position A D conversion result DX DXA DXB TXB TXA Where TXA TXB DXA DXB Number of dots per data of the Y position A D conversion result DY DY DYA DYB TYB TYA Where TYA TYB DYA DYB DXA X position drawing dot point of point A XAPDR DXB X position drawing dot point of point B TXA X position A D conversion result of point A XAPAR TXB X position A D conversion result of point B XBPAR DYA Y position drawing dot p
78. 0159 vecis 1016 84 602 1064 10 5 10 02 10112 10160 vecie 10 1017 23 a cko 1 87 5 05 6 22 1065 10 5 10 02 10113 10161 vcciz 1018 1066 1085 10114 10162 M4 19 3 ________ wE2 1 B75 C5 1067 10 85 10115 10163 e 1029 1068 10 85 10116 10164 vcc2o 1021 E 1069 1085 10117 10165 voca NT 022 1 B7 6 D2 1070 10 85 10118 10166 1023 wet 1 B7 5 C2 5 C5 6 D2 1071 10 85 0119 10167 48 a RDY 104 1072 10120 10168 1025 52 a UART CSE 502 1073 10121 10169 365362 1026 63 1074 10122 10170 2 365 1027 46 _________ UART 5 4 1075 10123 10171 Toop OM isp TD 362 1028 85 ________ DQMO 1 B7 5 E2 5 C5 6 D2 1076 10124 10172 isp TMS 3 C53 D3 1029 LF 10125 0173 256 1927 22 1078 10126 10174 1031 1079 10127 10175 un 1032 UART CSA 502 1080 10128 10176 GNDO 05 133 99 a 1081 10129 10177 D7 1034 F9 a PCIRG2 4E26 E2 1082 ACKO 1043 10130 10178 D8 4 1035 HE 1083 1045 10131 10179 010 4 1036 E a 187 1084 1005 10132 10180 012 1037 01 1085 10 5 10133 10181 013 4 1038 0 1086 105 10134 10182 anpe 1039 C 1087 1085 10135 10183 4 040 5 _______ POTRGO 1088 101
79. 05 MFID1 LCDD1 8503 AIB2 6 D2 MFIDO LCDDO RDWR a rowr 412 55 MFLINTLCD P ________ LCD 105 Ras pis RAS 565 DON P2 a LcD DON 765 RD CASS FRAME Y RD AJB2 5 E2 5 C2 5ICS G D2 ELCD 7 5 6114 DOM3 4 B25 C5 8 7065 9914 DQM2 4 B25 C5 RSILCD M DISP M DISP 765 DYZ 4 C2 5 C2 5 C5 6 D2 RWILCD 2 765 OW WEO DQMO 4 C2 5 E2 5 C5 6 D2 vcPWCiRQ4 EL vewe 765 vEPWCIRQS E2 a vePWC 7ic5 215 10E210A7 212 10 20 87 ______ ME 1142 212 1021087 _ 19 ________ 1142 210 _______ 5 10621087 FED TRST p rschH2 _ 1142 ASEBRKIBRKACK ASEBRK 10 210 7 19 _______ Foe HD6417760BP200D 4 C7 3 D3 4 D2 5 C2 SH7760 48 MRESET SPI CLK SIM 705 B7 L G RSTO 1 4 3 03 4 02 5 2 SPI CS SIM 5 87 785 HDLTRST 10621087 89 a 11 4112 DMCDAT simp 083 ViGOBACM cTR2 89 a
80. 115 10 3 2 Refresh 118 11 Attached 119 111 Engine Board Parts a 119 11 1 1 CRU Board Parts list ea ba Roca d 119 11 1 2 LOD Board Parts Liste seriis EE EE EENE 122 11 1 3 Debug Board Parts Ist iso tes roodo 123 Thi VO Board Parts c 123 11 2 FERONDO FPGA 124 11 2 1 CPU Board 011 FPGA 1 124 11 3 T Engine Board Circuit 143 11 3 1 CPU Board Circuit Diagrams 57760 01 143 11 3 2 LCD Board Circuit Diagrams 577601 01 4 143 11 3 3 Debug Board Circuit Diagrams MS7760DBG01 3 sese 143 11 3 4 Board Circuit 143 11 4 T Engine Board 143 11 4 1 CPU Board MS7760CP01 3 Dimensions 143 11 4 2 LCD Board MS7760LCD01 4 Dimensions 143 11 4 3 Debug Board MS7760DBG01 3
81. 2 11 04 11 C2 spi px BSa sPLRX 105 8 a 11 4 11 C2 Mte AJE2A B2 CMT 88 a CMT 11 C411 C2 scoL pci sch 1182 NI RO AE2AA2 5 F9 SCL 1 D5 9 B2 sciF2 sciF2 TxD 1065 5 18 _______ 5 1182 212 a sciF2 RXD 1065 220 pcosDA 1 1 059 82 RTS ot SCFFZ RIS 1005 RDY C ROY 4 2 HD6417760BP200D PAS SCFZCTS 10A7 SciF2 A10 H18 a 1 E4 1 851 2 LCD CLK 185 sciri 812 SCIF1_TXD 11 82 mpeoisie 919 MD6 1 SPLRX 165 1 R 10K 813 11 B4 11 82 MDS FRB MDS SCL 105982 RTS 0815 RTS 11 82 MD4 CE2B 17 2CO_SDA 1 059 82 Scri 0814 SOFi CTS 11 C4 11 B2 MD3 CE2A 817 Reto sciri 11 C4 11 B2 16 017 SciFo 16 5 11 82 216 SciFo 816________ SCIF0 11 84 11 82 HD6417760BP200D SciFo sciFo 11 84 11 82 SHT760 2 8 HD6417760BP200D SHT760 1 8 MD7 104 Do not stuff GND Title MS7760CP01P 1 Circuit Diagram Date 7 29 2003 14 52 Sheet 1 of 12 1 2 3
82. 2 408 _ ISP TDI ISP H 303 ISP 33v SH RST 9 101 29 284 19 109 1 ______________ DACK 1 2 38 DRAKG R 10K 4 2 1029 38 284 R 10K 8M4 SH NMI 1028 37 am 13 13 012 1027 39a MDSEL 382 1026 39 Siow 1025 34 16 1 015 1024 33 sr 2 17 veco qoo a ISP TDO 365 38 uci 3 19 Nc2 30 105102 RSTIN 20 11016 H 2107 Tms 28 ISP TMS 3654 68 2 1023 27 RST2 105 23 i019 1022 26 RSTi 7187 10 65 1002 24 1020 1021 25 RSTO 41C7 1 C4 4 D2 5 C2 32 32 48 GRD GRD 00 01 102 103 VBAT 104 3216 1206 105 1 8 2 807843 H8 MD 3 B2 6 F2 MD5SW m Ut DTCi43ZE TL 2 1 6 2 a GND vn 5 3 sense H 9134430 gt _ 15 GRD 5 2 d 4 4 5 gt gt 2 5 gt GND 2 59 22 BAS asses Brg erie seh 97 4974 al 1 gt GRD GRD GRD a 8 GND LSS 3 8 oras Tem 4S9 GND Title MS7760CP01 P1 Circuit Diagram Date 7 29 2003 14 52 Sheet 3 of 12
83. 23 GND 1 83 KEY OUTO ue x LCD9 2 GND E LCD8 FH12 24S 05SH BE e rtl 26 Eri ave aYw _ GND GND 9 9 27 GND LCD7 28 4 LCD6 29 sw3 sw1 sw2 LCD5 30 2 1 4 2 LCDS 5 4 wlio 5 LCD4 31 cops 5 LEDS 32 Q 9 LCD2 SKRHABEO10 e LCD1 34 LCD1 S 1 C3 KEY INOm LCDO 35 CDD 1 C3 KEY 37 1 C3 KEY 2 38 1 B3 VBAT a 1 B3 KEY INA VBAT 40 VBAT T FH12 40S 05SH 155 4 gt 3 3VSB GND m 1 GP1UC101 BPF 38KHZ 2 IR IN 1 A2 a 3 4 4 GND MS7727LCD01 4 1 Last Update 7 10 2002 19 56 2 3 4 5 6 7 8 1 LCD PANEL POWER vec 6 1 82 VCPWCm 22 N GND GND VBAT VDD SI3443DV n api 5 25V 5 4mA DTC143ZE T 1 2 1 82 VEPWCm 2 aM L 10UH 5 de Alte swt oS 2 25 1 OFT pud zee 99 TRI dis N 2 3 GND FB GND LT1615ES5 1 GND GND T GND 258 255 GND VGOFF 15V 0 2mA 1972 1 5045 Kt 94 C 1UF CRS03 V 25V EA 8 2 3 20 ove oT GND GND VGON 12 16 503 15V
84. 28 5158 gs ne LTC1555LEGN 1 8 3 2 NES USB OVC 1 R105 2 2 1 1 USB DM D VBUS En 3 7 24 8005 002 100 867 1 2 5 USB DP SHIELD S__ Do not stuff 160 309 nb 24 5041 0041 10 8343 bs gt x big 0 SLRS 5 55 259 559 GND BT IR ES E23 al 97 jr She Do not stuff GND GND GND GND Title MS7760CP01P 1 Circuit Diagram Date 7 29 2003_14 52 Sheet 7 of 12 1 2 3 4 5 6 7 8 H8 3048F ONE lt 5 33VSB H SBS ons 5 45 rnana 1 5558 55 58 ENA SST 2 2 FERES 2 RES Arm ko SEZBE3 FWE m FWE a lo 4 3888 Zeb Se 2 Cle ols SD78A3 jm mos 5 2222 5
85. 36 H12 10184 04 4 1041 UART INTA 5 4 1089 10137 10185 GNDo 68 a POCRST 672605 1090 10138 10186 GND10 S24 1043 H 091 10139 10187 1044 LHS 1092 10140 10188 GND12 8104 1045 YS 41C7 1 C4 3 D3 5 C2 1093 10141 10189 GND13 H13 os a 556 MAT 1094 10142 10190 GND14 5 1047 6 1095 10143 10191 _ GND16 219 E GBCLK1 11 GBCLK3 913 M4A3 256_192 7FAC M4A3 256_192 7FAC M4A3 256_192 7FAC M4A3 256_192 7FAC 4 25679211 6 a 4 3 25619202 6 a MAA3 256 192 3 6 a 256192 4 6 A250 1 4 25025 2 amp 2 GND19 35 50 01 0 V AZA AGSIC2S A3S C2 63 4 Na 1 M13 2 ADAA A2 GND23 3 GND24 4 41C4 4 B2 GND25 _ 6 00 4026 2 GND26 7 POIROT 4826 2 GND27 8 PCIRQ2 4 26 2 2 4 3 9 PCIRQS 4 26 2 M4A3 256_192 7FAC 9 10 6 Title MS7760CP01P 1 Circuit Diagram Date 7 29 2003 14 52 Sheet 4 of 12 1 2 3 4 5 6 7 8 FLASH MEMORY amp SDRAM M AZA AGA ESS C26 C2 1431 25026 2 A 5
86. 5 LCDDiA 22 T 57 23 100015 23 renis P RESET 58 reser 2 24 5 25 59 25 FH12 24S 0 5SH 1 85 26 ND E 27 PREG 51 27 a 62 185 185 LCD DON 28 DON 63 ovonsrsonar dm E 185 M DISP 29 M DISP E 5 P Do 5 185 FLM FLM P 32 P 165 VEPWC VEPWC teta 67 15 VCPWC 32 10616 PCs E 34 t 7 31 5027 068 130 833 31 5027 068 130 833 33 35 GND GND 92 IR IN 36 TRIN 37 38 39 40 GRD e x 235 x ug il 1 8 1 ES GND OUT3 32v 33V zu 2 2 3 w2 stl 33 165 SIM ifon 3 cscik 83282 DTCi43ZE TL 3 4 547 ku 165 SIM 2 mN 15 4 2 CA USB ET TPS2014D 165 SIM D 3 vo H4 5 C5 GND 28 vec H eu 5 12 7 a BEA SIM M2 X 8 ca dip SIM 1 7 ci 10 04 5036 008 110 862 8 9 T 5 gt T u gt 52 41
87. 760 External Dec 105 8 I Engine Exterision Slot e go Sk e oS ue Do Gunn ee So Da RE 106 8 1 Extension Slot SpecifICatiors Cedere ce ducis Ue deca duode UE But caue x e dit dan de ne 106 8 2 Extension Slot Signal Assignment 4 444040 107 9 Daughter Board Design Guilde 108 9 1 Daughter Board Dimensions E eye tue DER 108 9 2 Daughter Board Power 108 9 3 Daughter Board 109 9 4 Daughter Board WAITH Output tenet 109 9 5 Extension Slot AG Sore Eee BERE tue Spe e deux Ese Due SEE 110 10 Flash Memory Relresh iro ba becas Er ia 112 10 1 Preparation for Flash Memory Refresh 112 10 2 Bro Flash 113 10 2 1 113 10 3 Power Supply Controllers Internal Flash 115 ROP7760TH001TRK Users Manual Contents 10 3 1 Refresh
88. 7760 IRL 11 EXAR Homepage http www exar com Serial controller ST16C2550 RS 232C I F driver 15 pin Acdaress Serial connector 5 3223 Data bus Power supply controller 8 3048F ONE Control signal SCI chanel 1 IRIZ 4 FPGA AREL IRLO 7 3728 gt Figure 5 4 Serial Interface Block 7760 01 Users Manual Functional Blocks 5 3 2 Connector Pins Figure 5 5 shows the pins of a 15 pin serial interface connector CN1 15 pin serial connector Model name 15 15 Maker Honda Tsushin kogyo 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Figure 5 5 15 pin Serial Interface Connector Pins CN1 7760 01 Users Manual Functional Blocks 5 3 3 Register Map Tables 5 4 and 5 5 show register maps for the serial interface controller registers Each of the serial interface control registers must be accessed in words If access takes place in words data in the low order 8 bits D7 to DO will become effective Table 5 4 Serial Interface Controller Register Map Channel A Initial value Register name at read Register name at write Remarks ite H BA000000 RHR THR LCR bit7 0 ReceiveHoldingRegister TransferHoldingRegister H BA000000 DLL DLL LCR bit7 1 LSB of Divisor Latch LSB of Divisor Latch IER IER LCR bit7 0 InterruptEnableRegister InterruptEnableR
89. 800000 This device is used as h 1AFFFFFF UARTarea ChB Same as above interface with the host The DIP switch 18000000 h1BFFFFFF settings are read h 1C000000 Reserved h1FFFFFFF ROP7760TH001TRK Users Manual Memory Map Table 4 3 Memory Map during Debug Board Connection J1 short circuited Bus width Area0 16bits 00000000 DL o T 16 bits h 90900000 256kB h O03FFFFF M27C800 100F1 ST Micro x 300809 Debug LED area n 007FFFFF 2 salina LER Resources on h 20800000 2 the debug board 8 bit switch x 2 h OOBFFFFF Switch area h 09500008 OOFFEFFF h 01 000000 O1FFFFFF 90TN Fujitsu x h 02000000 Unused area h O3FFFFFF Area 1 16 bits h 0000809 Board control register 168 h 07FFFFFF area Board control register Area2 8 16 32 bits 1108900800 64MB Extension slot h OBFFFFFF Extension slot CS2 area 52 asserted Area 3 32 bits 0890998 SDRAM area 64MB h OFFFFFFF EDS2516APTA 75 ELPIDA x 2 4 8 16 32 bits h 10000009 64MB h i3FFFFFF Extension area CS4 Extension slot CS4 area CS4 asserted 5 8 16 32 bits h 14000000 E 64MB Extension slot h7FFFFFF Xtension rea Extension slot CS5 area CS5 asserted Area 6 16 bits h 18000000 Card controller Model name MR SHPC 01 V2T Marubun N
90. BCS KEY a N 7 7 8 5 KEY IN1 a Li Li TIATBCS KEY INO 5 5 3C28A4 SH CE SROM CS Title MS7760CP01P 1 Circuit Diagram Date 7 29 2003 14 52 Sheet 8 of 12 1 2 3 4 5 6 7 8 1 5 AVCCS 5 Re R 24 8005 002 100 867 BLMISPGSDOSNT D U14 Do not stuff 245 550 5 8 vourL 1 26 c u27 245 581 SCK g VOUTR 24 1 2 2 17 C ATUF C ATUF 215 ws ws gt 245 851 status 2 ges HP ase mi 22 4 n VREF voL AVCCS 1 E 5 13 L3MODE 4 7_ Bypass F 1 D5 D5 I2CO SCL m 14 gc 2789 LM4865MM Do not stuff 15 gt d 8
91. CIF1_RXD SCIF1_CLK SCIFI CLK SCIFI RTS SCIFI RTS CTS SCIF1 CTS IIC SCL Figure 5 13 Board Control Block ROP7760THO001TRK Users Manual Functional Blocks 5 7 2 Connector Through Hole Pin Assignments Tables 5 14 to 5 22 show the connector through hole pin assignments on the board Table 5 14 A D Converter Connector CN5 Pin Assignments Signal Name 1 AVecADC 2 AN3 6 ADC Table 5 15 2 I F Connector CN6 Pin Assignments Table 5 16 HCAN2 Connector Pin Assignments 1 2 3 CAN Table 5 17 Connector CN8 Pin Assignments 1 2 _ _ Table 5 18 SCIF Connector CN9 Pin Assignments Table 5 19 SCIF Connector CN10 Pin Assignments Signal Name Eu SCIFO TXD 2 SOFORXD ROP7760THO001TRK Users Manual Functional Blocks Table 5 20 5V Power Supply Connector CN6 Pin Assignments 5V ot Table 5 21 3 3V Power Supply Connector CN6 Pin Assignments 7760 01 Users Manual Power Supply Controller 6 Power Supply Controller 6 1 Power Supply Controller Functions The H8 3048F ONE power supply controller simply called the power supply controller provides the following control functions with firmware stored in the internal memory following functions can be contro
92. Cnt port map 5 x gt PcSirq x UartlntA UartlntA UartlntB Exlrq x gt Exlrq x H8lrq x H8lrq x IrqEna gt IrqEna Irl x gt x 7760 01 Users Manual U IntReg y U IdReg IntReg_rO port map Addrs gt ShAddrs 3 downto 1 IntRegCs gt IntRegCs Rd x gt ShRd x Wr x gt ShWe 0 WrDatas gt ShDatas 3 downto 0 Rst gt Rst RdDatas gt IntRegDatas IrqEna gt IrqEna IdReg port map IdRegCs gt IdRegCs Rd_x gt ShRd_x IdDatas gt ldDatas RdDatas gt ldRegDatas U_SLAddr SLAddr_r0 port map U_SLData end RTL ShAdr gt ShAdars ShCkio gt ShCkio ShCs2_x gt ShCs_x 2 ShCs4_x gt ShCs x 4 ShCsb5 x gt ShCs x 5 ShRdWr gt ShRdWr ShBs_x gt ShBs_x ShRd_x gt ShRd x ShWe x gt ShWe x ExAddrs gt ExAddrs ExCkio gt ExCkio ExCs2 x gt ExCs2 x 54 x gt ExCs4_x ExOs5 x gt 55 x ExRdWr gt ExRdWr ExBs x ExBs x ExRd x gt ExRd x ExWe x ExWe x BusEn BusEn Base x Base x SLData r0 port ShDin gt ShDatas ShDout ExRaDatas ExDatas gt ExDatas BusEn BusEn RdWr gt ShRdWr Attached Documents 7760 01 Users Manual 2 AddrDec_r0 vhd module name Address Decoder for MS7760CP01P 0 entity AddrDec_r0 file name AddrDe
93. D 28 EDS2516APTA 75 EDS2516APTA 75 1 87 41 2 5 5 6 02 DOMI No We 83957 AID2 53 o 1 2 _ 187 RAS 1 7 1 4 3 03 4 02 RSTO 12 RESET 1 B7 4 B2 5 E2 5 C2 6 D2 RD MBM29DL640E90TN 2 ROWR 4 GRD 1 B74 B2 1 B74 B2 WE2 DQM2 w MIAZAIABAIESSASSC2 0131 0 1 87 41 2 5 2 6 02 DOM 1 B7 41C2 5 E2 6 D2 DOMO 385 ABT AIB2 F2 4 385 187 4 yes 33v 33V 33V 33V 3 BS 5 MEE a a d AAA AEGAIA2 Sg e GND GND 42 UART CSB cse TTSA TTSA 8M 4 2 UART 5 DTR 1 B7A B2 5 C2 5 C5 6 D2 RD OR DSRA 09 4 B7 4 C2 5 C5 6 D2 DQMO 159 iow RADY 184 RXRDYB 310 RXRDYA 6 TXRDYB 430 TXRDYA 303 RST 36 REsET 1 a UART 402 30 UART INTA 402 am H8 13 OP28 OPA 8 16 2550 048 uns GRD GND Title MS7760CP01P 1 Circuit Diagram Date 7 29 2003_14 52 Sheet 5 of 12 1 2 3 4 5 7 M AAAEBAIAZSID2IA2 A D5 0 u12 50 25 2 saz 22 SA20 SAi9 sais SA17 16 SA15 SA14 SAi2 SA11 saio 5 9 sas 9 13 4 3 AVCCS CARD 6 4 7 83 7 82 26 avcc2 12
94. DANGER AN WARNING N CAUTION CAUTION IMPORTANT This symbol represents a warning about safety It is used to arouse caution about a potential danger that will possibly inflict an injury on persons To avoid a possible injury or death please be sure to observe the safety message that follows this symbol DANGER indicates an imminently dangerous situation that will cause death or heavy wound unless it is avoided However there are no instances of such danger for the product presented in this manual WARNING indicates a potentially dangerous situation that will cause death or heavy wound unless it is avoided CAUTION indicates a potentially dangerous situation that will cause a slight injury or a medium degree injury unless it is avoided CAUTION with no safety warning symbols attached indicates a potentially dangerous situation that will cause property damage unless it is avoided This is used in operation procedures or explanatory descriptions to convey exceptional conditions or cautions to the user In addition to the five above the following are also used as appropriate Zxmeans WARNING or CAUTION Example amp means PROHIBITION Example CAUTION AGAINST AN ELECTRIC SHOCK QpisasseveLy PROHIBITED means A FORCIBLE ACTION Example QC THE POWER CABLE FROM THE RECEPTACLE ROP7760TH001TRK Users Manual Precautions for Safety WARNING Warnings for AC Power Supply f the attached AC pow
95. H001TRK Users Manual Daughter Board Design Guide 9 Daughter Board Design Guide This chapter describes the design of the daughter board to be connected to the extension slot T Engine The daughter board may contain user specific devices and can be controlled by the address bus data bus and control signals or serial signals start stop of the SH7760 that connect to the extension slots of T Engine 9 1 Daughter Board Dimensions The recommended daughter board size is the CPU board size 120mm x 75mm of T Engine 9 2 Daughter Board Power Supply Table 9 1 shows the voltage and current that can be supplied from T Engine to a daughter board When a daughter board requires more current a power supply must be mounted on the daughter board Table 9 1 Voltage and Current to the Daughter Board Extension slot signal Output Permissible Remarks name voltage current 3 3V 3 3V 250mA 3 3V Supplied when the SH7760 is turned ON 3 3VSB 3 3VSB Always supplied when the AC adapter is connected 250 Supplied when the SH7760 is turned ON CAUTION When peripheral device operating on the bus power via the USB has been connected T Engine or the PCMCIA card is in use the permissible current is the current obtained by subtracting the dissipation current of the device and card from the permissible current ROP7760TH001TRK Users Manual Daughter Board Design Guide 9 3 Daughter Board Stack A maximum of 3 daughter bo
96. H12 408 0 5SH Model name FH12 248 0 58H Maker Hirose Electric Co LTD Maker Hirose Electric Co LTD Figure 5 7 LCD Interface Connector CN5 CN6 Pins Table 5 6 LCD Interface Connector CN5 Signals 3 ver 21 our 2 22 1 014 OUT LCDC 3 23 6015 OUT 4 Powersupply 24 GND Powersupply 5 Unused 25 Powersupply e 1000 our ooo coc 7 OUT coc 27 OUT 1002 8 LCD2 OUT 28 DON 1092 9 tco OUT 29 MDISP 1000 OUT 33 Unused 14 Powersupply 34 GND Powersupply 15 GND Powersupply 35 GND Powersupply 17 tco OUT 37 33V Powersupply 18 OUT 33V Powersupply 19 OUT LODC 39 33V Powersupply 20 16012 our 4o 33V Power supply ROP7760THO001TRK Users Manual Functional Blocks Table5 7 LCD Interface Connector CN6 Signals Pin Signal Remarks __ Signalname Remarks 1 Powersupply 13 5 2 Powersupply 14 PADIRQ NN PAD
97. IF 6 KEY INS IN KEYVF 18 Reser OUT Reset 8 KEY OUTO OUT KEY IF 20 LCD PWRDY LCD power supply 9 kEvour 21 Gnd Powersupply 10 our OUT Keyur 22 Powersupply Powersupply 23 33 58 Powersupply 12 and Powersupply 24 33VSB Powersupply 5 4 3 Register Map Table 5 8 shows a register map for the LCD controller Table 5 8 LCD Controller Registers Data format register Scan mode register H FE300C08 0 000000 Starting address register for fetching upper data on the display panel H FE300COC H 0C000000 Starting address register for fetching lower data on the display panel H FE300C10 H 0280 Data line address offset register for fetching display data H FE300C12 H 0000 Palette control register H FE300800 Palette data register H FE300BFC H FE300C14 H AF52 Horizontal character number register H FE300C16 H 0050 Horizontal synchronization signal register H FE300C18 H O1DF Vertical display line number register H FE300C1A H O1DF Vertical total line number Ea TE ERIT H FE300C1C H O1DF Vertical Vertical synchronization signal register signal register H FE300C1E H 000C AC modulation signal toggle line number register H FE300C20 0000 Interrupt control register H FE300C24 H 0010 Power management mode register H FE300C26 H F606 Power control seq
98. L640E 90TN Fujitsu x 1 h 00100000 Unused area h O3FFFFFF 1 bits 04000090 Board control register 16 h Board control register 2 Ll 6 32 bits h 08000090 inaa 64MB Extension slot h OBFFFFFF Extension slot CS2 area CS2 asserted Area 3 32 bits h 0C000000 SDRAM area 2082 75 ELPIDA x h OFFFFFFF Area4 8 16 32 bits h 10000000 64MB Extension slot Extension area CS4 Extension slot CS4 area 54 asserted h 13FFFFFF m 5 8 16 32bits h 64MB Extension slot Extension area CS5 Extension slot CS5 area 5 asserted h 17FFFFFF 6 16 bits Card controller n18000000 Model name MR SHPC 01 V2T os Marubun This device is simply called SH PCIC h 1A000000 This device is UART UART area ChA Model name ST16C2550CQ48 EXAR 4 This device is simply called UART ONE h 1A800000 This device is used as h 1AFFFFFF UART area ChB Same as above interface with the host h 1B000000 switch ID register area settings are read h 1BFFFFFF h 1C000000 Area 7 n Reserved CABE PCMCIA area h 1A7FFFFF ROP7760TH001TRK Users Manual Memory Map 4 2 Memory Map during Debug Board Connection Table 4 2 shows a memory map for the SH7760 when the debug board is connected to the T Engine board and the jumper switch J1 on the debug board is open Table 4 3 also shows a memory map for the SH7760 when the debug board is connected
99. M This device is simply called SH PCIC h 1A000000 UART UART area ChA Model name ST16C2550CQ48 EXAR This device is simply called UART This device is used for interface with H8 3048F ONE h 1A800000 This device is used as an UART area ChB Same as above interface with thie host ID register area The DIP switch h 1BFFFFFF settings are read h 1C000000 Area 7 Reserved h 1FFFFFFF h 1A7FFFFF h 1AFFFFFF 7760 01 Users Manual Functional Blocks 5 Functional Blocks 5 1 PCMCIA 5 1 1 Block Description Figure 5 1 shows the PCMCIA control block As shown in Figure 5 1 the PCMCIA control block contains a controller MR SHPC 01 V2 from Marubun Corporation a 68 pin PC card interface connector CN3 and a power supply controller IC TPS2211DB from This controller interfaces with the card s conforming to the PC Card Standard 97 and has the following features Internal memory windows 2 windows and I O window one window Card access timing adjustment function One step read write buffer Endian internal control circuit Support for 5 0V 3 3V cards External buffer not required Internal interrupt steering function Power down function Internal suspend function There are four kinds of controller interrupts SIRQ3 to SIRQO hputs to the H7760 are made by the IRL codes For details refer to Marubun s MR SHPC 01 V2 Manual Marubun Homepage http www m
100. O When a value of 1 is read from a bit the corresponding SW is turned off When a value of 0 is read from the bit the corresponding SW is turned on ROP7760TH001TRK Users Manual Installation 2 4 6 H UDI Debugger Connection The debug board allows the H UDI debugger to be connected to the pin 36 CN2 of the H UDI Hitachi User Debug Interface connector Connect the H UDI and AUD pins of the SH7760 board to the H UDI connector Figure 2 6 shows a method for connecting the H UDI debugger Connect an H UDI debugger cable to the H UDI connector CN2 of the debug board Note that the following H UDI debugger can be connected to T Engine For details on the H UDI debugger connection setup procedure refer to the pertinent manual of the product Renesas Technology Corporation E10A USB Emulator Model name HS80005KCUO2H AUD Hitachi ULSI Systems Co Ltd MY ICE EZ emulator T Engine Board CN2 Maker Hirose Electric Model name DX10M 36SE 36 pins H UDI debugger Host system Debug board Figure 2 6 H UDI Debugger Connection CAUTION Q T Engine permits the connection of only the H UDI debugger that uses the AUD and H UDI pins of the SH7760 board ROP7760TH001TRK Users Manual Switches 3 Switches 3 1 CPU Board Switches Figure 3 1 shows the location of the switches SW1 to SW5 on the CPU board addition this section gives a brief description of each switch in 1 to 5 System reset switch FU
101. REJ10J0782 0100Z 5 5 ROP77601H001THK Users Manual 5 7760 T Engine Development Kit www renesas com Rev 1 00 August 23 2004 Cautions Keep safety first in your circuit designs 1 Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable but there is always the possibility that trouble may occur with them Trouble with semiconductors may lead to personal injury fire or property damage Remember to give due consideration to safety when making your circuit designs with appropriate measures such as i placement of substitutive auxiliary circuits use of nonflammable material or prevention against any malfunction or mishap Notes regarding these materials 1 These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer s application they do not convey any license under any intellectual property rights or any other rights belonging to Renesas Technology Corporation or a third party Renesas Technology Corporation assumes no responsibility for any damage or infringement of any third party s rights originating in the use of any product data diagrams charts programs algorithms or circuit application examples contained in these materials All information contained in these materials including product data diagrams charts program
102. Set the CNTS bit to 1 after updating the value of each counter with the START bit set to 41 6 3 2 RTC Status Register RTCSR Address 0 001 Initial value 0 00 oo 05secF iseF R R RW RW Rw 1 ARF The setting of each alarm register with the AR bit set is not the same as that of each counter register Initial value The setting of each alarm register with the AR bit set is identical to that of each counter register At this time an interrupt occurs if the ARI bit is set to 1 Clear condition 0 is written with the bit set to 1 2 1secF 1secF Setting second has not elapsed yet Initial value A second has elapsed Clear condition 0 is written with the 1secF bit set to 1 3 0 5secF 0 5 bit ___ half second has not elapsed yet Initial value A half second has elapsed yet Clear condition 0 is written with the 0 5secF bit set to 1 7760 01 Users Manual Power Supply Controller 6 3 3 Second Counter SECCNT Address 0 002 Initial value OXXX Not defined 1 second S The counter value is a BCD Binary Coded Decimal value Counting takes place within range from 00 to 59 When the value changes from 59 to 00 a carry is generated in the min
103. T TTS aa Title 577600 001 1 1 Circuit Diagram Date 7 29 2003 14 55 Sheet 1 of 2 11260 1 2 3 4 5 6 7 8 EPROM amp E10A INTERFACE 9 lt ESES af cal e e 33V D E 0115 0 ER x x x x x x x x onz A19 Q15 A 1 2 sri AUDCK AUDCK 17 2 s 16 187 _ AUDATAO 6 2 5 L5 4 an ps 4 187 AUDATAi 5 AUDATA1 71 mE Qo aly 187 _ 2 7 AUDATA2 7 5 2 9 ET 187 w 9 AUDATAS Q6 19 11 5 20 AUDSYNC AUDSYNC DIR GND 10 12
104. ace LCD board interface connector2 n Power on switch Front view AC adapter connection connector Reset switch USB HOST interface connector NMI switch Note The 15 connector is used to test the board prior to shipping from the factory NO connection must be made to this connector Figure 1 5 CPU Board External View ROP7760TH001TRK Users Manual Outline Extension slot 8 bit LED 000009000 16 bit SW EPROM connection jumper switch CN2 H UDI connector Figure 1 6 Debug Board External View 1 CN8 5 CN10 CN6 CN9 CN7 Figure 1 7 I O Board External View ROP7760THO01TRK Users Manual Outline 1 4 T Engine Specifications Table 1 1 summarizes the T Engine function specifications and Table 12 the power supply dimensions and environmental specifications Table 1 1 T Engine Function Specifications Model name HD6417760BP200D RENESAS Technology Input clock 16 6667MHz Operating clock Internal 200 2 x 12 External 66MHz x 4 Package 256 pin BGA mu Flash memory Capacity 8MB EDS2516APTA 75 ELPIDA x2 PC Card I F One slot Controller MR SHPC 01 V2T Marubun Package 144pin TQFP Serial I F 2ch ChA H8 3048F ONE I F Controller ST16C2550CQ48 EXAR ChB Monitor for debugging Package 48pin TQFP Sound Model
105. ards can be stacked When multiple daughter boards are stacked care should be taken for electric capacity Figure 9 2 shows an example of daughter board stacks T Engine Board Extension slot 20 5603 14 0101 861 Daughter board Extension slot 10 5603 14 0101 861 Extension slot 20 5603 14 0101 861 Daughter board Extension slot 10 5603 14 0101 861 Extension slot 20 5603 14 0101 861 Figure 9 2 Daughter Board Stack 9 4 Daughter Board WAIT Output T Engine is provided with a input pin on the extension slot for WAIT input to the daughter board When a is output from the daughter board open collector output must take place to prevent a collision of WAIT output when multiple daughter boards are stacked T Engine Board side Daughter Board side 33V SH7760 FPGA 680 ohm lt Extension slot Extension slot Extension slot device Open collector output RDY IORDY Active Low Active High IORDY Active High Figure 9 3 Extension Slot IORDY Pin Structure ROP7760THO01TRK Users Manual Daughter Board Design Guide 9 5 Extension Slot AC Timing As shown in Figure 9 4 the SH7760 bus signal is output to the extension slot via the bus buffer For this reason the bus signal delays approx 8nsec for the AC timing of the SH7760 bus When designing the daughter board consider this delay Figure 9 5 shows the basic bus timing of the SH7760 For details on SH7760 bus timing refer to the pertinent SH7760 Hardware Ma
106. arubun co jp SH7760 Marubun PCMCIA controller System bus I F Xni PC Card CARD slot IRL2 SIRQ3 A Mu SIRQO Power supply control register 5 0V TPS2211IDB CARD PW GOOD Figure 5 1 PCMCIA Control Block 7760 01 Users Manual Functional Blocks 5 1 2 Connector Pins Table 5 1 summarizes the pins of 68 pin PC card interface connector Table 5 1 1 PC Card Interface Connector Signal Pins Memory card Signal name O Function Signal name O N D Address b it 11 Write enable Address bit 12 Address bit 3 Address bit 0 Data bit 0 O Data bit 1 Data bit 2 16bit I O port zll O 2 round ata bit 3 ata bit 4 ata bit 5 ata bit 6 ata bit 7 ard enable Address bit 10 utput enable ddress bit 11 ddress bit 9 ddress bit 8 ddress bit 13 13 ddress bit 14 A14 Write enable WE IREQ 5 U 1 10 gt amp gt 5 gt gt gt 2 gt mi Nu 02 lt upply voltage rogrammed supply voltage ddress bit 16 Address bit 15 ddress bit 12 ddress bit 7 Address bit 6 ddress bit 5 ddress bit 4 Address bit 3 Address bit 2 ddress bit 1 ddress bit 0 Data bit 0 Data bit 1 Data bit 2 Write Protect 101516 Ground GND VPP1 A16 A15 A12 gt gt gt gt 5
107. ata itself If this register is read the data count and data itself are output in this order 4 The size of received data is set in the received data count register IRRRDNR When two frames have been received the total data count and the two frames of data are set in the received data count register IRRRDNR 7760 01 Users Manual Power Supply Controller For infrared signal transmission 1 When transmission data is transmitted it is written to the transmitting FIFO data register The data count for one frame of transmission data and the data itself are written to this data register In addition this transmission data count is not counted as transmission data 2 The count for data not transmitted is set in the transmission data count register IRRSDNR 3 Data can be written to the transmission data IRRSFDR until the count for data not transmitted IRRSDNR reaches 255 4 When frame of data has been transmitted 1 the IRRIF bit of the RTKISR register is set to 1 An interrupt for transmission completion occurs so long as it is enabled CAUTION To change the type of format the FORMAT value of the same register must be set before the START bit of the IRRCR register is set to 1 When the START bit of the IRRCR register is 0 transmission reception is not guaranteed When the specified size is larger than the IRRRDNR value during a read operation FF is set for excessive read data
108. ation returns 4 Data Read data returns The size of this data is equal to the value specified in the function code 6 2 5 Error Response during a read Operation Figure 6 6 shows the error response format for the read command The power supply controller returns a NAK code and an error code in this order as a response at error occurrence 1 NAK code 2 Error code 1 byte Figure 6 6 Error Response during a Read Operation 1 NAK code This code is fixed at NAK 0x15 2 Error code Table 6 1 summarizes the error codes Table 6 1 Error Codes Error type Invalid function code Invalid register number 7760 01 Users Manual Power Supply Controller 6 2 6 Power Supply Control Register Write Procedure This subsection describes the procedure for writing to a controller control of the power supply controller from SH7760 1 SH7760 issues a write command to the power supply controller 2 The power supply controller returns a response the SH7760 A CAUTION Q Don t issue multiple commands continually from SH7760 Note that the next command must be issued after a response to the preceding command has been returned from the power supply controller 6 2 7 Write Command Figure 6 7 shows the write command format SH7760 sends a start code a function code a register address and data in this order as a write command 1 Start code 2 Function code 3 Register address 4 Register addre
109. avect Ht 8 sas Slave 8 5 33 8 e 3 33V 1 s 4 SAM 10 CARD 7 837 B2 AIAG AES SIC2 5 A3 D 31 0 P D 5O 7 2 8015 5 8 53 VCCDi 8 9014 bind pasate 8 VCCDO 5013 1 VPPD1 5012 15 VPPO VPPDO Spi SD10 ono Z sD9 TPS22111DB 308 1 507 ETE GND 2 CARD PW 6F2 402632 RST 806 ee HD74LVIGOSACM 805 cps 33 E 33V 5 504 905 415 415 802 Box EC 5 1 97 al O 1874 82 BS c xBS XCCED GND GND 2 CS 10 xcs XCCET 1 87 4 82 5 2 5 2 5 5 RD 39 XSRD XCIORD 783 W BZAIC2S C2S CS WE1 5 XSWET XCIOWR 783 1 7 4 25 25 5 WEO XSWEO XCOE 482 POROY XSWNT XCWE CBVD2 SPKR AJE24 B2 CBVDi STSCHG 1420 51402 XCCD2 143 XCCDi 4 402 14 5800 CRDY BSY x XCREG PREG 703 gi SSPKR OUT XCCWAIT PWT rou SLED OUT CWP XOSE Posie CRESET PRESET 7 03 86 Ra25 XCINPACK 763 5 WSZ 88 Raz ST 8 raw XCVCC3 ves ecs 6 2 MDSSW 93 ENDIAN XCVCCS voce ecs 4 5 test CVPP1 VPP1 ecs ecs 607 CARD PW 8 caRD_Pw_GooD m CARD
110. bient gas no corrosive gas Dimensions CPU board 120mm x 75mm LCD board 120mm x 75mm Debug board 101mm x 75mm board 101mm x 75mm Table 1 3 Permissible Current Supplied Externally by T Engine Supply Voltage Supply voltage Permissible current Locations subject to current supply 5V 250mA PCMCIA card power supply USB bus power e Extension slot 3 3V 250mA PCMCIA card power supply e Extension slot CAUTION Table 1 2 shows the maximum dissipation current of comprising only the CPU board LCD board debug board and board without external devices Table 1 3 shows the sum of permissible current in all the powered devices on T Engine Accordingly when a current of 100mA is used for the PCMCIA card supply voltage 5 the currents of the USB bus power or extension slot is 150mA 250mA to 100 This is true for the supply voltage 3 3V When the PCMCIA card etc is powered from the internal power supply of T Engine the current must not exceed the permissible current of each power supply shown in Table 1 3 Otherwise there is a risk of electric shock heat or fire ROP7760TH001TRK Users Manual Installation 2 Installation 2 1 Host System Connection To use T monitor connect the serial interface connector CN1 of the TEngine board with an RS 232C interface cable accessory Figure 2 1 shows the host system connection method Figure 2 2 shows the pins of the serial interface connec
111. c rO vhd rev 0 2003 01 15 Initial release library IEEE use IEEE std logic 1164 all use IEEE std logic unsigned all entity AddrDec 0 is port ShAdr in std logic vector 25 downto 23 ShCsO0 x std logic ShOCs1 x in std logic ShCs2 x in std logic ShCs4 x in std logic ShCs5 x std logic ShCs6 x std logic ShRdWr in std logic RomSel in std logic Base x in std logic ExWait x in std logic x in std logic x out std_logic EpCe_x out std_logic IntRegCs out std_logic 5 out std_logic UartCsA x out std_logic UartCsB_x out std_logic IdRegCs out std_logic BusEn out std_logic ShRdy_x out std_logic end AddrDec r0 Architecture RTL of AddrDec r0 is begin decode Attached Documents FlCe x lt 0 when ShCs0 0 and Base 1 and ShAdr 25 0 and ShAdr 24 0 7760 01 Users Manual Attached Documents or 50 0 and Base x 0 and RomSel 1 and ShAdr 25 0 and ShAdr 24 0 or ShCs0 x 0 and Base x 0 and RomSel 0 and ShAdr 25 0 and ShAdr 24 1 else 1 EpCe x lt 0 when ShCs0_x 0 and Base x 0 and RomSel 1 and ShAdr 25 0 and ShAdr 24 1 or ShCs0_x 0 and Base x 0 and RomSel 0 and ShAdr 25 0 and ShAdr 24 07 else 1 IntRegCs lt 1 when ShCs1_x 0 else 0 PcicCs_x lt 0 whe
112. ce Connector CN4 Pins Table 5 12 eTRON Interface Connector CN4 Signals 7 e 51 Pins 4 and 8 are connected to the connector 13 for board test Don t use this connector for the other purpose ROP7760THO001TRK Users Manual Functional Blocks 5 6 3 Register Map Table 5 13 shows a register map for the SH7760 SIM card module SIM Table 5 13 SIM Card Module Register Map Bit rate register Wait time register ROP7760THO001TRK Users Manual Functional Blocks 5 7 VO Board 5 7 1 Block Description Figure 5 13 shows the control block of an I O board As shown in Figure 5 13 the SH7760 module pins output signals to the connectors through holes which provide various interfaces with the external device As the connector is not installed when an external pin is to be connected it should be directly connected to the through hole or the connector should be installed The internal modules which output the signals are listed below Hitachi controller area network 2 HCAN2 2ch Serial communication interface SCIF 2ch bus interface 1ch A D converter 4ch Compare match timer CMT For details on each module refer to the pertinent SH7760 Hardware Manual CPU board board CN6 SH7760 CANO_RX CANO_TX NERR CN7 CANO NERR CANI RX CANI TX SCIF0 TXD n mum SCIF0 RXD E SCIF SCIFI TXD TXD SCIF1_RXD S
113. condition 0 is written with the bit set to 1 4 PONSWF PONSWE bit Setting The power on switch has not been turned on for 2sec or more itch has been turned on for 2 sec or more At this time if the PONSWI bit is set to 1 a power on interrupt 1 occurs 0 is written to the bit set to 1 7760 01 Users Manual Power Supply Controller Supplementary description on application switch key input 1 When multiple keys are pressed at the same time the corresponding bits are all set to 1 and a KEY ONF interrupt occurs so long as it is enabled 2 If data in the key bit pattern register changes when multiple keys are pressed at the same time a KEY ONF interrupt occurs so long as it is enabled Example This KEY ONF interrupt occurs when the state with switches SW1 and SW2 pressed simultaneously changes to one with switches SW1 and SW3 pressed simultaneously 3 When multiple keys are released in the state with the keys pressed and held a KEY OFFI interrupt occurs so long as it is enabled 4 When multiple keys are released the key states immediately before key release are retained in the key bit pattern register 7760 01 Users Manual Power Supply Controller 6 5 8 RTC Touch Panel Key Input Power Supply Status Register RTKISR This status register indicates the RTC touch panel or key input status Below is a brief des
114. cri mo 26 and GND 205 SCIFO TXD 27 scro 27 and 215 SCIFO RXD 28 LCDD7 28 205 SCIFO 29 scro mb LCDD6 29 Loops 205 DCi SCL 31 oci LCDD4 3i Ti cpa 205 32 soa LCDD3 32 Ti cpg Faso LCDD2 33 2 FRB 3 34 23 FOE 35 LCDDO 35 2 B3 FSC 36 Dc d Nc 2 B3 m 37 37 283 38 xx 38 283 AVE 39 ewe 39 40 FH12 40S 0 5SH 9 FH12 40S 0 5SH Title MS7760DBG01 2 1 Circuit Diagram Date 7 29 2003_14 58 Sheet 1 of 2 1 2 3 4 5 6 7 8 PORT INTERFACE 5 CNi6 1 2 AVCC 1 1 5 LCDD 15 0 2 1 852 2 1 00 15 0 2 1 2 2 12000 3 1187262 RESET
115. cription of the status bits for key input Address 0x0090 Initial value 0x00 05 o o mar PoweF Rw mw 1 KEYIF KEVIF bit The PONSWF ARKEYF KEY OFFF and KEY ONF bits of the key input status register are all set to 0 Initial value One of the PONSWF ARKEYF KEY OFFF or KEY ONF bits of the key input status register is set to 1 0 is written with the KEYIF bit set to 41 6 6 Power Supply Control This section describes the power supply control functions Table 6 6 summarizes the power supply control registers In addition refer to 6 6 1 to 6 6 3 for details of each register 1 is turned ON or OFF 2 When T Engine is OFF it is turned ON if the power on switch is pressed for 2 seconds or more 3 4 3 T Engine can be turned OFF from the SH7760 4 If the DIP switch SW7 is set to ON T Engine is also turned ON at the same time the power supply controller is turned ON Table 6 6 Power Control Registers sPOWCR 7 RW tbye System power control register 2 SPOWCR2 0x0071 ibyte 7760 01 Users Manual Power Supply Controller 6 6 1 System Power Control Register 1 SPOWCR1 Address 0x0070 Initial value 0x01 07 D3 2 Di ro ca a d spo SISSPOWERO LE
116. ctor 31 downto 0 ShDout outstd logic vector 31 downto 0 ExDatas inout std logic vector 31 downto 0 BusEn in std logic RdWr in std logic end component Signal signal IntRegCs std logic signal IdRegCs std_logic signal Rst std logic signal BusEn std logic signal IntRegDatas std logic vector 15 downto 0 signal IdRegDatas std logic vector 15 downto 0 signal ExRaDatas std logic vector 31 downto 0 signal IrqEna std logic vector 3 downto 0 7760 01 Users Manual Attached Documents Low hierarchy file port map begin Rst lt not Rst x ShDatas lt ExRdDatas or 0000000000000000 amp IntRegDatas or IdRegDatas when IntRegCs 1 or IdRegCs 1 or BusEn 1 ShRd_x 0 else ZZZZZZZZZZZZZZZZZZZZZZ PcicRst_x lt 0 when Rst x 0 or IrqEna 3 1 else 1 opt lt not ShCs x 3 AddrDec port ShAdr gt ShAddrs 25 downto 23 ShCsO x gt ShCs x 0 ShCs1 x ShCs x 1 ShCs2 x gt ShCs x 2 51084 x gt ShCs 4 ShCsb5 x gt ShCs x 5 ShCs6 x gt ShCs x 6 ShRdWr gt ShRdWr RomSel gt RomSel Base_x gt Base_x ExWait_x gt ExWait_x PcicRdy_x gt PcicRdy_x FlCe x gt FlCe EpCe x EpCe x IntRegCs gt IntRegCs PcicCs x gt x UartCsA x gt UartCsA x UartCsB x gt UartCsB x IdRegCs gt IdRegCs BusEn gt BusEn ShRdy_x gt ShRdy_x Irq
117. d cushion material when transporting this product If there is any question or doubt about the packaged product contact your local distributor ROP7760THO01TRK Users Manual Outline 1 2 System Configuration 1 2 1 T Engine Features The following summarizes the main features of T Engine 1 manual covers all information about T Engine including the circuit diagrams connector specifications and internal logic of FPGA employed on this board 2 The peripheral LSI chips PCMCIA controller and sound generator chips are commercially available 3 This board contains the PCMCIA controller sound generator chip SIM card connector etc so that application systems can be developed taking advantage of them 4 This board contains two SH7760 buses address bus and data bus and one extension slot subject to control signal output so that users can connect user specific hardware 1 2 2 T Engine Configuration Figure 1 1 shows a T Engine Board system configuration and Figure 1 2 shows a T Engine block diagram Users must prepare any user specific devices as needed in addition to preparing the T Engine and its accessories ATA card etc Host system SIM 05 USB mouse etc H T Engine Board AC adapter accessory Figure 1 1 System configuration ROP7760THO01TRK Users Manual Outline LCD Board interface SIM Card HP MIC LCDI LCD2 Serial AC adapter
118. dition of T Engine ON T Engine is powered when power supply takes place through the AC adapter OFF T Engine is powered when the power on switch is pressed Factory setting c The SW5 8 switch is connected to SH7760 s pin MD5 The SW5 8 switch is used to set the type of endian for SH7760 operation ON The MD5 pin goes Low to set the big endian for SH7760 operation OFF The MD5 pin goes High to set the little endian for SH7760 operation Factory setting Figure 3 2 Setting the 8 bit DIP Switch 5 System Reset Switch SW4 This switch resets the T Engine hardware All T Engine devices are reset so long as this switch is pressed and held down When this switch is released FEngine is turned off When the power on switch is pressed T Engine is turned on and started In addition if this switch is released while SW5 7 is ON T Engine is also turned on ROP7760TH001TRK Users Manual Switches 3 2 LCD Board Switch The states of the cursor switch SW1 and push button switches SW2 and SW3 are signaled to the SH7760 through the power supply controller For details refer to 6 Power Supply Controller ROP7760TH001TRK Users Manual Memory Map 4 Memory Map 4 1 Memory Map for the T Engine Board Table 4 1 shows an SH7760 memory map for the T Engine board without expansion board Table 4 1 SH7760 Memory Map for T Engine without Expansion Board Area 16 bits 00000000 8MB Flash memory area h O0FFFFFF MBM29D
119. downto 0 ExDatas inoutstd logic vector 31 downto 0 ExCkio out std_logic ExCs2_x out std_logic ExCs4 x out std_logic ExCs5 x out std_logic ExRdWr out std_logic ExBs_x out std_logic ExRd_x out std_logic ExWe_x out std_logic_vector 3 downto 0 opt out std_logic end 5010 Architecture RTL of YPA5010 is component AddrDec rO port ShAdr std logic vector 25 downto 23 ShCsO0 x in std logic ShCs1 x in std logic ShCs2 x in std logic ShOCs4 x in std logic ShCs5 x std logic ShCs6 x std logic ShRdWr in std logic RomSel in std logic Base x std logic ExWait x in std logic x in std logic x out std_logic EpCe_x out std_logic IntRegCs out std_logic PcicCs_x out std_logic UartCsA_x out std_logic UartCsB_x out std_logic IdRegCs out std_logic Attached Documents 7760 01 Users Manual BusEn ShRdy_x component port PcSirq x UartIntA UartIntB Exlrq x H8lrq x IrqEna x component IntReg rO port IntRegCs Rd x Wr x WrDatas Rst RdDatas IrqEna component IdReg port IdRegCs Rd x IdDatas RdDatas component SLAddr_r0 port ShAdr ShCkio ShCs2 x ShOCs4 x ShCsb5 x ShRdWr ShBs_x S
120. e SLData rO vhd rev 0 2003 01 27 Initial release library IEEE use IEEE std_logic_1164 all use IEEE std logic unsigned all entity SLData rO is port from SH side ShDin std logic vector 31 downto 0 ShDout outstd logic vector 31 downto 0 from Extend Connector ExDatas inout std logic vector 31 downto 0 from Controler BusEn in std logic RdWr in std logic end SLData r0 Architecture RTL of SLData 015 begin ExDatas lt ShDin when BusEn 1 and RdWr 0 else ZZZZZZZZZZZZZZZZZZZZAZZAAT ShDout ExDatas when BusEn 1 RdWr 1 else 00000000000000000000000000000000 end RTL Attached Documents ROP7760TH001TRK Users Manual 1 ypa5020 vhd module name CPLD YPA5020 Top module entity YPA5020 file name YPA5020 vhd rev 0 2003 01 28 Initial release library IEEE use IEEE std_logic_1164 all use IEEE std logic unsigned all entity 5020 is port SH7760 ShExtal in std logic form ROM ICE I F ExRstln x in std logic ExNmiln in std logic H8Rst x in std logic from H8 3048 ShRst x in std logic ShNmiln in std logic to SH7760 ShNmiOut out std logic to etc Rst out std_logic Rst_x outstd logic vector 2 downto 0 MdSel out std_logic end YPA5020 Attached Documents 7760 01 Users Manual Architecture RTL of YPA5020 is component RstCnt port S
121. e code is fixed at 0 x 02 2 Function code 1 byte function code specifies the size of data to be read in the lower 4 bits when the upper 4 bits of a function code are 1000 Figure 6 3 shows a function command where the upper 4 bits are 1000 os os o2 po Sieofdaa Figure6 3 Function Command 1 Byte A 2 byte function code specifies the size of data to be read in the lower 12 bits when the upper 4 bits of a function code are 1001 Figure 6 4 shows a function command where the upper 4 bits are 1001 pis pi2 pit oto po pe oz ps os vo pi vo o 1 Figure6 4 Function Command 2 Bytes 3 Register Address The register address specifies the address of the register to be read 7760 01 Users Manual Power Supply Controller 6 2 4 Normal Response during a Read Operation Figure 6 5 shows the response format for the read command The power supply controller returns an ACK code a function code a register address and target data in this order as a response 2 Function code 3 Register address 1 byte or 2 bytes 2 bytes Figure 6 5 Normal Response during a Read Operation 1 ACK code 1 byte 4 Data N byte 1 ACK code The code is fixed at ACK 0x06 2 Function code The same function code as for the read command returns 3 Register address The address of a register subject to a read oper
122. eek month and year BCD code 2 RTC start stop function 3 Alarm interrupt function 4 1sec 0 5sec cyclic interrupt function 3 4 5 Automatic correction function for leap years 6 6 Effective range of operation from January 1 2000 to December 31 2099 Table 6 3 RTC Registers RTC controlregister 00000 R W tibye RTCstatusregister RTCSR 00001 R W tbye Secondcouter 00002 Rw Minute counter 00003 R W tbye Hour counter 00004 R W tbye Day of the week counter WKCNT 00005 R W tbye Day counter 1 DAYCNT 00006 Month counter MONCNT 00007 R W tbye Year counter YRCNT 00008 R W tbye Second alarm counter 9 R W tbye Minute alarm counter MINAR 00004 R W 1bye Houralamcouner HRAR 0x00B R W tbye Day of the week alarm WKAR R W tbye Dayalarmcounter 0 0 0000 R W tbye Monthalarmcouner MONAR 0x00 RTC Touch panel Key input Power supply RTKISR 0x0090 status register 7760 01 Users Manual Power Supply Controller 6 3 1 RTC Control Registe
123. een turned off and on or the reset switch or NMI switch of T Engine has been pressed the following command cannot be executed normally 1 Reading the version Enter the command as shown on the following screen and the version of the written program will be read out Version information is displayed in X X Display Screen Ready h8 ver Hitachi ULSI T Engine PowerController VerX X 2 Reading flash memory data When the command and the address to be read have been entered as shown on the following screen 64 byte data can be read out from the internal flash memory of the power supply controller Display Screen Ready h8d 10000 00010000 00 01 02 00 00 01 02 00 00 01 02 00 00 01 02 00 00010010 00 01 02 00 00 01 02 00 00 01 02 00 00 01 02 00 00010020 00 01 02 00 00 01 02 00 00 01 02 00 00 01 02 00 00010030 00 01 04 CC 00 01 05 2A 00 01 02 00 00 01 05 70 3 Restarting the Power Supply Controller To restart the power supply controller enter the command as shown on the following screen Once the power supply controller is restarted the SH7760 is restarted too Display Screen Ready gt restart ReStart 7760 01 Users Manual Attached Documents 11 Attached Documents 11 1 T Engine Board Parts List 11 1 1 CPU Board Parts list CPU Board Parts List 1 60 PC Card convoler MRSHPCoT2T marun e _ UxrGcm
124. egister DLM DLM LCR bit7 1 MSB of Divisor Latch MSB of Divisor Latch ISR CR InterruptStatusRegister FIFOControlRegister F H BA000006 LCR LCR El ModemControlRegister ModemControlRegister LineStatusRegister ModemStatusRegister ScratchpadRegister ScratchpadRegister Table 5 5 Serial Interface Controller Register Map Channel B Initial value Register name at read Register name at write Remarks ReceiveHoldingRegister TransferHoldingRegister meer MeS LSB of Divisor Latch LSB of Divisor Latch InterruptEnableRegister InterruptEnableRegister _ MSB of Divisor Latch MSB of Divisor Latch mee InterruptStatusRegister FlFOControlRegister 00 LCR LCR H 00 H 01 H 00 H 00 H 60 FF LineControlRegister ModemControlRegister ModemControlRegister LineControlRegister H BA80000A LineStatusRegister mao ModemStatusRegister ee ScratchpadRegister ScratchpadRegister 7760 01 Users Manual Functional Blocks 5 4 LCD 5 4 1 Block Description Figure 5 6 shows the LCD control block As shown in Figure 5 6 the LCD control block contains an internal LCD controller and an LCD panel TFT liquid crystal panel mounted on the LCD board that can display 16 bit RGB data with a resolution of QVGA 240 x 320 In addit
125. en pressed Condition D The SPOWCR1 SPOWER bit has been set to 0 Table 6 12 Values under RTC Register Conditions n RTC Touch Panel Key Input Power RTKISR Initial value Initial value Hold Initial value Supply status register 7760 01 Users Manual Power Supply Controller Figure 6 13 Values under Touch Panel Register Conditions Initial value Initial value Initial value Initial value Initial value Initial value Initial value Initial value Initial value Initial value Hold Hold Hold Hold Initial value Hold Initial value Hold Hold Hold Hold Hold Hold Initial value Hold Hold Hold RTC Touch Panel Key RTKISR Initial value Initial value Hold Initial value Supply status register Table 6 14 Values under Switch Input Register Conditions Abbreviation Condition A Condition B Condition C Condition D Key control register KEYCR Initial value Initial value Initial value Key auto repeat time register KATIMER Initial value Initial value Initial value Key input status register KEYSR Initial value Initial value Initial value Key bit pattern register KBITPR Initial value Initial value Initial value RTC Touch Panel Key RTKISR Initial value Initial value Initial value Supply status register Table 6 15 Values under Power Supply Control Register Conditions Abbreviation Condition A Condition B Condition C Condition D System power control regist
126. en MdSel lt 1 end if end process process ShExtal begin if ShExtal event and ShExtal 1 then MdSel lt MGSel end if end process end RTL Attached Documents ROP7760THO001TRK Users Manual 11 3 T Engine Board Circuit Diagrams 11 3 1 CPU Board Circuit Diagrams MS7760CP01 1 11 3 2 LCD Board Circuit Diagrams MS7760LCD01 4 11 3 3 Debug Board Circuit Diagrams MS7760DBG01 3 11 3 4 I O Board Circuit Diagrams 11 4 T Engine Board Dimensions 11 4 1 CPU Board MS7760CP01 3 Dimensions 11 4 2 LCD Board MS7760LCD01 4 Dimensions 11 4 3 Debug Board MS7760DBG01 3 Dimensions Attached Documents 1 2 3 4 5 6 7 8 CPU SH7760 1 01 0 4 AGAESSC25 A3 6C2 25 0 AEGAIA ID SIA2 LCDD I50 7 5 MFIDIS LCDD15 FLD7 LCDDIS STATUSI D STATUSI 9 2 MFID14 LCDD14 FLD6 LCDDM 26_________ STATUSO 9E2 MFID1S LCDD13 FLDS 1529018 MFID12 LCDD12 FLD4 m 55 55 402 MFID11 LCDD11 FLD3 5 5 an MFID10 LCDD10 FLD2 10010 csi an MFID9 LCDD9 FLD1 quid 41 2 5 5 MFID LCDDB FLDO MFID7 LCDD7 DRAK3 DACK3 csi p an MFID6 LCDD6 DREQ3 55 55 402 MFIDSLCDDSIDRAK2DACK2 MFID4 LCDD4 DREQ2 19 _______ 41B2 5 05 6 F2 MFID3 LCDD3 IRQ7 H MFID2 LCDD2 IROG coke 8 _ 5
127. er 1 SPOWCR 1 Initial value Initial value 2 X position dot calculation A D value XPARDOT3 Initial value Hold X position dot calculation A D value 4 XPARDOT4 Initial value Hold Y position dot calculation A D value YPARDOT Initial value Hold System power snort register 2 SPOWCR2 Initial value Initial value Initial value RTC Touch Panel Key Input Power RTKISR Initial value Initial value Hold Initial value Supply status register 7760 01 Users Manual Power Supply Controller Table 6 16 Values under LED Register Conditions Abbreviation Condition Condition B Condition C Condition D LED register LEDR Initial value Initial value Table 6 17 Values under LCD Front Light Register Conditions Abbreviation Condition Condition B Condition Condition D LCD front light register LCDR Initial value Initial value Table 6 18 Values under Reset Register Conditions Abbreviation Condition A Condition Condition C Condition D Reset control register RESTCR Initial value Initial value Initial value Table 6 19 Values under Infrared Remote Control Register Conditions Abbreviation Condition A Condition B Condition C Condition D Infrared remote control register Initial value Initial value Initial value Infrared remote control status register IRRSR Initial value Initial value Initial value re
128. er cable does fit the receptacle do not alter the AC power cable and do not plug it forcibly Failure to comply may cause electric shock and or fire Use an AC power cable which complies with the safety standard of the country Do not touch the plug of the AC power cable when your hands are wet This may cause electric shock This product is connected signal ground with frame ground If your developing product is transformless not having isolation transformer of AC power this may cause electric shock Also this may give an unrepairable damage to this product and your developing one While developing connect AC power of the product to commercial power through isolation transformer in order to avoid these dangers f other equipment is connected to the same branch circuit care should be taken not to overload the circuit When installing this equipment insure that a reliable ground connection is maintained f you smell a strange odor hear an unusual sound or see smoke coming from this product then disconnect power immediately by unplugging the AC power cable from the outlet Do not use this as it is because of the danger of electric shock and or fire In this case contact your local distributor Before setting up this product and connecting it to other devices turn off power remove a power cable to prevent injury or product damage Warnings to Be Taken for This Product Do not disassemble
129. er value 02 01 00 0 0 0 Sunday 02 01 00 0 0 1 gt Monday 02 01 00 0 1 0 gt Tuesday 0 1 1 gt Wednesdady 02 01 00 02 01 00 1 0 0 gt Thursday 02 01 00 1 0 1 gt Friday 02 01 00 1 1 0 gt Saturday 7760 01 Users Manual Power Supply Controller 6 315 Day Alarm Register DAYAR Address 0 0000 Initial value 0x00 07 05 2 D 1 da aw R NW AW AW AW AW AW The alarm value must be a BCD Binary Coded Decimal code between 1 and 31 January March May July August October and December between 1 and 30 April June September and November between 1 and 28 February in normal year or between 1 and 29 February in leap year 6 3 16 Month Alarm Register MONAR Address OxOOOE Initial value 0x00 57 05 2 Di DO AR October Rw R R RW RW RW NW The alarm value must be a BCD Binary Coded Decimal code between 01 and 12 6 3 17 Panel Key Input Power Supply Status Register RTKISR This status register indicates the RTC touch panel or ley input status The following is a brief description of RTC related status bits Address 0 0090 Initial value 0x00 07 05 D4 pa m o POWERIF
130. eserved H elp for help messages Ready gt 1 H8 3048Fone Flash Memory Change Value Clear data buffer all OXFF Please Send A S format Record ROP7760TH001TRK Users Manual Flash Memory Refresh 3 Refreshing the flash memory of the power supply controller normally completes when the messages H8 flash erase complete and flash write complete sequentially appear on the screen after the Motorola S format object file has been transferred CAUTION 4 When the flash memory of the power supply controller is being refreshed never power OFF T Engine If ignored refreshing may terminate in error or the flash memory may be damaged Display Screen Ready gt fl 1 H8 3048Fone Flash Memory Change Value Clear data buffer all OXFF Please Send A S format Record Start Addrs 00001000 End Addrs 00003020 Transfer complete H8 Flash erase complete Program complete Flash write complete Ready ROP7760THO01TRK Users Manual Flash Memory Refresh 10 3 2 Refresh Check After the internal flash memory of the power supply controller is refreshed the version of the refreshed program or the data stored in the internal flash memory of the power supply controller can be checked by entering the following command However note that the following command can be executed immediately after the internal flash memory of the power supply controller has been refreshed When has b
131. espondence Correspondence between the alarm registers and counters Second alarm register BCD code second counter Minute alarm register BCD code minute counter Hour alarm register BCD code Hour counter Day of the week alarm register 0x00 to 0x07 Day of the week counter Day alarm register BCD code Day counter Month alarm register BCD code Month counter 6 3 11 Second Alarm Register SECAR Address 0 0009 Initial value 0 00 67 De 05 2 m The alarm value must be a BCD Binary Coded Decimal code between 00 59 6 312 Minute Alarm Register MINAR Address 0x000A Initial value 0x00 071 gt Di Do 1 minute AR Rw RW RW RW RW RW WW The alarm value must be a BCD Binary Coded Decimal code between 00 and 59 7760 01 Users Manual Power Supply Controller 6 313 Hour Alarm Register HRAR Address 0x000B Initial value 0x00 Ar The alarm value must be a BCD Binary Coded Decimal code between 00 and 23 6 3 14 Day of the Week Alarm Register WKAR Address 0x000C Initial value 0x00 67 05 2 m AR 0 _Septinary counter value Rw R AW RW BW The alarm value must be set within a range from 0x00 to 0 06 Day of the week and septinary count
132. gure 5 11 this control block contains the SIM card module of the SH7760 the power supply level converter LTC1555LEGN 1 8 and the 8 pin connector to interact with the eTRON card inserted into the eTRON interface connector The eTRON card can be reset by controlling the SH7760 internal SIM card module register SISCMR The control method is shown below Low output from PTE4 The reset pin of the eTRON card is set to Low Reset state High output from PTE4 The reset pin of the eTRON card is set to High Normal state Power supply to the eTRON card is controlled via the power supply controller H8 3048 ONE However when the T Engine board is ON the eTRON card is being powered When inserting or removing the eTRON card be sure to turn off T Engine in advance For more information refer to the pertinent SH7760 Hardware Manual 5 7760 SIM card interface module SIM connector CN4 SIM CLK Power supply level SIM D converter SIM RST LTC1555LEGN 1 8 Power supply controller H8 3048F ONE Figure 5 11 eTRON Interface Control Block ROP7760THO001TRK Users Manual Functional Blocks 5 6 2 Connector Pins Figure 5 12 shows the pins of the SIM card interface connector CN4 Table 5 12 summarizes the signals of the SIM card interface connector eTRON interface connector Model name 03 5036 006 071 862 Maker Kyocera Elco Figure 5 12 eTRON Interfa
133. hExtal in std logic ExRstln x in std logic ShRst x in std logic H8Rst x in std logic RstOut out std_logic MdSel out std_logic Signal signal RstOut std logic Function Low hierarchy port map begin Reset Rst x lt 000 when RstOut 1 else 111 Rst lt RstOut NMI ShNmiOut lt 0 when ShNmiln 0 or ExNmiln 0 else 1 U_RstCnt RstCnt port ShExtal gt ShExtal ExRstln x gt ExHRstln x ShRst x gt ShRst x H8Rst x gt H8Rst x RstOut gt RstOut MdSel gt MdSel end RTL Attached Documents 7760 01 Users Manual 2 RstCnt_r0 vhd module name Reset control for MS7760CP01P 0 entity RstCnt name RstCnt_r0 vhd rev 0 2003 01 15 Initial release library IEEE use IEEE std logic 1164 all use IEEE std logic unsigned all entity RstCnt rO is port ShExtal in std logic ExRstln x in std logic ShRst x in std logic H8Rst x in std logic RstOut out std_logic MdSel out std_logic end RstOnt Architecture RTL of RstCnt_r0 is signal logic begin Reset control RstOut lt 1 When ExRstln x 0 or ShRst 0 or H8Rst x 9 else 0 process ShExtal ExRstln x ShRst x H8Rst begin if ExRstIn x 0 ShRst 0 or H8Rst_x 0 then MdSel lt 0 elsif ShExtal event ShExtal 1 th
134. hRd_x ShWe_x ExAddrs ExCkio ExCs2_x 54 out std_logic out std_logic std logic vector 3 downto 0 in std_logic in std_logic in std_logic_vector 3 downto 0 in std_logic in std_logic_vector 3 downto 0 out std_logic_vector 3 downto 0 in std_logic_vector 3 downto 1 in std logic in std logic std logic in std logic vector 3 downto 0 std logic outstd logic vector 15 downto 0 outstd logic vector 3 downto 0 in std logic std logic in std logic 5 downto 0 outstd logic vector 15 downto 0 std logic vector 25 downto 0 in std logic in std logic std logic in std logic in std logic in std logic in std logic in std logic vector 3 downto 0 outstd logic vector 25 downto 0 out std_logic out std_logic out std logic Attached Documents MR SHPC 01 interrupt ST16C2550 interrupt ST16C2550 interrupt External Slot interrupt H8 3048 interrupt Interrupt enable H7760 IRL 3 0 ROP7760TH001TRK Users Manual 55 ExRdWr ExBs x ExRd x ExWe x BusEn Base x component SLData rO Attached Documents out std_logic out std_logic out std_logic out std_logic out std_logic_vector 3 downto 0 in std logic std logic port ShDin in std logic ve
135. ife is potentially at stake Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes such as apparatus or systems for transportation vehicular medical aerospace nuclear or undersea repeater use The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials If these products or technologies are subject to the Japanese export control restrictions they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination Any diversion or reexport contrary to the export control laws and regulations of Japan and or the country of destination is prohibited Please contact Renesas Technology Corporation for further details on these materials or the products contained therein ROP7760TH001TRK Users Manual Precautions for Safety Precautions for Safety Definitions of Signal Words In both the user s manual and on the product itself several icons are used to insure proper handling of this product and also to prevent injuries to you or other persons or damage to your properties This chapter describes the precautions which should be taken in order to use this product safely and properly Be sure to read this chapter before using this product AN AN
136. ing control register sets a sampling interval for the touch panel Address 0x0022 Initial value 0x01 sampling interval for the touch panel can be set within a range from 20msec to 160 unit 20msec When bit is set to 1 the corresponding sampling interval from 20msec to 160msec is set Note that only the following values can be specified Correspondence between the setting values and sampling intervals 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 20msec 40msec 60msec 80msec 100msec 120msec 140msec 160msec 6 4 4 X Position A D Register XPAR Address 0 0024 Initial value 0x000 oo o XxADtH XADI0 XA DS RB R R R R R 07 05 D4 D3 Di Sa Se Se mg m The X position A D register indicates the A D conversion result of a pen touched X position on the touch panel 7760 01 Users Manual Power Supply Controller 6 4 5 Y Position A D Register YPAR Address 0 0026 Initial value 0x0000 o o o 010 YA YA 08 R R R R The Y position A D register indicates the A D conversion result of a pen touched Y position the touch panel 6 4 6 X Position Dot Register XPDR Address 0x0028 Initial value 0 0000 Di5 pa Di2 DIO oo pan umm
137. ion the SRAM with an internal LCD controller is used for the LCD display VRAM Video RAM Display data is stored in the internal SDRAM of the LCD controller in the order of coordinates 0 0 1 0 and 239 319 from the address set in the register LDSARU of the LCD controller On the LCD panel display data at the upper left corner is handled as data on the origin 0 0 and data at the lower right corner is handled as data on the coordinates 239 319 The front light on the LCD panel can be turned on or off by the power supply controller For details on front light control refer to 6 Power Supply Controller In addition refer to the pertinent SH7760 Hardware Manual for details on the LCD controller LCD Board 239 319 CPU board connection q CPU board connector CN2 connection LCD board connector CN1 Power supply controller connection H8 3048F ONE connector CN6 Ou ane Front light control signal SH7760 LCD controller LCD control signal LCD board connection connector CN5 Data bus Video RAM SDRAM Figure 5 6 LCD Control Block 7760 01 Users Manual Functional Blocks 5 4 2 Connector Pins Figure 5 7 shows the pins of the LCD interface connectors CN5 and CN6 Tables 5 6 and 5 7 summarize the signals of these interface connectors 1 CN5 40 1 CN6 24 LCD interface connector CN5 LCD interface connector Model name F
138. is register will be functionally enhanced in future Don t access this register 6 4 13 YC Position Dot Register YCPDR Address 0x0036 Initial value 0x0000 Di5 04 02 Dio w YCD D15 YCD D14 YCD D13 YCD D12 YCD D11 YCD 010 D9 YCD D8 67 De 04 po YCD D7 YCD 06 05 YCD D4 YCD D3 YCD D2 YCD 01 YCD DO The position dot register indicates the Y dot position of point C where calibration takes place This register will be functionally enhanced in future Don t access this register 7760 01 Users Manual Power Supply Controller 6 4 14 XA Position A D Register XAPAR Address 0x0038 Initial value 0 0000 XA Dio XA 09 R R w 07 De 05 ps The XA position A D register indicates the X position A D conversion result of point A subject to calibration 6 4 15 YA Position A D Register YAPAR Address Initial value 0 0000 o YA Dti YAA 09 YAA De CR R R R mw RW RW D7 D D5 Dt Do YAA 07 YAA D6 YAA 05 YAA D4 YAA D3 YAA 02 YAA 01 YAA DO The YA position A D register indicates the Y position A D conversion result of point A subject to calibration 6 4 16 XB Po
139. l rl 907883 3aNSB MANN SD78A3 g 9 G 8002JF 7 372800M PCCB TIBZS ET amp CT amp EAS C2 H8 TXD1 m L Txbi 1 os vec 4 TIBZ8 E78 CZB EA H8 RXD1 g 8 ext TIBZS ET amp BT amp EASIC2 H8 5 1 2 our 3 30 vss F 7 3728MHZ FH12 10S 0 5SH GND 1 2 33ysB 1 3 88 588385 Rea GND 2s Ok 2 n und A asz z 25525 amp F28 A SROM CS les 2 gg 515455 412 5 ge 7IB7 8 E7 BIE4B A7 9IC2 S29391AFJA avec 13 25 0 a 9420 7 77 A12P24 49 a H SWi 8 7 1207 VOLT 78 48 12 7 79 prani 1 22 47 KEY OUT2 787 7 7 0 2 TXD1 80 2 E a KEY OUTi 787 8 RXDi ee aysi 5158 128 158 8 8 2 48 a KEY u17 pice gize n z9 9 ku 9 vss2 58 CE 7 ck 4 8 VOUT2 8E7 2 scik 818 42 4 PTG ANGIDAO AGPP16 VOUT si 0 85 H8 3048F ONE aspis 41 3
140. lled through the UART from the SH7760 Figure 6 1 shows a power supply controller block diagram 1 RTC real time clock function 2 System power supply 3 3V 5 0V ON OFF control function 8 Touch panel coordinate position read function 4 Key switch input function b Infrared remote control transmission reception function 6 Electronic volume 7 Serial EEPROM read write function These functions can be controlled through the UART chA from SH7760 H8 3048F ONE RVSC348A RTC MAXSAISECD Electronic volume 1 8V ON OFF 8H7727 CPUcore 8 7290 CPU core 3 ON OFF VCC3A SH7727 SDRAM 8H7727 FLASH SH7727 3 3V ON OFF VCC3B UART 5V ON OFF PCMCIA 6v USBHUB USB power Sound Sod generator SIM card SH7727 Reset signal for devices other than H8 3048F Reset circuit RESET 4 NMI PINTII LTCISSSLEGN Power supply MO battery monitoring ST16C2550CQ48 UART Infrared remote control TIOCAS PRO A eTRON socket LCD board TIOCB2 PA7 T P30 P37 8bit LED IRQ4 P94 P66 DIPSWS 8 Receiving unit Figure 6 1 Power Supply Control Block Diagram CAUTION Though the power supply controller s port is connected to the RTSA and CTSA pins of the UART controller ST16C2550 through the circuit the power supply controller does not execute hardware control during communications with SH7760 For details of communications between SH7760 and the
141. ller outputs the data derived from the above expressions to the X position dot register XPDR and Y position dot register YPDR When either value is 0 it does not use the above expression for calculation and outputs only and YPAR data 7760 01 Users Manual Power Supply Controller 6 5 Key Switch Control Figure 6 12 shows the T Engine switches under control by the power supply controller The power supply controller controls the switches SW1 to on the CPU board and the switches SW1to SW3 on the LCD board Power on switch SWI T Engine Board Reset switch CPU board switch NMI switch SW3 Application switch Figure 6 12 T Engine Switch 7760 01 Users Manual Power Supply Controller 6 5 1 CPU Board Switch Control 1 Power on switch SW1 When the 5 7760 is being powered a power on switch interrupt occurs for the SH7760 if the power on switch is pressed and held for 2 seconds or more When T Engine is OFF it is turned ON if the power on switch is pressed and held for 0 5 seconds or more When T Engine is ON it is turned OFF if the power on switch is pressed and held for 2 seconds or more 2 Reset switch SW2 T Engine is turned OFF when the reset switch is pressed 3 NMI switch SW3 An NMI interrupt occurs for the SH7760 when the NMI switch is pressed 6 5 2 LCD Board Switch Control Application Switch 1 Cursor switch SW1 and push button
142. mote control signals remote control signals infrared remote control signals Transmitting FIFO data register for infrared remote control signals Table 6 20 Values under Serial EEPROM Control Register Conditions Abbreviation Condition A Condition Condition Condition D EEPROM control register EEPCR Initial value Initial value Initial value EEPROM data register EEPDR Initial value Initial value Initial value Table 6 21 Values under Electronic Volume Control Register Conditions Abbreviation Condition A Condition Condition Condition D Electronic volume data register for EVRDR Initial value Initial value Initial value the right speaker Electronic volume data register from EVLDR Initial value Initial value Hold Initial value the left speaker ROP7760TH001TRK Users Manual External Interrupts 7 External Interrupts 7 1 SH7760 External Interrupts Figure 7 1 shows a mechanism for the SH7760 interrupt signal Table 7 1 shows the levels for respective interrupt signals As shown in Figure 7 1 interrupt signals from devices within T Engine are sent to the pins IRQ4 PINT11 PINT6 7 of theSH7760 The interrupt signals IRQO to are converted into the IRL signals by FPGA then output to the IRL 3 0 of the SH7760 PCMCIA controller MR SHPC 01 V2T gt IRL 7 IRQO Power supply controller H8 3048F ONE H8 IRQ PB3 UART ST16C2550 INTA TXA RXA TxD RxD
143. n ShCs6_x 0 and ShAdr 25 0 else 1 UartCsA_x lt 0 when ShCs6_x 0 and ShAdr B 100 else 1 UartCsB x lt 0 when ShCs6 x 0 and ShAdr B 101 else 1 IdRegCs lt 1 when ShCs6_x 0 and ShAdr 25 1 and ShAdr 24 1 else 0 BusEn lt 1 when ShCsO x 0 and Base 0 and RomSel 1 and ShAdr 25 0 and ShAdr 24 1 or ShCs0_x 0 Base 0 and RomSel 0 ShAdr 25 0 and ShAdr 24 0 or ShCs2_x 0 and Base x 0 or ShCs4_x 0 and Base x 0 ShCs5_x 0 and Base x 0 else 0 ShRdy_x lt 1 When ExWait x 0 and ShCs2_x 0 and Base x 0 or ExWait 0 and ShCs4_x 0 and Base x 0 ExWait 0 and ShCs5 x 0 and Base x 0 1 and ShCs6_x 0 ShAdr 25 0 else 0 end RTL 7760 01 Users Manual rO vhd module name Interrupt Controler for MS7760CP01 P O entity file name IrqCnt_r0 vhd rev 0 2003 01 28 Initial release library IEEE use IEEE std_logic_1164 all use IEEE std_logic_unsigned all entity IrqCnt_r0 is port Interrupt input PcSirq_x in std logic vector 3 downto 0 UartlntA in std logic in std logic Exlrq x in std logic vector 3 downto 0 H8lrq x std logic Interrupt Enable input IrqEna in std logic vector 3 downto 0 Interrupt ou
144. n application switch key ON interrupt is enabled 3 KEY OFFI KEY OFFI bit ___ An application switch OFF interrupt is disabled Initial value An application switch key OFF interrupt is enabled 4 ARKEYI An application switch auto repeat interrupt is disabled Initial value An application switch auto repeat interrupt is enabled 5 PONSWI PONSWI bit ___ power on switch interrupt is disabled Initial value A power on switch interrupt is enabled 6 NMIE An NMI interrupt is disabled for the SH7760 even when the NMI Switch is pressed 1 An NMI interrupt is disabled for the SH7760 when the NMI switch is pressed Initial value 7760 01 Users Manual Power Supply Controller 6 5 5 Key Auto Repeat Time Register Address 0x0061 Initial value 0x01 67 2 This register sets the auto repeat interrupt generation time The auto repeat interrupt generation time is set at intervals of 100msec to 450msec unit 50msec When one of the bits 100msec to 450 is set the corresponding auto repeat interrupt generation time is set 6 5 6 Key Bit Pattern Register KBIPR Address 0 0064 Initial value 0x0000 ois Dit 1 1 1 amp 1 35 8 o sw R R R R 07 05 2 m
145. name UDA1342TS Philips Package 28pin SSOP Earphone microphone 1 The SH7760 on chip SSI is used Headphone output 1ch to transmit data Microphone input Impedance 2 2KQ The SH7760 on chip is used Sensitivity 51 to select the mode Headphone output Impedance 320 USB Host Controller SH7760 on chip USB Host Display color 262 144 colors Display area 240 H x 320 V Controller SH7760 on chip LCDC Power supply controller H8 3048F ONE The control SH7760 working Model name HD64F3048BVTE25 for power supply control RTC Renesas Technology or tablet interface infrared Operating frequency 7 3728 2 remote control must be Package 100 interfaced via the serial chA Model name RV5C348B RICOH Via the H8 3048F ONE Package 10pin SSOP G Via the H8 3048F ONE Made nane ALS To be mounted on the LCD Package 16pin SSOP board Serial EEPROM Capacity 512 bytes Via the H8 3048F ONE Model name S 29391AFJA SII Transmission Model name GL100MNOMP SHARP Infrared remote control Transmission carrier 38KHz Reception Model name GP1UC101 SHARP Transmission carrier 38KHz Touch panel I F Via theH8 3048F ONE ROP7760THO01TRK Users Manual Outline Table 1 2 Power supply Dimensions and Environmental Specifications of the T Engine Board Environment Operating conditions Temperature 10 35 C Humidity 30 to 85 RH no dew condensation occurs Am
146. nfrared Remote Control Signals 95 6 9 4 Transmit Data Count Register for Infrared Remote Control Signals IRRSDNR 96 6 9 5 Receive FIFO Data Register for Infrared Remote Control Signals IRRRFDR 96 6 9 6 Transmit FIFO Data Register for Infrared Remote Control Signals 96 6 9 7 RTC Touch Panel Key Input Power Supply Status Register 97 6 9 8 Infrared Remote Control Data 97 6 10 Serial EEPROM 99 6 10 1 EEPROM Control Register EEPCR 99 6 10 2 EEPROM Data Register nennen nennen enin nne 99 6 10 3 Serial EEPROM Operation 100 6 11 Electronic Volume iecit decetero eS eese peine Soter me cede hele va coda direct su con Ede SU 101 6 11 1 Electronic Volume Data Register for the Right Speaker 101 6 11 2 Electronic Volume Data Register for the Left Speaker 101 6 12 Power Supply Controller Initial Valtos 4 102 S urine c 105 11 SH
147. nnector CN7 USB power USB PENC dipl USB DM Figure 5 2 USB Host Control Block 7760 01 Users Manual Functional Blocks 5 2 2 Connector Pins Figure 5 3 shows the pins of the USB host connector CN7 VBUS DATA CN7 USB host connector TypeA DATA Model name 20 5041 004 100 834 Maker Kyocera Elco Figure 5 3 USB Host Connector CN7 Pins 5 2 3 Register Map Table 5 3 shows a register map for the internal USB host controller of the 5 7760 Table5 3 USB Host Controller Register H FE341000 Shared memory area H FE342FFF 7760 01 Users Manual Functional Blocks 5 3 UART 5 3 1 Block Description Figure 5 4 shows the UART control block As shown in Figure 5 4 the UART control block contains the controller ST16C2550 from EXAR RS232C interface driver and 15 pin connector CN1 This controller uses the clock pulses 7 3728MHz supplied from the power supply controller H8 3048F ONE for operations and determines a baud rate transfer rate using these pulses as reference This controller has been provided with 2channel UART device Channel A is used to communicate with the power supply controller H8 3048F ONE Because channel B is connected to a 15 pin RS 232C connector CN1 it can be used as a debug interface if it is connected to a PC In addition channel A INTA inputs the controller interrupts to the SH7760 IRL9 and channel B INTB inputs them to the SH
148. ntReg rO vhd library IEEE use IEEE std logic 1164 all use IEEE std logic unsigned all entity IntReg rO is port Addrs IntRegCs Rd_x Wr_x WrDatas Rst RdDatas IrqEna end IntReg Architecture RTL of IntReg rO is constant RegRDO constant FpgaldO constant Fpgald1 constant Fpgald2 constant Fpgald3 signal IrqEnaReg signal RegWr begin in std logic vector 3 downto 1 in std logic std logic in std logic in std logic vector 3 downto 0 std logic outstd logic vector 15 downto 0 outstd logic vector 3 downto 0 std logic vector 15 downto 0 X 0000 0x0000 Initial value std logic vector 15 downto 0 5950 0x5950 Y P std logic 15 downto 0 X 4135 0x4135 A 5 std logic vector 15 downto 0 X 3031 0x3031 0 1 std logic vector 15 downto 0 X 3000 0x3200 0 Null std logic vector 3 downto 0 std logic RegWr lt 1 when Addrs 000 and IntRegCs 1 and Wr 07 IrqEna lt IrqEnaReg else 0 process Addrs IntRegCs Rd x IrqEnaReg begin if IntRegCs 1 and Rd 09 then case Addrs is ROP7760TH001TRK Users Manual Attached Documents when 000 gt RdDatas lt X 000 amp IrqEnaReg Interrupt control register when 100 when 101 when 110 when 111 gt RdDatas lt 0 gt RdDatas lt Fpgald1 gt RdDatas lt Fpgald2 gt RdDatas lt Fpgald3
149. nual SH7760 Bus signal Extension slot Bus buffer Address bus control signal Data bus Inside T Engine Board Figure 9 4 Extension Slot Bus Buffer Structure CAUTION o The bus timing delay time must be used only for reference This is not a guaranteed value TH1 T2 1 AnH 1 TS1 CKIO A25 A0 CSn RD WR D31 DO At Read RDY DACKn SA IO Memory Note IO DACK DEVICE DACKn DA SA Single address DMA Transfer DA Dual address DMA Transfer DACK in High Active Figure9 5 Memory Byte control SRAM Bus cycle Basic Read cycle No wait Address set up Insert hold time AnS ROP7760THO01TRK Users Manual Flash Memory Refresh 10 Flash Memory Refresh When refreshing the contents of the flash memory on or the internal flash memory of the power supply controller H8 3048F ONE connect the debug board to the extension slot of TEngine and run the program stored in the EPROM on the debug board 10 1 Preparation for Flash Memory Refresh Connect the debug board to the extension slot CN2 of T Engine In addition make the following settings for the jumper switch For details refer to 2 4 2 Debug Board Connection and 2 4 3 Debug Board Jumper switch Debug board jumper switch J1 Pins 1 and 2 must be short circuited EPROM allocation to an address range from h 00000000 to h 001FFFFF Connect the serial interface connector
150. o an address range Pins 1 and 2 must be open from h 01000000 to h O11FFFFF The 8bit LEDs mounted on the debug board are assigned to an address range from h 014000000 to h O17FFFFF The 16 bit SWs mounted on the debug board are assigned to an address range from 1701800000 to h01BFFFFF Debug board resources are assigned to area 0 on the SH7760 board as shown below The EPROM mounted on the debug board is assigned to an address range from h 00000000 to H 001FFFFF The amp bit LEDs mounted on the debug board are assigned to an address shortcircuited range from h 00400000 to h 007FFFFF The 16 bit SWs mounted on the debug board are assigned to an address range from h 00800000 to hOOBFFFFF The flash memory on the TEngine board is assigned to an address range from 701000000 to h017FFFFF Pins 1 and 2 must be 2 4 4 8bit LEDs on the Debug Board The low order 8 bits D7 to DO of the SH7760 data bus are connected to the amp bit LEDs placed on the debug board The 8 bit LEDs can be turned on or off by writing data to an area assigned for the LEDs through D7 to DO When a value of 1 is written to a bit the corresponding LED is turned off When a value of 0 is written to the bit it is turned on 2 4 5 16 bit SWs on the Debug Board The 16 bits D15 to DO of the SH7760 are connected to the 16 bit SWs placed on the debug board The 16 bit SWs can be turned on or off by reading data from an area assigned for the SWs through D15 to D
151. ocks the upper 4 blocks are occupied by the firmware for refreshing the flash memory and only the remaining 4 blocks to BLK7 are rewritten H 00000000 EPROM H 001FFFFF Power supply controller H8 3048F ONE Internal flash memory Transfer to power supply controller Writing by H 0C000000 firmwawre H 0CO1FFFF Transfer from host system object file H ODFFFFFF Figure 10 2 Refreshing the Flash Memory of the Power Supply Controller ROP7760THO01TRK Users Manual Flash Memory Refresh Below is a description of the method for refreshing the flash memory of the power supply controller 1 As shown on the following screen type FL 1 and hit the Enter key after the title screen appears on the communication software Display Screen SH7760 Self Debugger Ver x xL C Copyright 2002 2005 Hitachi Ltd rights reserved Ready gt H elp for help messages Ready gt fl 1 2 As shown on the following screen transfer the Motorola S format object file after the transfer request message Please Send A S format Record appears on the screen Note After data is transferred its program ID is checked to determine whether the transferred data is correct When the program ID is not correct the message Wrong appears and memory refresh terminates Display Screen SH7760 Self Debugger Ver xxL C Copyright 2002 2005 Hitachi Ltd rights r
152. oint of point A YAPDR DYB Y position drawing dot point of point B YBPDR TXA Y position A D conversion result of point A YAPAR TXB Y position A D conversion result of point B YBPAR The above calculation results are multiplied by 1 000 their decimal places are rounded and the resulting integers are written to the registers DXDR and DYDR DX dot register DXDR DX x 1 000 rounding the decimal places DY dot register DYDR DY x 1 000 rounding the decimal places The power supply controller uses data stored in the registers DXDR DYDR XAPDR YAPDR XAPAR and YAPAR to calculate dot position data XPDR YPDR of the pen touched point on the LCD The power supply controller uses the following expression to calculate dot position data X position dot register XPDR XPDR DXA DX x TXD TXA 1 000 Y position dot register YPDR YPDR DYA DY x TYD TYA 1 000 DXA XA position dot register XAPDR data DX DX1 dot register DXDR data TXA XA position A D register XAPAR data TXD X position A D register XPAR data DYA YA position dot register YAPDR data DY DY dot register DYDR data TYA YA position A D register YAPAR data TYD X position A D register YPAR data The power supply controller outputs data stored in the X position A D register XPAR and Y position A D register YPAR When the values stored in the DX dot register DXDR and DY dot register DYDR are not 0 the power supply contro
153. or 2 byte 2 byte N byte Figure 6 10 Normal Response during a Write Operation 1 ACK code This code is fixed at ACK 0x06 2 Function code The same code as for the write command returns 3 Register address The address of a register subject to a write operation returns 4 Data Write data returns The size of this data is equal to the value specified in the function code However note that no data returns for IRRSFDR subject to infrared remote control and EEPDR subject to serial EEPROM control 7760 01 Users Manual Power Supply Controller 6 2 9 Error Response during a Write Operation Figure 6 11 shows an error response format for the write command at error occurrence The power supply controller returns a NAK code and an error code in this order as an error response 1 NAK code 2 Error code 1 byte 1 byte Figure 6 11 Error Response during a Write Operation 1 NAK code This code is fixed at NAK 0x15 2 Error code Table 6 2 summarizes the error codes Table 6 2 Error Codes Error Code Error type No Communications error Invalid register number nvalid function code 7760 01 Users Manual Power Supply Controller 6 3 RTC Real time Clock Functions This section describes the RTC functions Table 6 1 summarizes the RTC registers For a detailed description of each register refer to 6 3 1 to 6 3 17 1 Function for counting the seconds minutes hours day of the w
154. or modify this product Personal injury due to electric shock may occur if this product is disassembled and modified Disassembling and modifying the product will void your warranty Make sure nothing falls into the cooling fan on the top panel especially liquids metal objects or anything combustible Warning for Installation Do not set this product in water or areas of high humidity Make sure that the product does not get wet Spilling water or some other liquid into the product may cause unrepairable damage Warning for Use Environment This equipment is to be used an environment with a maximum ambient temperature of 35 C Care should be taken that this temperature is not exceeded ROP7760TH001TRK Users Manual Precautions for Safety CAUTION Note on Connecting the Power Supply Q Do not use any power cable other than the one that is included with the product The power cable included with the product has its positive and negative poles color coded by red and black respectively Pay attention to the polarities of the power supply If its positive and negative poles are connected in reverse the internal circuit may be broken Do not apply any voltages exceeding the product s rated power supply voltage 5 0 5 Extreme voltages may cause a burn due to abnormal heat or cause the internal circuit to break down Cautions to Be Taken for Handling This Product Use caution when handling the
155. ower Supply Controller Table 6 4 Touch Panel Registers Touch panelcontrolregister TPLCR Touchpanelstatusregiser TPLSR_ 0x01 RW j ibye Touch panel sampling control register TPLSCR oxoo22 RW Xposiion A D register xPAR oxo24 29 Y position A D register YPAR oxo26 29 Xposiiondotregstr 29 Ypositiondotregister oxo2A 25 XApositiondotregister RW j 2byes YApositiondotregister RW j 2byes XB position dot register RW j 2byes YBpositiondotregister 2byes XCposiiondotregister xcPDR RW j 2byes YCpositiondotregister YcPDR RW j 2byes XAposiionA Dregister XAPAR RW j 2byes YA position A Dregister YAPAR oxosA Rw 2byes position A Dregister XBPAR RW j 2byes XC position A Dregister XCPAR R W 2bytes LC UII
156. p4 pb The YA position dot register indicates the Y dot position of point A when calibration takes place 6 4 10 XB Position Dot Register XBPDR Address Ox0030 Initial value 0x0000 015 02 Di w 015 014 D13 012 011 010 XBD 09 08 67 De m po D7 06 05 04 03 XBD D2 XBD 01 DO The XB position dot register indicates the X dot position point when calibration takes place 7760 01 Users Manual Power Supply Controller 6 4 11 YB Position Dot Register YBPDR Address 0x0032 Initial value 0x0000 Dis R W R W R W R W R W R W R W R W 07 De ps p3 Di DO 06 YBD_D5 D3 02 D1 DO R W R W R W R W R W R W R W R W The YB position dot register indicates the Y dot position of point B when calibration takes place 6 4 12 XC Position Dot Register XCPDR Address 0x0034 Initial value 0 0000 Di5 D4 D2 D9 XCD D15 XCD D14 XCD D13 XCD D12 XCD D11 XCD D10 XCD D9 XCD D8 oz po The XC position dot register indicates the X dot position of point C when calibration takes place Th
157. pen touch OFF interrupt is generated 4 PEN ONRE A pen touch ON interrupt is not generated when pen touch continues Initial value A pen touch ON interrupt is generated when pen touch continues 7760 01 Users Manual Power Supply Controller 6 4 2 Touch Panel Status Register TPLSR Address 0 0021 Initial value 0x00 D7 os D3 2 m CR R 1 PEN ONIF PEN ONIF bit SES The touch panel has not been pen touched pen touch OFF Initial value The pen touch state on the touch panel has been changed from OFF to ON The touched positions on the touch panel are output to the X position A D register Y position A D register X position dot register and Y position dot register At this time a pen touch ON interrupt is generated if the PEN ONI bit is set to 41 Clear condition 0 is written with the PEN ONIF bit set to 71 2 OFFIF PEN OFFIF bit The touch panel has not been pen touched pen touch OFF Initial value The pen touch state on the touch panel has been changed from ON to OFF At this time a pen touch OFF interrupt is generated if the PEN OFFI bit is set to 1 Clear condition 0 is written with the PEN OFFIF bit set to 1 7760 01 Users Manual Power Supply Controller 6 4 3 Touch panel Sampling Control Register TPLSCR The touch panel sampl
158. r RTCCR Address 0x000 Initial value 0x00 07 D4 Di R R Rw Rw RAV Rw Rw Rw 1 START _____ RTC start Initial value A CAUTION Q Don t write to any counter while the START bit is set to 0 Rewrite each counter after setting the START bit to 41 2 ARI ARI bit Setting ___ No alarm interrupt is generated Initial value An alarm interrupt is generated 3 1secl 1secl bit Setting No interrupt is generated at intervals of 1 second Initial value 1 interrupt is An interrupt is generated at intervals of 1 second at An interrupt is generated at intervals of 1 second of 1 second 4 0 5secl No interrupt is generated at intervals of 0 5 second Initial value An interrupt is generated at intervals of 0 5 second 5 SECCAF No carry has been generated in the second counter Initial value A carry has been generated in the second counter SECONT Zero clear condition The bit is set to 1 7760 01 Users Manual Power Supply Controller 6 CNTS The setting value of each counter is not updated Initial value The setting value of each counter is updated Zero clear condition Counter update is completed This clear operation is automatically performed A CAUTION Don t write to any counter while the START bit is set to 0
159. s POSCAP C 6TPB100MC Sanyo Electric components KRELBEO10 KQDAA ALPS CHS 08B RMC EA15MY OM15 MC1 24 5603 14 0101 861 1 5027 068 130 833 0 5027 000 907 000 4 5036 008 110 862 FH12 40S 0 5SH 12 245 0 55 SB connector 4 5041 0041 10 8345 CN7 Connector 24 8005 002 100 867 Kyocera Elco 4 8 and CN11 to CN13 2 5 Jack HSJ1602 011001 CN9 CN10 Power supply jack HEC3600 010020 CN14 FH12 10S 0 5SH Hirose Electric 2 JON 15 and C36 C7 C39 C68 C73 C86 C87 and C100 C29 C31 C44 C106 and C113 C23 and C109 T 3216 3528 5 3 E gt co 2 155 10 1052002 lt gt IGRM188B11E473KA01 lt D gt Chip ceramiccapacitor 4532 EMK432BJ226MM T antalum electrolytic capacitor TCFGB1A476M8R Mme antalum electrolytic capacito a ee C38 C3 C25 C30 C35 C40 C43 C45 C46 And C62 witch W1 SW2 SW3 witch witch 92 gt 79 Engine connector PC Card connector For CN3 CN4 CN5 and CN16 CN6 C Card ejector IM Card connector FPC connector PC connector OIIO jn 7760 01 Users Manual Attached Documents 11 1 2 LCD Board Parts List LCD Board Parts List 1 Touch screen controller Push button switch SKRHABEO10 Schottky barrier __ 7 65 _ 5016 Chip resistance 1608 MCROSEZH J103 ROHM E 81 5 and R14
160. s and algorithms represents information on products at the time of publication of these materials and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein The information described here may contain technical inaccuracies or typographical errors Renesas Technology Corporation assumes no responsibility for any damage liability or other loss rising from these inaccuracies or errors Please also pay attention to information published by Renesas Technology Corporation by various means including the Renesas Technology Corporation Semiconductor home page http www renesas com When using any or all of the information contained in these materials including product data diagrams charts programs and algorithms please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products Renesas Technology Corporation assumes responsibility for any damage liability or other loss resulting from the information contained herein Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or System that is used under circumstances in which human l
161. sition A D Register XBPAR Address Ox003C Initial value 000 Di5 Di2 Dii __ 011 010 09 08 Lm R A p R mw RW RW RW D7 De 05 Dt The XB position A D register indicates the X position A D conversion result of point B subject to calibration 7760 01 Users Manual Power Supply Controller 6 4 17 YB Position A D Register YBPAR Address OxOOSE Initial value 0 0000 o Dti YEA 09 R R R mw RW w gt The position A D register indicates the Y position A D conversion result of point subject to calibration 6 4 18 XC Position A D Register XCPAR Address 0 0040 Initial value 0 0000 o o XCA XcA 09 08 CR R R mw RW D7 D5 Do The XC position A D register indicates the X position A D conversion result of point C subject to calibration This register will be functionally enhanced in future Don t access this register 6 4 19 YC Position A D Register YCPAR Address 0x0042 Initial value 0 0000 Di5 m2 Di
162. so 7 8 88 avss a 2 SE28 C2 RTC INTR g 50 INTR 0 ___ ___ 78 2 87 peorRFSHIIRQO ii 1 9 KEY 3 e xdv sum 878 2 RTC INTR A2IP12 KEY 9 oscin 55 a 58 P HD64F3048BVF25 37 82199 504 RTS 89 26521802 KEY 2 kt o 8 2 12 87 POWER SW 1 36 KEY INO 7AA78F2 GND loscour vss 91 peaicso veco 3 RV5C348B 32 ysss 015037 34 a LED7 33 D14 P36 33 LEDG T GND 212 7 RESET SW 94 PAITPI TENDI TCLKB 32 LEDS MD2 1 821207 SW 95 PA2 TPZ TIOCAO TCLKC D12 p34 31 LED4 g 7 7 2 LCD PWRDY 36 30 LED3 _ TIBz8 E2 LCD FLON PAUTPAITIOCAT A23ICSS 29 LED2 MD amp 127 SIGN 38 PASTPSITIOCBI A22 CSS 1 28 LED mme iy 8 21283 59 PAGITPEITIOCAZ A21 CSA 5 22 LEDO HERES iniu 9 IR_DIN 100 PA7 TP7 TIOCB2 A20 2 am HB STBY
163. ss N 1 byte 1 byte or 2 byte 2 byte byte Figure 6 7 Read Command 1 Start code This code is fixed at 0x02 2 Function code 1 byte function code specifies the size of data to be written the lower 4 bits when the upper 4 bits of a function code are 1100 Figure 6 8 shows a function command where the upper 4 bits are 1100 os ps gt po t sizcofdata Figure 6 8 Function Command 1 Byte 2 byte function code specifies the size of data to be written in the lower 12 bits when the upper 4 bits of a function code are 1101 Figure 6 9 shows a function command where the upper 4 bits are 1101 pis pia rz oio 07 os os ms o 01 0 150 1 5 Sieo dta Figure 6 9 Function Command 2 Bytes 3 Register Address The register address specifies the address of the register to be written 4 Data This field specifies the size of data to be written This data size is equal to that specified in the function code 7760 01 Users Manual Power Supply Controller 6 2 8 Normal Response during a Write Operation Figure 6 10 shows the response format for the write command The power supply controller returns an ACK code a function code a register address and target data in this order as a response for the write command 1 ACK code 2 Function code 3 Register address 4 Data 1 byte 1 byte
164. ta has been transmitted or received 1 Clear condition 0 is written with the IRRIF bit set to 1 6 9 8 Infrared Remote Control Data Structure The following shows the relation between the infrared remote control data and repeat codes In addition it LEN DATA2 DATAn ata shows a structure of remote control data in the NEC format Example NEC format remote control data Repeat code Custom 1 Custom 2 Data 1 Data 2 Infrared Remote Control Operation Procedure Initial setting 1 Two kinds of formats are set by selecting the FORMAT bit of the IRRCR register 2 The START bit of the IRRCR register is set to 1 to start infrared remote control and infrared signal reception 3 To enable an interrupt at the time of receiving a frame of the signal the RDIE bit is set to 1 4 To enable an interrupt at the time of transmitting a frame of the signal the TDIE bit is set to 1 For infrared signal reception 1 When a frame of data has been received RDI 1 the IRRIF bit of the RTKISR register is set to 1 2 When an interrupt at completion of signal reception has been enabled RDIE 1 an interrupt occurs when a frame of data is stored in the IRRRFDE register 3 To obtain the received data the receiving FIFO data register IRRRFDR is read The IRRRFDR register contains a data count that indicates the number of items of one frame of data received and the received d
165. tion This A D value is obtained by calculating the mean of the previous four YPARDOT values and clearing the following 3 bits with zeros 6 4 28 Position Dot Calculation A D Value 1 YPARDOT1 Address 0 x0054 Initial value 0 0000 Mu o vor D 07 De 05 m ow YD1 07 YD1 De YD1 05 YD1 3 The Y position dot calculation A D value 1 register YPARDOT1 holds a YPARDOT value before sampling 6 4 29 Y Position Dot Calculation A D Value 2 YPARDOT2 Address 0x0056 Initial value 0 0000 vba po YD2 D D7 05 Dt 07 pe De Ds 2 D3 The Y position dot calculation A D value 2 register YPARDOT2 holds YPARDOT value before sampling 7760 01 Users Manual Power Supply Controller 6 4 30 Y Position Dot Calculation A D Value Address 0x0058 Initial value 0x0000 2 Dy w 65 368 pe 07 YS Ds vs pa vs The Y position dot calculation A D value register holds a YPARDOT value before sampling 6 4 31 Y Position Dot Calculation A D Value 4 YPARDOTA Address 0x005A Initial value 0 0000 ELTE
166. tor Table 2 1 shows the signals of the serial interface connector RS 232C interface cross cable accessory Host system Serial interface connector T Engine Board Figure 2 1 Host System Connection 1 15 Figure 2 2 Serial Interface Connector Pins ROP7760TH001TRK Users Manual Installation Table 2 1 Serial Interface Connector Signals iq 3 RD 1 RXBUART 4 GND 5 RS 6 _ 1 CTSNUR 8 Reserved 0 9 Resevea 10 Resewed ISPTMS Reserved ISPPug 12 Reseved ISPBScan 13 Reserved 14 Reserved ISPTDO 15 Reseved 083 C These pins are used only to test the board when it is shipped from the factory Don t use these pins for any other purpose 2 2 AC Adapter Connection Figure 2 3 shows an AC adapter connection method shown in Figure 2 3 connect the plug to the AC adapter connector of the T Engine board 1 then connect the adapter cord to the receptacle 2 T Engine Board 2 Connect the adapter cord to the receptacle AC adapter connection 1 Connect the plug connector CN14 Figure 2 3 AC Adapter Connection Cord ROP7760TH001TRK Users Manual Installation CAUTION
167. tput x outstd logic vector 3 downto 0 end IrqCnt Architecture RTL of IrqCnt is Attached Documents MR SHPC 01 interrupt ST16C2550 interrupt ST16C2550 interrupt External Slot interrupt H8 3048 interrupt Interrupt enable 7760 01 Users Manual signal begin std logic vector 3 downto 0 External slot interrupt process PcSirq x UartIntA x H8lrq x IrgEna end RTL begin IrqEna 0 17 if Exlrq x 3 0 elsif PcSirq x 3 0 elsif H8lrg x 0 elsif UartlntB EU elsif Exlrq_x 2 0 elsif PcSirq x 2 0 elsif UartlntA 1 elsif x 1 0 elsif PcSirq x 1 0 elsif x 0 0 elsif x 0 0 end if end process x lt not Irl then then then then then then then then then then then lt X F Irl lt Irl lt X D lt X C lt lt X A Irl lt X 9 lt 8 lt X 7 lt X 6 lt X 5 lt X 0 Attached Documents Level 15 Level 14 Level 13 Level 12 Level 11 Level 10 Level Level Level Level Level Level 9 o o ROP7760TH001TRK Users Manual Attached Documents 4 IntReg rO vhd module name Internal register entity IntReg file name I
168. uence period register H FE300C28 H 0000 Control register ROP7760THO001TRK Users Manual Functional Blocks 5 5 Sound Generator 5 5 1 Block Description Figure 5 8 shows the sound generator control block As shown in Figure 5 8 this control block contains the serial sound interface SSI of the SH7760 and the Audio CODE C UDA1342TS from Philips so that sound can be output to headphones connected to the output mini jack CN9 or can be input to earphones connected to the I O mini jack CN10 In addition headphone output takes place with the quality of stereo output while earphone takes place with the quality of monaural I O that uses only the The IIC interface of the SH7760 is used for the initial setting and for modification of the Audio CODEC internal registers This control block is connected to an electronic volume so that sound output volume can be controlled The electronic volume is controlled by the power supply controller details refer to 6 Power Supply Controller T Engine has the following characteristics for microphone input and headphone output Microphone input Impedance 2 2KQ Sensitivity 51dB Pa Headphone output Impedance 320 For more details refer to the SH7760 Hardware Manual or the Philips UDA1342TS Manual Philips Homepage http www semiconductors philips com S 60 Sound H77 Audio CODEC ouput mini jack UDA1342TS CN9 DATAO Reh output BCK Lchoutput WS Sound I O
169. umber of dots per data Y position A D conversion result at calibration by 1 000 The power supply controller outputs a dot position of the Y position to be stored in the Y position dot register YPDR from the values set in the DY dot register DYDR YA position dot register YAPDR and YA position A D register YAPAR When the DY dot register DY1DR has been set to 0 the dot position is not calculated 7760 01 Users Manual Power Supply Controller 6 4 22 X Position Dot Calculation A D Value XPARDOT Address 0X0048 Initial value 0x0000 25 08 RECTE UNES COEUR SY RN RR The X position dot calculation A D value register XPARDOT holds an AD value of X position dot calculation This A D value is obtained by calculating the mean of the previous four XPARDOT values and clearing the low order 3 bits with zeros 6 4 23 X Position Dot Calculation A D Value 1 XPARDOT1 Address 4 Initial value Ox0000 EL ETE ETUR 08 A The X position dot calculation A D value 1 register XPARDOT1 holds XPARDOT value before sampling 6 4 24 X Position Dot Calculation A D Value 2 XPARDOT2 Address Ox004C Initial value 0 0000 o o xb2 09 XD2De L pa 07
170. ute counter 6 3 4 Minute Counter MINCNT Address 0x0003 Initial value OxXX Not defined 67 De Ds 2 m 10 minutes 1 minutes o R aw RW RW RW RW RW WW The counter value is a BCD Binary Coded Decimal value Counting takes place within a range from 00 to 59 When the value changes from 59 to 00 a carry is generated in the hour counter 6 3 5 Hour Counter HRCNT Address 0x0004 Initial value Not defined 07 De 05 Di __ fOmus 1 6 RW RW RW RW RW RW The counter value is a BCD Binary Coded Decimal value Counting takes place within a range from 00 to 23 When the value changes from 23 to 00 a carry is generated in the day counter and the day of the week counter 7760 01 Users Manual Power Supply Controller 6 3 6 Day of the Week Counter WKCNT Address 0x0005 Initial Value Not defined 07 De m DO R R RW Rw RW Counting takes place within a range from 0x00 to 0x06 The following shows the correspondence between the day of the week and the value of the septinary incremental counter 02 01 00 0 0 0 gt Sunday 02 01 00 0 0 1 02 01 00 0 1 0 Tuesday 02 01 00 0 1 1 Wednesday 02 01 00 1 0 0 Thursday 02 01 00 1 0 1
171. y Screen Ready gt fl 0 ROP7760THO01TRK Users Manual Flash Memory Refresh 2 As shown on the following screen transfer the Motorola S format object file after the transfer request message Please Send A S format Record appears on the screen Display Screen 5 7760 Flash Memory Change Value Flash Memory data copy to RAM Please Send A S format Record 3 Flash memory refresh normally terminates when the messages flash memory chip erase complete and flash write complete sequentially appear on the screen after the Motorola S format object file has been transferred Display Screen Ready gt fl 0 SH7760 Flash Memory Change Value Flash Memory data copy to RAM Please Send A S format Record Start Addrs A0000000 End Addrs AOOFFFFF Transfer complete Flash chip erase complete Program complete Flash write complete Ready gt ROP7760THO01TRK Users Manual Flash Memory Refresh 10 3 Power Supply Controller s Internal Flash Memory 10 3 1 Refresh Method Figure 10 2 shows how the flash memory of the power supply controller is refreshed As shown in Figure 10 2 data transferred from the host system is saved in the SDRAM when power supply controller s flash memory is refreshed saved data is transferred to the power supply controller and written to the flash memory by the power supply controller firmware Though the flash memory of the power supply controller has been divided into 8 bl

Download Pdf Manuals

Related Search

Related Contents

Hunter Engineering ForceMatch HD Brochure  H31 (BG08) - Manuel d`installation  SK18A User`s Manual  Crescent Vector VS100 Series  User Manual  WARNING - Masterbuilt  Graco 8824 User's Manual  MAN-WZA215-LC WZA245-NC WZA26-NC-d  Programme des ateliers de la JOMD Ateliers techniques  

Copyright © All rights reserved. Failed to retrieve file