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1. Bit Symbol Description Access oe 31 24 Reserved 0 for reads 0 23 RAM ADD 23 0 22 22 0 21 21 0 20 20 0 19 RAM ADD 19 0 18 RAM ADD 18 0 17 ADD 17 0 Address Bit 23 10 R W 16 RAM ADD MAP BIT 16 0 15 RAM ADD MAP BIT 15 0 14 RAM ADD MAP BIT 14 0 13 RAM ADD MAP BIT 13 0 12 RAM ADD MAP BIT 12 0 11 RAM ADD MAP BIT 11 0 10 RAM ADD MAP BIT 10 1 9 0 Reserved 0 for reads 0 Figure 3 12 Address Map Register RAMR 3 2 11 RAM Space There is a 256 x 32 bit RAM space available it is accessed if the address bits match to the content of the RAM Address Map Register See Description of RAMR Only 32 bit accesses are possible TPMC630 User Manual Issue 1 6 Page 19 of 46 4 9030 Target Chip 4 1 PCI Configuration Registers PCR 4 1 1 9030 Header TEWS 42 TECHNOLOGIES PCI CFG Write 0 to all unused Reserved bits Initial Values Register writeable Hex Values Address 31 24 23 16 15 8 7 0 0x00 Device ID Vendor ID N 0276 1498 0x04 Status Command Y 0280 0000 0x08 Class Code Revision ID N 118000 00 0x0C BIST Header Type P
2. Figure 3 9 Interrupt Status Register ISR 3 2 8 Positive Edge Interrupt Enable Register PIER 0x1C Reset Value 00 eet Symbol Description Access qa Reserved 0 for reads 0 PIE 7 PIE 6 PIE 5 PIE 4 PIE 3 PIE 2 PIE 1 PIE 0 Line 7 0 Rising Edge Interrupt Enable 0 7 disabled R W 0 1 enabled Figure 3 10 Positive Edge Interrupt Enable Register PIER TPMC630 User Manual Issue 1 6 Page 17 of 46 TEWS 42 TECHNOLOGIES 3 2 9 Negative Edge Interrupt Enable Register NIER 0x20 Reset Value u Symbol Description Access x Reserved 0 for reads 0 NIE_7 6 _5 _4 _3 _2 _1 _0 Line 7 0 Falling Edge Interrupt Enable 0 disabled R W 0 1 enabled Figure 3 11 Negative Edge Interrupt Enable Register NIER TPMC630 User Manual Issue 1 6 Page 18 of 46 TEWS 42 TECHNOLOGIES 3 2 10 RAM Address Map Register RAMR 0x24 The RAM Address Map Register determines at which address the 256 x 32 bit RAM space begins within the 16 MByte address space If RAMR is set to 0x0 the addresses from 0 0 to 0x24 occupied by the registers Only 32 bit accesses are possible
3. U ene nn enhn tn aant a u u u J J J J 39 8 PIN ASSIGNMENT I O CONNECTOR 40 TPMC630 User Manual Issue 1 6 Page 4 of 46 TEWS 42 TECHNOLOGIES 8 1 Front Panel 1 0 Connector U sisse nenne nentes uu u u u u J 40 8 1 1 Front I O Assignment 630 0 41 8 1 2 Front I O Assignment 6 0 1 42 8 1 3 Front I O Assignment 630 lt 2 43 8 2 Back VO 44 8 2 1 Back I O Assignment TPMC630 X0 44 8 2 2 Back I O Assignment TPMC630 Xx1 45 8 2 3 Back I O Assignment 30 2 46 TPMC630 User Manual Issue 1 6 Page 5 of 46 FIGURE 1 1 FIGURE 2 1 FIGURE 3 1 FIGURE 3 2 FIGURE 3 3 FIGURE 3 4 FIGURE 3 5 FIGURE 3 6 FIGURE 3 7 FIGURE 3 8 FIGURE 3 9 FIGURE 3 10 FIGURE 3 11 FIGURE 3 12 FIGURE 4 1 FIGURE 4 2 FIGURE 4 3 FIGURE 4 4 FIGURE 4 5 FIGURE 5 1 FIGURE 5 2 FIGURE 5 3 FIGURE 5 4 FIGURE 5 5 FIGURE 5 6 FIGURE 5 7 FIGURE 6 1 FIGURE 6 2 FIGURE 6 3 FIGURE 7 1 FIGURE 7 2 FIGURE 7 3 FIGURE 7 4 FIGURE 7 5 FIGURE 7 6 FIGURE 8 1 FIGURE 8 2 FIGURE 8 3 FIGURE 8 4 FIGURE 8 5
4. 58 57 57 56 56 55 55 54 54 53 53 52 52 51 51 50 50 49 49 48 OUT 48 Output Port Bit 63 32 Data R W 0 47 OUT REG 47 see notes below 46 OUT_REG BIT_46 45 OUT REG 45 44 OUT_REG 44 43 OUT_REG 43 42 OUT_REG 42 41 OUT REG BIT 41 40 OUT REG BIT 40 39 OUT REG BIT 39 38 OUT REG BIT 38 37 OUT REG BIT 37 36 OUT REG BIT 36 35 OUT REG BIT 35 34 OUT REG BIT 34 33 OUT REG BIT 33 32 OUT REG BIT 32 Figure 3 4 Output Register 1 OUT REG1 TPMC630 x0 Output Port Bits 32 63 are written to 32 IO 63 TTL TPMC630 x1 Output Port Bits 32 63 are not used TPMC630 x2 Output Port Bits 32 63 are written to 32 63 TTL TPMC630 User Manual Issue 1 6 Page 12 of 46 TEWS 42 TECHNOLOGIES 3 2 3 Input Register 0 REGO 0x08 Read directly from the I O lines 31 to 0 Bit Symbol Description Access Reset Value 31 31 30 30 29 29 28 28 27 27 26
5. 50 49 49 Output Enable Bit 63 32 28 OE REG BIT 48 see notes below RAN 0 47 OE REG BIT 47 0 disables the output transceiver 46 REG 46 14 enables the output transceiver 45 45 44 44 43 43 42 42 41 41 40 40 39 39 38 38 37 37 36 36 35 35 34 34 33 33 32 32 Figure 3 8 Output Enable Register 1 TPMC630 x0 Output Enable Bits 32 63 control Output 32 Output 63 TTL TPMC630 x1 Output Enable Bits 32 63 are not used TPMC630 x2 Output Enable Bits 32 63 control Output 32 Output 63 TTL TPMC630 User Manual Issue 1 6 Page 16 of 46 TEWS 42 TECHNOLOGIES 3 2 7 Interrupt Status Register ISR 0x18 The Interrupt Status Register signals the lines on which an interrupt event occurred The example design supports interrupts only for line 0 to 7 Reset Value 8 Reserved 0 for reads 0 INT_7 INT_6 INT_5 INT_4 INT_3 INT_2 INT_1 0 Bit Symbol Description Access Line 7 0 Interrupt Request Status 0 no active interrupt request R W 0 1 active interrupt request
6. 58 57 57 56 56 55 55 54 54 53 53 52 52 51 51 50 50 49 49 48 48 Input Port Bit 63 32 Data I 47 IN_REG_BIT_47 see notes below 46 IN_REG_BIT_46 45 IN_REG_BIT_45 44 IN_REG_BIT_44 43 IN REG BIT 43 42 IN REG BIT 42 41 IN REG BIT 41 40 IN REG BIT 40 39 IN REG BIT 39 38 IN REG BIT 38 37 IN REG BIT 37 36 IN REG BIT 36 35 IN REG BIT 35 34 IN REG BIT 34 33 IN REG BIT 33 32 IN REG BIT 32 Figure 3 6 Input Register 1 IN REG1 TPMC630 x0 Input Port Bits 32 63 are read from 32 63 TTL TPMC630 x1 Input Port Bits 32 63 are not used TPMC630 x2 Input Port Bits 32 63 are read from 32 63 TTL TPMC630 User Manual Issue 1 6 Page 14 of 46 TEWS 42 TECHNOLOGIES 3 2 5 Output Enable Register 0 OE REGO 0x10 Bit Symbol Description Access 31 31 30 30 29 29 28 28 27 OE REG 27 26 26 25 25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 17 Output Enable Bit 31 0
7. me tL 581 Figure 7 4 Jumper positions for ground option TPMC630 User Manual Issue 1 6 Page 37 of 46 Back I O Line Signal Jumper Position ground R70 57 IO_56 IO_28A default ground R66 58 57 1O 28B default ud ground R74 59 58 10 29A default ground R71 60 I O_59 IO_29B default R73 ground R78 61 1 0_60 IO_30A default ROD ground R75 62 I O_61 IO_30B default Re ground R82 63 1 0_62 IO_31A default pod ground R79 64 63 10 31B default Figure 7 5 Jumper positions for Back I O options TEWS 42 TECHNOLOGIES Caution Never make simultaneous connections on both jumper positions of one line Serious damage of the module is possible TPMC630 User Manual Issue 1 6 Page 38 of 46 TEWS 42 TECHNOLOGIES 7 4F PGA Debug Connector The FPGA in circuit debug connector X2 is not populated by default It lets the user directly connect JTAG interface cable to the JTAG pins of the FPGA for readback and real time debugging of the FPGA design using Xilinx ChipScope The Platform Flash is not part of this JTAG chain it is only programmable via the 9030 GPIO A through hole vertical connector with 7 x 2 pins and 2mm pitch e g Molex 87831 1420 or others can be mounted Attention the connector has to be soldered from the bottom
8. 26 25 25 24 IN REG 24 23 REG 23 22 22 21 21 20 20 19 19 18 18 17 REG 17 16 16 Input Port Bit 31 0 Data R _ 15 15 see notes below 14 14 13 13 12 12 11 11 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 Figure 3 5 Input Register 0 REGO TPMC630 x0 Input Port Bits 0 31 are read from 0 10 31 TTL TPMC630 x1 Input Port Bits 0 31 are read from IO 0 31A B Differential TPMC630 x2 Input Port Bits 0 15 are read from 0 15 Differential Input Port Bits 16 31 are not used TPMC630 User Manual Issue 1 6 Page 13 of 46 5 42 TECHNOLOGIES 3 2 4 Input Register 1 IN REG1 Read directly from the I O lines 63 to 32 Bit Symbol Description Access ae 63 IN_REG_BIT_63 62 IN_REG_BIT_62 61 61 60 60 59 59 58
9. TPMC630 User Manual Issue 1 6 Table of Figures BLOCK DIAGRAM TECHNICAL SPECIFICATION 9030 LOCAL SPACE CONFIGURATION FPGA EXAMPLE DESIGN REGISTER SPACE OUTPUT REGISTER 0 OUT REGO OUTPUT REGISTER 1 OUT REG1 INPUT REGISTER 0 IN REGO INPUT REGISTER 1 IN REG1 OUTPUT ENABLE REGISTER 0 OE REGO OUTPUT ENABLE REGISTER 1 OE REG1 INTERRUPT STATUS REGISTER ISR POSITIVE EDGE INTERRUPT ENABLE REGISTER PIER NEGATIVE EDGE INTERRUPT ENABLE REGISTER NIER ADDRESS MAP REGISTER RAMR DEFAULT PCI9030 HEADER PCI9030 PCI BASE ADDRESS USAGE PCI9030 LOCAL CONFIGURATION REGISTER CONFIGURATION EEPROM TPMC630 DEFAULT VALUES OF SPACE 0 REGION DESCRIPTOR PIN ASSIGNMENT LOCAL BUS DATA SIGNALS PIN ASSIGNMENT LOCAL BUS ADDRESS SIGNALS PIN ASSIGNMENT LOCAL BUS CONTROL SIGNALS PIN ASSIGNMENT CLOCK INPUTS PIN ASSIGNMENT FPGA INPUT LINES PIN ASSIGNMENT FPGA OUTPUT LINES PIN ASSIGNMENT FPGA OUTPUT ENABLE LINES LOCAL BUS LITTLE BIG ENDIAN DEFAULT VALUES OF CLOCK OUTPUTS AT DELIVERY DEFAULT REGISTER VALUES AT DELIVERY PULL UP VOLTAGE JUMPER SETTING TTL I O INTERFACE DIFFERENTIAL I O INTERFACE JUMPER POSITIONS FOR GROUND OPTION JUMPER POSITIONS FOR BACK I O OPTIONS DEBUG CONNECTOR BOTTOM VIEW FRONT PANEL I O CONNECTOR NUMBERING PIN ASSIGNMENT FRONT I O CONNECTOR TPMC630 X0 PIN ASSIGNMENT FRONT I O CONNECTOR TPMC630 X1 PIN ASSIGNMENT FRONT I O CONNECTOR TPMC630 X2 PIN ASSIGNMENT P14 I O CONNECTOR TPMC630 X0 TEWS 42 TECHNOLOGIES Pag
10. GND IO_15A iff wass Diff GND 32 IO 15B Diff IO 31B GND Diff GND Figure 8 6 Pin Assignment P14 I O Connector TPMC630 x1 TPMC630 User Manual Issue 1 6 Page 45 of 46 5 42 TECHNOLOGIES 8 2 3 Back I O Assignment TPMC630 x2 IO 0 IO_0B IO_1A IO_1B 2 1 _2 IO_3A IO_3B IO_4A IO_4B IO_5A IO_5B IO_6A IO_6B IO_7A IO_7B IO_8A IO_8B IO_9A IO_9B IO_10A IO_10B IO_11A IO_11B IO_12A IO_12B IO_13A IO_13B IO_14A IO_14B IO_15A 32 15B Diff Pin Signal Level TTL GND TTL GND TTL GND io sieno TTL GND TTL GND osea 63 GND TTL GND Figure 8 7 Pin Assignment P14 I O Connector TPMC630 x2 TPMC630 User Manual Issue 1 6 Page 46 of 46
11. 16 OE REG BIT 16 see notes below RAN 0 15 OE REG BIT_15 0 disables the output transceiver 14 REG 14 1 enables the output transceiver 13 13 12 12 11 11 10 10 9 8 7 6 5 4 2 1 0 NI Figure 3 7 Output Enable Register 0 TPMC630 x0 Output Enable Bits 0 31 control Output 0 Output 31 TTL TPMC630 x1 Output Enable Bits 0 31 control Output 0 Output 31 Differential TPMC630 x2 Output Enable Bits 0 15 control Output 0 Output 15 Differential Output Enable Bits 16 31 are not used TPMC630 User Manual Issue 1 6 Page 15 of 46 TEWS 42 TECHNOLOGIES 3 2 6 Output Enable Register 1 1 0x14 Bit Symbol Description Access 63 63 62 REG BIT 62 61 OE_REG BIT 61 60 60 59 59 58 58 57 57 56 56 55 55 54 54 53 53 52 52 51 51 50
12. Jomo ozm 68 10_31B Diff 4 Figure 8 3 Pin Assignment Front I O Connector TPMC630 x1 TPMC630 User Manual Issue 1 6 Page 42 of 46 TEWS 42 TECHNOLOGIES 8 1 3 Front I O Assignment TPMC630 x2 Level 9 9 9 9 9 9 9 9 O z r TTL Pin Signal Level o o os 68 63 TTL Figure 8 4 Pin Assignment Front I O Connector TPMC630 x2 TPMC630 User Manual Issue 1 6 Page 43 of 46 TEWS 42 TECHNOLOGIES 8 2 Back I O PMC Connector 8 2 1 Back I O Assignment TPMC630 x0 Pin Signal Level m jos n TT 16ND TTL GND TTL GND io sieno TTL GND oe 63 GND GND Figure 8 5 Pin Assignment P14 I O Connector TPMC630 x0 TPMC630 User Manual Issue 1 6 Page 44 of 46 TEWS 42 TECHNOLOGIES 8 2 2 Back I O Assignment TPMC630 x1 Pin Signal Level IO 3B iff Diff IO 4B iff Diff IO 7B iff Diff for s IO_9B iff Diff IO_12A iff Diff GND IO_12B iff Diff GND IO_13A iff Diff GND IO_13B iff 60 29B GND Diff GND IO_14A iff Diff GND IO_14B iff Diff
13. Pull Up Voltage Jumper Setting 7 2 Interface 7 2 4 TTL I O Interface Each of the 64 TPMC630 x0 or 32 TPMC630 x2 TTL I O lines is realized with two 74LVT126 bus buffers as an interface to the FPGA pins The logic levels of the buffers are TTL compatible meaning that the minimum high level is 2 0V and the maximum low level is 0 8V The nominal output high voltage is 3 3V The buffer outputs are followed by 470 serial resistors for signal integrity reasons The 4 7kQ pull up resistors guaranty a high level when outputs are tristate and not driven externally As an option the pull up voltage can be set to 5V by jumper J1 to weakly drive a higher voltage than 3 3V by setting the output to tristate This means instead of toggling the corresponding bit of the output register the output enable register bit is set to O for an output high level or 1 to pull the output low the OUT REG bit is 0 For example when connecting to a standard 5V CMOS logic input not TTL compatible levels a high level of minimum 3 5V is required Please note that the pull up resistor can only drive high impedance inputs A TVS array protects against ESD shocks See the following figure for more information of the TTL I O circuitry Please note that the length and consequently the capacitance of a flat cable connected to the TPMC630 module should be kept as short as possible to prevent large cross talk To reduce the cross talk on the TPMC630 not all
14. 15 FPGA IN 47 V16 FPGA IN 16 E10 FPGA IN 48 V20 FPGA IN 17 E13 FPGA IN 49 L6 FPGA IN 18 M19 FPGA IN 50 U20 FPGA IN 19 L20 FPGA IN 51 T18 FPGA IN 20 A15 FPGA IN 52 AA13 FPGA IN 21 B14 FPGA IN 53 V12 FPGA IN 22 L22 FPGA IN 54 AB17 FPGA IN 23 K22 FPGA IN 55 U12 FPGA IN 24 J22 FPGA IN 56 AB18 FPGA IN 25 A18 FPGA IN 57 Y16 FPGA IN 26 R21 FPGA IN 58 W15 FPGA IN 27 R22 FPGA IN 59 AB20 FPGA IN 28 E16 FPGA IN 60 AA8 FPGA_IN 29 E17 FPGA_IN 61 N3 FPGA_IN 30 V21 FPGA_IN 62 W9 FPGA_IN 31 22 FPGA_IN 63 V9 TPMC630 User Manual Issue 1 6 Figure 5 5 Pin Assignment FPGA Input Lines Page 28 of 46 5 2 6 Pin Assignment of FPGA Output Lines TEWS 42 TECHNOLOGIES Signal Pin Signal Pin FPGA_OUT 0 E2 FPGA_OUT 32 B19 FPGA_OUT 1 E3 FPGA_OUT 33 C14 FPGA_OUT 2 B5 FPGA_OUT 34 C17 FPGA_OUT 3 B3 FPGA_OUT 35 D14 FPGA_OUT 4 A4 FPGA_OUT 36 K21 FPGA_OUT 5 F4 FPGA_OUT 37 J17 FPGA_OUT 6 FPGA_OUT 38 J19 FPGA_OUT 7 FPGA_OUT 39 J20 FPGA_OUT 8 8 FPGA_OUT 40 G5 FPGA_OUT 9 B8 FPGA OUT 41 F9 FPGA OUT 10 D10 FPGA OUT 42 G18 FPGA OUT 11 A17 FPGA OUT 43 G20 FPGA OUT 12 A10 FPGA OUT 44 V17 FPGA OUT 13 D8 FPGA OUT 45 U18 FPGA OUT 14 D13 FPGA OUT 46 U19 FPGA OUT 15 D16 FPGA OUT 47 K4 FPGA_OUT 16 D21 FPGA_OUT 48 T20 FPGA_OUT 17 E1
15. 4 5 Local BUS D dat 24 5 FPGA PROGRAMMING HINTS 25 5 1 FPGA DOSI OM eset sk hes 25 5 2 FPGA Pin ASSIG EN 25 5 2 1 Pin Assignment of Local Bus Data 25 5 2 2 Pin Assignment of Local Bus Address 26 5 2 3 Pin Assignment of Local Bus Control Signals 27 5 2 4 Pin Assignment of Clock 27 5 2 5 Pin Assignment of FPGA Input 28 5 2 6 Pin Assignment of FPGA Output Lines 29 5 2 7 Pin Assignment of FPGA Output Enable 30 6 CONFIGURATION HINTS aan rna us cucurrit gir 31 6 1 Big Little Endi an nra IR 31 6 2 Clock diri m 33 7 INSTALLATION eiie sieut niea u DI Q 35 TA P ll Up o Ireo e 35 7 2 VO WAC ACG ee DD 35 721 TIL O Interface e Edi tust er ined Ro due 35 7 2 2 Differential VO Intierfae uu uuu 36 7 3 Back VO Gonfiguralion inn CUP cava gU Dd U E 37 7 4 FPGA Debug Connector
16. 5 FPGA_OUT 49 K5 FPGA_OUT 18 L17 FPGA_OUT 50 J3 FPGA_OUT 19 K17 FPGA_OUT 51 P18 FPGA_OUT 20 D9 FPGA_OUT 52 15 FPGA_OUT 21 12 FPGA_OUT 53 W14 FPGA OUT 22 G21 FPGA OUT 54 AA17 FPGA OUT 23 E21 FPGA OUT 55 AB19 FPGA OUT 24 F22 FPGA OUT 56 Y17 FPGA OUT 25 D22 FPGA OUT 57 W16 FPGA OUT 26 N21 FPGA OUT 58 W17 FPGA OUT 27 N22 FPGA OUT 59 Y19 FPGA OUT 28 B15 FPGA OUT 60 W8 FPGA OUT 29 B17 FPGA OUT 61 V8 FPGA OUT 30 T21 FPGA OUT 62 V10 FPGA OUT 31 T22 FPGA OUT 63 AB14 TPMC630 User Manual Issue 1 6 Figure 5 6 Pin Assignment FPGA Output Lines Page 29 of 46 TEWS 42 TECHNOLOGIES 5 2 7 Pin Assignment of FPGA Output Enable Lines Signal Pin Signal Pin FPGA_OE 0 D1 FPGA_OE 32 B18 FPGA_OE 1 A3 FPGA_OE 33 C13 FPGA_OE 2 5 _ 34 16 FPGA_OE 3 F2 FPGA_OE 35 D12 FPGA_OE 4 F3 FPGA_OE 36 K18 FPGA_OE 5 B4 FPGA_OE 37 G4 FPGA_OE 6 D5 FPGA_OE 38 J18 FPGA_OE 7 B6 FPGA_OE 39 F20 FPGA_OE 8 C7 FPGA_OE 40 J21 FPGA_OE 9 D7 FPGA_OE 41 H18 FPGA_OE 10 B13 FPGA_OE 42 F10 FPGA_OE 11 A16 FPGA_OE 43 G19 FPGA_OE 12 9 44 W18 FPGA OE 13 E7 FPGA_OE 45 V19 FPGA_OE 14 C18 FPGA_OE 46 K6 FPGA_OE 15 8 FPGA_OE 47 19 _ 16 12 _ 48 T19 FPGA_OE 17 E14 FPGA_OE 49 R18 FPGA_OE 18 J6 FPGA_OE 50 P17 F
17. 64 I O lines should be switched at the same time The output lines could be switched in 8 groups of 8 signals in steps of 12 5ns 40 MHz clock as shown in the VHDL example After about 100ns the switching process is completed TPMC630 User Manual Issue 1 6 Page 35 of 46 TEWS S TECHNOLOGIES 5V or 3 3V FPGA OEx 3 1 TTL Line X1 P14 XILINX FPGA MSMF05 Protection FPGA INx 741 126 Figure 7 2 TTL I O Interface 7 2 2 Differential I O Interface Each of the 32 TPMC630 x1 or 16 TPMC630 x2 differential I O line pairs is realized with an input output and output enable pin at the XILINX FPGA connected to a MAX3078E an ESD protected RS485 RS422 transceiver and a 1200 termination resistor See the following figure for more information of the differential I O circuitry MAX3078E FPGA_OUTx FPGA_OEx 120R 1 Differential Line XILINX 1 14 Figure 7 3 Differential I O Interface TPMC630 User Manual Issue 1 6 Page 36 of 46 TEWS 42 TECHNOLOGIES 7 3 Back I O Configuration The configuration of P14 64 pin Mezzanine Back I O connector lines 57 64 can be changed to ground instead of port 7 signals by change of zero ohm resistors For removing mounting zero ohm resistors work on a grounded static free work surface P iE 4 REG 1 1874 R75 R78 1879 R82 L cc
18. CI Latency Cache Line Y 7 0 00 00 00 00 Timer Size 0x10 PCI Base Address 0 for MEM Mapped Config Registers Y FFFFFF80 0x14 PCI Base Address 1 for I O Mapped Config Registers Y FFFFFF81 0x18 PCI Base Address 2 for Local Address Space 0 Y FF000000 0x1C PCI Base Address 3 for Local Address Space 1 Y 00000000 0x20 PCI Base Address 4 for Local Address Space 2 Y 00000000 0x24 PCI Base Address 5 for Local Address Space 3 Y 00000000 0x28 PCI CardBus Information Structure Pointer N 00000000 0 2 Subsystem ID Subsystem Vendor ID N s b 1498 0x30 PCI Base Address for Local Expansion ROM Y 00000000 0x34 Reserved New Cap Ptr N 000000 40 0x38 Reserved N 00000000 Ox3C Max Lat Min Gnt Interrupt Pin Interrupt Line Y 7 0 00 00 01 00 0x40 PM Cap PM Nxt Cap PM Cap ID N 4801 00 01 0x44 PM Data PM CSR EXT PM CSR Y 00 00 0000 0x48 Reserved HS CSR HS Nxt Cap HS Cap ID Y 23 16 00 00 00 06 0x4C VPD Address VPD Nxt Cap VPD Cap ID Y 31 16 0000 00 03 0x50 VPD Data Y 00000000 Subsystem ID Value Offset 0 2 TPMC630 10 Figure 4 1 Default 9030 Header TPMC630 User Manual Issue 1 6 0x000A TPMC630 11 0 000 630 12 0x000C TPMC630 20 0 0014 TPMC630 21 0x0015 TPMC630 22 0 0016 Page 20 of 46 TEWS 42 TECHNOLOGIES 4 1 2 PCI Base Address Initialization PCI Base Address Initialization is scope of the PCI host software 9030 PCI Base Address Initialization 1 Write OxFFFF_FFFF to the PCI9030 PCI Base Address R
19. Local Re map Register Space 1 0x0000 0000 0x1C Local Re map Register Space 2 0x0000_0000 0x20 Local Re map Register Space 3 0x0000_0000 0x24 Local Re map Register ROM 0x0000_0000 0x28 Local Address Space 0 Descriptor 0 1581 20 0 Defines properties of space 0 2 Local Address Space 1 Descriptor 0x0000_0000 0x30 Local Address Space 2 Descriptor 0x0000_0000 0x34 Local Address Space 3 Descriptor 0x0000_0000 0x38 Local Exp ROM Descriptor 0x0000_0000 0x3C Chip Select 0 Base Address 0x0080_0001 Defines range for Chip Select 0x40 Chip Select 1 Base Address 0x0000_0002 0x44 Chip Select 2 Base Address 0x0000_0002 0x48 Chip Select 3 Base Address 0x0000_0002 4 Interrupt Control Status 0x0041 Ox4E EEPROM Write Protect Boundary 0x0030 0x50 Miscellaneous Control Register 0x0078 0000 0x54 General Purpose I O Control 0x0000 0240 0x70 Hidden1 Power Management data 0x0000_0000 select 0x74 Hidden 2 Power Management data 0x0000_0000 scale Figure 4 3 9030 Local Configuration Register TPMC630 User Manual Issue 1 6 Page 22 of 46 5 42 TECHNOLOGIES 4 3 Configuration EEPROM After power on or PCI reset the 9030 loads initial configuration register data from the on board configuration EEPROM The configuration EEPROM contains the following configuration data Address 0x00 to 0x27 PCI9030 PCI Configuration Register Values e Address 0x28 to 0x87 PCI9030 Local Configuration Register Values e Address 0x88 t
20. N6 LD 25 AA9 LD 10 V11 LD 26 P4 LD 11 AB15 LD 27 T5 LD 12 AA14 LD 28 9 LD 13 010 LD 29 V6 LD 14 W11 LD 30 Y7 LD 15 U9 LD 31 AB8 Figure 5 1 Pin Assignment Local Bus Data Signals TPMC630 User Manual Issue 1 6 Page 25 of 46 5 2 2 Pin Assignment of Local Bus Address Signals TEWS 42 TECHNOLOGIES Signal Pin Signal Pin LA 2 P3 LA 13 V4 LA 3 W6 LA 14 AB5 LA 4 T4 LA 15 R3 LA 5 AA7 LA 16 T3 LA 6 U4 LA 17 U3 LA 7 AB7 LA 18 V3 LA 8 LA 19 W3 LA 9 W5 LA 20 AB3 LA 10 AB6 LA 21 AA3 LA 11 Y5 LA 22 2 LA 12 5 LA 23 V2 Figure 5 2 Pin Assignment Local Bus Address Signals TPMC630 User Manual Issue 1 6 Page 26 of 46 TEWS 42 TECHNOLOGIES 5 2 3 Pin Assignment of Local Bus Control Signals Signal Pin Description LRESET T2 Local Reset LRD W1 Local Read LWR P1 Local Write LADS L1 Local Address Strobe LBE0 AA18 Local Byte Enable 0 LBE1 AB16 Local Byte Enable 1 LBE2 Y13 Local Byte Enable 2 LBE3 AA11 Local Byte Enable 3 LCS0 R1 Local Chip Select 0 LCS1 R2 Local Chip Select 1 LCS2 L2 Local Chip Select 2 LCS3 U1 Local Chip Select 3 LINT1 T1 Local Interrupt 1 LINT2 U2 Local Interrupt 2 LBLAST M1 Local Burst Last LRDY N2 Local Ready LW_R Y2 Local Write Read low active for reads high for writes LBTERM P2 Local Burst Termi
21. PGA_OE 19 121 FPGA_OE 51 N20 FPGA_OE 20 C10 FPGA_OE 52 V13 FPGA OE 21 A13 FPGA OE 53 AA16 FPGA OE 22 H21 FPGA OE 54 Y18 FPGA OE 23 F21 FPGA OE 55 AA20 FPGA OE 24 H22 FPGA OE 56 V14 FPGA OE 25 E22 FPGA OE 57 AA19 FPGA OE 26 P21 FPGA OE 58 M6 FPGA OE 27 M21 FPGA OE 59 L5 FPGA OE 28 A19 FPGA OE 60 R5 FPGA OE 29 B16 FPGA OE 61 W13 FPGA OE 30 P20 FPGA OE 62 Y14 FPGA OE 31 U22 FPGA OE 63 AA15 Figure 5 7 Pin Assignment FPGA Output Enable Lines TPMC630 User Manual Issue 1 6 Page 30 of 46 6 Configuration Hints 6 1 Big Little Endian PCI Bus Little Endian Byte 0 AD 7 0 Byte 1 AD 15 8 Byte 2 AD 23 16 Byte 3 AD 31 24 Big Endian Little Endian 32 Bit 32 Bit Byte 0 070 Bye 1 0116 8 Byte 2 0023 16 Bytes 0131 24 16 16 Bit Byte 0 070 1 015 8 16 Bit lower lane 8 Bit upper lane 8 Bit Byte 0 or 8 Bit lower lane bo 0 DIT 0 Figure 6 1 Local Bus Little Big Endian TPMC630 User Manual Issue 1 6 TEWS 42 TECHNOLOGIES Every Local Address Space 0 3 and the Expansion ROM Space can be programmed to operate in Big or Little Endian Mode Page 31 of 46 TEWS 42 TECHNOLOGIES Standard use of the TPMC630 example design Local Address Space 0 Local Address Space 1 Local Address Space 2 Local Address Space 3 Expansion ROM Space 32 bit bus in Big Endian Mode not used not used not used not used To cha
22. TEWS 2 The Embedded I O Company TECHNOLOGIES TPMC630 Reconfigurable FPGA with 64 TTL I O 32 Differential I O Lines Version 1 0 User Manual Issue 1 6 February 2008 D76630800 TEWS TECHNOLOGIES GmbH TEWS TECHNOLOGIES LLC Am Bahnhof 7 Phone 49 0 4101 4058 0 9190 Double Diamond Parkway Phone 1 775 850 5830 25469 Halstenbek Germany Fax 49 0 4101 4058 19 Suite 127 Reno NV 89521 USA Fax 1 775 201 0347 www tews com e mail info tews com www tews com e mail usasales tews com TPMC630 10 64 TTL IO Lines XC2S300E 6 5 FPGA TPMC630 11 32 Differential Lines XC2S300E 6 Spartan IIE FPGA TPMC630 12 32 TTL and 16 Differential I O Lines XC2S300E 6 FPGA TPMC630 20 64 TTL Lines 25600 6 Spartan llE FPGA TPMC630 21 32 Differential Lines XC2S600E 6 Spartan IIE FPGA TPMC630 22 32 TTL and 16 Differential I O Lines XC2S600E 6 FPGA TPMC630 User Manual Issue 1 6 TEWS 42 TECHNOLOGIES This document contains information which is proprietary to TEWS TECHNOLOGIES GmbH Any reproduction without written permission is forbidden TEWS TECHNOLOGIES GmbH has made any effort to ensure that this manual is accurate and complete However TEWS TECHNOLOGIES GmbH reserves the right to change the product described in this document at any time without notice TEWS TECHNOLOGIES GmbH is not liable for any damage arising ou
23. al time debugging of the FPGA design using Xilinx ChipScope A programmable clock generator provides up to six different clock output frequencies between 200 kHz and 166 MHz All outputs are available at the FPGA one clock source is in addition used as the local clock signal for the PCI controller The clock generator settings are stored in an EEPROM and can be changed by the driver software through the PCI Target Controller The configuration EEPROM of the PCI Target Controller can also be modified by the driver software to adapt address spaces etc User applications can be developed using the design software ISE WebPACK which can be downloaded free of charge from www xilinx com The TPMC630 provides front panel I O via a HD68 SCSI 3 type connector and rear panel I O via P14 For First Time Users the Engineering Documentation is recommended it includes schematics data sheets of the components and well documented sample VHDL source code 64 x TTL I O TPMC630 10 Clocks Flash 92 5 Differential Drivers TPMC630 11 or 32 TTLI O and 16 x Differential Drivers TPMC630 12 HD68 Connector Figure 1 1 Block Diagram TPMC630 User Manual Issue 1 6 Page 8 of 46 TEWS S TECHNOLOGIES 2 Technical Specification PMC Interface Mechanical Interface PCI Mezzanine Card PMC Interface Single Size Electrical Interface PCI Rev 2 1 compliant 33 MHz 32 bit PCI 3 3V and 5V PCI Signaling Voltag
24. bit 0 to 1 To enable PCI Memory Space access to the PCI9030 set bit 1 to 1 Offset in Config Description Usage 0x10 PCI9030 LCR s MEM Used 0x14 9030 LCR s I O Used 0x18 PCI9030 Local Space 0 Used Ox1C PCI9030 Local Space 1 Not used 0x30 Expansion ROM Not used Figure 4 2 PCI9030 PCI Base Address Usage TPMC630 User Manual Issue 1 6 Page 21 of 46 TEWS 42 TECHNOLOGIES 4 2 Local Configuration Register LCR After reset the PCI9030 Local Configuration Registers are loaded from the on board serial configuration EEPROM The PCI base address for the PCI9030 Local Configuration Registers is PCI9030 PCI Base Address 0 PCI Memory Space Offset 0x10 in the PCI9030 PCI Configuration Register Space or PCI9030 PCI Base Address 1 PCI I O Space Offset 0x14 in the PCI9030 PCI Configuration Register Space Please be very careful when changing any hardware dependent bit settings in the PCI9030 Local Configuration Registers Offset from Register Default Value Description PCI Base Address 0x00 Local Address Space 0 Range 0 0 00 0000 Defines size of space 0x04 Local Address Space 1 Range 0x0000_0000 0x08 Local Address Space 2 Range 0x0000_0000 OxOC Local Address Space 3 Range 0x0000 0000 0x10 Local Exp ROM Range 0x0000 0000 0x14 Local Re map Register Space 0 0x0000 0001 Defines local address of space 0x18
25. cess Reset Value 31 OUT REG 31 30 OUT 30 29 OUT 29 28 OUT 28 27 OUT REG BIT 27 26 OUT REG BIT 26 25 OUT REG BIT 25 24 OUT REG BIT 24 23 OUT REG BIT 23 22 OUT REG BIT 22 21 OUT REG BIT 21 20 OUT REG BIT 20 19 OUT REG BIT 19 18 OUT REG BIT 18 17 OUT REG BIT 17 16 OUT REG BIT 16 Output Port Bit 31 0 Data 15 OUT REG 15 notes below 14 OUT REG BIT 14 13 OUT REG BIT 13 12 OUT REG BIT 12 11 OUT REG BIT 11 10 OUT REG BIT 10 OUT REG BIT 9 OUT REG BIT 8 OUT REG BIT 7 OUT REG BIT 6 OUT REG BIT 5 OUT REG BIT 4 OUT REG BIT 3 OUT REG BIT 2 OUT REG BIT 1 OUT REG BIT 0 RAN 0 c O NI Figure 3 3 Output Register 0 OUT REGO TPMC630 x0 Output Port Bits 0 31 are written to lO 0 IO 31 TTL TPMC630 x1 Output Port Bits 0 31 are written to OA B IO 31A B Differential TPMC630 x2 Output Port Bits 0 15 are written to OA B IO 15A B Differential Output Port Bits 16 31 are not used TPMC630 User Manual Issue 1 6 Page 11 of 46 TEWS S TECHNOLOGIES 3 2 2 Output Register 1 OUT 0x04 Bit Symbol Description Access 63 OUT REG 63 62 OUT 62 61 61 60 60 59 59 58
26. e On Board Devices PCI Target Chip PCI9030 PLX Technology Local Control Logic TPMC630 1x FPGA Spartan lIE 25300 6 FG456 Xilinx TPMC630 2x FPGA Spartan lIE XC2S600E 6 FG456 Xilinx TTL Line Transceivers TALVT126 Interface Number of Channels 64 TTL I O TPMC630 x0 32 differential I O TPMC630 x1 or 32 TTL I O and 16 differential I O TPMC630 x2 TTL signaling voltage level maximum current 32 mA or EIA 422 485 signaling level Connectors Front I O HD68 SCSI 3 type Connector AMP 787082 7 or compatible PMC P14 I O 64 pin Mezzanine Connector Physical Data Power Requirements with Example Design TPMC630 x0 160mA typical no load 3 3V DC TPMC630 x1 110mA typical no load 3 3V DC 630 2 120mA typical no load 3 3V DC 10mA typical 5V DC TPMC630 x0 when used as pull up voltage 5V DC not used on TPMC630 x1 10mA typical 5V DC TPMC630 x2 when used as pull up voltage Temperature Range Operating 40 C to 85 C Storage 40 C to 85 C MTBF TPMC630 x0 407000 h TPMC630 x1 451000 h TPMC630 x2 428000 h Humidity 5 95 non condensing Weight 80g TPMC630 User Manual Issue 1 6 Figure 2 1 Technical Specification Page 9 of 46 TEWS 42 TECHNOLOGIES 3 Local Space Addressing 3 1 PCI9030 Local Space Configuration The local on board addressable regions are acce
27. e 6 of 46 TEWS 42 TECHNOLOGIES FIGURE 8 6 PIN ASSIGNMENT P14 CONNECTOR TPMC630 X1 45 FIGURE 8 7 PIN ASSIGNMENT P14 I O CONNECTOR 6 2 46 TPMC630 User Manual Issue 1 6 Page 7 of 46 TEWS S TECHNOLOGIES 1 Product Description The TPMC630 is a standard single width 32 bit PMC module providing a user configurable FPGA with 300 000 TPMC630 1x or 600 000 TPMC630 2x system gates All local signals from the PCI controller are routed to the FPGA The TPMC630 x0 has 64 ESD protected TTL lines the TPMC630 x1 provides 32 differential I O lines using EIA 422 EIA 485 compatible ESD protected line transceivers The TPMC630 x2 provides 32 TTL and 16 differential I Os All lines are individually programmable as input output or tri state The receivers are always enabled which allows determining the state of each I O line at any time This can be used as read back function for lines configured as outputs Each TTL I O line has a pull up resistor The pull up voltage is selectable to be either 3 3V or 5V The differential I O lines are terminated by 1200 resistors The FPGA is configured by a serial Flash The Flash device is in system programmable via driver software over the PCI bus An in circuit debugging option is available via an optionally mountable JTAG header on the backside of the board for readback and re
28. egister 2 Read back the PCI9030 PCI Base Address Register 3 For PCI Base Address Registers 0 5 check bit 0 for PCI Address Space Bit 0 0 requires PCI Memory Space mapping Bit 0 1 requires PCI I O Space mapping For the PCI Expansion ROM Base Address Register check bit 0 for usage Bit 0 0 Expansion ROM not used Bit 0 1 Expansion ROM used 4 For PCI I O Space mapping starting at bit location 2 the first bit set determines the size of the required PCI I O Space size For PCI Memory Space mapping starting at bit location 4 the first bit set to 1 determines the size of the required PCI Memory Space size For PCI Expansion ROM mapping starting at bit location 11 the first bit set to 1 determines the required PCI Expansion ROM size For example if bit 5 of a PCI Base Address Register is detected as the first bit set to 1 the PCI9030 is requesting a 32 byte space address bits 4 0 are not part of base address decoding 5 Determine the base address and write the base address to the PCI9030 PCI Base Address Register For PCI Memory Space mapping the mapped address region must comply with the definition of bits 3 1 of the PCI9030 PCI Base Address Register After programming the PCI9030 PCI Base Address Registers the software must enable the 9030 for PCI I O and or PCI Memory Space access in the PCI9030 PCI Command Register Offset 0x04 To enable PCI I O Space access to the 9030 set
29. gisters Description Default values CLK1 Output of Clock Generator 50 MHz CLK2 Output of Clock Generator 20 MHz CLK3 Output of Clock Generator 10 MHz CLK4 Output of Clock Generator 1 MHz CLK5 Output of Clock Generator 200 kHz CLK6 Output of Clock Generator Off Figure 6 2 Default values of clock outputs at delivery TPMC630 User Manual Issue 1 6 Page 33 of 46 Offset Description Default values 0x09 CLKOE control DIV1SRC mux DIV1N divider 0x64 0x10 Input Pin Control Registers 0x50 0x11 Write Protect Registers 0x04 0x12 Input crystal oscillator drive control 0x20 0x13 Input load capacitor control 0x00 0x14 ADC Register 0x00 0x40 Charge Pump and PB counter 0xC0 0x41 Charge Pump and PB counter 0x03 0x42 PO counter Q counter 0x81 0x44 Crosspoint switch matrix control 0x42 0x45 Crosspoint switch matrix control 0x9F 0x46 Crosspoint switch matrix control 0x3F 0x47 DIV2SRC mux and DIV2N divider OxE4 TPMC630 User Manual Issue 1 6 Figure 6 3 Default register values at delivery TEWS S TECHNOLOGIES Page 34 of 46 TEWS S TECHNOLOGIES 7 Installation 7 1 Pull Up Voltage The voltage of the pull up resistors can be 3 3V or alternatively 5V specified by jumper J1 The default pull up voltage is 3 3V J1 Jumper Position Pull Up Voltage 1 2 3 3V default 2 3 5V Figure 7 1
30. group of ten slave devices on the 2 wire bus The address of the clock configuration EEPROM is 0x68 Changes of the clock configuration by writing to the SRAM at address 0x69 should only be done with caution as these changes take immediately effect at the clock outputs This could cause problems by the occurrence of glitches Especially the LCLK input of the PCI9030 which is the CLK1 signal on the board should never be changed during operation recommendation by PLX For the same reason a soft reset of the device should not be activated after reprogramming the CY27EE16 clock configuration EEPROM Soft reset is generated by setting the MSB in the SRAM space at offset 0x00 followed by 2 stop This will update the SRAM as it is done at power up The CLK1 output of the CY27EE16 must never be switched off Off or Hi Z and the frequency has to be within 0 60 MHz When the local clock is switched off the 9030 will not work and the CY27EE16 can t be reprogrammed any more The board would have to be sent to the manufacturer for repair A detailed register description and the exact programming timing can be found in the datasheet of the CY27EE16 This is part of the TPMC630 ED Engineering Documentation and is also available at www cypress com as well as the CyberClocks software a tool which helps calculating the register values The drivers available from TEWS TECHNOLOGIES provide routines for easy setting of the CY27EE16 re
31. nate Figure 5 3 Pin Assignment Local Bus Control Signals In the VHDL example code low active signals have an n as last character instead of the 5 2 4 Pin Assignment of Clock Signals Signal Pin Description Default values BCLK AA12 Buffered PCI Clock PCI Clock from Carrier CLK1 AB12 CLK1 Output of Clock Generator 50 MHz CLK2 11 CLK2 Output of Clock Generator 20 MHz CLK3 C11 CLK3 Output of Clock Generator 10 MHz CLK4 AB21 CLK4 Output of Clock Generator 1 MHz CLK5 W22 CLK5 Output of Clock Generator 200 kHz CLK6 U21 CLK6 Output of Clock Generator Off Figure 5 4 Pin Assignment Clock Inputs TPMC630 User Manual Issue 1 6 Page 27 of 46 5 2 5 Pin Assignment of FPGA Input Lines TEWS 42 TECHNOLOGIES Signal Pin Signal Pin FPGA_IN 0 1 FPGA_IN 32 E19 FPGA_IN 1 C1 FPGA_IN 33 E20 FPGA_IN 2 D2 FPGA_IN 34 F11 FPGA_IN 3 D3 FPGA_IN 35 F19 FPGA_IN 4 G3 FPGA_IN 36 N18 FPGA_IN 5 C5 FPGA_IN 37 N19 FPGA_IN 6 F5 FPGA_IN 38 J4 FPGA_IN 7 B7 FPGA_IN 39 M18 FPGA_IN 8 AQ FPGA_IN 40 M20 FPGA_IN 9 C8 FPGA_IN 41 J5 FPGA_IN 10 A14 FPGA_IN 42 L18 FPGA_IN 11 C12 FPGA_IN 43 H4 FPGA_IN 12 C9 FPGA IN 44 U13 FPGA IN 13 B10 FPGA IN 45 V15 FPGA IN 14 C15 FPGA IN 46 U14 FPGA IN 15 D
32. nge the Endian Mode use the Local Configuration Registers for the corresponding Space Bit 24 of the according register sets the mode A value of 1 indicates Big Endian and a value of 0 indicates Little Endian For further information please refer to the PCI9030 manual which is also part of the TPMC630 ED Engineering Documentation Use the PCI Base Address 0 Offset or PCI Base Address 1 Offset Short cut LASOBRD LAS1BRD LAS2BRD LAS3BRD EROMBRD Offset Name 0x28 Local Address Space 0 Bus Region Description Register Ox2C Local Address Space 0 Bus Region Description Register 0 30 Local Address Space 0 Bus Region Description Register Ox34 Local Address Space 0 Bus Region Description Register 0x38 Expansion ROM Bus Region Description Register You could also use the PCI Base Address 1 I O Mapped Configuration Registers TPMC630 User Manual Issue 1 6 Page 32 of 46 TEWS 42 TECHNOLOGIES 6 2 Clock Programming A Cypress CY27EE16 can be used for generating up to six clock frequencies an oscillator provides the reference clock of 20 MHz CY27EE16 is programmed over a serial 2 wire programming interface with the serial clock signal SCLK and the serial data signal SDAT These two signals are directly controlled by the PLX PCI9030 the SDA signal by GPIO7 and SCL by EESK Because of the shared EESK signal the serial configuration EEPROM and the CY27EE16 cannot be accessed simultaneously The CY27EE16 is addressed as a
33. o OxFF Reserved See the 9030 Manual for more information The following table shows the default content of the EEPROM Address Offset 0x0000 0x0001 0x0C s b 0 0000 0 00 0 02 0 04 0 06 OxOE 0x0276 0x1498 0x0280 0x0000 0x10 0x0000 0x0040 0x0000 0x0100 0x20 0x0000 0x0006 0x0000 0x0003 0x1180 0x4801 0x0000 0x50 0x60 0x0000 0x0000 0x70 0x80 Ox0000 0 0000 0 0000 0 0000 OxFFFF OxFFFF OxFFFF OxFFFF 0 90 OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxAO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxBO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxDO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxEO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF Figure 4 4 Configuration EEPROM TPMC630 Subsystem ID Value Offset 0 0 TPMC630 10 0x000A TPMC630 11 0 000 TPMC630 12 0x000C TPMC630 20 0x0014 TPMC630 21 0x0015 TPMC630 22 0 0016 Highlighted values can be modified by the driver software TPMC630 User Manual Issue 1 6 Page 23 of 46 5 42 TECHNOLOGIES 4 4Local Soft
34. side to be accessible when the PMC is mounted and to have the correct pinning for Xilinx cables e g Parallel Cable IV or others Pin 1 is marked by a squared pad see next figure This is of cause a violation of the maximum component height given by the CMC specification be sure that there is enough space to neighboring cards X2 Figure 7 6 Debug Connector Bottom View TPMC630 User Manual Issue 1 6 Page 39 of 46 TEWS S TECHNOLOGIES 8 Pin Assignment I O Connector 8 1 Front Panel I O Connector AMP 787082 7 or compatible Pin 34 Pin 1 y Pin 68 Pin 35 Figure 8 1 Front Panel I O Connector Numbering TPMC630 User Manual Issue 1 6 Page 40 of 46 TEWS 42 TECHNOLOGIES 8 1 1 Front I O Assignment TPMC630 x0 Pin Signal Level Pin Signal Level o o os 34 IO 62 TTL 68 63 TTL Figure 8 2 Pin Assignment Front I O Connector TPMC630 x0 r O z TPMC630 User Manual Issue 1 6 Page 41 of 46 5 42 TECHNOLOGIES 8 1 2 Front I O Assignment TPMC630 x1 Pin Signal Level o jep
35. ssed from the PCI side by using the 9030 local spaces 9030 9030 Size Port Endian Description Local Address Space Byte Width Mode Space Offsetin Pci Mapping Bit Configuration Space 0 2 0x18 MEM 16M 32 BIG FPGA Example Design Register Space 1 3 0x1C Not Used 4 0x20 Not Used 5 0x24 Not Used Figure 3 1 PCI9030 Local Space Configuration 3 2 FPGA Example Design Register Space The TPMC630 is delivered with a FPGA example design in the configuration memory PCI Base Address PCI9030 PCI Base Address 2 Offset 0x18 in PCI Configuration Space Offset to PCI Register Name Size Base Address 2 Bit 0x00 OUTPUT REGISTER 0 OUT REGO 32 0x04 OUTPUT REGISTER 1 OUT REG1 32 0x08 INPUT REGISTER 0 IN REGO 32 0x0C INPUT REGISTER 1 IN_REG1 32 0x10 OUTPUT ENABLE REGISTER 0 OE_REG0 32 0x14 OUTPUT ENABLE REGISTER 1 OE_REG1 32 0x18 INTERRUPT STATUS REGISTER ISR 32 0x1C POSITIVE EDGE INTERRUPT ENABLE REGISTER 32 PIER 0x20 NEGATIVE EDGE INTERRUPT ENABLE REGISTER 32 NIER 0x24 RAM ADDRESS MAP REGISTER RAMR 32 28 256 x 32 bit RAM Space 32 Figure 3 2 FPGA Example Design Register Space TPMC630 User Manual Issue 1 6 Page 10 of 46 TEWS 42 TECHNOLOGIES 3 2 1 Output Register 0 OUT_REGO 0x00 Bit Symbol Description Ac
36. t of the application or use of the device described herein Style Conventions Hexadecimal characters are specified with prefix Ox 029 that means hexadecimal value 029 For signals on hardware products an Active Low is represented by the signal name with following i e IP_RESET Access terms are described as W Write Only R Read Only RW Read Write R C Read Clear R S Read Set 2005 2008 by TEWS TECHNOLOGIES GmbH Page 2 of 46 TEWS TECHNOLOGIES Issue Description Date 1 0 First Issue July 2005 1 1 Technical Specifications added September 2005 1 2 Default Pull Up Voltage changed October 2005 1 3 TTL Transceivers changed March 2006 1 4 Pin out description for each variant May 2006 1 5 New address TEWS LLC September 2006 1 6 New module variants 2x February 2008 TPMC630 User Manual Issue 1 6 Page 3 of 46 TEWS 42 TECHNOLOGIES Table of Contents 1 PRODUCT 8 2 TECHNICAL SPECIFICATION u Uu UU U 9 LOCAL SPACE ADDRESSINGQ U T 10 3 1 PCI9030 Local Space Configuration 10 3 2 FPGA Example Design Regis
37. ter Space U 10 3 2 1 Output Register 0 OUT 0 00 11 3 2 2 Output Register 1 OUT 0 4 12 3 2 3 Input Register 0 REGO 13 3 24 Input Register 1 IN 0x0C 14 3 2 5 Output Enable Register 0 OE REGO 0x10 emen 15 3 2 6 Output Enable Register 1 OE REG1 0x14 U ens 16 3 2 7 Interrupt Status Register ISR 18 17 3 2 8 Positive Edge Interrupt Enable Register PIER 0 1 6 17 3 2 9 Negative Edge Interrupt Enable Register 0 20 18 3 2 10 RAM Address Map Register RAMR 0 24 19 39 2 11 Per ve a 19 4 TARGET CHIP IT 20 4 1 PCI Configuration Registers PCR U U u u u 20 4 171 9030 ae tt dea tee i e 20 4 1 2 PCI Base Address rdv 21 4 2 Local Configuration Register LCR 22 4 3 Contiguration EEPROM E CC LINEA 23 4 4 Local Software 5 cate ua 24
38. tes NWAD Wait States 00010 Write Address to Data wait states NWDD Wait States 00 Write Data to Data wait states Local Address Space 0 Local Bus Width 10 32 bit bus width Byte Ordering 1 Big Endian Big Endian Byte Lane Mode 0 Use lanes 15 0 7 0 in non 32 bit modes Read Strobe Delay 01 Delay until assertion of RD Write Strobe Delay 01 Delay until assertion of WR Write Cycle Hold 00 Hold data after Figure 4 5 Default values of Space 0 Region Descriptor TPMC630 User Manual Issue 1 6 Page 24 of 46 TEWS 42 TECHNOLOGIES 5 FPGA Programming Hints 5 1 FPGA Design Custom FPGA designs can be developed using a commercial version like Xilinx ISE Foundation or the ISE WebPACK downloadable free of charge www xilinx com ise Taking the VHDL example provided with the Engineering Documentation would be a good basis After implementing the logic the resulting xsvf file can be downloaded to the configuration flash by the driver A detailed description of the example files and how to generate the configuration bit stream file is part of the Engineering Documentation 5 2 FPGA Pin Assignment 5 2 1 Pin Assignment of Local Bus Data Signals Signal Pin Signal Pin LD 0 W7 LD 16 AB13 LD 1 V7 LD 17 Y11 LD 2 AA10 LD 18 P6 LD 3 P5 LD 19 N5 LD 4 Y10 LD 20 L3 LD 5 M4 LD 21 N4 LD 6 W10 LD 22 M3 LD 7 K3 LD 23 Y9 LD 8 M5 LD 24 AB10 LD 9
39. ware Reset The 9030 Local Reset Output LRESETo is used to reset the on board local logic The 9030 local reset is active during PCI reset or if the PCI Adapter Software Reset bit is set in the 9030 local configuration register CNTRL offset 0x50 CNTRL 30 PCI Adapter Software Reset Value of 1 resets the PCI9030 and issues a reset to the Local Bus LRESETo asserted 9030 remains in this reset condition until the PCI Host clears this bit The contents of the 9030 PCI and Local Configuration Registers are not reset The 9030 PCI Interface is not reset 4 5 Local Bus The PCI9030 Local Bus is a 32 bit non multiplexed bus Many parameters of the local interface can be configured such as wait states delays etc see PCI9030 Data Book The default values of the Local Address Space 0 Bus Region Descriptor LASOBRD 0x28 for the example design are Bit Description Local Address Space 0 Burst Enable 0 Bursting disabled Local Address Space 0 READY Input Enable 0 READY input disabled Local Address Space 0 BTERM Input Enable 0 BTERM input disabled Prefetch Count 00 Do not prefetch disable Prefetch Counter Enable 1 Set to 1 disabled by Prefetch Count 0 NRAD Wait States 00010 Read Address to Data wait states NRDD Wait States 00 Read Data to Data wait states NXDA Wait States 01 Read Write Data to Address wait sta

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