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Update 8 Release Notes

1. VisualDSP 5 0 Update 8 Release Notes Rev 2 1 Page 8 8 Other Examples This section specifies new examples that are not specific to an evaluation board ACM Example ADSP BF506F Sample_ADC_ACM_Control example demonstrates how the ADC on ADSP BF506F processor can be operated using the ADC Controller Module ACM The example uses a GP Timer as external trigger to start ACM events ACM service handles the ADC control signals as per its event configuration settings and captures ADC samples to a data buffer This example has been added for the ADSP BF506F EZ KIT Lite Blackfin Examples ADSP BF506F EZ KIT Lite Drivers ADC Sample ADC ACM Control Audio Loopback Example ADSP BF518F The following audio loopback example has been added for the ADSP BF518F EZ Board Blackfin Examples ADSP BF518F EZ Board Drivers AudioCodec Audio_ Loopback Standard I O Service Example ADSP BF527 548 EZ KIT Lites The following examples have been added to demonstrate use of the new Standard I O System Service Blackfin Examples ADSP BF527 EZ KIT Lite Services stdio char_echo Blackfin Examples ADSP BF548 EZ KIT Lite Services stdio char echo Memory Service Example ADSP BF548 EZ KIT Lite The following examples have been added to demonstrate use of the new Memory Service Blackfin Examples ADSP BF548 EZ KIT Lite Services Mem CustomAlgorithm Blackfin Examples ADSP BF548 EZ KIT Lite Service
2. Cloning VisualDSP VisualDSP supports cloning of an existing installation A clone of an installation creates a new instance of a product from an existing installation rather than from a CD or web software distribution The use of clones allows you to maintain multiple versions of VisualDSP on the same PC at different update levels and provides a risk free way to test new updates or patches To clone your existing installation of VisualDSP VisualDSP 5 0 Update 6 Release Notes Rev 1 3 Page 6 3 9 Go to Start gt Programs gt Analog Devices gt VisualDSP 5 0 or equivalent gt Maintain this Installation 10 Select Clone this Installation and click Next 11 Optionally click Advanced to set the Start menu path 12 Enter the Clone install path and click Next Definitions This section provides definitions for terminology relating to VisualDSP and this document TAR Tools Anomaly Reference Number Tools Anomaly Reference Number or TAR is used for tracking confirmed defect reports in VisualDSP VisualDSP 5 0 Update 6 Release Notes Rev 1 3 Page 6 4 New Hardware Support VisualDSP updates often include support for new processors new silicon revisions for existing processors and new EZ KIT Lite and EZ Board evaluation systems In order to support these minor revisions are made to the tool chain and additional system services and device drivers need to be added This section describes the new suppo
3. Identifying Your VisualDSP Version The VisualDSP release and update level can be found in 2 locations In the Control Panel open the Add Remove Programs applet In the VisualDSP Development Environment select Help About VisualDSP In these locations VisualDSP 5 0 should be visible without any update listed Installing the Update Please follow the instructions below for installing this update Please note that since VisualDSP supports having multiple instances installed on a single system you can install this update on top of one instance while keeping the previous installation Use the Start Menu to navigate to VisualDSP Maintain this installation By default this is at Start Menu select All Programs Analog Devices VisualDSP 5 0 Select Go to the Analog Devices website and click Next This will open a window in your web browser Select the appropriate Processor Software Tools Upgrades to match your processor Select and download the desired update VisualDSP 5 0_Update2 vdu to your hard drive Again use the Start Menu to navigate to VisualDSP Maintain this installation Select Apply a downloaded Update and click Next Browse for the downloaded Update file VisualDSP 5 0_Update2 vdu and click Next Follow the on screen prompts to complete installation of this Update VisualDSP 5 0 Update 1 Release Notes Rev 1 1 Page 1 2 New Hardware Support VisualDSP updates often i
4. ADSP BF54x VDK LDF causes a linker error when USE_L2_ STACK is Blackfin 43445 VDK defined VisualDSP 5 0 Update 8 Release Notes Rev 2 1 Page 8 24 au 43576 Short Word Memory window does not display external address range A Memory two column hexadecimal data window during a 21479 SHARC 44132 Simulator Simulator session it doesn t display the both address values SHARC 42050 vox VDK LDFs for 2137x link in 36x versions of libcpp SHARC 41860 XML Files Anomaly detection for anomaly 15000005 is not enabled comments in sysreg h incorrectly state that link control and status TigerSHARC 43068 Run Time Libraries registers are quadable and or pairable Known Tools Anomalies Details can be found on the Tools Anomaly Web page The URL is http www analog com processors tools anomalies Software Anomalies Addressed The following table is a list of software anomalies addressed in VisualDSP 5 0 Update 8 In the future these details will also be searchable on the public tools anomaly website Other tools anomalies have also been fixed in the Update Software Processor Anomaly Family Report Tool Description Error in usb mass storage read capacity return value for N ice Software and Stack EH dek a ea File File System Service Service Add API to File Add API to File System to report volume usage stats to report volume usage stats Blackfin um File System Service MAC system files get overwritten by FAT driver FSS
5. OXxFF clear it to make sure USB will work after booting pUSB_APHY CNTRL 0 setup calibration register pUSB APHY CALIB 0x5411 ssync Similarly for ADSP BF52x ZE 0x00 pDSPID OxFF 0x01 pDSPID amp OxFF clear it to make sure USB will work after booting pUSB_APHY CNTRL 0 setup calibration register pUSB_APHY CALIB 0x6510 ssync Another aspect of the improvements in robustness the USB controller driver changed to use separate handlers for each of the four USB interrupts ADI_INT_USB_INTO ADI_INT_USB_INT1 ADI_INT_USB_INT2 ADI_INT_USB_DMAINT By default all the USB Interrupt handlers are chained at the default USB priority level IVG 11 for ADSP BF54x and IVG10 for ADSP BF52x It is important therefore that memory is made available to the interrupt manager for three additional secondary interrupt handlers Otherwise you may see the following message displayed in the Output Window of VisualDSP 5 0 ERROR Insufficient Memory in the Interrupt Manager VisualDSP 5 0 Update 6 Release Notes Rev 1 3 Page 6 16 USB requires memory for four secondary handlers sizeof ADI INT SECONDARY MEMORY 4 Supply more memory using adi int Init The simplest way to resolve the issue is to increase the amount of memory passed to the adi_int_Init routine by 3 ADI_INT_SECONDARY_MEMORY You could also experiment with changing the IVG lev
6. VisualDSP 5 0 Update 2 Release Notes Rev 1 1 Page 2 7 ADSP BF52x Silicon Anomaly 05 00 0380 Data Read from L3 Memory by USB DMA May be Corrupted To workaround this anomaly the USB Physical Interface Driver employs an intermediate buffer in L1 memory The larger this buffer the better the performance However the driver that is released with VisualDSP 5 0 employs a medium sized L1 buffer of size 8KB providing 10MB s read throughput and 0 8MB s write throughput These figures represent a 30 decrease in performance compared to the driver implemented for the ADSP BF548 processor Invalid SCLK Frequency for ADSP BF548 at Power Up TAR 35129 At power up SCLK frequency on ADSP BF548 EZ KIT Lite must be set to within 83MHz 133MHz if the stack or heap is located in DDR or else adi_pwr_SetFreq may fail The ADSP BF548 EZ KIT Lite is populated with double data rate SDRAM DDR There are two types of DDR mobile and non mobile The EZ kit uses non mobile DDR The nominal system clock SCLK frequency range for non mobile DDR is 83 MHz to 133 MHz The input clock CLKIN on the ADSP BF548 is 25MHz At reset the multiplier select MSEL value in the PLL control register PLL_CTL is decimal 10 while the PLL divider ratio register PLL_DIV contains 5 Together these values produce a SCLK value of 50MHz 25 10 5 which is below the minimum for non mobile DDR to work properly Therefore DDR should not be accessed until after
7. Blackfin and SHARC Due to popular demand 64 bit Windows drivers for bulk transfers are now included This has been tested on 64 bit Windows 7 Windows Vista and Windows XP Also support for USB has been added for the ADSP 21479 and ADSP 21489 EZ Boards VisualDSP 5 0 Update 8 Release Notes Rev 2 1 Page 8 15 Silicon Anomaly Workarounds Anomaly workaround information is available in the online help Select Help gt Contents gt Graphical Environment gt Silicon Anomaly Support gt Silicon Anomalies Tools Support and then click the appropriate processor series Silicon Errata Parts Workaround Support Further information Added 05000477 TESTSET Instruction cannot Be Interrupted 02000069 Incorrect Popping of stacks possible when exiting IRQx Timer Interrupts with DB modifiers 04000068 Incorrect Popping of stacks possible when exiting IRQx Timer Interrupts with DB modifiers 06000020 Indirect jumps or calls followed by Long Word accesses using PM bus or invalid instruction can vector to an unknown location 06000028 Incorrect Popping of stacks possible when exiting IRQx Timer Interrupts with DB modifiers 07000022 External FLAG based conditional instructions involving DAG register post modify operations must not be followed immediately by an instruction that uses the same index register as the register might not be updated with the result of the modify 08000028 External FLAG based conditional instructio
8. Emulator Incorrect display of instructions in external memory on Sharc SHARC 35013 Emulator Cannot load 16 bit external memory on 2126x Flash SHARC 34792 Programmer ADSP 21375 SPI flash will change from the Atmel to the STMicro Run Time SHARC 33670 Libraries SIG_MTM to be defined for 21362 3 4 5 6 Run Time SHARC 34727 Libraries sinf may return poor results for inputs close to a 2 PI multiple Known Problems Details can be found on the Tools Anomaly Web page The URL is http www analog com processors tools anomalies VisualDSP 5 0 Update 2 Release Notes Rev 1 1 Page 2 10 VisualDSP 5 0 Update 1 Release Notes Revision 1 1 2008 February 26 Table of Contents Nomenclatura xiii yredaniceateiatanncare uate said Ge edsantigasiadaureoonieead bed aenloel a 1 2 INSTA EE 1 2 Identifying Your VisualDSP Version ooooococncccccnoconononnnnnnnonnnnnnnononnnnnnnnonnnnnnnonnnnnnnnnnnnnnnonnnos 1 2 Installing the Update abia 1 2 New Hardware Upon EE ES A 1 3 New Processors and Revisions Support 1 3 New Emulation E ee O NEE 1 3 New System Services and Device Drivers 1 3 NANTA DEAT OLEE A E 1 5 ele sie 1 5 Getting Started EU e EE 1 5 EnticalExes Chantada aa 1 6 ADSP BF522 processor name change 1 6 Two header files for builtins_support h files TAR 22040 1 6 SSL USB and DRV libs for ADSP BF52x not in default LDFs TAR 24050 1 6 Default changed for EBIU_SDBCTL for ADSP BF533 LDF TAR 22401 1
9. SPORT is simultaneously accessing data in L1 or L2 Workaround No workaround exists in the driver The application developer needs to manage buffers such that when multiple peripherals are used with buffers in L1 or L2 USB buffers are placed in L3 or vice versa Silicon Anomaly 05000465 ADSP BF52x USB Receive DMA hang VisualDSP 5 0 Update 7 Release Notes Rev 1 0 Page 7 16 USB Rx DMA hangs if the endpoint FIFOs are configured in double buffer mode This is the case when MaxPacketSize in USB_EP_NIx_RXMAXP is equal or less than half the endpoint FIFO size When double buffering is enabled there is the possibility of a race condition where RxPktRdy is set and cleared in the same cycle When this happens RxPktRdy will remain cleared thus preventing the USB DMA from unloading the FIFO resulting in a Rx DMA hang This can manifest itself when SCLK is at or below 100 MHz Workaround Use DMA mode 0 with double buffering disabled This is implemented in the HDRC driver by default for ADSP BF52x only in VisualDSP 5 0 Update 7 Silicon Anomaly 05000466 ADSP BF52x ADSP BF54x TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access Endpoint FIFOs Simultaneously TX DMA data can be lost when both the USB DMA and the core access two different USB endpoint FIFOs at the same time The DMA pointer does not increment correctly for the last two bytes of the DMA accessed FIFO preventing the USB controller from settin
10. delay SHARC 36540 Compiler slot SHARC 36621 Compiler bad optimization of conditional stores SHARC 34165 Run Time Libraries using saturate h will result in errors SHARC 36489 Run Time Libraries strncat incorrect if strings in different memory banks SHARC 36598 Run Time Libraries The strncat implementation for DM to PM is flawed SHARC 36600 Run Time Libraries Strncat of NULL string behaves incorrectly division support funcs incorrect when placed in external SHARC 36709 Run Time Libraries memory SHARC 36770 Run Time Libraries MISRA violation 8 8 with string h and builtins h SHARC 36914 Run Time Libraries Byte address mode qsort multi thread can cause failure SHARC 36919 Run Time Libraries FFT functions read beyond the end of an array 64 bit double addition with results close to zero denorm SHARC 37382 Run Time Libraries wrong Some run time library functions use dual data move SHARC 37863 Run Time Libraries instructions SHARC 35592 Simulator Interrupt during abort of an arithmetic loop never serviced Known Tools Anomalies Details can be found on the Tools Anomaly Web page The URL is http VisualDSP 5 0 Update 5 Release Notes Rev 1 8 www analog com rocessors tools anomalies Page 5 18 VisualDSP 5 0 Update 4 Release Notes Revision 1 2 September 3 2008 Table of Contents Nomenclature 2d tated O TEE RA E 4 2 Release NOLES E E AE E TEE EE E E ET 4 2 Installati n rita AA RA A AA AS AAAA
11. 1 MISRA Rule 21 1 run time checking of global arrays not Blackfin 36341 Compiler enabled typedef d bit fields can be incorrectly packed with Blackfin 36424 Compiler pragma pack MISRA Rule 19 4 not always suppressed using pragma Blackfin 36453 Compiler diag Debug agent scans too fast can cause external memory Blackfin 30369 Debug Agent issues ADSP BF527 LCD Example does not work with deferred Blackfin 36186 Device Driver callbacks Blackfin 34944 Run Time Libraries clock is not thread safe 05 00 0248 workaround in adi_acquire_lock and Blackfin 35495 Run Time Libraries adi_try_lock default multi thread CRT objects may result in CPLB Blackfin 36110 Run Time Libraries misses Blackfin 36125 Run Time Libraries interrupt macros fail with MISRA Rule 16 5 Req errors Blackfin 36304 Run Time Libraries Edge case INT_MIN INT_MAX returns incorrect result cdefBF561 h pX macro uses result in MISRA Rule 19 4 Blackfin 36451 Run Time Libraries errors VisualDSP 5 0 Update 4 Release Notes Rev 1 2 Page 4 13 Incorrect display of data in HEX8 format in Blackfin Blackfin 35571 Simulator Memory Window Blackfin 36070 Simulator binary 16 bit memory window format only displays 8 bits Project fails to build when user sets heap space to less Blackfin 29902 System Builder than 1k Blackfin 34546 System Builder Incorrect path for basiccrt in exported makefile Hand
12. 7 4 Supported Operating Systems nn nnnnnnnnnnnnnnnrnnnnnnnnnnnnnnnnnnnnnnnnnos 7 4 Windows Vista SP EE 7 4 lee Pri A A Ad amuadans 7 4 New Hardware SUDDO tii in 7 5 New Processors and Processor Revision Support 7 5 Processor Revision Deprecation c ssssceccceccccenssssescecececsaneussescececesseeeueseseececesseeeueusseeseceesesauegssss 7 5 BOOt ROM Code lt a 7 6 Tee EE 7 6 NewEmulator SUP DOPE Zeta en eegen eege eege Ee Se 7 7 A 7 7 New Evalliatioh Board SUP PON ai A e 7 7 PDSPS2 0469 EZ ia 7 7 ADSP 2IS e RR EE ibi 7 8 ADSP BES518F EZ Board REVISION a A AAA A AAA 7 8 ADSP BF526 EZ BOard REVISION ici cease gnedtadastartiuanesanase 7 8 Landscape LCD EZ EXTENDER Examples ccccccsessssccececeeecsessaeeeceeeeseessesneaeseeeesesseesesaeaeeeeeeseneees 7 8 Blackfin SHARC USB EZ Extende r ccccccssssscccccsceessssssscececccecsessnssueceeseccessessssaeeseceeseesentaseeeseseeeees 7 9 SHARC AMIGO EZ EXtende siii adidas 7 9 New System Services and Device Drivers 7 10 File System Service for ADSP BF518F EZ Board 7 10 RamDisk FSS tor ADSP BF53x BF561 EZKIT Litas ii id 7 10 Other Elei EA ei cantare mud ont ad 7 10 Silicon Anomaly Workarounde raa a E E E EOE Ears 7 11 Silicon Anomalies 05000248 05000412 ADSb BEGGI ninos 7 11 Silicon Anomaly 06000020 ADSP 2126xX ccccsccssssscssssecsscecssssecssseecssesesssssecssseeessseeeseseseseeeeeees 7 11 Silicon Anomaly 09000021 15000003 ADSP 2127x ADSb 3Z1dxx 7 12
13. ADSP BF54 24789 revision 0 1 To avoid this issue change the project target to build for revision 0 0 rather than 0 1 Alternatively build C source for ADSP BF54 24789 revision 0 1 with switches workaround avoid quick rts 371 and build assembly source with switches anomaly workaround 05000371 anomaly detect 05000371 TAR 35159 VDK Thread Stack Space Reduced on TigerSHARC An anomaly has been identified in VisualDSP for TigerSHARC where the VDK thread stack pointers are not configured correctly during thread creation TAR 35194 Thread stack space is allocated and the stack pointers are configured so that they point to the end of the stack allocation spaces as the stacks grow from high to low memory The issue is that the stack pointers are placed too close to the end of each stack allocation resulting in up to 8 words of data being corrupted before the start of each thread stack space higher memory The fix correctly configures the stack pointers so that they are further into the thread stack allocation space on creation 8 words further in for the J stack and 4 for the K stack This effectively means that the stacks for each thread will reach their maximum limit slightly sooner than with previous releases VisualDSP 5 0 Update 3 Release Notes Rev 1 3 Page 3 12 TAR 35556 System Services Caps CCLK for DDR reliability Description The ADSP BF54X is the first Blackfin to use double data rate SDRAM DDR The first revisio
14. Analog TalkThru with SRC C 79 EZ Board SPDIFToAnalogTalkThru C 14xxlExampleslADS 14xxlExampleslADS 14xxlExampleslADS 14xxlExampleslADS 14xxlExampleslADS 14xxlExampleslADS 14xxlExampleslADS 14xxlExampleslADS 14xxlExampleslADS 14xxlExampleslADS 14xxlExampleslADS 14xxlExampleslADS 14xxlExampleslADS 14xxlExampleslADS 14xxlExampleslADS 14xxlExampleslADS 14xxlExampleslADS 14xxlExampleslADS 14xxlExampleslADS 14xx Examples ADSE Te ZE SS T TO TO 0 ZE FEI 20 0 ZE Ki EOL TER ZE NONNNNNNNNNNNNNNNNN DN NH E US ds vs ds vs ss vs vs BBB vs BBR BRB BA NNNNNNNNNNNNNNNNNDN DN LDN E Ss ds vs vs vs ss vs vs BBB ss BR BRB BA VisualDSP 5 0 Update 8 Release Notes Rev 2 1 Page 8 7 214xx Examples ADSP 21479 EZ Board Talkthrough_IIR Accelerator 214xx Examples ADSP 21479 EZ Board UART echo back C l4xx Examples ADSP 21479 EZ Board VISA example N E l4xx Examples SHARC Audio EZ Extender 21479 AD1939 C Block Based Talkthru 192kHz l4xx Examples SHARC Audio EZ Extender 21479 AD1939 C Block Based Talkthru 48 or 96 kHz l4xx Examples SHARC Audio EZ Extender 21479 AD1939 C Sampled Based Talkthru 192 kHz l4xx Examples SHARC Audio EZ Extender 21479 AD1939 C Sampled Based Talkthru 48 or 96 kHz l4xx Examples SHARC Audio EZ Extender 21479 AD1939 12S C Sampled Based Talkthru 14xxXExamplesXSHARC Audio EZ Extender 21479 AnalogInDigitalOut l4xx Examples SHARC Audio EZ Extender 21479 SPDIF to Analog TalkThru with
15. BF52x and ADSP BF54x Boot ROM e Fixed EBIU_SDBCTL_VALin ldr init code ezkitbf5xx initcode asm adsp bf561 ez kit litelezkitBF561 initcode h to use EBO_CAW_10 instead of EBO_CAW_9 TAR23499 Misallocation of Local Static Variables Common Local variables declared static const or local uninitialized variables declared static were previously placed in the data1 section by the compiler These will now be placed in constdata and bsz respectively These changes are for all Blackfin SHARC and TigerSHARC parts This might cause some applications to fail to link if the LDF does not map constdata or bsz to memory that can accommodate the increased size of these sections In this situation the memory output section that maps data1 reduced in size can also be used to map constdata and bsz which should allow the link to succeed VisualDSP 5 0 Update 4 Release Notes Rev 1 2 Page 4 9 Limitations This section highlights known significant limitations USB Driver Host ADSP BF52x ADSP BF54x For reliable operation of the USB controller in host mode to access USB flash drives it is necessary to ensure that the release build libraries are used for the System Services Device Drivers and USB libraries This is achieved by ensuring that the Use Debug System libraries option is unchecked in the Project Link Processor page of the Project Options dialog for the appropriate project The shell_browser examples dist
16. Blackfin 38060 Run Time Libraries Remove _SLEW registers from BF52x def cdef headers Accumulator Signbits simulates incorrectly for input of O Blackfin 36343 Simulator 1 Blackfin 37924 Simulator Floating point 32 bit memory display gives incorrect value VIT_MAX appears to give the wrong result in compiled Blackfin 37976 Simulator sim VisualDSP 5 0 Update 5 Release Notes Rev 1 8 Page 5 17 quoted library search directories causes malformed input Blackfin 36872 Source Generator XML a multi core project should always have C support Blackfin 37852 Source Generator enabled Blackfin 32230 System Services Add command to sense GP timer period Blackfin 36352 System Services Kookaburra SPI System Service has a bad select ID IwIP init_stack clears all other flags when setup IGMP Blackfin 37986 TCPIP Stack flag Blackfin 37987 TCPIP Stack IwIP nifce_driver_init should set up more flags Blackfin 37988 TCPIP Stack Iw P header files under include folder should be updated Blackfin 37989 TCPIP Stack BF526 LAN Software Readme file need be updated VDK headers should not include RTL headers in extern Blackfin 36860 VDK C blocks Cannot view the DMA addressing registers for SPIB on SHARC 36427 ADspCommon XML Files the 21364 SHARC 36536 Compiler Call to sysreg_read results in MISRA Rule 19 4 error Compiler uses a POP STS instruction in a RTI DB
17. Blackfin Examples ADSP BF526 EZ KIT Lite drivers usb bulk redirect io app Blackfin Examples ADSP BF526 EZ KIT Lite drivers usb mass_ storage app Blackfin Examples ADSP BF526 EZ KIT Lite drivers usb mass storage host app Blackfin Examples ADSP BF526 EZ KIT Lite services FileSystem NAND Blackfin Examples ADSP BF526 EZ KIT Lite services FileSystem VDK Landscape LCD EZ EXTENDER Examples VisualDSP 5 0 Update 6 includes a Landscape LCD EZ Extender example for the ADSP BF526 EZ Board evaluation system This example demonstrates the use of the LCD Driver Capacitive Touch Controller Driver and Touch Screen Controller Driver Blackfin Examples Landscape LCD EZ EXT END ER SketchPad VisualDSP 5 0 Update 6 Release Notes Rev 1 3 Page 6 6 New System Services and Device Drivers The following are now supported by VisualDSP 5 0 USB Audio Class Driver The USB Audio Class Driver is new with Update 6 Examples are provided for the ADSP BF526 ADSP BF527 and ADSP BF548 evaluation systems Blackfin Examples ADSP BF526 EZ KIT Lite Drivers usb usb audio app Blackfin Examples ADSP BF527 EZ KIT Lite Drivers usb usb audio app Blackfin Examples ADSP BF548 EZ KIT Lite Drivers usb usb audio app LCD Driver The LCD Driver to support the LCD on the Landscape LCD Extender has been added for Update 6 The new Sketchpad example for the ADSP BF526 EZ Board demonstrates how to use this new driver
18. Capacitive Touch Controller Driver The Capacitive Touch Controller Driver to support the AD7147 on the Landscape LCD Extender has been added for Update 6 The new Sketchpad example for the ADSP BF526 EZ Board demonstrates how to use this new driver Touch Screen Controller Driver The Touch Screen Controller Driver to support the AD7879 on the Landscape LCD Extender has been added for Update 6 The new Sketchpad example for the ADSP BF526 EZ Board demonstrates how to use this new driver ADSP BF51x System Services System Services and Device Driver support for the ADSP BF51x processor series and ADSP BF518F EZ Board has been added for Update 6 PWM System Service The PWM peripheral is new with Update 6 It is supported for the ADSP BF51x processor series An example for the ADSP BF518 EZ Board has been provided Blackfin Examples ADSP BF518F EZ Board Services PWM pwm sine wave New Examples This section specifies new examples that are not specific to evaluation boards No new examples for this section are provided with Update 6 VisualDSP 5 0 Update 6 Release Notes Rev 1 3 Page 6 7 Boot ROM Code This section describes changes to the Boot ROM code New Boot ROM Code is available in Update 6 for the following processors e ADSP BF51x rev 0 0 e ADSP BF522 524 526 rev 0 1 e ADSP BF54xM rev 0 3 Init Code This section describes the changes to the Init Code PLL Voltage Regulator Changing the PLL and the Voltage
19. EZ Extender LCD ColorBarDisplay ADSP BF527 Blackfin Examples Landscape LCD EZ Extender SketchPad ADSP BF518 VisualDSP 5 0 Update 7 Release Notes Rev 1 0 Page 7 8 Blackfin SHARC USB EZ Extender Update 7 introduces additional support for the Blackfin SHARC USB EZ Extender for the ADSP 21469 EZ Board The following examples are provided 214xx Examples USB EZ ExtenderYUSB_I0O 214xx Examples USB EZ Extender USB Loopback 214xx Examples USB EZ Extender USB Talkthrough Blackfin Examples USB EZ EXTENDER bulk loopback app Blackfin Examples USB EZ EXTENDER bulk_redirect_io_app Blackfin Examples USB EZ EXTENDER mass storage app SHARC Audio EZ Extender VisualDSP 5 0 Update 7 introduces support for the new SHARC Audio EZ Extender The following examples are provided 14xx Examp 14xx Examp 14xx Examp L4xx Examp L4xx Examp L4xx Examp 4xxXExampl 2 4 MNORPNNNNNN DY les S les S les S les S les S les S les S kHz 6serialpo 14xx Examp les S HARC HARC HARC HARC HARC HARC HARC rts HARC Audio Audio Audio Audio Audio Audio Audio Audio EZ E EZ E EZ E EZ E EZ E EZ E VUUUUUOU UV ER 21469 ER 21469 ER 21469 ER 21469 ER 21469 ER AnalogInDigitalout ER Sharc ER SPDIF VisualDSP 5 0 Updat
20. New System Registers Header Eles 6 12 Processor Header Files ci a ida A ssh a coe 6 12 A DEER 6 13 LOFand Mapping Cheese dass 6 13 VisualDSP 5 0 Update 6 Release Notes Rev 1 3 Page 6 1 Enhanced Disassembly Window Display of Pipeline Stages cccccccsesssssceceeeeesessssseseeeeeeseeeees 6 14 Project CONSUME A ais 6 14 Migrating Projects from the ADSP 2146x Beta 1 Update 6 15 Accelerator o A a O O On 6 15 Peripheral SiMUlA ION ido id AA AAA A A D eg 6 15 TAR 40528 SEGMENT assembler directive may behave incorrectly o ooccccccnncononoonnnnnnnnnnnnnos 6 15 USB Stack Enhancements ans A ERA E O aE ai 6 16 RODIN NR titi 6 16 Better Device Detection cidcid idea 6 17 EXE a ai 6 17 e a Si A Ob dd ia 6 17 EE 6 20 ADSP BFS1X any none 0 0 Een EE 6 20 ActiveCPLB BaCk a A a 6 20 Compiler Changes for MISRA Exemplar Suite Blackttn 6 20 New compiler error cc2238 for pragma interrupt FUNCTIONS cccooooncccononnnnnononnnnnnnnnnnnnccnnnnnnnos 6 21 New DCPLB_DATAx and ICPLB_DATAx bit position macros Blackfin 00s nnnnnsnnssonenssnsennanne1a 6 21 New VSTAT Macro in defBF52x_base h ADSP BF51x BF52X ooooococccocccooonoonoconononcnonn nono nocononnnnos 6 22 Deprecated IWR Macro ADSP BF51x BF52X oooocoocccconncconnnocononononnnononononnonononononononononnnonnnnnonnnnos 6 22 New Messages Due to the SIMD SHARC Assembler Enforcing Loop Restrictions cooommm o 6 22 TAR 39444 RFRAME Instruction Only
21. Other significant changes have been made to many of the VisualDSP header files to further improve VisualDSP MISRA compliance VisualDSP 5 0 Update 6 Release Notes Rev 1 3 Page 6 20 New compiler error cc2238 for pragma interrupt functions A new error cc2238 has been added to the C C compilers The error is issued if an interrupt handler function is defined to take parameters An interrupt handler function is a function defined using any of the following compiler pragmas e pragma interrupt used in the definition of Blackfin sys exception h macros EX_INTERRUPT_HANDLER EX_EXCEPTION_HANDLER and EX_NMI_HANDLER e pragma interrupt complete cc21k only e pragma interrupt complete nesting cc21k only e pragma interrupt reentrant ccts only Functions that are defined as interrupt handler functions cannot be passed parameters because they are not explicitly called and are only run in response to an interrupt event Functions that cause this error to be issues should be modified to remove parameters New DCPLB_DATAx and ICPLB_DATAx bit position macros Blackfin The defblackfin h and def LPBl1ackfin h include files have had new bit positions macros added for the DCPLB_DATAx and ICPLB_DATAx registers The new macros added to defblackfin h for use by the ADSP BF535 part are define CPLB USER WR_P 3 O no write access O write access allowed user mode define CPLB SUPV_WR_P 4 0 no write access O write ac
22. PWR CMD END 0 y Pass the command pair table to adi_pwr_Init as shown below Result adi pwr Init PowerInitTable The Power Management Service will then use the CCLK vs VLEV relationship defined by the array pwr_cclk_vlev_table instead of the columns of the array defined in the source file adi_pwr c VisualDSP 5 0 Update 3 Release Notes Rev 1 3 Page 3 14 Silicon Anomaly Workarounds Silicon Anomaly 09000011 ADSP 2137x Indirect Branches from External to Internal Memory may corrupt the Instruction Cache Workarounds for this anomaly have been implemented in the assembler the default behavior is to apply a workaround The compiler relies upon the default behavior of the assembler to apply the workarounds The runtime libraries and VDK have been rebuilt to avoid the anomaly or apply the workarounds except for code that must be mapped to internal memory One of the workarounds used by the assembler generates new code in section seg_int_code that must be mapped to internal memory The default Linker Description File LDF provided in VisualDSP does this already projects with customized LDFs may require modification to map this section The assembler will provide informational messages for each instance of an applied workaround to notify the user about code generated to seg_int_code When some condition prevents the assembler from applying the workaround the assembler will produce a descriptive er
23. Project Options 1 On the Project property page change the Target Type to Loader file 2 Onthe Load Splitter property page select Enable ROM Splitter set the Format to Hex and set the Mask address to 21 Memory Sections for Internal Memory and FLASH Unlike other Blackfin processors the ADSP BF50x processor series does not have support for External memory The ADSP BF504F and ADSP BF506F processors do have stacked parallel FLASH memory available and support for this is integrated into the VisualDSP tools in Update 8 The default and generated LDFs will map code and constant data inputs that cannot be fit into L1 memory to FLASH memory where possible by default They avoid placing functions that require automatic breakpoints since software breakpoints do not work in FLASH memory The default LDFs also provide support for input sections that can be used to map code and data explicitly pragma section L1 code Place code in L1 internal SRAM pragma section L1 data Place data especially r w data in Ll internal SRAM pragma section FLASH code Place code in L3 that is large and or does not need debugging pragma section FLASH data Place r o data in L3 Loading a Program into Internal Memory and FLASH Loading to Internal Memory and FLASH now takes place automatically The FLASH Programmer is loaded into Internal Memory and used to program the FLASH Then program and data are loaded into Intern
24. SRC C NONNMNNNN NY KB DDB vs BR p D D D D D The following new projects have also been added 214xx Examples USB EZ EXTENDER USB 10121479 usbio dpj 214xx Examples USB EZ EXTENDER USB Loopback 21479 usbloopback dpj 214xx Examples USB EZ EXTENDER USB Talkthrough 21479 usbtalkthrough dpj ADSP 21489 EZ Board This release integrates support from the VisualDSP 5 0 ADSP 21479 and ADSP 21489 EZ Boards release The following examples are provided 214xx Examples ADSP 21489 EZ Board 21489 AD1939 C Block Based Talkthru 192kHz 214xx Examples ADSP 21489 EZ Board 21489 AD1939 C Block Based Talkthru 48 or 96 kHz 214xx Examples ADSP 21489 EZ Board 21489 AD1939 C Sampled Based Talkthru 192 kHz 214xx Examples ADSP 21489 EZ Board 21489 AD1939 C Sampled Based Talkthru 48 or 96 kHz 214xx Examples ADSP 21489 EZ Board 21489 AD1939 I2S C Sampled Based Talkthru 214xx Examples ADSP 21489 EZ Board 256pointFFT 214xx Examples ADSP 21489 EZ Board 512pointFFT 214xx Examples ADSP 21489 EZ Board AnalogInDigitalOut 214xx Examples ADSP 21489 EZ Board Background Telemetry 214xx Examples ADSP 21489 EZ Board Core Timer C 214xx Examples ADSP 21489 EZ Board Decimation Filter 214xx Examples ADSP 21489 EZ Board Flash Programmer 214xx Examples ADSP 21489 EZ Board Interpolation Filter 214xx Examples ADSP 21489 EZ Board Multichannel Filter Autolterate 2
25. Silicon Anomaly 09000022 15000004 ADSP 2137x ADSP 214XxX occooccoccconoccoonoconnnonnnonncconnncnos 7 13 Silicon Anomaly 09000023 15000005 ADSP 2137x ADSP 214XxX ocooocooocconocooonoconnnonnnonnnconnncnns 7 13 Silicon Anomaly 15000011 ADSP 2 E EE 7 14 USB Hatdware Issues Update Tier iia A A dd da ida 7 15 Silicon Anomaly 05000450 ADSP BESAX aa E eEEe 7 15 Silicon Anomaly 05000456 ADSP BF52x ADSP BEGAN anos 7 15 VisualDSP 5 0 Update 7 Release Notes Rev 1 0 Page 7 1 Silicon Anomaly 05000460 ADSP BF52x ADSb BEGAN nooo nconncnncnnncnnnnnnno 7 16 Silicon A omaly 05000463 ADSP BFS AX aii as 7 16 Silicon Anomaly 05000464 ADSP BEGAN nn nnonnnnnnnss 7 16 Silicon PERRIN Ena aa 7 16 Silicon Anomaly 05000466 ADSP BF52x ADSP BEGAN 7 17 Silicon Anomaly 05000467 ADSP BF52x ADSP BEGAN 7 17 ADSP 214xx CHAN BOS sii iii doit 7 18 ADSP 2T4xx Interrupt VeEctors 2duert t eded dee NEEN dee NEEN iaa iii 7 18 TAR40528 Changes to legacy SEGMENT directive for SHARC parts with VISA support 7 18 ASDP 2146Xx Def a aa ari 7 18 ADSP 2146x SHARC Processor Hardware Retierence 7 18 CHIR Cal IMCS CHANCES 22 dd tica 7 19 Online Help for Silicon Anomaly Tools Support 7 19 Blackfin Nit ee 7 19 Peripheral Sim latio nea it A EE ETAGE 7 19 New pragma section compiler Warnings ccccesssscceceeecessesseaecececeeeseeseseeeeeeeesceeseaeaeeeeeeseesees 7 19 New compiler pragma Hpragma save restore A0 bit 7 20
26. The following table is a list of the problems addressed in the VisualDSP 5 0 release Details can be found on the Tools Anomaly Web page The URL is http www analog com processors tools anomalies Processor All All All All Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Problem Number 24089 24929 25649 26325 30604 26076 28145 28483 28898 29099 30547 30554 30886 Tool Compiler Compiler Compiler Compiler Compiler Compiler Compiler Compiler Compiler Compiler Compiler Compiler Compiler Compiler Compiler IDDE IDDE IDDE LDF Linker Linker Run Time Libraries Run Time Libraries Utilities VDK ADspCommon XML Files ADspCommon XML Files Compiler Compiler Compiler Compiler Compiler Compiler Compiler Compiler VisualDSP 5 0 Release Notes Description Generates bad code for old style C args with double size 64 pragma pack doesn t work as expected with bitfields Compiler crashes if a 64 bit float variable is used in an asm Speed size ratio inlining warning gives wrong source line Alternate pre processing sequences cause error with pedantic Multiple PGO files confuses IPA MQ switch crashes driver The optimize pragmas do not override Og Compiler switch s does not work Assertion macdefs c 2475 with extremely long variable names Pre compiled headers doesn t work with IPA and VDK pragma alignment_region modified by prior extern
27. This only applies when compiling for Hammerhead parts 211xx 212xx 213xx and 214xx When compiling for non Hammerhead parts the pragma is silently ignored The pragma will only take effect when it is used in conjunction with one of the SHARC Hammerhead interrupt pragmas e g interrupt_complete The compiler is not able to determine if the handler the pragma is applied to a handler for the IRQ VIRPTL or TIMER interrupts It will be up to the user to determine whether or not the pragma should be used Syscontrol variation for ADSP BF54xM rev 0 3 For the ADSP BF54xM rev 0 3 the syscontrol function in ROM increments the VLEV parameter before setting the VR_CTL register TAR 36697 MISRA Rule 19 4 Change MISRA Rule 19 4 Change Checks on define directive and not macro expansion use MISRA Rule 19 4 states that C macros shall only expand to a braced initializer a constant a string literal a parenthesized expression a type qualifier a storage class specifier or a do while zero construct Prior to VisualDSP 5 0 Update 5 the compiler would check this rule in macros that were used To improve the MISRA compliance support the checks are now done when a macro is defined One effect of this is that macros that are defined but unused may now cause rule 19 4 errors when they did not using the tools prior to Update 5 Another impact is that macros that are valid when expanded on use may not be valid and cause Rule 19 4 errors when defin
28. bases libsim for TS101 rev 0 4 is incomplete Details can be found on the Tools Anomaly Web page The URL is http www analog com processors tools anomalies Processor Family All All All Problem Number 30713 32429 33665 Tool Compiler Compiler Compiler VisualDSP 5 0 Release Notes Description Compiler is not using BSS Internal error diag_message missing string substitution internal compiler error driver c 1488 building VLA source Page 14 Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin 28272 32303 32092 31923 32237 32004 28572 29394 29851 29870 29874 30247 32466 32299 32749 33643 33721 33403 33405 30369 32752 24859 26184 27061 29791 31608 30087 33691 27445 27685 28755 29687 29727 31238 31720 32578 32665 32312 32957 33049 33680 31173 33057 28515 31695 29902 32747 33652 33722 29565 29065 29221 Run Time Libraries Run Time Libraries IDDE Compiler Compiler Assembler Compiler Compiler Compiler Compiler Compiler Compiler Compiler Com
29. called with Inf arg Multicore runtime libraries always link in I O library Page 15 Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin SHARC SHARC SHARC SHARC SHARC SHARC SHARC SHARC TigerSHARC TigerSHARC TigerSHARC TigerSHARC TigerSHARC TigerSHARC TigerSHARC 32179 32319 32867 33654 33733 33744 28581 31568 32230 33464 33518 33677 29313 29736 30157 32362 33007 33627 32949 32920 29561 32810 33574 32706 32881 33670 33671 28363 32961 33655 30749 28195 29110 32626 Run Time Libraries Run Time Libraries Run Time Libraries Run Time Libraries Run Time Libraries Run Time Libraries System Services System Services System Services System Services System Services System Services TCPIP Stack TCPIP Stack TCPIP Stack TCPIP Stack TCPIP Stack TCPIP Stack USB Stack Compiler Emulator Emulator IDDE Run Time Libraries Run Time Libraries Run Time Libraries Run Time Libraries Compiler Compiler Compiler Emulator Run Time Libraries Run Time Libraries Run Time Libraries VisualDSP 5 0 Release Notes VDK and RTL link in different libs for si revision none workaround crtn doj can be removed from LDF File without warning Make the header files MISRA compliant DSP library function conv2d3x3_fr16 bas
30. device driver libraries Anomaly workaround information is still available in the online help Select Help gt Contents gt Graphical Environment gt Silicon Anomaly Support gt Silicon Anomalies Tools Support and then select the appropriate processor family Silicon Anomaly 09000014 ADSP 2137x Incorrect Execution of Conditional External data accesses in a delayed branch DB slot The SHARC C C compiler assembler VDK and runtime libraries have been enhanced to include workarounds for anomaly 09000014 The anomaly occurs when a conditional external data access instruction is in the delayed slots of a branch instruction such as JUMP CALL RTS RTI The result is that the access can be incorrectly executed because the evaluation of the condition maybe wrong This applies to both internal as well as external memory execution The compiler workaround for this anomaly avoids having conditional data accesses in delayed branch slots To enable this compiler workaround manually the workaround 09000014 switch can be used When the workaround is enabled the macro WORKAROUND_09000014 is defined at compile assemble and link stages The SHARC assembler has been modified to issue a warning ea2521 for code that may hit the anomaly and require a workaround to be inserted An example of this new warning is Warning ea2521 wa_09000014 s 13 Potential Hardware Anomaly 09000014 due to conditional memory access by one of the two instructio
31. does not return error when attempt to write when Blackfin 42030 File System Service media full SDH PID default configuration table incorrect for ADSP Blackfin 42042 File System Service BF51x missing pop critical in case of error with Blackfin 42062 LwIP Stack for Blackfin sys_mbox_trypost Generic System Services Library for Blackfin 42059 Blackfin Incompatible with uC OS II version 2 86 USB driver should support Windows 64 bit operating Blackfin 38098 USB Software and Stack systems PC crashes if cable is unplugged plugged during a E a Software and Stack se Blackfin 50004 USB USB Software and Stack and Stack bf518 Mass bf518 Mass_Storage_app readme errors app readme errors USB Mass Storage Example fails to export RAM disk on EIN ETA aa Software and Stack successive e as ATA plug events sHaRe 50040 USB USB Software and Stack and Stack SHARC USB EZ SHARC USB EZ Extender driver won t load in 64 bit OS _ driver won t load in 64 bit OS VisualDSP 5 0 Update 8 Release Notes Rev 2 1 Page 8 25 VisualDSP 5 0 Update 7 Release Notes Revision 1 0 November 4 2009 Table of Contents Nomenclatura da A A AN a irai 7 3 Release Notes ia A A A As dad 7 3 NAS Lal ON a ia A EA A A 7 3 Identifying Your VisualDSP Version ocoooocccccncncnononononncnnnnnncnnnnnononnnnnnnnnnnnnnnn nn nnnnnnnnnnnannnnrnnnnnnnnnnnnnns 7 3 Installing the A a iia 7 3 Gloning VisualDSP FE it ege ES 7 3 dl ge EE 7 4 TAR Tools Aroma Reporta in
32. e ADSP 21471 ADSP 21472 ADSP 21475 e ADSP 21481 ADSP 21482 ADSP 21485 No new TigerSHARC processors are supported with this release VisualDSP 5 0 Update 8 Release Notes Rev 2 1 Page 8 5 New Silicon Revisions The following new silicon revisions are supported with Update 8 e ADSP BF512 4 6 8 silicon revision 0 2 e ADSP BF542 4 7 8 9 silicon revision 0 4 e ADSP 21462 5 7 9 silicon revision 0 1 No new silicon revisions to TigerSHARC processors are supported with Update 8 VisualDSP 5 0 Update 8 Release Notes Rev 2 1 Page 8 6 New Evaluation Board Support Support has been added for the following new evaluation boards and evaluation board revisions ADSP BF506F EZ KIT Lite This release integrates support from the VisualDSP 5 0 ADSP BF506F EZ KIT release The following examples are provided Blackfin Examples ADSP BF506F EZ KIT Lite Background_Telemetry CDemo Blackfin Examples ADSP BF506F EZ KIT Lite Drivers ADC Sample ADC ACM Control Blackfin Examples ADSP BF506F EZ KIT Lite Drivers UART Autobaud Blackfin Examples ADSP BF506F EZ KIT Lite Drivers UART Echo Blackfin Examples ADSP BF506F EZ KIT Lite Flash Programmer BF50x4MBFlash Blackfin Examples ADSP BF506F EZ KIT Lite Flash Programmer Serial Blackfin Examples ADSP BF506F EZ KIT Lite Power On Self Test ADSP BF526 EZ Board Rev 1 2 This release introduces support for the revision 1 2 of the ADSP BF527 EZ Board This revision includ
33. example to prepare and format the NAND flash device NFD on the ADSP BF527 EZ KIT Lite and ADSP BF548 EZ KIT Lite The NFD is formatted as a single FAT 16 partition They can be found in the following directories Blackfin Examples ADSP BF527 Blackfin Examples ADSP BF548 EZ KIT EZ KIT telServicesYFil telServicesYFil System NAND NandFormat System NAND NandFormat LwIP TCP IP Example LwIP TCP IP stack has been upgraded to 1 3 0 which includes multicasting support Multicasting is a mechanism to send messages to group of destination addresses among networked machines An example Multicast_Sender is included in the ADSP BF526 EZ KIT Lite LAN examples to demonstrate how to make multicast connection It can be found in the following directory Blackfin Examples ADSP BF526 EZ KIT Lite LAN Multicast Sender VisualDSP 5 0 Update 4 Release Notes Rev 1 2 Page 4 7 Critical Fixes Changes This section highlights significant changes due to software anomaly fixes or functional changes Upgrade to LwiP 1 3 The LwIP Ethernet stack has been upgraded from revision 1 2 to 1 3 Please refer to LwIP homepage for more information http savannah nongnu org projects Iwip and the associated Wiki http lwip scribblewiki com LwIP_Main Page As LwIP 1 3 supports multicast multicast has been added to the Ethernet drivers Boot ROM API Additions ADSP BF51x ADSP BF52x ADSP BF54x In certain Blac
34. examples can be found at Blackfin ldr init_code asm The assembly are the legacy versions Blackfin ldr init_code c New C versions VisualDSP 5 0 Update 3 Release Notes Rev 1 3 Page 3 8 These examples are developed and tested for respective EZ KIT Lite boards Customized hardware makes need for modifications likely For dynamic power management the initcode examples make use of the bfrom_SysControl function which is part of the ROM API featured by new processors Changes to Support MISRA Technical Corrigendum 1 The document for Technical Corrigendum 1 TC1 was produced in July 2007 to clarify and address issues with MISRA C 2004 The TC1 document describes changes to the original MISRA C 2004 document The TC1 document can be downloaded from the MISRA site http misra org uk The site requires you to register in order to download the document Most changes are simple clarifications although some changes affect the rule violations What follows is a brief description of the rules where the rule violations reported will significantly change Rule 4 1 The normative text now states that All hexadecimal escape sequences are prohibited Rule 10 3 Headline rule changed to The value of a complex expression of integer type shall only be cast to a type of the same signedness that is no wider than the underlying type of the expression This has the effect that casting the type of a complex expression to the same type as the complex e
35. files This macro was incorrectly defined and should not be used TAR 35481 Fixed Signed CHAR definition The definition of integer type s8 in services h has been fixed This could cause backwards compatibility issues if the user relied on it being unsigned The following definition typedef char s8 has been modified to the following typedef signed char s8 TAR 33557 Blackfin 64 bit double modf Result Changed The implementation of the Blackfin 64 bit double precision modf standard C function has been modified to return 0 0 rather than a NaN Not A Number when the second operand to modf is 0 0 The result in this situation is implementation defined according to the ANSI C standard The documentation for the function has always stated that it should return 0 0 for this input VisualDSP 5 0 Update 3 Release Notes Rev 1 3 Page 3 11 Limitations This section highlights known significant limitations VisualDSP 5 0 ADSP BF54x Known Limitations The following device drivers will be supported in a future update e NAND FLASH driver VisualDSP 5 0 ADSP BF52x Known Limitations The following device drivers will be supported in a future update e NAND FLASH driver Workarounds for Silicon Anomaly 05 00 00371 ADSP BF54 24789 Rev 0 1 The compiler and assembler workarounds for anomaly 05 00 0371 Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration are not automatically enabled when building for
36. following SHARC processor series e ADSP 2106x e ADSP 2116x e ADSP 2126x e ADSP 2136x e ADSP 2137x e ADSP 2146x The simulator now provides support for Memory to Memory DMA for the following SHARC processor series e ADSP 2136x e ADSP 2137x e ADSP 2146x New pragma section compiler warnings Compiler changes were made in Update 7 to fix issues with pragma section used to control placement of data and code in C and C code Some uses of pragma section that were accepted prior to Update 7 may cause the compiler to issue warnings now VisualDSP 5 0 Update 7 Release Notes Rev 1 0 Page 7 19 For example pragma section data 1 1 struct s pragma section data 2 2 int a 32 pragma section data 3 3 int b 32 ant 24d E y pragma section data 4 4 struct s s inst The only valid use of the pragma in this example is 4 used before the struct instance to tell the compiler to place that instance into section data_4 The others uses are accepted by compilers prior to Update 7 but cause build warnings when using the Update 7 one The warnings are ccblkfn exe S t c ctt t c line 4 cc2263 D warning pragma section before field a has no effect int a 32 t c line 6 cc2263 D warning pragma section before field b has no effect int b 32 t c line 1 cc0609 D warning this kind of pragma may not be used here pragma section data 1 1
37. for popping regions VDK does not handle all the exceptions that the cplb_hdr does Enabling self nested interrupts breaks VDK REVPID register displays PROCID and SIREV swapped Annotation information is incorrect for registers clobbered by an asm pedantic should put out warnings C C runtime not honored on SHARC Compiler not working around 2136x anomaly 07 00 0009 Asm statements using circ buf regs don t work 21262 AsmDemo CDemo BTC example README files need correction Additional options lost converting 3 0 dpj to 4 0 Zooming in the plot window may cause the IDDE to crash LDF can allow 1 too many words to be assigned to heap No output sections issued when empty with run spaces delete operator doesn t work with heap_install Multi threaded realloc will not allocate correct amount of mem heap_malloc with nonexistant heap causes invalid data accesses Bit macro FAR changed to FARF for SDCTL register in def header Mem21k update generates 1 exit code but seems to work anyway ADSP 21375 Primes example does not work in simulator Hang executing from ext mem consecutive reads from ext mem workaround all does not turn on all workarounds Assembler accepts invalid register move Symbols sizes for INC BINARY wrong Invalid warning on 2nd section directive Confusing annotations for compiler generated fp divide code Porting a VisualDSP 4 5 project causes different libraries to be linked in strtol and strtoul error for garbage
38. installation of VisualDSP 17 Go to Start gt Programs gt Analog Devices gt VisualDSP 5 0 or equivalent gt Maintain this Installation 18 Select Clone this Installation and click Next 19 Optionally click Advanced to set the Start menu path 20 Enter the Clone install path and click Next Definitions This section provides definitions for terminology relating to VisualDSP and this document TAR Tools Anomaly Reference Number Tools Anomaly Reference Number or TAR is used for tracking confirmed defect reports in VisualDSP VisualDSP 5 0 Update 4 Release Notes Rev 1 2 Page 4 3 New Hardware Support VisualDSP updates often include support for new processors new silicon revisions for existing processors and new EZ KIT Lite evaluation systems In order to support these minor revisions are made to the tool chain and additional system services and device drivers need to be added This section describes the new support available in this update New Processors and Processor Revision Support The New Product Release Bulletin contains the list of new processors available with VisualDSP 5 0 Refer to the processor s data sheet and hardware reference manuals for information on system configuration peripherals registers and operating modes Update 4 introduces the ADSP BF51x Blackfin processor family The following new processors are supported e ADSP BF512 silicon revision 0 0 e ADSP BF514 silicon revisio
39. memory For more information see tools anomaly 39641 Warning The assembler detection warning ea5517 for anomaly 05000428 will be triggered by code that contains the prescribed workaround for anomaly 05000283 System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage This case of this warning can be safely ignored and the warning may be suppressed using the MESSAGE directive as the code will not cause the 05000428 anomaly VisualDSP 5 0 Update 5 Release Notes Rev 1 8 Page 5 16 Anomaly Charts Tools Anomalies Addressed The following table is a list of tools anomalies addressed in VisualDSP 5 0 Update 5 for which details can be found on the public tools anomaly website Other tools anomalies have also been fixed in the Update Details can be found on the Tools Anomaly Web page The URL is http www analog com processors tools anomalies Tools Processor Anomaly Family Report Tool Description Compiler saves restores reserved registers if they are All 36599 Compiler used in asm MISRA Rule 16 7 incorrectly reported for pointer to All 36678 Compiler function All 36697 Compiler MISRA Rule 19 4 Check define directive not expansion MISRA Rule 10 1 a violation incorrectly reported for All 36910 Compiler operation All 36535 Run Time Libraries Call to sysreg_read results in MISRA Rule 19 7 warning All 3800
40. need to be added This section describes the new support available in this update New Processors and Revisions Support The Product Bulletin contains the list of new processors available with VisualDSP 5 0 Refer to the processor s data sheet and hardware reference manuals for information on system configuration peripherals registers and operating modes Update 3 provides support for the following silicon revisions to existing Blackfin processors e ADSP BF523 silicon revision 0 2 e ADSP BF525 silicon revision 0 2 e ADSP BF527 silicon revision 0 2 e ADSP BF531 silicon revision 0 6 e ADSP BF532 silicon revision 0 6 e ADSP BF533 silicon revision 0 6 e ADSP BF538 silicon revision 0 5 e ADSP BF539 silicon revision 0 5 There are no new silicon revisions to existing SHARC or TigerSHARC processors with Update 3 New System Services and Device Drivers The following are now supported by VisualDSP 5 0 e Support for on chip peripherals for the ADSP BF522 BF524 and BF526 processors VisualDSP 5 0 Update 3 Release Notes Rev 1 3 Page 3 5 New Examples ADSP BF527 EZ KIT Lite Audio Loopback Examples VisualDSP 5 0 Update 3 includes a new audio loopback example to demonstrate use of the audio codec supplied on the ADSP BF527 EZ KIT Lite evaluation system It can be found in the following directory Blackfin Examples ADSP BF527 EZ KIT Lite drivers AudioCodec Audio_ Loopback ADSP BF527 and ADSP BF548 EZ KIT Lit
41. not install this update This update is not intended to be installed on alpha or beta releases For example do not install this update on the ADSP 2146x Beta 1 Update Identifying Your VisualDSP Version The VisualDSP release and update number can be found in 2 locations 5 Inthe Control Panel open the Add Remove Programs applet 6 In the VisualDSP Integrated Development and Debug Environment IDDE select Help gt About VisualDSP Installing the Update Follow the instructions below for installing this update Please note that since VisualDSP supports having multiple instances installed on a single system See the Cloning VisualDSP section below for more information 17 Use the Start Menu to navigate to VisualDSP Maintain this installation By default this is at Start Menu gt All Programs gt Analog Devices gt VisualDSP 5 0 18 Select Go to the Analog Devices website and click Next This will open a window in your web browser 19 Select the appropriate Processor Software Tools Upgrades to match your processor 20 Select and download the desired update VisualDSP 5 0_Update6 vdu to your hard drive 21 Again use the Start Menu to navigate to VisualDSP Maintain this installation 22 Select Apply a downloaded Update and click Next 23 Browse for the downloaded Update file VisualDSP 5 0_Update6 vdu and click Next 24 Follow the on screen prompts to complete installation of this Update
42. revision none Blackfin 39844 Run Time Libraries fails PLL_STAT macro VSTAT wrong in defBF561 h and Blackfin 40186 Run Time Libraries defBF532 h Force Regen Project Link Processor Use C exceptions Blackfin 39516 Source Generator libraries Custom clock settings in Project Option is not proper for Blackfin 39712 Source Generator BF561 Blackfin 39701 System Services FSS locks when random seeking is performed in a file Files created on removable media cannot be deleted in Blackfin 39896 System Services Windows Blackfin 40245 System Services directory name truncated during creation Blackfin 40593 defect in adi_ebiu_SelfRefreshEnable a ee E Blackfin 39625 USB Stack 400MHz SHARC 38048 Memory overlap when PM segment is too big SHARC 38082 Run Time Libraries scanf strtold may not convert long double hexadecimal fp data SHARC 39482 Run Time Libraries BR glitch anomalies in assembler library sources SHARC 40045 Run Time Libraries matsaddf matsmltf and matssubf may return a wrong result cfftN ifftN rfftN in LIBDSP not safe against anomaly SHARC 40164 Run Time Libraries 07000010 SHARC 40290 Run Time Libraries lib_prog_term causes simulator warning SHARC 39857 Does not zero unspecified upper bits of XML register resets TigerSharc 39450 Run Time Libraries heap_switch reports error switching to last run time heap TigerSharc 39610 Run Time Libraries heap_realloc doesn t work for f
43. silicon anomaly 05000428 is enabled for silicon revision any Compiler e The compiler ensures that the targets of predicted jumps are safe against the anomaly Run Time Libraries e The source code for memcpy has been modified to work around this anomaly e The source code for zero_crossd has been modified to work around this anomaly VDK e The code for the API PostMessage has been modified to work around this anomaly Silicon Anomaly 09000020 ADSP 2137x Wrong instruction address may be cached when PMDA instruction executing from external memory is interrupted The compiler will ensure a FLUSH CACHE instruction is inserted at the start of interrupt service routines functions marked pragma interrupt_complete and pragma interrupt_complete_nesting those marked simply pragma interrupt contain the workaround in the appropriate interrupt dispatcher This workaround is automatically enabled when building for parts and revisions impacted by the 09000020 anomaly or when workaround 09000020 is passed to the compiler The macro __WORKAROUND_09000020 is defined when the workaround is enabled VisualDSP 5 0 Update 6 Release Notes Rev 1 3 Page 6 25 All runtime library interrupt dispatchers have been modified to workaround this anomaly using the FLUSH CACHE instruction In VDK all interrupt vector table entries now have FLUSH CACHE as their first instruction to workaround the anomaly Silicon Anomaly 09000023 ADSP 213
44. statements pragma always_inline in system headers can cause a warning Compiler doesn t recognize 1 0 as fract literal Circular buffer loops containing fn pointers don t zero Lregs Unnecessary silicon revision warning Default for new projects should be std enabled getTargetFileNameList returns bad filenames Inputs sections for tables require FORCE_CONTIGUITY Pragma align can lead to wasteful memory allocation No way to map anything after PLIT Cycle counting macros fail to compile in conditional statements printf ignores the h length modifier with 0 x and X elfdump doesn t flag error when archive object doesn t exist RunLastTime in VDK Status is displaying the wrong figure DMA register names have an extra number in the name BF561 has RTC window register defs These should be taken out WDOG_DISABLE not defined in defBF53 2 4 8 h and defBF561 h label displayed at wrong address pragma no_alias is too strict includes in UNC shares not found Debug info associated with wrong line of C source code BF shift with clipped shift distance builtins literal inconsistencies Local variables totalling gt 64KB can result in internal error Using n asm constraint results in compiler error Page 12 Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Black
45. the PLL registers have been set up to produce a system clock frequency in the range of 83 MHz to 133 MHz Ifthe stack is located in DDR then DDR will be accessed as soon as the application starts running so the PLL must be set up prior to loading and executing the application The EZ KIT Lite is delivered with an application in flash which sets SCLK to 133MHz If flash is erased and a new application is programmed into flash and the new application uses DDR for stack then prior to loading and executing the new application the boot kernel should set system clock frequency SCLK to a valid frequency using Pre boot or Init Code If SCLK is out of the valid range while DDR stack activity is taking place the power management function adi_pwr_SetFreq will fail This function takes DDR into self refresh mode to protect external memory while the system clock is adjusted This is problematic with SCLK at 50 MHz and stack heap located in DDR The function will hang under those conditions If stack heap is not located in DDR and no other DDR access is taking place then the adi_pwr_SetFreq function will succeed in changing the clock frequencies so that subsequently DDR can be used without problems VisualDSP 5 0 Update 2 Release Notes Rev 1 1 Page 2 8 Problem Charts Problems Addressed The following table is a list of problems addressed in VisualDSP 5 0 Update 2 for which details can be found on the public to
46. to send an additional data packet back to the Blackfin processor where it is received in the USB FIFO but no USB RX interrupt is generated Taking the Mass Storage Class as a specific example this causes the devices to send a status packet which should generate a USB RX interrupt This interrupt may be lost Device Mode For DMA Mode 1 device mode receive operations where the transfer size is unknown the Short Packet Interrupt must be relied upon to indicate the end of the transfer This anomaly prevents the USB controller from issuing an RX interrupt for the corresponding endpoint when a short null packet is received This anomaly does not apply to device mode when the size of the receive transfer is known in advance as the DMA Completion Interrupt is generated at the end of the transfer and the endpoint receive interrupt is not used VisualDSP 5 0 Update 7 Release Notes Rev 1 0 Page 7 15 Workaround Use DMA Mode 0 instead of DMA Mode 1 This workaround is implemented in the HDRC driver such that bulk transfers use DMA Mode 0 by default This results in slower transfer rates If the buffer size is known to always be an integer multiple of the packet size then this default can be overridden To override the default arrange for your data buffer ADI_DEV_1D_BUFFER element count and width so that ElementCount ElementWidth n MAX_PKT_SIZE where n is an integer and MAX_PKT_SIZE is either 64 or 512 depending on whether the USB is connected
47. will produce this message CALL M14 112 DB 114 DM i6 m7 m7 PM il2 m14 postmodify When the file is assembled with the workaround enabled the assembler will produce the following message specifying why neither workaround could be applied Error ea2516 trampolineDBerrors asm 69 Workaround for Hardware Anomaly 09000011 not applied Trampoline cannot be used because a delay slot instruction modifies a DAG register used in the branch instruction Branch around improperly cached location cannot be used because delayed branch call cannot insert jump around third location after the call This workaround may generate unused assembly code To avoid linking this unused assembly code turn on linker elimination Select Project Project Options from the VisualDSP menu Select Link Elimination Check the box Eliminate unused objects Click OK PIN For more information about this silicon anomaly please refer to the latest ADSP 21371 ADSP 21375 Silicon Anomaly List VisualDSP 5 0 Update 3 Release Notes Rev 1 3 Page 3 16 Trampoline A trampoline solution is replacing a problematic branch instruction with a direct branch to a location in internal memory containing a branch that uses the index and modify registers of the original replaced branch instruction VisualDSP 5 0 Update 3 Release Notes Rev 1 3 Page 3 17 Anomaly Charts Tools Anomalies Addressed The following table is a list of too
48. workarounds for anomaly 09000018 The anomaly occurs when specific multiplier operations where multiplier results registers MRF MRB are used as a destination as part of the same instruction as an external memory access The result is that the multiplier results registers MRF MRB are not correctly updated The compiler workaround for this anomaly avoids parallel issue of data accesses and instructions with results in MR F or MR B To enable this compiler workaround manually the workaround 09000018 switch can be used When the workaround is enabled the macro __ WORKAROUND_09000018 is defined at compile assemble and link stages The SHARC assembler has been modified to issue a warning ea2523 for code that may hit the anomaly and require a workaround to be inserted An example of this new warning is Warning ea2523 wa_09000018 s 27 Potential Hardware Anomaly 09000018 due to combining a multiply operation into multiplier result register with a data access operation The assembler detection warning is enabled manually using the anomaly detect 09000018 switch The assembler defines macro __ASM_DETECT_09000018__ when detection for this anomaly is enabled The compiler and assembler workarounds are enabled automatically when building for ADSP 21371 and ADSP 21375 revisions 0 0 and any The runtime libraries and VDK support that is linked in when building for impacted parts and silicon revisions have been modified to avoid the anomal
49. 0 installation If VisualDSP 5 0 is not installed please install it first Installation on a previous update is permitted If a newer update has already been installed please do not install this update This update is not intended to be installed on alpha or beta releases For example do not install this update on the ADSP BF518F EZ KIT Beta Update It can be installed on the following official special releases e VisualDSP 5 0 ADSP BF506F EZ KIT e VisualDSP 5 0 ADSP 21479 and ADSP 21489 EZ Boards Identifying Your VisualDSP Version The VisualDSP release and update number can be found in 2 locations 1 In the Control Panel open the Add Remove Programs applet 2 In the VisualDSP Integrated Development and Debug Environment IDDE select Help gt About VisualDSP Installing the Update Follow the instructions below for installing this update Please note that since VisualDSP supports having multiple instances installed on a single system See the Cloning VisualDSP section below for more information 1 Use the Start Menu to navigate to VisualDSP Maintain this installation By default this is at Start Menu gt All Programs gt Analog Devices gt VisualDSP 5 0 2 Select Go to the Analog Devices website and click Next This will open a window in your web browser Select the appropriate Processor Software Tools Upgrades to match your processor Select and download the desired update VisualDSP 5 0_Upda
50. 022 an arithmetic loop cannot end one instruction after the last instruction of a loop nested within the arithmetic loop Ea2023 In the 2136x and later processors loops cannot contain operations on LPSTK and PCSTK Ea2024 if the end instruction resides at a lower address than the do instruction the assembler cannot validate the loop VisualDSP 5 0 Update 6 Release Notes Rev 1 3 Page 6 22 TAR 39444 RFRAME Instruction Only Used in Delay Slots SHARC It has been reported by some customers that the rframe instruction is not in fact atomic and it is possible for an interrupt to occur during the execution of the rframe instruction If this happens the function return sequence may execute incorrectly To avoid this issue the compiler will ensure that the rframe instruction is either used only in a delay slot or it is not used This change will affect code and projects that use the following compiler features e the optimize for space os command line switch e the no db command line switch e pragma no db return TAR 40221 TRUNC Incorrect for Negative Underflow SHARC There have been enhancements to the compiler support routines which mean that the TRUNC instruction is now used more often Due to a simulator issue some arithmetic operations particularly division and modulus operations may report incorrect answers when executed on the simulator TAR 40290 New Simulator Warning for _ lib_prog_term SHARC The
51. 1 VDK Thread s msg queue should initialize fields to O Blackfin 36575 Assembler Assembler allows illegal instruction Preg RETS on 535 incorrect register allocation of multiply inlined asm Blackfin 36507 Compiler statements Blackfin 36562 Compiler rvitmax builtin doesn t zero AO x before storing history to it Blackfin 36909 Compiler writes to a pointer removed inconsistently AD7879 chip is new and causes LCD Touch example to Blackfin 37970 Emulator not work BF527 amp BF548 programmer fail if Verify while Blackfin 38065 Flash Programmer programming Blackfin 38078 Flash Programmer Serial FLASH Programmer Driver not functional Blackfin 34201 IDDE incorrect variable used in Automation API example Enabling custom board support through automation Blackfin 34263 IDDE doesn t work Blackfin 36922 IDDE PGO example failing Blackfin 32741 Installation installer is not cleaning up HPPCI driver INFs Blackfin 26133 Loader Specified addr from p did not get into the Idr file with init Blackfin 33934 Run Time Libraries float16 h issues with negate_fl16 and add_fl16 Blackfin 36729 Run Time Libraries LIBDSP twiddle table generators can overflow stack ADSP BF51x SD_CARD_DET_MASK of RSI_EMASK Blackfin 36825 Run Time Libraries register Incorrect Blackfin 36871 Run Time Libraries 11_ memcpy and memcpy _ 1 use cli and sti incorrectly Misra rule 8 8 error in bfrom h __aes_init prototype Blackfin 37859 Run Time Libraries duplicated
52. 1 Page 8 20 These have been changed to define BMODE FLASH 0x0002 Use Boot ROM to load from 8 bit or 16 bit flash define BMODE SPIHOST 0x0004 Boot from SPIO host slave mode define BMODE SPIMEM 0x0006 Boot from serial SPI memory User code which relied on the original incorrect macro definitions will need to be modified since these macro definition changes may change the behavior of their program TAR 43849 SourceGenerator writes out files with LF endings not CR LF The Startup Code LDF Source Generator writes out generated source files with LF Line Feed endings however any modifications made to a generated source file in the IDDE Editor are saved with CR Carriage Return LF endings This may cause issues for other editors or for certain source code management systems The Startup Code LDF Source Generator now ensures that all generated source files have CR LF line endings TAR 43542 Init code example for ADSP BF506F EZ KIT Lite has incorrect EZ Board naming There were name changes for the ADSP BF506F EZ KIT Lite for TAR 43542 Any project which references the previous ADSP BF506F initialization file on the Project gt Load gt Options page or via the init option in a makefile needs to update to the new DXE name The original file names were BlackfinXldrlezkitBF506f initcode ROM V00 dxe Blackfin ldr init code asm ADSP BF506F EZ KIT Lite ezkitBF
53. 14xx Examples ADSP 21489 EZ Board MultilIteration Mode 214xx Examples ADSP 21489 EZ Board Power On Self Test 214xx Examples ADSP 21489 EZ Board RTC_ Seconds Test 214xx Examples ADSP 21489 EZ Board SingleIteration Mode 214xx Examples ADSP 21489 EZ Board SPDIF to Analog TalkThru with SRC C 214xx Examples ADSP 21489 EZ Board SPDIFToAnalogTalkThru C 214xx Examples ADSP 21489 EZ Board Talkthrough_IIR Accelerator 214xx Examples ADSP 21489 EZ Board UART echo back C 214xx Examples ADSP 21489 EZ Board VISA example les SHARC Audio EZ Extender 21489 AD1939 C Block Based Talkthru 192kHz les SHARC Audio EZ Extender 21489 AD1939 C Block Based Talkthru 48 or 96 kHz les SHARC Audio EZ Extender 21489 AD1939 C Sampled Based Talkthru 192 kHz les SHARC Audio EZ Extender 21489 AD1939 C Sampled Based Talkthru 48 or 96 kHz les SHARC Audio EZ Extender 21489 AD1939 I2S C Sampled Based Talkthru les SHARC Audio EZ Extender 21489 AnalogInDigitalout les SHARC Audio EZ Extender 21489 SPDIF to Analog TalkThru with SRC C l4xx Exam l4xx Exam l4xx Exam l4xx Exam 14xxXlExam 14xxXlExam 14xxXlExam NNNNNNDN E Es DDB ds BR DO 0 0 O 0 TU The following new projects have also been added 214xx Examples USB EZ EXTENDER USB I0 21489 usbio dpj 214xx Examples USB EZ EXTENDER USB Loopback 21489 usbloopback dpj 214xx Examples USB EZ EXTENDER USB Talkthrough 21489 usbtalkthrough dpj
54. 214xx include 21465 h 214xx include 21467 h 214xx include 21469 h Run Time Libraries ADSP 21462 ADSP 21465 ADSP 21467 ADSP 21469 DSP DSP DSP DSP functions functions functions functions New C C files and libraries have been included for ADSP 2146x processors Description Library File Name C run time library libc dlb libcmt dlb libc_nwc dlb libcmt_nwc dlb C run time library libcpp dlb libcppmt dlb libcpp nwc dlb libcppmt nwc dlb C run time library with exception handling support libcppeh dlb libcppehmt dlb libcppeh_nwc dlb libcppehmt_nwc dlb DSP run time library libdsp dlb libdsp_nwc dlb I O run time library libio dlb libiomt dlb libio nwc dlb libiomt_ nwc dlb LO run time library with no support for alternative device drivers orprintf Sa libio lite dlb libio litemt dlb libio lite nwc dlb libio litemt_nwc dlb VDK libraries TMK 2146X dlb VDK CORE 21469 dlb VDK i 2146X dlb VDK e 2146X dlb VDK n 2146X dlb TMK 2146X nwc dlb VDK CORE 21469 nwc dlb VDK i 2146X nwc dlb VDK e 2146X nwc dlb VDK n 2146X nwc dlb C start up file calls set up routines and main 21462 hdr doj 21465 hdr doj 21469 hdr doj 21467 hdr doj C start up file calls set up routines and main 21462 cpp hdr doj 21465 cpp hdr doj 21467 cpp hdr doj 21469 cpp hdr doj 21462 cpp hdr mt doj 21465 cpp hdr mt doj 21467 cpp hdr
55. 4 2 Identifying Your VisualDSP Version ccccccccccccsssessnsecececececsesssaeeeceeeescseseseeaeseeeesessesseeaeeeeeesenses 4 2 Installing the Update ni A eege 4 2 r MisWal DS Pt EE 4 2 o EE 4 3 TAR Tools Anomaly Reference Number 4 3 New Hardware SUPPOr disco dd ae eech dE ENEE ee 4 4 New Processors and Processor Revision Support 4 4 New Evaluation Board Support 4 4 New System Services and Device Drivers 4 6 NAND Flash Access egene ebe eege 4 6 Improved FAT driveri cene AAA A AA AS AAA 4 6 Power Management Change ii ESA 4 6 New Example Sian a EE E EEE E EE ds dd eng 4 7 ADSP BF526 EZ KIT WIGS Example sita iaai aa 4 7 Landscape LCD EZ EXTENDER Examples ccccccsessssscececeesceeseseseeeceeecesseseeaeseeeesesseesesaeaeeeeeeseeeees 4 7 NAND Flash AGc ss Exam ples ii dia iii 4 7 IWIP TEPAPE Mp naa 4 7 Critical Fixes Chang esinaine Ai 4 8 Upgrade to WIP Dai AAA AAA A E E AR 4 8 Boot ROM API Additions ADSP BF51x ADSP BF52x ADSb BEGAN 4 8 Changes to Reserved DDR Bits ADsp BEGAN 4 8 Feature Macros Black io iia 4 9 Init Code Changes Blackfin iren lara dd 4 9 TAR23499 Misallocation of Local Static Variables ICommon 4 9 imitatio EE 4 10 USB Driver Host ADSP BF52x ADSP BF54Xx ssssssssnssssssessserrssserssresssessersserrssstesseessressersssreessees 4 10 A DSP BFSIX Hedd Sii a A cen waned ta A EE 4 10 Power Service May Cause Unhandled CPLB Miss Exceptions ADSP BF54x oocooccccccococccccononnno
56. 4x processor series the default Rx DMA MODE is O These silicon anomalies have been fixed in ADSP BF522 524 526 revision 0 2 For optimal performance for the ADSP BF522 524 526 rev 0 2 the user can set the Rx DMA MODE to 1 The following code snippet shows how to enable DMA MODE 1 at the application level Set Driver s DMA operational mode ADI USB HDRC DMA CONFIG DmaConfig DmaConfig DmaChannel ADI USB HDRC RX CHANNEL DmaConfig DmaMode DMA MODE 1 or DMA MODE 0 Result adi_dev_Control PeripheralDevHandle ADI USB CMD SET DMA MODE void amp DmaConfig VisualDSP 5 0 Update 8 Release Notes Rev 2 1 Page 8 18 Critical Fixes Changes This section highlights significant changes due to software anomaly fixes or functional changes Feature Macros The following macros are automatically predefined by the assembler compiler and linker _ ADSPBF50x__ All ADSP BF50x processors __ADSPBESO6F_ FAMILY The ADSP BF504 4F 6F processor series _ ADSPBF504__ ADSP BF504 __ADSPBF504F __ ADSP BF504F __ADSPBF506F__ ADSP BF506F _2147x__ All ADSP 2147x processors _ ADSP21478 ADSP 21478 _ ADSP21479 ADSP 21479 2148x All ADSP 2148x processors _ ADSP21483 ADSP 21483 _ ADSP21486 ADSP 21486 __ADSP21487__ ADSP 21487 _ ADSP21488 ADSP 21488 __ADSP21489 ADSP 21489 TAR 41311 BF54x and BF52x NAND Boot DMA co
57. 506f initcode asm Blackfin ldr init code asm ADSP BF506F EZ KIT Lite ezkitBF506f initcode dpj Blackfin ldr init_code asm ADSP BF506F EZ KIT Lite ezkitBF506f initcode h Blackfin ldr init code asm ADSP BF506F EZ KIT Lite ezkitBF506f initcode ldf Blackfin ldr init_code c ADSP BFS06F EZ KIT Lite ezkitBF506f initcode c Blackfin ldr init_code c ADSP BF506F EZ KIT Lite ezkitBF506f initcode h Blackfin ldr init code c ADSP BF506F EZ KIT Lite ezkitBF506f initcode ldf Blackfin ldr init code c ADSP BF506F EZ KIT Lite ezkitBF506f initcode ROM V00 dpj The new file names are Blackfin ldr ezboardBF506f initcode ROM V00 dxe Blackfin ldr init_code asm ADSP BF506F EZ Board ezboardBF506f initcode Blackfin ldr init_code asm ADSP BF506F EZ Board ezboardBF506f initcode asm dpj Blackfin ldr init_code asm ADSP BF506F EZ BoardlezboardBF506f initcode h Blackfin ldr init_code asm ADSP BF506F EZ BoardlezboardBF506f initcode ldf Blackfin ldr init_code c ADSP BF506F EZ Board ezboardBF506f initcode c Blackfin ldr init_code c ADSP BFS506F EZ Board ezboardBF506f initcode h Blackfin ldr init_code c ADSP BF506F EZ Board ezboardBF506f initcode ldf Blackfin ldr init code c ADSP BF506F EZ Board ezboardBF506f initcode ROM V00 dpj TAR 44191 LDFs generated for ADSP BF52x si revision 0 0 parts causes link error li1271 If you create a project with a generated LDF for any of the ADSP BF52x parts and revision 0 0 you will
58. 548 EZ KIT Lite lockbox Getting Started Guide The Getting Started Guide for the BF548 EZ KIT Lite has been added This includes 8 easy to use and well documented examples The examples can be found at the following location Blackfin Examples ADSP BF548 EZ KIT Lite Getting Started Examples The documentation can be found in the Hardware Tools Manual under EZ KIT Lite Evaluation Systems VisualDSP 5 0 Update 1 Release Notes Rev 1 1 Page 1 5 Critical Fixes Changes This section highlights significant changes due to anomaly fixes or functional changes ADSP BF522 processor name change The ADSP BF522 has been renamed as the ADSP BF523 Support for this new name will be available in a future update Those who already created projects for the BF522 and did not use automatically generated LDFs for the ADSP BF522 may need to rewrite or modify their LDF files in the future Two header files for builtins_support h files TAR 33949 The Blackfin include builtins_support h include file was erroneously part of the VisualDSP 5 0 base release lt has been removed in Update 1 If you were including it explicitly in your application source you should lt builtins h gt instead SSL USB and DRV libs for ADSP BF52x not in default LDFs TAR 34050 The default and generated LDF files for the ADSP BF52x parts now explicitly link against the system services libssl527y dlb device drivers libdrv527y dlb and USB libusb527y dlb libraries If
59. 561 revision 0 5 ADSP BF53 1 23 revision 0 5 If you enable hardware errors in your application and are building for one of these parts and revisions you can avoid the 05 00 0245 related hardware errors in the following ways Adding workaround speculative loads to the compiler additional options to enable the compiler workaround when building C and C source For ADSP BF53 123 and ADSP BF561 parts building for silicon revision 0 4 rather than 0 5 will avoid the anomaly in the compiler generated code and system libraries VisualDSP 5 0 Update 1 Release Notes Rev 1 1 Page 1 9 Problem Charts Problems Addressed The following table is a list of problems addressed in VisualDSP 5 0 Update 1 for which details can be found on the public tools anomaly website Other problems have also been fixed in the Update Details can be found on the Tools Anomaly Web page The URL is http www analog com processors tools anomalies Product Family Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin VisualDSP 5 0 Update 1 Release Notes Rev 1 1 Problem Number 33976 28492 33786 33963 33403 33405 33808 33803 34185 34198 34061 33049 31695 34059 33652 33722 33178 33654 33733 33744 33792 33
60. 6 Rename MISCPORT register macros in ADSP BF52x def file TAR 2393b cs 1 6 Sometimes unable to connect to multiprocessor boards TAR 22068 1 7 Limitations iao Ea tater dd e teg AE ee eg 1 8 VisualDSP 5 0 ADSP BF54x Known Limitations oros 1 8 VisualDSP 5 0 ADSP BF52x Known Limitations ono 1 8 Set memory option fails for NET2272 USB loopback TAR 34450 oooccccccnnnononoonnonononcnnnnns 1 8 BF548 EZ KIT Lite USB drives may need to be formatted TAR 24627 1 8 File System rename function does not work TAR ZAPEN 1 8 LCD driver for the BF527 EZ KIT Lite needs modification 1 8 LCD Example for the BF527 EZ KIT Lite is missing oocccoccnonononocnnnnnnnnnnonnnnnnnnnnnnnnonnnnnnnnnos 1 9 USB LAN EZ Extender examples may Tall 1 9 ADSP BF5xx Silicon Anomaly Ob O0 0245 1 9 Problem EE 1 10 Problems AQdressed nad aa A a dada 1 10 KNOWN Problems pts ee eege 1 11 VisualDSP 5 0 Update 1 Release Notes Rev 1 1 Page 1 1 Nomenclature In the past VisualDSP updates were labeled by the month and year of their release In order to improve clarity updates will now be numbered e g Update 1 Update 2 etc Installation This update should only be installed after installing the VisualDSP 5 0 base release If VisualDSP 5 0 is not installed please install it first If a newer update has already been installed please do not install this update This update is not intended to be installed on alpha or beta releases
61. 7 m7 r2 dm i7 m7 lt Unique label gt 1 lt Unique_label gt This calling sequence will work in short word mode and in normal word mode and with any parts in the SHARC family All existing return code will work since it will take the saved address no longer necessarily the PC of the last instruction in the delay slot and incrementing it will get the address of the next instruction The assembler does this fix up automatically when necessary Informational message ea2536 lets the user know that the assembler made this change If you were to look at the saved address in the debugger you might notice that it didn t save the PC and wonder why You can modify your source code and it will still work for the 2136x as well as the 2146x If you don t modify your source code the assembler will continue to do the fix up to make it work New System Registers Header Files The following header files to provide symbolic names of system registers and their bits have been added These are included from platform include h 214xx include def21462 h 214xx include def21465 h 214xx include def21467 h 214xx include def21469 h 214xx include Cdef21462 h 214xx include Cdef21465 h 214xx include Cdef21467 h 214xx include Cdef21469 h Processor Header Files The following processor specific header files have been added These are included from processor include h VisualDSP 5 0 Update 6 Release Notes Rev 1 3 Page 6 12 214xx include 21462 h
62. 7x Writes to LCNTR CURLCNTR and LADDR from Internal Memory may fail if there is a DMA block conflict The anomaly is avoided by ensuring that writes to LCNTR CURLCNTR occur in two stages rather than loading them directly from memory This workaround is used in the runtime libraries and VDK linked when building for parts and revisions affected by the 09000023 errata Known limitations with this anomaly support e TAR40789 rtl behavior description in SHARC 2137X anomaly xml confusingly references DMA memory VisualDSP 5 0 Update 6 Release Notes Rev 1 3 Page 6 26 Anomaly Charts Tools Anomalies Addressed The following table is a list of tools anomalies addressed in VisualDSP 5 0 Update 6 for which details can be found on the public tools anomaly website Other tools anomalies have also been fixed in the Update Details can be found on the Tools Anomaly Web page The URL is http www analog com processors tools anomalies Tools Processor Anomaly Family Report Tool Description A Wee All 39414 Compiler boolean Blackfin 39634 asm cannot load to A1 BF548 Getting Started Examples misaligned address Blackfin 39783 Compiler violation Blackfin 40179 internal error circbuf c 258 building code with circindex Blackfin 36774 SPI driver requires baud rate in slave mode Blackfin 39698 Failure to create more than 507 files on FAT 32 volume Blackfin 40541 Device Driver adi_rawpid h has no C linkage SW
63. 8 Follow the on screen prompts to complete installation of this Update Cloning VisualDSP VisualDSP supports cloning of an existing installation A clone of an installation creates a new instance of a product from an existing installation rather than from a CD or web software distribution The use of clones allows you to maintain multiple versions of VisualDSP on the same PC at different update levels and provides a risk free way to test new updates or patches To clone your existing installation of VisualDSP VisualDSP 5 0 Update 3 Release Notes Rev 1 3 Page 3 3 21 Go to Start gt Programs gt Analog Devices gt VisualDSP 5 0 or equivalent gt Maintain this Installation 22 Select Clone this Installation and click Next 23 Optionally click Advanced to set the Start menu path 24 Enter the Clone install path and click Next Definitions This section provides definitions for terminology relating to VisualDSP and this document TAR Tools Anomaly Reference Number Tools Anomaly Reference Number or TAR is used for tracking confirmed defect reports in VisualDSP VisualDSP 5 0 Update 3 Release Notes Rev 1 3 Page 3 4 New Hardware Support VisualDSP updates often include support for new processors new silicon revisions for existing processors and new EZ KIT Lite evaluation systems In order to support these minor revisions are made to the tool chain and additional system services and device drivers
64. 825 33835 Tool ADspCommon XML Files Compiler Compiler Compiler CRTGen CRTGen Emulator Examples Examples Examples Flash Programmer IDDE LDF LDF LDFGen LDFGen Run Time Libraries Run Time Libraries Run Time Libraries Run Time Libraries Run Time Libraries Run Time Libraries Run Time Libraries Description Wrong breakout width for BF52x EBSZ bit field of EBIU_SDBCTL reg csqu_fr16 should be using saturating fractional operations Use of overlay can result in compiler assert bitset c 67 Compiler doesn t count inline asm length towards size of hw loop Generated cplbtab file unusable CPLB_D_PAGE_MGMT used indiscriminately in gen d BF535 cplbtab BF533 POST Release mode sets Loader width to 8 bit ADSP BF537 Drivers UART AutoBaud readme has no jumper settings The host side of the Inetd does not build for release build USB LAN EZ Extender board examples may fail to run correctly Error in ReadData for BF548 flash driver Loading DWARF3 debugging information may crash VisualDSP data1 is mapped before L1_bsz p1 and p2 do not work with default LDFS 5 0 Stack in mem covered by cplb data table entry in WB mode problem Two output sections with the same name are generated Remove NWIDTH in NFC_ CTL bit definitions for ADSP BF52x devices DSP library function conv2d3x3_fr16 based on wrong algorithm Disable_data_cache does not work Incorrect macro names for HOSTDP masks in BF52x BF54x he
65. A To avoid these warnings remove the pragma section indicated and place it before the required variable or function declaration instead New compiler pragma pragma save_restore_40_bits The new compiler pragma save restore 40 bits can be used along with pragma interrupt complete or pragma interrupt complete nesting to save and restore all 40 bits of the data registers Dregs used by the handler This ensures that any routines using 40 bit arithmetic that are interrupted do not suffer inaccuracies For leaf routines that is routines that do not call any other functions the compiler saves and restores only the registers that are used For non leaf routines the compiler saves and restores 40 bits of all Dregs Note that saving and restoring each Dreg requires 6 instructions For newly created VDK interrupts the templates include this pragma if the macro VDK_SAVE_RESTORE SIMD 40 BITS is defined Defining VDK_SAVE RESTORE SIMD 40 BITS in a VDK assembly ISR before the inclusion of the VDK h file also ensures that the 40 bits of the registers are saved and restored by the VDK ISR macros Using VisualDSP 5 0 Update 7 Release Notes Rev 1 0 Page 7 20 these macros incurs both performance and space penalties Customers who want to change the behavior of existing C ISRs must add the pragmas themselves Improved 64 bit Floating point Support for SHARC The support routines for primitive double precision flo
66. BF526 EZ Board Example S iii ainia sics 6 6 Landscape LCD EZ EXTENDER Examples ccccccsessssccececeeecseseeaeceeeeseeesesseaeseeeeeesseesseseaeeeeeeseneaes 6 6 New System Services and Device Drivers ccccecsesssscceceeeesesessnaecececeesssesnsaeaeeeeeesseeseaaeeeeeesesssessaaeas 6 7 USB Audio Class DRIVEN sises00s320he00 anene i beat ica 6 7 LED DIME ii A A ee A A A eae ide Ween ee 6 7 Capacitive Touch Controller Driver 6 7 Touch Screen Controller Driver mouara cxsctesescsashateds condenses ENEE a oaa o ed skartesesssaviette 6 7 ADSP BE5SLx SyStem Services s Aecnc idl A eg leh eh hide cated eh A A tis oa aah 6 7 PWM System S rviCe a sec cctectiasbesieessesbaaanalbovieesvsaativel ai SE 6 7 New Exatrgpl g ii a ii as dd eegent 6 7 BOOT ROM ee EE 6 8 ge ee dd da da ida 6 8 ER Voltage Regulatorn nnna a a iaa 6 8 ADSP 2146x Processor Series REENEN REENEN EEN 6 9 Feat re MAGIOS EE 6 9 New COM piler SwitGhes zcviscecsgeee cceerssedevytees eed cadet A A a ET 6 9 New Pragma SUPONE iii 6 10 New Automatic Attributes ssessseesessssesreensessssesrreretsssssserrrresessssesrrerstsssseserereesssseseerreesesssseereera 6 10 NEW ASSEMBDIERSWITCHES iaso eenei inann inmensa leloudedsleeghesy de eege 6 10 New SECTION Directive Qualifiers ssnnssnnsnssssossrenerssssssesrrresrssssesrrersrsssseserererssssssrerreesesssseseeens 6 11 New Assembler Directives aren reg eet Eeer 6 11 New Assembler Intormatonaleaib p 6 12
67. Bits ADSP BF54x Some incomplete support from mobile DDR has been removed from the BOOT ROM header Blackfin include bfrom h These changes are for the ADSP BF542 ADSP BF544 ADSP BF547 ADSP BF548 and ADSP BF549 parts e Definitions of macros OTP_EBIU_MOBILE_DDR_P and OTP_EBIU_MOBILE_DDR_M have been removed VisualDSP 5 0 Update 4 Release Notes Rev 1 2 Page 4 8 e The ebiu_mobile_ddr field has been deleted from the ADI_PBS_BITFIELDS struct type e Bit 5 the former MDDRENABLE bit is now a reserved bit field Feature Macros Blackfin The lt feature macros gt block in the System ArchDef compiler xml files contain macros that the assembler and compiler automatically pre define General macros for processor families e g __ADSPBF54x__ are now consistently defined for the Blackfin processor families For more details see below Macro Processors _ADSPBFS1x__ ADSP BF512 ADSP BF514 ADSP BF516 __ADSPBFS2x__ ADSP BF522 ADSP BF523 ADSP BF524 ADSP BF525 ADSP BF526 ADSP BF527 __ADSPBFS2xLP__ ADSP BF522 ADSP BF524 ADSP BF526 __ADSPBF53x__ ADSP BF531 ADSP BF532 ADSP BF533 ADSP BF534 ADSP BF536 ADSP BF537 ADSP BF538 ADSP BF539 _ADSPBF54x__ ADSP BF542 ADSP BF544 ADSP BF547 ADSP BF548 ADSP BF549 _ ADSPBFS6x__ ADSP BF561 Init Code Changes Blackfin The Blackfin initialization code has been modified in the following ways e Added a UART Baud Rate Handler e SysControl available in the ADSP
68. Blackfin Examples ADSP BF518F Blackfin Examples ADSP BF518F Blackfin Examples ADSP BF518F ADSP BF526 EZ KIT Lite Examples VisualDSP 5 0 Update 5 provides a LockBox example for the ADSP BF526 EZ KIT Lite The example can be found in the following directory Blackfin EZ Board Flash Programmer Parallel EZ Board Flash Programmer Serial EZ Board Power On Self Test Examples ADSP BF526 Landscape LCD EZ EXTENDER Examples VisualDSP 5 0 Update 5 provides an LCD example for the ADSP BF526 ADSP BF527 and ADSP BF548 EZ KIT Lites Blackfin EZ KIT Lite lockbox END Examples Landscape LCD EZ EXT VisualDSP 5 0 Update 5 Release Notes Rev 1 8 ER LCD ColorBarDisplay Page 5 7 Critical Fixes Changes This section highlights significant changes due to software anomaly fixes or functional changes New Blackfin Compiler Switches New Blackfin Compiler Switches icplbs dcplbs icplbs The icplbs Instruction CPLBs are active switch instructs the compiler to assume that all instruction memory accesses will be validated by the Blackfin processor s memory protection hardware This allows the compiler to identify situations where the cacheability protection lookaside buffers CPLBs will avoid issues the compiler would otherwise workaround e g anomaly 05 00 0426 improving code size and performance dcplbs The dcplbs Data CPLBs are active switch i
69. Breakpoints Ignored Upon Return From Lockbox Blackfin 36663 Emulator Authentication Blackfin 39639 BF533 POST failed at Ethernet test for EZ USBLAN board Blackfin 39939 Emulator Windows Driver Entry Point Not Found Blackfin 39766 Examples BF548 Driver Example UART AutoBaud readme txt pb2 doesn t halt BF526 POST example readme for USB Peripheral Host Blackfin 40592 Examples confusing LDF SIZEOF macro reports incorrect value when using Blackfin 40073 Linker RESOLVE Blackfin 40024 Loader Compression the later part of user application is lost in LDR BF518F example Flash programmer Internal SPI won t load Blackfin 40469 Examples dxe Blackfin 38090 Run Time Libraries strtoull may give incorrect result Blackfin 39572 Run Time Libraries li2152 due to missing Instrumented Profiling support for BF51x Blackfin 39623 Run Time Libraries no prototype for adi_acquire_lock adi_try_lock with no builtin Blackfin 38085 Run Time Libraries float16 negate_fl16 is incorrect Blackfin 39636 Run Time Libraries memcpy not safe against IC anomaly 05000428 Blackfin 39637 Run Time Libraries zero_crossd not safe against IC anomaly 05000428 VisualDSP 5 0 Update 6 Release Notes Rev 1 3 Page 6 27 Blackfin 39681 Run Time Libraries libdsp FFT functions fail for sizes gt 32K Blackfin 39705 Run Time Libraries Default 561 CPLB data table causes CPLB exception meminit for BF53 467 BF51x BF52x BF54x
70. C processor has been corrected VisualDSP 5 0 Release Notes Page 9 throughout the tools including the linker and the default LDFs This was fixed in the VisualDSP 4 5 June update There are three consequences to these changes 1 Any LDF that is heavily derived from a default LDF of a version of VisualDSP prior to the VisualDSP 4 5 June update may result in linker error el2011 Invalid memory range and or width for memory when linking In this situation the LDF must be corrected to reflect the actual memory map of the ADSP 21375 target 2 Any application that uses the default LDF and more memory than is available on the ADSP 21375 part memory map will cause linker errors li1040 Out of memory in output section In previous Updates the link of such applications may have succeeded In this situation it will be necessary to reduce memory usage or build for a part with more memory available oo Out of the box the VDK 21375 ldf will get a linker error li1040 for Out of memory in output section seg_pmco in processor VDK is too large for the ADSP 21375 to fit in internal memory To use VDK in an ADSP 21375 processor external memory must be used The data sheets for these parts have corrected memory map information and can be downloaded from www analog com by doing a search for the required part number e g ADSP 21375 Former Workaround for 05 00 0311 is Not Safe Blackfin TAR 32344 TAR 32344 Former workaro
71. CMD_SET_CACHE_PERFORMANCE command can be used to change this default behavior to either synchronize immediately on cache changes for maximum data integrity or to synchronize only when media is unmounted Extreme caution is advised for the latter option Power Management Change The power management service for the ADSP BF54x revisions 0 1 and 0 2 have been modified to call the Boot ROM function bfrom_syscontrol This function safely programs the VR and PLL registers incorporating trim offsets values that have been stored in the OTP VisualDSP 5 0 Update 4 Release Notes Rev 1 2 Page 4 6 New Examples ADSP BF526 EZ KIT Lite Examples VisualDSP 5 0 Update 4 includes full support for the ADSP BF526 EZ KIT Lite evaluation system Examples can be found in the following directory Blackfin Examples ADSP BF526 EZ KIT Lite Landscape LCD EZ EXTENDER Examples VisualDSP 5 0 Update 4 includes initial support of the Landscape LCD EZ Extender There is sample source code available for the LCD touch screen and capacitance touch Additional support will be available in future updates Blackfin Examples landscape Blackfin Examples sandscape Blackfin Examples andscape CD EZ EXTENDER Power On Self Test LCD CD EZ EXTENDER Power On Self Test TouchScreen CD EZ EXTENDER Power On Self Test CapTouch NAND Flash Access Examples VisualDSP 5 0 Update 4 includes a new
72. CRT header source 06x hdr asm for example defined function 1ib prog term executed after _main returns used to be lib prog term pm _done execution pc idle jump __ lib prog term As of VisualDSP 5 0 Update 6 this code may cause the following simulator warning xxx Write access to Read only Address 0x900c1 in 32 bit space from instruction at PC 0x900be The warning is valid and the writeto done execution does not work The warning indicates the issue on parts where the write is actually to ROM The fix that has been done is to remove this store along with the associated done execution for all SHARC processors VisualDSP 5 0 Update 6 Release Notes Rev 1 3 Page 6 23 Silicon Anomaly Workarounds Anomaly workaround information is available in the online help Select Help gt Contents gt Graphical Environment gt Silicon Anomaly Support gt Silicon Anomalies Tools Support and then click the appropriate processor series Silicon Anomaly 05000412 ADSP BF561 TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled The anomaly occurs when a TESTSET instruction is used to operate on L2 memory and there is data in external memory that is cached using write back mode The result is that data in L2 and or external memory can become corrupted Runtime library workarounds for this anomaly were made in VisualDSP 5 0 Update 5 In Update 6 compiler and assembler support has been added The Update 6 comp
73. EEEE ved chateaus eaten atte EAAS 8 9 MECA das 8 10 Programming for Internal Memory and FLASH on ADSb BEN 8 11 Project Settings for Internal Memory and FLASH 8 11 Memory Sections for Internal Memory and FLASH 8 11 Loading a Program into Internal Memory and FLASH 8 11 Introducing the ADSP BF592 with Tools Utility ROM 8 12 Sim l tor SUP DO EE 8 12 Compiler Assembler Linker eerste eege 8 12 ADSP BF592 System Services and Device Driver Support 8 12 System Services Device Driver Notes oracion nnnronannrnnnnnnns 8 13 ADSP BF506F System Services and Device Driver Support ccooooccccononccononononononanannncconanccononanannnnnnns 8 13 ADSP BES5OX PWM SERVICE iaa ia 8 13 ADSP BF527 Modifications EE 8 13 LAN9218 Memory DMA based driver support for ADSP BF548 Plattorm 8 14 VisualDSP 5 0 Update 8 Release Notes Rev 2 1 Page 8 1 Memory Manager Service 8 14 Standard I O Service taa ad 8 15 USB Support Blackfin and SHARC Lada ia 8 15 Silicon Anomaly Workaround So ersaat a ataa a a adaa rana e ASEA aaea EARE asai 8 16 Silicon Anomaly 05000431 ADSP BF51x 52x 54X oooococococooncononononoonncconocono nono ncon occ nn nnnnnonnccon anios 8 17 Silicon Anomalies 05000456 05000460 05000465 ADSP BF522 4 6 rev 02 8 18 Critical Fixes 7 CHAN BES ta A 8 19 Feat re MAGCIOS tasis nininini is DIAL ADS AAA ARA AA Abs 8 19 TAR 41311 BF54x and BF52x NAND Boot DMA codes incorrect ADSP BF52x BF54x 8 19 TAR 43683 Watchdo
74. Handle iii AAA sanded AAA A R died cote 5 10 Syscontrol variation for ADSP BF54xM rev 0 3 isscsccissccossascsssdenssovovaasrvvaconnssesesa ances daba veni coa 5 10 TAR 36697 MISRA Rule 19 4 Change ds 5 10 TAR 38060 ADSP BF52x Macros Removed EE 5 11 TAR 37863 Run Time Library uses dual data move 5 11 TAR 39783 Misaligned address violation 5 11 TAR 39756 Some examples cause hardware rTOTF cocccccccnnononoonnnnnnnnnnononononnnnnonnnnnnnnnnnnnnnnnnnnnnnnos 5 13 LIMA ION CN 5 14 ADSP BF51x Silicon REVISION Support 5 14 OUP BO add 5 14 Silicon Anomaly Workarounde 5 15 Silicon Anomaly 05000412 ADSP BF561 scccsssccssssecsscecssssecssssecssseecssssecssseeesseeesesesesseeesees 5 15 Silicon Anomaly 05000426 ADSP BF5xXxX ccccssecsssecsseecssseecesseecsseeecseeecseeecseeeceeeeesaeeeesaeeseaas 5 15 Silicon Anomaly 05000428 ADSP BF561 assi sae tadad EE ege 5 16 Anomaly Charts 5 isi stssccbeced hie vsastiveds hideste eae its 5 17 VisualDSP 5 0 Update 5 Release Notes Rev 1 8 Page 5 1 Tools Anomalies Addressed ccccccesssccccccsscecccescccccueccceauscecessececeaueseeceauensecesseseeesueseceuaenseeeaa 5 17 KNOWN Tools Anomali s 000 ta 5 18 Nomenclature In the past VisualDSP updates were labeled by the month and year of their release In order to improve clarity updates are now numbered e g Update 1 Update 2 etc Release Notes These release notes subsume the release notes for previo
75. Improved 64 bit Floating point Support for SHARE 7 21 Assembler Processing of Anomaly Options EN 7 21 TAR42009 526 Audio_Loopback dpj ran and terminated almost right away ccccnnoccnccnnnnnnos 7 21 TAR42058 526 audio codec example readme diagram wrong 7 21 TAR42059 SSL DD Incompatible with UC OS II version 2 86 7 22 ue 7 23 Fools Anomalies AOS ati AA AAA A 7 23 n Le Tools Nee EU 7 25 VisualDSP 5 0 Update 7 Release Notes Rev 1 0 Page 7 2 Nomenclature In the past VisualDSP updates were labeled by the month and year of their release In order to improve clarity updates are now numbered e g Update 1 Update 2 etc Release Notes These release notes subsume the release notes for previous updates Release notes for previous updates can be found at the end of this document Installation This update can only be installed on a previous VisualDSP 5 0 installation If VisualDSP 5 0 is not installed please install it first Installation on a previous update is permitted If a newer update has already been installed please do not install this update This update is not intended to be installed on alpha or beta releases For example do not install this update on the ADSP BF518F EZ KIT Beta Update Identifying Your VisualDSP Version The VisualDSP release and update number can be found in 2 locations 3 Inthe Control Panel open the Add Remove Programs applet 4 In the VisualDSP Integrated Development and De
76. N anomaly xml has been modified to include anomaly workarounds specific to the system services and device driver libraries Anomaly workaround information is still available in the online help Select Help gt Contents gt Graphical Environment gt Silicon Anomaly Support gt Silicon Anomalies Tools Support and then select the appropriate processor family Silicon Anomaly 05000412 ADSP BF561 TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled The Blackfin runtime libraries have been enhanced to include workarounds for anomaly 05000412 The anomaly occurs when a TESTSET instruction is used to operate on L2 memory and there is data in external memory that is cached using writeback mode The result is that data in L2 and or external memory can become corrupted The runtime libraries that are linked in when building for impacted parts and silicon revisions have been modified to avoid the anomaly The workaround involves preceding TESTSET instructions with a dummy read and an SSYNC instruction Assembler detection and modifications to the compiler s testset built in function will be provided in a future update Silicon Anomaly 05000426 ADSP BF5xx Speculative Instruction Fetches Can Cause Spurious Hardware Errors The Blackfin C C compiler VDK and runtime libraries have been enhanced to include workarounds for anomaly 05000426 The anomaly occurs when there is an indirect jump or call through a po
77. Pd example missing copyright notice Blackfin 40868 BF537 and Audio EZ Extender do not work Blackfin 41267 POST config loader option Initialization file path wrong 538 539 default LDFs do not provide ARGV section if Blackfin 40788 LDF SDRAM is on Loader start address argument inconsistent with Blackfin 40883 Loader documentation Blackfin 41365 si revision any generates incorrect loader stream Blackfin 33934 Run Time Libraries float16 h issues with negate_fl16 and add_fl16 Using IO and thread local storage can cause deadlock Blackfin 40163 Run Time Libraries bf561 Blackfin 40481 Run Time Libraries evicting ICPLB 15 in _cplb_mgr causes a core fault memcpy_l1 asm and 1_memcpy asm not safe from Blackfin 40815 Run Time Libraries anomaly 05 00 0312 Blackfin 40880 Run Time Libraries multicore startup corruption in shared library variables II memcpy and memcpy_l1 can fail with BF51x revision Blackfin 41134 Run Time Libraries 0 1 Blackfin 41164 Run Time Libraries cplb_init treats P1 as a preserved register disabling Idf gen in BF561 single core single app proj Blackfin 40928 Source Generator cause err Project name with 8 6 etc in it causes MD Blackfin 40939 Source Generator failure ADSP BF561 boundary workaround not applied for si Blackfin 40950 Source Generator revision auto Blackfin 40953 full io does not trigger regeneration of LDF adi_ebiu_Init to config ext mem is called from Core A a
78. Regulator is now turned off by default You can activate this feature again in the corresponding initcode header file For example undefine the following in ezkitBF527 initcode h define ACTIVATE DPM This was done to be compatible with the emulator register resets in the processor XML files which just set up the EBIU VisualDSP 5 0 Update 6 Release Notes Rev 1 3 Page 6 8 ADSP 2146x Processor Series The ADSP 2146x is a new SHARC processor series that supports a short word instruction set for code size reduction The ADSP 2146x is binary backwards compatible that is ADSP 2137x binary code will run on the ADSP 2146x without modification Short word instructions and normal word instructions must be in separate sections but otherwise can both be used in the same application for optimal compatibility This section outlines the changes necessary to VisualDSP 5 0 provided in Update 6 to support this new processor series At the time of the Update 6 release the short word instruction set had not been fully tested It is advisable to use the normal word instruction set Feature Macros The following macros are automatically predefined by the assembler compiler and linker New macro Description _2146x__ All ADSP 2146x processors _ 214xx __ ADSP21462__ ADSP 21462 __ADSP21465__ ADSP 21465 __ ADSP21467__ ADSP 21467 _ ADSP21469 ADSP 21469 The following macros are automatically predefined by the as
79. SIC_IWR register name the compiled code will only address the wakeup bits in SIC_IWRO while SIC_IWR1 is neglected The application may need to be modified if the intent was to address both the SIC_IWRO and SIC_IWR1 registers If porting an application to an ADSP BF51x or ADSP BF52x from an older Blackfin processor any usage of the SIC_IWR register in the source code should be examined to determine whether it should be replaced by both the SIC_IWRO and SIC_IWR1 registers New Messages Due to the SIMD SHARC Assembler Enforcing Loop Restrictions The assembler will analyze hardware loop code warning the user when the documented restrictions have been violated and providing a reminder when its static analysis cannot verify the code adheres to the restrictions specifically that a CALL in the last three instructions must return with the LR option to preserve integrity of the loop The new messages the assembler can produce during this validation are Ea2018 error detected that two loops end on the same instruction Ea2019 warns that the code violates restrictions on loop end instructions Ea2020 warns of a possible violation of the loop end restrictions as when a call is in two instruction loop and the assembler does not know the loop count a one iteration two instruction loop should not have a CALL in it Ea2021 reminder that any call in the last three instructions of a hardware loop must return with the LR option Ea2
80. T when stack in scratchpad FLT_MAX nota float literal DMA32 bit in PPI erroneously appears in single core def headers mulfl64 asm in release not same as used to build library BF535 crash running attached DXE in BF535 CAS Self Nesting Interrupts not supported in Blackfin BF533 CAS 32 bit registers in EBIU only accept 16 bit writes on a BF561 Page 13 Blackfin Blackfin Blackfin Blackfin Blackfin SHARC SHARC SHARC SHARC SHARC SHARC SHARC SHARC SHARC SHARC SHARC SHARC SHARC SHARC SHARC SHARC SHARC SHARC TigerSHARC TigerSHARC TigerSHARC TigerSHARC TigerSHARC TigerSHARC TigerSHARC TigerSHARC 31895 28946 30450 30991 32156 28087 20526 28993 29964 31767 32198 29246 25305 31421 29802 28074 30078 31200 31850 33303 29900 30460 32673 32115 22672 31832 32041 29096 32803 29735 29836 Simulator TCPIP Stack ADspCommon XML Files Compiler Compiler Compiler Compiler Compiler Examples IDDE IDDE LDF Linker Run Time Libraries Run Time Libraries Run Time Libraries Run Time Libraries Utilities Simulator Simulator ADspCommon XML Files Assembler Assembler Assembler Compiler IDDE Run Time Libraries Run Time Libraries Known Problems The following table is a list of known problems in VisualDSP 5 0 Size information for all of the caches show up as 0 Kbytes LwIP Project does not accept broadcast traffic in VDSP 4 5 Contradictory information provided
81. Used in Delay Slots SHARC sss nnnnssnnssesnnssoneessnsrnnnssene 6 23 TAR 40221 TRUNC Incorrect for Negative Underflow SHARE 6 23 TAR 40290 New Simulator Warning for __lib_ prog term SHARE 6 23 Silicon Anomaly Work FO UN Asoc EA AAA 6 24 Silicon Anomaly 05000412 ADSP BESGL ua a 6 24 Silicon Anomaly 05000426 ADSP BF5xXxX cccsssccssssecessecseseecesseecseeeecseeecseeecsseeecseeeesseeeesseesenas 6 24 Silicon Anomaly 05000428 ADSP BF561 scccsssccssssecssssecssssecssseecssecesssssesseseesseeeeseseseneeeeees 6 25 Silicon Anomaly 09000020 ADSP 2137X cccssccssssscssssecssssecssssecssseesssneesssesecseseeeseeesesssesssaeeesees 6 25 Silicon Anomaly 09000023 ADSP 21 3 7 iii aa as 6 26 Anomaly Charts alii 6 27 FOOIS Anomalles e EE 6 27 Known RE ele E 6 28 VisualDSP 5 0 Update 6 Release Notes Rev 1 3 Page 6 2 Nomenclature In the past VisualDSP updates were labeled by the month and year of their release In order to improve clarity updates are now numbered e g Update 1 Update 2 etc Release Notes These release notes subsume the release notes for previous updates Release notes for previous updates can be found at the end of this document Installation This update can only be installed on a previous VisualDSP 5 0 installation If VisualDSP 5 0 is not installed please install it first Installation on a previous update is permitted If a newer update has already been installed please do
82. VisualDSP 5 0 Update 8 Release Notes Revision 2 1 September 29 2010 Table of Contents ere getest 8 3 Release NOLES O A cause cranbageceoasbutes 8 3 Installati n rita AA A A A AA AS E 8 3 Identifying Your VisualDSP Version ocoooococncncncncconnoonnnnnnnnncnnnnnononnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnonnnnnnnnnnnnnnns 8 3 Installing the Update AA A A 8 3 TAE ege ANEN ege 8 3 A A A A A a a daa 8 4 TAR Tools Anomaly Reporta EEGEN 8 4 NewW Silicon Support scoisina iaa id 8 5 ADSP BF5OX ProceSSOr Seri s mrar ege cia A a iii 8 5 ADSP BE59IZ ROCOSO fia ddr inde ri 8 5 ADSP 21 47x lee 8 5 ADSP 21 48x SAA hactegeeccuabedevduendecccaseateeendecececsabetes 8 5 New Silicon Rev CEET 8 6 New Evaluation Board SUDDO eeen a a s 8 7 ADSP BESOGF EZ KI Lite at A A de E 8 7 ADSP BESZ6 EZ BOAFA REVA Piironen natie adaini A RA T 8 7 ADSP BF527 EZ KIT Lit REV Zilina dalla 8 7 ADSLAREA 8 7 ADSP 21489 EZONE aaa 8 8 Ebert Eege edel ee EE ta Id Eens 8 9 ACM Example ADSP BESOGE asii AA AA 8 9 Audio Loopback Example ADSP BESTB eege gege eege 8 9 Standard I O Service Example ADSP BF527 548 EZ KIT Lites ooococcoonccconnnononnnononnnonananonancnonnnoos 8 9 Memory Service Example ADSP BF548 EZ KIT Lite ccoooocccnnnocccnnonooocnncnononnccnnnonncnnnnnnnnnnccononnnnos 8 9 OTP Programmer ADSP BF526 527 548 EZ KIT Lites oooooocincccnoccconaconnnonnnconnnconoconnnnnn ccoo cnica nonnnnos 8 9 Boot ROM COde saniet ak T eet arctan ca Nude A
83. Word accesses using PM bus can vector to an unknown location New information about this anomaly has been added to the anomaly dictionary in system ArchDef SHARC 2126X anomaly xml The anomaly concerns indirect jumps or calls followed by Long Word accesses using PM bus or invalid instruction possibly vectoring to an unknown location VisualDSP 5 0 Update 7 Release Notes Rev 1 0 Page 7 11 One situation that can cause the anomaly that is of concern to many applications is at the end of a program s code It is likely that the last instruction in an application will be an indirect jump that is a return from the last function linked If the memory that follows such a jump is not initialized or is data this could trigger the anomaly This cause of the anomaly can be avoided by inserting a NOP at the end of your application code This workaround can be implemented in the VisualDSP LDF by placing a FILL command anda 2 command after your code sections INPUT_SECTIONS commands e g seg pmco INPUT SECTIONS SOBJS seg_pmco LIBS seg_pmco FILL 0x0 workaround 06000020 at the end of instruction memory 2 there must be a space on both sides of each An automatic tools workaround for this anomaly is being considered for a future release Silicon Anomaly 09000021 15000003 ADSP 2137x ADSP 214xx IOP Register access immediately following an External Memory access may not work The anomaly happens i
84. able_delay 0 Blackfin lib src drivers Ilcd adi_Icd c line 504 VisualDSP 5 0 Update 1 Release Notes Rev 1 1 Page 1 8 FsTmrBuf enable_delay 0 Blackfin lib src drivers Ilcd nec adi_nl6448bc33_54 c line 477 FsTmrBuf enable_delay 0 LCD Example for the BF527 EZ KIT Lite is missing There is no example for the ADSP BF527 EZ KIT Lite LCD LCD Drivers exist but there is no example project on how to use it This will be available in a future Update USB LAN EZ Extender examples may fail When using BF561 EZ KIT Lite rev 2 0 or 2 1 with ADSP BF561 revision 0 5 silicon in conjunction with the USB LAN EZ Extender USB and LAN examples may fail to run To avoid this problem reduce the SCLK to 100 MHz or lower To avoid this problem make the following changes On line 105 in Blackfin Examples USB LAN EZ EXTENDER USB bulk_loopback_app usb_ezkit_utils c define SCLK 100000000 On line 105 in Blackfin Examples USB LAN EZ EXTENDER USB bulk_redirect_io_app usb_ezkit_utils c define SCLK 100000000 On line 105 in Blackfin Examples USB LAN EZ EXTENDER USB mass_storage_app usb_ezkit_utils c define SCLK 100000000 ADSP BF5xx Silicon Anomaly 05 00 0245 The 05 00 0245 anomaly causes hardware errors on speculative loads The tools workarounds for this anomaly is not enabled for all parts and revisions which are impacted by the anomaly The missing parts and revisions are ADSP BF54x all revisions ADSP BF52x revision 0 0 ADSP BF
85. ader Files 3 10 TAR 34700 HMDMAx_CONTROL Bit Macros in ADSP BF54x Definition Header Files 3 10 TAR 35154 SIC_RVECT Removed from Definition Header Ples 3 11 TAR 35481 Fixed Signed CHAR definition E 3 11 TAR 33557 Blackfin 64 bit double modf Result Changed ooooonccccccncnononooncnnnnnncnnnanannnnos 3 11 Bil L ele 3 12 VisualDSP 5 0 ADSP BF54x Known Limitations cccccecessseeeceeesseeeeeseseeecesseeeeeeseaes 3 12 VisualDSP 5 0 ADSP BF52x Known Limitations cccccccessseeeeesssneeeecssneeeeesseeeeeeeeaes 3 12 Workarounds for Silicon Anomaly 05 00 00371 ADSP BF54 24789 Rev 01 3 12 TAR 35159 VDK Thread Stack Space Reduced on TigerHAbt 3 12 TAR 35556 System Services Caps CCLK for DDR reliability cccoooooonocccncncnonanonn noo 3 13 Silicon Anomaly Workarounde hieno nraesa inaintarea iaie en nia 3 15 VisualDSP 5 0 Update 3 Release Notes Rev 1 3 Page 3 1 Silicon Anomaly 09000011 ADSp 2137 3 15 Recul Le UE data 3 17 NS NN 3 18 Tools Anomalies Addressed ro nncnnnnnnonaninannns 3 18 Known Tools Anomalies VisualDSP 5 0 Update 3 Release Notes Rev 1 3 Page 3 2 Nomenclature In the past VisualDSP updates were labeled by the month and year of their release In order to improve clarity updates are now numbered e g Update 1 Update 2 etc Installation This update should only be installed after installing the VisualDSP 5 0 base release If VisualDSP 5 0
86. aders Remove PORT_MUX from ADSP BF52x def cdef headers PPI_STATUS missing bit masks for ADSP BF52x Rename HYSTERESIS MISCPORT_ register macros in ADSP BF52x hdr Page 1 10 Blackfin 33901 Run Time Including before vdk h will result in an error Libraries Blackfin 34112 Run Time BF561 Memory Initializer will not initialize external SDRAM Libraries Blackfin 33627 TCPIP Stack Corrupted BF537 EZ KIT proj LAN Host FILESERVER FileServer dsp Blackfin 33843 TCPIP Stack BF USB LAN Extender Examples and library do not work SHARC 33968 Emulator Unable to connect to Multi processor boards SHARC 33938 Hardware 21369 EZ KIT Lite SPI Flash support changing Board SHARC 33671 Run Time MTM registers missing from cdef21364 h Libraries SHARC 34118 Run Time CYCLE_COUNT_ macros can give wrong results with Libraries optimization SHARC 33887 Simulator Reg modify then write to ext mem writes old reg value TigerSharc 28363 Compiler Functions with pragma weak_entry can be inlined TigerSharc 32429 Compiler Internal error diag_message missing string substitution TigerSharc 34022 VDK VDK API level check can cause false positive Kernel Panic Known Problems Details can be found on the Tools Anomaly Web page The URL is http www analog com processors tools anomalies VisualDSP 5 0 Update 1 Release Notes Rev 1 1 Page 1 11 VisualDSP 5 0 Release Notes 2007 August 28 Table of Contents VisualDSP 5 0 Documents 2 Release Ote A da ia 2 Produ
87. al Memory VisualDSP 5 0 Update 8 Release Notes Rev 2 1 Page 8 11 Introducing the ADSP BF592 with Tools Utility ROM The ADSP BF592 is the first Analog Devices DSP to include a ROM with run time libraries The ROM helps reduce the application footprint for this processor Applications that use the functions available in the ROM are linked to reference the ROM code thus reducing the size of the application Simulator Support VisualDSP 5 0 Update 8 provides simulator support forthe ROM The ADSP BF592 Single Processor Simulator will load the ROM image into memory prior to loading the application on a File Load Program The entry points and contents of the Tools Utility ROM will be displayed in the disassembly window and breakpoints can be set on the ROM code Compiler Assembler Linker VisualDSP 5 0 Update 8 automatically links against the ROM content For more information on how this works please see the associated FAQ http ez analog com docs DOC 1594 ADSP BF592 System Services and Device Driver Support The following System Services and Device Driver support are provided for the ADSP BF592 Device Drivers SPI SPORT TWI e PPI UART System Services DMA Interrupt Power Timer e Flag Ports VisualDSP 5 0 Update 8 Release Notes Rev 2 1 Page 8 12 System Services Device Driver Notes ADSP BF506F System Services and Device Driver Support The following System Services and Dev
88. art of the workaround for silicon anomaly 09000011 the time critical part of VDK has been mapped to seg_int_code instead of seg_pmco Customers using VDK with the ADSP 21371 and ADSP 21375 will see an increase in the size of the code that is required to be in internal memory VDK LDF Change for ADSP 21371 ADSP 21375 Customers that use VDK with the ADSP 21371 and ADSP 21375 must change their LDFs to link TMK 2137x dlb instead of TMK 213xx dlb SHARC Workaround Informational A new informational message is generated for PC relative jump instructions eal130 Constant offset in JUMP is not recommended JUMP to a label instead Th assembler has done this for you The assembler automatically changes PC relative jumps in order to prevent problems with the insertion of anomaly workaround code You can turn off this message by adding the following to assembly files which generate the warning message suppress 1130 New Type Header Files for all Processors The following header files have been added for all processors VisualDSP 5 0 Update 3 Release Notes Rev 1 3 Page 3 7 stdint h ANSI C99 standard conformant header file that defines various integer typedefs stdbool h ANSI C99 standard conformant header file that defines various boolean related macros services _types h Header file that defines various integer typedefs for use in system services code some boot kernels and examples adi_types h Includes stdint h stdbool h and d
89. ase Notes Rev 1 2 Page 4 4 Landscape LCD EZ Extender Update 4 also introduces initial support for the Landscape LCD EZ Extender which connects to the ADSP BF526 ADSP BF537 ADSP BF538 and ADSP BF548 EZ KIT Lites as well as other current and future EZ KIT Lites This extender board will allow customers to quickly interface a landscape LCD to their own custom board for evaluation This extender board also includes a touch screen capacitance touch push buttons and a scroll wheel Visit the website for more information http www analog com en embedded processing dsp blackfin BF EXTENDERLCD processors product html VisualDSP 5 0 Update 4 Release Notes Rev 1 2 Page 4 5 New System Services and Device Drivers The following are now supported by VisualDSP 5 0 NAND Flash Access A new physical interface driver PID is released for use with both the file system service and the USB mass storage device MSD class driver to enable NAND flash devices NFD to be accessible from both an embedded application and externally from a Host PC The NAND PID requires the use of a flash translation layer FTL to affect wear leveling and bad block management To this end an FTL has been licensed from HCC Embedded www hcc embedded com for evaluation use with EZ KIT Lite platforms only As such the FTL is distributed as a binary library only Usage beyond this requires a full license that can be obtained upon contacting HCC Embedded The installation of U
90. at and there are significant changes since Rev 0 1 neither version are included in Update 7 Please use the PDF version found at the link below This manual will be available in help format in a future update http www analog com en embedded processing dsp sharc adsp 21469 processors manuals resources html VisualDSP 5 0 Update 7 Release Notes Rev 1 0 Page 7 18 Critical Fixes Changes This section highlights significant changes due to software anomaly fixes or functional changes Online Help for Silicon Anomaly Tools Support The Online Help for the Silicon Anomaly Tools Support provides information per processor and per silicon revision in addition to the per family information already available For access see the Silicon Anomaly Tools Support Help topic as follows Help gt Contents gt Graphical Environment gt Silicon Anomaly Support gt Silicon Anomaly Tools Support Then select SHARC or Blackfin and follow the links for the specific processor and silicon revision Specific processor and silicon revision support is not available for TigerSHARC processors Blackfin Init Code Examples for Multi DXE Boot Streams were added for the ADSP BF526 EZ Board ADSP BF527 EZ KIT Lite and ADSP BF548 EZ KIT Lite evaluation systems See Boot Management in the System Reset and Booting chapter of the HRM Peripheral Simulation The simulator now provides support for SPORT peripherals including SPORT DMA for the
91. at full USB 1 1 or high USB 2 0 speed If the connection speed is not known an integral multiple of 512 can always be used Silicon Anomaly 05000460 ADSP BF52x ADSP BF54x USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled When multiple USB DMA Mode 1 channels are enabled and active at the same time one of the channel s DMA Address registers may be corrupted resulting in either DMA hang or data corruption Workaround Use DMA Mode 0 if the application requires multiple USB DMA channels to be concurrently enabled This is not implemented in the HDRC in VisualDSP 5 0 Update 7 Applications need to serialize their endpoint transfers ensuring only one active USB DMA in the system at any one time Silicon Anomaly 05000463 ADSP BF54x USB DMA Receive data corruption USB DMA Rx data corruption is observed when the USB buffer destination is in L1 or L2 memory and another peripheral s DMA buffers e g SPORT are also in L1 or L2 memory spaces and are accessed at the same time as the USB DMA is accessing its buffer Workaround No workaround exists in the driver The application developer needs to manage buffers such that when multiple peripherals are used with buffers in L1 or L2 USB buffers are placed in L3 or vice versa Silicon Anomaly 05000464 ADSP BF54x USB DMA Transmit DMA hang USB Transmit DMA may hang when the USB buffer is located in L1 or L2 memory and another peripheral e g
92. ating point operations addition subtraction multiplication and division have been extensively modified to improve their run time performance decrease code size and improve the accuracy of their results As a result of these modifications there may be minor discrepancies with results produced from previous releases of VisualDSP Assembler Processing of Anomaly Options The Blackfin and SHARC assembler method for processing command line anomaly options via the anomaly switches has been updated to be more consistent and robust Specifically the al 1 and none options can now be used with all four switches anomaly detect no anomaly detect anomaly workaround no anomaly workaround In addition these options a11 amp none are processed first so that users can easily control which anomaly IDs are being detected worked around by using them in conjunction with anomaly IDs For example anomaly detect none 05000227 which is the same as anomaly detect 05000227 none will only detect anomaly 05000227 and ignore all other anomaly IDs that may normally be detected NOTE In this example default actions will still be taken for workarounds as no workaround switches were present to over ride that behavior Finally by using the verbose option v users can see the actions being performed by the assembler for anomaly processing under the new Anomaly Actions section TAR42009 526 Audio_Loopback dpj ran and te
93. avoid prefetch CRC error For the ADSP BF54x ADSP BF52x and the ADSP BF54xM the loader stream will be appended with 256 bytes of data This is because the boot kernel uses a prefetch mechanism and while processing one 256 block of data it will fetch in the next 256 byte block of data Padding the loader stream with an additional 256 bytes at the very end ensures that the 256 byte block of data following the final block of the loader stream is programmed and the error correction parity data is written Appending this block prevents the boot from failing at the very end of the boot cycle as data will be fetched although never actually required and it will have valid ECC parity data resulting in the successful completion of the boot Coexistence of NAND Boot and File System Support The ADI file system service FSS provides support for the NAND flash device NFD to be formatted as a file system and leverages a flash translation layer FTL to provide wear leveling and bad block management To cater for both NAND boot and FSS support the FTL is instructed to manage only a portion of the NFD beyond a specified reserved area at the beginning of the NAND array This reserved area starting from block O is provided for NAND boot purposes The size of the reserved area is determined upon format and the following examples are provided to format the NFD as a FAT 16 volume SADI_DSP Blackfin Examples ADSP BF548 EZ KIT Lite Services Fil System NAND NandFo
94. bug Environment IDDE select Help gt About VisualDSP Installing the Update Follow the instructions below for installing this update Please note that since VisualDSP supports having multiple instances installed on a single system See the Cloning VisualDSP section below for more information 9 Use the Start Menu to navigate to VisualDSP Maintain this installation By default this is at Start Menu gt All Programs gt Analog Devices gt VisualDSP 5 0 10 Select Go to the Analog Devices website and click Next This will open a window in your web browser 11 Select the appropriate Processor Software Tools Upgrades to match your processor 12 Select and download the desired update VisualDSP 5 0_Update7 vdu to your hard drive 13 Again use the Start Menu to navigate to VisualDSP Maintain this installation 14 Select Apply a downloaded Update and click Next 15 Browse for the downloaded Update file VisualDSP 5 0_Update7 vdu and click Next 16 Follow the on screen prompts to complete installation of this Update Cloning VisualDSP VisualDSP supports cloning of an existing installation A clone of an installation creates a new instance of a product from an existing installation rather than from a CD or web software distribution The use of clones allows you to maintain multiple versions of VisualDSP on the same PC at different update levels and provides a risk free way to test new updat
95. cess allowed supervisor mode define CPLB LISRAM P 5 0 SRAM mapped in Ll O SRAM not mapped to L1 define CPLB DAOACC P 6 O access allowed from either DAG l access from DAGO only e define CPLB DIRTY P 7 l dirty O clean define CPLB_L1 CHBL P 12 O non cacheable in L1 l cacheable in L1 DH define CPLB WT P 14 O write back l write through The new macros added to def LPblackfin h for use by non ADSP BF535 parts are H define CPLB PORTPRIO P 9 O low priority port 1 high priority port define CPLB LRUPRIO P 8 O can be replaced by any line l priority for non replacement define CPLB_ USER WR_P 3 O no write access O write access allowed user mode define CPLB_SUPV WR PA O no write access O write access allowed supervisor mode e define CPLB DIRTY P 7 l dirty O clean define CPLB_L1 CHBL P 12 O non cacheable in L1 l cacheable in L1 DH define CPLB WT P 14 O write back l write through o define CPLB L1 AOW P 15 0 do not allocate cache lines on write through writes 1 allocate cache lines on write through writes Applications that contain their own local definitions of these macros may encounter compiler warning oc0047 D warning incompatible redefinition of macro if the definition does not match the ones given above Presuming that the application s local definition is for the same p
96. ckfin Processor Support The Product Bulletin contains the list of new processors available at VisualDSP 5 0 Refer to the processor s data sheet and hardware reference manuals for information on system configuration peripherals registers and operating modes The following are new Blackfin processors e ADSP BF542 ADSP BF544 ADSP BF548 ADSP BF549 e ADSP BF522 ADSP BF525 ADSP BF527 Ignore any mention of the ADSP BF541 It does not exist but is reserved for future use and references to it may appear in some places VisualDSP 5 0 ADSP BF54x Known Limitations The following device drivers are not yet available e NAND e Mass Storage Host USB VisualDSP 5 0 ADSP BF52x Support Emulator support and the EZ KIT Lite6 debug agent are provided for the ADSP BF52x parts VisualDSP 5 0 provides the tools required to build and debug ADSP BF52x code The ADSP BF522 ADSP BF525 ADSP BF527 Blackfin Embedded Processor Preliminary Data Sheet is located here VisualDSP 5 0 Release Notes Page 4 htto www analog com processors blackfin technicalLibrary dataSheets html VisualDSP 5 0 ADSP BF52x Known Limitations These are the known limitations specific to the new Blackfin ADSP BF52x processors The System Service Libraries are not yet available The Device Driver Libraries are not yet available LwlIP support is not yet available ADSP BF527 EZ KIT Lite example set is not yet available The Blackfin ADSP BF52x Hardware Referenc
97. ct Release Bulletin 2 DOCUMENTATION dui A ld adas 2 LICENSING Uri A A AA AAA A dad AAA Ad A 2 ADI ELF DOCUMENTATION siii ii ds 2 Problem Repo dd Se See 3 Project Upper di N a 3 VisualDSP 5 0 dpj Projects Have New Format 3 Project Wizard Template Changes Blackfin coooococococcnncnononononnnnnnnnnnononarnnnnnnnnnnonnonnnnonanoss 3 Processor Specific Release Notes sssesssresesssseserererssssesrrerresssssserrreesrssssesrrerressssesrrereessssesenne 4 New Blackfin Processor Support 4 VisualDSP 5 0 ADSP BF54x Known Limitations cccccesessceceeeeessessnseceeeeeeseessesssaeeeeeeeens 4 VisualDSP 5 0 ADSP BF52x Support 4 VisualDSP 5 0 ADSP BF52x Known Limitations ccccesessceceeeeessesssseeeeeceescessessaeeeeeeeens 5 Compiler Release Notes ananena Te aria EIER ENEE EEN 5 Compiler Assumes Strong Alignment of Global Arrays TAR 22640 5 Simulator Release Notes a 5 Limitations Blackfire ii ias 5 System Services Release Notes Blackfin oococcconoooononncnoncnonnnonnnnnnnnnconcnnnnnonnnnnnnonanananonnnoss 7 Silicon Anomaly OS DOOR A AAA AA 7 SDH Driver Corrupts Directory Structures for Write Operations TAR 22464 7 adi_pwr_SetPowerMode Does Not Help Transition from SLEEP TAR 22518 7 File System Corruption When Number of Files Exceeds One Cluster TAR 33677 8 Additional System Service Library Documentation ccccconocoonnnnnnnnnnnnononnnnnnnnnonnnn
98. d by the swc switch New Assembler Directives Three new directives are available to control whether instructions will be compressed COMPRESS This directive indicates that all the following instructions in the source file should be compressed if possible It has no effect on sections that are not being assembled as short word Its effect is canceled by a NOCOMPRESS directive later in the source file NOCOMPRESS This directive indicates that all the following instructions in the source file should not be compressed Its effect is canceled by a COMPRESS directive later in the source file FORCECOMPRESS This directive causes the next instruction to be compressed if possible Has no effect on sections that are not being assembled as short word Only the immediately following assembly instruction is affected by this directive This directive overrides the effect of a previous NOCOMPRESS directive but only for this one instruction It can also override certain conservative assumptions normally made by the assembler such as when an immediate value is an expression containing a symbol in this case the assembler normally does not generate a compressed instruction because the ultimate value of the symbolic expression might not fit in the immediate field of the compressed instruction Note that COMPRESS and FORCECOMPRESS are advisory only e There is no guarantee that a particular instruction will be compressed eve
99. des incorrect ADSP BF52x BF54x Prior to VisualDSP 5 0 Update 8 the Blackfin loader wrote incorrect DMA codes for NAND boot to the headers The NAND boot DMA codes are fixed in VisualDSP 5 0 Update 8 There is no longer a need to have the following additional options in your projects to get a compliant boot stream For the ADSP BF54x processors the workaround is to add the following switches to the additional options width 16 dmawidth 32 For the ADSP BF52x processors the workaround is to add the following switches to the additional options width 16 dmawidth 16 VisualDSP 5 0 Update 8 Release Notes Rev 2 1 Page 8 19 TAR 43683 Watchdog Timer Use with the Emulator ADSP 2148x The emulator does not automatically disable the Watchdog Timer upon hitting a breakpoint This could cause an exception when single stepping or resuming The user should disable the Watchdog Timer before debugging their code TAR 43781 Behavior of w and misra is inconsistent Prior to VisualDSP 5 0 Update 8 the compilers various MISRA C options didn t always conflict with other options that are incompatible when building with MISRA C checking enabled For example building with w disable warnings switch should cause an error but prior to Update 8 it didn t if it was used before the options to enable MISRA C on the command line This means that it is possible that some project will hit this error when built with Update 8 that didn t previously I
100. do not need to take any action other than simply linking with the appropriate System Services library as usual Users of the System Services do not need to include the file sys 05000311 h nor do they need to use the FIO_ANOM_0311_XXX macros unless they are accessing the flag MMRs directly See below Noteworthy VisualDSP 4 5 Update Changes 05 00 0311 section for further details SDH Driver Corrupts Directory Structures for Write Operations TAR 33464 The Secure Digital Host SDH driver is currently only cleared for read only access to SD cards inserted into the SD slot on the ADSP BF548 EZ KIT Lite development board Note This problem has been identified as a symptom of anomaly 05 00 0340 that is planned to be fixed in Rev 0 1 silicon adi_pwr_SetPowerMode Does Not Help Transition from SLEEP TAR 33518 The Blackfin System Services power management function adi_pwr_SetPowerMode does not currently support a transition from SLEEP or DEEP SLEEP into any other mode Upon wakeup from SLEEP or DEEP SLEEP a call to ad _pwr_SetPowerMode will fail The function was not written to support either of these transitions is because upon wakeup the processor transitions automatically from SLEEP or DEEP SLEEP into the FULL_ON or ACTIVE mode depending on the status of the BYPASS bit so it was assumed that this function call was not necessary This assumption was correct with regard to the transition from DEEP SLEEP But the proble
101. e 2 e ADSP BF522 silicon revision 0 0 e ADSP BF524 silicon revision 0 0 e ADSP BF526 silicon revision 0 0 Please note that the ADSP BF522 processor supported in VisualDSP 5 0 has been renamed as the ADSP BF523 The following are newly supported silicon revisions to existing Blackfin processors with Update 2 e ADSP BF523 silicon revision 0 1 e ADSP BF525 silicon revision 0 1 e ADSP BF527 silicon revision 0 1 There are no new silicon revisions to existing SHARC or TigerSHARC processors with Update 2 New Emulation Support The following emulation features are now supported by VisualDSP 5 0 Support for the ADSP BF522 BF524 and BF526 processors Please note that the ADSP BF522 processor supported in VisualDSP 5 0 has been renamed as the ADSP BF523 New System Services and Device Drivers The following are now supported by VisualDSP 5 0 Initial System Services Library support for the ADSP BF522 BF524 and BF526 processors Please note that the ADSP BF522 processor supported in VisualDSP 5 0 has been renamed as the ADSP BF523 VisualDSP 5 0 Update 2 Release Notes Rev 1 1 Page 2 3 New Examples LCD VisualDSP 5 0 Update 2 includes a new LCD example to demonstrate use of the LCD supplied on the ADSP BF527 EZ KIT Lite evaluation system lt can be found in the following directory Blackfin Examples ADSP BF527 EZ KIT Lite drivers LCD File System VisualDSP 5 0 Update 2 now includes a File Sys
102. e 7 Release Notes Rev 1 0 AD1939 C Block Based Talkthru 192kHz AD1939 C Block Based Talkthru 48 or 96 kHz AD1939 C Sample Based Talkthru 192kHz AD1939 C Sample Based Talkthru 48 or 96 kHz AD1939 I2S C Sample Based Talkthru EZ Extender 21469 AD1939 Sample Based Talkthru to Analog TalkThru with SRC Page 7 9 New System Services and Device Drivers The following are now supported by VisualDSP 5 0 File System Service for ADSP BF518F EZ Board The File System Service FSS has been expanded in Update 7 to support the Removable Storage Interface RSI on the ADSP BF518F EZ Board evaluation System Blackfin Examples ADSP BF518F EZ Board Services File System RSI eMMCFormat Blackfin Examples ADSP BF518F EZ Board Services File System VDK shell browser RamDisk FSS for ADSP BF53x BF561 EZ KIT Lites The File System Service has been expanded in Update 7 to support the ADSP BF533 ADSP BF537 ADSP BF538 and ADSP BF561 EZ KIT Lite evaluation systems Full support is provided for accessing a RAM disk by using the following driver Blackfin lib src drivers pid ramdisk adi_ramdisk c This driver is included in the driver libraries for ADSP BF533 ADSP BF537 ADSP BF538 and ADSP BF561 Examples for these processors are lackfin Examples ADSP BF533 EZ KIT Lite Services File System RamDiskAccess lackfin Examples ADSP BF533 EZ KIT Lite Services File System VDK shell browser lackfin Examples ADSP BF537 EZ KIT Lite S
103. e Autobaud Examples VisualDSP 5 0 Update 3 includes new examples to demonstrate use of the UART device driver in Autobaud mode supplied on the ADSP BF527 and ADSP BF548 EZ KIT Lite evaluation systems They can be found in the following directory Blackfin Examples ADSP BF527 Blackfin Examples ADSP BF548 EZ KIT site drivers UART Autobaud EZ KIT site drivers UART Autobaud VisualDSP 5 0 Update 3 Release Notes Rev 1 3 Page 3 6 Critical Fixes Changes This section highlights significant changes due to software anomaly fixes or functional changes Use Linker Elimination Options for ADSP 21371 ADSP 21375 The workaround for silicon anomaly 09000011 may generate unused assembly code To avoid linking this unused assembly code turn on linker elimination Select Project Project Options from the VisualDSP menu Select Link Elimination Check the box Eliminate unused objects Click OK E KS Customized Linker Description Files LDFs Change for ADSP 21371 ADSP 21375 Customers using the ADSP 21371 and ADSP 21375 that have non default customized LDFs may need to make a modification to their LDFs Ifthe workaround for silicon anomaly 09000011 is required trampoline code see definition in Silicon Anomaly Workarounds is placed in section seg_int_code If not already done the section seg_int_code should be mapped to internal memory VDK Internal Memory Code Size Increase for ADSP 21371 ADSP 21375 As p
104. e Manuals are not included in VisualDSP 5 0 e No online help for the ADSP BF52x Hardware Reference Manuals Compiler Release Notes Compiler Assumes Strong Alignment of Global Arrays TAR 33540 For performance reasons the compiler explicitly aligns arrays at global scope which allows the compiler to vectorize accesses to the array For example char glob array BYTECOUNT data aligned on a 4 byte boundary The compiler assumes that externally defined arrays will also be aligned in this manner extern char ext_array compiler assumes aligned on a 4 byte boundary If such arrays are defined in other C files this will be the case If however you define such arrays in assembly source you must ensure that they are suitably aligned otherwise run time exceptions are possible For example GLOBAL _unsafe array TYPE unsafe array STT OBJECT BYTE unsafe array 100 no alignment misaligned access possible ALIGN 4 GLOBAL safe array TYPE safe array STT OBJECT BYTE safe array 1001 4 byte aligned access is safe Simulator Release Notes Limitations Blackfin The following is a list of supported peripherals in the Blackfin simulators VisualDSP 5 0 Release Notes Page 5 Core Peripherals All Blackfin Processors Data Cache 8 SRAM Memory Instruction Cache amp SRAM Memory Event Interrupt Controller Registers Core Timer Registers Trace Buffer Registers Watchpoint C
105. e Updates iia A AR 3 3 Cloning VisualDS PF n ere a 3 3 D finiti n ee EE EE 3 4 TAR Tools Anomaly Reference Number 3 4 New Hardware SUppolt neninn kanet nyia E a e aae E 3 5 New Processors and Revisions SUPpO Euviiionn iia di 3 5 New System Services and Device Drivers 3 5 AA eegne tee EES 3 6 ADSP BF527 EZ KIT Lite Audio Loopback Examples 3 6 ADSP BF527 and ADSP BF548 EZ KIT Lite Autobaud Examples 3 6 Critical PINGS CANTES A A A ds 3 7 Use Linker Elimination Options for ADSP 21371 ADSP 21375 cccccccsscccsscecssseeesseeeesseeees 3 7 Customized Linker Description Files LDFs Change for ADSP 21371 ADSP 21375 3 7 VDK Internal Memory Code Size Increase for ADSP 21371 ADSP 21375 ss snssssesse1ss0e00 3 7 VDK LDF Change for ADSP 21371 ADSP 21375 csccesscesssesseecssecsseceeeeeseeeeseecsseceeeseeeeeseees 3 7 SHARC Workaround Intormational 3 7 New Type Header Files for all Processors 3 7 Boot Code Sources Available for ADSP BF52x and ADSP BF54X ooooccccococcccnoconnnnncconncnonnonnnos 3 8 Changes to Blackfin Idr Source Tree nnsnnssssosnseseesessssesereesesssseseeererssssssereereesesssseereeesessssene 3 8 New Blackfin ROM Header API iii A a cota 3 8 Changes to Support MISRA Technical Corrigendum 1 3 9 Ability to Suppress all MISRA Rules Checkng 3 10 TAR 35448 MCMEN Defined in ADSP BF54x Definition Header Files 3 10 TAR 34699 EBIU_AMGCTL Bit Macros in ADSP BF54x Definition He
106. e exhibits this problem when built in release mode VisualDSP 5 0 Update 5 Release Notes Rev 1 8 Page 5 11 VisualDSP 5 0 Update 5 Release Notes Rev 1 8 Page 5 12 TAR 39756 Some examples cause hardware error BF548 NAND format example causes hardware error When building and running the ADSP BF548 NAND format example Blackfin Examples ADSP BF548 EZ KIT Lite Services File System NAND NandFormat for the first time a hardware error interrupt may occur This may also occur with other examples This is a configuration issue To resolve this problem change the configuration from Debug to Release rebuild the project and the example will run successfully After the first successful run the configuration may be returned to Debug and the example will continue to run successfully VisualDSP 5 0 Update 5 Release Notes Rev 1 8 Page 5 13 Limitations This section highlights known significant limitations ADSP BF51x Silicon Revision Support For the ADSP BF51x only use the silicon revision 0 0 Silicon revisions none and any are not supported in Update 5 Attempts to use none or any for ADSP BF51x in Update 5 will result in link time errors relating to MEM_L1_CODE OTP Boot Preliminary work for OTP Boot is in Update 5 This feature will be available for use in a future Update VisualDSP 5 0 Update 5 Release Notes Rev 1 8 Page 5 14 Silicon Anomaly Workarounds The file System ArchDef BLACKFIN ED
107. e functions the following restriction on their use of external data has been imposed When running on an ADSP 21367 ADSP 21368 ADSP 21369 ADSP 21371 or ADSP 21375 processor both the filter coefficients and the delay line must not be allocated in external memory otherwise the function can generate an incorrect set of results This is because in a dual data move instruction the hardware does not support both memory accesses being to external memory Therefore ensure that the filter coefficients or the delay line or optionally both are allocated in internal memory when running on one of the ADSP 213xx processors specified above Changes have been made to the VisualDSP 5 0 Run Time Library Manual for SHARC Processors to document this restriction TAR 39783 Misaligned address violation BF548 Getting Started Examples misaligned address violation Using the section C C compiler switch or Hpragma default_section to move alldata or constdata to a non default memory section may cause a data access misaligned address violation run time exception The compiler generated assembly code is not always correctly aligning the non default section which the data is placed into The use of these methods for placing alldata and constdata need to be avoided to workaround this problem Alternate placement can be performed in the LDF The ADSP BF548 Blackfin Examples ADSP BF548 EZ KIT Lite Getting Started Examples Example_2 exampl
108. e of DMA in the respective direction or a non zero value to enable it The default values if none are supplied are VisualDSP 5 0 Update 6 Release Notes Rev 1 3 Page 6 18 USE_RX_DMA 1 and USE_TX_DMA 0 This combination is chosen to provide the best performance for the bulk loopback examples VisualDSP 5 0 Update 6 Release Notes Rev 1 3 Page 6 19 Critical Fixes Changes This section highlights significant changes due to software anomaly fixes or functional changes ADSP BF51x any none 0 0 Support Revision any and none application builds failed to link in Update 5 as these revisions use the revision 0 1 memory map in the default and generated LDFs The Update 6 linker is modified to correctly check for the revision 0 1 memory map so revisions any and none no longer fail This linker change means that applications built for revision 0 0 are built with the linker nomemcheck switch This is automatically applied by the compiler driver ccblkfn when building for ADSP BF51x processors revision 0 0 The linker will now issue the following warning when building for ADSP BF518 parts and revision 0 0 Warning 112280 The ADSP BF518 si revision 0 0 has been deprecated use nomemcheck to suppress error el2011 This warning is issued even when nomemcheck is used While this message says that revision 0 0 has been deprecated that is not currently the case The warning is not issued for builds that target ADSP BF512 or ADSP BF516 b
109. e provided in Update 3 of VisualDSP 5 0 No ADSP BF523 BF524 Startup Wizard Support TAR 35164 When creating a new project for either the ADSP BF523 or ADSP BF524 the startup code page in the project wizard does not appear To avoid this problem create a project for the ADSP BF527 instead of ADSP BF523 or a project for the ADSP BF526 instead of the ADSP BF524 Full processor support will be available in Update 3 VisualDSP 5 0 Update 2 Release Notes Rev 1 1 Page 2 6 Silicon Anomaly Workarounds ADSP BF5xx Silicon Anomaly 05 00 0323 Erroneous GPIO Flag Pin Operations under Specific Sequences anomaly workarounds support has been added Include file sys 05000323 h is now supplied with VisualDSP 5 0 It contains a group of macros for reading and writing MMRs applicable to this anomaly if the anomaly applies for the current value of the silicon revision of your target these macros will ensure that the read or write is safe against anomaly 05 00 0323 When building for parts and silicon revisions that require the anomaly 05 00 0323 workaround the macro WORKAROUND_FLAGS_MMR_ANOM_323 is defined at compile assemble and link stages To enable the workaround manually you can define use the D WORKAROUND_FLAGS_MMR_ANOM_323 switch See comments in the new file lt VisualDSP 5 0 Install gt Blackfin include sys 05000323 h for further details ADSP BF5xx Silicon Anomaly 05 00 0371 Possible RETS Register Corruption when Sub
110. ed For example define ONE 1 define ANOTHER ONE ONE This violates rule 19 4 even though when expanded will result as the constant 1 The example is corrected by parenthesizing ONE in the definition of ANOTHER_ONE VisualDSP 5 0 Update 5 Release Notes Rev 1 8 Page 5 10 TAR 38060 ADSP BF52x Macros Removed The NONGPIO_SLEW PORTF_SLEW PORTG_SLEW and PORTH_SLEW macros previously defined by including the defBF52x h and cdefBF52x h headers have been removed in Update 5 They should not be used Any application source that contains them will need to be changed TAR 37863 Run Time Library uses dual data move Some run time library functions use dual data move instructions 213xx Page 3 78 of the ADSP 21368 SHARC Processor Hardware Reference manual which includes the ADSP 21367 ADSP 21369 ADSP 21371 and ADSP 21375 documents some restrictions with accessing external memory One of these restrictions is that in a dual data move instruction both accesses should not be to external memory This restriction is not observed by some functions in the run time library in particular those functions that operate on arrays and vectors that are allocated in Program Memory PM This issue has been resolved in Update 5 apart from the biquad fir fir_decima fir_interp and iir filter functions Addressing the issue in the filter functions would have a severe impact on their performance and so rather than modifying th
111. ed driver documentation is to be found in Blackfin doc drivers keypad adi_adp5520 pdf Blackfin doc drivers Touchscreen adi_ad7879 pdf Blackfin doc drivers lcd sharp adi_1q035qldh02 pdf Note that the LCD driver currently only supports using the CPLD LCD in RGB888 data mode 24 bits per pixel Example projects using the new and modified drivers are supplied in the following folders Blackfin Examples ADSP BF527 EZ KIT Lite Drivers Keypad ADP5520 Blackfin Examples ADSP BF527 EZ KIT Lite Drivers TouchScreen AD7879 1 Blackfin Examples ADSP BF527 EZ KIT Lite Drivers LCD LQ035Q1DH02 Note that these three examples are for Revision 2 2 and later of the ADSP BF527 EZ KIT Lite only and that the projects in the LCD and touchscreen keypad folders are for revisions prior to 2 2 In addition the example project in the following directory is only for revisions prior to 2 2 Blackfin Examples Landscape LCD EZ EXTENDER LCD ColorBarDisplay ADSP BF527 LAN9218 Memory DMA based driver support for ADSP BF548 Platform e Memory DMA based LAN9218 driver has been added This is a separate driver from that of programmed I O variant Applications that intend to use memory DMA driver has to link with liblan9218bf548_dma dlb e By default this driver uses MDMA_STREAM2 for both transmit and receive operations e MDMA based driver operates asynchronously and reduces the processor loading considerably An app
112. ed on wrong algorithm disable_data_cache does not work Incorrect macro names for HOSTDP masks in BF52x def header adi_pwr_SetFreq locks up sometimes on ASDP BF561 Add command to sense the PERIOD register for GP timers Add command to sense GP timer period SDH driver corrupts directory structures for write operations Note This problem has been identified as a symptom of anomaly 05 00 0340 that is planned to be fixed in Rev 0 1 silicon pwr mgmt to facilitate transition from SLEEP File System Corruption when number of files exceeds 1 cluster ETHARP_ALWAYS_INSERT option is deprecated in IwIP Multiple network interface problem lwip send function returns bytes sent but sends only 64K max getsockopt with SO_ERROR does not return error INETD example should not set the user_data_ptr in the header Corrupted ADSP BF537 EZ KIT Lite in Blackfin Examples patch available ADSP BF537 EZ KIT Lite LAN Host FILESERVER FileServer dsp Intermittent USB connectivity on ADSP BF548 EZ KIT Lite PCH fails with cc0219 on Vista VisualDSP disconnect if Sport DMA Addressing debug window open Incorrect display of instructions in external memory on Sharc Value of float pointers displayed in unexpected format Increase in printf footprint Thread safe time library ctime problem SIG_MTM to be defined for ADSP 21362 3 4 5 6 MTM registers missing from cdef21364 h Functions with pragma weak_entry can be inlined Use of setimp longimp incompatible with comp
113. efines other float and char typedefs For use in generic code that requires a complete set of typedefs such as MISRA conformant applications Boot Code Sources Available for ADSP BF52x and ADSP BF54x The Boot Code Sources are now available for the ADSP BF52x and ADSP BF54x and can be found in Blackfin Idr Boot ROM Changes to Blackfin Idr Source Tree Prior to VisualDSP 5 0 Update 3 there was a single set of Blackfin Boot Kernel sources With the introduction of the ADSP BF52x and ADSPBF54x processors a next generation Boot Kernel was written VisualDSP 5 0 Update 3 contains the sources for both Two new folders were created within Boot ROM src bk_ad00 contains the legacy Boot Kernel sources for the ADSP BF53x and ADSP BF561 bk_ad03 contains the latest generation Boot Kernel sources versions 03 and 02 New Blackfin ROM Header API To better support the on chip Boot ROM and L1 ROM the ROM Header API is now defined in bfrom h Location lt install dir gt Blackfin include bfrom h C Versions of Initialization Code Update 3 includes initialization code examples for the ADSP BF52x and ADSP BF54x processor written in C language Unlike former Blackfin derivatives such as ADSP BF53x and ADSP BF561 devices the new ADSP BF52x and ADSP BF54x processors initialization code concept is compliant to C language calling conventions Therefore the user has the choice to implement initialization codes in C or assembly language The
114. efining the CCLK vs VLEV relationship see table 13 Core Clock Requirements 500 MHz 533 MHz and 600 MHz Models in Revision E of the ADSP BF531 2 3 datasheet as a general guideline but note that the ADSP BF54X is NOT guaranteed for these same values Define an array of ADI_PWR_NUM_VLEVS elements defined in the API header file adi_pwr h of type unsigned 32 bit integer u32 which specifies the maximum core clock frequency for the associated voltage level as shown below static u32 pwr_cclk vlev table ADI_PWR_NUM VLEVS ADI PWR _VLEV_085 250 ADI_PWR_VLEV_090 334 ADI PWR _VLEV_095 334 ADI PWR_VLEV 100 400 ADI _PWR_VLEV_105 400 ADI PWR_VLEV 110 444 ADI _PWR_VLEV_115 444 ADI _PWR_VLEV_120 500 ADI PWR_VLEV_125 533 ADI_PWR_VLEV_130 533 VisualDSP 5 0 Update 3 Release Notes Rev 1 3 Page 3 13 Create the command pair table to include the command ADI_PWR_CMD_SET_CCLK_TABLE followed by a pointer to the array as shown below ADI PWR COMMAND PAIR PowerlnitTable ADI PWR CMD SET PROC VARIANT void ADI PWR_PROC_BF549SBBC1533 ADI PWR CMD SET PACKAGE void ADI_ PWR PACKAGE MBGA ADI PWR CMD SET VDDEXT void ADI PWR VDDEXT 330 ADI PWR CMD SET CLKIN void 25 ADI PWR CMD SET CCLK TABLE void zi pwr cclk vlev table ADI
115. els of each interrupt to suit your application requirements This will change the number of additional secondary handlers according to your existing interrupt priority assignments To change the priority level of an interrupt add the following statement in your application code ahead of enabling the USB driver using the ADI_USB_ENABLE_USB Command For example to change the priority of the ADI_INT_USB_INTO interrupt to IVG 10 adi_int SICSetIVG ADI_INT_USB_ INTO 10 To assist you in this note that each of the above interrupts are assigned to handle the following events ADI_INT_USB_INTO Data receive events to Blackfin ADI_INT_USB_INT1 Data transmission events from Blackfin ADI_INT_USB_INT2 Connection events ADI_INT_USB_DMAINT DMA buffer completion events Better Device Detection More USB memory devices can now be detected including some card reader devices single cards only multiple cards are outside the scope of the hardware and low cost USB flash drives Device detection can also be achieved at higher core clock frequencies up to 600 MHz on the ADSP BF548 processor Hot plug support is greatly improved making the removal and insertion of USB memory devices quick and reliable A consequence of this is that it may take slightly longer for the device mode applications to be recognized by the host PC Extensibility Support has been added so that more complex device classes can be implemented
116. emulator This emulator can be used with all Blackfin processors Please note that the Background Telemetry Channel BTC and statistical profiling are not supported with this emulator Please refer to the ICE 100B manual included in Update 7 for more information New Evaluation Board Support Support has been added for the following new evaluation boards ADSP 21469 EZ Board Update 7 introduces official support for the ADSP 21469 EZ Board The Power On Self Test POST and Flash Programmer are provided with this release In addition the following examples are provided 69 EZ Board 21469 AD1939 C Block Based Talkthru 192kHz 69 EZ Board 21469 AD1939 C Block Based Talkthru 48 or 96 kHz 69 EZ Board 21469 AD1939 C Sample Based Talkthru 192kHz 69 EZ Board 21469 AD1939 C Block Based Talkthru 48 or 96 kHz 69 EZ Board 21469 I2S C Block Based Talkthru 69 EZ Board AnalogInDigitalOut 69 EZ Board Background Telemetry 69 EZ Board Block Based SPDIF Talk Thru C 69 EZ Board Core Timer C 69 EZ Board Flash Programmer 69 EZ Board Power On Self Test 69 EZ Board Primes C from External Memory 69 EZ Board SPDIF to Analog TalkThru with SRC C 69 EZ Board SPDIFToAnalogTalkThru C 69 EZ Board UART echo back C 14xxlExampleslADSEP 14xxlExampleslADSE l4xx Examples ADSF l4xx Examples ADSF l4xx Examples ADSF l4xx Examples ADSF l4xx Examples ADSF l4xx Examples ADSF l4xx Examples ADSF l4xx Examples ADSF l4xx Examples ADSF l4xx Examples ADSF
117. erals e DDR2 controller e DICH e Link Ports e MediaLB e Programmable Clock Generator e Shared Memory e S PDIF e SPI e SPORTS e SRC e TWI e UART TAR 40528 SEGMENT assembler directive may behave incorrectly The SEGMENT and SECTION directives behave differently with the assembler The SEGMENT defaults to normal word code whereas the SECTION defaults to whichever mode is enabled To avoid any issues it is best to use the SECTION assembler directive and not the SEGMENT assembler directive VisualDSP 5 0 Update 6 Release Notes Rev 1 3 Page 6 15 USB Stack Enhancements The ADI USB Stack has undergone a considerable overhaul and with Update 6 provision is made for a more robust and extensible solution to your USB needs Robustness Several issues have been addressed that were the cause of lock ups and data corruption particularly regarding the operation of the ADI specific Bulk transfer class driver With ADSP BF548 rev 0 1 and higher and ADSP BF52x rev 0 2 and higher the PHY calibration register is set upon reset to a factory defined default obtained from direct calibration of the specific part This calibration value may vary from part to part It is recommended that an application adds the following statements to the initialization code of their application include lt builtins h gt include lt sys platform h gt PA ST for rev 0 0 we need to calibrate the USB analog PHY ay if 0x00 pDSPID
118. ervices File System RamDiskAccess lackfin Examples ADSP BF537 EZ KIT Lite Services File System VDK shell browser lackfin Examples ADSP BF538F EZ KIT Lite Services File System RamDiskAccess lackfinlExampleslADSP BF538F EZ KIT Lite Services File System VDK shell browser lackfin Examples ADSP BF561 EZ KIT Lite Services File System RamDiskAccess lackfin Examples ADSP BF561 EZ KIT Lite Services File System VDK shell browser DD DD w w w D The RAM Disk driver can also be used with ADSP BF518 ADSP BF52x and ADSP BF54x processors but the above source file is required to be added to the project as it is not included in driver libraries for these processors Other Examples This section specifies new examples that are not specific to an evaluation board There are no new examples for this category in Update 7 VisualDSP 5 0 Update 7 Release Notes Rev 1 0 Page 7 10 Silicon Anomaly Workarounds Anomaly workaround information is available in the online help Select Help gt Contents gt Graphical Environment gt Silicon Anomaly Support gt Silicon Anomalies Tools Support and then click the appropriate processor series Silicon Anomalies 05000248 05000412 ADSP BF561 TESTSET Operation Forces Stall on the Other Core The 05000248 compiler workaround for uses of the TESTSET instruction has changed in Update 7 because it is now deemed necessary to have inte
119. es the new silicon revision 0 2 of the ADSP BF526 processor No examples needed updating ADSP BF527 EZ KIT Lite Rev 2 2 This release integrates support from the VisualDSP 5 0 ADSP BF506F EZ KIT release The following examples are provided Blackfin Examples ADSP BF527 EZ KIT Lite Drivers Keypad ADP5520 Blackfin Examples ADSP BF527 EZ KIT Lite Drivers LCD 1003501DH02 Blackfin Examples ADSP BF527 EZ KIT Lite Drivers TouchScreen AD7879 1 Please note that the Power On Self Test should be built under the debug and not the release configuration ADSP 21479 EZ Board This release integrates support from the VisualDSP 5 0 ADSP 21479 and ADSP 21489 EZ Boards release The following examples are provided 79 EZ Board 21479 AD1939 C Block Based Talkthru 192kHz 79 EZ Board 21479 AD1939 C Block Based Talkthru 48 or 96 kHz 79 EZ Board 21479 AD1939 C Sampled Based Talkthru 192 kHz 79 EZ Board 21479 AD1939 C Sampled Based Talkthru 48 or 96 kHz 79 EZ Board 21479 AD1939 I2S C Sampled Based Talkthru 79 EZ Board 256pointFFT 79 EZ Board 512pointFFT 79 EZ Board AnalogInDigitalout 79 EZ Board Background Telemetry 79 EZ Board Core Timer C 79 EZ Board Decimation Filter 79 EZ Board Flash Programmer 79 EZ Board Interpolation Filter 79 EZ Board Multichannel Filter Autolterate 79 EZ BoardWMultilteration Mode 79 EZ Board Power On Self Test 79 EZ BoardXRTC_Seconds Test 79 EZ Board SingleIteration Mode 79 EZ Board SPDIF to
120. es ADSE 13xx Examples ADSE 13xx Examples ADSE 13xx Examples ADSE 13xx Examples ADSE 13xx Examples ADSE 13xx Examples ADSE MNINNNNNNNNNNNN DN DN KH JH PL ZE TE P 32 ZE 3 HE ZK ZK FEI O MNINNNNNNNNNNNNN DN ADSP BF518F EZ Board Revision Update 7 introduces support for the ADSP BF518F EZ Board rev 1 0 This EZ Board includes the ADSP BF518F rev 0 1 with the revised memory map and National Semiconductor DP83848 PHY device For more information please refer to the ADSP BF518F EZ Board Evaluation System Manual ADSP BF526 EZ Board Revision Update 7 introduces support for the ADSP BF526 EZ Board rev 1 1 This EZ Board includes the ADSP BF526 rev 0 1 and the SSM2603 Audio Codec For more information please refer to the ADSP BF526 EZ Board Evaluation System Manual The following new example for use with the SSM2603 Audio Codec is provided Blackfin Examples ADSP BF526 EZ KIT Lite Drivers AudioCodec Audio_ Loopback Landscape LCD EZ EXTENDER Examples VisualDSP 5 0 Update 7 includes new Landscape LCD EZ Extender examples for the ADSP BF518F EZ Board ADSP BF526 EZ Board and ADSP BF527 EZ KIT Lite evaluation systems The following examples are provided Blackfin Examples Landscape LCD EZ Extender LCD ColorBarDisplay ADSP BF518 Blackfin Examples Landscape LCD EZ Extender LCD ColorBarDisplay ADSP BF526 Blackfin Examples Landscape LCD
121. es or patches To clone your existing installation of VisualDSP VisualDSP 5 0 Update 7 Release Notes Rev 1 0 Page 7 3 5 Go to Start gt Programs gt Analog Devices gt VisualDSP 5 0 or equivalent gt Maintain this Installation 6 Select Clone this Installation and click Next Optionally click Advanced to set the Start menu path 8 Enter the Clone install path and click Next x Definitions This section provides definitions for terminology relating to VisualDSP and this document TAR Tools Anomaly Report Tools Anomaly Report or TAR is used for tracking confirmed defect reports in VisualDSP Supported Operating Systems This section specifies changes in supported Operating Systems Windows Vista SP2 VisualDSP 5 0 Update 7 introduces support for Windows Vista SP2 without any new known issues Windows 7 VisualDSP 5 0 Update 7 introduces support for Windows 7 For more information please refer to the relevant FAQ on our new online forum Engineering Zone VisualDSP 5 0 Update 7 Release Notes Rev 1 0 Page 7 4 New Hardware Support VisualDSP updates often include support for new processors new silicon revisions for existing processors and new EZ KIT Lite EZ Board and EZ Extender evaluation systems In order to support these minor revisions are made to the tool chain and additional system services and device drivers need to be added This section describes the new support available in t
122. f an instruction making an access to an IOP register immediately follows another instruction that performs an access to external memory The result of the anomaly can be that he IOP register access may not occur correctly The assembler has new anomaly detect 09000021 switch for the ADSP 2137x processor series and anomaly detect 15000003 switch for the ADSP 214xx processor series The functionality of these switches is to detect an obvious IOP register access following any memory access When detected the assembler issues warning ea2541 These switches are disabled by default The compiler workaround for these anomalies inserts a NOP between a potential external memory access and a potential IOP register access By default the compiler assumes that any access to a memory location using a volatile pointer is an access of an IOP register unless it can determine and therefore check the physical address at compile time The compiler workaround is automatically enabled for parts and revisions that require it The compiler can be enabled manually using the workaround 09000021 or workaround 15000003 switched Corresponding no workaround switches have also been added A new compiler switch and two new built in functions have been added to allow users to configure the compilers support for these anomalies The new switch no assume vols are iops allows you to disable the compiler s default assumption that all volatiles are IOP accesses The new function
123. f that happens the correct action is to remove the conflicting options from the build options An example of the error that might be seen is cc3150 D error Option misra conflicts with option w The switches that conflict with MISRA C are W Wsuppress Wwarn SG enum is int implicit pointers warn protos decls weak Blackfin only option alttok TAR 41677 FFTs with dynamic scaling can overflow The FFT functions cfft_fr16 ifft_fr16 and rfft_fr16 were modified to ensure that suitably conditioned input data will not cause an overflow when dynamic scaling is selected The functions now use a threshold of 0 25 instead of 0 5 previously when deciding whether to apply scaling This may cause the functions to apply scaling more often than previously done However any additional scaling performed by the FFT functions will be reflected by a corresponding increase in the value of the block exponent that they return TAR 41829 defBF532 h SYSCR masks incorrect The macros definitions for BMODE_FLASH BMODE_SPIHOST and BMODE_SPIMEM in Blackfin include defBF532 h have been modified because they were incorrect The original incorrect macro definitions were define BMODE FLASH 0x0001 Use Boot ROM to load from 8 bit or 16 bit flash define BMODE SPIHOST 0x0002 Boot from SPIO host slave mode define BMODE SPIMEM 0x0003 Boot from serial SPI memory VisualDSP 5 0 Update 8 Release Notes Rev 2
124. fin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin Blackfin VisualDSP 5 0 Release Notes 31849 32823 32858 32904 32910 32939 33668 30796 22657 23285 27938 28150 28197 28404 28891 28902 28922 28975 29017 29087 29384 29605 29846 30494 31336 32024 32038 32067 32620 30349 31346 32725 30935 22930 28518 28558 28965 29525 30752 31869 31881 32864 32911 28099 29583 30628 Compiler Compiler Compiler Compiler Compiler Compiler Compiler Emulator Installation LDFGen LDFGen Linker Run Time Libraries Run Time Libraries Run Time Libraries Run Time Libraries Run Time Libraries Run Time Libraries Run Time Libraries Run Time Libraries Run Time Libraries Run Time Libraries Simulator Simulator Simulator The complex fract function csqu_fr16 doesn t work abs saturates even with no saturation Callee function doesn t truncate parameter to expected type K amp R C internal compiler error in peephole c 2387 Buffer overrun detected error message from linker Short names for video functions being defined with no builtins Fatal error in do_expr HPPCI ICE does not work under OEM Windows Vista Backslash causes problems for assembler property page Cannot export from VDK State History pane top bar Random license failure when bu
125. from source as follows 1 In the file SVDSP Blackfin lib src services int adi int module h where SVDSP represents the VisualDSP installation path add the instruction SP 60 immediately after the STARTFUNC Name entry point for both ADI_INT_ISR FUNCTIONandADI_INT EXC FUNCTION define ADI_INT_ISR FUNCTION Name 1IVG Nested __STARTFUNC Name SP 60 lt ADD THIS INSTRUCTION SP RO SP Pl define ADI INT EXC FUNCTION Name IVG Nested __STARTFUNC Name SP 60 lt ADD THIS INSTRUCTION SP RO SP Pl Also in the file SVDSP Blackfin lib src services int adi_int_module h the complementary stack modification must be made to the end of the handlers The SP 60 instruction must be inserted before the RTI in ADI_INT ISR EPILOG and before the RTX inADI_ INT EXC_EPILOG For example VisualDSP 5 0 Update 8 Release Notes Rev 2 1 Page 8 17 define ADI INT EXC EPILOG Nested unlink SP 12 SP 60 lt ADD THIS INSTRUCTION RTX NOP NOP NOP 3 Rebuild the DD SS library with these changes and use them instead of the prebuilt libraries distributed within VisualDSP For more information please contact processor tools support analog com Silicon Anomalies 05000456 05000460 05000465 ADSP BF522 4 6 rev 0 2 Due to silicon anomalies 05000456 05000460 and 05000465 on the ADSP BF52x BF5
126. g TXPKTRDY when AUTOSET is enabled If TXPKTRDY is set manually data will be sent on the bus but the last two bytes will be missing Workaround Do not mix concurrent DMA and core accesses to the USB TX endpoint FIFOs The HDRC driver uses DMA for all transfers and is not affected by this anomaly Silicon Anomaly 05000467 ADSP BF52x ADSP BF54x Possible USB RX Data Corruption When Control and Data EP FIFO s are accessed via the core USB received data may be corrupted while receiving data under the following conditions 1 Control and data USB endpoints are enabled 2 Data has been received at the control endpoint 3 Datais being received at the data endpoint while the processor core is reading data from the control endpoint Workaround Use DMA to read data from the streaming data endpoint FIFO The HDRC driver in VisualDSP Update 7 has this workaround VisualDSP 5 0 Update 7 Release Notes Rev 1 0 Page 7 17 ADSP 214xx Changes This section highlights significant changes due to software anomaly fixes or functional changes ADSP 214xx Interrupt Vectors Interrupt vector table cannot be in short word memory the processor requires that the Interrupt Vector Table IVT reside in normal word memory Ensure that the nw qualifier is used Please see the example below for TAR40528 TAR40528 Changes to legacy SEGMENT directive for SHARC parts with VISA support There has been a change in the SHARC assembler
127. g Timer Use with the Emulator ADSb 214gxvl 8 20 TAR 43781 Behavior of w and misra is nconsistent 8 20 TAR 41677 FFTs with dynamic scaling can overflow ccccononoonoccnnnncnonononnnnnnnnnnoncnnononnnnnnnnnnnnnnns 8 20 TAR 41829 defBF532 h SYSCR masks incorrect oooooooocccncccnononononnnnnnnnnnnnnnnnnnononnnnnnnnnnononnnnnnnnnnnnnnos 8 20 TAR 43849 SourceGenerator writes out files with LF endings not CRILE 8 21 TAR 43542 Init code example for ADSP BF506F EZ KIT Lite has incorrect EZ Board naming 8 21 TAR 44191 LDFs generated for ADSP BF52x si revision 0 0 parts causes link error li1271 8 21 Opening a prior VisualDSP release may cause bad generated CRTs in Update 8 0005 8 22 A O MA YENES A AS AA A dd 8 23 Tools Anomalies AddresS WEE 8 23 KNOWN Tools ANOMAli S cccccccccecssssssnsccecececsenssnnansececessessansausececuseesesseataeseceeeesessansanseeeeneeeseess 8 25 Software Anomalies Addressed REENEN 8 25 VisualDSP 5 0 Update 8 Release Notes Rev 2 1 Page 8 2 Nomenclature In the past VisualDSP updates were labeled by the month and year of their release In order to improve clarity updates are now numbered e g Update 1 Update 2 etc Release Notes These release notes subsume the release notes for previous updates Release notes for previous updates can be found at the end of this document Installation This update can only be installed on a previous VisualDSP 5
128. ge your license for VisualDSP software For users who purchase floating licenses the guide describes the VisualDSP Floating License Server Note The Licensing Guide does not describe versions of VisualDSP licensing prior to VisualDSP 5 0 For information about older versions refer to Help gt Contents gt Assistance gt Software License Management The VisualDSP License Installation Procedure is also available on the Analog Devices Web site on the Upgrades Archives page available at http www analog com processors tools updates ADI ELF Documentation If you have tools that consume the ELF object files produced by VisualDSP the following document will be of interest Most VisualDSP 5 0 users need not be concerned with this level of detail VisualDSP5_ 0 ADI_ELF_Changes pdf VisualDSP 5 0 Release Notes Page 2 The ADI ELF document covers the most recent changes in the ADI ELF since VisualDSP 4 5 was released Updated versions of the complete ADI ELF ABI specification general and processor specific are available from Customer Support by request Problem Reports Charts summarizing the problems fixed in this release and the known open problems are included at the end of this document Project Upgrades We recommend working with a copy of your existing applications when first upgrading to the VisualDSP 5 0 release The upgrade will change existing dpj projects and in some instances the Projec
129. get a linker error when building because there are two reserve commands in the same section VisualDSP 5 0 Update 8 Release Notes Rev 2 1 Page 8 21 The error issue looks like the following Error 111271 ALDFGen TAR ldf 252 Due to insufficient space or conflicts with other placement requirements in processor p0 command RESERVE bootLoader OxFF807FEF bootLoaderLength 0147FE58 1 has failed Total of 0x11 word s were not allocated For more details see linker_log xml in the output directory To avoid this issue modify the LDF template code for your part by adding the two lines indicated by a below don t include the though The files to modify are installed into folder System SystemBuilder CodeGenerators Startup Code Wizard LDFGen so for example to fix this issue for BF527 modify file System SystemBuilder CodeGenerators Startup Code Wizard LDFGen ADSP BF527 LDF XML file lt workaround for rev revisions 0 0 gt lt if dataa cache value false enabled true gt lt reserve symbol name bootLoader 0xFF807FEF length_symbol bootLoaderLength min size 0x11 gt lt if dataa cache gt lt workaround_for_rev gt Take care with this modification and perhaps save the original file first so that the change can be reverted if needed Opening a prior VisualDSP release may cause bad generated CRTs in Update 8 Running multiple versions of VisualDSP at the same
130. he XML files in the lt install dir 5 0 gt System ArchDef directory The list of register names and reset values are extracted from the XML block lt register reset definitions gt lt register reset definitions gt that is located within the XML files for that processor s EZ KIT Lite For the TigerSHARC processors the register resets are located in the ADSP TS resets xml files For the Blackfin and SHARC processors the register resets are located within the proc xml files In previous releases the only method for overriding the XML reset values for custom boards was to edit the system XML files directly If you had more than one custom board you needed to rename the XML file to a known processor name prior to use At VisualDSP 5 0 you no longer need to make edits to the XML register resets in the shipped versions or manage multiple boards by renaming files The new Custom Board Support includes a feature that enables you to specify register reset values for your custom boards in separate XML files with names and locations of your choice For details refer to Custom Board Support within Graphical Environment in the VisualDSP 5 0 online Help Noteworthy VisualDSP 4 5 Update Changes If you have kept current to the VisualDSP 4 5 2007 June update skip this section Incorrect Memory Mapping for ADSP 21375 TAR 31816 TAR 31816 Incorrect memory mapping for ADSP 21375 The memory map for the ADSP 21375 SHAR
131. he compiler does not currently avoid the placement of potentially problematic reads in the instruction following the target of a predicted not taken branch The runtime libraries and VDK support that is linked in when building for impacted parts and silicon revisions have been modified to avoid the anomaly The support for this anomaly workaround is incomplete The ADI components affected are Assembler e Assembler detection of silicon anomaly 05000428 is not enabled for silicon revision any any is intended to enable all workarounds for the processor The detection can be obtained by explicitly building with si revision 0 4 or si revision 0 5 In future updates detection for this anomaly will be enabled by default for any Compiler e The compiler will not ensure that the targets of predicted jumps are safe against the anomaly Runtime Libraries e The source code for memcpy does not work around the anomaly To solve this you can edit the code provided in the VisualDSP install in the file Blackfin lib src libc memcpy asm For more information see tools anomaly 39636 e The source code for zero_crossd does not work around the anomaly To solve this you can edit the code provided in the VisualDSP install in the file Blackfin lib src libdsp zero_crossd asm For more information see tools anomaly 39637 VDK e The code for the API PostMessage does not work around the anomaly To avoid hitting the anomaly place the variable tmk in L1
132. his update New Processors and Processor Revision Support This section lists new processors and processor revisions available in this update Refer to the data sheets and hardware reference manuals for information on system configuration peripherals registers and operating modes No new Blackfin SHARC or TigerSHARC processors are supported with Update 7 Update 7 also provides support for the following silicon revisions to existing Blackfin processors e ADSP BF522 silicon revision 0 2 e ADSP BF524 silicon revision 0 2 e ADSP BF526 silicon revision 0 2 No new silicon revisions to existing SHARC or TigerSHARC processors are supported with Update 7 Processor Revision Deprecation Support for the following processor support has been completely removed in Update 7 as the processor was never released e ADSP BF541 VisualDSP 5 0 Update 7 Release Notes Rev 1 0 Page 7 5 Boot ROM Code This section describes changes to the Boot ROM code New Boot ROM Code is available in Update 7 for the following processors e ADSP BF50x rev 0 0 Init Code This section describes the changes to the Init Code New Init Code is available in Update 7 for the following processors e ADSP BF50x rev 0 0 VisualDSP 5 0 Update 7 Release Notes Rev 1 0 Page 7 6 New Emulator Support Support has been added for the following new evaluation boards ICE 100B Update 7 introduces support for the new low cost ICE 100B USB bus powered
133. ice Driver support are provided for this release Device Drivers SPI SPORT TWI PPI RSI SDH UART Counter e Internal ADC adi_bf506fadc1 System Services e DMA DCB Interrupt Power e PWM Timer e Flag Ports e Semaphore e ACM ADC Controller Module ADSP BF50x PWM Service Because the ADSP BF50x has two identical PWMs the SSL PWM Service has been modified slightly to accommodate the two PWMs Special instructions for using the new PWM service can be found here Blackfin docs services PWM Service ADSP BF50x pdf ADSP BF527 Modifications This VisualDSP release contains new and modified device drivers to match the hardware changes made for Revision 2 2 of the ADSP BF527 EZ KIT Lite The new drivers support use of the keypad scanning feature of the ADP5520 multi function controller and the AD7879 1 touch screen controller The modified driver controls the Sharp LA03501DH02 LCD display connected via the EZ KIT s CPLD The header files for these drivers are Blackfin include drivers keypad adi_adp5520 h VisualDSP 5 0 Update 8 Release Notes Rev 2 1 Page 8 13 Blackfinlincludeldriversltouchscreenladi_ad7879 1 h Blackfin include drivers lcd sharp adi_1q035qldh02 h and their implementation files are Blackfin lib src drivers keypad adi_adp5520 c Blackfin lib src drivers touchscreen adi_ad7879 l c Blackfin lib src drivers lcd sharp adi_lq035qldh02 c New or updat
134. ilding using a floating license Cannot view defined static member variable LDFGen ignores multicore settings User corrupted VDK history data window can crash Idde Startup code LDF wizard doesn t warn when overwriting LDF file Additional include dirs from 3 0 or earlier project settings Show tabs now also show spaces Creating a new TCPIP project pops up message about replacing srcs VDSP not expanded when just building one file in a project Thread Types missing from Threads in VDK Status Window Go To in BTC Memory window causes Runtime Abnormal termination VDK Status window Event Bit display error Doubles not fully displayed when double size 64 Whole word replacement does not work with undercores Two elements allowed to be placed at the same location Trace window does not display all of its entries Expert Linker crashes when opening LDF file ADspStreamList Add methods don t work for BF561 C NMI interrupt handler does not end with an RTN msxml3 dll registration problems prevent install shared data locks etc need to be non cached Workaround comment incomplete in generated LDFs Cannot jump call expand PLIT C exception handling may not work with spilled sections Interrupt dispatcher does not include 05 00 0071 32 bit signed division wrong for inputs near INT_MIN min_fr1x16 and max_fr1x16 missing adi_core_b_enable unresolved in assembly CPLB Manager can cause double exception meminit support fails to for ZERO_INI
135. iler issues the required workaround sequence of code to avoid the errata for calls to the testset compiler built in function when the workaround is enabled This workaround is automatically enabled when building for parts and revisions impacted by the 05000412 anomaly or when workaround 05000412 is passed to the compiler The macro WORKAROUND_05000412 is defined when the workaround is enabled The assembler issues a detection warning ea5519 when a TESTSET instruction is not immediately preceded by an SSYNC required by the 05000412 errata workaround This detection warning is automatically enabled when building for parts and revisions impacted by the 05000412 anomaly or when anomaly detect 05000412 is passed to the assembler The macro __ ASM_DETECT_05000412 _ is defined when this anomaly detection is enabled Known limitations with this anomaly support e TAR40784 05000412 anomaly detection fails if TESTSET follows align Silicon Anomaly 05000426 ADSP BF5xx Speculative Instruction Fetches Can Cause Spurious Hardware Errors The anomaly occurs when there is an indirect jump or call through a pointer which may point to an invalid address on the opposite control flow of a conditional jump to the predicted taken path and ICPLBS are disabled The result of this is potentially spurious hardware errors Blackfin C C compiler VDK and run time libraries workarounds for anomaly 05000426 were added in VisualDSP 5 0 Update 5 In U
136. iler optimizations link error __memzero could not be resolved Halting single proc during MP run halts both processors Compiler fails using some library functions prefixed with std fp div lib doesn t work when compiling Inf NaN with ve value ADSP TS201 BTB not enabled by default in the boot process Page 16 TigerSHARC 32758 Run Time namespace std does not contain builtins Libraries TigerSHARC 32782 Run Time DSP real vector functions can raise FP exceptions Libraries TigerSHARC 27911 Simulator ADSP TS203 session displays the CLU registers VisualDSP 5 0 Release Notes Page 17
137. include the ADSP BF518F ADSP BF526 ADSP BF537 ADSP BF538F and ADSP BF548 evaluation systems as well as future EZ Boards The SHARC evaluation systems include soon to be released ADSP 21469 EZ Board as well as other future EZ Boards Examples for the ADSP BF518F EZ Board are provided for bulk loopback bulk redirect and mass storage Blackfin Examples USB EZ EXTENDER bulk loopback app Blackfin Examples USB EZ EXTENDER bulk redirect jo app Blackfin Examples USB EZ EXTENDER mass_ storage app ADSP BF518F EZ Board Examples VisualDSP 5 0 Update 6 includes additional examples for the ADSP BF518F EZ Board evaluation system Blackfin Examples ADSP BF518F Blackfin Examples ADSP BF518F Blackfin Examples ADSP BF518F Blackfin Blackfin Examples ADSP BF518F Examples ADSP BF518F Blackfin Examples ADSP BF518F EZ BoardW EZ BoardM EZ BoardW EZ BoardW EZ BoardW LAN DNS Client LAN FileServerStdio LAN HTTP Server LAN Multicast Sender LAN PTP EZ BoardWM LAN TCPIP Trace This is a new example for Precise Time Protocol necessary for IEEE 1588 support ADSP BF526 EZ Board Examples VisualDSP 5 0 Update 6 includes additional examples for the ADSP BF526 EZ Board The example can be found in the following directories Blackfin Examples ADSP BF526 EZ KIT Lite drivers usb bulk loopback app
138. inter which may point to an invalid address on the opposite control flow of a conditional jump to the predicted taken path and ICPLBS are disabled The result of this is potentially spurious hardware errors The compiler works around this anomaly by not generating indirect call or jump instructions in the 2 instruction slots following a conditional jump for impacted parts unless either the icplbs or cplbs switches are used The runtime libraries and VDK support that is linked in when building for impacted parts and silicon revisions have been modified to avoid the anomaly Assembler detection for this anomaly will be provided in a future update VisualDSP 5 0 Update 5 Release Notes Rev 1 8 Page 5 15 Silicon Anomaly 05000428 ADSP BF561 Lost Write to L2 Memory Following Speculative Read from L2 Memory The Blackfin C C compiler assembler VDK and runtime libraries have been enhanced to include workarounds for anomaly 05000428 The anomaly occurs when a write to L2 memory is followed by a speculative read from L2 memory in the shadow of a branch executed on core B This results in the write being lost or corrupted The compiler works around this anomaly by not generating potentially problematic reads in the 2 slots following a conditional jump for any impacted parts The compiler will allow reads from MMR s or external memory if they can be identified as such to remain in the 3 slots following the conditional jump T
139. irst run time heap Known Tools Anomalies Details can be found on the Tools Anomaly Web page The URL is http www analog com processors tools anomalies VisualDSP 5 0 Update 6 Release Notes Rev 1 3 Page 6 28 VisualDSP 5 0 Update 5 Release Notes Revision 1 8 November 21 2008 Table of Contents anne EE 5 2 Release Notes ia TE 5 2 Sta ON A A AR AI i 5 2 Identifying Your VisualDSP Version oooocococnnncncncnonononnnnnnnoncnnonannonnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnns 5 2 stalling the Und Beete AE dee EES 5 2 Cloning VisualDSP EE 5 2 O EE 5 3 TAR Tools Anomaly Reference Number 5 3 New Hardware SUPPONE ii A A A Ai 5 4 New Processors and Processor Revision Support 5 4 Processor Revision Deprecati0N csssssceccceccccenssssescecececseueusseseecececsuaeusssscececesseseuaussesseceeessanegssss 5 5 New Evaluation Board Support 5 5 New System Services and Device Drivers ccoccconononoonnnnnnnonnonnnonnnnnnnnnnnnnononnnnnnnnnnonnnnnn non nnnnnnnnnnnnnononnns 5 6 NEE EES eege e gg 5 6 NEW EXAMP ES gt EE 5 7 ADSP BF518F EZ KIT Lite lu Sicilia diia iaa 5 7 ADSP BFS26 EZ KIT Lite Examples 0 a ia 5 7 Landscape LCD EZ EXTENDER Examples occcccccncnonononnnnnononcnononononnnnnnnnnnnnnnnononnnnnnnnnnnnnnnnnnnnnnnnnnnnnnns 5 7 Wd te RE NENT ii 5 8 New Blackfin Compiler Switches aiiis a a E TEA EAEE EKE 5 8 Feature Macros Bla ekfa id 5 8 NAND BO0t Release NOLES tuto a Aida 5 9 Implicit PUSFESTS
140. is not installed please install it first Installation on a previous update is fine If a newer update has already been installed please do not install this update This update is not intended to be installed on alpha or beta releases Identifying Your VisualDSP Version The VisualDSP release and update level can be found in 2 locations 1 In the Control Panel open the Add Remove Programs applet 2 In the VisualDSP Development Environment select Help About VisualDSP Installing the Update Please follow the instructions below for installing this update Please note that since VisualDSP supports having multiple instances installed on a single system you can install this update on top of one instance while keeping the previous installation 1 Use the Start Menu to navigate to VisualDSP Maintain this installation By default this is at Start Menu select All Programs Analog Devices VisualDSP 5 0 2 Select Go to the Analog Devices website and click Next This will open a window in your web browser 3 Select the appropriate Processor Software Tools Upgrades to match your processor 4 Select and download the desired update VisualDSP 5 0_Update3 vdu to your hard drive 5 Again use the Start Menu to navigate to VisualDSP Maintain this installation 6 Select Apply a downloaded Update and click Next 7 Browse for the downloaded Update file VisualDSP 5 0_Update3 vdu and click Next
141. isters that have an effect latency of 1 the maximum number of instructions it takes for a write to these registers to take effect instead of having an effect latency of 2 if any of their bits impact an instruction containing an external data access MODE1 MODE2 MMASK ASTATx ASTATy STKYx and STKYy The compiler has new workaround 09000022 and workaround 15000004 switches that are enabled automatically when building for parts and revision that are impacted by the anomaly When these are used the compiler will insert a nop if required between a system register use and an affected instruction Note that user supplied assembly code will not be modified Run time library code has also been rebuilt with the modified compiler and assembly code modified where necessary to ensure the anomaly does not occur Silicon Anomaly 09000023 15000005 ADSP 2137x ADSP 214xx Writes to LCNTR CURLCNTR and LADDR from Internal Memory may fail if there is a DMA block conflict This anomaly may occur when writes to LCNTR CURLCNTR and LADDR are made from internal memory when there is a DMA block conflict VisualDSP 5 0 Update 7 Release Notes Rev 1 0 Page 7 13 The assembler has a new anomaly detect 09000023 switch forthe ADSP 2137x processor series and anomaly detect 15000005 switch for the ADSP 214xx processor series The functionality of these switches is to detect any write to LCNTR CURLCNTR or LADDR from memory When detec
142. kfin products optimized software implementations of some cryptographic algorithms are stored in ROM These algorithms are C callable with an API that is documented in the respective Hardware Reference Manual HRM and defined in the Boot ROM header Blackfinlincludelb rom h 1 In the Blackfin ADSP BF54x processors the algorithms available are SHA 1 AES and ARCA In these devices the cryptographic algorithms are stored in Instruction ROM IROM which operates in the CCLK domain 2 Inthe Blackfin ADSP BF52x and ADSP BF51x processors the only cryptographic algorithm available is SHA 1 In these processors SHA 1 is stored in Boot ROM which operates in the SCLK domain In order to build with the algorithm definitions users must build for the correct silicon revision The following table shows which revisions of the above processor families introduced the cryptographic support Processor Family Silicon Revision Cryptographic Algorithms ADSP BF51x Rev 0 0 SHA 1 ADSP BF522 524 526 Rev 0 0 SHA 1 ADSP BF523 525 527 Rev 0 1 SHA 1 ADSP BF54x Rev 0 1 SHA 1 AES ARC4 These cryptographic algorithms have not been FIPS certified to ensure their correctness and cryptographic security Therefore while the intent of providing these algorithms in ROM is to enable their use by customers users are strongly urged to verify the adequacy of the algorithms before using them in real applications Changes to Reserved DDR
143. l4xx Examples ADSF l4xx Examples ADSF l4xx Examples ADSF NONNNNNNNNNNNNDN NH KBR ds ds vs vs BB BB BB BBA KBR ds ds vs vs BB BB BB BBA YO Ee PO SD 0 ED Ki SE ZE Ki EOL ZE MINNNNNNNNNNNNDND LD New accelerator examples are provided 69 EZ Board 256pointFFT 69 EZ Board 512pointFFT 69 EZ Board Decimation Filter 69 EZ Board Interpolation Filter 69 EZ Board Multichannel Filter Autolterate 69 EZ Board MultilIteration Mode 69 EZ BoardYSinglelteration Mode 69 EZ Board Talkthrough_ IIR Accelerator 14xxlExampleslADS 14xxlExampleslADS 14xxlExampleslADS 14xxlExampleslADS 14xxlExampleslADS 14xxlExampleslADS 14xxlExampleslADS 14xx Examples ADSE TR EE ET A ORR ZER ZE NONNNNNN NY KB DDB DB BRB MNNNNNNN DN KB DDB DB BR WD A new example for converting a project from normal word to short word VISA is provided 214xx Examples ADSP 21469 EZ Board VISA example VDK examples are also provided 214xx Examples No Hardware Required VDK 21469 BoundedBuffer Mutex 214xx Examples No Hardware Required VDK 21469 BoundedBuffer Semaphor 214xx Examples No Hardware Required VDK 21469 DiningPhilosopher 214xx Examples No Hardware Required VDK 21469 Factory VisualDSP 5 0 Update 7 Release Notes Rev 1 0 Page 7 7 Hardware Required VDK 21 Hardware Required VDK 21 Hardware Required VDK 21469 MultipleHeaps Hardware Required VDK 21469 ProducerConsumer 14
144. lication that used to take 90 of processor time now takes only 20 Memory Manager Service The memory manager allows user applications and other services to dynamically allocate memory from application specific memory pools using various allocation algorithms The currently released algorithms are fixed block size binary buddy circular queue and user customizable algorithms The flexibility in choosing the algorithm helps the user optimize their system by providing him with the choice of allocation speed vs memory overhead For more details see the System Services User s Manual VisualDSP 5 0 Update 8 Release Notes Rev 2 1 Page 8 14 Standard I O Service The Standard I O service provides an easy way to redirect the regular C streams to a physical output Currently the UART output is supported More devices peripherals may be added in the future The streams that can be redirected are the stdout the stderr and stdin Once the streams are redirected using a simple API the application can simply continue using the regular stdio h APIs printf scanf the service initializes the physical device and intercepts stdio accesses to forward them to the selected device By default standard I O is directed to the console via the JTAG which requires halting the processor Redirecting the I O to the UART could provide a better run time performance while debugging code For more details see the System Services User s Manual USB Support
145. licon Anomaly Ob O0 03271 2 7 ADSP BF52x Silicon Anomaly Ob O0 03280 2 8 Invalid SCLK Frequency for ADSP BF548 at Power Up TAR 35129 ccccnnnccocncnncnoncnonnnonnnnos 2 8 Problem Chats td a aia 2 9 Problems Addressed iii a 2 9 L ae Problems end a a a 2 10 VisualDSP 5 0 Update 2 Release Notes Rev 1 1 Page 2 1 Nomenclature In the past VisualDSP updates were labeled by the month and year of their release In order to improve clarity updates will now be numbered e g Update 1 Update 2 etc Installation This update should only be installed after installing the VisualDSP 5 0 base release If VisualDSP 5 0 is not installed please install it first Installation on a previous update is fine If a newer update has already been installed please do not install this update This update is not intended to be installed on alpha or beta releases Identifying Your VisualDSP Version The VisualDSP release and update level can be found in 2 locations In the Control Panel open the Add Remove Programs applet In the VisualDSP Development Environment select Help About VisualDSP Installing the Update Please follow the instructions below for installing this update Please note that since VisualDSP supports having multiple instances installed on a single system you can install this update on top of one instance while keeping the previous installation Use the Start Menu to navigate to VisualDSP Maintai
146. ling of stack and heap sizes in Bytes should be Blackfin 35610 System Builder reviewed Heap Stack configured with KB will not select kB in Proj Blackfin 36158 System Builder Options Blackfin 36223 System Builder CACHE_MEM_MODE is undefined Blackfin 35045 System Services error during fss_rename function Blackfin 29736 TCPIP Stack Multiple network interface issue Iwip send function returns bytes sent but sends only 64K Blackfin 30157 TCPIP Stack max asm warns about the part of anomaly 07000009 fixed in SHARC 36505 Assembler rev 0 5 SHARC 35661 Emulator Unable to set core child register bits via register window OxCDCDCDCD in the SDRAM ranges higher than 0x80000 SHARC 36421 Emulator for 21065L The kernel dxe does not correlate with the asm file in SHARC 36444 Loader project PM version of setlocale ___setlocaleP has code in wrong SHARC 36075 Run Time Libraries section SHARC 36371 Run Time Libraries powd returns wrong result for powers gt 1e8 and lt 1e8 Known Tools Anomalies Details can be found on the Tools Anomaly Web page The URL is http VisualDSP 5 0 Update 4 Release Notes Rev 1 2 www analog com rocessors tools anomalies Page 4 14 VisualDSP 5 0 Update 3 Release Notes Revision 1 3 June 16 2008 Table of Contents N m n lat re ai 3 3 INS a di 3 3 Identifying Your VisualDSP Version oooooococccncccnononononnnnnnnonnnnnnnonnnnnnnnnnnnnnnnnnonnnnnnnnconnnnnnnnnos 3 3 installing th
147. ls anomalies addressed in VisualDSP 5 0 Update 3 for which details can be found on the public tools anomaly website Other tools anomalies have also been fixed in the Update Details can be found on the Tools Anomaly Web page The URL is http www analog com processors tools anomalies Tools Processor Anomaly Family Report Tool Description Extern C after All 34023 Compiler default_section ALLDATA L1_data gives error default_section pragma doesn t work with All 34828 Compiler concatenated strings sizeof multi dimensional array of variable amp static All 34928 Compiler length array VDK Status window shows incorrect message All 35158 IDDE channel ADspCommon XML anomalies 05 00 0312 and 05 00 0283 don t apply Blackfin 35512 Files to BF52x Blackfin 35047 MISRA rules 10 1 b amp 10 2 b incorrectly reported int div mod causes internal compiler error Blackfin 35122 Compiler peephole c 1472 O Missing boot ROM sources for ADSP BF52x Blackfin 35102 Examples ADSP BF54x processors ADSP BF561 internal external regulator readme Blackfin 35488 Examples note incorrect Compare does not work for Blackfin 35178 Flash Programmer BF527EzFlashDriver_M25P16 Trying to run VisualDSP 5 0 but nothing Blackfin 34397 IDDE happens License Server s License Manager reads both Blackfin 35039 IDDE license dat files Request to support p exclusively for application Blackfin 29526 Loader HEX address 64 bit fast floa
148. ly configured during TigerSHARC 35194 VDK thread creation Known Tools Anomalies Details can be found on the Tools Anomaly Web page The URL is http www analog com processors tools anomalies VisualDSP 5 0 Update 3 Release Notes Rev 1 3 Page 3 19 VisualDSP 5 0 Update 2 Release Notes Revision 1 1 2008 February 26 Table of Contents Nomenclatura acia 2 2 Sta EE 2 2 Identifying Your VisualDSP Version cccccccccssssssssssececeeeesssessnseeeseeeescesseessaeeeeeesesssessaaees 2 2 Installing th Updaten eninde ad aii 2 2 New Hardware Upon a cibeies bce a a eae ete 2 3 New Processors and Revisions Support 2 3 New Emulation SUP DOM NEE 2 3 New System Services and Device Drivers 2 3 New DEA OLEE A is 2 4 en GE 2 4 SIE EE 2 4 EnticalExes Chats iaa nasided SassedatuadedoundlaiaaAadunrd a a daveretelee 2 5 ADSP BF522 processor name change 2 5 Linker error li1040 and meminit in LDFs TAR 24071 2 5 Limitation karla Rana ida do 2 6 VisualDSP 5 0 ADSP BF54x Known Limitations ccccecessceceeecesssssaececeeeeesessssteaeeeeees 2 6 VisualDSP 5 0 ADSP BF52x Known Limitations ccccesscsceceeecessesssaeeeceeeesssesssseaeeeeees 2 6 Incomplete ADSP BF523 BF525 BF527 silicon rev 0 1 Support TAR 26224 2 6 No ADSP BF523 BF524 Startup Wizard Support TAR 25164 2 6 Silicon Anomaly Workaround Ss ierse iane a AEEA E a aA 2 7 ADSP BF5xx Silicon Anomaly Ob O0 03272 2 7 ADSP BF5xx Si
149. m is that when transitioning from SLEEP the STOPCK bit is NOT automatically cleared the same way it is cleared VisualDSP 5 0 Release Notes Page 7 upon wakeup from DEEP SLEEP The core clock is enabled but the STOPCK bit does not reflect this The application must explicitly clear the STOPCK bit upon wakeup to resume running or else a subsequent read modify write of PLL_CTL followed by the IDLE sequence can put the processor back to sleep In VisualDSP 5 0 Update 1 the adi_pwr_SetPowerMode function will be modified to facilitate the transition from SLEEP mode to ACTIVE or FULL ON mode The function will update the appropriate register values to complete the transition from SLEEP mode As a workaround the following code can be used clear the STOPCK bit manually upon wakeup from the SLEEP mode enabling the application to resume successfully ul6 PLLCtlVal pPLL CTL PLLCtlVal amp OxFFF7 pPLL CTL PLLCtlVal A subsequent call to adi_owr_GetPowerMode will then reflect the correct power mode File System Corruption When Number of Files Exceeds One Cluster TAR 33677 A known issue with the ADI FAT File System Driver is that when more file entries are created in a directory than there is space available with one cluster directory corruption may occur as subsequent clusters are not zeroed before use For the hard disk attached to the ADSP BF548 EZ KIT Lite development board formatted as a 32GB FAT 32 partition this limita
150. mp Blackfin 40981 Source Generator B Blackfin 36592 System Services USB driver copies from 0x00000000 2 to some location Blackfin 40875 System Services BF518 RSI driver fails to handle FIFO under run errors Blackfin 41593 TCPIP Stack multicast apps does not work on BF527 ez kit rev 2 0 BF527 bulk USB example causes blue screen and Blackfin 40586 USB Stack reboot USB 1 1 07000006 text unclear regarding assumption about block SHARC 41146 ADspCommon XML Files 0 PM use Informational msg ea1130 cannot be suppressed at the SHARC 40041 Assembler cmd line segment assembler directive may behave incorrectly for SHARC 40528 Assembler 2146x Compiler can fail to initialize structs if annotations SHARC 41073 Compiler disabled assembler messages ea2018 ea2024 missing from SHARC 40797 Document Help Help Sharc 21375 example block based talkthru audio heard SHARC 40770 Examples one channel SHARC 40363 IDDE Debug option is not set in Debug_NWC configuration VisualDSP 5 0 Update 7 Release Notes Rev 1 0 Page 7 24 SHARC 40578 LDF undefined symbol ___ memzero in C code 2137x objects are not filtered when using a section SHARC 40807 Linker qualifier SHARC 41344 SW plit sections can be mapped into PM segments kee i SHARC 40616 Loader be used SHARC SHARC strncat return incorrect for size argument of zero SHARC SHARC SHARC The short word code set_flag library function SHARC 40763 Run Time Libraries cra
151. mpoline JUMP must execute from internal memory For the simplest type 9 instructions this workaround avoids the cache corruption at the cost in execution of an additional branch and a maximum of one word of memory per index and modify register pair used in branch instructions Each instance of the trampoline workaround will produce a message ea2518 VisualDSP 5 0 Update 3 Release Notes Rev 1 3 Page 3 15 Informational ea2518 myFile asm 43 Applied Workaround for Hardware Anomaly 09000011 converted the indirect branch to a direct branch to trampoline at label JUMP m08i08 The assembler will add the trampoline instructions to the section seg Int code it will generate that section if necessary The assembler will emit message ea2519 identifying the trampolines generated For the message below the source code contained indirect branch instructions using only 18 and m8 Informational ea2519 Trampolines generated for Hardware Anomaly 09000011 section name seg int code trampolines JUMP m08i08 Each object file in which trampoline workarounds have been applied will contain a section seg_int_code providing the trampolines for the code in that object Where different objects each contain the same trampoline the linker will resolve all references to a single instance of the trampoline When the assembler fails to apply the workaround it will produce message 2516 The following series of instructions illustrates one case that
152. mt doj 21469 cpp hdr mt doj The new libraries located in the 214xx 1ib in the install are built without any workarounds enabled si revision none In addition a library directory called 21469 rev_any is supplied Libraries in this directory will contain workarounds for all relevant anomalies on all revisions of ADSP 2146x processors Libraries with names that end in _nwc dl1b have been built for normal word mode nwc Other libraries are built for short word mode swc where possible LDF and Mapping Changes A new SW memory type keyword has been introduced for the ADSP 2146x processor family The SW memory type refers to short word memory 16 bits wide This new memory type can be used within the MEMORY command and as a section qualifier in the section mapping command See the VisualDSP 5 0 Linker and Utilities Manual for more information VisualDSP 5 0 Update 6 Release Notes Rev 1 3 Page 6 13 A new output section memory type qualifier has been introduced This qualifier forces all input objects within the output section to be mapped as the memory type specified Not all combinations are valid See the table below for a list of newly supported translation mappings Input Section Type Output Section Qualifier Memory Segment Mapped To PM PM SW DM DM 32 bit Sw DATA64 DATA64 SW Using the section qualifier mapping of NW DATA64 DM input sections into SW memory segments is allowed for ADSP 2146
153. n 0 0 e ADSP BF516 silicon revision 0 0 Please note that the ADSP BF516 processor was renamed shortly before release as the ADSP BF518 Users developing for the ADSP BF518 should select the ADSP BF516 processor This name change will be reflected in Update 5 Also in Update 5 a new ADSP BF516 processor will be introduced Please refer to the processor datasheet for details on the new ADSP BF516 processor Update 4 provides support for the following silicon revisions to existing Blackfin processors e ADSP BF542 silicon revision 0 2 e ADSP BF544 silicon revision 0 2 e ADSP BF547 silicon revision 0 2 e ADSP BF548 silicon revision 0 2 e ADSP BF549 silicon revision 0 2 There are no new silicon revisions to existing SHARC or TigerSHARC processors with Update 4 New Evaluation Board Support ADSP BF526 EZ KIT Lite Update 4 introduces support for the ADSP BF526 EZ KIT Lite The ADSP BF526 EZ KIT Lite is the first in the new standard of EZ KITs There are two expansion slots for easy stacking of extender boards The board itself is now labelled EZ Board instead of EZ KIT Lite EZ KIT Lite refers to the package not the board itself Instead of having the debug agent designed into the board the Standalone Debug Agent SADA is officially released and is paired with the ADSP BF526 EZ Board This new technology allows the reuse of the SADA board with multiple ADSP BF526 EZ Board and future EZ Board offerings VisualDSP 5 0 Update 4 Rele
154. n if it is theoretically possible to do so e Instructions might be uncompressed if they are near the end of a DO loop e Whether you get compression for a particular instruction might change due to assembler enhancements or fixes e There will be no warnings if instructions cannot be compressed Therefore it is probably not recommended to create code layouts e g tables with fixed size entries that depend on particular instructions being compressed VisualDSP 5 0 Update 6 Release Notes Rev 1 3 Page 6 11 New Assembler Informational ea2536 There is a difference in addressing while in short word mode instructions are no longer one address unit apart as it is in normal word mode and for all other SHARC parts So address arithmetic is dangerous Unfortunately the SHARC calling and returning sequence relies on address arithmetic based on each instruction being one instruction apart SHARC parts have always used a call sequence like cjump func db dm 17 m7 r2 dm i7 m7 pc The function that gets called will compute the return address by taking the saved PC and adding 1 to it The problem occurs in short word mode where the return address is no longer one address further than the saved PC because all instructions are no longer guaranteed to be one address unit long In order to maintain compatibility with all existing SHARC calling conventions we have adopted the following paradigm for invoking a function cjump func db dm 1
155. n include support for new processors new silicon revisions for existing processors and new EZ KIT Lite EZ Board and EZ Extender evaluation systems In order to support these minor revisions are made to the tool chain and additional system services and device drivers need to be added This section describes the new support available in this update ADSP BF50x Processor Series This release introduces support for the ADSP BF50x Blackfin processor series The following new processors are supported ADSP BF504 silicon revision 0 0 ADSP BF504F silicon revision 0 0 ADSP BF506F silicon revision 0 0 ADSP BF592 Processor This release introduces support for the ADSP BF592 Blackfin processor The following new processor is supported e ADSP BF592 silicon revision 0 1 with Tools Utility ROM ADSP 2147x Processor Series This release introduces support for the ADSP 2147x SHARC processor series The following new processors are supported e ADSP 21478 silicon revision 0 0 0 1 0 2 e ADSP 21479 silicon revision 0 0 0 1 0 2 ADSP 2148x Processor Series This release introduces support for the ADSP 2148x SHARC processor series The following new processors are supported e ADSP 21483 silicon revision 0 1 0 2 e ADSP 21486 silicon revision 0 1 0 2 e ADSP 21487 silicon revision 0 1 0 2 e ADSP 21488 silicon revision 0 1 0 2 e ADSP 21489 silicon revision 0 1 0 2 The following part numbers have been reserved for future use
156. n of the silicon was tested to 533 MHz VDD_INT 1 25v 5 Some applications with data buffers located in external L3 memory DDR had occasional intermittent data corruption problems at certain combinations of core clock frequency CCLK and voltage level VLEV The temporary workaround has been to reduce the core clock frequency CCLK to 400 MHz with VLEV set at 1 2 V The System Services Power Management module caps CCLK and VLEV as a precautionary measure The second revision of ADSP BF54X silicon is still under evaluation and the recommendations will soon be available for the CCLK vs VLEV relationship In the absence of exact characterization data for the silicon the System Services Power Management module continues to limit CCLK and VLEV for reliable DDR performance If the application is not affected by the intermittent data corruption problem higher core clock frequencies may be attained using the System Services Power Management command ADI_PWR_CMD_SET_CCLK_TABLE described in the Power Management API reference section of the Device Drivers and System Services User Manual in VisualDSP Help This command overwrites the hard coded CCLK vs VLEV values located in the Power Management source file Blackfin lib src services pwr adi_pwr c The command ADI_PWR_CMD_SET_CCLK_TABLE is passed to the Power Management initialization function adi_pwr_init to define one such CCLK vs VLEV relationship As a general guideline for d
157. n revision 0 3 e ADSP BF549M silicon revision 0 3 Update 5 provides support for the following silicon revisions to existing Blackfin processors e ADSP BF522 silicon revision 0 1 e ADSP BF524 silicon revision 0 1 e ADSP BF526 silicon revision 0 1 There are no new silicon revisions to existing SHARC or TigerSHARC processors with Update 5 Initial support for the ADSP 2146x SHARC processor family will be provided in a separate release VisualDSP 5 0 Update 5 Release Notes Rev 1 8 Page 5 4 Processor Revision Deprecation Support for the following silicon revisions will be deprecated in Update 5 e ADSP TS201 silicon revision 0 1 e ADSP TS202 silicon revision 0 1 e ADSP TS203 silicon revision 0 1 New Evaluation Board Support ADSP BF518F EZ KIT Lite Update 5 introduces initial support for the ADSP BF518F EZ KIT Lite The Power On Self Test POST and Flash Programmer are provided with this release VisualDSP 5 0 Update 5 Release Notes Rev 1 8 Page 5 5 New System Services and Device Drivers The following are now supported by VisualDSP 5 0 NAND Flash Access Support for the NAND flash access has been extended to support the ADSP BF526 EZ KIT Lite VisualDSP 5 0 Update 5 Release Notes Rev 1 8 Page 5 6 New Examples ADSP BF518F EZ KIT Lite Examples VisualDSP 5 0 Update 5 includes initial support for the ADSP BF518F EZ KIT Lite evaluation system The following examples can be found in the following directories
158. n this installation By default this is at Start Menu select All Programs Analog Devices VisualDSP 5 0 Select Go to the Analog Devices website and click Next This will open a window in your web browser Select the appropriate Processor Software Tools Upgrades to match your processor Select and download the desired update VisualDSP 5 0_Update2 vdu to your hard drive Again use the Start Menu to navigate to VisualDSP Maintain this installation Select Apply a downloaded Update and click Next Browse for the downloaded Update file VisualDSP 5 0_Update2 vdu and click Next Follow the on screen prompts to complete installation of this Update VisualDSP 5 0 Update 2 Release Notes Rev 1 1 Page 2 2 New Hardware Support VisualDSP updates often include support for new processors new silicon revisions for existing processors and new EZ KIT Lite evaluation systems In order to support these minor revisions are made to the tool chain and additional system services and device drivers need to be added This section describes the new support available in this update New Processors and Revisions Support The Product Bulletin contains the list of new processors available with VisualDSP 5 0 Refer to the processor s data sheet and hardware reference manuals for information on system configuration peripherals registers and operating modes The following are Blackfin processors newly supported with Updat
159. nclude support for new processors new silicon revisions for existing processors and new EZ KIT Lite evaluation systems In order to support these minor revisions are made to the tool chain and additional system services and device drivers need to be added This section describes the new support available in this update New Processors and Revisions Support The Product Release Bulletin contains the list of new processors available with VisualDSP 5 0 Refer to the processor s data sheet and hardware reference manuals for information on system configuration peripherals registers and operating modes The following are Blackfin processors newly supported with Update 1 e ADSP BF547 silicon revision 0 1 The following are newly supported silicon revisions to existing Blackfin processors with Update 1 ADSP BF542 silicon revision 0 1 ADSP BF544 silicon revision 0 1 ADSP BF548 silicon revision 0 1 ADSP BF549 silicon revision 0 1 The following are newly supported silicon revisions to existing SHARC processors with Update 1 e ADSP 21367 silicon revision 0 2 e ADSP 21368 silicon revision 0 2 e ADSP 21369 silicon revision 0 2 New Emulation Support The following emulation features are now supported by VisualDSP 5 0 Support for the ADSP BF52x processors Support for the BF527 EZ KIT Lite and onboard debug agent Flash programming for the BF527 EZ KIT Lite for STMicroelectronics M25P16 and STMicroelectronics M29W320 New S
160. ng LDF Blackfin 34621 IDDE si revision any in project options does not work Blackfin 34259 LDFGen Start symbol of second user heap in SDRAM has wrong value Blackfin 34478 Loader Loader Driver creates incomplete dependency Run Time Blackfin 34317 Libraries L2 shared memory used to map locks etc can be cached Run Time Blackfin 34487 Libraries SYSCR bits not yet updated in defBF52x_base h Run Time Blackfin 34488 Libraries SYSCR bits not yet updated in defBF54x_base h Run Time Blackfin 34744 Libraries meminit support zero init of arrays larger than 64k fails Blackfin 34291 Simulator MDMA needs to be supported in BF54x for meminit to work Blackfin 34319 Simulator Filling memory with Hex32 format file reads the wrong way Blackfin 34434 Simulator Binary 16 Bit does not work in memory window Blackfin 34742 Simulator DMA MMRs incorrect in memory locals expr windows VisualDSP 5 0 Update 2 Release Notes Rev 1 1 Page 2 9 Blackfin 33518 System Services pwr mgmt to facilitate transition from SLEEP Blackfin 29313 TCPIP Stack ETHARP_ALWAYS_INSERT option is deprecated in IwIP Blackfin 34680 VDK VDK Status window does not display any threads SHARG 32749 Compiler slowdown of code using division when build Os SHARC 34819 Compiler USTAT1 and USTAT2 used in compiler generated code VisualDSP disconnects if Sport DMA Address reg window is SHARG 29561 Emulator open SHARC 32810
161. ng this update Please note that since VisualDSP supports having multiple instances installed on a single system you can install this update on top of one instance while maintaining the previous installation 33 Use the Start Menu to navigate to VisualDSP Maintain this installation By default this is at Start Menu gt All Programs gt Analog Devices gt VisualDSP 5 0 34 Select Go to the Analog Devices website and click Next This will open a window in your web browser 35 Select the appropriate Processor Software Tools Upgrades to match your processor 36 Select and download the desired update VisualDSP 5 0 Update4 vdu to your hard drive 37 Again use the Start Menu to navigate to VisualDSP Maintain this installation 38 Select Apply a downloaded Update and click Next 39 Browse for the downloaded Update file VisualDSP 5 0 Update4 vdu and click Next 40 Follow the on screen prompts to complete installation of this Update Cloning VisualDSP VisualDSP supports cloning of an existing installation A clone of an installation creates a new instance of a product from an existing installation rather than from a CD or web software distribution The use of clones allows you to maintain multiple versions of VisualDSP on the same PC at different update levels and provides a risk free way to test new updates or patches VisualDSP 5 0 Update 4 Release Notes Rev 1 2 Page 4 2 To clone your existing
162. nnannnnnnnnonnnns 8 Device Driver Release Notes Blackfin cccocononocnonncnnnnnonononnnnnnnnnnnnnonononnnnnononnnnnnnnnnnnnnnnnnnns 8 Additional Device Driver Documentation 8 Emulator Release NOLES cis s cefeclehsedesnaneteddeseeddvnasen da lesebedsesacedel dape decadas 9 Customizing XML Register Reset Values 9 Noteworthy VisualDSP 4 5 Update Changes ccccccccccccccsssssssssceceeeescseseeaeeeeeesesesesssaeeeeeeeens 9 Incorrect Memory Mapping for ADSP 21375 TAR 2181 9 Former Workaround for 05 00 0311 is Not Safe Blackfin TAR 23244 10 Problem S AT 1E EEA BEE Ae AL A ta tote eo EE 12 Problems Addressed es cti dicas 12 KNOWN Prol IIS ati a E E E daa 14 VisualDSP 5 0 Release Notes Page 1 VisualDSP 5 0 Documents Release Notes This document provides the Release Notes for the VisualDSP 5 0 release Product Release Bulletin Your primary source of information for the VisualDSP 5 0 Release is the Product Release Bulletin manual in paf format that accompanies this release Documentation Set The complete set of documentation in pdf format is provided on the VisualDSP Installation CD The manuals are available in chm online Help format in the installation Additional information is available online in the Technical Library http www analog com processors technicalSupport technicalLibrary Licensing Guide The VisualDSP 5 0 Licensing Guide is a new document that describes how to mana
163. ns following a delayed branch The assembler detection warning is enabled manually using the anomaly detect 09000014 switch The assembler defines macro __ASM_DETECT_09000014__ when detection for this anomaly is enabled The compiler and assembler workarounds are enabled automatically when building for ADSP 21371 and ADSP 21375 revisions 0 0 and any The runtime libraries and VDK support that is linked in when building for impacted parts and silicon revisions have been modified to avoid the anomaly Silicon Anomaly 09000015 ADSP 2137x Incorrect Popping of stacks possible when exiting IRQx Timer Interrupts with DB modifiers VisualDSP 5 0 Update 4 Release Notes Rev 1 2 Page 4 11 A new SHARC compiler pragma pragma no db return has been added This pragma is used immediately before a function definition and will cause the compiler to ensure that non delayed branch instructions are used to return from the function The pragma may be applied to both interrupt and non interrupt function definitions Applying the pragma to an interrupt function can be used as a workaround for ADSP 2137x silicon anomaly 09000015 Incorrect Popping of stacks possible when exiting IRQx Timer Interrupts with DB modifiers Silicon Anomaly 09000018 ADSP 2137x Specific Multiplier operations must not be part of the same Instruction as an External Memory access The SHARC C C compiler assembler VDK and runtime libraries have been enhanced to include
164. ns involving DAG register post modify operations must not be followed immediately by an instruction that uses the same index register as the register might not be updated with the result of the modify 09000023 Writes to LCNTR CURLCNTR and LADDR from Internal Memory may fail if there is a DMA block conflict 15000005 Writes to LCNTR CURLCNTR and LADDR from Internal Memory may fail if there is a DMA block conflict 15000010 Incorrect value when the results of Enhanced Modify BITREV Instruction are used in the very next Instruction 15000012 External FLAG based conditional instructions involving DAG register post modify operations must not be followed immediately by an All Blackfin parts and revisions ADSP 21160 the testset builtin was added A compiler pragma and assembler detection support was added ADSP 21161 A compiler pragma and assembler detection support was added ADSP 2126x Default LDF changes automatically enabled for affected parts ADSP 2126x A compiler pragma and assembler detection support was added ADSP 21362 Assembler detection 21363 21364 added automatically 21365 21366 ADSP 21367 21368 21369 Assembler detection added automatically enabled for affected parts ADSP 2137x Compiler workaround added and VDK changes ADSP 214xx Compiler workaround added and VDK changes ADSP 214xx Assembler detect option enabled by default ADSP 214xx Assembler detection added a
165. nstructs the compiler to assume that all data memory accesses will be validated by the Blackfin processor s memory protection hardware This allows the compiler to identify situations where the cacheability protection lookaside buffers CPLBs will avoid issues the compiler would otherwise workaround e g anomaly 05 00 0428 improving code size and performance If both ICPLBs and DCPLBs are active the cplbs switch should still be used Feature Macros Blackfin The lt feature macros gt block in the System ArchDef compiler xml files contain macros that the assembler and compiler automatically pre define New feature macros have been added for processor family names for standardization To maintain backwards compatibility no preexisting feature macros have been deleted For more details see below Family M ow pe __ADSPBF537_FAMILY__ __ADSPBF53x__ ADSP BF534 ADSP BF536 ADSP BF537 __ADSPBF538_FAMILY__ __ADSPBF53x__ ADSP BF538 ADSP BF539 __ADSPBF548_FAMILY__ __ADSPBF54x__ ADSP BF542 ADSP BF544 ADSP BF547 ADSP BF548 ADSP BF549 __ADSPBF548M_FAMILY__ _ ADSPBF54x__ ADSP BF542M ADSP BF544M ADSP BF547M ADSP BF548M ADSP BF549M __ADSPBF561_FAMILY__ ADSPBF56x__ ADSP BF561 VisualDSP 5 0 Update 5 Release Notes Rev 1 8 Page 5 8 NAND Boot Release notes NAND Boot Command line Option b NAND Appending 256 byte End Block as Ignore Block The Blackfin loader appends an ignore block containing 256 bytes all zeros to
166. o navigate to VisualDSP Maintain this installation 30 Select Apply a downloaded Update and click Next 31 Browse for the downloaded Update file VisualDSP 5 0 Update5 vdu and click Next 32 Follow the on screen prompts to complete installation of this Update Cloning VisualDSP VisualDSP supports cloning of an existing installation A clone of an installation creates a new instance of a product from an existing installation rather than from a CD or web software distribution The use of clones allows you to maintain multiple versions of VisualDSP on the same PC at different update levels and provides a risk free way to test new updates or patches VisualDSP 5 0 Update 5 Release Notes Rev 1 8 Page 5 2 To clone your existing installation of VisualDSP 13 Go to Start gt Programs gt Analog Devices gt VisualDSP 5 0 or equivalent gt Maintain this Installation 14 Select Clone this Installation and click Next 15 Optionally click Advanced to set the Start menu path 16 Enter the Clone install path and click Next Definitions This section provides definitions for terminology relating to VisualDSP and this document TAR Tools Anomaly Reference Number Tools Anomaly Reference Number or TAR is used for tracking confirmed defect reports in VisualDSP VisualDSP 5 0 Update 5 Release Notes Rev 1 8 Page 5 3 New Hardware Support VisualDSP updates often include support for new processor
167. odifications 43849 Source Generator made in the IDDE are saved with CR LF All VDK_kDoNotWait and VDK_kNoTimeoutError in C are constant 43035 VDK variables instead of macros Blackfin 42049 05000283 workaround to avoid killed MMR write is not implemented Blackfin 43044 struct with mixed bitfields chars not initialized properly compiler internal error building compiler that uses compilers testset Blackfin 43084 Compiler builtin with O for BF561 Bad power of two inputs minus one modulus results when optimizing Blackfin 43359 Compiler for speed IDDE crash with program gt 8 MB and Verify all writes to target Blackfin 43350 Emulator memory selected Writing HEX32 memory mapped stream only puts 16 bits into the ea 43258 IDDE stream data file Blackfin 41966 iors MEM_ARGV is not defined in BF50x default LDFs when caching is on The default LDFs for BF538 are only configured for 32 MB SDRAM when a 43419 64 MB is on EZ Kit Blackfin 41996 BF518 EZ KIT license doesn t work VisualDSP 5 0 Update 8 Release Notes Rev 2 1 Page 8 23 111040 linker error for out of memory in L1_data_b when using a Blackfin 43032 Source Generator generated LDF with Partition external memory set to custom Core fault before entering main when cache is enabled in Write Back Blackfin 43041 Source Generator mode and System Stack in L2 or L3 typo introduced when ensuring that ctor ctorl gdt gdtl are only Blackfin 43096 Source Generator mapped once
168. ols anomaly website Other problems have also been fixed in the Update Details can be found on the Tools Anomaly Web page The URL is http www analog com processors tools anomalies Product Problem Family Number Tool Description All 33743 IDDE Dumping empty 21160 core file fails All 33758 IDDE trouble opening file in IDDE after adding it to a project Run Time All 34558 Libraries snprintf and vsnprintf may write 1 too many chars to the output All 34720 VDK Scheduling is disabled after call to DestroyMutex ADspCommon EBSZ Field in EBIU_SDBCTL is 3 bits in BF534 6 7 8 9 Blackfin 34809 XML Files Processors Blackfin 33643 Compiler keywords such as section cause spurious errors in MISRA mode Blackfin 32752 Debug Agent IceT est fails on ROHS EZ KITs using USB 2 0 HUB Blackfin 34628 Device Driver NEC LCD driver broken by a PPI driver change Blackfin 34668 Emulator Watchdog timer does not fully reset when reset through emulator Blackfin 33862 Examples CDemo Buffer description are incorrect Blackfin 33942 Examples BF561 Chained DMA example does not work Blackfin 34444 Examples BF537_SAFP js does not run to completion Blackfin 34597 Examples Problems with BF533 EZ kit Example Video In Flash Blackfin 34368 Programmer When erasing sector 1 on the BF548 it also erases sector 0 Blackfin 33680 IDDE Changing project options may overwrite worki
169. ontrol Registers Performance Monitor Registers System Peripherals All Blackfin processors PLL Registers CHIPID RTC Registers System Timers System Interrupt Controller SIC DMA MDMA UART SPORT ADSP BF535 also includes SYSCR Watch Dog Timer PCI GPIO SPI All Blackfin Processors NOT including the ADSP BF535 also have PPI EBIU Full MMR support on MP Processors Single Core only has SRAM support Note The ADSP BF54x processors have a limited list of Core and System peripherals that are supported Data Cache amp SRAM Memory Instruction Cache amp SRAM Memory Event Interrupt Controller Registers Core Timer Registers VisualDSP 5 0 Release Notes Page 6 Trace Buffer Registers Watchpoint Control Registers Performance Monitor Registers PLL Registers CHIPID RTC Registers System Services Release Notes Blackfin Silicon Anomaly 05 00 0311 The previous compiler workaround for this anomaly has been deemed unsafe and removed from this release As such the Programmable Flag service no longer relies on the compiler to workaround this anomaly Therefore in this VisualDSP 5 0 release the Programmable Flag service in conjunction with the Interrupt Manager service collectively workaround this anomaly in a safe fashion All versions of the System Service Libraries for Blackfin processors that could potentially be affected by this anomaly inherently work around the anomaly Users of the System Services
170. os 4 10 Silicon Anomaly Workarounde 4 11 Silicon Anomaly 09000014 EE gedeien 4 11 Silicon Anomaly 09000015 ADSP 2137X cccssccssscccssscecssscecssscecsscceesscceessecesseeceesccseseccesseceesaes 4 11 Silicon Anomaly 09000018 ADSP 213 7 Dia a 4 12 Anomaly gn tada 4 13 Tools A omalles Addressed EE 4 13 KNOWN EE ee EE 4 14 VisualDSP 5 0 Update 4 Release Notes Rev 1 2 Page 4 1 Nomenclature In the past VisualDSP updates were labeled by the month and year of their release In order to improve clarity updates are now numbered e g Update 1 Update 2 etc Release Notes These release notes subsumes the release notes for previous updates Release notes for previous updates can be found at the end of this document Installation This update should only be installed after installing the VisualDSP 5 0 base release If VisualDSP 5 0 is not installed please install it first Installation on a previous update is permitted If a newer update has already been installed please do not install this update This update is not intended to be installed on alpha or beta releases Identifying Your VisualDSP Version The VisualDSP release and update level can be found in 2 locations 9 In the Control Panel open the Add Remove Programs applet 10 In the VisualDSP Integrated Development and Debug Environment IDDE select Help gt About VisualDSP Installing the Update Please follow the instructions below for installi
171. ounds at the time of the VisualDSP 5 0 Update 7 release Silicon Anomaly 05000450 ADSP BF54x USB DMA Mode 1 Short Packet Data Corruption DMA mode 1 allows large size transfers to generate a single interrupt at the end of the entire transfer The transfer is split up in packets of length specified in the Maximum Packet Size field for that endpoint If the transfer size is not an integer multiple of the Maximum Packet Size then a short packet will be present at the end of the transfer Under certain conditions this packet may be corrupted in the USB FIFO Workaround The workaround for this anomaly is to use the faster DMA Mode for all packets except for the last packet If the last packet is shorter than the maximum packet size MAX_PKT_SIZE DMA Mode 0 is used MAX_PKT_SIZE is either 64 or 512 depending on whether the USB is connected at full USB 1 1 or high USB 2 0 speed This workaround is implemented with Update 7 Silicon Anomaly 05000456 ADSP BF52x ADSP BF54x USB Receive Interrupt Is Not Generated in DMA Mode 1 Whether the USB is used in host or device mode the USB receive interrupt may not be generated when DMA Mode 1 is used This anomaly also does not apply to transmit operations Host Mode For DMA Mode 1 host mode receive operations where the transfer size is an integer multiple of MaxPacketSize extra in tokens are sent out by the USB controller at the end of the DMA transfer This causes the slave device
172. pdate 4 contains a license dialog to this effect which you must accept before installation can be completed A new example is provided to prepare the NFD for use by the FTL and to format it as a FAT 16 volume Please see the New Examples section for further details Once formatted the NFD can be mounted from the shell_browser application This is done by default in the ADSP BF527 EZ KIT Lite example but needs to be selected as an alternative to the SD card for the equivalent ADSP BF548 EZ KIT Lite example this is because the NAND flash controller shares a DMA channel with the SD host controller To select the NAND ensure that _USE_NAND_ macro is set in the Project Options Improved FAT driver To provide better throughput performance on removable media such as USB flash drives and SD cards the FAT driver has been upgraded to use memory caches for the File Allocation Table FAT and directory information These caches are allocated from the cache heap assigned to the FAT driver The default settings are to provide 256 512 byte sectors of FAT cache and 16 clusters size depends on media of directory information and can be changed with ADI_FAT_CMD_SET_FAT_CACHE_SIZE and ADI_FAT_CMD_SET_DIR_CACHE_SIZE commands IMPORTANT Please note that for optimal benefit these caches are only synchronized with the media upon closure of an open file halting and restarting an application while a file is open for write access can result in data loss The ADI_FAT_
173. pdate 6 assembler anomaly detection support has been added The assembler issues warning ea5518 if either of the two instructions following a not predicted taken conditional jump or the target of a predicted taken conditional jump is an indirect jump or call instruction The anomaly detection is VisualDSP 5 0 Update 6 Release Notes Rev 1 3 Page 6 24 not automatically enabled as many users will have ICPLBS meaning that the errata is avoided Users that do not use ICPLBS can enable the detection warning support by passing anomaly detect 05000426 to the assembler The macro __ ASM_DETECT_05000426__ is defined when this anomaly detection support is enabled Known limitations with this anomaly support e TAR40786 assembler behavior information in BLACKFIN EDN anomaly xml for 05000426 is not correct e TAR40787 anomaly detect 05000426 causes ea1222 ID does not exist Silicon Anomaly 05000428 ADSP BF561 Lost Write to L2 Memory Following Speculative Read from L2 Memory The Blackfin C C compiler assembler VDK and run time libraries have been enhanced to include workarounds for anomaly 05000428 The anomaly occurs when a write to L2 memory is followed by a speculative read from L2 memory in the shadow of a branch executed on core B This results in the write being lost or corrupted The anomaly workaround was incomplete in Update 5 The following additional support is provided in Update 6 Assembler e Assembler detection of
174. piler Compiler Compiler Compiler CRTGen CRTGen Debug Agent Debug Agent Device Driver Device Driver Device Driver Device Driver Device Driver elf2fit Examples IDDE Installation Installation Run Time Libraries Run Time Libraries VisualDSP 5 0 Release Notes C library code linked in with rtti is bigger than 4 0 cycle_t function return types causes compiler warning cc0815 int PrimlOCB means no output multiply defined sym or software exception Compiler driver accepts illegal flags options Workaround switches don t match annotations Inconsistent Assembler behavior with integer constants BF535 float div returns small denorm result when zero expected Wremarks doesn t always warn about deprecated switches section does not apply qualifiers ISR problems with SAVE_REGS functionality no builtin switch causing failures section attribute__ does not work as documented C template instantiations ignore pragma uses volatile store inputs also treated as volatile when unnecessary Slowdown of code using division when build Os Keywords such as section cause spurious errors in MISRA mode still possible to write bad context sensitive builtin_aligned Generated cplbtab file unusable CPLB_D_PAGE_MGMT used indiscriminately in generated BF535 cplbtab Debug agent scans too fast can cause external memory issues IceTest fails on ROHS EZ KIT Lite s using USB 2 0 HUB Autobauding fails at 38 400bps on the 561 only UART au
175. rd template changes include e TAR 31346 Shared data locks etc need to be non cached e TAR 31938 inputs sections for tables require FORCE_CONTIGUITY e TAR 32725 Workaround comment incomplete in generated LDFs TAR 31346 dual core ADSP BF561 applications in order for shared data and locks to be correctly accessed by each core that data must not be allowed to be cached lt has been the case that LDFs and CPLB tables generated by the Project Wizard did not respect that requirement That problem has been fixed TAR 31938 The linker will not guarantee contiguous placement of sections unless the FORCE_CONTIGUITY operator is used If you have table inputs in your LDF that require contiguous placement these should be mapped in a separate memory output section using FORCE_CONTIGUITY In VisualDSP 5 0 the default LDFs have been modified to reflect this More information on the FORCE_CONTIGUITY can be found in the Linker and Utilities manual TAR 32725 In LDFs generated by the Project Wizard there is a particular section of code that works around two silicon anomalies 05 00 0189 and 05 00 0310 However the comment for that section of code only mentions 05 00 0189 If a user believes that 05 00 0189 does not apply the user may remove that section of code only to run into problems because 05 00 0310 does indeed apply To avoid this possibility the comment for that section of code has been corrected Processor Specific Release Notes New Bla
176. ributed with the kit are already configured such ADSP BF51x Headers The definition for the Mask Card Detect in defBF514 h defBF516 h contains an error that will be fixed in the next update define SD CARD DET MASK 0x40 Mask Card Detect should be define SD CARD DET MASK 0x10 Mask Card Detect Power Service May Cause Unhandled CPLB Miss Exceptions ADSP BF54x Users upgrading from VisualDSP 5 0 Base Update 1 or Update 2 that use a customized CPLB table and System Services may experience a problem upgrading to Update 4 In the older releases the generated CPLB tables did not provide page descriptors for Boot ROM address space In Update 4 the Power Service in the System Service Layer calls SysControl in the Boot ROM If the project has a CPLB table generated prior to VisualDSP 5 0 Update 3 a CPLB Miss exception will be generated In this case applications may experience unhandled CPLB Miss exceptions To avoid this problem add the following entries to the CPLB tables dcplbs_table OxEF000000 PAGE SIZE AER CPLB L1 CHBL CPLB VALID CPLB USER RD 4kB Boot ROM Icplbs_table OxEF000000 PAGE SIZE AER CPLB IDOCACHE 4kB Boot ROM VisualDSP 5 0 Update 4 Release Notes Rev 1 2 Page 4 10 Silicon Anomaly Workarounds The file System ArchDef BLACKFIN EDN anomaly xm1 has been modified to include anomaly workarounds specific to the system service and
177. rmat SADI_DSP Blackfin Examples ADSP BF527 EZ KIT Lite Services Fil System NAND NandFormat SADI_DSP Blackfin Examples ADSP BF526 EZ KIT Lite Services Fil System NAND NandFormat The default reserved area size is 10 blocks For the EZ KIT implementations this provides 10 blocks of 64 pages of 2112 bytes per page 1 3MB approx If this default is to be overridden it is important that the ADI NAND_CMD_SET_RESERVED_SIZE command is passed to the FSS NAND Physical Interface Driver PID with the required reserved size upon format and every time it is required for file system access For example if the NAND boot required twice as many blocks you would need to pass the following command pair to the NAND PID on format as well as every time file system access is required ADI NAND CMD SET RESERVED SIZE void 20 VisualDSP 5 0 Update 5 Release Notes Rev 1 8 Page 5 9 This command value pair must be passed in the configuration stage of the NAND PID Please refer to the NAND PID documentation for further details SADI_DSP Blackfin docs drivers pid nand adi_ nand pdf For NAND and OTP boot please refer to Table 2 3 in the VisualDSP 5 0 Loader and Utilities Manual Implicit Push STS Handler Support for a new pragma implicit_push_sts_handler has been added to the SHARC compiler so that the compiler does not generate an explicit PUSH and POP of STS for interrupt handlers
178. rminated almost right away The Readme for the following example is incomplete SW20 1 and 2 must be ON Blackfin Examples ADSP BF526 EZ KIT Lite Drivers AudioCodec Audio Loopback TAR42058 526 audio codec example readme diagram wrong The Readme for the following example is incorrect The display has the input and output connectors swapped VisualDSP 5 0 Update 7 Release Notes Rev 1 0 Page 7 21 Blackfin Examples ADSP BF526 EZ KIT Lite Drivers AudioCodec Audio_ Loopback TAR42059 SSL DD Incompatible with uC OS II version 2 86 Libraries specific for uC OS II cause link errors with latest uC OS II v2 86 The SSL DD Interrupts manager calls internal wC OS II functions upon entry and exit from ISRs Those functions have been removed from the latest wC OS II v2 86 Until fixed please use one of the following two workarounds 1 Use uC OS II v2 85 2 Do not use the SSL DD Interrupt Manager VisualDSP 5 0 Update 7 Release Notes Rev 1 0 Page 7 22 Anomaly Charts Tools Anomalies Addressed The following table is a list of tools anomalies addressed in VisualDSP 5 0 Update 7 for which details can be found on the public tools anomaly website Other tools anomalies have also been fixed in the Update Details can be found on the Tools Anomaly Web page The URL is http www analog com processors tools anomalies Tools Processor Anomaly Family Report Description pragma section does not work with C templa
179. rocessor and Linker Processor to default to VISA Debug Release New Project Configurations set the Assembler Compiler Processor and Linker Processor to default to normal word DebugNWC ReleaseNWC VisualDSP 5 0 Update 6 Release Notes Rev 1 3 Page 6 14 Migrating Projects from the ADSP 2146x Beta 1 Update It is not advisable to migrate projects directly from the Beta 1 Update as there has been a number of changes Should this be necessary please keep in mind the following changes e The default LDFs have changed e The Debug and Release Project Configurations in Beta 1 built normal word projects They will build VISA short word projects in Update 6 In order to build a normal word project make the following changes to the Project Options o On the Compiler Processor property page set the Variable Instruction Set Encoding VISA to Generate Normal Word code o On the Assembler property page set the Variable Instruction Set Encoding VISA to Generate Normal Word code o On the Linker Processor property page set the Libraries to Use Normal Word code Run Time Libraries Accelerator Simulation This release has simulator support for the ADSP 2146x FIR IIR and FFT hardware accelerators Peripheral Simulation The simulator will provide support for the following ADSP 2146x peripherals in future releases e DDR2 e Link Ports e SPORT DMA The simulator does not provide support for the following ADSP 2146x periph
180. ror message instead The assembler will not apply workarounds to code defined in a section named seg_int_code If a user prefers to adjust their code to avoid the anomaly specifying anomaly detect 09000011 will cause the assembler to instead produce a warning for each instance of a problematic branch instruction Specifying no anomaly workaround 09000011 will suppress all assembler activity for this anomaly The assembler will apply one of two identified workarounds depending upon the specific instruction containing an indirect branch One form of workaround avoids the anomaly by inserting a PC relative branch around the potentially improperly cached location and inserting a NOP instruction at that location thus preventing execution of an instruction at the location that could be improperly cached due to the anomaly at the cost of two words of memory and a branch execution Each instance of the workaround will produce a message ea2517 Informational ea2517 BranchAroundCache asm 24 Applied Workaround for Hardware Anomaly 09000011 Inserted JUMP PC 2 nop after the instruction following the indirect branch The second workaround replaces the problematic indirect branch with an indirect branch to a trampoline see definition below JUMP instruction which will use the same index and modify register as the replaced branch to jump to the original destination of that replaced instruction To avoid the anomaly the tra
181. routine is under 5 Cycles in Duration anomaly workarounds support has been added The Blackfin C C compiler has been enhanced to include workarounds for anomaly 05 00 0371 Possible RETS Register Corruption when Subroutine is under 5 Cycles in Duration The anomaly happens very rarely when calling functions with an RTS within 5 instructions from the start of the function The C C compiler workaround is to avoid generating such functions in the assembly it produces these would typically result from stub function code The workaround involves inserting NOP instructions or an unconditional JUMP instruction before the RTS The JUMP workaround variant is used when optimizing for code size Os and there would be more than two NOPs otherwise required To enable this compiler workaround manually the workaround avoid quick rts 371 switch can be used When the workaround is enabled the macro __ WORKAROUND_AVOID_QUICK_RTS_371 is defined at compile assemble and link stages The Blackfin assembler has been modified to issue a warning ea5516 for code that may hit the anomaly and require a workaround to be inserted An example of this new warning is Warning ea5516 memchr asm 39 RTS instruction use may trigger hardware anomaly 05 00 0371 See appropriate Blackfin anomaly lists for more information The runtime libraries and VDK support linked when building for impacted parts and silicon revisions have been modified to avoid the anomaly
182. rrupts disabled around the workaround This has meant some associated changes in the workaround for the related TESTSET anomaly 05000412 The compiler has workarounds for these anomalies that are issued for calls of the compiler builtin function builtin testset as used in ccblkfn h defined functions adi_acquire lock andadi_try_lock The 05000248 workaround is automatically enabled for ADSP BF561 revisions 0 2 0 3 and any The 05000412 workaround is automatically enabled when building for 0 2 0 3 0 5 and any Here is an example of what the compiler produces foracallto buitin_testset when both the 05000248 and 05000412 workarounds are enabled PO L _ var wa 05000248 PO H __ var wa _05000248 Inserted to fix anomaly 05000248 and 05000412 MESSAGE SUPPRESS 5515 FOR 1 LINES CLI RO R1 Pl NOP NOP SSYNC TESTSET P1 W PO RO STI RO Here is the 05000412 only workaround code MESSAGE SUPPRESS 5515 FOR 1 LINES CLI RO R1 P1 NOP NOP SSYNC TESTSET P1 STI RO Inserted to fix anomaly 05000412 Here is the 05000248 only workaround PO L var wa 05000248 PO H var wa_05000248 Inserted to fix anomaly 05000248 CLI RO NOP NOP TESTSET P1 W P0 RO STI RO These sequences of instructions match IC Anomaly list for the ADSP BF561 Silicon Anomaly 06000020 ADSP 2126x Indirect jumps or calls followed by Long
183. rt available in this update New Processors and Processor Revision Support This section lists new processors and processor revisions available in this update Refer to the data sheets and hardware reference manuals for information on system configuration peripherals registers and operating modes Update 6 introduces a new processor series to the SHARC processor family e ADSP 21462 silicon revision 0 0 e ADSP 21465 silicon revision 0 0 e ADSP 21467 silicon revision 0 0 e ADSP 21469 silicon revision 0 0 No new Blackfin or TigerSHARC processors are supported with Update 6 Update 6 also provides support for the following silicon revisions to existing Blackfin processors e ADSP BF512 silicon revision 0 1 e ADSP BF514 silicon revision 0 1 e ADSP BF516 silicon revision 0 1 e ADSP BF518 silicon revision 0 1 No new silicon revisions to existing SHARC or TigerSHARC processors are supported with Update 6 Processor Revision Deprecation Support for the following silicon revisions are deprecated in Update 6 as the revision was never released e ADSP BF561 silicon revision 0 4 VisualDSP 5 0 Update 6 Release Notes Rev 1 3 Page 6 5 New Evaluation Board Support Support has been added for the following new evaluation boards USB EZ Extender Update 6 introduces initial support for the USB EZ Extender which connects with both Blackfin and SHARC EZ KIT Lite and EZ Board evaluation systems The Blackfin evaluation systems
184. s allow you to inform the compiler that an IOP register access will take place Use of the new switch and the new functions allows you to ensure that the workaround is only applied when an IOP register is actually accessed Note that if the compiler is able to determine at compile VisualDSP 5 0 Update 7 Release Notes Rev 1 0 Page 7 12 time that the volatile memory access is to an IOP register the workaround will be applied regardless of whether the switch is used no assume vols are iops e Instructs the compiler to not assume that volatile loads and stores are to IOP addresses and therefore candidates for any IOP related silicon errata workarounds include lt builtins h gt unsigned int iop read volatile void a e Reads the IOP register at address at a void iop write volatile void a unsigned int _ b e Writes the value __b to the IOP register at address ai For example volatile unsigned int iop ptr volatile unsigned int 0x1234 unsigned int val iop read iop ptr The run time libraries do not use IOP registers and are not affected by this anomaly Silicon Anomaly 09000022 15000004 ADSP 2137x ADSP 214xx Effect latency of some System Registers may be 2 cycles instead of 1 for External data accesses Compiler and library workarounds to support ADSP 2137x anomaly 09000022 and ADSP 2146x anomaly 15000004 have been added in VisualDSP 5 0 Update 7 This anomaly concerns the following reg
185. s new silicon revisions for existing processors and new EZ KIT Lite evaluation systems In order to support these minor revisions are made to the tool chain and additional system services and device drivers need to be added This section describes the new support available in this update New Processors and Processor Revision Support This section lists new processors and processor revisions available in this update Refer to the data sheets and hardware reference manuals for information on system configuration peripherals registers and operating modes Update 5 introduces two new processors to the ADSP BF51x Blackfin processor family In addition to the ADSP BF512 and ADSP BF514 processors the following new processors are supported e ADSP BF516 silicon revision 0 0 e ADSP BF518 silicon revision 0 0 Please note that the previous ADSP BF516 processor was renamed shortly before release to be the ADSP BF518 The ADSP BF518 is newly supported in Update 5 A new ADSP BF516 processor has been introduced and is supported in Update 5 Please refer to the processor datasheet for details on the new ADSP BF516 processor Update 5 also introduces support for the Mobile DDR variant of the ADSP BF54x Blackfin processor family The Mobile DDR variants are provided separate processor names in VisualDSP for full support e ADSP BF542M silicon revision 0 3 e ADSP BF544M silicon revision 0 3 e ADSP BF547M silicon revision 0 3 e ADSP BF548M silico
186. s Mem PredefinedAlgorithm OTP Programmer ADSP BF526 527 548 EZ KIT Lites The following example OTP programmers have been added to VisualDSP in this release to support programming the One Time Programmable memory on the ADSP BF52x and ADSP BF54x processor series Blackfin Examples OTPProgrammer ADSP BF526 Blackfin Examples OTPProgrammer ADSP BF527 Blackfin Examples OTPProgrammer ADSP BF548 Boot ROM Code This section describes changes to the Boot ROM code VisualDSP 5 0 Update 8 Release Notes Rev 2 1 Page 8 9 New Boot ROM Code is available in Update 8 for the following processors e ADSP BF50x rev 0 0 e ADSP BF51x rev 0 2 e ADSP BF523 5 7 rev 0 3 e ADSP BF54x rev 0 4 e ADSP BF592 rev 0 1 Init Code This section describes the changes to the Init Code New Init Code is available in Update 8 for the following processors e ADSP BF506F rev 0 0 e ADSP BF518F rev 0 2 e ADSP BF527 rev 0 3 e ADSP BF548 rev 0 4 e ADSP BF592 rev 0 1 e ADSP 21479 e ADSP 21489 VisualDSP 5 0 Update 8 Release Notes Rev 2 1 Page 8 10 Programming for Internal Memory and FLASH on ADSP BF50x Configuring your project to use both internal memory stacked parallel FLASH requires a couple of extra steps This section will guide the user through the proper steps Project Settings for Internal Memory and FLASH To build a project for Internal Memory and FLASH the following changes need to be made to the Project
187. sembler and compiler New macro Description _ NORMAL WORD_CODE ADSP 2146x processors when building in normal word mode SHORT_WORD_CODE ADSP 2146x processors when building in short word mode New Compiler Switches The following C C compiler switches have been added normal word code The normal word code switch is for ADSP 2146x processors only It has the same effect as compiling with the nwc switch It directs the compiler to generate instructions of normal word size 48 bits nwc Same as normal word code short word code VisualDSP 5 0 Update 6 Release Notes Rev 1 3 Page 6 9 The short word code switch is for ADSP 2146x processors only It has the same effect as compiling with the swc switch and directs the compiler to generate instructions of short word size 16 32 48 bits This switch is the default setting when compiling for ADSP 2146x processors SWC Same as short word code New Pragma Support The C C compiler support for pragma section and pragma default section has been modified to accept new section qualifiers New Qualifier Description SW code is short word ADSP 2146x only NW code is normal word ADSP 2146x only Example usage pragma section foo SW Code is short word pragma default section CODE foo2 NW Code is normal word New Automatic Attributes When no auto attrs is not specified the compiler defines a new default at
188. shes loop SHARC 40836 Run Time Libraries seg_init output section too small SHARC 40881 Run Time Libraries cfft may fail if the twiddle table is in external memory besen Sas RTH SHARC 40919 Run Time Libraries def21469 h SHARC SHARC SHARC TRUNC incorrect for negative underflow when TRUNC bit SHARC 40221 Simulator is set SHARC 40766 SPORTs are not supported SHARC 40812 VDK VDK omits SPERRI interrupt on 21368 9 Known Tools Anomalies Details can be found on the Tools Anomaly Web page The URL is http www analog com processors tools anomalies VisualDSP 5 0 Update 7 Release Notes Rev 1 0 Page 7 25 VisualDSP 5 0 Update 6 Release Notes Revision 1 3 August 24 2009 Table of Contents Nomenclat te nanenane r RE ind id 6 3 Release Notes EE AEE T EE A A A EE ETE EAE TEE OE O 6 3 Vita tiie eras ca AA AA ESA A Ad 6 3 Identifying Your VisualDSP Version cccccccccccssssssssecececececsessaeaececeesesesesssaeseeeeeesseeseeaeeeeeeseesaes 6 3 Installing the UA a ica 6 3 Gloning VisualDSP FE ii A A E ci dic feces 6 3 Definition Saa tes 6 4 TAR Tools Anomaly Reference Number 6 4 New Hardware Support 6 5 New Processors and Processor Revision Support 6 5 Processor Revision Deprecati0N c ssssceccccccccenssssescecccesseueesescecececseaeuessseececessaseneasseeseeeeeasanegsess 6 5 New Evaluation Board Sup Ports ii tb 6 6 USBiEZSEXMON O geet Seege eege 6 6 ADSP BR518FEZ Board Examples is EA AR 6 6 ADSP
189. ssor session This issue has been resolved in this update VisualDSP 5 0 Update 1 Release Notes Rev 1 1 Page 1 7 Limitations This section highlights known significant limitations VisualDSP 5 0 ADSP BF54x Known Limitations The following device drivers will be supported in a future update e NAND FLASH driver VisualDSP 5 0 ADSP BF52x Known Limitations The following device drivers will be supported in a future update e NAND FLASH driver Set memory option fails for NET2272 USB loopback TAR 34450 The following examples fail after executing the set memory hostapp s when any other option is run Blackfin Examples USB LAN EZ EXTENDER USB bulk_loopback_app Blackfin Examples USB LAN EZ EXTENDER USB bulk_redirect_io_app BF548 EZ KIT Lite USB drives may need to be formatted TAR 34633 Before using the USB drives build and run the format utility found here Blackfin Examples ADSP BF548 EZ KIT Lite Services File System HardDisk HardDiskFormat File System rename function does not work TAR 34561 The adi_fss_FileRename function fails to rename files within the same partition LCD driver for the BF527 EZ KIT Lite needs modification The ADSP BF527 EZ KIT Lite LCD requires that there be at least a 2 PPI CLK delay between the enabling of the frame and horizontal sync signals In the following 3 files insert the following lines at the specified Blackfin lib src drivers adc adi_ad7674 c line 898 ppi_fs_data en
190. such as the USB Audio class for which Update 6 provides both a class driver and example applications Support is included for e Large configurations e Multiple alternate interfaces e Arbitrary data transmitted and received on Endpoint Zero for control interfaces Net2272 As well as providing improved support for the built in USB OTG controllers on ADSP BF52x 54x improvements have also been made to the net2272 controller driver to provide enhanced support for VisualDSP 5 0 Update 6 Release Notes Rev 1 3 Page 6 17 Blackfin parts without integrated USB The Audio class driver can be implemented on the net2272 interface but no examples are released at this time Please contact Support if you require these examples stating the processor type for which you require them ADSP BF533 ADSP BF561 only In addition to the extensibility improvements above the following issue is also addressed e Handling of multiple read writes requests e No longer required to copy device driver to project directory In order to provide greater flexibility with interrupt priorities the net2272 driver has been changed to use the default IVG level of the Memory DMA streams and Programmable Flag interrupts as set in the System Interrupt Controller SIC_IARx registers Unfortunately on ADSP BF533 BF537 processors the default priority of the Memory DMA interrupts are lower than that of the Programmable Flag interrupt which will result in lock up in existing applica
191. t Wizard will prompt for regeneration of the LDF and startup code These upgrade changes are covered in more detail in the following two sub sections VisualDSP 5 0 dpj Projects Have New Format The format of VisualDSP dpj projects has changed from previous releases and the new VisualDSP 5 0 format is not backwardly compatible At the time VisualDSP 5 0 reads an older generation project the IDDE will provide a pop up asking if it can convert the project to the new format It will save the pre existing version in MyProject dpj bak and the VisualDSP 5 0 version becomes MyProject dp If you would like to keep working with VisualDSP 4 5 without any changes to your application and or projects make a copy of your application for use with the VisualDSP 5 0 version Project Wizard Template Changes Blackfin If you have a project that was generated with the Project Wizard loading the project after installing VisualDSP 5 0 may result in a pop up requesting regeneration of the code LDF Regeneration affects three files 1 LDF 2 basiccrt s 3 heaptab c After regeneration you will be current with the latest improvements in the templates If you would like to keep working with VisualDSP 4 5 without any changes to your application and or projects follow the recommendation in the previous section and make a copy of your application for use with VisualDSP 5 0 VisualDSP 5 0 Release Notes Page 3 Project Wiza
192. t mult inaccurate when result close Blackfin 28489 Run Time Libraries to denorm crtn doj can be removed from LDF File without Blackfin 32319 Run Time Libraries warning Incorrect figures from instrumented profiling using Blackfin 33761 Run Time Libraries compiled sim VisualDSP 5 0 Update 3 Release Notes Rev 1 3 Page 3 18 Blackfin 34699 Run Time Libraries AMBEN_ALL missing in defBF54x_base h Error in defBF54x_base h which defines MCMEM Blackfin 35448 Run Time Libraries instead of MCMEN memory dma fails for 54x meminit on compiled Blackfin 34370 Simulator simulation INETD example should not set the user_data_ptr Blackfin 33007 TCPIP Stack in the header ADSP BF527 LAN examples fail because of MAC Blackfin 35276 TCPIP Stack address in reverse order Unable to modify MAC address for Network0O in Blackfin 34703 TCPIP Wizard LwIP Project VDK does not reset the contents in memory for Blackfin 35060 VDK mempools Context switch code may get split between Blackfin 35254 VDK memory regions pragma interrupt_complete_nesting causes SHARC 35205 Compiler unsafe code internal error at bitmatrix c 81 restrict hardware SHARC 35245 Compiler loops 1 memory access from O pre modified with address SHARC 35390 Compiler O SHARC 35340 Run Time Libraries Missing in 212xx include def21266 h terminate not called when exception thrown TigerSHARC 34924 Compiler during handler TS VDK Thread stack incorrect
193. te All 39918 Compiler functions Params declared as ptr to array may generate false All 40572 Compiler MISRA errors compiler crash misra and save temps or misra no All 40773 Compiler cross module m dim array initialized by zero detected as MISRA All 40862 Compiler violation 9 2 41248 Type error in MISRA C runtime support 39900 elf2fit elf2flt crashes when producing version 5 flat files ADI web links changed Tools Anomaly links not working Blackfin 40818 ADspCommon XML Files as before Blackfin 40310 anomaly 05 00 0209 warnings issued for safe code no anomaly 05000209 detect warnings in multi issued Blackfin 40311 Assembler instructions asm source dependencies not created using the compiler Blackfin 40224 Compiler driver Blackfin 40279 Instrumented Profiling not working in the IDDE Blackfin 40417 memcpy causes misaligned access exceptions eter ae lone internal compiler error brilgen c 2976 in code using Blackfin 40585 Compiler testset Compiler BF518F JTAG errors setting Boot Load from the Blackfin 40627 Debug Agent settings menu Blackfin 40536 BF518F POST SPI flash test fails in release configuration Emulator stdio not able to handle more than Ox7FFFFF Blackfin 40609 Emulator bytes Blackfin 40598 BF526 POST example fails to build a loader file Blackfin 40700 BF526 sketchpad example does not work first time VisualDSP 5 0 Update 7 Release Notes Rev 1 0 Page 7 23 Blackfin 40839 BF518 PT
194. te8 vdu to your hard drive Again use the Start Menu to navigate to VisualDSP Maintain this installation Select Apply a downloaded Update and click Next Browse for the downloaded Update file VisualDSP 5 0_Update8 vdu and click Next Follow the on screen prompts to complete installation of this Update 0 2091 i Cloning VisualDSP VisualDSP supports cloning of an existing installation A clone of an installation creates a new instance of a product from an existing installation rather than from a CD or web software distribution VisualDSP 5 0 Update 8 Release Notes Rev 2 1 Page 8 3 The use of clones allows you to maintain multiple versions of VisualDSP on the same PC at different update levels and provides a risk free way to test new updates or patches To clone your existing installation of VisualDSP 1 Go to Start gt Programs gt Analog Devices gt VisualDSP 5 0 or equivalent gt Maintain this Installation 2 Select Clone this Installation and click Next Optionally click Advanced to set the Start menu path 4 Enter the Clone install path and click Next Y Definitions This section provides definitions for terminology relating to VisualDSP and this document TAR Tools Anomaly Report Tools Anomaly Report or TAR is used for tracking confirmed defect reports in VisualDSP VisualDSP 5 0 Update 8 Release Notes Rev 2 1 Page 8 4 New Silicon Support VisualDSP updates ofte
195. ted the assembler issues warning ea2540 These switches are enabled by default Run time library code avoids this anomaly by ensuring that writes to LCNTR CURLCNTR and LADDR occur in two stages using a register move to load rather than loading them directly from memory The VDK context switch also uses the same workaround Two known issues remain that will be worked around in the next update For more information please refer to the following to public TARs TAR41767 Compiler generates code that can trigger 09000023 15000005 TAR41860 Anomaly detection for anomaly 15000005 is not enabled Silicon Anomaly 15000011 ADSP 214xx Incorrect Execution of VISA CALL DB Instructions under specific conditions The assembler will issue warning ea1092 if the CALL DB instruction is used in VISA mode The compiler normally issues CJUMP instructions to implement function calls rather than CALL instructions The only times the compiler uses CALL instructions is for a subset of the compiler support functions When this workaround is enabled the compiler ensures that it does not issue delayed branch CALLs for these functions in code being compiled for VISA execution the default and swc Library and VDK code has been modified to avoid CALL DB instructions where necessary VisualDSP 5 0 Update 7 Release Notes Rev 1 0 Page 7 14 USB Hardware Issues Update 7 This section details the status of the USB hardware issues and software workar
196. tem example for the ADSP BF527 EZ KIT Lite evaluation system similar to the ADSP BF548 EZ KIT Lite evaluation system example It can be found in the following directory Blackfin Examples ADSP BF527 EZ KIT Lite services File System VisualDSP 5 0 Update 2 Release Notes Rev 1 1 Page 2 4 Critical Fixes Changes This section highlights significant changes due to software anomaly fixes or functional changes ADSP BF522 processor name change The ADSP BF522 has been renamed as the ADSP BF523 Support for this new name is available in Update 2 to VisualDSP 5 0 Those who already created projects for the BF522 and did not use automatically generated LDF s for the ADSP BF522 may need to rewrite or modify their LDF s in the future There is a new ADSP BF522 processor Please refer to the datasheet online for clarification http www analog com en epProd 0 ADSP BF527 00 html Linker error li1040 and meminit in LDFs TAR 34071 The linker has a modification to resolve issues with meminit support TAR34071 that can expose errors in existing LDFs The linker issues error li1040 for these problems This is an example of the linker output Error 111040 C Program Files Analog Devices VisualDSP5 0 TS ldf ADSP TS101 1df 204 Out of memory in output section meminit in processor p0 Total of 0x1 word s were not mapped The default ADSP TS101 LDFs had the problem and has been fixed in Update 2 TAR34273 Older Blackfin defa
197. time can cause undefined behavior as DLLs for the most recently opened VisualDSP IDDE are used rather than those for each separate version One instance of this issue can be seen is you create a new project with a generated CRT in Update 8 if an earlier version of VisualDSP has been opened since opening Update 8 This issue causes a bad CRT to be created that will fail to build Avoid this issue by only running one version of VisualDSP at a time VisualDSP 5 0 Update 8 Release Notes Rev 2 1 Page 8 22 Anomaly Charts Tools Anomalies Addressed The following table is a list of tools anomalies addressed in VisualDSP 5 0 Update 8 for which details can be found on the public tools anomaly website Other tools anomalies have also been fixed in the Update Details can be found on the Tools Anomaly Web page The URL is http www analog com processors tools anomalies Tools Processor Anomaly Family Report Tool Description 41867 subscript out of range warning that should be a MISRA violation All MISRA Rule 2 1 does not always indicate the correct line containing the 43061 Compiler error All using section or segment keyword to place static C class members 43428 Compiler doesn t work gt gt operator performs logical shifts when an arithmetic shift is a E Compiler expected pan 1866 Run Time Libraries array bounds check for rule 21 1 does not fault negative index SourceGenerator writes out files with LF endings but any m
198. tion equates to 512 short name 8 3 entries per cluster Please note that deleting files does not alleviate the issue Additional System Service Library Documentation In the VisualDSP 5 0 installation directory is a subdirectory called _ Blackfin docs services This subdirectory contains updated documentation for the EBIU and Dynamic Power system services In addition this subdirectory contains new documentation for the File System Service and the Real Time Clock service Device Driver Release Notes Blackfin Additional Device Driver Documentation In the VisualDSP 5 0 installation directory is a subdirectory called Blackfin docs drivers This subdirectory contains detailed documentation for each VisualDSP 5 0 Release Notes Page 8 device driver Within each subdirectory is detailed information describing each driver including the dataflow methods it supports command IDs return codes configuration issues etc Included in the USB documentation subdirectory is a porting guide document This document describes the application changes necessary to migrate an application using the USB device driver provided in VisualDSP 4 5 to the newer USB driver provided with VisualDSP 5 0 It is very strongly recommended that all USB users refer to this document Emulator Release Notes Customizing XML Register Reset Values The Use XML Reset Values target option relies on the register reset definitions defined in t
199. tions All net2272 examples have been updated to set the priority of the Memory DMA interrupt to a higher priority than the Programmable Flag interrupt as follows BF533 BF537 IVG 11 BF561 IVG 9 BF518 new IVG 10 The ADI_USB_CMD_SET_DMA_CHANNEL I O command has been added to facilitate the setting of this priority level without detailed knowledge of the Interrupt Manager peripheral ID value e g adi_dev Control PeripheralDevHandle ADI USB CMD SET DMA IVG void 11 Please see the examples in the VisualDSP installation for further details These examples for the ADSP BF53x and ADSP BF561 can be found under VDSP Blackfin Examples USB LAN EZ EXTENDER USB For the ADSP BF518 the examples can be found under VDSP Blackfin Examples USB EZ EXTENDER Configuring the net2272 driver for DMA operation Users who previously took a private copy of the adi_usb_net2272 c driver source file in order to modify the definition of the USE_DMA pre processor macro should note that this is no longer necessary and its use will not produce the desired effect The driver source now uses two macros USE_RX_DMA and USE_TX_DMA to enable or disable its use of memory DMA These macros may be defined in a project s pre processor options and used to selectively enable and disable DMA in either direction USE_RX_DMA and USE_TX_DMA should be given the value O to disable the us
200. to ensure that the legacy segment directive responds to the switches to control Variable Instr Set Architecture VISA encoding swc and nwc in the same way as section Previously code sections defined with segment would be encoded only for normal word execution ignoring default behavior and explicit command line switches intended to produce short word encoding It is necessary that interrupt vector code the 4 instructions per interrupt at the start of code memory that the parts jump to service interrupts is normal word encoded and this might be affected by the assembler change Therefore we recommend that interrupt vector code defined in sections using segment should be modified to use section with explicit NW qualification For example if defined SHORT WORD CODE For parts that support VISA this code has to be mapped to a normal word section so make sure that happens even when building swc section pm nw seg_rth else section pm seg rth fendif interrupt vector code ASDP 2146x Def Headers The def headers for the ADSP 2146x e g def21469 h have been modified to match the new ADSP 2146x SHARC Hardware Processor Manual Rev 0 2 August 2009 Some macros have been modified or deleted ADSP 2146x SHARC Processor Hardware Reference The new ADSP 2146x SHARC Hardware Processor Manual Rev 0 2 has been recently released As this manual has not yet been converted to a help form
201. tobaud timer selection Memory size given to adi_dev_Init must be larger than expected PPI Error Callbacks Error Interrupt Side Effects Bad relocations out of elf2flt when no code ADSP BF561 POST does not stop at main on load with 1 3 rev EZ KIT Lite Step over out doesn t work in flash Deleted SW breakpoints keep re appearing after load After selecting text print from source window prints entire file Terminal font doesn t work in the source window static member of class not resolved in expressions window No warning on Memory Fill Dump outside valid memory Various tool switches reported as not enabled via automation Should keep the paths in the additional include as absolute File specific compile options do not take defaults from existing License not migrated when installing under Windows Vista F2 does not rename VDK items Loading DWARF3 debugging information may crash VisualDSP Changing project options may overwrite working LDF Install_CL does not handle VC2005 SP1 update Unknown publisher warnings during 5 0 Installation on Vista Issues with the 2 link approach for BF561 projects data1 is mapped before L1_bsz Project fails to build when user sets heap space to less than 1k LDFGen doesn t sufficiently support run from flash Stack in mem covered by cplb data table entry in WB mode problem Two output sections with the same name are generated Wrong assignment in the ADSP BF537 Init file Hyperbolic Functions do not return Inf when
202. tribute called Encoding The value of the attribute depends on the code produced during compilation e If only short word code is produced the attribute has the value Sw e If only normal word code is produced the attribute has the value NW e If both short and normal word code is produced the attribute has the value Mixed New Assembler Switches The following assembler switches have been added normal word code Instructs the assembler not to treat input sections bearing the qualifier PM as if they were SW NWC Same as normal word code short word code Instructs the assembler to treat input sections bearing the qualifier PM as if they were SW SWc Same as short word code swc exclude namel name2 Excludes the named section s from the effect of the swc switch VisualDSP 5 0 Update 6 Release Notes Rev 1 3 Page 6 10 New SECTION Directive Qualifiers There are two new qualifiers for the SECTION directive Sw 16 bit short word section This specifies that the section contains instructions that are to be assembled for loading into a 16 bit short word memory segment Instructions will be assembled as compressed 32 or 16 bit instructions if possible NW Normal word section Instructions will be assembled as normal 48 bit instructions to be loaded into a 48 bit memory segment Unlike the PM section qualifier NW sections will always be 48 bits they are not affecte
203. ts and silicon revisions that require the anomaly 05 00 0311 workaround the macro_ WORKAROUND_FLAGS_MMR_ANOM_311 is defined at compile assemble and link stages 05 00 0311 Anomaly 05 00 0311 is seen when an access of a System MMR Flag register is followed by an access of a specific MMR The result of the anomaly can be that flag pins configured as outputs that are set can erroneously transition to clear The anomaly impacts all revisions of ADSP BF53 123 and ADSP BF561 parts Given some sample application code such as int accessMMR unsigned short w X Y Z x pFIO FLAG D y pFIO MASKA D Z X Y pFIO FLAG C z w pFIO_EDGE pFIO DIR 0 The anomaly safe code would be include lt sys 05000311 h gt int accessMMR unsigned short w X Y Z FIO ANOM 0311 FLAG R x pFIO_ FLAG D FIO ANOM 0311 MASKA R y pFIO MASKA D Z X y FIO ANOM 0311 FLAG W z pFIO_ FLAG C A A FIO ANOM 0311 EDGE R w FIO ANOM 0311 DIR W 0 Note System Service Libraries are anomaly safe for 05 00 0311 See above System Services Release Notes Silicon Anomaly 05 00 0311 section For more information on anomaly 05 00 0311 see the appropriate errata sheet which can be downloaded from VisualDSP 5 0 Release Notes Page 11 lt http www analog com processors blackfin support ICanomalies html gt Problem Charts Problems Addressed
204. ult LDFs also had the problem so user customized LDF based on these older versions of the files may also encounter the error for example see TAR35101 The fix for the problem is to remove the meminit command from the LDF file This can be done by either deleting it or by guarding it with the _ MEMINIT__ pre processor macro defined by the linker when meminit support is actually required For example if defined _ MEMINIT_ meminit ALIGN 4 gt MEM L1 DATA A endif VisualDSP 5 0 Update 2 Release Notes Rev 1 1 Page 2 5 Limitations This section highlights known significant limitations VisualDSP 5 0 ADSP BF54x Known Limitations The following device drivers will be supported in a future update e NAND FLASH driver VisualDSP 5 0 ADSP BF52x Known Limitations The following device drivers will be supported in a future update e NAND FLASH driver Incomplete ADSP BF523 BF525 BF527 silicon rev 0 1 Support TAR 35224 The VisualDSP 5 0 Project Target selections will not allow the option to build for the new 0 1 silicon revisions of ADSP BF523 ADSP BF525 or ADSP BF527 Only Automatic none 0 0 or any can be selected If Automatic is selected and you are connected through an emulator to a revision 0 1 part you will get multiple cc3146 and ea1142 warnings when building your project To avoid these warnings change the Project Target revision selection to any Full support for these new revisions will b
205. und for 05 00 0311 is not safe New information regarding anomaly 05 00 0311 has moved the scope of this anomaly beyond the realm of a VisualDSP Blackfin compiler workaround and into the region of application specific behavior In the VisualDSP 4 5 February 2007 Update the Blackfin compiler runtime VDK and SSL libraries automatically included a new workaround for hardware anomaly 05 00 0311 The VisualDSP 4 5 February 2007 Update C C compiler also automatically enabled this workaround when building for parts and silicon revisions that require it New information about anomaly 05 00 0311 reveals that it is necessary to temporarily disable interrupts during MMR accesses which is a decision the compiler should not be making as it could be disabling interrupts for far too long or during a critical moment when the code relies on receiving one For this reason the implementation of the workaround was changed for the VisualDSP 4 5 June 2007 Update In the VisualDSP 4 5 June 2007 Update the Blackfin compiler runtime VDK and SSL libraries no longer workaround hardware anomaly 05 00 0311 Instead an include VisualDSP 5 0 Release Notes Page 10 file called sys 05000311 h is supplied and contains a group of macros for reading and writing the MMRs if the anomaly applies for the current value of the silicon revision of your target the macro will ensure that the read or write is safe against anomaly 05 00 0311 When building for par
206. urpose as the new VisualDSP 5 0 ones it can be deleted Otherwise the local definition and uses of the local definition will need to be renamed VisualDSP 5 0 Update 6 Release Notes Rev 1 3 Page 6 21 New VSTAT Macro in defBF52x_base h ADSP BF51x BF52x A new macro called VSTAT for the PLL_STAT voltage regulator status bit has been added to the def headers for ADSP BF52x parts If your application contains a macro called VSTAT and uses the ADSP BF52x def include files you will need to change the applications macro and uses to use a different name to avoid build errors or warnings Deprecated IWR Macro ADSP BF51x BF52x The ADSP BF51x and ADSP BF52x Blackfin processor series have two wakeup registers called SIC_IWRO and SIC_IWR1 The ADSP BF54x processor series has three wakeup registers but other single core Blackfin processors designed prior to the ADSP BF54x have only one wakeup register called SIC_IWR If the register name SIC_IWR is used in an ADSP BF51x or ADSP BF52x application the compiler does not issue an error or a warning It uses the legacy definitions contained in the include files def BF51xbase h and defBF52xbase h which define SIC_IWR as equivalent to SIC_IWRO This can be misleading when porting an application from a previous Blackfin processor which has only one wakeup register to a Blackfin processor with two wakeup registers The application may have intended to address all the wakeup bits but by using the
207. us updates Release notes for previous updates can be found at the end of this document Installation This update can only be installed on a previous VisualDSP 5 0 installation If VisualDSP 5 0 is not installed please install it first Installation on a previous update is permitted If a newer update has already been installed please do not install this update This update is not intended to be installed on alpha or beta releases Identifying Your VisualDSP Version The VisualDSP release and update number can be found in 2 locations 7 Inthe Control Panel open the Add Remove Programs applet 8 In the VisualDSP Integrated Development and Debug Environment IDDE select Help gt About VisualDSP Installing the Update Follow the instructions below for installing this update Please note that since VisualDSP supports having multiple instances installed on a single system See the Cloning VisualDSP section below for more information 25 Use the Start Menu to navigate to VisualDSP Maintain this installation By default this is at Start Menu gt All Programs gt Analog Devices gt VisualDSP 5 0 26 Select Go to the Analog Devices website and click Next This will open a window in your web browser 27 Select the appropriate Processor Software Tools Upgrades to match your processor 28 Select and download the desired update VisualDSP 5 0 _Update5 vdu to your hard drive 29 Again use the Start Menu t
208. ut the use of nomemcheck for these parts is also automatically included as they have the same memory map change as ADSP BF518 Using nomemcheck disables linker memory checking so care should be taken to ensure that memory is defined correctly in customized LDFs in ADSP BF51x revision 0 0 applications as any errors will not be caught by the linker One potential issue is when building a project using revision automatic without being connected and then subsequently connecting and loading that DXE to a revision 0 0 ADSP BF51x target is that the will fail This is because automatic causes the tools to build for the default revision which is 0 1 when not connected to target with rev 0 0 This issue can be avoided by explicitly building for revision 0 0 when the target is an ADSP BF51x revision 0 0 part Please review silicon anomaly 05 00 0444 in the ADSP BF51x parts Errata Sheets for details of the memory map change Active CPLBs Blackfin All locked CPLBs will be loaded into the CPLB registers before any unlocked CPLBs instead of just the first 16 as happened previously Error labels too many locked data cplbs and too many locked instruction cplbs Will indicate that there are at least 16 locked data or instruction cplbs respectively and additional cplbs will be locked out Compiler Changes for MISRA Exemplar Suite Blackfin The compiler MISRA checking has been enhanced to improve compliance against the MISRA C 2004 Exemplar Suite
209. utomatically enabled for affected parts VisualDSP 5 0 Update 8 Release Notes Rev 2 1 A compiler workaround for enabled for affected parts System ArchDef BLACKFIN EDN anomaly xml See System ArchDef SHARC 21160 anomaly xml See System ArchDef SHARC 21161 anomaly xml See System ArchDef SHARC 2126X anomaly xml See System ArchDef SHARC 2126X anomaly xml See System ArchDef SHARC 2136X anomaly xml See System ArchDef SHARC 2136X LX3 anomaly xml See System ArchDef SHARC 2137X anomaly xml See System ArchDef SHARC 2146X anomaly xml See System ArchDef SHARC 2146X anomaly xml See System ArchDef SHARC 2146X anomaly xml Page 8 16 instruction that uses the same index register as the register might not be updated with the result of the modify 15000016 When specific PM accesses ADSP 214xx Compiler workarounds and See System ArchDef SHARC which conflict with another core DMA assembler detection 2146X anomaly xml access either the PM instruction or support added both some instructions which follow this automatically enabled for instruction may get corrupted affected parts Also there are various runtime libraries workarounds Silicon Anomaly 05000431 ADSP BF51x 52x 54x Incorrect Use of Stack in Lockbox Firmware During Authentication To use Lockbox and the Device Driver System Services Libraries DD SS distributed with VisualDSP Update 8 the DD SS libraries need to be rebuilt
210. x processor series The linker will place the input sections into a SW memory segment and then translate the objects addresses to the specified memory space The resulting behavior is as if the memory segment was defined as the memory type specified in the output section qualifier Enhanced Disassembly Window Display of Pipeline Stages Changes have been made to the Disassembly Window to provide better information about the instruction pipeline 1 The Disassembly Window now indicates when the instruction in Address or Decode stage has been overridden or had a stall inserted The gutter label of the instruction in that stage will change from upper case to lower case in such instances that is from A to a for Address stage and from D to d for Decode stage 2 The window will show that the pipeline continues to advance while stepping through a non delayed branch in the ADSP 2136x ADSP 2137x and ADSP 2146x parts Previously the arrow indicating the execute stage had stayed on the branch instruction for the three steps following such branches Now the arrow becomes gray and advances with each step following the branch until it becomes a green arrow at the branch target address Project Configuration Additional project configurations are provided for the ADSP 2146x processor series to better support the new Variable Instruction Set Assembly VISA The current Project Configurations set the Assembler Compiler P
211. xpression will not report a rule violation Rule 10 4 Headline rule changed to The value of a complex expression of floating type shall only be cast to a floating type which is narrower or of the same size This has the effect that casting the type of a complex expression to the same type as the complex expression will not report a rule violation Rule 10 5 The headline rule has not changed but the normative text has changed in respect to a cast e Acast is no longer required in all circumstances e Bitwise operations do not require a cast if e immediately assigned to an object of the same underlying type e used as a function argument of the same underlying type as the operand VisualDSP 5 0 Update 3 Release Notes Rev 1 3 Page 3 9 e used as a return expression of a function whose return type is the same underlying type as the operand Rule 12 6 Additional operators and added to the list of operators Rule 19 4 C macros can also expand to a string literal Ability to Suppress all MISRA Rules Checking In some code it is necessary to suppress all MISRA checks New support for pragma diag has been added to make that easy to do to For example pragma diag suppress misra rules all Misra rules all suppressed because TAR 35448 MCMEN Defined in ADSP BF54x Definition Header Files A macro for the SPORTx_MCMC2 Multi channel Frame Mode Enable bit has been added to defBF54x_base h This file is included b
212. xxlExamplesAN 4 4 4 4 Hardware Required VDK 21469 ReadersWriters 4 4 4 4 L4xx Examples L4xx Examples N L4xx Examples N L4xx Examples N L4xx Examples N L4xx Examples L4xx Examples N 14xx Examples 69 InterProcessCommunication_DD 69 LoadMeasurement Hardware Required VDK 21469 ReplaceHistoryLogging Hardware Required VDK 21469 StackOverflowDetection Hardware Required VDK 21469 StatusMonitor Hardware Required VDK 21469 ThreadLocalStorage NONNNNNNN NH E BA DDB BR BR BBB 00 00 00 00 00 ADSP 21371 EZ KIT Lite Update 7 introduces support for the ADSP 21371 EZ KIT Lite complete with a full set of examples 1371 EZ KIT LitelAMD Flash Programmer ASM 1371 EZ KIT Lite AMD Flash Programmer C 1371 EZ KIT LitelBackground Telemetry 1371 EZ KIT Lite Blink with External Memory ASM 1371 EZ KIT Lite Block Based Talk Thru C 1371 EZ KIT Lite Core Timer ASM 1371 EZ KIT Lite Core Timer C 1371 EZ KIT Lite EZ KIT Push Button ASM 1371 EZ KIT Lite Flash Programmer 1371 EZ KIT Lite Power On Self Test 1371 EZ KIT Lite Primes C from External Memory 1371 EZ KIT Lite STMicro SPI Flash Programmer ASM 1371 EZ KIT Lite talkthru analog in out asm 1371 EZ KIT Lite UART echo back ASM 1371 EZ KIT Lite UART echo back C 13xx Examples ADSE 13xx Examples ADSE 13xx Examples ADSE 13xx Examples ADSE 13xx Examples ADSE 13xx Examples ADSE 13xx Examples ADSE 13xx Examples ADSE 13xx Exampl
213. y VisualDSP 5 0 Update 4 Release Notes Rev 1 2 Page 4 12 Anomaly Charts Tools Anomalies Addressed The following table is a list of tools anomalies addressed in VisualDSP 5 0 Update 4 for which details can be found on the public tools anomaly website Other tools anomalies have also been fixed in the Update Details can be found on the Tools Anomaly Web page The URL is http www analog com rocessors tools anomalies Tools Processor Anomaly Family Report Tool Description All 23499 Compiler Misallocation of Local Static Variables All 29851 Compiler section does not apply qualifiers All 30247 Compiler section attribute__ does not work as documented All 36116 Compiler edt and gdt generated when not requested on some PCs All 36188 Compiler Prelinker loops in MISRA mode All 36247 Compiler Incorrect violation of MISRA Rule 10 5 All 36292 Compiler MISRA Rule 17 4 incorrectly reported at run time All 35664 Run Time Libraries The n conversion code may assign a wrong value All 36096 VDK VDK Yield does not reset timeslice DMAx_CONFIG Register Couples DI_SEL and DI_EN In Blackfin 36057 ADspCommon XML Files Display Window compiler XML enables workaround for 05 00 0283 when Blackfin 36093 ADspCommon XML Files unnecessary workaround for 05 00 00371 required for ADSP Blackfin 36266 ADspCommon XML Files BF54 24789 rev 0 0 0
214. y all the platform include files defBF549 h etc The new macro is called MCMEN Any code that defines or uses a macro with the same name will need to be modified to avoid a conflict with the new definition The prior definition of a macro for this bit MCMEM is deprecated It should not be used and will not be supported in future releases TAR 34699 EBIU_AMGCTL Bit Macros in ADSP BF54x Definition Header Files Two new macros for EBIU_AMGCTL to enable all Async memory banks have been added to defBF54x_base h The new macros are defined as follows define AMBEN BO Bl B2 B3 0x0008 Enable Async Memory Banks 0 1 2 and 3 define AMBEN ALL 0x0008 Enable All Async Memory Banks Any code that defines or uses a macro with the same name as these will need to be modified to avoid a conflict with the new definitions TAR 34700 HADMAx_CONTROL Bit Macros in ADSP BF54x Definition Header Files Two new macros for HADMAx_CONTROL bit for source not destination have been added to defBF54x_base h The new macros are defined as follows define SND 0x80 Source Not Destination define nSND 0x0 VisualDSP 5 0 Update 3 Release Notes Rev 1 3 Page 3 10 Any code that defines or uses a macro with the same name as these will need to be modified to avoid a conflict with the new definitions TAR 35154 SIC_RVECT Removed from Definition Header Files The definition of a macro SIC_RVECT has been removed from the various def header
215. you were using Alpha releases of these libraries you would have required project or LDF modifications to link with them These changes will no longer be required when using default and generated LDFs and should be undone Default changed for EBIU_SDBCTL for ADSP BF533 LDF TAR 33491 The default LDFs for ADSP BF533 prior to Update 1 only populated 32MB of SDRAM when enabled unless macro EZKIT_SDRAM_64MB was defined in which case 64MB was used This has changed in Update 1 to make use of the 64MB SDRAM that is on revisions 1 7 and above of the ADSP BF533 EZ KIT Lite The LDFs now default to use 64MB of SDRAM and for revisions 1 6 of the EZ KIT Lite and below macro EZKIT_SDRAM_32MB can be defined to revert to using 32MB Rename MISCPORT register macros in ADSP BF52x def file TAR 33835 Register name changes in the ADSP BF52x Hardware Reference Manual have also resulted in macro name changes in the various ADSP BF52x def and cdef headers in Blackfin include MISCPORT_DRIVE pMISCPORT_DRIVE MISCPORT_SLEW pMISCPORT_SLEW MISCPORT_HYSTERISIS pMISCPORT_HYSTERISIS VisualDSP 5 0 Update 1 Release Notes Rev 1 1 Page 1 6 are replaced with NONGPIO_DRIVE pNONGPIO_DRIVE NONGPIO_SLEW pNONGPIO_SLEW NONGPIO_HYSTERESIS pNONGPIO_HYSTERESIS Sometimes unable to connect to multiprocessor boards TAR 33968 If a multiprocessor board contains a processor with an unknown silicon revision the target could not connect in a multi proce
216. ystem Services and Device Drivers The following are now supported by VisualDSP 5 0 Full System Services Library support for the ADSP BF522 BF525 and BF527 processors Device Drivers for the ADSP BF54x processors VisualDSP 5 0 Update 1 Release Notes Rev 1 1 Page 1 3 o USB Mass Storage OTG Host Device Drivers and Middleware for the BF548 EZ KIT Lite o AD1980 AC 97 Codec Driver for the BF548 EZ KIT Lite o Added SD Write Capability Device Drivers and Middleware for the ADSP BF52x processors o PPI SPI SPORT UART TWI Rotary Counter Background Telemetry USB Mass Storage Device USB Mass Storage OTG Host FAT File System Ethernet o LwiP Device Drivers for the BF52x EZ KIT Lite o LCD o Touch Screen controller o Keypad O O O O O o Integrated Stereo Audio Codec O O O O O Library and Examples to support the SHARC USB EZ Extender with the ADSP 2137x processors VisualDSP 5 0 Update 1 Release Notes Rev 1 1 Page 1 4 New Examples Lockbox The ADSP BF52x and BF54x processors include the new Secure Lockbox Technology http www analog com processors blackfin lockboxSecureTechnology html for Blackfin Lockbox enables secure execution by providing a secure mode of operation in which only trusted code is allowed to execute Two new examples have been added to demonstrate this technology They can be found in the following examples Blackfin Examples ADSP BF527 EZ KIT Lite lockbox Blackfin Examples ADSP BF

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