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SMT148 User Manual
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1. e SHB e RS485 16 pairs e USB x2 e Firewire 1394b x2 e LED x32 Related Documents Texas Instruments Module specification External Interface User Manual this document gathers all the functionalities of the Sundance s firmware implemented on DSP TIMs SMT118 Carrier with 3 Module sites and I O facilities SMT180 Carrier with 8 Module sites Version 1 4 Page 7 of 35 SMT148 User Manual General Description Carrier block diagram TIM site 4 TIM site 1 TIM site 2 TIM site 3 ee ComPorts Global buses HART fie it feats FPGA Virtexll P E Xilinx a ges bees ee ___ _ JTAG configuration chain E JTAG FF896 oii ower In Power Raced management d 100Mhz crystal DAC circuitry ADC circuitry LVDS ee as SHB 22 LED 8 ccs 6 bit 8 er U fuliduplex 400Mbytes s display cho ch7 ch0 ch7 Figure 1 Carrier block diagram Interface XC2VP7 ADC optional DAC yes UART yes LVDS yes RSL optional SHB half optional RS485 optional USB optional Firewire optional LED yes TIM global bus connections yes 20 pins TIM ComPorts yes 4 Table 1 Interfaces Version 1 4 Page 8 of 35 SMT148 User Manual ComPorts interconnections The four TIM sites and the FPGA on the SMT148 carrier card can communicate through ComPorts The following diagram shows the ComPort interconnections Each
2. 12 Power out pinout JTAG A single JTAG chain connects all 4 TIM sites and the JTAG in amp out connectors This chain is used with the TI Code Composer Studio software suite The JTAG out JTAG2 connector can be connected to the JTAG in JTAG1 connector of other SMT148 thus extending the chain see cable SMT503 LED A 8x4 array of LED is connected directly to the FPGA and is controlled by the FPGA firmware Fan Power Eight two pin connectors are provided to supply fans with a 12V supply Reset Scheme A power rail monitor observes the state of the 3 3V supply This device will generate a reset to the SMT148 RESET148 during power up or if the 3 3V supply drops below 3V This signal is an open collector output and is also driven to the inter card ComPort connector and thus to another SMT148 The POR power on reset signal is driven to the RESETOUT pin on the external ComPort1 connector The RESETIN pin on the above connector is buffered by an open collector device which in turn can also drive the RESET148 signal An additional 4 pin header is provided to allow other devices to share the open collector RESET 148 signal The TIM reset pins are connected to the FPGA and will be reset when RESET 148 is active as well as when some firmware conditions trigger a reset to the different TIMs see Firmware description for more details about TIM reset Version 1 4 Page 18 of 35 SMT148 User Manual JOE Connectivity Each TIM site
3. TIM site has two ComPorts connected to the FPGA on the carrier TIM site 4 TIM site 3 CP5 CPO TIM site 1 TIM site 2 CP3 CP3 CP4 CP4 CP1 External External External Gwienna External ComPort5S ComPort1 ComPort2 ComPort3 i ComPort4 i CPO CP1 CP3 CP2 a l l l l I l l l l I l l l I l l l l I I l I l I I l l l I l l l l I l j l l I I I I I l I I l I l I CP5 ja L CP4 Available only on XC2VP20 30 Figure 2 ComPorts interconnection Version 1 4 Page 9 of 35 SMT148 User Manual The external ComPort_1 is accessible on a 26 Way connector 3M which cable SMT502 can be used to connect to a SMT310Q and download application from a PC This connector has the following pin out 1 CSTRB 2 GND 3 CRDY 4 GND 5 CREQ 6 GND 7 CACK 8 GND 9 DO 10 D1 11 D2 12 D3 13 D4 14 D5 15 D6 16 D7 17 3 3V 18 GND 19 RESETOUT 20 GND 21 RESETIN 22 GND 23 NC 24 NC External Comports 2 3 4 and 5 are routed to two SHB connectors Samtec QSH 030 01 to allow connection to another SMT148 carrier and its ComPorts The pin out Table 2 External ComPort_1 pinout is as follow 1 CSTRB_CP2 2 CRDY_CP2 3 S 4 S E DO_CP2 S D1_CP2 9 D2_CP2 3 D3_CP2 S D4__CP2 10 D5_CP2 T D6_CP2 12 D7_CP2 13 Se 14 GE 15 CSTRB_CP3 16 CRDY_CP3 Q CREQ_CP3 19 CACK_C
4. a slave and will disconnect itself from the input node only if it receives the instruction to do so To initialize a transfer or disconnect itself from the input node the DAC interface expects to receive the following 32 bit word 4 consecutive bytes LSB first Bit 31 new transfer initialization if 1 Bit 30 disconnect from input node if 1 will result in a DONE pulse sent to the switch fabric Bit 15 down to 8 sampling ratio The DAC devices are converting data from digital to analogue at a fixed rate of 200 KHz However the user can reduce this converting rate by a factor determined by the sampling ratio value Example if sampling ratio 8 the new conversion rate is 200KHz 8 25KHz Sampling ratio O Sampling ratio 1 Bit 7 down to 0 Channels enable 1 on bit X indicates that channel X will be used 0 that it will not If the DAC interface received a new transfer initialization command the next words will be interpreted as samples One sample is coded on 4 bytes LSB received first Bit 31 must be 0 otherwise interpreted as initialization Bit 30 must be 0 otherwise interpreted as disconnection Bit 23 down to 16 channel to which the sample belongs 1 on bit X indicates that the sample belongs to channel X 16 All the other bits must be set to 0 Bit 15 down to 0 sample value The DAC interface communicates to the DAC device on board using the following signals Please refer to the DAC7742 datasheet for more deta
5. and has the following input and output signals WE output Write enable FULL input Receiver full transmitter must hold transfer DATA output 8 bit data bus DONE input Transfer completed Table 16 Output node IO The output node interface depending on the settings and data it received and detecting that the transfer is completed will assert a completion signal DONE to the switch fabric that will disable the connection between the two nodes ComPorts x8 The ComPorts interfaces are directly connected to the switch fabric and allow communication with external devices and modules using the ComPort or SDL protocol please refer to the SDL Technical Specifications for more details On the switch fabric side the ComPorts must comply with the input and output node descriptions Source As an input to the switch fabric the ComPort interface can access any output resources destinations connected to the switch fabric To enable the connection to a specific destination the ComPort interface must send the right address to the switch fabric and once connected can start streaming data and or control to the output node The ComPort source to the switch fabric also expects one 32 bit word before it can start sending data to the switch fabric Bit 31 never ending transfer if 1 This setting can be useful when the connection needs to always be enabled such as the DSP is streaming data to the DAC via the ComPort without
6. carrier cards can be cascaded and thus creating an embedded system with up to 8 TIM sites and double the number of interfaces The JTAG chain between the two carriers can be enabled by connecting a cable between JTAG2 of the first SMT148 to JTAG1 of the second SMT148 3L Diamond users can also enable a ComPort link between both carriers using an SHB cable SMT511 between JP1 of the first carrier card to JP2 of the second carrier card Checking that the system is functional A DSP Sundance TIM SMT365 SMT376 SMT374 is required to check that the ComPort link between the SMT148 and the host is properly enabled This DSP TIM needs to be fitted on TIM Site 1 of the SMT148 to access the external ComPort 1 connected to JP4 The user should then open the SMTBoardinfo SMT6300 program and launch the Confidence Test Tools menu If the test fails please check the ComPort switch settings Tools Menu and make sure that the External Buffered ComPort is enabled Version 1 4 Page 35 of 35 SMT148 User Manual Running your first application on the SMT148 A DSP module fitted on Site 1 of the SMT148 is necessary to run any application The SMT148 you received has been delivered with an example of 3L Diamond application that accesses some of the interfaces on the SMT148 In addition to the application the application source file test c is available in the 3L folder and can be modified by users at their convenience The example provided shows how the
7. down to 0 This is the total number of 32 bit words that will be sent to the microcontroller interface excluding this word This gives a maximum transfer length of 2426 4 bytes 64Mbytes When the microcontroller interface has received all data it expected from the switch fabric it will disconnect itself automatically by sending a done pulse Polling interrupts The microcontroller is a master over the FPGA It needs to check regularly what the status of the different resources inside the microcontroller interface is Note that a status request can be performed at any time during a transfer from the microcontroller to the interface However a status request during an interface to microcontroller transfer can only be performed when a 32 bit word transfer is complete Version 1 4 Page 25 of 35 SMT148 User Manual Registers and address mapping In addition to being written and read for data transfers the microcontroller interface includes some registers that can be accessed or written by the microcontroller Register command pery Settings write 000 003 Write data 004 007 Read data 008 00B Destination register read 00C 00F Destination register write 010 013 Status register read 014 017 Firmware revision number 018 01B RAM read write 800 FFF Table 17 Register addresses When ordered to read a register the interface inside the FPGA will then be given the bus and will shift out the require
8. on board Receptacle mini fit 8 Way Molex 39 28 1083 18 30V 18 30V 18 30V 18 30V GND GND GND GND 8 NI OO oO B amp B W NM gt Table 11 Power in pinout The mating part to this connector is a Molex 39 01 2080 Farnell order code 151 869 8 off 39 00 0039 Farnell 151 890 The external source is input to a DC DC converter module which produces 12V to the TIM sites It is also used as an input to two DC DC converters that produce the 5V 3 3V 2 5V and 1 5V supply to the TIM sites carrier FPGA and other devices Power Consumption The typical current consumption of an SMT148 LT would be 120mA at 24V For an SMT 148 this would be 280mA These are actual measured values with no TIMs fitted When TIMs are added then the power consumption of the TIMs must be added to that of the SMT148 LT with the SMT148 power supply efficiency taken into account approximately 80 Example Power consumption of SM1T148 LT only 24 0 12 2 88W Power consumption of TIM say 3 3V at 1A 3 3W Total power consumption 2 88 3 3 0 80 7 0W Version 1 4 Page 17 of 35 SMT148 User Manual Power out Power can be supplied to external devices or modules The 8 pin connector Receptacle mini fit 8 Way Molex providing different voltages has the following pinout Pin number 12V 1 12V 2 5V 3 3 3V 4 GND 5 GND 6 GND 7 GND 8 Table
9. protected from damage by fast voltage transients originating from outside the host system which may be introduced through the output cables Short circuiting any output to ground does not cause the host PC system to lock up or reboot Version 1 4 Page 34 of 35 SMT148 User Manual Getting started with the SMT148 Please note that information regarding Power connections and interfaces is not outlined in this section of the document For more details please refer to the relevant paragraphs of this document Connection to the host JTAG connection If you wish to run Code Composer Studio and have access to any DSP present in your embedded SMT148 system you are required to connect a JTAG cable combination of SMT508 XDS and SMT501 JTAG between the SMT148 JTAG1 and the JTAG connector on the front panel of the carrier card hosted in a PC An alternative solution for users who wish to run the JTAG chain from a laptop is to use a PCMCIA JTAG module SMT107 XDS connected to the SMT148 External ComPort cable 3L Diamond users in order to interact with the embedded system for development purposes will require to use an external ComPort cable SMT502 Embedded connected between the SMT148 connector JP4 and a carrier card hosted in a PC On the PC side the ComPort cable plugs into the front panel ComPort connector of the carrier card This cable is also required for running the Confidence Test SMT148 interconnection Two SMT148 embedded
10. GA in both directions thus allowing the implementation of many different schemes The flash device will hold the FPGA and microcontroller firmware The 48MHz clock is required for the use of the USB Each microcontroller will have the following interfaces The second microcontroller interfaces only to a USB connector RS232 and the FPGA The microcontrollers are accessible through a JTAG connector JP10 This is the only device in this chain The pinout is as follow 3 3V TRST TCK TMS TDO TDI OIJ lG IM gt Table 5 Microcontroller JTAG FPGA RS485 UART transceivers RS485 SN65HVD3082E DB25 UART USB Firewire 1394b D USB Microcontroller D connector oxuf922 FireWire connector A FireWire connector B A jumper JP14 enables RS232 when inserted RS485 when removed Figure 6 Microcontroller interfaces uC1 U65 Version 1 4 Page 14 of 35 DCD Rx Tx DTR GND DSR RTS GO ld OQ lO gt CTS LO RI Table 6 RS232 UART DB9 pinout SMT148 User Manual The RS232 cable needs to be a Null Modem cable DB9 1 DCD 14 DCD 2 Rx 15 Rx 3 TX 16 Tx 4 DTR 17 DTR 5 DSR 18 DSR 6 RTS 19 RTS 7 CTS 20 CTS 8 RI 21 RI 9 GND Table 7 RS485 UART DB25 pinout all other pins are not connected 1 USB
11. P3 L DO_CP3 a D1_CP3 a D2_CP3 2a D3_CP3 a D4 _CP3 S D5_CP3 D6_CP3 e D7_CP3 2r NC 28 NC 29 CSTRB_CP4 3 cRDY_cP4 31 CREQ_CP4 32 CACK_CP4 33 DO_CP4 sai D1_CP4 S D2_CP4 e D3_CP4 af D4 CP4 a D5_CP4 39 D6_CP4 ao D7_CP4 ol NC Re NC 714 cstrp_cps 4 cRDY_cP5 33 CREQ_CP5 46 cack cps T DO_CP5 49 D1_CP5 43 D2_CP5 50 D3_CP5 51 D4_CP5 52 D5_CP5 53 D6_CP5 4 D7_CP5 55 NC 56 NC 57 NC 38 NC 59 NC 60 RESET Table 3 External ComPorts 2 5 pinout Version 1 4 Page 10 of 35 SMT148 User Manual Global Bus connections Some of the Global bus signals from the TIM sites are connected point to point to the FPGA on the SMT148 carrier card These 19 bit data communication links can be used for different purposes McBSP HPI interrupts and any protocol could be implemented in order to meet specific requirements The firmware in the FPGA will make use of these links to give more flexibility to the system and thus balance the data control load on the carrier depending on the customer constraints DAC circuitry The SMT148 comprises eight 16 bit low speed DAC channels with a 10V output voltage span DAC7742 200kSPS channel max and internal voltage reference See firmware description for details about DAC control control signals 6 DAC7742 L ch0 DAC7742 FPGA DAC7742 DAC7742 m Analog outputs DAC7742 y DAC7742 DAC7742 e DAC7742 m ch7 Figur
12. SMT148 User Manual Sundance Digital Signal Processing Inc 4790 Caughlin Parkway 233 Reno NV 89509 0907 USA Version 1 4 Page 2 of 35 SMT148 User Manual Revision History Date Comments Engineer Version 31 03 2004 First release PV 1 0 26 10 2004 Added power consumption 02 11 2004 Power connector part numbers clarified 08 03 2006 Removed textual references to VP20 30 08 2006 JTAG header pinout corrected Version 1 4 Page 3 of 35 SMT148 User Manual Table of Contents Revision lt Ts T 2 List of abbreviations sese 5 Tal ats Yale D ELL el TT D Related Documents eee eee ee eee D General Descriptions eee 7 Carrier sale As Tele TT 7 ComPorts anlerGonnecionS cnccccccencscecseeceeeseneueEceomeucnemen 8 GIBB ALIBUS Connections ze at cas tod icc ant dans Serlhiea dd Saris Sarda davik aed daoak Lena oa ed dan evades 10 DAC CUCU soe cece ek Sects ek ce tes ek eh ek ih ek eh ek ih a eh ek ah a ah ek ah el ee 10 ADC Ta TT pete a a ee a e a a ae dae 11 LVDS Tee eT 12 32 bit microcontrollers eee eee 13 is cy ho S CMe dda adad ad aad aaa aI aali aE aal aI aal ado aa 15 MRR PR PSR H er ee cane ee eae ee 15 eal 15 P wers ppleS a e O E E aes anveencasetanaceantanecenetaneceaanecenees 16 AONI Lo AEEA E E T 16 Power Consumption sss sese ee eee eee eee 16 Power QUE 5c ouapedcsantpedarenagedscentnessieseness EE EEE EEEE PE EER eE EEEE EE EES en 17 Hye 17 EIT 17 Fan eT 17 RESELL len TTT 17 NO PaCOnmMe
13. X Tx 1 18 Mepsp Dx Tx1 36 MoBsP Dx Tx 1 GND Ooo da GND Table 4 LVDS pinout default firmware x refers to the TIM site number Each LVDS input pair is terminated with a 100Q resistor The LVDS driver devices are enabled by a signal generated by the FPGA TX_EN each enable controls 2 McBSP ports see firmware description The digital isolators have their own 3 3V power supply with magnetic isolation This 4 8Gb s full duplex link up to 100Mb s per differential pair can be used for different purposes that require LVDS on the external world for long distance communications Data transfers and their associated protocol can be performed and specifically implemented to meet customers requirements e g 4x McBSP channels SPI interfaces interrupts LVDS I oO data control 7 7 channels h N FPGA v z va Digital isolators out Digital isolators in IL715 3B ND LVDS drivers receivers SN6S5LVDS391 x B Magnetic isolation s Or rag 0330 Figure 5 LVDS circuitry Version 1 4 Page 13 of 35 SMT148 User Manual 32 bit microcontrollers The FPGA on the SMT148 carrier card is connected to two 32 bit microcontrollers oxuf922 that enable communication with some of the most widely used standards UART RS485 RS232 USB and Firewire 1394b Data transfers and instructions can be set between the microcontrollers and the FP
14. _ind 2 Data 3 Data 4 GND Table 8 USB pinout 1 NC 2 GND 3 TPB 4 TPB 5 TPA 6 TPA Table 9 Firewire pinout Version 1 4 Page 15 of 35 SMT148 User Manual RS485 16 bi directional RS485 pairs are connected to the FPGA Each byte direction is controlled by the firmware The RS485 driver receivers are connected to a SDB type connector 40 way The connector pinout is as follow GND sz 5 e sa sa 25 26 ser s3 7 a s3 s 27 28 s s to s sto 29 30 stor Table 10 RS485 pinout RSL A RSL link is available on the carrier and can allow users to transfer up to 20Gb s of data in full duplex mode This ultra high speed transfer link uses the dedicated Rocket IO from the Xilinx FPGA Refer to RSL specifications and pinout for more details SHB One 60 pin SHB connector Samtec QSH 030 01 is connected to the FPGA It can be used for debugging purposes and connected to a Logic Analyser using some specific adapters It can also be used as a high speed link to transfer data to the FPGA carrier and TIM modules using the SDB protocol 2x 200Mbytes s For this configuration please refer to SHB documentation Version 1 4 Page 16 of 35 SMT148 User Manual Power supplies Power in Power is supplied from an external source The voltage of the external source needs to be in the range 18V 30V This enters the board via an 8 pin connector JP6
15. civil TTT 18 FPGA CORTMQUIAL OM lt 2 220 rece oe i eee 18 FPGA Firmware description sese see eee 19 eUe 1 slal 20 INPUT NOS SOURCE zi ceca ener ies ee ae ie as ee ae ae es fae te fate tla 21 Output node destination 26 sss 21 COMPOS KG zeera pen ee e pen iae e en actos th Ae A EA TAE A eA TREA EAA TE AEE AEA EEA TE AeA TAART EREE 21 OUNCE E 21 DS SUMAN eere raar EEE EE EEE EE E E ERE 22 WTS eTel TT 23 Interface description sese eee eee eee 23 Lele E A AA A E A A O O A E AE 23 RIZ Te a secretes certs ieee tate ete ete te aa a aa aa a a A 24 Version 1 4 Page 4 of 35 SMT148 User Manual Polling Tais 24 Registers and address mapping sese 25 WVALCMOOQUIMONS x02 dc oon diet ttt ati adit stes dati nds ates dd sti sds steed stu sds steed stu ade re 27 PROSE T 27 DAG acs caseload eee cn EE EE OE 28 PROG ee Sect asceacad r alae easel ae EA Seen E E ised e E A EEA 29 DE ale ac ak we a i a a ae ral E a ta a EE 30 PRS areen eee eE Ee cane cesidesencttceoeaaent veseacGicenkcastveseadGocest cent E EE 30 lal 30 pte foo eee ne ee nN OER URNA RO ERO EMY BN STEAN i a a 30 Global Busan MeBSP virstaa aaa e aaae aed a Raa a Ganda as eaa an 31 Verification Procedures inei n a ae E N ae Eae DE EEE DE 31 R view Procedures aeeie eee eee r aea EaR E yS Ere 31 PCB Layout Details 32 Connectors placement eee eee 33 SAO ee eroe e eer citer alec Scan Sen cent den Scien a Gent ten tcentder GdenGeei aude e ees 33 FEM Caco sacnertetavncave incest cia e
16. controller is able to convey data from a USB Firewire or RS485 232 connection When initiating a new transfer the microcontroller should signal where the data are coming from how much data there is and what the final destination for these data will be The first 32 bit word expected by the interface contains information about the transfer type and the amount of data that need to be transferred to the switch fabric This word needs to be sent to address h000 Bit 31 never ending transfer if 1 This setting can be useful when the connection needs to always be enabled such as the microcontroller is streaming data to the DAC without stopping This bit must be set to 0 if the microcontroller interface needs to be dynamically reconnected to another node at some stage Bit 29 down to 28 Transfer type RS232 00 RS485 01 USB 10 Firewire 1 1 Bit 25 down to 0 This is the total number of bytes that will be sent to the microcontroller interface excluding this word This gives a maximum transfer length of 2426 1 bytes 64Mbytes When the microcontroller interface has received all data it expected it will go in an idle state for 2us before starting a new transfer if instructed to do so This setting is ignored if bit 31 is set to 1 Please note that all nodes connected to the switch fabric transmit and receive information based on 32 bit words All the remaining words part of this transfer will be sent to address h001 The second 32 bit
17. d it meaning that a DONE pulse is sent to the switch fabric Bit 8 indicate the LED value on if 1 off if 0 Bit 4 down to 0 LED address RSL The RSL interface is compliant to the Sundance RSL specifications A fast bi directional data pipe can be connected between the RSL interface and the SHB interface for data conversion from one to the other SHB The SHB interface is compliant to the Sundance SHB specifications and protocol RS485 The RS485 interface is an output node as well as an input node to the switch fabric The first 32 bit word received by this interface defines the transfer direction of the 2 bytes connected to RS485 transceivers on the carrier board It also defines the length of the transfer for both bytes and the address of the output node in the case one of the bytes is set as an output Byte 1 Byte 0 Bit 31 Bit30 bit 15 down to 8 bit 7 down to 0 0 0 Output Output 0 1 Output Input 1 0 Input Output 1 1 Input Input Table 22 RS485 settings Bit 29 down to 16 Bytes transfer length if length 0 the transfer will never end Bit 7 down to 0 Output node address in the case one or both bytes are set as an input to the system On the FPGA IO side in addition to the 2 bytes 2 signals controlled by the settings allow to set the transceivers directions on the carrier Version 1 4 Page 31 of 35 SMT148 User Manual Global Bus and McBSP In the current version of t
18. d register to the microcontroller Version 1 4 Page 26 of 35 SMT148 User Manual Status register Bit 29 down to 28 Transfer type to microcontroller RS232 00 RS485 01 USB 10 Firewire 11 Bit 9 Busy signal active high It indicates that the data path to the switch fabric is busy with a transfer from the microcontroller A new transfer from the microcontroller cannot be started until this signal has been de asserted Bit 8 FIFO to Switch Fabric almost full gt the microcontroller should stop writing data to the interface and wait for this flag to be low again before continuing the transfer Bit 7 down to 0 Number of words in the FIFO to the microcontroller FIFO is 1024 words deep gt the microcontroller can start reading data with a maximum burst size of this number Destination register This register contains the address of the destination connected to the switch fabric when the microcontroller does not know where to send the words it will transmit i e when the microcontroller tries to access a node with address 255 The default value of this register is h40000000 ComPort 0 This register can be written or read by the microcontroller using register addresses Table 17 This register can also be written by any node connected to the switch fabric e g ComPorts when sending the following word to the microcontroller interface Bit 30 must be 1 Bit 7 downto 0 Address of the destination node Firmware revisio
19. different resources on the carrier card can be accessed The settings for the different interfaces have been directly derived from this document s firmware description section In order to recompile the source file open a command prompt in the same folder and type nmake to generate a new app file that can be run in the 3L Diamond server Make sure the TIM type in the cfg file matches with the TIM in your system Please not that 3L Diamond requires a compatible version of Code Composer Studio to be installed on the same PC Extra information you might require for 3L Diamond functions as well as TIM types can be found in the 3L Diamond User Guide Technical specifications and user guides for the different Sundance TIM modules and carrier cards can be downloaded directly from www sundance com The Sundance Wizard Help file is also a great source for pertinent and precise information about Sundance hardware software and systems Updating the FPGA firmware or the microcontroller boot code Refer to the SMT148 microcontroller application note for updating the FPGA or the microcontroller firmware
20. e 3 DAC circuitry Version 1 4 Page 11 of 35 SMT148 User Manual ADC circuitry Eight ADC channels 8x AD7899 1 with a 14 bit resolution and a 10V voltage input span are available on the SMT148 The analog inputs can be sampled up to a rate of 400kHz See firmware description for details about DAC control control signals 6 AD7899 cho 1 AD7899 AD7899 FPGA Analog T 14 bit inputs A r mf L ST k ee Figure 4 ADC circuitry Version 1 4 Page 12 of 35 SMT148 User Manual LVDS drivers receivers 24 LVDS drivers and 24 LVDS receivers are fitted on the carrier card to convert LVDS signals from to LVTTL signals The connectors used for the LVDS signals are four straight NorComp 37 pin D Type 191 037 113 001 In the default carrier FPGA firmware implementation two McBSP connections coming from each TIM site are mapped per connector McBSP_CLKR Tx 0 214 McBSP_CLKR Tx 0 McBSP_FSR_Tx o 22 McBSP_FSR_Tx 0 4 mospr or mor 1 GND ee a 6 moBsp_cikx xor 25 7 msp rsx xor O 26 e msp oxxo z o GND O a pio enn S m owo J 12 MopspclkR 1 3o 13 moBsp esr Txi 1 a 14 moBsP oR Tuir 1 32 s aR McBSP_DR_Tx_0 GND McBSP_CLKX_Tx_0 McBSP_FSX_Tx_0 McBSP_DX_Tx_0 GND GND McBSP_CLKR_Tx_1 McBSP_FSR_Tx_1 McBSP_DR_Tx_1 GND 16 McBSP_cLKxtx1 34 McBSP_CLKX_Tx_1 17 Mosp Fsx Tx 1 35 MoBSP FS
21. eeds to access Bit 31 down to 8 set to 0 Bit 7 down to 0 output node address see table 14 The next words sent to the switch fabric will have the following format Bit 31 down to 24 time stamp This value is incremented by one every time a new sample is available on a specific channel If the receiver detects that 2 samples from the same channel received consecutively have a time stamp difference not equal to one this means that some samples have been lost during transfer Bit 23 down to 16 channel to which the sample belongs 1 on bit X indicates that the sample belongs to channel X 16 All the other bits will be set to 0 Bit 13 down to 0 digitized sample value The ADC interface communicates with the ADC device on board using the following signals Please refer to the AD7899 datasheet for more details nRD Output Read active low nCS Output Chip select active low nCONVST Output Convert start analog input active low CLKIN Output Conversion Clock BUSY Input Conversion is in progress nSTBY Output Standby active low DATA_in Input 14 bit data bus Table 21 ADC interface extra IO Version 1 4 Page 30 of 35 SMT148 User Manual LED The LED interface is only a slave output node and turns on or off the 32 LED on the carrier depending on the settings it receives The LED interface expects only one 32 bit word and will disconnect itself automatically from the input node after it receive
22. he firmware the global bus and McBSP interfaces are directly connected to each other to allow direct McBSP channels connections between the different TIM sites and the external world However in a future revision of the firmware both interfaces could also be connected to the switch fabric in order to increase flexibility The current firmware allows the user to enable or disable the McBSP channels Each receiving or transmitting channel per TIM can be controlled by the DSP user program The receiving signals will be enabled or disabled inside the FPGA whereas this is done directly on the LVDS drivers for the transmitting signals This interface expects to receive a single 32 bit word that will determine the on or off status of the McBSP channels After receiving the 32 bit word it will disconnect itself automatically from the input node by sending a DONE pulse to the switch fabric Bit 25 McBSP channel 1 transmitter enabled if 1 disabled if 0 This setting is ignored if bit 24 is set to 0 Bit 24 McBSP channel 1 transmitter selected if 1 Bit 17 McBSP channel 1 receiver enabled if 1 disabled if 0 This setting is ignored if bit 16 is set to 0 Bit 16 McBSP channel 1 receiver selected if 1 Bit 9 McBSP channel 0 transmitter enabled if 1 disabled if 0 This setting is ignored if bit 8 is set to 0 Bit 8 McBSP channel 0 transmitter selected if 1 Bit 1 McBSP channel 0 receiver enabled if 1 disabled if 0 This setting is
23. ignored if bit O is set to 0 Bit 0 McBSP channel 0 receiver selected if 1 Verification Procedures The specification design requirements will be tested using the following 1 Running Code Composer Studio 2 Test Program Review Procedures Reviews will be carried out as indicated in design quality document QCF14 and in accordance with Sundance s ISO9000 procedures Version 1 4 Page 32 of 35 SMT148 User Manual PCB Layout Details The SMT148 dimensions are as follow 200mmx250mm 7 87 x 9 84 The following picture shows the component placement on the PCB Brews Oe n Glo s o L m m Figure 8 PCB layout details Version 1 4 Page 33 of 35 SMT148 User Manual Connectors placement 1EEE1394 USB RS232 optional optional optional TEA T pe use 4 optional LVDS connectors 1 1 FPGA JTAG Ey header j J RS232 TM O ee optional RS485 TIM Tm TIM Power out TT TM TiM optional i AN Fan headers Power in __ en 12V e n as i j ADC header DAC header JTAG in out ComPorts Reset jumpers optional RS485 optional Safety This module presents no hazard to the user EMC This module is designed to operate from within an enclosed host system which is build to provide EMC shielding Operation within the EU EMC guidelines is not guaranteed unless it is installed within an adequate host system This module is
24. ils RnW output Read not Write nCS output 8 bit chip select active low one nCS per channel nLDAC output Load DAC register to output active low RSTSEL output Tied to 1 output is half scale code when DAC reset nRST output Reset active low nREFEN output Enables internal 10V reference active low Data_to_dac output 16 bit data bus Table 20 DAC interface extra IO Version 1 4 Page 29 of 35 SMT148 User Manual ADC The ADC interface is an input as well as an output node to the switch fabric All eight channels are controlled by this interface It needs to receive settings before it can transmit digitized samples to the interface it was initialized by To initialize a transfer or disconnect itself from the input node the ADC interface expects to receive the following 32 bit word 4 consecutive bytes LSB first Bit 31 new transfer initialization if 1 Bit 30 disconnect from input node if 1 will result in a DONE pulse sent to the switch fabric Bit 23 down to 16 output node address to which the digitized samples will be sent to Bit 7 down to 0 Channels enable 1 on bit X indicates that channel X will acquire data 0 that it will not After the ADC interface has been initialized it will start transmitting the digitized samples through the switch fabric to the specified output node The first 32 bit word sent from the ADC interface to the switch fabric will address the output node it n
25. n number The firmware revision number can be accessed by the microcontroller in order to check what are the version of the current firmware as well as the size of the FPGA The firmware revision number is coded on 8 bits Bit 31 down to 8 reserved Bit 7 down to 5 a revision number before comma Bit 4 down to 2 b revision number after comma Bit 1 down to 0 c FPGA size 00 gt VP7 Version 1 4 Page 27 of 35 SMT148 User Manual Watchdog timers The watchdog timers are used for reset purposes by the different TIM modules in the system Each TIM can access its own watchdog timer and set a time that will elapse before the TIM or all TIM modules are reset The watchdog timer expects 4 words of one byte each The first byte received is the LSB the fourth byte is the MSB After receiving these four words the watchdog timer will send a DONE pulse to the switch fabric in order for the input node to be disconnected The four bytes received by the watchdog timer accounts for a 32 bit word Bit 29 All TIM reset if 1 only one TIM reset if 0 Bit 28 down to 0 number of clock cycles before reset If this number has been set to 0 the watchdog timer is disabled The watchdog timer can be programmed for 1 clock cycle 10ns up to 2429 1 cycles 5 3s Each watchdog timer can be interrupted any time by writing 4 bytes of 0 to it On the switch fabric side the watchdog timer is compliant to interface to an output node The watchd
26. og timer also interfaces to the reset circuitry with the following signals GRESET Output Global reset to all TIM TRESET Output Reset one TIM only Table 18 Watchdog timer extra IO Reset The reset circuitry inside the FPGA is connected to the watchdog timers When it receives a GRESET pulse it will reset all TIM modules for 2420 cycles 10ms When it receives a TRESET pulse it will reset one TIM module for 2520 cycles 10ms The reset circuitry has the following inputs and outputs GRESET1 input Global reset to all TIMs from watchdog timer 1 GRESET2 input Global reset to all TIMs from watchdog timer 2 GRESET3 input Global reset to all TIMs from watchdog timer 3 GRESET4 input Global reset to all TIMs from watchdog timer 4 TRESET1 input Reset TIM 1 from watchdog timer 1 TRESET2 input Reset TIM 2 from watchdog timer 2 TRESET3 input Reset TIM 3 from watchdog timer 3 TRESET4 input Reset TIM 4 from watchdog timer 4 nTIM1RESET output TIM1 reset active low nTIM2RESET output TIM1 reset active low nTIM3RESET output TIM1 reset active low nTIM4RESET output TIM1 reset active low Table 19 Reset lO Version 1 4 Page 28 of 35 SMT148 User Manual DAC The DAC interface is only an output node to the switch fabric and it interfaces to the DAC device on the carrier card All eight channels are controlled and updated by this interface The DAC interface is
27. provides 3 interrupt pins IIOFO 1 amp 2 IIOFO amp 1 are connected in a daisy chain with TIM site 1 IIOFO connected to TIM site 2 IIOF1 TIM site 2 IIOFO connected to TIM site 3 IIOF1 finishing with TIM site 4 IIOFO connected to TIM site 1 IIOF1 All TIM sites IIOF2 signals are connected together FPGA configuration In the default configuration the FPGA is configured by the microcontroller that fetches the configuration in the flash device However it is possible to download a new configuration to the FPGA using the Xilinx JTAG cable connected to a PC and to JP5 on the SMT148 carrier The pinout is as follow 1 3 3V ae OO 4 TCK 5 TDI 6 TDO Table 13 FPGA configuration Version 1 4 Page 19 of 35 FPGA Firmware description SMT148 User Manual The FPGA Virtex Il Pro on the SMT148 carrier card is connected to many different devices and therefore has many internal interfaces that allow it to exchange data or commands with the external world All interfaces are reset at power on or when a manual reset is applied The diagram below shows the interconnections between the digital modules inside the FPGA TIM1 TIM2 TIM3 TIM4 gor SS eye AE TTE thy se sigs E E wa 7 6 N di N 4 7 N I N E E 4 Uf CPO CP1 CP2 CP3 CP4 CP5 CP6 CP7 RESET TIMs t a A t ComPort ComPort ComPort ComPort ComPort ComPort ComPort ComPo
28. rt Global IFO IF 1 IF 2 IF 3 IF 4 IF 5 IF 6 IF 7 m Bus IF1 Global Bus IF2 Watchdog uc timer 1 R Watchdog Global UGT a iE a Gan E Bus IF3 Watchdog S timer 3 E Watchd Global fez 9 T Bus IF4 UC C2 UGZ lt iF McBSP en dis 1 McBSP enidis 2 McBSP en dis 3 McBSP en dis 4 T RS485 IF DAC IF ADC IF LED IF RSL IF R SHB IF DAC ADC LED RSL SHB RS485 Figure 7 FPGA firmware McBSP IF To from LVDS drivers receivers GB1 GB2 GB3 GB4 Version 1 4 Page 20 of 35 SMT148 User Manual Switch Fabric Due to the high number of interfaces to be implemented in the firmware it is important to keep the design scalable and flexible The switch fabric is a digital component that could be seen as a giant multiplexer demultiplexer and that allows to dynamically connect the different interfaces to each others The switch fabric will run on the FPGA system clock 100MHz by default and will therefore not become the bottleneck for any transfer It has multiple input nodes and output nodes operating under a protocol disregarding the specificities of the interfaces it is connected to The node data address bus is 8 bit wide plus few control signals Any input node can target any output node but one input node can be remotely connected to only one output node at a time When a transfer is about to be started by a specific interface input node the first word received on the switch fabric input node will be the address of the o
29. s is the total number of 32 bit words that will be sent to the ComPort interface excluding this word This gives a maximum transfer length of 2426 4 bytes 64Mbytes When the ComPort interface has received all data it expected it will disconnect itself from the input node by sending a done pulse to the switch fabric This setting is ignored if bit 31 is set to 1 Version 1 4 Page 23 of 35 SMT148 User Manual Microcontroller The microcontroller brings great flexibility to this carrier card by enabling USB Firewire and UART RS485 RS232 external communications Its interface inside the FPGA is directly connected to the switch fabric and must therefore comply with the input node and output node descriptions Interface description The microcontroller is connected to the FPGA on the carrier card with the following signals DATA input output 8 bit data bus bidirectional ADDRESS input 12 bit address bus NWE input Write enable active low NOE input Output enable active low NCS2 input Chip select active low The microcontroller is the master device and sees the FPGA as an addressable memory space There is no interrupt signal available between the two devices and in order to catch any event the microcontroller will poll the interrupts from the FPGA regularly Source As an input to the switch fabric the microcontroller interface can access any destination resource connected to the switch fabric The micro
30. ste needed U dacs Mote deena dais dee date kat esate lose teen de vasaty 33 Getting started with the SMITA 34 Connection to the MOST enc scat eee eee eee 34 JTAG connection iesene a a e E a E 34 External ST sla cables becscenscesecessnenerestscsecensnesecenisestcesspesarenencsectneneseereceaciges 34 SMT148 interconnection eee eee 34 Checking that the system is Tunctional sese 34 Running your first application on the SM1148 eee 35 Updating the FPGA firmware or the microcontroller boot Code sese eee 35 Version 1 4 Page 5 of 35 List of abbreviations ADC DAC DSP EPROM FPGA JTAG LED LSB LVDS MSB RSL SDB SHB SPI TIM UART USB Analog to Digital Converter Digital to Analog Converter Digital Signal Processing Erasable Programmable Read Only Memory Field Programmable Gate Array Join Test Action Group Light Emitting Diode Least Significant Bit s Low Voltage Differential Signaling Most Significant Bit s Rocket IO Sundance Link Sundance digital bus Sundance High speed Bus Serial Peripheral Interface Texas Instrument Module Universal Asynchronous Receiver Transmitter Universal Serial Bus SMT148 User Manual Version 1 4 Page 6 of 35 SMT148 User Manual Introduction Overview The SMT148 is a four sites TIM carrier board with external interfaces Connectors are provided to interface to e Analog inputs x8 e Analog outputs x8 e UART RS485 e UART RS232 x2 e LVDS 56 pairs e JTAG e RSL
31. stopping This bit must be set to 0 if the ComPort needs to be dynamically reconnected to another node at some stage Bit 23 down to 0 transfer length This is the total number of 32 bit words that will be sent to the ComPort interface excluding this word This gives a maximum transfer length of 2426 4 bytes 64Mbytes When the ComPort interface has received all data it expected it will go in an idle state for 2us before starting a new transfer if instructed to do so This setting is ignored if bit 31 is set to 1 Version 1 4 Page 22 of 35 SMT148 User Manual Destination Any input node to the switch fabric can access the ComPort interface Please note that a ComPort is a bi directional bus However it is not possible to transfer data in both directions at the same time Therefore if some activity has been detected on the input path to the switch fabric the output path if accessed will raise its full flag when it cannot accept data anymore i e when its FIFO is full The ComPort interface must first receive a 32 bit word of settings In order to be able to start transmitting the data it will receive Bit 31 never ending transfer if 1 This setting can be useful when the connection needs to always be enabled such as the case the ADC streams its data to the same DSP via one of his ComPorts This bit must be set to 0 if the ComPort needs to be dynamically reconnected to another node at some stage Bit 23 down to 0 transfer length Thi
32. utput node it needs to access Three bytes of zeros will then be sent after the address byte The data address control words that will follow will be sent to the output node and must comply with the specific format of the targeted interface Output node Address Hex ComPort_0 TIM1 00 ComPort_1 TIM1 01 ComPort_2 TIM2 02 LED 03 ComPort_4 TIM3 04 DAC 05 ComPort_6 TIM4 06 ucontroller1 07 McBSP TIM1 08 McBSP TIM2 09 McBSP TIM3 OA McBSP TIM4 0B Watchdog timer TIM1 UC Watchdog timer TIM2 oD Watchdog timer TIM3 0E Watchdog timer TIM4 OF RS485 10 ucontroller2 11 RSL 12 SHB 13 ComPort_3 TIM2 14 ComPort_5 TIM2 15 ComPort_7 TIM2 16 ADC 17 Switch Fabric FO Table 14 Output nodes addresses Version 1 4 Input node source The input node is defined as being an input to the switch fabric It runs on the FPGA system clock and has the following input and output signals Page 21 of 35 SMT148 User Manual WE input Write enable HOLD output Receiver is full or already busy with another node hold transfer DATA input 8 bit data bus Table 15 Input node IO Note that all transfers are made in burst of 4 words Therefore the HOLD flag should be taken into account when the burst is completed Output node destination The output node is an output from the switch fabric It runs on the FPGA system clock
33. word sent to the interface and passed to the switch fabric is the destination address coded on the LSB all other bytes must be set to 0 It can Version 1 4 Page 24 of 35 SMT148 User Manual happen that the microcontroller is not aware of the destination of the data it passes to the FPGA If the address sent is 255 hFF the interface will fetch the value of a specific register that can be set by any resource in the system see destination register This register will contain the address of the destination and will be passed to the switch fabric if required In RS232 and RS485 modes only one byte the 1 byte LSB of relevant data is transferred by 32 bit words This has no implication on the firmware However users who for example write a program to be executed on DSP TIM to receive or transmit data from to the microcontroller should bear this in mind Destination The microcontroller can be accessed by any resource connected to the switch fabric It offers the option of streaming data over USB Firewire RS485 or RS232 The first 32 bit word this node will receive will describe the type of transfer it needs to perform as well as how much data will be transferred Bit31 never ending transfer if 1 This bit must be set to 0 if the microcontroller interface needs to be dynamically reconnected to another node at some stage Bit 30 must be 0 Bit 29 down to 28 Transfer type RS232 00 RS485 01 USB 10 Firewire 11 Bit 23
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