Home

1982 , Volume , Issue Oct-1982

1. depth x by 1 assuming the lateral outdiffusion of an layer is the same as the vertical diffusion In a positive photoresist process L is typically 1 9 0 2 um for a 2 mask geometry With nonundercutting dry etching this L value can be reproduced with no more than 0 1 um shrinkage For xj 0 3 um Leg should be 1 1 to 1 5 um for a 2 um mask size In addition to doping the contact region with phosphorus after contact etching to ensure at least a 0 3 to 0 4 m thick n layer at the contact the aluminum metallization is also doped 2 with silicon to avoid problems where the aluminum dissolves some of the underlying silicon material and in some cases can reach a junction and short it out Low temperature phosphorus doped oxide flow To en sure proper metal step coverage at any step the phosphorus doped oxide layer must be softened at an elevated temperature so that it will flow to provide a smoother surface The higher the temperature the smoother the surface is going to be However if the tem perature is too high the diffused junctions will be af fected A 900 C steam process was developed for this purpose so that the overall heat treatment can be kept to a minimum Fig 7 shows the surface topography of the finished devices with phosphorus doped oxide Excellent metal step coverage is achieved here Device Characteristics When an MOS device is operating in the electron velocity satur
2. Semiconductor diodes and transistors are the building blocks of the electronic marvels that make our lives easier more interesting and more productive The semiconductor is usually silicon the main component of beach sand artfully doped with impurities to give it desirable electrical properties Sometimes diodes and transistors come one to a package as discrete components and sometimes many are combined in an integrated circuit single chip of silicon In this age of VLSI very large scale integration there may be MM hundreds of thousands of these devices chip forming a complete microcomputer mem e or other functional system Integrated circuits begin their lives as wafers of silicon Dozens or hundreds of circuits are formed on each wafer in a series of processing steps and then the wafer is cut apart into individual chips which are put into packages ready to be assembled into electronic equipment On our cover this month you can see a wafer and a variety of packaged devices The instrument pictured on this month s cover is the 4145A Semiconductor Parameter Analyzer It s a powerful tool designed to make measurements on transistors and diodes and tell semiconductor manufacturers some ofthe things they need to know to improve device performance and increase yields yield is the percentage of chips that operate correctly when they re completed Parameter measurements are also needed by users of semiconductor
3. 1 ents related to MOS technology and over 20 articles and conference papers about semiconductor device physics and processing Horng Sen was born in Taiwan and is a member of the IEEE and the Electrochem ical Society He is married has three children and lives in Sunnyvale California CKARD JOURNAL 27 OCTOBER 1982 HEWL Copr 1949 1998 Hewlett Packard Co MOS Device and Process Design Using Computer Simulations By using carefully developed computer models device performance can be accurately simulated and the effects of process changes predicted saving time and expense in new product design and development by Soo Young Oh transistors MOSFETs first proposed 50 years ago are based on the principle of modulating longi tudinal electrical conductance by varying a transverse elec tric field Since its conception MOSFET technology has improved steadily and become the primary technology for large scale circuit integration on a monolithic chip primar ily because of the simple device structure VLSI very large scale integration development for greater functional complexity and circuit performance on a single chip is strongly motivated by the reduced cost per device and has been achieved in part by larger chip areas but predomin antly by smaller device dimensions and the clever design of devices and circuits As a consequence of reduced device dimensions a small two dimensional o
4. and Teruo Takeda materials requires an assortment of dc current and voltage sources and monitors To connect these to the device or material to be tested usually requires an array of cables and a matrix of switches As such setting up the equipment for a particular measurement is often compli cated and time consuming In addition the nest of cables and the switch contacts can contribute significant resis tance capacitance inductance and electrical noise com ponents that adversely affect measurement accuracy and speed To minimize these problems and simplify test setups new approach was chosen for the HP 4145 Semiconductor Parameter Analyzer the use of program mable stimulus measurement units SMUs E VALUATION OF SEMICONDUCTOR DEVICES and Stimulus Measurement Unit Each of the four stimulus measurement units in the 4145A is an independently adjustable analog voltage controlled dc port that can be programmed from the 4145A s front panel or via the HP IB to function either as a voltage source and current monitor V mode as a current source and voltage monitor I mode or as a ground refer ence COM mode Also each SMU can be programmed to increment or sweep its output Hewiett Packard interface Bus HP s implementation of IE The main advantage of programmable SMUs is that a device can be completely characterized using only one setup For example a transistor can be characterized in common base common col
5. can be obtained by increasing the base drive current and or the Extending the 4145A s Output Range for Power Transistor Measurements control voltage Vs Fig 3 shows the results of a high power over 40W measurement There are several points concerning safety and accuracy that must be kept in mind when using this method 1 Depending the forward transfer gain hpg of the transistor undertest current levels up to 10A are possible with this setup Be sure to close the lid of the 16058A Test Fixture before starting the measurement and do not touch the connection plate 2 Because of the high current flow there will be an unavoidable voltage drop across the residual resistance of the test leads and cables This voltage drop represents a measurement er ror The actual collector emitter voltage Vcg is calculated as Vce7Vour lourxR where Vour is the 6024A s output voltage is the output current and R is the total residual resistance of the leads cables and test fixture By using the 4145A s remaining SMU and one of its voltage monitors for voltage sensing at the collector and emitter this error can be reduced to almost zero Ap x GRAPHICS PLOT POWER TR 243051 008 Ed VCE 1808 div V Fig 2 Typical graphics display of results obtained with test setup shown in Fig 1 Low voltage Vog characteristics at collector currents up to 10A are easily shown 10 HEWLETT PACKARD JOURNA
6. tration profile peaks at a depth of approximately 0 05 um and tapers off at 0 1 zm The source and drain junction profile is shown in Fig 2c The junction depth predicted by a SUPREM simulation is only 0 2 um However spreading process modeling program developed at Stanford University under the sponsorship ot bath and the Advanced Research Projects Agency Table Nominal HQMOS Process Parameters Polysilicon lineispace width 2 um 1 5 um Metal lineispace width 3 um 2 um Gate oxide thickness 40 nm Diffusion sheet resistivi 40 00 Polysilicon sheet resistivity 35 WO Metal 2 Si Al sheet resistivity 0 03 Metal current density 1 105 Aicm Junction depth xj 0 3 um 2AW 1 8 um 2AL 2xj 0 6 resistance measurements show that a small amount of arsenic doping extends to a depth of about 0 3 um Key Process Development Areas The standard MOS device in 1976 had an effective chan nel length of 6 um with 120 nm thick gate oxide This was reduced to 3 5 um and 70 nm of oxide in 1977 and to 2 um and 40 nm in 1978 Intel s HMOSII process Shorter channel lengths and thinner gate oxides are two key factors in the improvement of the process technology Develop ments making them possible include Fine line lithography The smallest line to line pitch used in HQMOS is 3 5 um with lines 2 um wide and spaced 1 5 um apart on the polysilicon gate level This exceeds the capability of typical 1 1 pr
7. was an aluminum gate p channel process that exhibited low device density and slow speed compared to today s MOS circuits A major breakthrough was the realization of self aligned silicon gate processing This greatly reduced the parasitic overlap capacitance between an MOS device s gateelectrode and its source and drain thus achieving more speed and improving circuit performance Because electron mobility in silicon is higher than hole mobility n channel MOS devices are faster than p channel MOS devices using today s shorter device channel lengths Theuse of n channel technology and the introduction of the depletion mode device as an active load were two other steps toward high speed MOS devices Perhaps the most recent advance in MOS circuit performance has been the development of device scaling theory Reducing the size of an MOS device gains the advantages of shorter propagation Polysilicon Gate Fig 1 HQMOS process se quence a Boron field implant threshold voltage adjustment b After field oxidation c After gate oxidation d Arsenic depletion implant e After buried contact etch f After polysilicon gate def fmm Depletion Mode Transistor Transistor inition g Arsenic source drain implant h After contact oxide etching i Completed structure before final passivation step OCTOBER 1982 HEWLETT PACKARD JOURNAL 21 Copr 1949 1998 Hewlett
8. BS degree in physics electronics awarded by the University of Manchester United Kingdom in 1979 His work at HP is concerned with NMOS process development Dev was in Kingston Jamaica and now lives in Mountain View California He enjoys playing soccer riding bicycles working with computers and playing guitar 3 Anders T Dejenfelt Anders Dejenfelt was born in M rard Malm Sweden and attended Lund In stitute of Technology Lund Sweden eaming MS degree in applied physics in 1977 After two years doing development work in Sweden on high power thyristors he joined HP in 1979 as amemberof the technical staff at HP Laboratories Until he left HP recently to work on custom IC designs his work involved MOS device characterization and modeling Anders is a member of the IEEE and lives in Los Altos Califor nia He is interested in fast cars board 1 sailing playing guitar and skiing Horng Sen Fu Horng Sen Fu received the PhD degree in electrical engineering from the Uni versity of Illinois at Urbana Champaign in 1971 He performed research on MOS devices and physics there until 1973 He joined HP in 1978 after five years of doing R amp D work on CCD memories for a major semiconductor manufacturer Horng Sen is now a proj manager in HP Laboratories re sponsible for developing high Performance NMOS devices and cir cuits His work has resulted in eight pat
9. Packard Co delay and lower power dissipation without losing the basic operating characteristics of its original size If the feature size linewidth is shrunk by a factor k k gt 1 then the propagation delay is divided by k power dissipation by k and delay power product by k Thus it is possible to achieve high speed low voltage MOS operation that com petes directly with bipolar devices HQMOS Process The HQMOS process is a scaled down version of a stan dard n channel MOS process Because the feature sizes are smaller new patterning and etching techniques are re quired For example polysilicon gates contacts and aluminum lines are formed by state of the art dry etching processes A 10 1 optical projection wafer stepper and mask aligner and a positive photoresist process are also needed for all photomasking levels to define the narrow lines and spacings Several innovative processing techniques such as a new buried contact scheme for thin gate insulators a three step contact etching process and a low temperature steam process to flow phosphorus doped oxide were de veloped and implemented Fig 1 shows the major process ing and masking steps of the HQMOS process with the exception of the seventh and final masking step that defines the windows through the top passivation layer to the metal bonding pads Because junction and line capacitances are major factors contributing to circuit delay it is important that parasitic c
10. SMU is inductive in V mode oper ation and usually several SMUs are connected to each other through the DUT ES te gt There are two sources of SMU oscillation one related RE Fig 6 a SMU output circuit b Equivalent circuit for OCTOBER 1982 HEWLETT PACKARD JOURNAL 19 Copr 1949 1998 Hewlett Packard Co b V Mode Fig 7 a Output impedance circuit of SMU in the I mode b Output admittance circuit of SMU in the V mode solely to the output stage of the SMU and the other related to overall SMU construction when operating in the I mode current forcing and voltage sensing Fig 6a shows a simplified drawing of the SMU output circuit Here C is the capacitance between the center conductor and the inner shield of the triaxial output cable Redrawing Fig 6a we obtain Fig 6b If the Q of the C L circuit exceeds unity this circuit will oscillate at a frequency of 127 VC L Fig 7 shows the equivalent circuit of an SMU operating in the I mode The output impedance of this circuit Zou is R 1 o CR R o CR o TREE RT SML ET a CERT 9 1 wCR 1 wCR where w is the resonant frequency of the system consisting of two amplifiers Thus if gt 1 the equivalent series resistance of Zout is negative If an inductive load is con nected that cancels the equivalent series capacitance of Zout this system will oscillate What is the chance of being connected to an i
11. are approximated as follows on the condition that fj fr T 21 Y EC ra 6 fr a 1 eS nina 2 i joc 7 1 2 OCTOBER 1982 HEWLETT PACKARD JOURNAL 17 1949 1998 Hewlett Packard Co amp Thus with the guard filter the additional admittance be comes a capacitance of without a negative resis tance and only the feedback of the output current compo nent lags at high frequencies Moreover the additional capacitance C which appears in parallel with the load contributes to stability in the current control mode The low pass characteristics of the guard filter also func tion to surround the center conductor of the triaxial cable with an equipotential surface Current Ranging Current ranging in each SMU is performed automatically so that optimum accuracy is assured This requires a spike less current range change scheme to prevent sudden changes of output voltage during a range change that can adversely affect a sensitive DUT SAW A novel soft switch scheme shown in Fig 4 is used in the 4145A to control current ranging By turning 01 on or off a range resistance of 10 or 1 can be selected To maintain the SMU output current at 10 n when switching range resistance from 1 GN to 10 the voltage across the range resistor V Vg must change between 10V and 0 1V as shown in Fig 4 The maximum change rate
12. born in Kagoshima Japan and received his BSEE and MSEE degrees from Tokyo Institute of Technology in 1972 and 1974 He joined Yokogawa Hewlett Packard in 1977 and worked on the 4140B pA Meter Voltage Source and designed the digital section of the 4145A mainly the software He enjoys playing the guitar and the recorder Fig 11 Each 41454 comes complete with the HP 160584 Test Fixture cables and connector plates Also included not shown are five system discs and a head cleaning disc Copr 1949 1998 Hewlett Packard Co Teruo Takeda received his BSEE and married and enjoys working on audio equipment and singing design and Kazunori Nishitsuru and Hideyuki Norimatsu for application evaluation We would like to express our appreciation to Ulrich Kaempf of HP s Integrated Circuit Processing Laboratory who introduced us to the SMU con cept Special thanks are also due Haruo Ito our section manager who gave us the original idea of the product and many useful suggestions To many other people not men tioned here who contributed to the product s development many thanks Reference 1 K Hasebe W R Mason and Zamborelli Fast Compact High Quality Digital Display for Instrumentation Applications Hewlett Packard Journal Vol 33 no 1 January 1982 Programmable Stimulus Measurement Units Simplify Device Test Setups by Susumu Takagi Hiroshi Sakayori
13. circuit performance can be simulated by HP SPICE based on electrical parameters and capacitances that were obtained from the process schedule and device layout using this simulation system Application Examples An example of an application of this simulation system is the scaling down of a standard n channel MOS process see zi Lol um 1285 15 20 25 103 10 41 10 41 5 EA 2 aes 10 44 10 24 10 44 a oo 05 Vos V Fig 6 Effects of variations in effective channel length on subthreshold MOS device characteristics Copr 1949 1998 Hewlett Packard Co article on page 21 from 2 5 um to 1 5 um The impurity distribution simulated by SUPRA for the standard NMOS process is shown in Fig 3 To simulate the scaled down process the mask channel length is first reduced from 2 5 um to 1 5 um while all the process steps remain the same Fig 4 and Fig 5 show the simulated potential distribution of 2 5 and 1 5 um channel length devices with V 0 2V Vps 3V and Vgs 2V Because stronger two dimensional field cou pling is evident in Fig 5 where the mask channel length is shorter the threshold voltage is lower for the shorter device In Fig 6 the Ips versus Vcs characteristic is simu lated by GEMINI for various channel lengths to show the ef fect of channel length on The Vy of a 1 5 device is shifted by 0 34V from that of a 2 5 um device Next the gate oxide is scaled down fr
14. from x1 to X10 requires no special circuitry During current ranging a control signal called Loop Cut is fed back to the I and I error amplifiers to inhibit their override capability and ensure SMU control by the voltage error amplifier When I Loop Cut is enabled the other changes inherent to thecurrent ranging such as the analog input which must be changed to correspond with the new range factor are done in a predetermined manner by the SMU controller If the SMU is operating in a current control mode before the change the input reference voltage Vin is modified step by step until the SMU reaches its voltage control mode At the instant of detecting the SMU control mode change the I Loop Cut signal is asserted and Vin is held constant so that the current ranging is done at the same actually a little less in magnitude output current Control Mode Change Each SMU has three control amplifiers They are the voltage error I error and I error amplifiers and the con trol modes they monitor are called the V control mode I control mode and I control mode respectively One of them is selected in accordance with the input reference voltage and feedback signal levels In each of the SMU control modes the error amplifiers not used are completely out of the control loop and do not affect operation How ever they are in a standby condition ready to take over SMU control at the instant that the feedback level to any standby error
15. input level and fed back to the I error amplifier and the I error amplifier Five range resis tors and the selectable gain factor X1 or X10 of the current float amplifier provide the wide output current range 1 pA to 100 mA of the SMU with excellent accuracy The connection of the SMU output to the DUT is made by a triaxial cable whose inner shield is connected to the volt age follower output so that it surrounds the center conduc tor with an equipotential field The outer shield is con nected to the low impedance circuit common This config uration effectively prevents the SMU output s picking up undesired noise This is particularly important in low current measurements where the noise level can exceed the signal level by several decades Guard Filter The guard filter is a novel approach implemented in the 4145A SMUs It contributes greatly to stable oscillation free SMU operation especially in the very low current ranges Fig 3 shows a simplified schematic of the output circuit of the SMUs and the equivalent circuit The guard capacitance C consists mainly of the capaci tive coupling between the center conductor and inner shield guard of the triaxial cable Y and Y in Fig represent the additional admittances of C that appear in parallel with the range resistor R and the load R spectively In equation form Y joC 1 F o F o 1A 2 where F is the transfer function
16. monitor names only and physical constants electron charge Boltzmann s constant and vacuum dielectric con stant can be used in the equation defining a user function User functions are executed during measurements and the calculation results can be displayed in the same manner as the measurement results Keyboard calculations can be made at any time simply by keying in the expression and pressing EXECUTE All of the arithmetic functions available for user function definitions can be used Also keyboard calculations can be performed in conjunction with the dis play marker For example if the expression Ic Ig is executed when the marker indicated by the symbols e and is positioned at 0 9 as shown in Fig 7d the value of the expression at this point will be displayed on the bottom line of the CRT not shown in Fig 7d Systems Use The 4145A is equipped with the HP IB and almost all measurement functions are remotely programmable There fore the 4145A is a powerful component for a semiconduc tor measurement system For more sophisticated users the 4145A has a special user mode In this mode an operator can control the SMUs voltage sources and voltage monitors directly and use the CRT as an independent graphics plot ter The operator can use the powerful HP GL commands and graphics utilities of HP s desktop computers to build a user oriented dc parameter measurement system easily The 4145A s PLOT function dumps all i
17. of Vp versus time is determined by the response of the voltage control loop The range resistance value cannot change faster than the response of the voltage control loop without causing a transient change in V This is prevented by applying to the gate of Q1 a ramp voltage whose slew rate is slow enough to allow Vp to change in step with the change in range resistance During this change the output voltage V is kept nearly constant by the voltage error amplifier However a small Vo Vin Pin Fig 5 a Schematic of the SMU current control amplifiers b Output characteris tics of the voltage and current control amplifiers 18 HEWLETT PACKARD JOURNAL OCTOBER 1982 Copr 1949 1998 Hewlett Packard Co amount of output voltage disturbance is required to supply the feedback loop current to change V as calculated by 8 VF Sa ICR ae TE GR On where f is the total gain bandwidth product of the voltage control system In the 4145A the gain bandwidth prod uct of the SMUs is 200 kHz and the ramp rate of the soft switches is 5V ms Thus AV is only 4 0 mV The ramp signal is referenced to or V whichever is more positive so that a single n channel FET can handle the slew rate limited current ranging for both directions of output current The current range which is selectable simply by chang ing the gain of the current float amplifier Fig 2
18. of the guard filterand Ay is the open loop gain of the voltage follower whose power supply is referenced to the power amplifier output When the guard is connected directly to the voltage fol lower output equals 1 and equations 1 and 2 become 0 3 1 joCy 1 2zFpja 4 where fy is the gain bandwidth product of the internally compensated voltage follower At frequencies much less Fig 3 a Simplified schematic of guard filter b Equivalent circuit for a 10 1 60210 nA AVe b Fig 4 a Schematic of soft switching circuit for current rang ing with negligible effect the output voltage b Voltage relationships for circuit shown a during range change than fy wiC 2nty 5 The total range admittance Y 1 R Y becomes negative for frequencies above 500 Hz given a range resistance of 1 GQ guard capacitance of 500 pF and fy of 1 MHz for instance This means that the feedback component of the output current is not negative but positive above 500 Hz This indicates that stable SMU operation totally free from oscillation is not possible without changing parameters that would sacrifice SMU performance speed resolution et cetera The simple low pass guard filter provides the solution without degrading SMU performance At frequencies above the cutoff frequency f of the low pass filter and Y
19. records data files 12 records and sequence files 1 record Up to 43 program files can be stored on each disc Each file has a unique name 6 characters maximum The following commands and the catalog function see Fig 6 are provided for management of these user files SAVE PDS Filename storing user files GET PDS Filename for retrieving user files PURGE IDS Filename for purging user files REPACK for repacking the user area P indicates a program file D indicates a data file and S indicates a sequence file Instrument Operation There are two important points to consider when design ing a keyboard operated instrument One is simplicity and ease of use making the measurement complexity trans parent to the inexperienced or casual user The other is versatility for more experienced users and sophisticated measurements The operating system of the 4145A is designed to perform wide range of operations with menu driven softkey oriented control The measurement procedures are divided functionally into four parts that are each displayed in a menu page format CHANNEL DEFINITION SOURCE SET UP MEAS amp DISP MODE SET UP and DISPLAY see Fig 7 These pages can be accessed sequentially by pressing the PREV or NEXT keys and directly from the menu page by pressing the appropriate softkey The user sets up or programs the measurement by filling in blanks on each menu page The 1 R FILE CATALO
20. scaled down version of a standard n channel MOS process resulting in lower power consumption and higher speed by Horng Sen Fu Roger To Hoi Szeto Anders T Dejenfelt and Devereaux C Chen the most rapidly changing technologies in modern society Among major semiconductor device tech nologies such as bipolar MOS metal oxide semiconduc tor and or II VI compounds MOS has probably ad vanced the fastest in recent years especially during the past decade Silicon processing technology on which most bipolar and MOS devices are based has emerged as a major manufacturing technology mainly because of the ability to grow high quality silicon dioxide This greatly reduces de vice fabrication difficulty Although and II VI com pound technologies have made major progress in recent years they still cannot compete with silicon technology because of material preparation and device fabrication problems Bipolar devices have been traditionally recognized as superior to MOS devices in speed because of fundamental differences in device structure and operating principles This tradition has changed recently because of advances in S EMICONDUCTOR DEVICE TECHNOLOGY is one of Boron implant 45 nm Stress Relief Oxide t Field Oxide 525 nm Pass Gate Oxide MOS processing that now allow MOS to achieve a faster access speed than its bipolar counterpart Back in 1969 the standard MOS fabrication technology
21. short channel and narrow width effects This may not be a prob lem if the ideal scaling down theory is followed because in concept all dimensions and impurity profiles are scaled so as to maintain the same electric field pattern as for a long channel device However this is not typically fol lowed because of practical limitations such as retaining a standard 5V operating voltage and requiring thicker oxides to prevent gate breakdown Device characteristics are highly dependent therefore on the two dimensional struc ture classical analysis based on the one dimensional model is not valid Conventional process and device designs for integrated circuit technologies have been based on the use of a trial and error approach and simple analytical modeling to achieve the desired electrical characteristics and circuit performance The left half of Fig 1 outlines a systematic SUPRA Fig 2 Block diagram of two dimensional simulation system Copr 1949 1998 Hewlett Packard Co procedure process device and circuit design using both trial and error and experimental measurement This ap proach is not adequate however for small geometry MOS FETs where process complexity especially patterning and tolerance requirements and two dimensional field cou pling prevent the use of a simple one dimensional analysis for obtaining accurate quantitative information In addi tion the purely experimental approach yields littl
22. this equation we find that the relationship between V Ip and Vas ls linear the slope of the line is and the point at which the line crosses the X axis is Vy Thus Vip VB Vos Vj Tne 4145A s user function can be set up to perform this calcula tion during the measurement From Fig 4 X INTERCEPT shows of 2 17V The square of the line GRAD is 8 566 x 107 source and voltage monitor 1 mode In the V mode SMU can supply from 1 mV to 100V over three output ranges as given in Table I In the I mode currents as low as 1 pA and as high as 100 mA can be forced as listed in Table II If higher currents or voltages are required an SMU can be used to program an external power supply see box on page 10 One advantage of the SMU concept is that a four terminal device can be completely characterized by the 4145A without changing connections For example a bipo lar transistor can be characterized in common base common collector and common emitter configurations without any connection changes See the article on page 15 OCTOBER 1982 HEWLETT PACKARD JOURNAL 7 Copr 1949 1998 Hewlett Packard Co Table SMU Output Capability V Mode Voltage Maximum Range Resolution Accuracy Current I 20V 1mV 0 1 of reading 100 mA 40V 2mV 0 05 of range 50 mA 100V 5 0 40x1 20 mA 1 output current at set voltage Table Il SMU Output Capability Mode Current Reso Maximum Range lu
23. 6058A Test Fixture Fig 11 is furnished with the 4145 The 16058A holds the device to be tested and pro vides all necessary connections to the test input output terminals of the 4145A For stable and accurate measure ments at extremely low current levels the 16058A is fur nished with an electrostatic light shielding cover This coveris also a safety feature to protect users from hazardous voltages When the cover is open output voltages are lim ited to 42 volts automatically To facilitate testing various types of devices eight interchangeable socket boards and three types of special plug leads are furnished Acknowledgments The authors wish to thank Hiroshi Kanamori and Hideyuki Hasegawa for developing the digital hardware and software Akinori Maeda for power supply design Yoshimasa Shibata for mechanical design Tsuneji Nakayasu and Akihiko Goto for test fixture and industrial Jin ichi Ikemoto Jin ichi Ikemoto received the BS 1972 and MS 1974 degrees in electrical engineering from Waseda University With Yokogawa Hewlett Packard since 1974 he has worked on automatic test systems in the computer group for about three years Since joining the R amp D lab he has contributed to the de sign of the 4191A RF Impedance Analyzer and designed the main pro cessing HP IB and mass storage sec tions ofthe 4145A Jin ichi is single and enjoys playing the guitar and swim ming Fumiro Tsuruda Fumiro Tsuruda was
24. 949 1998 Hewlett Packard Co
25. G lable records 25 name typ comments adcs rev usd GEN sys system 5 B sys system 220 33 sys system 093 929 sys system 2oE grs Seq DEMO 1 53 Seq DEMO 2 1 Seq FOR T D 231 1 1 Seq FOR 232 1 1 Pro APP 1 233 zi S Pro 2 236 3 3 Pro APP 3 239 3 3 Pro APP 4 242 3 3 Fig 6 Typical directory listing of files stored on a flexible disc Each disc contains the operating system for the 4145A in addition to saved user programs and stored data OCTOBER 1982 HEWLETT PACKARD JOURNAL 9 Copr 1949 1998 Hewlett Packard Co Each of the 4145A s stimulus measurement units SMUs is capable of supplying up to 100 mA or 100V with a maximum power output of 2W This is more than sufficient for stimulating and measuring low power semiconductor devices which account for perhaps 90 of semiconductor products To cover the remaining 10 which consists mainly of power transistors and diodes the 4145A s output capabilities must be increased This can be ac complished simply and economically The method requires no controller or interface The only equip ment needed is the 4145A its furnished accessories and a suit able power supply that can be controlled by an analog voltage and has a current monitoring terminal such as HP s 6024A Auto ranging DC Power Supply Fig 1 shows the setup Fig 1 Test configuration using HP 6024A Autoranging DC Power Supply controlled by the 4145A s SM
26. KARD JOURNAL OCTOBER 1982 Real Time Monitor Utilities Analysis Task Fig 4 The software architecture of the 4145A is based on a real time monitor to control the utilities and four priority levels of tasks ASP Autosequence program time monitor whose functions are as follows Task management multitasking A task is the primary structure of an execution environment under the real time monitor The monitor supports multitasking opera tions with four priority levels Eight tasks are available for each level Task management services include start end and abort Task synchronization Tasks can communicate informa tion to another task via an event control block which is managed by the real time monitor and not visible to a task programmer The receiving task calls the WAIT mac rocommand with the event control block number The sending task calls the POST macro with the event control block number and a post code Program management Certain tasks are resident on the flexible disc If one of these tasks is required but is not already in the overlay area see Fig 5 the program man ager loads the appropriate file containing the task and starts it Timer services The real time monitor can periodically initiate execution of a specified task This is a very impor tant function for measurement instrumentation The monitor can also suspend task execution for a specified interval and initiate executi
27. L OCTOBER 1982 Copr 1949 1998 Hewlett Packard Co me SS 1100 Se dtv _ B 42 08 vc 4 288 dwv v gt Fig 3 Result of a high power measurement using the setup Fig 1 The control voltage is swept from OV to 3 5 in 0 07V steps and lg is swept from 1 mA to 9 mA in 2 steps To do this however the test setup and the user function calculating Vcg must be changed slightly Fig 4 SMU 4 is Connected to the collector of the transistor and set up in the mode as a constant current source at 0 0A with a compli ance of 100 00V This allows it to behave as a voltage moni tor One of the 4145A s two voltage monitors is connected Fig 4 Revised Fig 1 setup to correct for voltage drop error introduced by high current flowing through the test leads and connectors By measuring the voltage across the transistor directly using SMU 4 and VM 1 this error can be eliminated to the emitter of the transistor and the user function for Voe is changed from Vce 12xVs to Vce Vyi Ve 3 Wait until the transistor has sufficiently cooled before making additional measurements Heat generated by high current flow drastically affects the transistors parameters espe cially and Icgo Thus if the measurement is repeated be lore the transistor has cooled measurement results will differ significantly 4 Set the 4145 to MED or LONG integration time to
28. OCTOBER 1982 JURNAL HEWLETT PACKARD J IIIILII GRAPHICS PLOT EXTN MOSFET ID AND GM VERSUS VG 10 GM CURSOR 2 S52B81V 19 67 1 85E 03 S gt MARKER 1 6800V _ 2 725mA __ s STORE 1E 02 4 303 E 3 RECALL 4303 decade Zd i v COMMNT div 1 GRAD 112E 3 1 67E 00 919 12 333338 HEWLETT PACKARD JOURNAL Technical Information from the Laboratories of Hewlett Packard Company OCTOBER 1982 Volume 33 e Number 10 Contents Intelligent Instrument Streamlines dc Semiconductor Parameter Measurements by Kohichi Maeda Jin ichi Ikemoto Fumiro Tsuruda and Teruo Takeda Curve tracer mea surements take a quantum leap forward in accuracy and ease of use Programmable Stimulus Measurement Units Simplify Device Test Setups by Susumu Takagi Hiroshi Sakayori and Teruo Takeda Each SMU be electronically set to supply a specified voltage or current and to measure the associated current or voltage HQMOS A High Performance NMOS Technology by Horng Sen Fu Roger To Hoi Szeto Anders Dejenfelt and Devereaux C Chen Smaller NMOS devices operate faster and use less power Some process innovations are required to make them MOS Device and Process Design Using Computer Simulations by Soo Young Oh effects of design changes can be accurately predicted by the proper computer model elimi nating the need for actual fabrication In this Issue
29. SAVE P Filename Measurement data is stored in the data buffer 2304 bytes The measurement control block and the data buffer can be stored on the disc by the command SAVE D Filename The UF object and stack area 256 bytes is used as an intermediate code area for user functions and as a stack area for RPN Reverse Polish Notation operation The in termediate code of the autosequence program is resident in the ASP object area 256 bytes This area can be stored on the disc by the command SAVE S Filename Nonresident tasks and data are loaded into the overlay area by the real time monitor before execution Resident tasks common data and utilities are loaded into the system resident area at instrument power on The 4145 uses an internal single sided single density flexible disc drive to store system programs measurement data and user programs The disc space is divided into a system area and a user area see Fig 5b The system area consists of a system label 12 system files and a directory Files in the user area are organized by an indexed access method The size of each system file is 4K bytes including tasks utilities and data The directory is provided for user area management with a spare directory for backup The size of the directory is 2K bytes The user area has room for 143 records 256 bytes record The first 12 records are reserved for system default pro grams The 41454 has three types of user files program files 3
30. Us effectively boosting the output current and voltage range of the 41454 for power transistor measurements Three of the 4145A s SMUs are used SMU 2 programmed to function as a variable current source drives the base of the transistor being measured SMU 1 programmed to function as a variable voltage source is connected to the 6024A s remote Control analog programming terminal A2 to provide the voltage necessary to control the 6024A s output voltage Output voltage from the 6024A is directly proportional to the voltage supplied by SMU 1 and can be calculated as Veozsa 12Vg Voe 1 Thus by sweeping the SMU 1 voltage from OV to 5 the 6024A s output can swept from OV to 60V SMU 3 pro grammed to function as a voltage monitor is connected to the 6024A s current monitor terminal A4 6024A s output current is directly proportional to the voltage V measured at this terminal by SMU 3 and can be calculated as legas 7 2XV ul 2 The 6024A s outputs are connected to the collector and emitter of the transistor as shown in Fig 1 By using the two internal user functions of the 4145A to calcu late the output voltage and current by equations 1 and 2 the actual values applied to the transistor tested can be displayed directly The results of an actual measurement using this setup are shown in Fig 2 Maximum current through the transistor is approx imately 1A and power is close to 1W Higher current and power
31. amplifier is about to exceed its input reference Fig 5 shows a simplified schematic of the voltage I and 1 error amplifiers and their output characteristics The con struction of the I and I error amplifiers is almost identical to that of the voltage error amplifier except that the values of the current sources are appropriate to overridable and one sided control and their outputs are connected to that of the voltage error amplifier All three are connected to the input of the power amplifier which develops the specified output voltage or current to the load through the range resistor When output of U1 is near zero the voltage error amplifier controls the total loop so that the output volt age is proportional to Vi and the SMU works in its volt age control mode v varys from near zero to maintain the desired output voltage until it reaches a level equal to two diode forward voltage drops At this time a current i flows in the internal feedback loop of the voltage error amplifier and it can no longer control the SMU output voltage Then control by the I or I error amplifiers is established and the SMU s output current is proportional to the voltage V _ to the I and I error amplifiers The voltage error amplifier U1 is not saturated at this time but is operating with a local feedback current i to prevent saturation of the voltage control loop and set near its control level by twice the diode forward age drop F
32. an n region or polysilicon The first wet etching step clears about one third of the total oxide JOURNAL thickness with some undercutting The dry etching re moves all of the remaining oxide except the last 50 nm which is removed by wet etching This last wet etching step overcomes the poor selectivity of the dry etch step and also widens the edges of the contact area slightly to achieve the desired oxide slope A slope of 50 to 60 degrees is obtained routinely by this method Dry etching of aluminum The etch gas is a mixture of CCl He similar to that used for polysilicon etching The VLSI Buried Contact Process Standard Buried Contact Process Silicon a 1 Gate Oxide Photoresist Polysilicon 2 9 Fig 5 Comparison of the new buried contact process with conventional process a Gate oxide formation b First polysilicon deposition Buried contact masking First polysilicon etching e Contact oxide etching f Resist strip ping residue oxide etching second polysilicon deposition g Polysilicon gate patterning and etching Copr 1949 1998 Hewlett Packard Co Gate Source Drain e t ae 4 us a L 1 Fig 6 Cross section of an MOS trans typical etch rate is approximately 150 nm minute at RF power levels from 300 to 800 watts with b
33. apacitances be kepttoa minimum A lightly doped silicon substrate helps reduce junction capacitance HQMOS sub strate material is p type has a lt 100 gt surface orientation and has a resistivity of 17 to 35 ohm cm This corresponds to a boron doping level of 4 to 8x 10 cm A boron implant is required to adjust the threshold voltage of the MOS tran sistors and to prevent source to drain punchthrough This implant is done before the polysilicon deposition and is subject to all subsequent heat treatments A thin layer of stress relief oxide approximately 45 nm thick is grown first on the fresh surface of the starting wafer A 150 nm thick film of high quality silicon nitride is deposited on top of the stress relief oxide A 1 1 4m thick layer of positive photoresist is applied and patterned by photolithographic means to define the active device regions CF4 O plasma is used to etch the nonmasked silicon nitride areas A boron implant dose of 2 x 10 2 cm at 70 keV is used to adjust the threshold voltage of the field regions A cross section of the device structure at this point is shown in Fig 1a The next step grows about 525 nm of field oxide in a 900 C steam ambient using silicon nitride to mask the active regions Fig 1b The nitride layer is then removed by a hot phos phoric acid etch An enhancement threshold voltage adjustment boron implant is done at this stage with a dose of 7 X 10 cm at 50 keV The stress relief oxide is etc
34. ation between the two sections is through an optoisolator 4 HEWLETT PACKARD JOURNAL OCTOBER 1982 Copr 1949 1998 Hewlett Packard Co and an asynchronous communication interface capable data transmission rate of 250 000 bits s The two analog interfaces are used to communicate with the four SMUs two VSs and two VMs via analog to digital and digital to analog converters as shown in Fig 2 The asynchronous interface is ground isolated and connected to the system microprocessor in the main processing unit by op toisolators This arrangement allows floating ground mea surements The SMU controller has intelligent functions that enable the system processor to give commands or get data with ease For example it has sweep control capability Once the SMU controller has been given sweep parameters linear log start value step size number of steps it sets up the source output values gives hold or delay time measures monitored values and reports measurement data automati cally at every step A second feature is the line frequency synchronized sampling and averaging technique to reduce ac line noise When INTEG TIME is set to SHORT the measured data is stored directly without integration However when INTEG TIME is set to MED 16 samples are taken during one ac line frequency cycle and averaged for each measurement value The LONG setting averages 256 samples taken during 16 ac line cycles The sample timing is controlled b
35. ation mode the maximum source to drain current de Fig 7 Microphotograph of finished device surface topogra phy The phosphorus doping level is 7 5 OCTOBER 1982 HEWLETT PACKARD JOURNAL 25 Copr 1949 1998 Hewlett Packard Co en GRAPHICS PLOT sess VGS 6V STEP 1 Fig 8 characte M 14W C 2 where V is the saturation velocity of electrons W is tk is the gate oxide capacita Vr is t threshold voltage of the transistor and K is a figure of merit effective channel width C Ves is the voltage between source and gate for the given device design The exact value of K is deter mined by the vertical impurity profile and the normalized The value for K ranges from 0 0 to 1 0 capacitance Equation 2 indicates that the source to drain current is linearly proportional to the gate voltage which is different from that for a long channel device In the latter case the current is proportional to the square of gate voltage T typical I V characteristic of an HQMOS device is shown in Fig 8 ForL saturation mode The K value for the device can be obtained king t currents and dividing by the corresponding difference in 9 X 10 cm s and is approx 2 um the device is operating in the velocity t difference between two from equation 2 by two voltages Typically v imately 0 5 sensitive to at leng The threshold vol
36. ayed numerically above the graph In Fig 3 Vra Vse 0 is 2 213V Threshold Voltage Vy Another method of measuring V is to bias the MOSFET such that the gate and drain are always at the same potential and measure the characteristics in the saturation region Drain current in the saturation region is calculated as Ip version of zero input which is shown in Fig as Igy From these values the microprocessor is able to determine the absolute offset value of each range and to get true data by simple addition or subtraction Thus this ADC can measure approximately 11 volts full scale with 0 5 mV resolution and 200 conversion speed The 16 bit DAC is used by the SMU controller to output control settings It has a 10 channel distributor that allo cates outputs from the DAC to each SMU and VS input The four stimulus measurement units are the heart of the 4145A Each SMU can be programmed to function as a voltage source and current monitor V mode or a current Fig 3 a Log linear display of MOSFET threshold characteristics for five different substrate volt ages b Source setup values V test configuration for a Fig 4 a Linear display for de termining threshold voltage of an MOS device see text Cursor is at point A marker at point B b Source setup values and test con figuration for a where is the gain factor of the device By taking the square root of
37. cess is used to etch the polysilicon layer Fig 1f shows the cross section after polysilicon etching After the photoresist is removed the entire structure is implanted with an arsenic dose of 7X10 5 cm at 90 keV to form the source and drain n re gions as shown in Fig 1g This is followed by an anneal ing cycle at 900 C to activate the arsenic and at the same time grow a thin layer of oxide on top of the n regions and polysilicon surfaces About 500 nm of phosphorus doped 7 5 low temperature oxide is then deposited on the sur face This layer of oxide acts as an insulating layer between the polysilicon and metal layers A 900 C steam cycle is used to soften the phosphorus doped oxide so that it will flow a little and thus smooth the steps over the polysilicon edges The next step is contact masking and oxide etching A wet dry wet etching process was developed to create proper oxide slopes at the edge of the contact windows while maintaining proper control of the contact areas Fig 1h shows the cross section of the structure after contact etching Wafers are then subjected to a short phosphorus predeposition cycle at 900 C The purpose of this step is to form junction where contact window openings at the edge of active regions overlap the field substrate This avoids any shorts at the overlapped regions and allows contacts to be placed very close to or even overlap the field oxide Before a 1 4m thick layer of 296 silico
38. defect density of the gate oxide ranges from 5 to 40 cm These numbers were gen erated from the yield data of 500 ym by 500 um square polysilicon gate MOS capacitors that withstand an elec tric field greater than 510 volts cm Buried contact process for thin gate oxides Conventional methods for fabricating this type of contact face a severe gate oxide degradation problem when the oxide is thin ner than 50 nm orso This is because during a short oxide etching step to remove about 3 to 5 nm of native oxide from the contact region the oxide in the active gate is also etched This etch reduces the strength of the oxide and increases its defect density The new process uses a thin layer of polysilicon to protect the gate oxide during the short etch operation Fig 5shows the steps of the new process compared to the conventional approach Only two extra steps are needed for the new process namely deposition of the first polysilicon layer and the etching of the layer No extra masking is involved Test results have shown that about 50 to 70 nm of polysilicon is adequate for the purpose Too thick a polysilicon layer results in removing too much of the silicon substrate during the etching step to pattern the gate electrodes a Shallow junction formation 6 shows the cross sec f a or The effective channel length Lig is related to polysilicon gate length L and the junction
39. devices who have to know how a device will behave in a circuit and by people developing computer models of devices for use in computer aided design systems The 4145A resembles a venerable instrument called a curve tracer which has been used for twenty years to measure transistor parameters However the resemblance is slight because the 4145A has a built in microcomputer and can automatically execute measurement sequences and perform calculations It can also operate under computer control as part of an automated test system Engineers who have used a ruler to measure distances on a curve tracer s screen so they could calculate the slope of a trace are impressed when they find they can position two markers on the 4145A s display and see the slope displayed on the screen This slope function and the 4145 ability to display calculated parameters are illustrated in the cover photograph You can get capability like the 4145A s elsewhere but only in sophisticated expensive system that really represents overkill for many measurement applications The complete story of the design of the 4145A is on pages 3 to 20 On page 21 is an article about one of the many processes used to make HP integrated circuits This process is called HOMOS for reasons explained in the article and it was developed by scaling down a standard process taking advantage of advances in process technology The scaled down process produces transistors that operate faster and use le
40. e physi cal insight into the factors governing device operation However it is well suited for later design cycles where final parameter adjustments can be accommodated A com plementary analysis and design path right half of Fig 1 using process device and circuit simulations has been proposed and is now widely accepted Compared to laboratory experimentation the design path via simulation is less costly and faster More important it produces detailed information about device operation in a well controlled environment Two Dimensional Simulation System Many two dimensional device simulation programs have been developed and several reported recently These pro grams however are research tools rather than design tools More stress has been put on the development of fast al gorithms and the implementation of the physical mechanism than on the user interface Furthermore each program was developed independently without an inter face to other programs Thus transferring massive amounts Fig 3 Simulated two dimen sional impurity distribution for a Standard NMOS device with a 2 5 channel length of two dimensional numerical data from one program to another is very difficult Analyzing and interpreting the data is also difficult To overcome these problems and pro videa convenient design path using simulation a complete two dimensional simulation system has been developed and implemented at HP with an emphasis on
41. emiconductor industries It is a fully automatic high performance in strument designed to measure analyze and graphically display the dc parameters and characteristics of diodes transistors ICs solar cells and semiconductor materi In stand alone use the 4145A can rapidly and accurately evaluate a complete range of param as threshold p DEVICE PARAMETER MEASUREMENTS voltage transconductance 8m common emitter cur rent gain hpg Early voltage VA and many others See pages 6 and 10 for examples of typical applications All of the necessary stimulus measurement calculation display and data storage facilities required are contained in the 4145A Because the 4145A uses the HP IB and HP GL Hewlett Packard Graphics Language it is easy to interface the 4145A to other measuring instrumentation and control lers for laborato utomation Publication quality hard copies of the measurement results displayed on the 4145A s CRT can be obtained simply by connecting an HP IB compatible plotter printer such as the HP 7470A Graphi Plotter and pressing the PLOT or PRINT keys The plots for the application examples discussed on pages 6 7 10 and 11 were obtained in this manner No controller is needed However by connecting a controller and using simp HP GL commands additional information notes com ments overlay plots et cetera can be displayed on the 5A s CRT or the CRT can be used as an independ
42. ent graphics display Hewlett Packard Interface Bus IEEE Standard 488 11978 Fig 1 4145 Semicon ductor Parameter Analyzer is the first stand alone instrument capa d ble of fully automatic measure ments of dc semiconductor parameters Using the Hewlett Packard Interface Bus IEEE 488 it can also form part of a larger computer controlled test system lor parameter evaluation com parison and storage OCTOBER 1982 HEWLETT PACKARD JOURNAL 3 Copr 1949 1998 Hewlett Packard Co Features Some of the features of the 4145A are Four stimulus measurement units SMUs that can be programmed to perform in one of three different modes 1 Voltage source and current monitor V mode 2 Current source and voltage monitor I mode 3 Common connection COM mode Two voltage sources VS that can be linearly or logarith mically swept over their programmed output range Two voltage monitors VM High resolution digital CRT display module for display ing graphic and alphanumeric information in any of five different display modes graphic display matrix display schmoo plot list display and time domain The display can also be programmed by an external controller using HP GL commands Internal flexible disc drive for storing measurement setups autosequence programs and data Built in HP IB interface for easy connection of the 4145A to other HP IB compatible inst
43. es not depend on the structure of the SMU but on the combination of the DUT and stray parameters around the DUT such as load induc tance and parasitic capacitance The frequency of this type of oscillation is rather high well into the 3 to 30 MHz re gion This type of oscillation usually cannot be detected by the 4145A s oscillation detection circuit To prevent oscil lation we can use ferrite beads on the test leads If an unusual display appears we recommend the use of addi tional ferrite beads on the DUT leads Hiroshi Sakayori Hiroshi Sakayori earned his BS degree in electrical engineering from Waseda University in 1972 and joined Yokogawa Hewlett Packard the same year He helped design the SMU and developed the analog performance test system for the 4145 He enjoys moun tain climbing skiing and watching Noh plays in his spare time Susumu Takagi Susumu Takagi eamed his BS degree in electrical engineering from Kyoto University in 1970 He joined Yokogawa Hewlett Packard the same year as a design engineer He has worked on the 1504 1505 Elec trocardiograph and the 4140A pA 77245 Meter DC Voltage Source He designed the SMU of the 4145A Susumu and his wife have two sons He enjoys camping woodworking and assembling models of various kinds Copr 1949 1998 Hewlett Packard Co HQMOS High Performance NMOS Technology Innovative processing methods are used to fabricate a
44. etter aniso tropic results at higher power levels A two step etching method first at 800 watts and then at 300 watts is needed to avoid any residual aluminum rings around the steps Etching at 800 watts not only provides an anisotropic result but also removes any aluminum oxide on the surface The 300 watt etch usually starts when the metal layer is etched through and provides some isotropic etch ing to remove residue With optical endpoint detection the typical undercut for 1 aluminum is approx imately 0 2 per edge Gate oxide The 40 nm thick gate oxide is grown in 900 C steam followed by one hour of gettering in a dry oxygen ambient mixed with 0 63 111 trichloroethane TCA Typical thickness variation from run to run is 10 with better uniformity from wafer to wafer in a single run Uniformity across a wafer is better than 5 This important because the threshold voltage of a device is proportional to the oxide thickness Typical fixed oxide surface charge is in the 4 to 610 cm range Break down voltage of the oxide is approximately 35 volts which corresponds to a dielectric strength of 8 7 x10 volts cm Results of bias temperature stress tests which were done by applying an electric field of 5 x 105 volts cm or 1X10 volts cm at 300 C for five minutes and then cooling to room temperature with the electric field still applied indicate that the oxide is relatively free from mobile ion contamination The
45. example hpg be displayed as a function of base current Ig and collector to emitter voltage Vcg The dis play can have up to 512 rows of data corresponding to steps for variable VAR1 and up to six columns per row corresponding to steps for the second variable VAR2 Matrix elements can be measured values or the results of user function calculations List Display Fig 8c A complete numeric listing of up to six parameters and user function results dependent on variable VAR1 Time Domain The time dependency of semiconductor parameters can be observed and analyzed This is done by not assigning VAR1 to any of the source channels SMUs and voltage sources on the CHANNEL DEFINITION page Measurements over a period as long as 85 minutes can be made with measurement intervals specified from 10 ms to 10 s Results can be displayed in graphic matrix or list formats Graphic Display Fig 8d The source variable mea surement variables maximum of six and user functions maximum of two can be independently assigned to three axes X Y1 and Y2 Therefore two characteristics can be displayed simultaneously double Y axis format Various display scaling configurations can be specified independently of the sweep mode of the source variable e g linear X linear Y1 linear Y2 or linear log linear or log log log The versatility of the graphics display mode is enhanced by its various analysis functions The marker function pr
46. has to know the offset value for each range To measure these offset values a self calibration is per formed First the main DAC s output current Im is set to zero and the offset DAC s output current Ip is set to Ip see Fig 3b At this time the sample and hold circuit is set to the sample mode and a ramp voltage is applied to its input The comparator output goes high at the balancing point i e Va R 10 At this moment sample and hold circuit is set to the hold mode Then the output current of the offset DAC is changed to loz and a successive approxi mation conversion is performed using the main DAC The result of this conversion gives the relative offset value be tween l and 1 2 Similarly the second step of the calibra tion process determines the difference between the Ip and values of the offset DAC In addition the absolute offset value can be measured by the normal analog to digital con OCTOBER 1982 HEWLETT PACKARD JOURNAL 5 Copr 1949 1998 Hewlett Packard Co Four examples of common semiconductor device measure ments done by the 4145A are shown in Fig 1 through Fig 4 The first two examples evaluate characteristics of a bipolar npn trans istor and the remaining two examples evaluate an MOS device Part a of each figure is a hard copy of the 4145A s graphic display and part 6 shows the 4145 test connections and SMU mode settings to the device under test Static Collector Characteristic
47. hed off and a fresh layer of oxide about 40 nm thick is regrown on the surface of the active regions as shown in Fig 1c Now depletion threshold adjustment masking and an arsenic implant can be done selectively on those regions where depletion transistors will be built as shown on the left side of Fig 1d This step can be repeated for different arsenic implant energies and doses on different regions depending on the needs of the circuits The next step which is op 22 HEWLETT PACKARD JOURNAL OCTOBER 1982 tional opens buried contacts for the depletion mode tran sistors A new buried contact process was developed and used here to avoid the gate oxide degradation problem encountered in a conventional buried contact process A more detailed description of this new process will be given later Fig 1e shows the device cross section after the contact oxide is etched A 400 nm thick layer of polysilicon is de posited on the surface using a low pressure chemical vapor deposition LPCVD process and is doped with phosphorus using a standard POCIs predeposition cycle e Fig 2 HOMOS impurity profiles from SUPREM simulations a Active region of an enhancement device b Active region of depletion device c Source drain n p junction Copr 1949 1998 Hewlett Packard Co Polysilicon gates 2 wide and interconnects are then patterned by another photolithographic process Anonundercutting dry etching pro
48. in HQMOS circuits Field oxide thickness 0 4 um polysilicon thickness 0 4 um and line width 1 8 the field oxide between the polysilicon and the substrate is 0 4 um The polysilicon line is also 0 4 thick cal culated capacitance of this line is 0 117x10 pF um using the one dimensional parallel plate approximation The actual measured capacitance which includes the fringing field effects is 0 196x10 The fringing field increases the capacitance by 67 596 Acknowledgments GEMINI SUPRA and TECAP are programs that have been developed at Stanford University under the direction of Bob Dutton and sponsored by both HP and the Advanced Re search Projects Agency CADDET is a program developed by Hitachi Company in Japan References 1 R H Dennard et al Design of Ion Implanted MOSFETs Very Small Physical Dimensions IEEE Journal of Solid State Cir cuits Vol SC 9 October 1974 pp 256 268 2 D Chin Kump and R W Dutton SUPRA Stanford Univer sity Process Analysis Program Stanford Electronics Laboratories Stanford University Stanford California October 1979 3 T Toyabe et al Numerical Model of Avalanche Breakdown in MOSFETs IEEE Transactions on Electron Devices Vol ED 25 1978 pp 825 831 4 J A Greenfield S E Hansen and R W Dutton Two Dimensional Analysis for Device Modeling Technical Report No G201 7 Stanford Electronics Laboratories Stanfo
49. ion no signi cant undercut is observed even with 10096 overetch 3 3 shows the etch rates of doped polysilicon oxide and photoresist An etch ratio of better than 10 1 was ob served between polysilicon and thermal oxide or photo resist This differential etch ratio is more than adequate for 40 nm of oxide Fig 4 shows a typical etch result before the photoresist was removed Another etch pro sess which uses Co s gas lieu of helium was developed by HP s Cupertino Integrated Circuit Operation Similar results were obtained with smaller differential etch ratios Based on electrical test data an overall linewidth reduction of 0 1 0 2 um was observed this includes both photolithographic and etching components Dry etching of contact oxide There are three factors to be considered in contact oxide etching namely size con trol edge slope and selectivity Since no single etch process has been found that provides an adequate solu tion to all of these factors a wet dry wet etching process was developed to overcome the difficulties The first wet etching step is done a 20 1 NHsF HF buffered etch solution and the dry etching step is done C Fe He plasma The buffered etch solution etches phosphorus doped oxide at 110 nm minute and thermal oxide at 28 nm minute This was the lowest etch ratio found This low etch ratio is important in the final wet etching step because the oxide to be etched is thermally grown on the surface of
50. lector and common emitter configurations without having to change the physical con nections between it and the 4145A Design Considerations In designing the 4145A s SMUs two approaches were considered a basic voltage source capable of limiting out put current and a basic current source capable of limiting output voltage The dc characteristics shown in Fig 1a are those of a basic current limiting voltage source This volt age source operates in the current limit mode when the voltage setting results in an output current that exceeds the preset limits In this mode the voltage source now behaves like a current source In Fig 1a two different loads are shown Rr and Ry is relatively high forcing the source into a constant voltage mode and is relatively low forcing the source into a current limited mode The dc characteristics shown in Fig 1b are those of a basic current source capable of voltage limiting There is no difference between the two types of sources in normal oper ation In the limited operation region however there is a great difference The voltage source just needs to increase OCTOBER 1982 HEWLETT PACKARD JOURNAL 15 Copr 1949 1998 Hewlett Packard Co Lower Voltage Limit 1 Upper Voltage Output Current d Setting V Lower 9 vt Current a b Fig 1 a Output characteristic of a current limited voltage source b Output characteristic of a voltage limited current so
51. n doped aluminum is deposited a brief deglazing step removes any oxide grown in the contact window Metal lines are defined by a photolithographic process and etched in CCls He plasma A CFs O2z plasma is used to etch off the silicon residue The wafers are alloyed in a pure H2 ambient for 30 minutes to ensure good n to metal contacts and reduce the surface states or any damage caused by the sputtering or dry etching process The completed structure is shown in Fig 1i A passivation layer is not shown but is included for scratch protection Table I summarizes some of the key process parameters Only nominal values are listed here The amount of side encroachment 2AW is obtained from electrical measure ments of transistors with different channel widths W The value of channel length reduction 2AL comes directly from the junction depths Fig 2a and Fig 2b show simu lated impurity profiles for the active region of the en hancement and depletion transistors respectively The boron concentration profile which determines the en hancement threshold voltage as well as the source to drain punchthrough voltage peaks at 2x10 cm within a depth of 0 to 0 2 beneath the Si SiO interface shown as 0 00 in the horizontal scale and tapers off to the substrate dop ing level ata depth of 0 5 A similar plot for a depletion transistor is shown in Fig 2b Here the arsenic profile is superimposed onto the boron profile The arsenic concen
52. nductive load When the SMU is operating in the V mode voltage sourcing and current sensing the output impedance of the SMU is inductive Fig 7b When an inductance L is con nected to the emitter of a transistor its effect is multiplied because the base input impedance of the transistor is 1 times hfe Fig 8 depicts another example The SMUs con nected to the MOSFET s gate and drain are operating in the V mode so these SMUs appear to be inductive making this configuration equivalent to a Hartley oscillator To prevent oscillation the SMU uses a network consist ing of C and as shown in Fig to compensate for the output inductive reactance However the value of C can not be made large enough to make Zout capacitive because of the need of a short settling time Therefore the SMU may 20 HEWLETT PACKARD JOURNAL OCTOBER 1982 m c 1 b Mode Fig 8 A test configuration that could cause SMU oscillation Itis equivalent to a Hartley oscillator because SMUs operating in the V mode can act as inductive components oscillate if an unusually large inductance is connected This can occur when the DUT is a high hg 73000 transis tor and the SMU connected to its emitter is set to a low current range If oscillation does occur it is detected by the oscillation detector in the 4145A and an error message is displayed on the 4145A s CRT The second source of oscillation do
53. nformation dis played on the CRT directly onto a digital printer plotter via the HP IB providing publication quality hard copies The plot area is front panel programmable and no HP IB con troller is necessary The PRINT function operates similarly but only data stored in the measurement data buffer is printed The external CRT output allows view test results on a large screen monitor Small scale systemization of the 4145 is possible by using an analog data link For example if you connect a capacitance meter equipped with an analog output to the he operator to Copr 1949 1998 Hewlett Packard Co CE PLOT seeeeee MATRIX DISPLAY 2 189089 12 LUE moa m t t 1 08 1 06 1 07 4 8 12 08 8 66E 00 16 7 ee 25 8E e 26 7 39 4 40 2 56 8 56 5 78 1E 08 76 2 103 00 98 4145A you can plot the C V curve of a device on the 1145A s CRT In such a measurement one SMU stimu the device under test which is connected to the capacitance meter The analog output of the capacitance meter is con nected to another SMU or a voltage monitor which me sures the analog volt The 4145 user functions can then calculate and display the capacitance values E the appropriate tr ical parameters such as temperature and pressure Fig 9 is an example of a 1 MHz C V de b
54. nsumption of an HQMOS inverter With delay per stage is approximately 450 3 volts and Vout 2 volts the typical ga picoseconds and the delay power product is approxi mately The first IC chip designed using the HQMOS process is a 80 femtojoules digital filter chip This chip contains approximately 42 500 10 5 volts T4 105 0 1 pA 2 volts 1 W 5 054 a 5 10 Loss um 1 04 Vos 3 volts 1 pA TR 2 volts 2 L 2 pm gt tt Wack um L 5 ans um a 4 2 A E tEA 4 71 10 20 vor Copr 1949 1998 Hewlett Packard Co Table 11 Nominal HQMOS Electrical Parameters Vr enhancement WIL 5 2 Voeptt W L 5 2 Vpepiz optional W L Subthreshold slope L 2 Enhancement Depletion 80 mVidecade 90 mV decade Table Ill Extracted SPICE Parameters Enhancement device W L 5 2 Ho tox 36 nm Vro 0 69V R 0 Nsub 1 1 10 5 cm Ry 0 Vnom 5V 1 00x10 V cm 1 0 105V cm Etra 5 104Vicm L4 AL 0 38 WA AW 0 95 um transistors and operates at a 20 MHz clock rate A very fast digital to analog converter and 4 bit shift registers and latches operated at 180 MHz have been demonstrated by various groups within HP Laborator es Acknowledgments The development effort was carried out by Hewlett Packard s Integrated Circuit Laborat
55. o OCTOBER 1982 HEWLETT PACKARD JOURNAL 11 Copr 1949 1998 Hewlett Packard Co b Ge GRAPHICS 152 Fig 7 Typical measurement s CHANNEL DEF g for the SMUs are selected ai sources and monitors are s T e oa 88 9 vides readout of not only measurement point values but also intermediate point values by linear interpolation The X Y1 and Y2 coordinate values of any point on the graph can be read by the cursor function The line function en ables direct readout of slope GRAD plus X and Y inter cepts Comparison functions are provided by the STORE and RECALL softkeys They provide overlay displays or double axis formats The autoscale function optimizes graphic display scaling after measurement The zoom function horizontally or vertically expands 2 or contracts 0 5 the displayed graph window can be moved to any location centered on the The zoom cursor The background area of the vector memory can be used to display user oriented graphics via the HP IB This function enhances user applications User Functions and Keyboard Arithmetic The 4145A has two programmable user functions which provide real time calculation of current voltage dependent parameters such as hpg gj and maximum power hyper bola All of the 4145A s arithmetic functions V EXP LOG LN ABS EEX and A variables source and
56. ojection mask aligners A direct step on wafer DSW system using 10 1 optical projection was chosen here The 10 x reticles are generated by a direct electron beam writing process to provide better mask geometry control A positive photo resist process is required for better resolution and etch masking In the routine operation a level to level regis tration accuracy of 0 35 um is adequate for the process 800 watts 13 1 Polysilicon SIO 8 18 Doped Polysilicon Etch Rate nm minute 1000 Power watts Fig 3 Plasma etch rates for doped polysilicon thermal oxide and photoresist versus RF power level OCTOBER 1982 HEWLETT PACKARD JOURNAL 23 Copr 1949 1998 Hewlett Packard Co Photoresist Polysilicon Silicon Fig 4 Microphotograph of a typical polysilicon etch result before photoresist is removed This is the manufacturer s specification and can be im proved by machine optimization and operator training Experimental results indicate that linewidth control of 1 9 0 2 can be achieved Dry etching of polysilicon A nonundercutting plasma etching process was developed to etch 2 um wide polysilicon lines CCla vapor is introduced into an evacuated planar reactor and mixed with helium gas to maintain a stable etch gas pressure The typical etch rate is 120 nm minute on phosphorus doped polysilicon using 500 watts of RF power at a gas pressure of 250 millitorr Under a typical etching condit
57. om 40 nm to 30 nm and the resulting changes in the subthreshold characteris tics are shown in Fig 7 Because of the lower body effect caused by the higher gate capacitance Vy is lowered farther by 0 18V To maintain the same threshold voltage in the scaled down device the dose of the channel implantation must be changed The subthreshold characteristics for sev eral different doses and the corresponding impurity pro files were obtained by using SUPRA and GEMINI The optimum dose was found to be 1 2x10 cm The sub threshold characteristics of the scaled down device with this dose are shown by curve d in Fig 7 Another example involves the two dimensional semirecessed field oxidation used for device isolation in an NMOS process As shown in Fig 8 simulation the field oxide layer grows laterally bird s beak under the silicon nitride mask and reduces the effective channel width sig nificantly The penetration distance AW is a function of oxidation temperature oxidation time and the thickness of the nitride mask SOAP calculates the diffusion of the oxy gen from the oxide surface to the silicon oxide interface and the growth of the extra oxide volume generated during the oxidation including the stress of the nitride layer It accu rately simulates the effects of the oxidation temperature oxidation time and the nitride thickness on the lateral shape and penetration of the field oxide In the example shown in Fig 8 0 95 um
58. on of a specified task after a specified interval Interrupt handling The interrupt handler monitors and processes interrupts from the powerfail detector timer and asynchronous communication interface Up to eight interrupt processing routines can be supported control The I O control subsystem provides the basic drivers and various utilities to control the instrument hardware graphics display mass storage front panel and asynchronous communication interface The 4145A has a memory mapped I O system and 16K Copr 1949 1998 Hewlett Packard Co 143 Records 6K ROM a Fig 5 a Memory map for main processing unit b Disc memory structure for the single sided single density 5 25 in flexible discs used by the 4145A s internal disc drive bytes 4K x4 of ROM The ROM area contains the real time monitor I O control power on self test programs and some frequently used utilities The 4145A s memory map is shown in Fig 5a The direc tory isa copy of the directory stored on the disc If the disc is changed the directory is automatically revised at the next file access The measurement control block contains the control information fora measurement Data in this block is changed by changing the information on the CHANNEL DEF INITION SOURCE SET UP MEAS amp DISP MODE SET UP OUT PUT SEQUENCE SET UP and DISPLAY menu pages This area 768 bytes can be stored on the disc by the command
59. ory ICL in conjunc tion with the then Instrument Research Laboratory IRL now Measurement and Communication Laboratory and the Santa Clara Division Process development work and device modeling and characterizations were done in ICL with the help of IRL in device and SPICE modeling Circuit designs were done in Santa Clara Division also with help from IRL All wafer processing was done in HP s Integrated Circuit Processing Laboratory ICPL The initial phase of the development work was carried out under the guidance of Juliana Manoliu Kuang Chiu s participation in the early development work is also acknowledged Many thanks to Fred Schwettmann Dirk Bartelink Pat Castro John Moll and Bob Grimm for their support and encouragement dur ing the course of this work References 1 R Dennard et al Design of Ion Implanted MOSFETs with Very Small Physical Dimensions IEEE Journal of Solid State Circuits Vol 5 no 5 October 1974 2 R Szeto et al Buried Contact Process for VLSI to be presented at the Fall Meeting of the Electrochemical Society paper 175 Detroit Michigan October 1982 3 J Moll Outer Limits of VLSI presented at Semiconductor Interface Specialist Conference New Orleans Louisiana November 29 1979 Roger Szeto 5 Devereaux Chen Dev Chen joined HP in 1 after eam ing the MSc degree in electrical en gineering at Yale University He also holds the
60. r even three dimensional MOSFET structure has evolved Scaling down dimensions intro duces problems in both fabrication and operation that are not significant in larger long channel devices The two dimensional aspects of the impurity profiles and oxidation processes become important in determining the effective fess ator st propose field effect Fabrication Measurement Simulation Process Specification Process Models Spreading Process Resistance imulation impurity Semiconductor Profile o d Devi Simulation e Device ult Models H Parameters for Circuit Simulation 9 Transient Circuit Measurement Simulation Circuit al Performance Fig 1 Block diagram of MOS process device and circuit design paths The left hand path shows the traditional trial approach and the right hand path illustrates the simulation approach 28 HEWLETT PACKARD JOURNAL OCTOBER 1982 channel length and width More processing steps are re quired such as channel implantation and local oxidation which make more stringent control of the process neces sary Secondary effects such as oxidation enhanced diffu sion significantly affect the impurity profile As a result better understanding and accurate control of these phenomena are crucial to achieving the desired perfor mance from scaled down devices Device operation reveals the existence of two dimensional field coupling involving both the
61. rd University Stanford California 1980 5 E Khalily T E C A P An Automated Characterization Sys tem Technical Report No 5017 1 Stanford Electronics Laboratories Stanford University Stanford California 1980 and Transistor Electrical Characterization and Analysis Program Hewlett Packard Journal Vol 32 no 6 June 1981 6 L K Scheffer R I Dowell and Apte Design and Simula tion of VLSI Circuits Hewlett Packard Journal Vol 32 no 6 June 1981 and HP SPICE User s Manual DA320 3C Hewlett Packard Design Aids October 1980 Soo Young Oh Soo Young Oh was born in Seoul Korea and attended Seoul National University earning a BS degree in 1972 He continued his studies at Stan ford University eaming an MS degree 1976 and a PhD degree 1980 in elec trical engineering Soo Young joined HP in 1980 and is a project leader for device and process modeling He has written two papers on two dimensional device simulation and is a member of the IEEE Soo Young lives in Union City California is married and enjoys play ing tennis 3000 Han 94304 Palo Alto Californ Street HEWLETT PACKARD JOURNAL APPLIED PHY Rate U S Postage Paid Hewlett Packard Company SICS LAG NS CHANGE OF ADDRESS 8953 8504 old address label Send va 94304 U S A Allow 60 days Copr 1
62. reduce the effects of ac line frequency noise on the measurement Michitaka Obara field pointer gt and system messages displayed on the CRT guide the operator through the programming procedure If only minor modifications are desired the field pointer can be moved directly to the target field by pressing the appro priate cursor control keys The interactive fill in the blank programming is further enhanced by the softkey concept If the 4145A s operating system were controlled by a conventional keyboard more than 200 keys would be needed or the operator would have to input commands with alphabetic and numeric keys The advantages of using softkeys are that an operator can quickly select the desired command from softkey prompts and all possible commands and functions can be displayed Thus the operator doesn t have to memorize the commands or refer to a command summary or the manual Display Modes and Analysis Functions Measurement results can be displayed in one of five different formats Schmoo Plot Fig 8a A three dimensional XYZ dis play in which five level dependent weighted symbols indicate the relative values of measurement results on the Z axis The symbol at any selected X Y measurement point can be highlighted by the cursor function to pro vide direct numeric readout of the Z axis value Matrix Display Fig 8b A numerical presentation of a single characteristic affected by two varying parameters For
63. rom another point of view as long as the saturation prevention current is maintained the voltage error amplifier is kept ready to control and maintain the SMU output voltage All error amplifiers work to maintain the present output condition Thus the smooth transfer of control modes during changes in settings and outputs of the SMU is assured preventing overshoot or spikes at the output Automatic Calibration The monitor functions of the SMU can be used for self calibration Output errors can be compensated by measur ing the raw errors with the calibrated monitors offset errors of the SMU source monitor are updated every five minutes by the normal measurement sequence Extensive use of high stability precision resistors and resistor net works in the SMU design eliminates the need for gain adjustments Because only the single high performance DAC and the single high performance ADC are used to communicate between all of the SMUs and the SMU con troller no individual adjustments are required for each SMU Stability The dc characterization of semiconductors is sometimes affected by oscillation There are two modes of oscillation one caused by the SMU and the other caused by the DUT and the connection leads The oscillation caused by the SMU occurs when an inductive load is connected to the SMU output The oscillation frequency is low less than 300 kHz The SMU often has an inductive load because the output impedance of the
64. ruments and controllers to form automated test systems Eight built in functions to simplify control and manipu lation of the displayed data Two user functions that allow front panel programming of two different arithmetic operations for calculating parameters from measured values The results can be displayed in real time versus the measured values Versatile front panel keyboard for measurement setup and manipulation of displayed data Eight softkeys along the right side of the display make it easy foran operatorto select the desired test conditions and display format theae dimensional plot in which Z axis values are indicated by different symbols on an XY plot Microprocessor E 7 68800 Main Processing Unit SMU Controller Interface Optoisolator Interface ible Disc Controller Mass Storage Unit Hardware Architecture A block diagram of the 4145A s hardware system is shown in Fig 2 The digital system is functionally divided into six blocks the main processing unit graphic display unit mass storage unit front panel unit and HP IB inter face contained in the digital section and the SMU control ler located in the measurement section and coupled to the rest of the digital system through an optoisolator The main processing unit uses a 68 00 microprocessor and contains 16K bytes of ROM 32K bytes of dynamic RAM a 10 ms interval timer and the SMU controller interface The graphics display unit contain
65. s The static collector characteristics of a bipolar transistor are shown in Fig 1 They were obtained by linearly sweeping the collector voltage Vcg from 0 to 10V at five different values of base current lg and measuring the resulting collector current I SMU 1 is pro grammed for operation as a common source COM mode to which all other sources in the measurement are referenced SMU 2is used as a variable current source I mode to provide the requisite base current SMU 3 acts as a variable voltage source V mode and current meter to provide collector voltage and mea sure the collector current SMU 3 is the primary sweep source VAR and SMU 2 is the secondary or dependent sweep source GRAPHICS PLOT esee 1c M CURSOR MARKER thpl e e GRAPHICS PLOT emen 2 gt CURSORS 2 333uA 67 0 28 gt decade 7447 1 21 16 12 E div GRAD intersect LINEI 3785 03 2 2 8 12 8 83 23 LINE2 coim Typical Applications of the 4145A Semiconductor Parameter Analyzer VAR2 The VAR2 source is incremented only after each VARI source sweep By using the 4145A s built in line functionto draw a straight line between points A and B the transistor s collector output resistance and Early voltage can be read directly from the GRAD and X INTERCEPT value
66. s respectively In this example the output resistance is 9 37 and the Early voltage is 77 7V Characteristics By using one of the two internal user functions a bipolar tran sistor s hee Ic curve can be obtained Fig 2 h is defined as 1 1 The decay constant can be read directly from the 4145A s CRT display by using the line function to draw a line tangent to the linear portion of the curve as shown in Fig 2a MOS Threshold Characteristics The five curves shown in Fig 3 represent an MOS device s characteristics al five different substrate voltages Vsg The threshold voltage V of an enhancement type MOSFET is defined as the gate voltage required to cause a predetermined value of drain current in this example 10 4A V can be obtained by Fig 1 a Linear graphics display for static collector characteristics measurement of an npn bipolar transistor Cursor is at point B marker at point A b Source setup values and test configuration for a SMU 3 Fig 2 a hee versus I display for a npn bipolar transistor Both axes are logarithmic b Source setup values and test configura tion for a 6 HEWLETT PACKARD JOURNAL OCTOBER 1982 Copr 1949 1998 Hewlett Packard Co bis Co MM oj resse S PLOT 5p eese GRAPHICS PLO moving the display marker along the curve until I 10 uA point A and then reading the value Vg at that point as displ
67. s an HP 1345A Digital Display Module and a two port read write 4K x 16 bit vec tor memory to store picture data The 1345A picture data is refreshed automatically by scanning the vector memory at a rate of approximately 50 Hz A keyboard rotary pulse generator and various indi cators make up the front panel unit The keyboard consists of a number of keys arranged in convenient groupings for page control measurement control autosequence control integration time selection editing alphanumeric and arithmetic operation entry autocalibration print plot con trol softkeys file storage and retrieval and cursor position ing The rotary pulse generator outputs 120 pulses per rev olution and controls the display marker The indicators show the current HP IB status and selected operations The mass storage unit contains a flexible disc controller and drive The drive handles 5 25 in single sided single density flexible discs having a storage capacity of 92 kilo bytes on 40 tracks with 9 sectors per track 256 bytes per sector The SMU controller is the measurement controller in the 4145A It uses 6802 microprocessor and contains 12K bytes of ROM 1K byte of static RAM two analog interfaces Vector HP IB Interface B 4 in Flexible Disc Drive Display Graphics Display Unit Fig 2 Block diagram of the 4145A s hardware system consisting of a grounded digital section and a floating measurement section Communic
68. sivity in a numerical finite difference method For a more accurate two dimensional oxidation simulation SOAP should be used SOAP is a program that simulates the diffusion of the oxygen in the oxide and the propagation of the extra oxide volume generated during the oxidation in a rigorous man ner Two dimensional oxidation is a difficult problem to simulate because of nonplanar geometries and moving boundaries SOAP uses the boundary value BV method In this method the nodes are allocated only along the boundary Thus it is very suitable for nonplanar geometry and moving boundary problems Electrical device characteristics are predicted by two dimensional device simulators based on the impurity dis tributions predicted by SUPRA In these device simula tions the Poisson and current continuity equations should be solved with the appropriate boundary conditions to be valid over the whole operating region of MOS transistors Such an algorithm is used by the full two dimensional simulator CADDET The full simulator however is slow a simplified analysis should be used whenever possible hierarchial simulations For the subthreshold region where the current is small the two dimensional Poisson equation solver is fast and accurate enough for most applications For a large number of simulations such as l V characteristic generation SDVICE is accurate enough SDVICE numerically solves the one dimensional current contin
69. ss power than those of the standard process In the article on page 28 you can find an example of the use of computer models to simulate how process changes may alter device performance Using these models process engineers can predict the effects of changes without actually making a wafer R P Dolan 2 HEWLETT PACKARD JOURNAL Company 1982 Printed in USA Copr 1949 1998 Hewlett Packard Co Intelligent Instrument Streamlines dc Semiconductor Parameter Measurements Used as a stand alone instrument or as part of an automated test system this smart curve tracer makes it measure analyze graphically display at semiconductor parameters easy to d store dc by Kohichi Maeda Jin ichi Ikemoto Fumiro Tsuruda and Teruo Takeda are essential for computer aided design and semiconductor research and development for real time feedback on wafer evaluations to improve the semiconductor process and increase yields on the produc tion line and for incoming inspection by end users of semiconductor products The need for an instrument capa ble of such measurements that can be used by itself or can be easily incorporated into an automated test system is becom ing more and more acute The HP 4145A Semiconductor Parameter Analyzer Fig 1 was developed to provide an attractive alternative to curve tracer or an expensive test system and to satisfy the measurement and evaluation needs of the s
70. suppression is in the firmware in the ROMs of the SMU controller This spike suppression is effective even at instrument power on off Construction A simplified block diagram of an SMU is shown in Fig 2 Only one of the three error amplifiers controls the power amplifier during normal operation The other two error amplifiers operate in their standby mode and take control when the output compliance is reached The SMU output voltage V is buffered by the voltage follower and fed back to the voltage error amplifier It is measured by the voltage monitor amplifier which normalizes it to the analog to digital converter ADC input level The SMU s output cur rent develops a proportional voltage across the selected range resistor which is measured by the current monitor amplifierafter the unwanted common mode voltage error is rejected The output of the current monitor amplifier is also Data Bus To 8 Bit SMU Controller Address Bus Current Float Amplifier 50 m or 25 L joltage orton Mn Range Follower 7 A ANN Ej Voltage t sd e From Poner V V iw 160 or 10 or 100 ort orion DAC PACKARD JOURNAL SMU Output SMU Circuit Common n Fig 2 Simplified block diagram of one of the four SMUs used in the Amplifier Output 4145 Semiconductor Parameter Common Analyzer Copr 1949 1998 Hewlett Packard Co normalized to the ADC
71. tage of a device is ver jecially when the The threshold voltage is also channel length variations e h is less than 5 um Fig 9a sensitive to the channel width W when W is less than 5 um om width come f Fig 9b Encroachments into the channel the lateral diffusion of implanted boron during field oxida tion Substrate bias also greatly affects the th This effect is illustrated sshold volt age Fi w versus the square root of V sub 2 p of the substrate and is the substrate bias vol There are two slopes in the plot One corresponds to the higher doping level near the silicon to silicon dioxi nter face and the other corresponds to the subst loping shoulder region corresp to the junct ye tween the implanted boron and the substrate Table lists some electrical parameters of the HQMOS d Subtl slopes are relatively independent o e nd are 80 mV decade and 90 mV decade for the Table sts aset of SPICE parameters generated by matching the ental he surface the value is hancemen pletion transistors respectively results Because of e models with experir n boron doping near I thr different from the actua 1014 voltage measured at zero ias voltage stage ring oscillator with pull up depletion load down enhancement W L 5 2 devices W L 3 2 and pul used to es 1e gate delay and power co
72. the user inter face The following schemes have been adopted to make this system a more practical and user oriented design tool programs are an HP 1000 Computer for fast turn around Friendly interactive input output Data transfer between programs using standard format disc files that are transparent to the user Graphic plotting capability accessible to all two dimensional programs to process and analyze the mas sive amounts of data generated by these programs Hierarchical simulations are used wherever possible because full two dimensional simulations are time consuming A block diagram of this system is shown in Fig 2 The process simulator SUPRA Stanford University Process Analysis program simulates processes based on the de vice geometry and process schedule and generates the im purity distributions SUPRA can handle deposition etch ion implant diffusion and oxidation process cycles The oxidation model is based on empirical data For impurity diffusions SUPRA analytically solves the diffusion equa tion using a constant diffusivity for low impurity concen Fig 4 Simulated two dimen sional potential distribution for standard NMOS device Chan nel length L 2 5 um Vs 0 2V Vps 3V and Vas 2V OCTOBER 1982 HEWLETT PACKARD JOURNAL 29 Copr 1949 1998 Hewlett Packard Co trations For higher concentrations it solves the diffusion equation using a concentration dependent diffu
73. thick field oxide is grown using a two hour wet oxidation cycle at a temperature of 1000 C The thickness of the nitride layer is 50 nm The lateral 0407 10 7 10 24 10 8 10 104 los Alum 10 14 10 124 10 34 10 14 Fig 7 Subthreshold characteristics as function of channel length L gate oxide thickness toy and channel implant dose a L 2 5 um t 740 dose 7 x10 icm b L 1 5 um t 740 nm dose 7 x 10 cm c L 1 5 um t 730 nm dose 7 x 10 lcm 0 L 1 5 um t 730 nm dose 1 2x10 cm penetration AW is 0 8 um The simulated result agrees well with actual results observed by a scanning electron microscope A third example is the calculation of the parasitic tance of the interconnect line for the HQMOS process using FCAP2 When the width of the interconnect line decreases the capacitance of the line does not decrease linearly be cause of fringing electric field effects at the edges of the line Fig 9 shows the equipotential lines for the 1 8 polysilicon line as simulated by FCAP2 The thickness of Fig 8 Two dimensional simula tion of semirecessed field oxida tion process used for NMOS device isolation Temperature 1000 C oxidation time 120 minutes OCTOBER 1982 HEWLETT PACKARD JOURNAL 31 Copr 1949 1998 Hewlett Packard Co 510 si Fig 9 Parasitic capacitance calculation by FCAP2 for polysilicon line used
74. tion Accuracy Voltage V 100 mA 100 pA 20V I 100 40V I 40 mA 0 396 of reading nece 0 1 0 002 10mA 104A of range 1000 14A 100 100 nA 10 pA 10 nA 100 1 20 mA 1nA 0 5 of reading 000 nA 100nA 100 pA 0 1 0 002V of range 10 nA 10 pA 5 pA 1 of reading 1000 pA 1pA 0 1 0 002 of range voltage at set current for a discussion of the design of the SMUs As mentioned earlier the output from each SMU is de termined by two input control voltages from the 16 bit DAC one for output voltage and one for output current Other information such as voltage or current ranging is given directly by the SMU controller Each SMU outputs two monitor voltages to the 16 bit ADC that correspond to SMU output voltage and output current The two additional voltage sources VS and two voltage monitors VM are built in for measurements that require more sources and or monitors than provided by the four SMUs Each VS isa programmable voltage source whose 1 mV to 20V output is determined like the SMUs by the output from the 16 bit DAC Each VM is similar to a buffer amplifier whose monitor output is sent to the ADC via the multiplexer Each VM can measure voltages from 100 aV to 2V or from 1 mV to 20V depending on its range setting Software System The 4145A s software system Fig 4 is based on a real B HEWLETT PAC
75. uity equations along the channel with ap propriate two dimensional field coupling to the boundary conditions using the boundary value method as mentioned above In the BV method because the nodes are allocated only along the boundaries and the channel a much smaller number of nodes are required than for the finite difference or finite element methods Furthermore a fast two dimensional Poisson equation solver has been incorpo rated to enhance the accuracy for nonuniform substrate doping The calculation speed of this method is an order of magnitude faster than that of the full two dimensional simulator Based on the device characteristics calculated by these simulations the electrical parameters can be extracted by TECAP for use in circuit simulations TECAP measures the device characteristics of MOS and bipolar transistors and 30 HEWLETT PACKARD JOURNAL OCTOBER 1982 Fig 5 Potential distribution for scaled down NMOS device HQMOS channel length reduced to 1 5 um and using same volt ages as for Fig 4 extracts their parameters Here the data is taken from the simulation and only the parameter extraction part of TECAP is used In VLSI circuits accurate determination of interconnect and other capacitance values becomes crucial in the circuit simulation The value of various capacitance components in MOS circuits can be simulated and deter mined by FCAP2 a two dimensional arbitrary geometry linear Poisson equation solver The
76. ultiplexer The multiplexer selects one channel from the 10 channels connected to the four SMU voltage monitor outputs the four SMU current monitor outputs and the two VM outputs Digital data from the ADC is sent to the digital section to be processed and displayed To obtain both high resolution and high speed from a simple hardware configuration the ADC in the 4145A uses aspecial input range expansion technique As shown in the block diagram in Fig 3a the ADC is of the successive approximation type It uses two DACs One is a 14 bit Output a Raw Data lor eee t e Time b e Fig 3 a Block diagram of the ADC used in the measure ment section of the 4145A The conversion is done by succes sive approximation using DACs to supply the error signal to the comparator b By setting o and login turn the error signals to correct the offset of the ADC can be derived c Relationship of the voltages V and Vs shown in a for the first sample and hold period monotonic main DAC and the other is an offset DAC for input range expansion The offset DAC outputs three offset current values that provide three expanded ranges Within each range the main DAC has 14 bit resolution The raw digital data is output as 2 bits of offset range data plus 14 bits of main data To convert this intermittent binary data into consecutive data over the full input range the micro processor
77. urce This source is impractical for real designs because of the inability to supply very large currents at the voltage limit the output voltage until the current limit is reached How ever the current source must be able to clamp the output voltage with an infinite current source orsink capability In real applications such abnormal conditions can occur when the current source is incorrectly programmed or when the connections between its outputs and the pins of the device under test DUT are incorrect This capability for infinite current is not feasible in practical designs and it can easily damage the load or device under test There were two other considerations in designing the SMUs One was to obtain stable operation of each SMU independent of the other SMUs and the DUT s characteris tics The other was to prevent excessive SMU output volt age that could result in damage to a sensitive DUT One of the keys to stable SMU operation is the novel guard filter scheme This will be discussed later Most circuit designers have observed a partial or total loss of hpg for transistors operating in the low collector current region This is often caused by voltage transients For example a transient spike exceeding 25 mV can totally change the characteristics of some sensitive semiconductor devices Some of the methods used in the 4145A suppress undesirable excessive output voltages are implemented in the SMU hardware But much of the
78. y and a V measurement m consist quasistatic of the 4145A HP 4140B pA Meter DC Voltage Source and HP 4271B 1 MHz Digital LCR Meter Autosequence Programs The 4145A can be programmed to perform sequential measurements and output the results The autosequence 10 is an automated procedure for hpe lc 1 and or T a measurement sequence setup shown in Fig Ig Vg characteristics of a bipolar transi measuring the I nce autoseq activates the the program initiates plotter printer for hard copy results and then store LIST DISPLAY SHEE Li 04 GRAPHICS PLOT ssseee TEMPERATURE TRANSIENT 62 c aes GRAPHICS PLOT se quasistati Copr 1949 1998 Hewlett Packard Co high frequency capac MHz 13 Call up program from disc ST Single sweep Output CRT display contents to plotter Save test results on disc Allows viewing of results before output to plotter M Advance plotter page Wait time before execution of next Fig 10 A typical autosequence program for the 4145A This feature allows a user to develop measurement setups save them by name on the internal disc unit and then later call them back in any order automatically including plotting and saving any results measurement data on the flexible disc Test Fixture The 1
79. y a timer that counts the main processing unit clock pulses Another feature is SMU dc offset correction The SMU controller calibrates all dc offsets in the SMUs and cancels these parameters on every setting and measurement Con sequently there are no adjustable components on the SMU assemblies This improves the long term stability of the dc offset error specification The SMU controller also has a self test function Self test consists of two parts One is the test of the SMU controller itself and the analog to digital and digital to analog con verters interfacing the SMU controller to the SMUs and the other is the SMU test If an error occurs in the former test the SMU controller shuts down operation because this kind of error is a fatal error The system processor detects this stateand displays A01 on the CRT indicating that the SMU controller is down The light emitting diodes LEDs on the SMU controller board show the error number which indi cates the error block In the SMU test detected errors are not fatal to system operation The SMU controller simply re ports the results of the test and system operation continues At this time the CRT display shows the error number if any for each SMU The measurement section is divided into seven blocks excluding the SMU controller an analog to digital con verter ADC a digital to analog converter DAC four SMUS two VSs and two VMs The 16 bit ADC is combined with a 10 channel m

1982 , Volume , Issue Oct-1982

Contents

Download Pdf Manuals

Related Search

Related Contents