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STM8L051F3 - STMicroelectronics

1. STM8L051F3 Memory and register map Table 7 General hardware register map continued Address Block Register label Register name aaa prs us Reserved area 104 bytes 0x00 5430 Reserved area 1 byte 0x00 0x00 5431 RI ICR1 RI Timer input capture routing register 1 0x00 0x00 5432 RI ICR2 RI Timer input capture routing register 2 0x00 0x00 5433 RI IOIR1 RI I O input register 1 OxXX 0x00 5434 RI IOIR2 RI I O input register 2 OxXX 0x00 5435 RI IOIR3 RI I O input register 3 OxXX 0x00 5436 RI IOCMR1 RI I O control mode register 1 0x00 0x00 5437 RI IOCMR2 RI I O control mode register 2 0x00 0x00 5438 D RI IOCMR3 RI I O control mode register 3 0x00 0x00 5439 RI IOSR1 RI UO switch register 1 0x00 0x00 543A RI IOSR2 RI I O switch register 2 0x00 0x00 543B RI IOSR3 RI I O switch register 3 0x00 0x00 543C RI IOGCR RI I O group control register OxFF 0x00 543D RI ASCR1 Analog switch register 1 0x00 0x00 543E RI ASCR2 RI Analog switch register 2 0x00 0x00 543F RI RCR RI Resistor control register 0x00 0x00 5440 to Reserved area 16 bytes 0x00 544F 0x00 5450 RI CR RI I O control register 0x00 0x00 5451 RI MASKR1 RI I O mask register 1 0x00 0x00 5452 RI MASKR2 RI I O mask register 2 0x00 0x00 5453 RI MASKR3 RI I O mask register 3 0x00 0x00 5454 P RI MASKR4 RI I O mask register 4 0x00 0x00 5455 RI IOIRA RI UO input register 4 OxXX 0x00 5456 RI IOCMR4 RI UO control mode register 4 0x00 0
2. Address Block Register label Register name Reset status 0x00 50C4 CLK_PCKENR2 CLK Peripheral clock gating register 2 0x00 0x00 50C5 CLK_CCOR CLK Configurable clock control register 0x00 0x00 50C6 CLK_ECKCR CLK External clock control register 0x00 0x00 50C7 CLK_SCSR CLK System clock status register 0x01 0x00 50C8 CLK_SWR CLK System clock switch register 0x01 0x00 50C9 CLK_SWCR CLK Clock switch control register 0xX0 0x00 50CA CLK CLK CSSR CLK Clock security system register 0x00 0x00 50CB CLK CBEEPR CLK Clock BEEP register 0x00 0x00 50CC CLK HSICALR CLK HSI calibration register OxXX 0x00 50CD CLK HSITRIMR CLK HSI clock calibration trimming register 0x00 0x00 50CE CLK HSIUNLCKR CLK HSI unlock register 0x00 Obxx11 1 0x00 50CF CLK REGCSR CLK Main regulator control status register 00X 0x00 50DO CLK PCKENR3 CLK Peripheral clock gating register 3 0x00 0x00 50D1 to Reserved area 2 bytes 0x00 50D2 0x00 50D3 WWDG CR WWDG control register Ox7F WWDG 0x00 50D4 WWDG WR WWDR window register Ox7F 0x00 50D5 to Reserved area 11 bytes 00 50DF 0x00 50E0 IWDG KR IWDG key register 0x01 0x00 50E1 IWDG IWDG PR IWDG prescaler register 0x00 0x00 50E2 IWDG RLR IWDG reload register OxFF 0x00 50E3 to Reserved area 13 bytes 0x00 50EF 0x00 50FO BEEP CSR1 BEEP control status register 1 0x00 0x00 50F1 0x00 50F2 BEEP Reserved area 2 bytes 0x00 50F3 BEEP CSR2 BEEP control status register 2 Ox1F 0x00 50F4 to0x00 513F Reserved area 76 bytes 0x00 5140
3. Figure 15 Typical LSI frequency vs Vpp 45 43 41 39 37 eee e 33 40 C LSI frequency kHz Voo V ai18219V2 2 64 93 DoclD023465 Rev 2 STM8L051F3 Electrical parameters 8 3 5 Memory characteristics Ta 40 to 85 C unless otherwise specified Table 32 RAM and hardware registers Symbol Parameter Conditions Min Typ Max Unit VRM Data retention mode 1 Halt mode or Reset 1 8 V 1 Minimum supply voltage without losing data stored in RAM in Halt mode or under Reset or in hardware registers only in Halt mode Guaranteed by characterization not tested in production Flash memory Table 33 Flash program and data EEPROM memory Symbol Parameter Conditions Min Typ jos Unit Operating voltage Von all modes read write erase SEET ko Ga Y Programming time for 1 or 64 bytes block 6 ms erase write cycles on programmed byte t PS Programming time for 1 to 64 bytes block 3 ms write cycles on erased byte Ta 25 C Vpp 3 0 V lorog Programming erasing consumption 0 7 mA TA 25 C Vpp 1 8 V Data retention program memory after 100 1 erase write cycles at Ta 40 to 85 C mep tee 29 tret years Data retention data memory after 100000 Tor 85 C 300 erase write cycles at TA 40 to 85 C RET Erase write
4. 10 RTC window watchdog independent watchdog Others 16 MHz and 32 kHz internal RC 1 to 16 MHz and 32 kHz external oscillator CPU frequency 16 MHz Operating voltage 1 8 to 3 6 V Operating temperature 40 to 85 C Package TSSOP20 1 The number of GPIOs given in this table includes the NRST PA1 pin but the application can use the NRST PA1 pin as general purpose output only DAT 2 10 93 DoclD023465 Rev 2 STM8L051F3 Description 2 2 Note 2 Ultra low power continuum The ultra low power value line STM8L05xxx and STM8L15xxx are fully pin to pin software and feature compatible Besides the full compatibility within the STM8L family the devices are part of STMicroelectronics microcontrollers ultra low power strategy which also includes STM8L101xx and STM32L 15xxx The STM8L and STM32L families allow a continuum of performance peripherals system architecture and features They are all based on STMicroelectronics 0 13 um ultra low leakage process The STM8LO5xxx are pin to pin compatible with STM8L 101xx devices The STM32L family is pin to pin compatible with the general purpose STM32F family Please refer to STM32L 15x documentation for more information on these devices Performance All families incorporate highly energy efficient cores with both Harvard architecture and pipelined execution advanced STM8 core for STM8L families and ARM 32 bit Cortex M3 core for STM32L family In addition specific
5. WU neen i mode using HSI T i Wakeup time from Halt mode 3 4 Ewu_LSI Halt to Run mode using LSI 180 ps Ta 40 to 85 C no floating I O unless otherwise specified Tested in production ULP 0 or ULP 1 and FWU 1 in the PWR_CSR2 register Wakeup time until start of interrupt vector fetch The first word of interrupt routine is fetched 4 CPU cycles after twy gt o qwe 2 58 93 DoclD023465 Rev 2 STM8L051F3 Electrical parameters Current consumption of on chip peripherals Table 24 Peripheral current consumption Typ i Symbol Parameter Vop 3 0 V Unit Ipp riM2 TIM2 supply current 1 8 IDD TIM3 TIM3 supply current 1 8 Ipp riM4 TIM4 timer supply current 1 3 IDD USART1 USART1 supply current 2 6 HA MHZ Ipp sPH SPI1 supply current 2 3 IDD I201 12C1 supply current 2 5 IDD DMA1 DMA1 supply current 3 IbowwbG WWDG supply current 2 IDD ALL Peripherals ON 44 yA MHz IDD ADC1 ADC1 supply current 1500 Power voltage detector and brownout Reset unit supply IDD PVD BOR 5 2 6 current IDD BOR Brownout Reset unit supply current 9 24 UA including LSI supply 0 45 current IDD IDWDG Independent watchdog supply current excluding LSI 0 05 supply current 1 Data based on a differential Ipp measurement between all peripherals OFF and a timer counter running at 16 MHz The CPU is in Wait mode in both cases No I
6. ai18227V2 Figure 22 Typ Vo Vpp 3 0 V true open drain ports Figure 23 Typ Vo Vpp 7 1 8 V true open drain ports 0 5 40 C 04 a 25C 85 C 0 3 3 gt 0 2 me E ee A i gem 0 1 g 3 4 5 6 T lo mA ai18228V2 Figure 24 Typ Vpp Vou O Vpp 3 0 V high sink ports 0 5 0 4 40 C 25 C 0 3 a z 85 C gt 0 2 0 1 a gt et 0 1 2 3 4 5 6 7 lo mA ai18229V2 Figure 25 Typ Vpp Von O Vpp 1 8 V high sink ports 1 75 40 C 15 a 25 C E 85 C s 1 25 3 gt i 8 075 0 5 0 25 p on 0 2 4 6 8 10 12 14 16 18 20 lon mA ai12830V2 0 5 40 C 25 C 0 4 85 C gt 0 3 3 gt B8 02 0 1 0 0 1 2 5 6 7 3 lou mA ai18231V2 2 DoclD023465 Rev 2 71 93 Electrical parameters STM8L051F3 NRST pin Subject to general operating conditions for Vpp and Ta unless otherwise specified Table 39 NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit Vi NRST NRST input low level voltage 1 Vss 0 8 VIH NRST NRST input high level voltage UI 14 Vpp loL 2 mA V for 2 7 V Vpp 23 6 V VoL NRST NRST output low level voltage 1 0 4 lo 1 5 mA for Vpp 27V 10 Vpp Vuyst NRST input hysteresis 2 mV RPU NRST SCH pull up equivalent resistor 30 45 60 ko Ve NRST NRST input filtered pulse 9 50 ns VNF NRS
7. and register map Table 5 Flash and RAM boundary addresses Memory area Size Start address End address RAM 1 Kbyte 0x00 0000 0x00 03FF Flash program memory 8 Kbytes Ox00 8000 0x00 9FFF 5 2 Register map Table 6 I O port hardware register map Address Block Register label Register name buda 0x00 5000 PA ODR Port A data output latch register 0x00 0x00 5001 PA IDR Port A input pin value register OxXX 0x00 5002 Port A PA DDR Port A data direction register 0x00 0x00 5003 PA CR1 Port A control register 1 0x01 0x00 5004 PA CR2 Port A control register 2 0x00 0x00 5005 PB ODR Port B data output latch register 0x00 0x00 5006 PB IDR Port B input pin value register OxXX 0x00 5007 Port B PB DDR Port B data direction register 0x00 0x00 5008 PB CR1 Port B control register 1 0x00 0x00 5009 PB CR2 Port B control register 2 0x00 0x00 500A PC ODR Port C data output latch register 0x00 0x00 500B PB IDR Port C input pin value register OxXX 0x00 500C Port C PC DDR Port C data direction register 0x00 0x00 500D PC CR1 Port C control register 1 0x00 0x00 500E PC CR2 Port C control register 2 0x00 0x00 500F PD ODR Port D data output latch register 0x00 0x00 5010 PD IDR Port D input pin value register OxXX 0x00 5011 Port D PD DDR Port D data direction register 0x00 0x00 5012 PD CR1 Port D control register 1 0x00 0x00 5013 PD CR2 Port D
8. fe SA life augmented STM8L051F3 Value Line 8 bit ultralow power MCU 8 KB Flash 256 byte data EEPROM RTC timers USART I2C SPI ADC Features March 2014 Operating conditions Operating power supply 1 8 V to 3 6 V Temperature range 40 C to 85 C Low power features 5low power modes Wait Low power run 5 1 uA Low power wait 3 A Active halt with RTC 1 3 pA Halt 350 nA Ultra low leakage per 1 0 50 nA Fast wakeup from Halt 5 us Advanced STM8 core Harvard architecture and 3 stage pipeline Maxfreq 16 MHz 16 CISC MIPS peak Up to 40 external interrupt sources Reset and supply management Low power ultra safe BOR reset with 5 selectable thresholds Ultra low power POR PDR Programmable voltage detector PVD Clock management 32 kHz and 1 to 16 MHz crystal oscillators Internal 16 MHz factory trimmed RC Internal 38 kHz low consumption RC Clock security system Low power RTC BCD calendar with alarm interrupt Digital calibration with 0 5 ppm accuracy LSE security system Auto wakeup from Halt w periodic interrupt Memories 8 Kbytes of Flash program memory and 256 bytes of data EEPROM with ECC Flexible write and read protection modes 1 Kbyte of RAM Datasheet production data NS NS a TSSOP20 DMA 4 channels supporting ADC SPI DC USART timers 1 channel for memory to
9. 18 3 9 System configuration controller and routing interface 19 SH MES a a eke ANA a m ee ek aa sale Ra Ra c 19 3 10 1 16 bit general purpose timers TIM2 TIM3 o o o o o 19 3 10 2 8 bitbasictimer TIMA ers 19 3 11 Watchdog timers aken sandal aor Rr merce ax dee 19 3 11 1 Window watchdog timer esses 20 3 11 2 Independent watchdog timer oo 20 3 12 Beeper EN hae d NEEN ER EENS ke RE Rc E E ax eos 20 3 13 Communication interfaces 20 E ILIO DPI pr CCP EP 20 on D c PP 20 3 13 3 USART 43 03 34 dane bed ped mem EAT 21 3 14 Infrared IR interface A NEE ENEE kk RR a 21 2 93 DocID023465 Rev 2 Ly STM8L051F3 Contents 3 15 Development support 20 00 00 cee 21 4 Pin description casa rada nda radial 23 4 1 System configuration options 25 5 Memory and register map 2 00 e cece eee eee 26 5 1 Memory mapping c uc ph ee d doe dos ERES AKALA 26 5 2 R gister Map Em 27 6 Interrupt vector mapping 40 7 Option DyteS sonrisas dress 5 EE 42 8 Electrical parameters 45 8 1 Parameter conditions ccc eee 45 8 1 1 Minimum and maximum values 22 eee 45 8 1 2 Typical Values a da a ANN yam e DR AC NEE ENN AR 45 8 1 3 Typical curves 45 8 1 4 Loading capacitor arinak kaa a ren 45 8 1 5 Pin input voltage voeem e REED EU MR ORRE RA 46 8 2 Absolute maximum ratings oo 46 8 3 Operating conditi
10. VDD LSI clock source aaae 55 Typ IDD LPW vs VDD LSI clock source een 56 HSE oscillator circuit diagram liliis ren 61 LSE oscillator circuit diagram eh 62 Typical HSI frequency vs Ven 63 Typical LSI frequency vs VDD 2 hr 64 Typical VIL and VIH vs VDD high sink I Os 0 else 68 Typical VIL and VIH vs VDD true open drain I Os 0 68 Typical pull up resistance Rp vs Vpp with VIN VSS 0 0 00 eee eee 69 Typical pull up current Ip vs Von with VIN 69 Typ VOL VDD 3 0 V high sink porte 71 Typ VOL VDD 1 8 V high sink porte 71 Typ VOL VDD 3 0 V true open drain porte 71 Typ VOL VDD 1 8 V true open drain porte 71 Typ VDD VOH VDD 3 0 V high sink porte 71 Typ VDD VOH VDD 1 8 V high sink ports esee 71 Typical NRST pull up resistance Rp VS VDD B 72 Typical NRST pull up current VDD seemed edam ia e erenn 73 Recommended NRST pin configuration lille 73 SPI1 timing diagram slave mode and CPHA 0 0 2200 75 SP11 timing diagram slave mode and CPHA 1 aa et eege 75 SP11 timing diagram master mode MAD 76 Typical application with DC bus and timing diagram 1 78 ADC1 accuracy characteristics 2 83 Typical connection diagram using the ADC 0000 c eee eee 83 Maximum dynamic current consumption on Mer supply pin during ADC sonic T 84 Power supply and reference decoup
11. 0x00 0x00 525C TIM2 CNTRH TIM2 counter high 0x00 0x00 525D TIM2_CNTRL TIM2 counter low 0x00 0x00 525E TIM2_PSCR TIM2 prescaler register 0x00 0x00 525F TIM2_ARRH TIM2 auto reload register high OxFF 34 93 DoclD023465 Rev 2 er STM8L051F3 Memory and register map Table 7 General hardware register map continued Address Block Register label Register name ee 0x00 5260 TIM2 ARRL TIM2 auto reload register low OxFF 0x00 5261 TIM2 CCR1H TIM2 capture compare register 1 high 0x00 0x00 5262 TIM2 CCR1L TIM2 capture compare register 1 low 0x00 0x00 5263 TIM2 TIM2 CCR2H TIM2 capture compare register 2 high 0x00 0x00 5264 TIM2 CCR2L TIM2 capture compare register 2 low 0x00 0x00 5265 TIM2 BKR TIM2 break register 0x00 0x00 5266 TIM2 OISR TIM2 output idle state register 0x00 UE Reserved area 25 bytes 0x00 5280 TIM3 CR1 TIM3 control register 1 0x00 0x00 5281 TIM3 CR2 TIMS control register 2 0x00 0x00 5282 TIM3 SMCR TIM3 Slave mode control register 0x00 0x00 5283 TIM3 ETR TIMS external trigger register 0x00 0x00 5284 TIM3 DER TIM3 DMA1 request enable register 0x00 0x00 5285 TIMS3 IER TIM3 interrupt enable register 0x00 0x00 5286 TIM3 SR1 TIM3 status register 1 0x00 0x00 5287 TIM3 SR2 TIM3 status register 2 0x00 0x00 5288 TIM3 EGR TIM3 event generation regist
12. 2 Data output hold time Master mode after enable 4 h MO edge ui 1 Parameters are given by selecting 10 MHz I O output frequency 2 Values based on design simulation and or characterization results and not tested in production 3 Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data 4 Min time is for the minimum time to invalidate the output and max time is for the maximum time to put the data in Hi Z 74 93 DoclD023465 Rev 2 2 STM8L051F3 Electrical parameters Figure 29 SPI1 timing diagram slave mode and CPHA 0 CPHA 0 an WB S v CPOL 0 SCK Input OO i VT o a 7 O A FE 8 v SO gt i lg tr SCK t 5 gt h SO ME mur Mim dis SO MISO 5 weer r y tsu Sl gt w T L sn X INPUT MSB IN EA IN LSB IN tS ai14134 Figure 30 SPI1 timing diagram slave mode and CPHA 1 m NSS input A fi ISU NSS He La ic SCKj gt h NSS 9 CPHA 1 Ah XA E a CPOL 0 i i x CPHA 1 Mee aaa B 9 CPOL 1 ma maa am GE VSO gt e Lue GER gt Th so MS0 gt e th SO Kee Seo MISO Cute hour wsBour BIT6 OUT Bou OUT tsu V r gt hs gt gt Liens MSB IN BITI IN LSB IN INPUT j ai14135 1 Measurement points are done at CMOS levels 0 3Vpp and 0 7Vpp 2 DoclD023465 Rev 2 75 93 Electrical parame
13. 36 0 39 KA OFF code f 1 MH IDD RUN ip Run a HSE external PU S E mode y clock fcpy 4 MHz 1 15 131 1 40 DD trom 4 fcpufuse O 1 8 V to 3 6 V fcpu 8 MHz 217 2 33 244 fopy 16 MHz 40 446 4 52 LSI RC osc fcpu fi si 0 110 0 123 0 130 LSE ext clock 32 768 fcpu fLse 0 100 0 101 0 104 kHz 1 All peripherals OFF Vpp from 1 8 V to 3 6 V HSI internal RC osc feru fsyscLk 2 CPU executing typical data processing The run from RAM consumption can be approximated with the linear formula Ipp run from RAM Freq 90 pA MHz 380 pA Ly DoclD023465 Rev 2 51 93 Electrical parameters STM8L051F3 4 Oscillator bypassed HSEBYP 1 in CLK ECKCR When configured for external crystal the HSE consumption Ibp Hse must be added Refer to Table 28 Tested in production The run from Flash consumption can be approximated with the linear formula Ipp run from Flash Freq 195 pA MHz 440 yA 7 Oscillator bypassed LSEBYP 1 in CLK ECKCR When configured for extenal crystal the LSE consumption Ipp tse must be added Refer to Table 29 Figure 8 Typ Ipp RUN VS Vpp fcPu 16 MHz 3 00 2 75 2 50 2 25 2 00 IDD RUN HSI mA 1 75 1 50 1 8 2 1 2 6 3 1 3 6 Von V ai18213V2 1 Typical current consumption measured with code executed from RAM 2 52 93 DoclD023465 Rev 2 STM8L051F3 Electrical parameters 2 In the following t
14. Low power run and Low power wait modes When entering Halt or Active halt modes the system automatically switches from the MVR to the LPVR in order to reduce current consumption DoclD023465 Rev 2 15 93 Functional overview STM8L051F3 3 4 16 93 Clock management The clock controller distributes the system clock SYSCLK coming from different oscillators to the core and the peripherals It also manages clock gating for low power modes and ensures clock robustness Features e Clock prescaler to get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler e Safe clock switching Clock sources can be changed safely on the fly in run mode through a configuration register e Clock management To reduce power consumption the clock controller can stop the clock to the core individual peripherals or memory e System clock sources four different clock sources can be used to drive the system clock 1 16 MHz High speed external crystal HSE 16 MHz High speed internal RC oscillator HSI 32 768 Low speed external crystal LSE 38 kHz Low speed internal RC LSI e RTC clock sources the above four sources can be chosen to clock the RTC whatever the system clock e Startup clock After reset the microcontroller restarts by default with an internal 2 MHz clock HSI 8 The prescaler ratio and clock source can be ch
15. MHz 44 us t Wakeup time from OFF 3 WKUP state H o 7 te 6 Time before a new Ta 25 C 10 s IDLE conversion Ta 70 C 20 ms t Internal reference refer to ms VREFINT voltage startup time Table 42 1 The current consumption through Vpep is composed of two parameters one constant max 300 yA one variable max 400 pA only during sampling time 2 first conversion pulses So peak consumption is 300 400 700 pA and average consumption is 300 4 sampling 2 16 x 400 450 pA at 1Msps p o gx decor m 2 Vrer OF Vppa must be tied to ground Guaranteed by design not tested in production Value obtained for continuous conversion on fast channel The tjpj g maximum value is coon the Z revision code of the device Minimum sampling and conversion time is reached for maximum Rext 0 5 kQ DoclD023465 Rev 2 The time between 2 conversions or between ADC ON and the first conversion must be lower than Ir 81 93 Electrical parameters STM8L051F3 In the following three tables data is guaranteed by characterization result not tested in production Table 44 ADC1 accuracy with VppA 3 3 V to 2 5 V Symbol Parameter Conditions Typ Max Unit fapc 16 MHz 1 1 6 DNL Differential non linearity fapc 8 MHz 1 1 6 fapc 4 MHz 1 1 5 fanc 16 MHz 1 2 2 INL
16. SSRH RTC Subsecond register high 0x00 0x00 5159 RTC WPR RTC Write protection register 0x00 0x00 5158 RTC SSRH RTC Subsecond register high 0x00 0x00 5159 RTC WPR RTC Write protection register 0x00 0x00 515A RTC SHIFTRH RTC Shift register high 0x00 0x00 515B RTC SHIFTRL RTC Shift register low 0x00 0x00 515C RTC ALRMAR1 RTC Alarm A register 1 0x00 1 0x00 515D RTC ALRMAR2 RTC Alarm A register 2 0x001 0x00 515E RTC_ALRMAR3 RTC Alarm A register 3 0x00 1 0x00 515F RTC ALRMAR4 RTC Alarm A register 4 0x001 EE Reserved area 4 bytes 0x00 5164 RTC ALRMASSRH RTC Alarm A subsecond register high 0x00 1 0x00 5165 RTC ALRMASSRL RTC Alarm A subsecond register low 0x00 1 32 93 DoclD023465 Rev 2 er STM8L051F3 Memory and register map Table 7 General hardware register map continued Address Block Register label Register name ada 0x00 5166 RTC ALRMASSMSKR RTC Alarm A masking register 0x001 p B Reserved area 3 bytes 0x00 516A RTC CALRH RTC Calibration register high 0x00 1 0x00 516B RTC CALRL RTC Calibration register low 0x001 0x00 516C is RTC TCR1 RTC Tamper control register 1 0x00 1 0x00 516D RTC TCR2 RTC Tamper control register 2 0x001 ee Kerg Reserved area 36 bytes 0x00 5190 CSSLSE CSR CSS on LSE control and status register 0x00 1 Kao bois Reserved area 11
17. The low density STM8L05xxx devices contain an infrared interface which can be used with an IR LED for remote control functions Two timer output compare channels are used to generate the infrared remote control signals Development support Development tools Development tools for the STM8 microcontrollers include e The STice emulation system offering tracing and code profiling e The STVD high level language debugger including C compiler assembler and integrated development environment e TheSTVP Flash programming software The STM8 also comes with starter kits evaluation boards and low cost in circuit debugging programming tools Single wire data interface SWIM and debug module The debug module with its single wire data interface SWIM permits non intrusive real time in circuit debugging and fast memory programming The Single wire interface is used for direct access to the debugging module and memory programming The interface can be activated in all device operation modes The non intrusive debugging module features a performance close to a full featured emulator Beside memory and peripherals CPU operation can also be monitored in real time by means of shadow registers DoclD023465 Rev 2 21 93 Functional overview STM8L051F3 22 93 Bootloader The low density value line STM8LO5xxx ultra low power devices feature a built in bootloader see UM0560 STM8 bootloader user manual The bootloader is used to downloa
18. Vppa lt 3 6 V 1 8 V sVppa lt 2 4 V 2 4 V lt Vopa lt 3 3 V 1 8 V lt Vopa lt 2 4 V 4 0 25 Not allowed Not allowed 0 7 Not allowed 9 0 5625 0 8 Not allowed 2 0 1 0 16 1 2 0 0 8 4 0 3 0 24 1 5 3 0 1 8 6 0 4 5 48 3 6 8 4 0 15 0 10 0 96 6 15 0 10 0 30 0 20 0 192 12 32 0 25 0 50 0 40 0 384 24 50 0 50 0 50 0 50 0 Power supply decoupling should be performed as shown in Figure 36 or Figure 37 depending on whether Ver is connected to Vppa or not Good quality ceramic 10 nF capacitors should be used They should be placed as close as possible to the chip DoclD023465 Rev 2 2 STM8L051F3 Electrical parameters Figure 36 Power supply and reference decoupling VRef not connected to Vppa External reference 1 uF 10 nF Supply 1 pF 10 nF ai17031b Figure 37 Power supply and reference decoupling VRef connected to VppA VREF VDDA Supply 1 uF 10 nF Vrer Vssa ai17032b 2 DoclD023465 Rev 2 85 93 Electrical parameters STM8L051F3 8 3 11 86 93 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization Functional EMS electromagnetic susceptibility Based on a simple running application on the product toggling 2 LEDs through UO ports the product is stressed by two electromagnetic events until a failure occurs indicated by the LEDs e ESD Electrostatic discharge positive and negat
19. at 38 kHz Ta 40 C to 25 C 54 57 with TIM2 active T 55 C 6 0 6 3 one Supply current in Ta 85 C 7 2 7 8 ta LPR Low power run mode TA7 40 Ct025 C 525 5 6 all peripherals OFF TA 55 C 5 67 6 1 LSE 9 external Ta 85 C 5 85 6 3 clock M a 32 768 kHz TA7 40 Ct025 C 5 59 6 with TIM2 active 2 T4 55 C 6 10 6 4 Ta 85 C 6 30 7 No floating I Os 2 Timer 2 clock enabled and counter running Oscillator bypassed LSEBYP 1 in CLK_ECKCR When configured for extenal crystal the LSE consumption Ibp Lse must be added Refer to Table 29 Figure 10 Typ Ipp LPR VS Vpp LSI clock source 18 16 14 40 C m 25 C 12 Tz 85 C 10 8 z 6 9 eene A 2 0 18 2 1 2 6 3 1 3 6 Vpp V ai18216V2 Ly DoclD023465 Rev 2 55 93 Electrical parameters STM8L051F3 In the following table data is based on characterization results unless otherwise specified Table 20 Total current consumption in Low power wait mode at Vpp 7 1 8 V to 3 6 V Symbol Parameter Conditions Typ Max Unit TA 40 C to 25 C 3 3 3 all peripherals OFF TA 55 C 3 3 3 6 LSI RC osc Ta 85 C 44 5 at 38 kHz Ta 40 C to 25 C 3 4 3 7 with TIM2 active TA 55 C 37 4 l de Geer Ta 85 C 48 54 DD LPW Low power wai aii mode Ta 40 C to 25 C 2 35 2 7 all peripherals OFF T 55 C 2 42 2 82 pk ia Ta 85 C 3 10 3 71 cl
20. control register 2 0x00 0x00 5014 to Reserved area 0 bytes 0x00 501D er DoclD023465 Rev 2 27 93 Memory and register map STM8L051F3 Table 7 General hardware register map Address Block Register label Register name Reset status 0x00 502E to Reserved area 44 bytes 0x00 5049 0x00 5050 FLASH CR1 Flash control register 1 0x00 0x00 5051 FLASH CR2 Flash control register 2 0x00 0x00 5052 Flash FLASH _PUKR Flash program memory unprotection key register 0x00 0x00 5053 FLASH DUKR Data EEPROM unprotection key register 0x00 0x00 5054 FLASH IAPSR Flash in application programming status register 0x00 0x00 5055 to Reserved area 27 bytes 0x00 506F 0x00 5070 DMA1 GCSR DMA1 global configuration amp status register OxFC 0x00 5071 DMA1 GIR1 DMA1 global interrupt register 1 0x00 0x00 5072 to Reserved area 3 0x00 5074 bytes 0x00 5075 DMA1 COCR DMA1 channel O configuration register 0x00 0x00 5076 DMA1 COSPR DMA1 channel 0 status amp priority register 0x00 0x00 5077 DMA1 CONDTR DMA1 number of data to transfer register 0x00 a channel 0 d DMA1 peripheral add high regist 0x00 5078 DMA1 COPARH ideo Tgn ee 0x52 E channel 0 0x00 5079 DMA1 COPARL DMA1 peripheral address low register 0x00 channel 0 0x00 507A Reserved area 1 byte 0x00 507B DMA1 COMOARH DMA1 memory 0 address high register 0x00 channel 0 0x00 507C DMA1 C
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22. 039 1 Values in inches are converted from mm and rounded to 4 decimal digits 2 Dimension D does not include mold flash protrusions or gate burrs Mold flash protrusions or gate burrs shall not exceed 0 15mm per side 3 Dimension E1 does not include interlead flash or protrusions Interlead flash or protrusions shall not exceed 0 25mm per side 2 DoclD023465 Rev 2 89 93 Package characteristics STM8L051F3 9 3 90 93 Thermal characteristics The maximum chip junction temperature T max must never exceed the values given in Table 15 General operating conditions on page 48 The maximum chip junction temperature T Jmax in degree Celsius may be calculated using the following equation TJmax Tamax PDmax X Dal Where e Tamax is the maximum ambient temperature in C e Oya is the package junction to ambient thermal resistance in C W Ppmax is the sum of Pintmax and Pijomay PDmax PINTmax Pomaxd e PinTmax S the product of Ipp and Vpp expressed in Watts This is the maximum chip internal power e Promax represents the maximum power dissipation on output pins Where Pjjomax Vor Jo Z Vpp Vou og taking into account the actual Volle and Vop lop of the I Os at low and high level in the application Table 53 Thermal characteristics Symbol Parameter Value Unit Thermal resistance junction ambient CAN TSSOP20 Thermal resistances are based on JEDE
23. 0x00 508F DMA1 C2MOARH DMA1 memory 0 address high register 0x00 channel 2 0x00 5090 DMA1 C2MOARL DMA1 memory O address low register 0x00 channel 2 0x00 5091 0x00 5092 Reserved area 2 bytes 0x00 5093 DMA1 C3CR DMA1 channel 3 configuration register 0x00 0x00 5094 DMA1 C3SPR DMA channel 3 status amp priority register 0x00 0x00 5095 DMA1 C3NDTR DMA1 number of data to transfer register 0x00 channel 3 DMA1 C3PARH DMA1 peripheral address high register 0O 209e C3M1ARH channel 3 SEN DMA1 C3PARL DMA1 peripheral address low register 0x00 3937 C3M1ARL channel 3 SH KYI DoclD023465 Rev 2 29 93 Memory and register map STM8L051F3 Table 7 General hardware register map continued Address Block Register label Register name Reset status 0x00 5098 DMA C3MOEAR DMA channel 3 memory 0 extended address 0x00 register 0x00 5099 DMA1 C3MOARH DMA1 memory 0 address high register 0x00 channel 3 DMA1 f 0x00 509A DMA1 C3MOARL DMA1 memory 0 address low register 0x00 m channel 3 0x00 509B to 0x00 509C Reserved area 3 bytes 0x00 509D SYSCFG RMPCR3 Remapping register 3 0x00 0x00 509E SYSCFG SYSCFG RMPCR1 Remapping register 1 0x00 0x00 509F SYSCFG RMPCR2 Remapping register 2 0x00 0x00 50A0 EXTI CR1 External interrupt control register 1 0x00 0x00 50A1 EXTI CR2 External in
24. 0x00 7F77 ITC SPR8 Interrupt Software priority register 8 OxFF 0x00 7F78 to Reserved area 2 bytes 0x00 7F79 0x00 7F80 SWIM SWIM CSR SWIM control status register 0x00 0x00 7F81 to Reserved area 15 bytes 0x00 7F8F 0x00 7F90 DM BK1RE DM breakpoint 1 register extended byte OxFF 0x00 7F91 DM BK1RH DM breakpoint 1 register high byte OxFF 0x00 7F92 DM BK1RL DM breakpoint 1 register low byte OxFF 0x00 7F93 DM DM BK2RE DM breakpoint 2 register extended byte OxFF 0x00 7F94 DM BK2RH DM breakpoint 2 register high byte OxFF 0x00 7F95 DM BK2RL DM breakpoint 2 register low byte OxFF 0x00 7F96 DM CR1 DM Debug module control register 1 0x00 38 93 DoclD023465 Rev 2 er STM8L051F3 Memory and register map Table 8 CPU SWIM debug module interrupt controller registers continued Address Block Register label Register name mesel status 0x00 7F97 DM_CR2 DM Debug module control register 2 0x00 0x00 7F98 Ba DM CSR1 DM Debug module control status register 1 0x10 0x00 7F99 DM CSR2 DM Debug module control status register 2 0x00 0x00 7F9A DM ENFCTR DM enable function register OxFF 0x00 7F9B to Reserved area 5 bytes 0x00 7F9F 1 Accessible by debug module only Ky DoclD023465 Rev 2 39 93 Interrupt vector mapping STM8L051F3 6 Interrupt vector mapping Table 9 Interrupt mapping Wakeup Wakeup Wakeup IRQ Source
25. 1 bytes 0x00 5200 SPI1 CR1 SPI1 control register 1 0x00 0x00 5201 SPI1 CR2 SPI1 control register 2 0x00 0x00 5202 SPI1 ICH SPI interrupt control register 0x00 0x00 5203 SPI SR SPI status register 0x02 0x00 5204 bak SPI1 DR SPI1 data register 0x00 0x00 5205 SPI1 CRCPR SPI1 CRC polynomial register 0x07 0x00 5206 SPI1 RXCRCR SPI1 Rx CRC register 0x00 0x00 5207 SPI1 TXCRCR SPI1 Tx CRC register 0x00 0x00 5208 to Reserved area 8 bytes 0x00 520F 0x00 5210 I2C1 CR1 I2C1 control register 1 0x00 0x00 5211 I2C1 CR2 I2C1 control register 2 0x00 0x00 5212 I2C1 FREQR I2C1 frequency register 0x00 0x00 5213 I2C1 OARL I2C1 own address register low 0x00 0x00 5214 DC OARH I2C1 own address register high 0x00 0x00 5215 I2C1 OAR2 I2C1 own address register for dual mode 0x00 0x00 5216 1201 I2C1 DR I2C1 data register 0x00 0x00 5217 I2C1 SR1 I2C1 status register 1 0x00 0x00 5218 DC SR2 I2C1 status register 2 0x00 0x00 5219 I2C1 SR3 I2C1 status register 3 0x0X 0x00 521A I2C1 ITR I2C1 interrupt control register 0x00 0x00 521B I2C1 CCRL I2C1 clock control register low 0x00 0x00 521C I2C1 CCRH I2C1 clock control register high 0x00 er DoclD023465 Rev 2 33 93 Memory and register map STM8L051F3 Table 7 General hardware register map continued Address Block Register la
26. 58 Reserved 0x00 5FFF 0x00 6000 Boot ROM 0x00 67FF 2 Kbytes 0x00 6800 Reserved 0x00 7EFF 0x00 7F00 CPU SWIM Debug ITC Registers 0x00 7FFF 0x00 8000 0x00 80FF 0x00 8100 Low density Flash program memory 8 Kbytes 0x00 9FFF uc 0x00 5000 0x00 501E 0x00 5050 0x00 5055 0x00 5070 0x00 509D 0x00 50A0 0x00 50A6 0x00 50AA 0x00 50A9 0x00 50B0 0x00 50B2 0x00 50B4 0x00 50CO 0x00 50D1 0x00 50D3 0x00 50D5 0x00 50E0 0x00 50E3 0x00 50F0 0x00 50F4 0x00 5040 0x00 5191 0x00 5200 0x00 5208 0x00 5210 0x00 521F 0x00 5230 0x00 523B 0x00 5250 0x00 5267 0x00 5280 0x00 5297 0x00 52E0 0x00 52EA 0x00 52FF 0x00 5317 0x00 5340 0x00 53C8 0x00 5430 0x00 5440 0x00 5450 0x00 5457 GPIO ports Reserved Flash Reserved DMA1 SYSCFG ITC EXT1 E m ITC EXT1 Reserved pu N T zu 2 Reserved C 2 Reserved WWDG Reserved IWDG Reserved BEEP Reserved RTC Reserved SPI1 Reserved DCH Reserved USART1 Reserved TIM2 Reserved TIM3 Reserved TIM4 Reserved IRTIM Reserved ADC1 Reserved Reserved MS18274V3 Table 5 lists the boundary addresses for each memory size The top of the stack is at the RAM end address Refer to Table 7 for an overview of hardware register mapping to Table 6 for details on I O port hardware registers and to Table 8 for information on CPU SWIM debug module controller registers DoclD023465 Rev 2 Ly STM8L051F3 Memory
27. 7 Typical Vj and Vu vs Vpp true open drain I Os 1 8 2 1 2 6 3 1 3 6 Voo V ai18221V2 2 DoclD023465 Rev 2 STM8L051F3 Electrical parameters Figure 18 Typical pull up resistance Rpy vs Vpp With Viy Vss Pull Up resistance kQ 60 55 50 45 40 35 1 8 2 2 2 24 2 6 2 8 3 3 2 3 4 3 6 Vpp V ai18222V2 Figure 19 Typical pull up current ly vs Vpp With Vin Vss Pull Up current uA 120 100 80 60 40 20 0 1 8 1 95 2 1 225 24 2 55 27 2 85 3 3 15 33 345 3 6 ai18223V2 2 DoclD023465 Rev 2 69 93 Electrical parameters STM8L051F3 70 93 Output driving current Subject to general operating conditions for Vpp and Ta unless otherwise specified Table 36 Output driving current high sink ports NO Symbol Parameter Conditions Min Max Unit Type Jeje SATIN 045 V Vpp 3 0V Vio Output lowievervetagetoraniiapin OP ES 045 V OL utput low level voltage for an pin Vpp 1 8 V i x lio 10 mA 0 7 V 5 Vpp 3 0V c D lio 2 mA Vpp 0 45 Vppz30v V220 y lio 1 mA 2 P IO j VoH Output high level voltage for an UO pin Vop 1 8 V Vpp 0 45 V lio 10 mA V 0 7 V Vpp 3 0 V Bie The lig current sunk must always respect the absolute maximum rating specified in Table 13 and the sum of lio I O ports and cont
28. BOR TH 2 0 001 Rising edge 1 96 2 04 2 07 V Brown out reset threshold 2 Falling edge 2 22 2 3 2 35 V BOR BOR TH 2 0 010 Rising edge 2 31 241 2 44 V Brown out reset threshold 3 Falling edge 2 45 2 55 2 60 BOR BOR TH 2 0 011 Rising edge 2 54 2 66 27 V Brown out reset threshold 4 Falling edge 2 68 2 80 2 85 BORA y BOR TH 2 0 100 Rising edge 2 78 2 90 2 95 Falling edge 1 80 1 84 1 88 Vpypo PVD threshold 0 Rising edge 1 88 1 94 1 99 Falling edge 1 98 2 04 2 09 Vpyp1 PVD threshold 1 Rising edge 2 08 2 14 2 18 Falling edge 2 2 2 24 2 28 Vpyp2 PVD threshold 2 Rising edge 2 28 2 34 2 38 Falling edge 2 39 2 44 2 48 Vpyp3 PVD threshold 3 V Rising edge 2 47 2 54 2 58 Falling edge 2 57 2 64 2 69 Vpyp4 PVD threshold 4 Rising edge 2 68 2 74 2 79 Falling edge 2 77 2 83 2 88 Vpyps PVD threshold 5 Rising edge 2 87 2 94 2 99 Falling edge 2 97 3 05 3 09 VpvD6 PVD threshold 6 Rising edge 3 08 3 15 3 20 1 Data guaranteed by design not tested in production 2 Data based on characterization results not tested in production Zar DoclD023465 Rev 2 49 93 Electrical parameters STM8L051F3 8 3 3 50 93 Figure 7 POR BOR thresholds Vdd Vdd 3 6V i Operating power supply 1 8 V BOR threshold vBoRo 12 8 i E FE VPDR de Et 10 o ro KR ix D o 1 9 1 Internal NRST with without BOR BOR BOR always active BOR activated by user for Time at power up power down detection Supply current chara
29. C JESD51 2 with 4 layer PCB in a natural convection environment 2 DoclD023465 Rev 2 STM8L051F3 Device ordering information 10 Device ordering information 2 Example Product class STMB8 microcontroller Family type L Low power Sub family type 051 Ultra low power Pin count F 20 pins Program memory size 3 8 Kbytes Package P TSSOP Temperature range 6 40 to 85 C STM8 a L 051 F 3 DoclD023465 Rev 2 P Figure 40 Low density value line STM8L051F3 ordering information scheme 6 For a list of available options e g memory size package and orderable part numbers or for further information on any aspect of this device please contact the ST sales office nearest to you 91 93 Revision history STM8L051F3 11 92 93 Revision history Table 54 Document revision history Date Revision Changes 01 Aug 2012 1 Initial release Updated TSSOP20 package information Updated pin name related to pin1 and 2 inside Table 4 Low density 26 Mar 2014 2 value line STM8LO5xxx pin description Updated inside Table 10 Option byte addresses OPT5 default factory of BOR to 0x00 DoclD023465 Rev 2 2 STM8L051F3 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections
30. C OC programmed no UO pins toggling Not tested in production 2 Data based on a differential Ipp measurement between the on chip peripheral in reset configuration and not clocked and the on chip peripheral when clocked and not kept under reset The CPU is in Wait mode in both cases No I O pins toggling Not tested in production 3 Peripherals listed above the Ipp A parameter ON TIM1 TIM2 TIM3 TIM4 USART1 SPI1 I2C1 DMA1 WWDG Data based on a differential Ipp measurement between ADC in reset configuration and continuous ADC conversion gn s Including supply current of internal reference voltage Table 25 Current consumption under external reset Symbol Parameter Conditions Typ Unit Vop 1 8V 48 Supply current under All pins are externally l Vop 3V 76 A DD RST external reset 1 tied to Vpp BB n Vop 3 6V 91 1 All pins except PAO PBO and PB4 are floating under reset PAO PBO and PB4 are configured with pull up under reset Ly DocID023465 Rev 2 59 93 Electrical parameters STM8L051F3 8 3 4 Clock and timing characteristics HSE external clock HSEBYP 1 in CLK ECKCR Subject to general operating conditions for Vpp and T Table 26 HSE external clock characteristics Symbol Parameter Conditions Min Typ Max External clock source frequency OSC_IN input pin high level voltage fuse ext VHSEH Unit MHz OSC_IN input pin low level V SE
31. Description ie from from Wait from Wait Vector No block P Active halt WFI WFE address mode 1 mode mode mode RESET Reset Yes Yes Yes Yes 0x00 8000 TRAP Software interrupt 0x00 8004 0 TLI External Top level Interrupt 0x00 8008 FLASH end of programing 1 FLASH write attempted to Yes Yes 0x00 800C protected page interrupt DMA1 channels 0 1 half 2 DMA1 0 1 transaction transaction Yes Yes 0x00 8010 complete interrupt DMA1 channels 2 3 half 3 DMA1 2 3 transaction transaction Yes Yes 0x00 8014 complete interrupt 4 me ETE ae Yes Yes Yes Yes 0x00 8018 tamper 1 tamper 2 tamper 3 5 PVD PVD interrupt Yes Yes Yes Yes 0x00 801C 6 EXTIB External interrupt port B Yes Yes Yes Yes 0x00 8020 7 EXTID External interrupt port D Yes Yes Yes Yes 0x00 8024 8 EXTIO External interrupt 0 Yes Yes Yes Yes 0x00 8028 9 EXTI1 External interrupt 1 Yes Yes Yes Yes 0x00 802C 10 EXTI2 External interrupt 2 Yes Yes Yes Yes 0x00 8030 11 EXTI3 External interrupt 3 Yes Yes Yes Yes 0x00 8034 12 EXTI4 External interrupt 4 Yes Yes Yes Yes 0x00 8038 13 EXTI5 External interrupt 5 Yes Yes Yes Yes 0x00 803C 14 EXTI6 External interrupt 6 Yes Yes Yes Yes 0x00 8040 15 EXTI7 External interrupt 7 Yes Yes Yes Yes Ox00 8044 16 Reserved Ox00 8048 CLK system clock 17 CLK switch CSS interrupt Yes Yes 0x00 804C ACD1 end of conversion 18 ADC1 analog watchdog Yes Yes Yes Yes 0x00 8050 overrun interrupt TIM2 update 19 TIM2 loverflow trigger break Ye
32. E voltage OSC IN input 2 6 capacitance Cin HSE pF OSC_IN input leakage Veo lt Vin lt V current SS IN ED mi ILEAK_HSE HA 1 Data guaranteed by Design not tested in production LSE external clock LSEBYP 1 in CLK ECKCR Subject to general operating conditions for Vpp and T Table 27 LSE external clock characteristics Symbol Parameter Min Typ Max fLSE_ext External clock source frequency 32 768 Unit kHz Vi seu OSC32 IN input pin high level voltage 0 7 x Vpp Vpp Vise OSC32_IN input pin low level voltage Vss 0 3 x Vpp Cin LSE OSC32 IN input capacitance 0 6 pF liEAK LSE OSC32 IN input leakage current 1 pA 1 Data guaranteed by Design not tested in production 2 Data based on characterization results not tested in production 60 93 DoclD023465 Rev 2 2 STM8L051F3 Electrical parameters HSE crystal ceramic resonator oscillator The HSE clock can be supplied with a 1 to 16 MHz crystal ceramic resonator oscillator All the information given in this paragraph is based on characterization results with specified typical external components In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time Refer to the crystal resonator manufacturer for more details frequency
33. FT pins PA7 and 5 2 V V i 2 IH Input high level voltage PEO with Vpp lt 2 V Input voltage on five volt TOXV tolerant FT pins PA7 and POX Yon 5 5 PEO with Vpp 2 2 V Input voltage on 3 6 V tolerant 3 6 TT pins i Input voltage on any other pin 0 70 x Vpp Vpp 0 3 Schmitt trigger voltage l Os 200 Vhys h ta 3 q mV ysteresis True open drain I Os 200 VssVinVpp 50 5 High sink I Os Vss lt VinsVpp 2005 likg Input leakage current 4 True open drain I Os nA VsssVinsVpp PAO with high sink LED driver 200 capability Weak pull up equivalent Rpu ye 3 Vin Vss 30 45 60 kQ resistor Cio I O pin capacitance 5 pF Vpp 3 0 V Ta 40 to 85 C unless otherwise specified Data based on characterization results not tested in production Hysteresis voltage between Schmitt trigger switching levels Based on characterization results not tested The max value may be exceeded if negative current is injected on adjacent pins Not tested in production oa ONS Rpy pull up equivalent resistor based on a resistive transistor corresponding Ipy current characteristics described in Figure 19 Ly DocID023465 Rev 2 67 93 Electrical parameters STM8L051F3 68 93 Figure 16 Typical Vj and Vu vs Vpp high sink I Os Vi and Vis V 3 1 8 2 1 2 6 3 1 3 6 Vbo V ai18220V2 Vi and Vu V Figure 1
34. Integral non linearity fapc 8 MHz 1 2 1 8 LSB fapc 4 MHz 1 2 1 7 fapc 16 MHz 2 2 3 0 TUE Total unadjusted error fapc 8 MHz 1 8 2 5 fapc 4 MHz 1 8 2 3 fanc 16 MHz 1 5 2 Offset Offset error fapc 8 MHz 1 1 5 fapc 4 MHz 0 7 1 2 T fapc 16 MHz Gain Gain error fapc 8 MHz 1 1 5 fapc 4 MHz Table 45 ADC1 accuracy with VppA 2 4 V to 3 6 V Symbol Parameter Typ Max Unit DNL Differential non linearity 1 2 LSB INL Integral non linearity 1 7 3 LSB TUE Total unadjusted error 2 4 LSB Offset Offset error 1 2 LSB Gain Gain error 1 5 3 LSB Table 46 ADC1 accuracy with VppA Vrer 1 8 V to 2 4 V Symbol Parameter Typ Max Unit DNL Differential non linearity 1 2 LSB INL Integral non linearity 2 3 LSB TUE Total unadjusted error 3 5 LSB Offset Offset error 2 3 LSB Gain Gain error 2 3 LSB 82 93 DoclD023465 Rev 2 2 STM8L051F3 Electrical parameters Figure 33 ADC1 accuracy characteristics MLSBipeaL Zoe or Yopa depending on package 4096 4096 EE Xx de 1 Example of an actual transfer curve 7 I 2 The ideal transfer curve 4094 ze 1 3 End point correlation line 4093 PE Pa Gi a 2 is mil rJ E N O fF a DN e 7 P EL gt M 1 tag L2 Ep 44 1 LSBineaL Er Total Unadjusted Error maximum deviation between the actual and the ideal transfer curves Eg Offset Error deviation between the first actual transiti
35. Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com Ly DocID023465 Rev 2 93 93
36. LANTED DEVICES OR SYSTEMS WITH PRODUCT FUNCTIONAL SAFETY REQUIREMENTS B AERONAUTIC APPLICATIONS C AUTOMOTIVE APPLICATIONS OR ENVIRONMENTS AND OR D AEROSPACE APPLICATIONS OR ENVIRONMENTS WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE THE PURCHASER SHALL USE PRODUCTS AT PURCHASER S SOLE RISK EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE UNLESS A PRODUCT IS EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR AUTOMOTIVE AUTOMOTIVE SAFETY OR MEDICAL INDUSTRY DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS PRODUCTS FORMALLY ESCC QML OR JAN QUALIFIED ARE DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2014 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy
37. M8L051F3 3 2 3 2 1 3 2 2 14 93 Central processing unit STM8 Advanced STM8 Core The 8 bit STM8 core is designed for code efficiency and performance with an Harvard architecture and a 3 stage pipeline It contains 6 internal registers which are directly addressable in each execution context 20 addressing modes including indexed indirect and relative addressing and 80 instructions Architecture and registers e Harvard architecture e 3 stage pipeline e 32 bit wide program memory bus single cycle fetching most instructions e Xand Y 16 bit index registers enabling indexed addressing modes with or without offset and read modify write type data manipulations e 8 bit accumulator e 24 bit program counter 16 Mbyte linear memory space e 16 bit stack pointer access to a 64 Kbyte level stack e 8 bit condition code register 7 condition flags for the result of the last instruction Addressing e 20 addressing modes e Indexed indirect addressing mode for lookup tables located anywhere in the address space e Stack pointer relative addressing mode for local variables and parameter passing Instruction set e 80 instructions with 2 byte average instruction size e Standard data movement and logic arithmetic functions e 8 bit by 8 bit multiplication e 16 bit by 8 bit and 16 bit by 16 bit division e Bit manipulation e Data transfer between stack and accumulator push pop with direct stack access e Data transf
38. MHZ gta neei ke naga an me KAL e at eee ee EE 84 DoclD023465 Rev 2 5 93 List of tables STM8L051F3 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 6 93 EMS data s 6o cc a Giga REENEN A TG NG reu se 86 EMI datas uc 87 ESD absolute maximum ratings eh 87 Electrical sensitivities 87 TSSOP20 20 lead thin shrink small package mechanical data 89 Thermal characteristics 90 Document revision history 92 2 DoclD023465 Rev 2 STM8L051F3 List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 2 Low density value line STM8LO5xxx device block diagram oooooocoocoooooo 12 Low density value line STM8LO5xxx clock tree diagram 17 STM8L051F3 20 pin TSSOP20 package pinout 0c eee 23 Memory MAD E 26 Pin loading conditions 45 Pin input Voltage m er 46 POR BOR thresholds 50 Typ IDD RUN vs VDD fCPU 16Mn rne 52 Typ IDD Wait vs VDD fCPU 16 MHZ1 e 54 Typ IDD LPR vs
39. N 2 channels 8 Kbyte 2 channels LI 16 bit Timer 3 Z Pogram memdsy Hi 8 bit Timer 4 OT 8 256 byte 5 Data EEPROM a bd IR TIM ko E S SCL SDA 5 PA 7 0 SPI1 MOSI SPI MISO 5 PB 7 0 SPI1_SCK SPI1 NSS ka 2 PC 7 0 i 5 PD 7 0 USART1 RX USART1 TX o 7 0 USART1_CK lt Vopa ssa ADC1_INx V DDREF BEER VSSREF ALARM CALIB TAMP1 2 3 VREFINT out MS30321V1 1 Legend 12 93 ADC Analog to digital converter BOR Brownout reset DMA Direct memory access IC Inter integrated circuit multimaster interface IWDG Independent watchdog POR PDR Power on reset power down reset RTC Real time clock SPI Serial peripheral interface SWIM Single wire interface module USART Universal synchronous asynchronous receiver transmitter WWDG Window watchdog 2 DoclD023465 Rev 2 STM8L051F3 Functional overview 3 1 2 Low power modes The low density value line STM8L05xxx devices support five low power modes to achieve the best compromise between low power consumption short startup time and available wakeup sources Wait mode The CPU clock is stopped but selected peripherals keep running An internal or external interrupt or a Reset can be used to exit the microcontroller from Wait mode WFE or WFI mode Low power run mode The CPU and the selected peripherals are running Execution is done from RAM with a low speed oscillator LSI or LSE Flash memory and data EEPROM are stopped and the volt
40. OMOARL DMA1 memory 0 address low register 0x00 channel 0 28 93 DoclD023465 Rev 2 Zar STM8L051F3 Memory and register map Table 7 General hardware register map continued Address Block Register label Register name Reset status 0x00 507D to 0x00 507E Reserved area 2 bytes 0x00 507F DMA1_C1CR DMA1 channel 1 configuration register 0x00 0x00 5080 DMA1_C1SPR DMA1 channel 1 status amp priority register 0x00 0x00 5081 DMA1 CINDTR DMA1 number of data to transfer register 0x00 channel 1 0x00 5082 DMA1 CIPARH DMA1 peripheral address high register 0x52 hz channel 1 0x00 5083 DMA1 CIPARL DMA1 peripheral address low register 0x00 channel 1 0x00 5084 Reserved area 1 byte 0x00 5085 DMA1 C1MOARH DMA1 memory 0 address high register 0x00 channel 1 0x00 5086 DMA1 C1MOARL DMA1 memory 0 address low register 0x00 channel 1 0x00 5087 0x00 5088 Reserved area 2 bytes 0x00 5089 DMA1_C2CR DMA1 channel 2 configuration register 0x00 0x00 508A DMA1_C2SPR DMA1 channel 2 status amp priority register 0x00 0x00 508B DMA1 DMA1_C2NDTR DMA1 number of data to transfer register 0x00 channel 2 0x00 508C DMA1 C2PARH DMA1 peripheral address high register 0x52 B channel 2 0x00 508D DMA1 C2PARL DMA1 peripheral address low register 0x00 channel 2 0x00 508E Reserved area 1 byte
41. R 0x00 480A BOR 3 0 Reserved BOR TH ON 0x00 0x00 480B Bootloader 0x00 option bytes pla OPTBL 15 0 0x00 480C OPTBL 15 0 0x00 2 42 93 DoclD023465 Rev 2 STM8L051F3 Option bytes Table 11 Option byte description Option byte No OPTO Option description ROP 7 0 Memory readout protection ROP OxAA Disable readout protection write access via SWIM protocol Refer to Readout protection section in the STM8L05x 15x and STM8L 16x reference manual RM0031 OPT1 UBC 7 0 Size of the user boot code area 0x00 UBC is not protected 0x01 Page O is write protected 0x02 Page 0 and 1 reserved for the UBC and write protected It covers only the interrupt vectors 0x03 Page O to 2 reserved for UBC and write protected Ox7F to OxFF All 128 pages reserved for UBC and write protected The protection of the memory area not protected by the UBC is enabled through the MASS keys Refer to User boot code section in the STM8L05x 15x and STM8L 16x reference manual RM0031 OPT2 Reserved OPT3 IWDG HW Independent watchdog 0 Independent watchdog activated by software 1 Independent watchdog activated by hardware IWDG HALT Independent window watchdog off on Halt Active halt 0 Independent watchdog continues running in Halt Active halt mode 1 Independent watchdog stopped in Halt Active halt mode WWDG HW Window watchdog 0 Window watchdog activated by software 1 Window watchdog ac
42. RTC TR1 RTC Time register 1 0x00 0x00 5141 RTC RTC TR2 RTC Time register 2 0x00 0x00 5142 RTC TR3 RTC Time register 3 0x00 KYI DoclD023465 Rev 2 31 93 Memory and register map STM8L051F3 Table 7 General hardware register map continued Address Block Register label Register name pada 0x00 5143 Reserved area 1 byte 0x00 5144 RTC DR1 RTC Date register 1 0x01 0x00 5145 RTC DR2 RTC Date register 2 0x21 0x00 5146 RTC DR3 RTC Date register 3 0x00 0x00 5147 Reserved area 1 byte 0x00 5148 RTC CR1 RTC Control register 1 0x001 0x00 5149 RTC_CR2 RTC Control register 2 0x001 0x00 514A RTC_CR3 RTC Control register 3 0x00 1 0x00 514B Reserved area 1 byte 0x00 514C RTC ISR1 RTC Initialization and status register 1 0x01 0x00 514D RTC ISR2 RTC Initialization and Status register 2 0x00 Ge Ge Reserved area 2 bytes 0x00 5150 RTC SPRERH RTC Synchronous prescaler register high 0x00 1 0x00 5151 RTC SPRERL RTC Synchronous prescaler register low OxFF 0x00 5152 RTC APRER RTC Asynchronous prescaler register 0x7F 1 0x00 5153 Reserved area 1 byte 0x00 5154 RTC RTC_WUTRH RTC Wakeup timer register high Vidal 0x00 5155 RTC WUTRL RTC Wakeup timer register low OxFF D 0x00 5156 Reserved area 1 byte 0x00 5157 RTC SSRL RTC Subsecond register low 0x00 0x00 5158 RTC
43. T NRST input not filtered pulse 9 300 1 Data based on characterization results not tested in production 2 200 mV min 3 Data guaranteed by design not tested in production Figure 26 Typical NRST pull up resistance Rpy vs Vpp 60 55 50 45 40 Pull up resistance ko 35 30 1 8 2 22 24 26 28 3 32 34 36 Vop V ai18224V2 2 72 93 DoclD023465 Rev 2 STM8L051F3 Electrical parameters Figure 27 Typical NRST pull up current lj vs Vpp 120 100 80 60 Pull Up current JA 40 20 0 1 8 1 95 21 225 24 255 27 2 85 3 3 15 3 3 345 3 6 Voo V ai18225V2 The reset network shown in Figure 28 protects the device against parasitic resets The user must ensure that the level on the NRST pin can go below the Vj wrst max level specified in Table 39 Otherwise the reset is not taken into account internally For power consumption sensitive applications the external reset capacitor value can be reduced to limit the charge discharge current If the NRST signal is used to reset the external circuitry attention must be paid to the charge discharge time of the external capacitor to fulfill the external devices reset timing conditions The minimum recommended capacity is 10 nF Figure 28 Recommended NRST pin configuration EXTERNAL NRST Filt INTERNAL RESET RESET e LJ ilte
44. Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Ly Low density value line STM8LO5xxx low power device features and peripheral counts 10 Timer feature comparison llis rh 19 Legend abbreviation for Table 4 liliis n 23 Low density value line STM8LO5xxx pin description 24 Flash and RAM boundary addresses 4 esse 27 I O port hardware register map ren 27 General hardware register map ree 28 CPU SWIM debug module interrupt controller registers lille less 38 Interrupt mapping clum a NEE ENEE ee ay Ro REOR A NEE d EUR ees 40 Option byte addresses ete 42 Option byte description eae 43 Voltage characteristics nn 46 Current characteristics 0 2 00 00 ccc tae 47 Thermal characteristics 47 General operating conditions 00 ccc tae 48 Embedded reset and power control block characteristics 49 Total current consumption in Run mode 51 Total current consumption in Wait mode e 53 Total current consumption and timing in Low power run mode at VDD 1 8 V to SON anna bu MIL EC E M RARE DINEM mgawa 55 Total current consumption in Low power wait mode at VDD 1 8 V to 3 6V 56 Total current consumption and timin
45. X C5 master slave select USART transmit Timer 2 channel 1 24 93 DoclD023465 Rev 2 Ly STM8L051F3 Pin description Table 4 Low density value line STM8L05xxx pin description continued a Input Output So o D o amp 5 HE EM Pin name Ei 2 o 2313 ou Default alternate function Se HO 5 aa 2 ola s o Sas S 20 5G o 2 9 z H c w gt I PC6 OSC32 OUT SPI SCkJ Port LSE oscillator output SPI clock 2 ES T 1 0 X X XHS X X USART receive USART RX TIM2 CH2 C6 Timer 2 channel 2 PDO TIM3 CH2 ADC1 TRIG Port Timer 3 channel 2 3 YADC1 IN22 baa A BS LA DO ADC1 Trigger ADC1 IN22 Digital supply voltage 8 Ion Vopa Vngr S ADC1 positive voltage reference 7 Man V IN Ground voltage ADC1 negative voltage no EHEH ooh reference Analog ground voltage 5 2 USART1 synchronous clock 3 EE e HA 1 0 XXX Ha XX GE SWIM input and output Beep output Infrared Timer output 1 Atpower up the PA1 NRST pin is a reset input pin with pull up To be used as a general purpose pin PA1 it can be configured only as output open drain or push pull not as a general purpose input Refer to Section Configuring NRST PA1 pin as general purpose output in the STM8L15xxx and STM8L16xxx reference manual RM0031 2 Alternate function remapping option if the same alternate function is shown twice it indicates an exclu
46. able data is based on characterization results unless otherwise specified Table 18 Total current consumption in Wait mode Max Symbol Parameter Conditions Typ Unit 55 C 85 C fcpu 125 kHz 0 33 0 39 0 41 feru 1 MHz 0 35 0 41 0 44 HSI fcpu 4 MHz 0 42 0 51 0 52 f 8 MH CPU not CPU Zz 0 52 0 57 0 58 clocked fopy 16 MHz 0 68 0 76 0 79 all peripherals OFF fcpu 125 kHz 0 032 0 056 0 068 Supply code executed Ipp wait currentin rom RAM HSE external fcpu 1 MHz 0 078 0 121 0 144 mA Wait mode with Flash in clock fopy 4 MHz 0 218 0 26 0 30 Ippa mode t o fi sg 9 E Vpop from fcpu 8 MHz 0 40 0 52 0 57 1 8 V to 3 6 V fopy 16 MHz 0 760 1 01 1 05 LSI feru fisi 0 035 0 044 0 046 LSE external clock fcpu fLse 0 032 0 036 0 038 32 768 kHz fopy 125 kHz 0 38 0 48 0 49 Luss MHz 0 41 0 49 0 51 HSI fcpu 4 MHz 0 50 0 57 0 58 fcpy 8MHz 0 60 0 66 0 68 CPU not fopy 16 MHz 0 79 0 84 0 86 clocked Supply all peripherals fcpu 125 kHz 0 06 0 08 0 09 currentin OFF 3 HSE f 1 MHz 0 10 0 17 0 18 open Wall code executed external clock Si s mode IE fopy HSE fcpu 4 MHz 0 24 0 36 0 39 pp from z 1 8 V to 3 6 V feru 8 MHz 0 50 0 58 0 61 fcpy 16 MHz 1 00 1 08 1 14 LSI feru fis 0 055 0 058 0 065 LSE extern
47. age regulator is configured in ultra low power mode The microcontroller enters Low power run mode by software and can exit from this mode by software or by a reset All interrupts must be masked They cannot be used to exit the microcontroller from this mode Low power wait mode This mode is entered when executing a Wait for event in Low power run mode It is similar to Low power run mode except that the CPU clock is stopped The wakeup from this mode is triggered by a Reset or by an internal or external event peripheral event generated by the timers serial interfaces DMA controller DMA1 and I O ports When the wakeup is triggered by an event the system goes back to Low power run mode All interrupts must be masked They cannot be used to exit the microcontroller from this mode Active halt mode CPU and peripheral clocks are stopped except RTC The wakeup can be triggered by RTC interrupts external interrupts or reset Halt mode CPU and peripheral clocks are stopped the device remains powered on The RAM content is preserved The wakeup is triggered by an external interrupt or reset A few peripherals have also a wakeup from Halt capability Switching off the internal reference voltage reduces power consumption Through software configuration itis also possible to wake up the device without waiting for the internal reference voltage wakeup time to have a fast wakeup time of 5 us DoclD023465 Rev 2 13 93 Functional overview ST
48. al clock fcpu fLse 0 051 0 056 0 060 32 768 kHz consumption lbp Hse Must be added Refer to Table 28 DoclD023465 Rev 2 All peripherals OFF Vpp from 1 8 V to 3 6 V HSI internal RC osc fepy fsyscLk Flash is configured in Ippo mode in Wait mode by setting the EPM or WAITM bit in the Flash CR1 register Oscillator bypassed HSEBYP 1 in CLK ECKCR When configured for external crystal the HSE 53 93 Electrical parameters STM8L051F3 54 93 4 Oscillator bypassed LSEBYP 1 in CLK ECKCR When configured for extenal crystal the LSE onsumption lbp Hse must be added Refer to Table 29 Figure 9 Typ Ipp wait VS Von fcpu 16 MHz 1 1000 950 IDD WAIT HSI UA 2 1 2 6 Voo V 3 1 3 6 ai18214V2 1 Typical current consumption measured with code executed from Flash memory DoclD023465 Rev 2 d STM8L051F3 Electrical parameters In the following table data is based on characterization results unless otherwise specified Table 19 Total current consumption and timing in Low power run mode at Vpp 1 8 V to 3 6 V Symbol Parameter Conditions Typ Max Unit Ta 40 C to 25 C 5 1 5 4 all peripherals OFF T 55 C 5 7 6 LSI RC osc Ta 85 C 6 8 7 5
49. anged by the application program as soon as the code execution starts e Clock security system CSS This feature can be enabled by software If a HSE clock failure occurs it is automatically switched to HSI e Configurable main clock output CCO This outputs an external clock for use by the application 2 DoclD023465 Rev 2 STM8L051F3 Functional overview 2 Figure 2 Low density value line STM8L05xxx clock tree diagram OSC32 OUT SWIM 3 0 SYSCLK to core and OSC OUT r3 SYSCLK memory prescaler 1 2 4 8 16 32 64 Peripheral Clock enable 13 bits PCLK to peripherals to BEEP BEEPCLK LKBEEPSEL 1 0 to IWDGCLK IWDG to RTC RTC LSE OSC prescaler 32 768 kHz 1 2 4 8 16 32 64 RTCCLK OSC32 IN Configurable clock output cco L3 prescaler LSE 1 2 4 8 16 32 64 PUER MS18281V1 The HSE clock source can be either an external crystal ceramic resonator or an external source HSE bypass Refer to Section HSE clock in the STM8L 15x and STM8L16x reference manual RM0031 The LSE clock source can be either an external crystal ceramic resonator or a external source LSE bypass Refer to Section LSE clock in the STM8L15x and STM8L 16x reference manual RM0031 DoclD023465 Rev 2 17 93 Functional overview STM8L051F3 3 5 3 6 3 7 3 8 Note 18 93 Low power real time clock The real time clock RTC is an i
50. arges a positive then a negative pulse separated by 1 second are applied to the pins of each sample according to each pin combination The sample size depends on the number of supply pins in the device 3 parts n 1 supply pin Two models can be simulated human body model and charge device model This test conforms to the JESD22 A114A A115A standard Table 50 ESD absolute maximum ratings 2 Maximum Symbol Ratings Conditions value 1 Unit Electrostatic discharge voltage V ESD HBM human body model 2000 Ta 25 C V V Electrostatic discharge voltage 500 ESD CDM charge device model 1 Data based on characterization results not tested in production Static latch up e LU 3 complementary static tests are required on 6 parts to assess the latch up performance A supply overvoltage applied to each power supply pin and a current injection applied to each input output and configurable I O pin are performed on each sample This test conforms to the EIA JESD 78 IC latch up standard For more details refer to the application note AN1181 Table 51 Electrical sensitivities Symbol Parameter Class LU Static latch up class ll DoclD023465 Rev 2 87 93 Package characteristics STM8L051F3 9 9 1 88 93 Package characteristics ECOPACK In order to meet environmental requirements ST offers these devices in different grades of ECOPACKO packages dependin
51. ata is guaranteed by design not tested in production Table 43 ADC1 characteristics Symbol Parameter Conditions Min Typ Max Unit Vopa fAnalog supply voltage 1 8 3 6 V Veer Reference supply 24 V Nppas 3 6 V 24 VDDA V x E E voltage 1 8 V Vppas 2 4 V Vp V Ver Lower reference voltage Vssa V Current on the VDDA l VDDA input pin 1000 1450 HA 700 NU He Current on the VREF peak lvREF 400 input pin 450 A average v Conversion voltage V 2 V AIN range 0 REF TA Temperature range 40 85 C j on PFO fast channel RAN External resistance on 50 3 ko VAIN on all other channels on PFO fast channel Dos Internal sample and hold 16 pF capacitor on all other channels Pe DEA ON 0 320 16 MHz Bee ADC sampling clock without zooming frequency ED Tw 0 320 8 MHz with zooming Vain on PFO fast 406 MHz channel fcoNv 12 bit conversion rate Vain on all other 4 5 channels 760 kitz External trigger TRIG frequency tconv l fApc ti AT External trigger latency 3 5 l fsyscLk 80 93 DoclD023465 Rev 2 Ly STM8L051F3 Electrical parameters Table 43 ADC1 characteristics continued Symbol Parameter Conditions Min Typ Max Unit Vain on PFO fast channel 0 4309 us Vopa lt 24 V Vain on PFO fast o channel 0 2206 us ts Sampling time 24V Nppas 3 6 V Vain on slow channels 4 5 Vppa lt 2 4 V 0 86 m Vain on slow channels 4 5 24V spp E36 V 94 ps 12 ts 1 fapc teonv 12 bit conversion time 16
52. ating UO unless otherwise specified 2 Oscillator bypassed LSEBYP 1 in CLK ECKCR When configured for extenal crystal the LSE consumption Ipp Lse must be added Refer to Table 29 3 Wakeup time until start of interrupt vector fetch The first word of interrupt routine is fetched 4 CPU cycles after twy 4 ULP 0 or ULP 1 and FWU 1 in the PWR CSR2 register Table 22 Typical current consumption in Active halt mode RTC clocked by LSE external crystal Symbol Parameter Condition Typ Unit LSE 1 15 Vpp 1 8 V LsE 320 1 05 Supply current in Active halt LSE 1 30 ona SE Vpp 3V 3 HA LSE 32 1 20 y RT LSE 1 45 DD 9 LSE 32 3 1 35 1 No floating I O unless otherwise specified 2 Based on measurements on bench with 32 768 kHz external crystal oscillator 3 RTC clock is LSE divided by 32 Ly DoclD023465 Rev 2 57 93 Electrical parameters STM8L051F3 In the following table data is based on characterization results unless otherwise specified Table 23 Total current consumption and timing in Halt mode at Vpp 7 1 8 to 3 6 V Symbol Parameter Condition Typ Max Unit TA 40 C to 25 C 350 2 Supply current in Halt mode A Lot Ipp Halt Ultra low power ULP bit 21 in Ta 55 C 580 2000 nA the PWR CSR2 register Ta 85 C 1160 28002 Supply current during wakeup Ipp wUHalt time from Halt mode using 2 4 mA HSI 3y4 Wakeup time from Halt to Run
53. bel Register name ege 0x00 521D I2C1 TRISER I2C1 TRISE register 0x02 0x00 521E SS I2C1 PECH I2C1 packet error checking register 0x00 0x00 521F to Reserved area 17 bytes 0x00 522F 0x00 5230 USART1 SR USART1 status register OxCO 0x00 5231 USART1 DR USART1 data register OxXX 0x00 5232 USART1 BRR1 USART1 baud rate register 1 0x00 0x00 5233 USART1 BRR2 USART1 baud rate register 2 0x00 0x00 5234 USART1 CR1 USART1 control register 1 0x00 0x00 5235 USART1 USART1 CR2 USART1 control register 2 0x00 0x00 5236 USART1_CR3 USART1 control register 3 0x00 0x00 5237 USART1_CR4 USART1 control register 4 0x00 0x00 5238 USART1_CR5 USART1 control register 5 0x00 0x00 5239 USART1_GTR USART guard time register 0x00 0x00 523A USART1_PSCR USART 1 prescaler register 0x00 0x00 523B to Reserved area 21 bytes 0x00 524F 0x00 5250 TIM2 CR1 TIM2 control register 1 0x00 0x00 5251 TIM2 CR2 TIM2 control register 2 0x00 0x00 5252 TIM2 SMCR TIM2 Slave mode control register 0x00 0x00 5253 TIM2 ETR TIM2 external trigger register 0x00 0x00 5254 TIM2 DER TIM2 DMA1 request enable register 0x00 0x00 5255 TIM2 IER TIM2 interrupt enable register 0x00 0x00 5256 TIM2 SR1 TIM2 status register 1 0x00 0x00 5257 TIM2 SR2 TIM2 status register 2 0x00 0x00 5258 S TIM2 EGR TIM2 event generation register Ox00 0x00 5259 TIM2 CCMR1 TIM2 capture compare mode register 1 0x00 0x00 525A TIM2 CCMR2 TIM2 capture compare mode register 2 0x00 0x00 525B TIM2 CCER1 TIM2 capture compare enable register 1
54. care for the design architecture has been taken to optimize the mA DMIPS and mA MHz ratios This allows the ultra low power performance to range from 5 up to 33 3 DMIPs Shared peripherals STM8L05xx STM8L15xx and STM32L 15xx share identical peripherals which ensure a very easy migration from one family to another e Analog peripheral ADC1 e Digital peripherals RTC and some communication interfaces Common system strategy To offer flexibility and optimize performance the STM8L and STM32L devices use a common architecture e Same power supply range from 1 8 to 3 6 V e Architecture optimized to reach ultra low consumption both in low power modes and Run mode e Fast startup strategy from low power modes e Flexible system clock e Ultra safe reset same reset strategy for both STM8L and STM32L including power on reset power down reset brownout reset and programmable voltage detector Features ST ultra low power continuum also lies in feature compatibility e More than 10 packages with pin count from 20 to 100 pins and size down to 3 x 3 mm e Memory density ranging from 4 to 128 Kbytes DoclD023465 Rev 2 11 93 Functional overview STM8L051F3 3 Functional overview Figure 1 Low density value line STM8L05xxx device block diagram OSC IN OSC OUT Power Vop 1 E y i Clock v to 3 OSC32 IN controller VOLT REG SS OSC32 OUT and CSS Clocks 7 to core and peripherals NRST SWIM Debug module SWIM PVD_I
55. cified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature supply voltage and frequencies by tests in production on 100 of the devices with an ambient temperature at Taz 25 C and Ta Ta max given by the selected temperature range Data based on characterization results design simulation and or technology characteristics is indicated in the table footnotes and are not tested in production Based on characterization the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation mean 32 Typical values Unless otherwise specified typical data is based on Ta 25 C Vpp 3 V It is given only as design guidelines and is not tested Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range where 95 of the devices have an error less than or equal to the value indicated mean 22 Typical curves Unless otherwise specified all typical curves are given only as design guidelines and are not tested Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 5 Figure 5 Pin loading conditions CT STM8L PIN 50pF DoclD023465 Rev 2 45 93 Electrical parameters STM8L051F3 8 1 5 Pin input voltage The input voltage measurement on a pin of the device i
56. cteristics Total current consumption The MCU is placed under the following conditions e A UO pins in input mode with a static value at Vpp or Vss no load e All peripherals are disabled except if explicitly mentioned In the following table data is based on characterization results unless otherwise specified Subject to general operating conditions for Vpp and Ta 2 DoclD023465 Rev 2 STM8L051F3 Electrical parameters Table 17 Total current consumption in Run mode Para 4 Max Symbol neter Conditions Typ Unit 55 C 85 C fcpu 125 kHz 0 39 0 47 0 49 feru 1 MHz 0 48 0 56 0 58 HSIRC Na lfcpu 4 MHz 0 75 0 84 0 86 16 MHz fcpu 8 MHz 1 10 1 20 1 25 Aj Luz 16 MHz 1 85 1 93 2 126 peripherals feru 125 kHz 0 05 0 06 0 09 Supply OFF eru current code fcpu 1 MHz 0 18 0 19 0 20 IDD RUN lin nun lexecuted HSE external mA mode from RAM clock fcpu 4 MHz 0 55 0 62 0 64 f f 4 Vpp from fcpu fuse fopy 8 MHz 099 120 121 1 8 V to 3 6 V Lous 16 MHz 1 90 222 2 236 LSI RC osc f f typ 38 kHz CPU fs 0 040 0 045 0 046 LSE external clock fopy fise 0 035 0 040 0 048 32 768 kHz fcpu 125 kHz 0 43 0 55 0 56 fcpu 1 MHz 0 60 0 77 0 80 HSI RC 6 fopy 4 MHz 1 11 1 34 1 37 OSC fcpu 8 MHz 1 90 2 20 223 peripherals fopy 125 kHz 0 30 0
57. cycles program memory 1001 cycles Naw 9 Ta 40 to 85 C 1 Erase write cycles data memory S tea kcycles 1 Data based on characterization results not tested in production Conforming to JEDEC JESD22a117 The physical granularity of the memory is 4 bytes so cycling is performed on 4 bytes even when a write erase operation addresses a single byte 4 Data based on characterization performed on the whole data memory 8 3 6 UO current injection characteristics As a general rule current injection to the I O pins due to external voltage below Vss or above Vpp for standard pins should be avoided during normal product operation However in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens susceptibility tests are performed on a sample basis during device characterization 2 DoclD023465 Rev 2 65 93 Electrical parameters STM8L051F3 8 3 7 66 93 Functional susceptibilty to I O current injection While a simple application is executed on the device the device is stressed by injecting current into the l O pins programmed in floating input mode While current is injected into the I O pin one at a time the device is checked for functional failures The failure is indicated by an out of range parameter ADC error out of spec current injection on adjacent pins or other functional failure for example reset oscillator f
58. d application software into the device memories including RAM program and data memory using standard serial interfaces It is a complementary solution to programming via the SWIM debugging interface 2 DoclD023465 Rev 2 STM8L051F3 Pin description 4 2 Pin description Figure 3 STM8L051F3 20 pin TSSOP20 package pinout PC5 g1 20h PC4 PC6 q2 195 PC1 PAO g3 18H PCO NRST PA1 g4 175 PB7 PA2 d5 165 PB6 PA3 do 155 PB5 Vss VSSA VREF 47 14h PB4 VpD VDDA VREF de 13h PB3 PDO de 12b PB2 PBO 10 11 PB1 MS18280V1 Table 3 Legend abbreviation for Table 4 Type l input O output S power supply Output HS high sink source 20 mA Level Input FT five volt tolerant Port and control _ nput float floating wpu weak pull up configuration Output T true open drain OD open drain PP push pull Reset state Bold X pin state after reset release Unless otherwise specified the pin state is the same during the reset phase i e under reset and after internal reset release i e at reset state DoclD023465 Rev 2 23 93 Pin description STM8L051F3 Table 4 Low density value line STM8L05xxx pin description pa Input Output So o 5 0 o wl 9 o o o 2 5 Pin name Ei 2 o S 3 5 Defa
59. d line sink 80 Output current sunk by IR TIM pin with high sink LED driver 80 capability lio Output current sunk by any other I O and control pin 25 Output current sourced by any I Os and control pin 25 Injected current on true open drain pins PCO and PC1 5 0 Injected current on five volt tolerant FT pins PA7 and PEO Y 5 0 mA INPN ooN Injected current on 3 6 V tolerant TT pins 1 5 0 Injected current on any other pin 2 5 5 EliNJ PIN Total injected current sum of all UO and control pins 3 25 1 Positive injection is not possible on these I Os A negative injection is induced by Vin lt Vgs Iing pin Must never be exceeded Refer to Table 12 for maximum allowed input voltage values 2 A positive injection is induced by V y gt Vpp while a negative injection is induced by Viy lt Vgs li piu Must never be exceeded Refer to Table 12 for maximum allowed input voltage values 3 When several inputs are submitted to a current injection the maximum Z1 ny pin is the absolute sum of the positive and negative injected currents instantaneous values Table 14 Thermal characteristics Symbol Ratings Value Unit TsrG Storage temperature range 65 to 150 pa Ty Maximum junction temperature 150 DoclD023465 Rev 2 47 93 Electrical parameters STM8L051F3 8 3 Operating conditions Subject to general operating conditions for Vpp and T 8 3 1 Genera
60. en TIM2 overflow interrupt and TIM4 overflow interrupts The device is woken up from Halt or Active halt mode only when the address received matches the interface address 41 93 Option bytes STM8L051F3 7 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device They are stored in a dedicated memory block All option bytes can be modified in ICP mode with SWIM by accessing the EEPROM address See Table 10 for details on option byte addresses The option bytes can also be modified on the fly by the application in IAP mode except for the ROP and UBC values which can only be taken into account when they are modified in ICP mode with the SWIM Refer to the STM8L05x 15x Flash programming manual PM0054 and STM8 SWIM and Debug Manual UM0470 for information on SWIM programming procedures Table 10 Option byte addresses Option Option bits Factory Addr Option name byte default No 7 6 5 4 3 2 1 0 setting Read out 0x00 4800 protection OPTO ROP 7 0 OxAA ROP 0x00 4802 UBC User opty UBC 7 0 0x00 Boot code size 0x00 4807 Reserved 0x00 Independent OPT3 WWDG WWDG IWDG IWDG 0x00 4808 watchdog 3 0 Reserved HALT HW HALT Hw 0x00 option Number of stabilization 0x00 4809 clock cycles for OPT4 Reserved LSECNT 1 0 HSECNT 1 0 Ox00 HSE and LSE oscillators Brownout reset OPT5 BO
61. er 0x00 0x00 5289 TIM3 CCMR1 TIM3 Capture Compare mode register 1 0x00 0x00 528A TIM3 CCMR2 TIM3 Capture Compare mode register 2 0x00 0x00 528B TIM3 TIM3 CCER1 TIM3 Capture Compare enable register 1 0x00 0x00 528C TIM3 CNTRH TIM3 counter high 0x00 0x00 528D TIM3_CNTRL TIM3 counter low 0x00 0x00 528E TIM3_PSCR TIM3 prescaler register 0x00 0x00 528F TIM3_ARRH TIM3 Auto reload register high OxFF 0x00 5290 TIM3 ARRL TIM3 Auto reload register low OxFF 0x00 5291 TIM3 CCR1H TIM3 Capture Compare register 1 high 0x00 0x00 5292 TIM3 CCR1L TIM3 Capture Compare register 1 low 0x00 0x00 5293 TIM3 CCR2H TIM3 Capture Compare register 2 high 0x00 0x00 5294 TIM3 CCR2L TIM3 Capture Compare register 2 low 0x00 0x00 5295 TIM3 BKR TIM3 break register 0x00 0x00 5296 TIM3 OISR TIMS output idle state register 0x00 E Reserved area 72 bytes er DoclD023465 Rev 2 35 93 Memory and register map STM8L051F3 Table 7 General hardware register map continued Address Block Register label Register name ege 0x00 52E0 TIM4 CR1 TIM4 control register 1 0x00 0x00 52E1 TIM4 CR2 TIM4 control register 2 0x00 0x00 52E2 TIM4 SMCR TIM4 Slave mode control register 0x00 0x00 52E3 TIM4 DER TIM4 DMA1 request enable register 0x00 0x00 52bE4 TIM4 IER TIM4 Interrupt enable register 0x00 0x00 52bE5
62. er adjustable to fixed power of 2 ratios 1 128 e 2 individually configurable capture compare channels e PWM mode e Interrupt capability on various events capture compare overflow break trigger e Synchronization with other timers or external signals external clock reset trigger and enable 3 10 2 8 bit basic timer TIM4 The 8 bit timer consists of an 8 bit up auto reload counter driven by a programmable prescaler It can be used for timebase generation with interrupt generation on timer overflow 3 11 Watchdog timers 2 The watchdog system is based on two independent timers providing maximum security to the applications DoclD023465 Rev 2 19 93 Functional overview STM8L051F3 3 11 1 3 11 2 3 12 3 13 3 13 1 Note 3 13 2 Note 20 93 Window watchdog timer The window watchdog WWDG is used to detect the occurrence of a software fault usually generated by external interferences or by unexpected logical conditions which cause the application program to abandon its normal sequence Independent watchdog timer The independent watchdog peripheral IWDG can be used to resolve processor malfunctions due to hardware or software failures It is clocked by the internal LSI RC clock source and thus stays active even in case of a CPU clock failure Beeper The beeper function outputs a signal on the BEEP pin for sound generation The signal is in the range of 1 2 or 4 kHz Communication inter
63. er using the X and Y registers or direct memory to memory transfers Interrupt controller The low density value line STM8L05xxx features a nested vectored interrupt controller e Nested interrupts with 3 software priority levels e 32 interrupt vectors with hardware priority e Up to 17 external interrupt sources on 11 vectors e Trap and reset interrupts 2 DoclD023465 Rev 2 STM8L051F3 Functional overview 3 3 3 3 1 3 3 2 3 3 3 2 Reset and supply management Power supply scheme The device requires a 1 8 V to 3 6 V operating supply voltage Vpp The external power supply pins must be connected as follows e Vss1 Vpp1 1 8 to 3 6 V external power supply for I Os and for the internal regulator Provided externally through Vpp4 pins the corresponding ground pin is Vas e Vssap Vppa 1 8 to 3 6 V external power supplies for analog peripherals Vppa and Vssa must be connected to Vpp4 and Vss4 respectively e Vss2 Vpp2 1 8 to 3 6 V external power supplies for I Os Vpp2 and Vas must be connected to Vpp4 and Vgg respectively e VreF Vrer for ADC1 external reference voltage for ADC1 Must be provided externally through Vggr and Vggr pin Power supply supervisor The device has an integrated ZEROPOWER power on reset POR power down reset PDR coupled with a brownout reset BOR circuitry When the microcontroller operates between 1 8 and 3 6 V BOR is always active and ensures proper op
64. eration starting from 1 8 V After the 1 8 V BOR threshold is reached the option byte loading process starts either to confirm or modify default thresholds or to disable BOR permanently Five BOR thresholds are available through option bytes starting from 1 8 V to 3 V To reduce the power consumption in Halt mode it is possible to automatically switch off the internal reference voltage and consequently the BOR in Halt mode The device remains in reset state when Vpp is below a specified threshold Vpor ppr or Vgog without the need for any external reset circuit The device features an embedded programmable voltage detector PVD that monitors the Vpp Vppa power supply and compares it to the Vpyp threshold This PVD offers 7 different levels between 1 85 V and 3 05 V chosen by software with a step around 200 mV An interrupt can be generated when Vpp Vppa drops below the Vpyp threshold and or when Vpp VppaA is higher than the Vpyp threshold The interrupt service routine can then generate a warning message and or put the MCU into a safe state The PVD is enabled by software Voltage regulator The low density value line STM8L05xxx embeds an internal voltage regulator for generating the 1 8 V power supply for the core and peripherals This regulator has two different modes e Main voltage regulator mode MVR for Run Wait for interrupt WEI and Wait for event WFE modes e Low power voltage regulator mode LPVR for Halt Active halt
65. faces SPI The serial peripheral interfaces SPI1 provide half full duplex synchronous serial communication with external devices e Maximum speed 8 Mbit s fsysci K 2 both for master and slave e Full duplex synchronous transfers e Simplex synchronous transfers on 2 lines with a possible bidirectional data line e Master or slave operation selectable by hardware or software e Hardware CRC calculation e Slave master selection input pin SPI1 can be served by the DMA1 Controller PC The 12C bus interface I2C1 provides multi master capability and controls all PC bus specific sequencing protocol arbitration and timing e Master slave and multi master capability e Standard mode up to 100 kHz and fast speed modes up to 400 kHz e T bit and 10 bit addressing modes e SMBus 2 0 and PMBus support e Hardware CRC calculation 12C1 can be served by the DMA1 Controller 2 DoclD023465 Rev 2 STM8L051F3 Functional overview 3 13 3 Note 3 14 3 15 2 USART The USART interface USART1 allows full duplex asynchronous communications with external devices requiring an industry standard NRZ asynchronous serial data format It offers a very wide range of baud rates e 1 Mbit s full duplex SCI e SPI1 emulation e High precision baud rate generator e Smartcard emulation e IrDA SIR encoder decoder e Single wire half duplex mode USART1 can be served by the DMA1 Controller Infrared IR interface
66. g in Active halt mode at VDD 1 8 V to 3 6 V 57 Typical current consumption in Active halt mode RTC clocked by LSE external crystal 57 Total current consumption and timing in Halt mode at VDD 1 8 to 3 6 V 58 Peripheral current consumption nn 59 Current consumption under external reset llle eee eee 59 HSE external clock characteristics lille 60 LSE external clock characteristics ern 60 HSE oscillator characteristics liiis 61 LSE oscillator characteristics 0 ccc eh 62 HSI oscillator characteristics lille 63 LSI oscillator characteristics ren 64 RAM and hardware registers rn 65 Flash program and data EEPROM memory sees 65 I O current injection susceptibility llli RR 66 I O static characteristics liliis rh 67 Output driving current high sink ports eh 70 Output driving current true open drain ports 0 0 cece ee 70 Output driving current PAO with high sink LED driver capability 70 NRST pin characteristics 72 SPI1 characteristics Lomas LEE ere REY ara ve aed crue x 74 12C characteristics uuene rn 77 Reference voltage characteristics 79 ADC1 characteristics tees 80 ADC1 accuracy with VDDA 32Vio2bV ee 82 ADC1 accuracy with VDDA 2 2 4 V t6 3 6V 2 82 ADC1 accuracy with VDDA VREF 2 1 8 V to2 4V lees ees 82 Rain max fortapo 10
67. g on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark 2 DoclD023465 Rev 2 STM8L051F3 Package characteristics 9 2 Package mechanical data 9 2 1 20 lead thin shrink small package TSSOP20 Figure 38 TSSOP20 20 lead thin shrink small package outline Figure 39 TSSOP20 recommended footprint AARRARARAR Q aaa CP Al r4 LJ gt r zl e lt b gt e YA ME anos 1 Drawing is not to scale 2 Dimensions are in millimeters Table 52 TSSOP20 20 lead thin shrink small package mechanical data Dim mm inches Typ Min Max Typ Min Max A 1 200 0 0472 A1 z 0 050 0 150 0 0020 0 0059 A2 1 0 800 0 050 0 0394 0 0315 0 0413 b 0 190 0 300 0 0075 0 0118 c 0 090 0 200 0 0035 0 0079 D2 6 500 6 400 6 600 0 2559 0 2520 0 2598 E 6 400 6 200 6 600 0 252 0 2441 0 2598 E10 4 400 4 300 4 500 0 1732 0 1693 0 1772 e 0 650 0 0256 L 0 600 0 450 0 750 0 0236 0 0177 0 0295 L1 1 000 0 0394 k 0 0 8 0 0 0 8 0 aaa 0 1 0 0
68. ive is applied on all pins of the device until a functional disturbance occurs This test conforms with the IEC 61000 standard e FTB A burst of fast transient voltage positive and negative is applied to Vpp and Vss through a 100 pF capacitor until a functional disturbance occurs This test conforms with the IEC 61000 standard A device reset allows normal operations to be resumed The test results are given in the table below based on the EMS levels and classes defined in application note AN1709 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software It should be noted that good EMC performance is highly dependent on the user application and the software in particular Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application Prequalification trials Most of the common failures unexpected reset and program counter corruption can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second To complete these trials ESD stress can be applied directly on the device over the range of specification values When unexpected behavior is detected the software can be hardened to prevent unrecoverable errors occurring see application note AN1015 Table 48 EMS da
69. l operating conditions Table 15 General operating conditions Symbol Parameter Conditions Min Max Unit System clock fsvscuk Has 1 8 V lt Vpp lt 3 6 V 0 16 MHz Standard operatin Von voltage panang 1 8 3 6 V Analog operating Must be at the same Von voltage potential as Vpp 18 36 KM 2 Power dissipation at Pp Ta 85 C TSSOP20 181 mw TA Temperature range 1 8 V XVpp lt 3 6 V 40 85 C T id Pene 40 C lt TA lt 85 C 40 1056 C 1 fsyscik fcpu 2 To calculate Ppmax Ta use the formula Pomax Tymax TA Oj with T Aen in this table and Oj in Thermal characteristics table 3 T max S given by the test limit Above this value the product behavior is not guaranteed 2 48 93 DoclD023465 Rev 2 STM8L051F3 Electrical parameters 8 3 2 Embedded reset and power control block characteristics Table 16 Embedded reset and power control block characteristics Symbol Parameter Conditions Min Typ Max Unit t tal BOR detector 1 ao Ml Vpp rise time rate enabled 0 mp us Vpp fall time rate auo a 20 oo 1 trEMP Reset release delay Vpp rising 3 ms Vpepg Power down reset threshold Falling edge 1 300 1 50 1 65 V V Brown out reset threshold 0 Falling edge 1 67 1 70 1 74 BORO BOR TH 2 0 000 Rising edge 1 69 1 75 1 80 V Brown out reset threshold 1 Falling edge 1 87 1 93 1 97 BOR1
70. ling rer not connected to Vppa 85 Power supply and reference decoupling VREF connected to VDDA 85 TSSOP20 20 lead thin shrink small package outline oococcoccocoo o 89 TSSOP20 recommended footprint esee 89 Low density value line STM8L051F3 ordering information scheme 91 DoclD023465 Rev 2 7 93 Introduction STM8L051F3 8 93 Introduction This document describes the features pinout mechanical data and ordering information for the low density value line STM8L051F3 microcontroller with 8 Kbyte Flash memory density For further details on the whole STMicroelectronics low density family please refer to Section 2 2 Ultra low power continuum For detailed information on device operation and registers refer to the reference manual RM0031 For information on to the Flash program memory and data EEPROM refer to the programming manual PM0054 For information on the debug module and SWIM single wire interface module refer to the STM8 SWIM communication protocol and debug module user manual UM0470 For information on the STM8 core refer to the STM8 CPU programming manual PM0044 Low density value line devices provide the following benefits e Integrated system 8 Kbytes of low density embedded Flash program memory 256 bytes of data EEPROM 1 Kbyte of RAM Internal high speed and low power low speed RC Embedded reset e Ultra low powe
71. memory 12 bit ADC up to 1 Msps 28 channels Internal reference voltage Timers Two 16 bit timers with 2 channels used as IC OC PWM quadrature encoder One 8 bit timer with 7 bit prescaler 2 watchdogs 1 Window 1 Independent Beeper timer with 1 2 or 4 kHz frequencies Communication interfaces Synchronous serial interface SPI Fast C 400 kHz SMBus and PMBus USART Up to 18 I Os all mappable on interrupt vectors Development support Faston chip programming and non intrusive debugging with SWIM Bootloader using USART DoclD023465 Rev 2 1 93 This is information on a product in full production www st com Contents STM8L051F3 Contents 1 Introduction wa fhe Stee is boss NAKA RENE Se Seka ERR ENSE 8 2 Description rosse sw KG E Peeters AA 9 2 1 Device overview ns 10 2 2 Ultra low power continuum o 11 3 Functional overview 12 3 1 Low power modes 13 3 2 Central processing unit STM8 ees 14 3 2 1 Advanced STM8 Core 2 2 2 2 ees 14 3 2 2 Interrupt controller eh 14 3 3 Reset and supply management selle 15 3 3 1 Power supply scheme 15 3 3 2 Power supply supervisor 000 cece eee eens 15 3 3 3 Voltage regulator 15 3 4 Clock management a nawa amak Rte dca A EROR dob wonton KAG eee 16 3 5 Low power real time clock cee eee eee 18 3 6 Memories 18 3 7 DMA EET 18 3 8 Analog to digital converter
72. ndependent binary coded decimal BCD timer counter Six byte locations contain the second minute hour 12 24 hour week day date month year in BCD binary coded decimal format Correction for 28 29 leap year 30 and 31 day months are made automatically It provides a programmable alarm and programmable periodic interrupts with wakeup from Halt capability e Periodic wakeup time using the 32 768 kHz LSE with the lowest resolution of 61 us is from min 122 us to max 3 9 s With a different resolution the wakeup time can reach 36 hours e Periodic alarms based on the calendar can also be generated from every second to every year Memories The low density value line STM8LO5xxx devices have the following main features e Upto 1 Kbyte of RAM e The non volatile memory is divided into three arrays 8 Kbytes of low density embedded Flash program memory 256 bytes of Data EEPROM Option bytes The EEPROM embeds the error correction code ECC feature The option byte protects part of the Flash program memory from write and readout piracy DMA A 4 channel direct memory access controller DMA1 offers a memory to memory and peripherals from to memory transfer capability The 4 channels are shared between the following IPs with DMA capability ADC1 I2C1 SPI1 USART1 and the three timers Analog to digital converter e 12 bit analog to digital converter ADC1 with 10 channels including 1 fast channel and internal
73. nit Internal reference voltage IREFINT consumption la HA eme ADC sampling time when reading Ts VREFINT the internal reference voltage P n Hs 2 Internal reference voltage buffer ou consumption used for ADC 139 25 pA VREFINT out Reference voltage output 1 20200 1 224 1 2429 V 2 Internal reference voltage low ILPBUF power buffer consumption 130 1209 na IREFOUT A Buffer output current 1 pA CREFOUT Reference voltage output load 50 pF Internal reference voltage startu tVREFINT time x 2 3 ms 2 Internal reference voltage buffer t 2 1 10 us RUFEN startup time once enabled 1 Accuracy of Vrerint stored in the ACCVREFINT VREFINT_Factory_CONV byte 9 zu id mp NUT a Stability of VREFINT over 40 C lt Ta lt 85 20 50 ppm C STAB temperature C VREFINT m Stability of Vrer nT over 0 C TA lt 50 C 20 ppm C temperature Stability of V after 1000 STABVREFINT Hours 4 EBENE TBD ppm Defined when ADC output reaches its final value 1 2LSB Data guaranteed by Design Not tested in production Tested in production at Vpp 3 V 10 mV To guaranty less than 1 Vpepour deviation gv ZS o m Measured at Vpp 3 V 210 mV This value takes into account Vpp accuracy and ADC conversion accuracy 2 DoclD023465 Rev 2 79 93 Electrical parameters STM8L051F3 8 3 10 12 bit ADC1 characteristics In the following table d
74. ock S S 32 768 kHz Ta 7 40 Cto25 C 2 46 2 75 with TIM2 active TA 55 C 2 50 2 81 Ta 85 C 3 16 3 82 No floating I Os Timer 2 clock enabled and counter is running Oscillator bypassed LSEBYP 1 in CLK_ECKCR When configured for extenal crystal the LSE consumption Ibp tse must be added Refer to Table 29 Figure 11 Typ IDD LPW vs Vpp LSI clock source 16 00 TT 14 00 40 C E 25 C 85 C 6 00 4 00 12 00 10 00 8 00 Joo Pw isi HA Von V ai18217V2 56 93 DoclD023465 Rev 2 2 STM8L051F3 Electrical parameters In the following table data is based on characterization results unless otherwise specified Table 21 Total current consumption and timing in Active halt mode at Vpp 7 1 8 V to 3 6 V Symbol Parameter Conditions 1 Typ Max Unit TA 40 C to 25 C 0 9 2 1 LSI RC at 38 kHz Ty 55 C 1 2 3 Supply current in Ta 85 C 1 5 3 4 UA PP AH Active halt mode Ta 40 Cto25 C 05 12 LSE external clock 32 768 Ce kHz Ta 55 C 0 62 1 4 Ta 85 C 0 88 2 1 Supply current during wakeup time from l DD WUFAH Active halt mode 2 4 mA using HSI Wakeup time from twu asian A Active halt mode to 47 7 us i Run mode using HSI t 3 Wakeup time from WU LSI AH Active halt mode to 150 us 4 Run mode using LSI 1 No flo
75. on and the first ideal one Eg Gain Error deviation between the last ideal transition and the last actual one Ep Differential Linearity Error maximum deviation between actual steps and the ideal one E Integral Linearity Error maximum deviation between any actual transition and the end point correlation line gt Vssa LJ I G LIL T T 6 7 4093 4094 4095 4096 DDA ai14395b Figure 34 Typical connection diagram using the ADC Refer to Table 43 for the values of Ray and Cape STM8LO5xxx Sample and hold ADC converter RADC 12 bit converter ai17090e Cparasitic represents the capacitance of the PCB dependent on soldering and PCB layout quality plus the pad capacitance roughly 7 pF A high Cparasitic value will downgrade conversion accuracy To remedy this fapc should be reduced DoclD023465 Rev 2 83 93 Electrical parameters STM8L051F3 Figure 35 Maximum dynamic current consumption on VRef supply pin during ADC conversion l ADC clock l 300pA Conversion 12 cycles i Sampling n cycles 4 Table 47 Ram max for fapc 16 MHz 1 Guaranteed by design not tested in production 84 93 General PCB design guidelines Ram max kohm m e Slow channels Fast channels 24V lt
76. ons vues 405402900080 coe ANY DINA pp qp 48 8 3 1 General operating conditions 48 8 3 2 Embedded reset and power control block characteristics 49 8 3 3 Supply current characteristics ooo 50 8 3 4 Clock and timing characteristics oooocoooooooooo 60 8 3 5 Memory characteristics o 65 8 3 6 I O current injection characteristics 65 8 3 7 I O port pin characteristics 66 8 3 8 Communication interfaces o 74 8 3 9 Embedded reference voltage ee 79 8 3 10 12 bit ADC1 characteristics sees 80 8 3 11 EMC characteristics es 86 9 Package characteristics c cece eee eee eee 88 9 1 EGOPAGK iaa yr Eg Naka eee aS dake whe do atin ah eats ath ans 88 9 2 Package mechanical data 89 Ky DoclD023465 Rev 2 3 93 Contents STM8L051F3 9 2 1 20 lead thin shrink small package TSSOP20 89 9 3 Thermal characteristics eens 90 10 Device ordering information eee eee 91 11 Revision history vg ee ee ERRARE EGG EN e be Ber EE cede 92 4 93 DoclD023465 Rev 2 Ly STM8L051F3 List of tables List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27
77. package accuracy Table 28 HSE oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit fuse High speed external oscillator 4 16 MHz frequency Rr Feedback resistor 200 kQ C Recommended load capacitance 2 20 pF C 20 pF 2 5 startup fosc 16 MHz 0 7 stabilized lbo Hse HSE oscillator power consumption mA C 10 pF 2 5 startup fosc 216 MHz 0 46 stabilized 9m Oscillator transconductance 3 50 mA V tsutusE Startup time Vpp is stabilized 1 ms 1 C C C is approximately equivalent to 2 x crystal Cj gap 2 The oscillator selection can be optimized in terms of supply current using a high quality resonator with small R value Refer to crystal manufacturer for more details Data guaranteed by Design Not tested in production 4 tsuHse is the startup time measured from the moment it is enabled by software to a stabilized 16 MHz oscillation This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Figure 12 HSE oscillator circuit diagram Rum de diis es 3 fuse to core a HSE R Co j l Em l m i C e L OSC IN os eism e I Consumption A JL Control Resonator l STM8 OSC_OUT Cio 2 HSE oscillator critical gm formula 2 9merit 2X MX fyse x Rm 2C0 C Rm Motional
78. r CIRCUIT 04 pF SENG Optional 2 DoclD023465 Rev 2 73 93 Electrical parameters STM8L051F3 8 3 8 Communication interfaces SPM Serial peripheral interface Unless otherwise specified the parameters given in Table 40 are derived from tests performed under ambient temperature fsysc_ frequency and Vpp supply voltage conditions summarized in Section 8 3 1 Refer to I O port characteristics for more details on the input output alternate function characteristics NSS SCK MOSI MISO Table 40 SPI1 characteristics Symbol Parameter Conditions Min Max Unit Master mode 0 8 fsck SP11 clock frequency MHz tsek Slave mode 0 8 Weck AR CIOCK rise and fal Capacitive load C 30 pF 30 ns t sck time Lues NSS setup time Slave mode 4 X l fsvscik E timss NSS hold time Slave mode 80 twscKH 2 Master mode SCK high and low time 105 145 tw SCKL 9 fuaster 8 MHz fsck 4 MHz t 2 Master mode 30 su Mi Data input setup time tsusi Slave mode 3 t 2 Master mode 15 AMI 2 Data input hold time tsi Slave mode 0 taso 90 Data output access time Slave mode 3x l fsvscik tuis so Data output disable time Slave mode 30 tso 2 Data output valid time Slave mode after enable edge 60 2 E Master mode after enable tymo Data output valid time edge 20 tnso Slave mode after enable edge 15 t
79. r consumption 1yAin Active halt mode Clock gated system and optimized power management Capability to execute from RAM for Low power wait mode and Low power run mode e Advanced features Upto 16 MIPS at 16 MHz CPU clock frequency Direct memory access DMA for memory to memory or peripheral to memory access e Short development cycles A Application scalability across a common family product architecture with compatible pinout memory map and modular peripherals Wide choice of development tools These features make the value line STM8LO5xxx ultra low power microcontroller family suitable for a wide range of consumer and mass market applications Refer to Table 1 Low density value line STM8LO5xxx low power device features and peripheral counts and Section 3 Functional overview for an overview of the complete range of peripherals proposed in this family Figure 1 shows the block diagram of the low density value line STM8L05xxx family 2 DoclD023465 Rev 2 STM8L051F3 Description 2 2 Description The low density value line STM8L05xxx devices are members of the STM8L ultra low power 8 bit family The value line STM8LO5xxx ultra low power family features an enhanced STM8 CPU core providing increased processing power up to 16 MIPS at 16 MHz while maintaining the advantages of a CISC architecture with improved code density a 24 bit linear addressing space and an optimized architecture fo
80. r low power operations The family includes an integrated debug module with a hardware interface SWIM which allows non intrusive In Application debugging and ultra fast Flash programming Low density value line STM8L05xxx microcontrollers feature embedded data EEPROM and low power low voltage single supply program Flash memory The devices incorporate an extensive range of enhanced l Os and peripherals a 12 bit ADC a real time clock two 16 bit timers one 8 bit timer as well as standard communication interfaces such as an SPI an Ic interface and one USART The modular design of the peripheral set allows the same peripherals to be found in different ST microcontroller families including 32 bit families This makes any transition to a different family very easy and simplified even more by the use of a common set of development tools All value line STM8L ultra low power products are based on the same architecture with the same memory mapping and a coherent pinout DoclD023465 Rev 2 9 93 Description STM8L051F3 2 1 Device overview Table 1 Low density value line STM8L05xxx low power device features and peripheral counts Features STM8L051F3 Flash Kbytes 8 Data EEPROM Bytes 256 RAM Kbytes 1 Basic 1 8 bit Timers General 2 purpose 16 bit SPI 1 Communicati 120 1 on interfaces USART 1 GPIOs 18 1 12 bit synchronized ADC 1 number of channels
81. reference voltage e Conversion time down to 1 us with fgysc x 16 MHz e Programmable resolution e Programmable sampling time e Single and continuous mode of conversion e Scan capability automatic conversion performed on a selected group of analog inputs e Analog watchdog e Triggered by timer ADC7 can be served by DMAf 2 DoclD023465 Rev 2 STM8L051F3 Functional overview 3 9 System configuration controller and routing interface The system configuration controller provides the capability to remap some alternate functions on different I O ports TIM4 and ADC1 DMA channels can also be remapped The highly flexible routing interface controls the routing of internal analog signals to ADC1 and the internal reference voltage VREFINT 3 10 Timers Low density value line STM8L05xxx devices contain two 16 bit general purpose timers TIM2 and TIM3 and one 8 bit basic timer TIM4 All the timers can be served by DMA1 Table 2 compares the features of the advanced control general purpose and basic timers Table 2 Timer feature comparison Counter Counter DMAT Capture compare Complementar Timer Prescaler factor request pru P p y resolution type channels outputs generation TIM2 16 bit up down Any Beer oe 2 TIM3 from 1 to 128 Yes None F Any power of 2 PM debi R from 1 to 32768 a 3 10 1 16 bit general purpose timers TIM2 TIM3 e 16 bit autoreload AR up down counter e T bit prescal
82. requency deviation LCD levels etc The test results are given in the following table Table 34 I O current injection susceptibility Functional susceptibility Symbol Description Negative Positive Unit injection injection Injected current on true open drain pins PCO and 5 0 PC1 lii Injected current on all five volt tolerant FT pins 5 0 mA Injected current on all 3 6 V tolerant TT pins 5 0 Injected current on any other pin 5 5 UO port pin characteristics General characteristics Subject to general operating conditions for Vpp and T4 unless otherwise specified All unused pins must be kept at a fixed voltage using the output mode of the l O for example or an external pull up or pull down resistor d DoclD023465 Rev 2 STM8L051F3 Electrical parameters Table 35 I O static characteristics Symbol Parameter Conditions Min Typ Max Unit Input voltage on true open drain Ves 0 3 0 3x V pins PCO and PC1 es ore Input voltage on five volt tolerant FT pins PA7 and Vss 0 3 0 3 x Vpp Vi Input low level voltage 2 PEO V Input voltage on 3 6 V tolerant Vec 0 0 3 x V TT pins sel 2x VDD Input voltage on any other pin Vss 0 3 0 3 x Vpp Input voltage on true open drain pins PCO and PC1 5 2 with Vop lt 2V 0 70 x Vpp Input voltage on true open drain pins PCO and PC1 5 5 with Vpp gt 2V Input voltage on five volt tolerant
83. resistance see crystal specification Lm Motional inductance see crystal specification Cm Motional capacitance see crystal specification Co Shunt capacitance see crystal specification C 472C 52C Grounded external capacitance 9m gt gt Omerit DoclD023465 Rev 2 61 93 Electrical parameters STM8L051F3 LSE crystal ceramic resonator oscillator The LSE clock can be supplied with a 32 768 kHz crystal ceramic resonator oscillator All the information given in this paragraph is based on characterization results with specified typical external components In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time Refer to the crystal resonator manufacturer for more details frequency package accuracy Table 29 LSE oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit fs PR external oscillator 32 768 kHz Rr Feedback resistor AV 200 mV 1 2 MO c Recommended load capacitance 2 8 pF 1 49 UA Vop 1 8 V 450 Joo sp LSE oscillator power consumption Von 3 V Sg S Vpp 3 6 V 750 Om Oscillator transconductance 3 pA tsuLse A Startup time Vpp is stabilized 1 s C C 4C is approximately equivalent to 2 x crystal Cj gap 2 The oscillator selection can be optimized in terms of supply current using a high quality
84. resonator with a small Rm value Refer to crystal manufacturer for more details Data guaranteed by Design Not tested in production 4 tsu Lse is the startup time measured from the moment it is enabled by software to a stabilized 32 768 kHz oscillation This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Figure 13 LSE oscillator circuit diagram Bm Co l Lm l Cm Resonator STM8 Lse gt Rr M C OSC_IN e 9m Consumption o control Resonator FE OSC_OUT Ci 62 93 DoclD023465 Rev 2 2 STM8L051F3 Electrical parameters Internal clock sources Subject to general operating conditions for Vpp and Ta High speed internal RC oscillator HSI In the following table data is based on characterization results not tested in production unless otherwise specified Table 30 HSI oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit fusi Frequency Vpp 3 0 V 16 MHz Accuracy of HSI Vpp 3 0 V Ta 25 C 40 10 Vo ACChs oscillator factory 1 8 V Vpp lt 3 6 V a calibrated 40 C lt T lt 85 C 5 5 SEIT HSI user trimming Trimming code multiple of 16 0 4 0 7 Yo step Trimming code multiple of 16 15 HSI oscillator setup 4 suHS time wake
85. rol pins must not exceed lyss The le current sourced must always respect the absolute maximum rating specified in Table 13 and the sum Of lio I O ports and control pins must not exceed lypp Table 37 Output driving current true open drain ports Eid Symbol Parameter Conditions Min Max Unit ype lo 3 MA c IO D Von 3 0V 0 43 2 Va Output low level voltage for an UO pin V 2 lio 1 mA 0 45 o Vpp 1 8 V The lig current sunk must always respect the absolute maximum rating specified in Table 13 and the sum of lio I O ports and control pins must not exceed lyss Table 38 Output driving current PAO with high sink LED driver capability din Symbol Parameter Conditions Min Max Unit Type 4 lio 20 mA x Vo Output low level voltage for an UO pin Van 2 0 V 0 45 V DD 4 The lig current sunk must always respect the absolute maximum rating specified in Table 13 and the sum of ljo do ports and control pins must not exceed lyss d DoclD023465 Rev 2 STM8L051F3 Electrical parameters Figure 20 Typ Vo Vpp 3 0 V high sink Figure 21 Typ Vo Vpp 1 8 V high sink ports ports 1 07 Se 40 C 0 6 40 C 25 C a 25 C 0 5 85 C 85 C os SEH gt 3 gt 0 3 0 25 0 2 a 0 1 0 0 2 4 6 8 10 12 14 16 18 20 os lo mA 0 1 2 3 4 5 6 7 8 ai18226V2 lo mA
86. s Yes 0x00 8054 interrupt 40 93 DoclD023465 Rev 2 ky STM8L051F3 Interrupt vector mapping Table 9 Interrupt mapping continued Wakeu Wakeup Wakeup Wakeup IRQ Source Description from SCH from from Wait from Wait Vector No block P Active halt WFI WFE address mode 1 mode mode mode s0 ima RENE e Yes Yes 0x00 8058 interrupt TIM3 Update 21 TIM3 Overflow Trigger Break Yes Yes 0x00 805C interrupt ex Tig A Capture Compare e Yes Yes 0x00 8060 interrupt 23 RI RI trigger interrupt Yes 0x00 8064 24 Reserved 0x00 8068 TIM4 updat rfl 2 2 ma AN e gt Yes Yes 0x00 806C trigger interrupt SPI1 TX buffer empty 26 SPI RX buffer not empty Yes Yes Yes Yes 0x00 8070 error wakeup interrupt USART1 transmit data 27 UsART 1 register empty Yes Yes 0x00 8074 transmission complete interrupt USART1 received data 28 eneen Yemen e Yes Yes 0x00 8078 idle line detected parity error global error interrupt 29 12C1 12C1 interrupt Yes Yes Yes Yes 0x00 807C 1 The Low power wait mode is entered when executing a WFE instruction in Low power run mode In WFE mode the interrupt is served if it has been previously enabled After processing the interrupt the processor goes back to WFE mode When the interrupt is configured as a wakeup event the CPU wakes up and resumes processing 2 DoclD023465 Rev 2 The TLI interrupt is the logic OR betwe
87. s described in Figure 6 Figure 6 Pin input voltage cn STM8L PIN 8 2 Absolute maximum ratings Stresses above those listed as absolute maximum ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device under these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability Table 12 Voltage characteristics Symbol Ratings Min Max Unit External supply voltage including Vppa Vpp Vss and Vpp2 0 3 4 0 V Input voltage on true open drain pins PCO and PC1 Vss 0 3 Voo 4 0 Input voltage on five volt tolerant FT VIN pins PA7 and PEO Vss 0 3 Vas 4 0 V Input voltage on 3 6 V tolerant TT pins Vss 0 3 4 0 Input voltage on any other pin Vss 0 3 4 0 see Absolute maximum Vesp Electrostatic discharge voltage ratings electrical sensitivity on page 87 1 All power Vpp1 Vpp2 VppA and ground Masi Vss2 Vssa pins must always be connected to the external power supply 2 Vij maximum must always be respected Refer to Table 13 for maximum allowed injected current values 46 93 DoclD023465 Rev 2 2 STM8L051F3 Electrical parameters 2 Table 13 Current characteristics Symbol Ratings Max Unit kapp Total current into Vpp power line source 80 lyss Total current out of Vss groun
88. sive choice not a duplication of the function 3 A pull up is applied to PBO and PB4 during the reset phase These two pins are input floating after reset release 4 In the open drain output column T defines a true open drain UO P buffer and protection diode to Vpp are not implemented The PAO pin is in input pull up during the reset phase and after reset release High Sink LED driver capability available on PAO opm Note The slope control of all GPIO pins except true open drain pins can be programmed By default the slope control is limited to 2 MHz 4 1 System configuration options As shown in Table 4 Low density value line STM8LO5xxx pin description some alternate functions can be remapped on different UO ports by programming one of the two remapping registers described in the Routing interface RI and system configuration controller section in the STM8L 15xx and STM8L16xx reference manual RM0031 2 DoclD023465 Rev 2 25 93 Memory and register map STM8L051F3 5 5 1 26 93 Memory and register map Memory mapping The memory map is shown in Figure 4 Figure 4 Memory map 0x00 0000 RAM Up to 1 Kbyte including Stack 512 bytes 0x00 03FF 0x00 0400 0x00 1FFF BEE 0x00 1000 Data EEPROM 256 Bytes 0x00 10FF 0x00 1100 Reserved 0x00 47FF 0x00 4800 ti t 0x00 487 F Option bytes 0x00 4880 0x00 4FFF Reserved 0x00 5000 GPIO and peripheral registers 0x00 5457 0x00 54
89. ta Symbol Parameter Conditions riu Voltage limits to be applied on Vpp 3 3 V Ta 25 C Vresp any I O pin to induce a functional fepy 16 MHz 3B disturbance conforms to IEC 61000 Fast transient voltage burst limits o Vop 3 3 V Tas V to be applied through 100 pF on f BB SC ME ai Using HSI JA EFTB Vpp and Vss pins to induce a CPU Es functional disturbance conforms to IEC 61000 Using HSE 2B Electromagnetic interference EMI Based on a simple application running on the product toggling 2 LEDs through the I O ports the product is monitored in terms of emission This emission test is in line with the norm IEC61967 2 which specifies the board and the loading of each pin DocID023465 Rev 2 Ly STM8L051F3 Electrical parameters 2 Table 49 EMI data 1 Monitored MAX Ve Symbol Parameter Conditions Unit frequency band 16 MHz Vpp 3 6 V 0 1 MHz to 30 MHz 3 TA 25 C 30 MHz to 130 MHz 9 dBuv SEMI Peak level LQFP32 conforming to 130 MHz to 1 GHz 4 1EC61967 2 SAE EMI Level 2 1 Not tested in production Absolute maximum ratings electrical sensitivity Based on two different tests ESD and LU using specific measurement methods the product is stressed in order to determine its performance in terms of electrical sensitivity For more details refer to the application note AN1181 Electrostatic discharge ESD Electrostatic disch
90. terrupt control register 2 0x00 0x00 50A2 EXTI CR3 External interrupt control register 3 0x00 ITC EXTI 0x00 50A3 EXTI SR1 External interrupt status register 1 0x00 0x00 50A4 EXTI SR2 External interrupt status register 2 0x00 0x00 50A5 EXTI CONF1 External interrupt port select register 1 0x00 0x00 50A6 WFE CR1 WFE control register 1 0x00 0x00 50A7 WEE WFE CR2 WEE control register 2 0x00 0x00 50A8 WFE CR3 WFE control register 3 0x00 0x00 50A9 WEE CR4 WEE control register A 0x00 0x00 50AA EXTI CR4 External interrupt control register 4 0x00 ITC EXTI 0x00 50AB EXTI CONF2 External interrupt port select register 2 0x00 0x00 50A9 to Reserved area 7 bytes 0x00 50AF 0x00 50B0 Bi RST CR Reset control register 0x00 0x00 50B1 RST SR Reset status register 0x01 0x00 50B2 PWR_CSR1 Power control and status register 1 0x00 PWR 0x00 50B3 PWR CSR2 Power control and status register 2 0x00 0x00 50B4 to Reserved area 12 bytes 0x00 50BF 0x00 50CO CLK CKDIVR CLK Clock master divider register 0x03 0x00 50C1 CLK CRTCR CLK Clock RTC register 0x001 tuma CLK 0x00 50C2 CLK ICKCR CLK Internal clock control register 0x11 Ox00 50C3 CLK PCKENR1 CLK Peripheral clock gating register 1 0x00 30 93 DoclD023465 Rev 2 KYI STM8L051F3 Memory and register map Table 7 General hardware register map continued
91. ters STM8L051F3 Figure 31 SPI1 timing diagram master model High NSS input SCK output SCK output i T TEE SCK WER MSBIN BIT6 IN LSB IN lt th C rry Ml M wspout OUT BIT1 OUT isor OUT OUTUT les h MO DING 1 ai14136 1 Measurement points are done at CMOS levels 0 3Vpp and 0 7Vpp 2 76 93 DoclD023465 Rev 2 STM8L051F3 Electrical parameters 12C Inter IC control interface Subject to general operating conditions for Vpp fasc and Ta unless otherwise specified The STMBL IC interface 12C1 meets the requirements of the Standard I C communication protocol described in the following table with the restriction mentioned below Refer to I O port characteristics for more details on the input output alternate function characteristics SDA and SCL Table 41 I2C characteristics Standard mode 2 Ge Fast mode CT Symbol Parameter Unit Min Max Min Max 2 twsciL SCL clock low time 4 7 1 3 us twsciH SCL clock high time 4 0 0 6 tsuspa SDA setup time 250 100 thispa SDA data hold time 0 0 900 t SDA SDA and SCL rise time 1000 300 ns tuscL t SDA SDA and SCL fall time 300 300 t scL tista START condition hold time 4 0 0 6 Repeated START condition setu us tsu STA E P 4 7 0 6 tsusto STOP condition setup time 4 0 0 6 us STOP to START condition time bus
92. tivated by hardware WWDG HALT Window window watchdog reset on Halt Active halt 0 Window watchdog stopped in Halt mode 1 Window watchdog generates a reset when MCU enters Halt mode OPT4 HSECNT Number of HSE oscillator stabilization clock cycles 0x00 1 clock cycle 0x01 16 clock cycles 0x10 512 clock cycles 0x11 4096 clock cycles LSECNT Number of LSE oscillator stabilization clock cycles 0x00 1 clock cycle 0x01 16 clock cycles 0x10 512 clock cycles 0x11 4096 clock cycles Refer to Table 29 LSE oscillator characteristics on page 62 2 DoclD023465 Rev 2 43 93 Option bytes STM8L051F3 Table 11 Option byte description continued Option byte Option description No BOR ON 0 Brownout reset off OPT5 1 Brownout reset on BOR TH 3 1 Brownout reset thresholds Refer to Table 20 for details on the thresholds according to the value of BOR TH bits OPTBL 15 0 This option is checked by the boot ROM code after reset Depending on OPTBL content of addresses 00 480B 00 480C and 0x8000 reset vector the CPU jumps to the bootloader or to the reset vector Refer to the UM0560 bootloader user manual for more details 44 93 2 DoclD023465 Rev 2 STM8L051F3 Electrical parameters 8 8 1 2 Electrical parameters Parameter conditions Unless otherwise specified all voltages are referred to Vss Minimum and maximum values Unless otherwise spe
93. tw STO STA free 4 7 1 3 us Cp Capacitive load for each bus line 400 400 pF 1 fsyscix must be at least equal to 8 MHz to achieve max fast C speed 400 kHz 2 Data based on standard I C protocol requirement not tested in production Note For speeds around 200 kHz the achieved speed can have at 5 tolerance For other speed ranges the achieved speed can have at 2 tolerance The above variations depend on the accuracy of the external components used Ly DoclD023465 Rev 2 77 93 Electrical parameters STM8L051F3 78 93 Figure 32 Typical application with 12C bus and timing diagram Von Von 4 7kQ 2 mog 1000 SDR e Wi PC BUS 1000 SCL STM8L REPEATED START 1 su SDA th SDA 1 pe START tsu STA 1 iw STO STA START PAM Ng soa NJ L X X ua pa HI i i i bn NG i i t gt e E Sereaiy 1 i SDA SDA um STOP i i gt lt thsta twScLH twScLL ec Web tsu sTO Measurement points are done at CMOS levels 0 3 x Vpp and 0 7 x Vpp DoclD023465 Rev 2 2 STM8L051F3 Electrical parameters 8 3 9 Embedded reference voltage In the following table data is based on characterization results not tested in production unless otherwise specified Table 42 Reference voltage characteristics Symbol Parameter Conditions Min Typ Max U
94. ult alternate function 5 9 5 a s alal s D S E O e ss 0 9 z E mm c ul I 4 NRST PA1 1 O D HS X Reset PA1 PA2 OSC IN USART TX Oy Port HSE oscillator input USART 5 SPI MISO ue X bei S E aaa transmit SPI master in slave out 2 6 Daer OUTI USART RXf 1 0 xixixius x x Port HSE oscillator output USART SPI MOSI A3 receive SPI master out slave inj 10 PBOO TIM2 CH1 ADC1 IN18 I O X X X HS X X a Timer 2 channel 1 ADC1 IN18 11 PB1 TIM3 CH1 ADC1 IN17 1 0 X X X HS X X E Timer 3 channel 1 ADC1 IN17 12 PB2 TIM2 CH2 ADC1 IN16 I O X X X HS X X dnd Timer 2 channel 2 ADC1 IN16 PB3 TIM2 ETR Port Timer 2 external trigger 13 ADC1_IN15 RTC_ALARM us XTX S pss A B3 ADC1 IN15 RTC ALARM 3 Port SPI master slave select 14 IPBAS SPI1 NSS ADC1 IN14 I O X X X HS X X B4 ADC1 IN14 PB5 SPI SCK Port 15 ADC1 IN13 1 0 X X X HS X X B5 SPI clock ADC1 IN13 PB6 SPI1_MOSI Port SPI master out 16 ADC1 IN12 is Apes Kas Laba kl B6 slave in ADC1 IN12 Port SPI1 master in slave out 17 PB7 SPI1 MISO ADC1 IN11 1 0 X X X HS X X B7 ADC1_IN11 4 Port 18 PCO I2C SDA lO FT X X T CO I2C data 3 Port 19 PC1 I2C SCL lO FT X X T C1 I2C clock USART synchronous clock PCA USART CK Port 20 1 0 X X X HS X X I2C1 SMB Configurable clock I2C SMB CCO ADC1 IN4 C4 output ADC1 IN4 LSE oscillator input SPI PC5 OSC32 IN SPI1 NSSI Y Port 1 USART TXJITIM2 CH1 1 0 X X X HS X
95. up time Ge S e lone HSI oscillator power 100 440 UA consumption 1 Vpp 3 0 V T4 40 to 85 C unless otherwise specified Tested in production The trimming step differs depending on the trimming code It is usually negative on the codes which are multiples of 16 0x00 0x10 0x20 0x30 0xE0 Refer to the AN3101 STM8L 15x internal RC oscillator calibration application note for more details 2 Guaranteed by design not tested in production Figure 14 Typical HSI frequency vs Vpp HSI frequency MHz 18 0 17 5 17 0 16 5 16 0 15 57 15 0 14 5 14 0 13 5 13 0 1 8 1 95 2 1 2 25 24 2 55 2 7 2 85 Voo V 3 3 15 33 345 3 6 ai18218V2 DoclD023465 Rev 2 63 93 Electrical parameters STM8L051F3 Low speed internal RC oscillator LSI In the following table data is based on characterization results not tested in production Table 31 LSI oscillator characteristics Symbol Parameter 1 Conditions Min Typ Max Unit fLsi Frequency 26 38 56 kHz tu si LSI oscillator wakeup time 2002 us LSI oscillator frequenc 7 pps ara SM 0 C TA 85 C 12 11 1 Vpp 1 8 V to 3 6 V Ta 40 to 85 C unless otherwise specified 2 Guaranteed by design not tested in production 3 This is a deviation for an individual part once the initial frequency has been measured
96. us TIM4 SR1 TIM4 status register 1 0x00 0x00 52E6 TIM4 EGR TIM4 Event generation register Ox00 0x00 52E7 TIM4 CNTR TIM4 counter 0x00 0x00 52E8 TIM4 PSCR TIM4 prescaler register 0x00 0x00 52E9 TIM4 ARR TIM4 Auto reload register 0x00 0x00 52EA to Reserved area 21 bytes 0x00 52FE 0x00 52FF IRTIM IR CR Infrared control register 0x00 0x00 5317 to Reserved area 41 bytes 0x00 533F 0x00 5340 ADC1 CR1 ADC1 configuration register 1 0x00 0x00 5341 ADC1 CR2 ADC1 configuration register 2 0x00 0x00 5342 ADC1 CR3 ADC1 configuration register 3 Ox1F 0x00 5343 ADC1 SR ADC1 status register 0x00 0x00 5344 ADC1 DRH ADC1 data register high 0x00 0x00 5345 ADC1 DRL ADC1 data register low 0x00 0x00 5346 ADC1 HTRH ADC1 high threshold register high OxOF 0x00 5347 ADC1 HTRL ADC1 high threshold register low OxFF 0x00 5348 ADC1 LTRH ADC1 low threshold register high 0x00 0x00 5349 SZ ADC1 LTRL ADC1 low threshold register low 0x00 0x00 534A ADC1 SQR1 ADC1 channel sequence 1 register 0x00 0x00 534B ADC1 SQR2 ADC1 channel sequence 2 register 0x00 0x00 534C ADC1 SQR3 ADC1 channel sequence 3 register 0x00 0x00 534D ADC1 SQR4 ADC1 channel sequence 4 register 0x00 0x00 534E ADC1 TRIGR1 ADC1 trigger disable 1 0x00 0x00 534F ADC1_TRIGR2 ADC1 trigger disable 2 0x00 0x00 5350 ADC1_TRIGR3 ADC 1 trigger disable 3 0x00 0x00 5351 ADC1_TRIGR4 ADC1 trigger disable 4 0x00 36 93 DoclD023465 Rev 2 er
97. x00 5457 RI IOSRA RI I O switch register 4 0x00 1 These registers are not impacted by a system reset They are reset at power on er DoclD023465 Rev 2 37 93 Memory and register map STM8L051F3 Table 8 CPU SWIM debug module interrupt controller registers Address Block Register label Register name deba 0x00 7F00 A Accumulator 0x00 0x00 7F01 PCE Program counter extended 0x00 0x00 7F02 PCH Program counter high 0x00 0x00 7F03 PCL Program counter low 0x00 0x00 7F04 XH X index register high 0x00 0x00 7F05 cpu XL X index register low 0x00 0x00 7F06 YH Y index register high 0x00 0x00 7F07 YL Y index register low 0x00 0x00 7F08 SPH Stack pointer high 0x03 0x00 7F09 SPL Stack pointer low OxFF 0x00 7FOA CCR Condition code register 0x28 ped p mr Reserved area 85 bytes 0x00 7F60 CFG GCR Global configuration register 0x00 0x00 7F70 ITC SPR1 Interrupt Software priority register 1 OxFF 0x00 7F71 ITC SPR2 Interrupt Software priority register 2 OxFF 0x00 7F72 ITC SPR3 Interrupt Software priority register 3 OxFF 0x00 7F73 ITC SPR4 Interrupt Software priority register 4 OxFF 0x00 7F74 nens ITC SPR5 Interrupt Software priority register 5 OxFF 0x00 7F75 ITC SPR6 Interrupt Software priority register 6 OxFF 0x00 7F76 ITC SPR7 Interrupt Software priority register 7 OxFF

STM8L051F3 - STMicroelectronics

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