DK4000-C167 User Manual
Contents
1. 507 Or 5 14914 0709 eor 0010 Ww 09 Z W 0 810 7m TOV 0019 5 22 0005 exu OIOV 00 100168 NIZX3 OISLOO S 2d 00771 ed NISX3 OI LOO E 24 09 21 Zd NIEX3 OILLOO L bed NIZX3 OI0199 01 Zd NILX3 OI6OO 6 NIOX3 OI8O9 8 2d 0 09 24 OI900 92d 520 924 09 Zd OI009 02d Old 1 4 ld vai aw THM HMi zzy AANZL SLNV SL Sd G3neLvINV eL Sd NISL ELNV EL Sd G30SLLINV LI Sd G3n9L 0INv OL Sd lev fed 492919 61 aly Lv tiay giay ziav oray 5 d IM 84 Olz229 9 88 0 99 Ol0229 8d 016109 89 018 00 2 88 OIZ199 L 8d 019199 0 8d 4 OI0629 9 4d 016209929 29 BLNOd E 4d 1 74 LINOJ 2d 01nOd 0 2d 9d 9 Q 10Hi S 9d SOi E 9d 260 294 180i L 9d 0SOi 0 9d BNV 6 Sd SNV 8 Sd INV L Sd 9NV 9 Sd SNV S Sd Sd ENV E Sd INV L Sd ONV O Sd2. wos 0 99 0 55 OOVeL T T aen 11881 aen S0OVeL wey MU EY rd Sezu y D ot wees JIL NIST TII TOHINOD OE 90994 oen azn 859 T ven eru NISHI Na OPZOHAbL 224 1 Gum nv ____ L 4 aw Trea 145 NHHS 2780 trad NYT 9 srad IND zaa USHEG V mojek av Ww 7201 31109 UN 90 19180 Ta SNITT par 299 5 09 1180 23 27 DK4000 C167 USER MANUAL Figure 18 Loop Back Tester Passive FlashLINK to FlashLINK assy TMS TDO ITERR CON14 PC signal PC signal output input connector
3. receptacle polarized TDI ITSTAT ACKN 8 ERRN 10 PAP 9 105346 Appendix E Results codes and debug tree 8031_f1 obj Results codes Table 4 Hexadecimal to Binary Conversion pow par p pm foo for fon MN 24 27 DK4000 C167 USER MANUAL Table 5 Debug Tree 4 7 EE ____________ Replace PSD u1 EVD and retest Replace PSD u1 EVD and retest External Ram error Replace sram u3 EVM and retest Repair u4 or surrounding circuitry EVM this is under the EVD board Note X don t care Appendix F Board errata Following is a brief list of issues with correlated on a revision level basis Rev B Center row of connections for U5 contain solder mask This row is intended for a socket to accom modate 0 3 wide SRAM Also pin 16 is left out These will be corrected at next board rev 25 27 DK4000 C167 USER MANUAL Table 6 Document Revision History Rev Description of Revision a Document written in the WSI format 19 Oct 2001 2 Document converted to the ST format 26 27 DK4000 C167 USER MANUAL For current information on PSD products please consult our pages on the world wide web www st com psd If you have any questions or suggestions concerning the matters raised in this document please send them to the fol
4. osezezsonw 90 Ko FOOPNL za 16 27 DK4000 C167 USER MANUAL Table 2 DK4000 Parts List Generic Part Description Vendor Number dis101 0001 hantronix umcu0002 infineon Yamiachi IC149 080 030 S5 u232 0001 analog devices adm202jrn usup0002 maxim 5 max6315leuk ureg 0001 micrel mic5237 5 0bt cr101 0001 stab vr101 0001 mmsz5254bt1 cr101 0002 national fdLL4148 led101 0002 lumex SLX LX5093ID 2 cap0805 2209 22 pf caps cer murata grm40c0g22050ad Qua ntity 1 1 1 1 Ref Des Part Number hdm16216h b vfsmc 316pf11 0592 C161V c lt 4 1 1 1 4 1 1 47 15 1 2 c10 c21 c23 c25 4 1206 1004 1uf tant murata grm42 6y5v105z016ad 12 19 2 1206 1004 tuf cer 1206 AVX 1206zc105mat2a C3 9 c11 c13 18 c20 c22 c24 18 cap0805 1003 0 1 cap smt cer murata 1 3 grm40z5u104z016ad rm10j106ct rm12j101ct res0805 1005 resistor smt 10M 1 8 watt 0805 samsung res0805 1000 resistor smt 100 1 8 watt samsung res0805 1002 resistor smt 10k 1 8 watt 0805 samsung r5 10 r12 r23 r32 47 R54 35 R55 R24 31 R53 jp1 jp3 rm10f1002ct 3309P 103 ND rm10f820ct tsw 103 23 L s LL snt 100 bk g tsw 103 23 L T LL mnt 103 bk g variable resistor 10k digikey res0805 8200 resi
5. 05 8 YSLW 6 Ed 1SHW 8 Ed SLE9XVIN anaeLr ed 1 10091789 t 72155 iau No A 99 Figure 12 Main Schematic 15 27 DK4000 C167 USER MANUAL 7 tiva e Af EEENTETI ELENEI Tedi OL odd oidr zl 969 4 T4 gt Figure 13 Power Supply Schematic meod 13934 4M 01ND 4 09 7
6. be controlled by the definition of pairs of buscon and addr registers for each discrete area The project definitions of these registers are denoted in the memory map figure below The default configuration syscon and buscon0 is 16 bit multiplexed for the following system resources m C167 resources m PSD code memory main and secondary Flash memory and boot areas m PSD SRAM Two additional areas are defined as 8 bit multiplexed as shown below for the following system resources m LCD m CSIOP space PSD registers The C167CR XRAM and CAN areas are not used Figure 8 Memory map of DK4000 167 Board OxOFFFF Ox1 FFFF 167 System Area 0x0C000 CSIOP PSD buscon1 LCD buscon1 0 0 00 0 0 000 PSD RAM 4 16 Flash 0 08000 PSD FSO 32Kx16 0x04000 Code PSD Boot area 0 1 x16 0x10000 Segment 0 Segment 1 Boot Configuration 105706 Note Default x16 multiplex bus used syscon and buscon0 unless otherwise noted Memory Swapping in the PSD For this test hwtest obj the dip switch should be in the following position As a component of this test a copy of the executing code that resides in csboot0 1 is made The destination of this copy is 1577 9 27 DK4000 C167 USER MANUAL the main Flash memory area FSO as shown in the figure below After the copy operation the following map applies Figure 9 Memory map after ru
7. 00 C167 USER MANUAL Appendix C Development Board Schematic and parts list 0002 Zi Jequin ueuinoog 80291 peog jueuidojeneg 000a 939 135397 qu ILNI eps ye 8218295 1 O11NO 82 OL Y SON 0 Fe 222 666 18538 ABLSA 93d 1 93 AGU LV LSL P3d Usp MOL Lad ISOi eQd dd anv oad qui HN 011 0 sioiav groay 02510107 SIOIdV errom Sir TO TE 21010 LLOIAY 6010Y 1111914 91770707 mov ororo 0 10 211 sora 20107 solay volav 2010 1L SOIdV Bory OIOV 707 SOIGv 901 5010 2
8. 57 CONTENTS m A COUPLE OF DEFINITIONS HARDWARE m SOFTWARE m DETAILED DESCRIPTIONS m OTHER BOARD FEATURES Step By Step Instruc tions for ISP Program ming m USING DK4000 AS A DEVELOPMENT PLATFORM FOR C167CR USERS Concept Downloading to the De velopment Board JTAG ISP m 167 DESIGN OVERVIEW Memory Swapping in the PSD What really happens Creating your own IAP code bundle m REFERENCES m APPENDIX October 2001 DK4000 C167 USER MANUAL Development Kit for PSD4000 and C167 Congratulations on purchasing ST s DK4000 Development kit The DK4000 110 or 220 volt version is a low cost kit for eval uating the PSD4000 series of Flash Programmable System Devices called PSDs The DK4000 kit is extremely versatile and can be used in several different modes It can be used to demonstrate the PSD4000 s capability of JTAG In System Pro grammability ISP Once initial code is resident in the PSD the program code can be updated while the MCU is running called In Application Programming IAP Also Infineon C167CR family users can utilize the DK4000 as an evaluation platform for code development The DK4000 C167 Development Board is specific to the Infi neon C167CR micro controller family However other prolifer ation boards will be available Check the website at www st com psd as to availability A COUPLE OF DEFINITIONS In System Programming ISP A JTAG inter
9. D 06 00 01 S N 8 HN RST VCC Note 2 85 TDI is a signal source on the Flashlink TSTAT TDI and a signal destination on the target 4B board or Digikey M3CCK 14065 ND TDO is a signal destination on the FlashLink and a signal source on the target board 105343 21 27 DK4000 C167 USER MANUAL Figure 16 Chaining Example FlashLink Adapter Conncetor TMS TCK TDI TDO 14 optional TERR E 13 PSD4000 1 optional TMS 2 2 Optional TCK 3 4 Optional TDI 8 recommended TDO 10 Any JTAG 12 Device in all ground pins are ByPass Mode connected together inside FlashLINK assembly TMS h TCK straight through TDI ribbon cable TDO 2 row 7 position System TSTAT Reset JTAG Chaining Example Circuitry TERR bep400p PSD4000 and other JTAG compatible devices A105344 22 27 DK4000 C167 USER MANUAL Figure 17 Loop back connector schematic 5002781 Mumyse jequimNiueumoog 225 gt 6 wurquser4 8956 VO uou oey 082 4 ejeosieje 909994 zr 909 or 320 vO6ENZ 10 DAs t r
10. DK4000 C167 USER MANUAL Figure 4 PSDsoft Express flow Design Flow Specify Projet Click here EN Dere PSD Fin gt her etian her Artian F amp dcriznal PTS verga wcU dtar Czirpier Femyeare wta SL Lnksr Cisbueger 1 ede or Asserbhy Dev ming alx EY Conventional eater tbe FBP The following screen appears inquiring if it s desired to program a single device or multiple devices in the JTAG chain Select Only one and then click OK Figure 5 JTAG ISP Operations dialog JTAG ISP Operations x How many devices are in the JTAG chain on your circuit board More than one Do not display this message on subsequent entry into the JTAG ISP Clicking OK brings up the JTAG Operations Single device dialog shown in the following figure 6 27 DK4000 C167 USER MANUAL Figure 6 PSDsoft Express JTAG Operations dialog JTAG ISP Operations Single Device 14 32an 5 Step 1 Select Programming file and PSD Select folder and programming file Select device D PSDexpress dk4kp 167 demo1 167 a1 6xbhe obj PSD4135G2 Step 2 Specify JTAG ISP operation and conditions Select operation Select PSD region Select of JTAG pins to use Other conditions Program h All pins Propertie
11. FLASH The following memory map applies Figure 10 Memory map for alternate memory boot OxoFFFF OxiFFFF 167 System Area 0x0C000 CSIOP PSD buscon1 0 0 00 LCD buscon1 0x0A000 PSD RAM 4Kx16 0x08000 0x04000 Main Flash code copy from 500010 1 message main flash 0x10000 Segment 0 Segment 1 105708 The memory movement within the MCU memory map is accomplished via the logic contained in the PLD equations in the PSD Each segment that moves must have dual ranged defined in these equations The selection is made based on a single logic bit exe_src_a that resides in the PSD PAGE register Following are the equations for the system These can bee seen in the PSDsoft Express project included with the kit Note that indicates logical OR and 8 indicates a logical AND Csboot0 0x0 OxOlPFF amp exe src a Csboot1 0x02000 Ox03FFF amp exe src a FsO 0x10000 OxlFFFF amp exe src a 0 0 OxOGFFF amp exe src Note that the logic variable bit controlling the actual location of the memory is src a When this bit is zero 0 the memory segments are as shown in figure 9 When exe src a is one 1 FSO appears in the execution location and the csboot areas are not in the map at all The physical location of this logic bit exe src a is in the bit6 position of the PAGE register Actually this bi
12. ace from a standard PC parallel port to one or more PSD4000 devices located within a target PC board as shown below This interface cable allows the PSD to be ex ercised for purposes of programming and or testing PSDsoft Express is the source for driving FlashLINK Figure 14 Typical FLASHlink application Flying lead cable Mates with FlashLink fiz wines Target adapter j device port CV 6inches 9 105342 Operating considerations Operating power for FlashLINK is derived from the target system in the range of 2 7 to 5 5 V Compatibility over this voltage range is ensured by the design of FlashLINK No set tings are involved On acautionary note it is recommended that the target system be powered with a well regulated and sta ble source of power which is energized at the final value of Vcc It is not recommended that the input volt age be varied using the verneer on a regulated power supply as this may cause the internal FlashLINK ICs 74VHC240 to misoperate toward the lower end of the supply range Each FlashLINK is packaged with a six inch flying lead cable for maximum adaptability a ribbon cable requires the use a certain connector on the target assembly This flying lead cable mates to the FlashLink adapter on one end and has loose sockets on the other end to slide onto 0 025 square posts on the target assembly 19 27 DK4000 C167 USER MANUAL Table 3 Pin descr
13. by manufacturer and part number Graphical definition of pin functions Easy creation of memory JTAG ISP Programming Downloadable demonstration software Visit the development tools section of ST PSM product division website at www st com psd to down load the file 167_disk zip The development boards ship with the hardware test hwtest obj file already resident A detailed descrip tion of this software bundle is included in Appendix B The following table is a specific listing of the files contained in the 167_disk zip file including the directory to which the file automatically extracts them 2 27 DK4000 C167 USER MANUAL Table 1 Listing of the files and destinations in 167_disk zip 7 rel 71 meer E 71 _ Freep 166c10demo zip contains all c level code files demo10 h86 alternate firmware to load to demonstrate IAP late breaking information Note 1 Hex file carries the extension h86 from the Keil tools 2 Infineon Dave 2 0 cd was used in these projects 3 Keil compiler version is 4 03 or later See readme file for particulars 3 27 DK4000 C167 USER MANUAL DETAILED DESCRIPTIONS Figure 1 DK4000 Develo
14. connector and pinout for the FlashLINK programmer adapter The connector scheme on the FlashLink adapter can accept a standard 14 pin ribbon connector 2 rows of 7 pins on 0 1 centers stan dard keying or any other user specific connector that can slide onto 0 025 square posts The pinout for the FlashLINK adapter connector is shown in the following figure A standard ribbon cable is good way to quickly connect to the target circuit board If a ribbon cable is used then the receiving connector on the target system should be the same connector type with the same pinout as the FlashLINK adapter shown in the following figure Keep in mind that the JTAG signal TDI is sourced from the FlashLINK adapter and should be routed on the target circuit card so that it connects to the TDI input pin of the PSD device Although the name TDI infers Data In by convention it is an output from FlashLINK and an input to the PSD device Also keep in mind that the JTAG signal TDO is an input re ceived by the FlashLINK adapter and is sourced by the PSD device on the TDO output pin Figure 15 Pinout for FlashLINK Adapter and Target System WSi ENHANCED JTAG ISP CONNECTOR DEFINITION VIEW LOOKING INTO FACE OF SHROUDED MALE CONNECTOR IER 0 025 POSTS ON 0 1 CENTERS TERR TDO 12 B B Connector reference Molex 70247 1401 GND TCK Recommended ribbon cable for quick 10 8 Bo connection of FlashLink adapter to end product GND TMS Samtec HCSD 07
15. d the display PSD memory and chip selects and the UART channel single character only on receive and transmit This confirms func tionality and is used as a production test The following list is a detailed description of the viewable LCD screens Invocation banner software version Display execution source boot area or main Flash memory Motherboard LED test PSD RAM test 57 13 27 DK4000 C167 USER MANUAL Code Copy Executing boot code is copied to main Flash memory block FSO BOOT gt FLASH Displays Flash memory ID and does erase of FSO prior to the copy operation UART test waiting for host to send 0 development board reply is a 1 baud rate is19200 with 8 data bits no parity and one stop bit This software also includes provision for external SRAM test in evaltest c but this code is not utilized at this time since the site is unpopulated If this code is used be aware that the appropriate buscon must be set for 8 bit demuxed bus After this code has run one time a copy of the executing code exists in the Flash memory area FSx The system can run from this code copy by placing the dip switch in the appropriate configuration as described in the Memory Swapping in the PSD section of this document Demotl This is a simple program that displays the following text on the LCD display The intent is to show a minimal level of functionality No UART support is provided 14 27 DK40
16. face IEEE 1149 1 compliant is included on the PSD enabling the entire device to be rapidly programmed while soldered to the circuit board Main Flash memory Secondary Boot Flash memory the PLD and all configuration areas This requires no MCU participa tion so the PSD can be programmed or reprogrammed any time anywhere even while completely blank The MCU is completely bypassed In Application Programming IAP Since two independent Flash memory arrays are included in the PSD the MCU can ex ecute code from one memory while erasing and programming the other Robust product firmware updates in the field are pos sible over any communication channel a few examples are CAN Ethernet UART J1850 using this unique architecture For IAP all code is updated through the MCU HARDWARE m PSD4000 Flash PSD Programmable System Device see www st com psd for data sheet PSD4135G2 4Mbit Main Flash memory 512Kx8 256Kbit Boot Flash memory 32 8 64Kbit SRAM 8Kx8 1 27 DK4000 C167 USER MANUAL Eval Demo Board with C167CR or other MCU LCD Display JTAG and UART ports for ISP IAP FlashLINK JTAG ISP Programmer uses PC s parallel port Straight through serial cable Male Female Power Supply SOFTWARE To ensure you have the latest versions check the website often PSDsoft Express Point and Click Windows programming development software This will install to it s own directory MCU Selection
17. flow for this critical area is guaranteed to occur properly These steps involve the absolute location of certain modules within the base application and the new IAP appli cation Locating these modules is accomplished using linker controls With this framework booting from one application to another is EASY REFERENCES IEEE Std 1149 1 1990 IEEE Test Access Port and Boundary Scan Architecture Flashlink User Manual included in the Appendix of this document AN1153 Application note JTAG Information AN1426 Application note Design Guide PSDsoft Express and PSD4135G2 12 27 DK4000 C167 USER MANUAL APPENDIX Appendix A Jumper configuration on DK4000 Default position Description shown by dotted Board position line JP1 Measure PSD current Upper center JP3 Internal external power supply Internal power supply Lower right 9v battery connector None no jumper Lower right Figure 11 Assembly Drawing with default jumper positions 1 serial port PSD Meas Power Supply Int Ext 9o o LCD Contrast battery connection 0000 LCD Display d7 14 OOOO Power on indicator 105339 Appendix Software functional description Hwtest This code exercises all components of the development boar
18. in the 167 Design Overview section of this document 2 PSDsoft Express project a16xbhe ini 3 The file source code included to see how the executing code was configured Notice An additional code bundle will be posted on the web in the future to cover the IAP functionality Please go to www st com psd and select Development Tools and scroll down to DK4000 Latest software and manual can then be downloaded USING DK4000 AS A DEVELOPMENT PLATFORM FOR C167CR USERS Concept The ST DK4000 Development Board provides the following capabilities Demonstrate design concepts early optimizing time to market Jump start user application with proven framework hardware and software Substitute for user target system until target prototypes are available m Gives instant platform for testing ISP and IAP demonstration Allows programming the PSD using included Flashlink cable Downloading to the Development Board Executable code can be downloaded to the Development Board two different ways via the JTAG ISP or via the UART IAP This manual only describes the ISP capabilities at this time The IAP capabilities will be supported in the future using PSDload available on the website at www st com psd JTAG ISP The PSD4000 series JTAG interface provides the capability of programming all memory areas within the PSD PLD configuration MAIN and secondary Flash memories This interface can also be used to pro gram a c
19. iptions for FlashLINK adapter assembly DESCRIPTION JTAG IEEE 1149 1 Flashlink is Signal EJTAG ST EHANCED JTAG jew EA EA TERR EJTAG programming error optional Note 1 Bold signals are required connections 2 all signal grounds are connected inside FlashLink adapter 3 OC open collector pulled up to Vcc inside FlashLink adapter 4 Not supported initially by PSDsoft 5 The target device must supply Vcc to the FlashLink Adapter 2 7 to 5 5 VDC 15mA max 5 5V All 14 signals may not be needed for a given application Here s how they break down 6 Core signals that must be connected TDI TDO TMS TCK Vcc and GND 2 Optional signals for enhanced ISP TSTAT TERR Optional signal to control multiplexing of the JTAG signals JEN Recommended signal to allow FlashLINK to reset target system during and after ISP RST 1 Optional IEEE 1149 1 signal for JTAG chain reset TRST 1 Optional generic control signal from FlashLink to target system CNTL 2 Two additional ground lines to help reduce EMI if a ribbon cable is used These ground lines sandwich the TCK signal in the ribbon cable These lines are not needed for use with the flying lead cable That is why the flying lead cable has only 12 of 14 wires populated 1 1 20 27 DK4000 C167 USER MANUAL FlashLINK pinouts There is no standard JTAG connector Each manufacturer differs ST has a spe cific
20. lowing electronic mail addresses apps psd st com for application support ask memory st com for general enquiries Please remember to include your name company location telephone number and fax number Information furnished is believed to be accurate and reliable However STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners 2001 STMicroelectronics All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia Brazil China Finland France Germany Hong Kong India Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom U S A www st com 57 27127
21. nning of hwtest obj 0x0C000 0 0 000 0 08000 0 04000 167 System Area CSIOP PSD buscon1 LCD buscon1 PSD RAM 4Kx16 PSD Boot area 500010 1 message boot area Segment 0 OxOBFOO 0 0 00 Ox1FFFF 0x10000 Flash PSD FSO 32Kx16 Copy of code from csbooto 1 message main flash Segment 1 105707 Notice in the above figure the element denoted as message in each of the code areas This element is displayed as the second LCD screen to show the source of execution For normal boot the second LCD Screen shows executing from BOOT area The message exists in a fixed location in the code and is read from this location and copied to the LCD at boot up When the code copy is performed a different message is inserted into the same fixed location based on the destination of the copy as shown in FSO When this version of the code is executed the message is displayed executing from MAIN FLASH This method yields a single unambiguous confirmation of the execution source which is very convenient for demonstrating memory swapping operations 10 27 DK4000 C167 USER MANUAL Now let s boot from the other memory to demonstrate the swapping capability of the PSD Place the dip switch in the following position and press the reset button You should see the execution source annunciated to the display booting from MAIN
22. ompletely blank component as JTAG is enabled as the default PSD state See Application Note 54 54 for further description of the JTAG interface on our CD or our website at www st com psd The LCD will be non operational during JTAG ISP since the MCU is not operating During this interval the PSD is not connected to the MCU bus To restrain the MCU during this interval the JTAG interface contains a signal RST that is connected to the MCU reset pin ST provides a FlashLINK programmer to facilitate the JTAG programming operation The FlashLINK pro grammer connects the PC parallel port to the Eval Board JTAG header and is driven by PSDsoft Express the PSD development tool 167 DESIGN OVERVIEW The following figure depicts how the memory is allocated in this project for the hwtest obj Hwtest obj uses the segmented mode of the C167CR The demo1 project uses the non segmented mode of the C167CR The C167CR contains a large addressable memory area that is partitioned into segments of 64k bytes each Even though many memory segments exist in the C167CR only segments 0 and 1 are used in this 8 27 DK4000 C167 USER MANUAL project The configuration of the C167CR is controlled by two registers that are written at system startup syscon and These registers handle the mechanism for different bus width peripherals in the C167CR as well as many other items See the C167CR user manual for details Additional areas can
23. ory to the other After the reset signal is deasserted the MCU is executing from the csboot area normally This continues until the exe_src_a bit is written moving FSO into the execution location 0 0 Ox3FFF At this same time csboot area is for all practical purposes gone from the system memory map At this point the MCU is generating the next address from the instruction received from the csboot area However the next instruction will come from the FSO area This next instruction fetch must be appropriate to maintain the program flow That is the next instruction must be received by the MCU on an instruction boundary and be appropriate for the program flow In addition any issues with the stack and stack pointer must be resolved so program flow can continue subroutine return addresses temporary variables etc Pipelining operations can result in execution from the pipeline instead of the new memory but the pipeline will continue to be filled from the new memory The method we ve used to ensure correct operation is to place identical code at identical locations in both applications through the point of the swap After the point of the swap the code bundles can diverge with out problems While this result is inherently ensured in a code copy scenario like hwtest obj it s not so automatic when the applications are different such as exists in a true IAP scenario Creating your own IAP code bundle A few easy steps can ensure that program
24. pment Board JTAG Programming port Serial Port Provision for chaining port ST10 or E PSD4135G2 Infineon C167CR i SRAM provision Power switch Expansion 5 LED s Ports a TT DC Power Input 2x16 character Reset Button LCD contrast 4 position LCD display adjustment DIP switch The following features are included in the development board and shown graphically in the above figure Display A two line by 16 character LCD display is included on the Development Board Power switch UART Serial Port female Connected to MCU serial port used for In Application Programming IAP Infineon 167 or other MCU PSD4000 software The PSD4000 is programmed with C167CR demonstration code User can program alternative programs via JTAG ISP JTAG programming Port Used in conjunction with FlashLINK programmer for ISP Reset Button For resetting the MCU and PSD Pads for additional SRAM The resident PSD4000 contains 8KB SRAM This site is for additional SRAM OTHER BOARD FEATURES Other features of the DK4000 board are listed below These elements unpopulated to provide lowest cost to the user 4 27 Provision for C167CR boot elements are provided with JP5 6 and 7 Provision for chaining JTAG connector is provided in P2 and JP2 Provision for C167CR OWE control is provided in JP8 Provision for an analog Vref input is provided in JP9 DK4000 C167 USER MANUAL Provision for off e
25. s Click here to perform specified JTAG ISP operation Execute Step 3 Save or retrieve JTAG ISP setup Specify folder and filename to save the setup of this JTAG ISP session or retrieve a previous session Save Select folder and file Browse Log Mode Click to record session infomation in the loa file PSD JTAG ISP Operations PSDsoft Express 6 12 Copyright 2000 Waferscale Integration Inc All Rights Reserved DATE 05 04 2000 TIME 08 14 01 fa Hw Setup Reset Target Close A105709 f In Step 1 browse to find the obj file shown in the above figure g In select device box choose the PSD4000 device you have installed on the board h In step 3 select the operation of Program Click execute i Observe in the lower pane the JTAG activities that occur while programming your device j Watch the display When the download is completed as indicated in the log window push the reset but ton on the Development Board The displays below will sequence one time and then operation will stop Figure 7 Eval Board Displays for IAP obj 1577 7 27 DK4000 C167 USER MANUAL If you cycle power to the board you will see that the display will resequence confirming that the program and all configuration information are stored in the PSD s non volatile Flash memory k For better understanding of the program you may want to examine the following references 1 System memory map
26. stor smt 820 1 8 watt rec225 1002 samtec con225 3003 samtec rec225 3002 samtec 1 1 1 745988 4 con232 0001 ic rs232 connector female 9 amp Sw102 0001 reset switch momentary bourns swdip0004 4 position dip switch side actuated cts 195 4mst sw101 0002 on off switch digikey EG1906 ND tr101 0001 class 2 transformer 500ma female dpd090050 p 5 103 0001 connector for ps male digikey pj 202a 79149 1 1 1 E DK4000 C167 USER MANUAL Qua Generic Part er con104 2007 _ connectors em emm 01 L D LL 13 16 P16 225 1014 pirisinglerihine co nnestorr samtec dw 14 17 T S 250 LL spacer display See jenem Jer essen 18 27 DK4000 C167 USER MANUAL Appendix D FlashLINK Users Manual Features Allows PC parallel port to communicate with PSD4000 via PSDsoft Express Provides interface medium for JTAG communications Supports basic IEEE 1149 1 JTAG signals TCK TMS TDI TDO Supports additional signals to enhance download speed ITERR TSTAT Can be used for programming and or testing Wide power supply range of 2 7 to 5 5V Pinout independent with target side flying leads Convenient desktop packaging allows varying applications desk lab or production m Synchronous JTAG interface allows speeds as fast as pc can drive Overview FlashLINK is a hardware interf
27. t can be anywhere the only important element is that it is contained in the PLD equations as shown above and accessible by the MCU Control of this bit is via a board mounted dip switch The power up sequence is as follows 1 Execute start167 a66 2 Read the dip switch 57 11 27 DK4000 C167 USER MANUAL 3 Write the dip switch setting into the PSD PAGE register some positioning is done prior to the write Once the PAGE register write operation has completed the next instruction is fetched from the new mem ory location FSO This same sequence of events occurs every time power is applied to the board Since the PAGE register is always 00 at power up the software always executes steps and b from the boot area Then based on the dip switch selection the code will either stay in the boot area or jump to the main Flash memory area What really happens There is a subtlety involved in the transfer of execution described above This subtlety is because the MCU really doesn t know the source of the instruction bytes boot area or main Flash memory All the MCU knows is that valid instructions on valid address boundaries are presented on the bus when the MCU needs them Then the MCU executes the instruction and generates the next address The key element involved is the generation of the address by the MCU To understand this critical transfer of control let s examine the instruction by instruction transition from one mem
28. xpansion is provided by board connectors suitable for 0 025 square posts Provision for 9v battery input is provided near power connector solder pads only Step By Step Instructions for ISP Programming a Install PSDsoft Express on your PC running Windows 95 98 NT 2000 Check web for latest version b Plug the FlashLINK Programmer into your PC s parallel port and plug in the ribbon cable to the JTAG port on the eval board for help see the Appendix C FlashLINK manual c Plug in power supply and turn on power An LCD contrast control is provided as R11 The typical setting is near the counterclockwise stop d Run PSDsoft Express Here is the initial screen if no project was open Figure 2 Opening screen upon PSDsoft Express invocation PSDsoft Specify Project x Choose one Create a new project Open an existing project Cancel Use cancel at this point since all we need to do is program the PSD with an existing demonstration obj and there is no need to create a new project Later in the Using the DK4000 as a development platform a further tutorial is given on using PSDsoft Express with the Eval Board for development Figure 3 Invocation reminder screen PSDsoft Design Environment N Use Project Open or Project New to select or create a project file e In the Design Flow shown below click on the ST JTAG ISP button Bottom row of boxes left side 1577 5 27
Download Pdf Manuals
Related Search