RX63N Group, RX631 Group
Contents
1. RX63N Group RX631 Group 5 4 Constants Table 5 3 lists the constants used in the sample code Table 5 3 Constants Used in the Sample Code Constant Name Clock Synchronous GClc Communication Using the DMACA Setting Value MASTER 00h Set value of the SCI9 SCR CKE 1 0 bits Internal clock master SLAVE 02h Set value of the SCI9 SCR CKE 1 0 bits External clock slave SCI_CLK MASTER Set value of the SCI9 SCR CKE 1 0 bits Master mode selected BUF_SIZE 256 Size of the transmission and reception data storage areas DMAC_CNT BUF_SIZE DMAC transfer count SW_ON 1 Switch input on state SW_OFF 0 Switch input off state 5 5 Variable Table 5 4 lists the global variables Table 5 4 Global Variables unsigned char Variable Name rcv_end_flag Contents Reception complete flag 0 Reception in progress 1 Reception complete Function Used main Excep_DMAC_DMACOI Excep_SCI9_TEI9 unsigned char unsigned char trn_end_flag rcvbuf BUF_ SIZE Transmission complete flag 0 Transmission in progress 1 Transmission complete Receive data storage area main Excep_DMAC_DMACOI Excep_SCI9_TEI9 dmaco0_ init sci9_ start unsigned char trnbuf BUF_SIZE RO1AN1064EJ0100 Rev 1 00 Apr 05 2013 Transmit data storage area RENESAS main dmac1_init sci9_start Page 12 of 26 RX63N Group RX631 Group 5 6 Functions Table 5 5 lists the functions used in the sampl2. RX63N Group RX631 Group Clock Synchronous SCic Communication Using the DMACA 5 8 2 Port Initialization Figure 5 4 shows the flowchart for the port initialization PORTB PODR register eer porreulpat cats B7 bite 1 PB7 TXD9 High level output S PORTO PDR register Ser pow direction B7 bit 0 P07 IRQ15 Input PORTB PDR register B5 bit 0 PB5 SCK9 Input B6 bit lt 0 PB6 RXD9 Input B7 bit 1 PB7 TXD9 Output PORT3 PMR register B2 bit lt 0 P07 IRQ15 Used as a general purpose UO port PORTB PMR register B5 bit lt 0 PB5 SCK9 Used as a general purpose UO port B6 bit 0 PB6 RXD9 Used as a general purpose UO port B7 bit 0 PB7 TXD9 Used as a general purpose UO port Figure 5 4 Port Initialization RO1AN1064EJ0100 Rev 1 00 Page 18 of 26 Apr 05 2013 RENESAS RX63N Group RX631 Group Clock Synchronous SCic Communication Using the DMACA 5 8 3 Peripheral Function Initialization Figure 5 5 shows the flowchart for the peripheral function initialization peripheral_init Gs PRCR register lt A502h Enable writing to related registers PRC1 bit 1 Clear module stop state MSTPCRC register MSTPC26 bit lt 0 Clears the SCI9 module stop state cl dule stop stat MSTPCRA register SA ee ene MSTPA28 bit lt 0 Clears the DMAC module stop state PRCR register lt A500h Disable writing to related registers PRC1 bit 0 Initialize SCI9 sci9_init Initialize DMACO dmac0_init Initialize DM
3. SM 1 0 bits 10b Increment DMAC1 DMTMD register lt 0001h Set transfer mode DCTG 1 0 bits 01b Peripheral module interrupts SZ 1 0 bits 00b 8 bit transfers MD 1 0 bits 00b Normal transfers DMAC1 DMCSL register lt 00h Set up clear as the start factor DISEL bit 0 Clears to 0 the interrupt flag that was the start factor at transfer start Set transfer source address DMAC1 DMSAR register lt The address of the trnbuf 0 Set transfer destination address DMAC1 DMDAR register lt The address of the SCI9 TDR register Set transfer count DMAC1 DMCRA register lt DMAC_CNT Set interrupt priority level EE PEP y IPR 3 0 bits 0001b Sets the DMAC11 interrupts to priority level 1 A DMAC1 DMINT register 10h Enable transfer complete interrupt DTIE bit 1 Enable DMAC11 interrupt IER18 register requests IEN7 bit lt 1 DMAC1 DMCNT register lt 01h Enable DMA transfers DTE bit 1 Figure 5 8 DMAC1 Initialization RO1AN1064EJ0100 Rev 1 00 Page 22 of 26 Apr 05 2013 RENESAS RX63N Group RX631 Group Clock Synchronous SCic Communication Using the DMACA 5 8 7 SCI9 Transmission and Reception Start Figure 5 9 shows the flowchart for the SCI9 transmission and reception start SC start Set e destination DMACO DMDAR register lt The address of the revbuf 0 Set DMACO transfer count DMACO0 DMCRA register lt DMAC_CNT DMACO DMCNT register lt 01h Enable DMA transfers DTE bit 1 Set DM
4. Receive error interrupt ERI9 DMACO e Start factor RXI9 interrupt request The IR flag for the RX19 interrupt is cleared to 0 at the start of transfer e Transfer source address SCI9 RDR register e Transfer source address update mode Fixed address e Transfer destination address RAM start address of the receive data storage area e Transfer destination address update mode Increment e Transfer mode Normal mode e Data transfer size 8 bits e Transfer count 256 transfers e Interrupts used Transfer complete interrupt DMACOI RO1AN1064EJ0100 Rev 1 00 Page 6 of 26 Apr 05 2013 RENESAS RX63N Group RX631 Group Clock Synchronous SCic Communication Using the DMACA DMACT e Start factor TXI9 interrupt request The IR flag for the TXI9 interrupt is cleared to 0 at the start of transfer e Transfer source address RAM start address of the transmit data storage area e Transfer source address update mode Increment e Transfer destination address SCI9 TDR register e Transfer destination address update mode Fixed address e Transfer mode Normal mode e Data transfer size 8 bits e Transfer count 256 transfers e Interrupts used Transfer complete interrupt DMAC1T IRQ15 input pin e Detection method Falling edge detection e Digital filter Enabled sampling clock PCLKB 8 e Interrupts used None 5 1 Operational Overview 5 1 1 Transmit Operation 1 Initialization After initialization the sample code waits for a transmit receive s
5. Set transfer mode DCTG 1 0 bits 01b Peripheral module interrupts SZ 1 0 bits 00b 8 bit transfers MD 1 0 bits 00b Normal transfers DMACO DMCSL register lt 00h Set up clear as the start factor DISEL bit 0 Clears to 0 the interrupt flag that was the start factor at transfer start Set transfer source address DMACO DMSAR register lt The address of the SCI9 RDR register DMACO DMDAR register lt The address of the rcvbuf 0 DMACO DMCRA register DMAC_CNT IPR 3 0 bits lt 0001b Sets the DMACOI interrupts to priority level 1 eer register lt 10h Enable DMACOI interrupt IER18 register requests IEN6 bit lt 1 DMACO DMCNT register lt 01h Enable DMA transfers DTE bit 1 Figure 5 7 DMACO Initialization RO1AN1064EJ0100 Rev 1 00 Page 21 of 26 Apr 05 2013 RENESAS RX63N Group RX631 Group Clock Synchronous SCic Communication Using the DMACA 5 8 6 DMAC1 Initialization Figure 5 8 shows the flowchart for the DMAC1 initialization Disable DMAC1I interrupt IER18 register requests IEN7 bit lt 0 DMAC1 DMCNT register lt 00h Disable DMA transfers DTE bit 0 DMRSR1 register lt 242 Set up start factor DMRS 7 0 bits 11011101b Sets the DMAC1 start request TXI9 vector number Set add i d DMAC1 DMAMD register lt 8000h DARA 4 0 bits 00000b Does not set up an extended repeat area DM 1 0 bits 00b Fixed address SARA 4 0 bits 00000b Does not set up an extended repeat area
6. bit lt 0 SCI9 SCR register RIE bit 0 IR241 register IR flag lt 0 rcv_end_flag lt 1 Reads out trn_end_fig Disables SCI9 RXI9 interrupt requests Disables RXI and ERI interrupt requests No SCI9 RXI9 interrupt requests Reception complete 0 Transmission in progress 1 Transmission complete Yes PORTB PMR register Set UO port functions B7 bit lt 0 SCI9 SCR register SCI9 SCR register amp 03h TEIE bit 0 Disables TEI interrupt requests RE bit 0 Disables serial reception operation TE bit 0 Disables serial transmission operation RIE bit 0 Disables RXI and ERI interrupt requests TIE bit 0 Disables TXI interrupt requests PB7 TXD9 Used as general purpose UO ports Disable SCI9 transmission and reception Note 1 After writing a value to the RIE bit verify that the written value can be read Figure 5 10 DMACO Transfer Complete Interrupt Handler 5 8 9 DMAC1 Transfer Complete Interrupt Handler Figure 5 11 shows the flowchart for the DMAC1 transfer complete interrupt handler Excep_DMAC_DMAC1I Disable TXI9 interrupt request IER1E register IEN2 bit lt 0 Disables SCI9 TXI9 interrupt requests SCI9 SCR register x1 Disable interrupt requests TIE bite 0 Disables TXI interrupt requests IR242 register Clear TXI9 interrupt request IR flag 0 No SCI9 TXI9 interrupt requests IER1E register IEN3 bit lt 1 Enab
7. data output from TXD9 pin Transmission of 256 bytes Figure 5 1 Transmission Operation Timing Chart RO1AN1064EJ0100 Rev 1 00 Page 8 of 26 Apr 05 2013 RENESAS RX63N Group RX631 Group Clock Synchronous SCic Communication Using the DMACA 5 1 2 Reception Operation 1 Initialization After initialization the sample code waits for a transmit receive start switch input 2 Transmit receive start switch input detection When a transmit receive start switch input is detected the IRQ15 interrupt IR flag is set to 0 After verifying that transmission and reception have completed by checking the transmission complete flag and the reception complete flag the reception complete flag is set to 0 reception in progress The DMACO transfer destination address and transfer count are set and DMA transfers are enabled The SCI9 SCR TEIE TIE RIE TE and RE bits are all set to 1 at the same time to enable transmission and reception operations and the RXI9 interrupt 3 Data reception completion When reception of the first byte of data completes the data is transferred from the SCI9 RSR register to the SCI9 RDR register and the RXI9 interrupt IR flag is set to 1 4 Data transfer start DMACO is started by the RXI9 interrupt request and the RXI9 interrupt IR flag is cleared to 0 The first byte of receive data is transferred from the SCI9 RDR register to the RAM receive data storage area 5 DMACOI interrupt When the 256th data transfer c
8. function starts SCI9 transmission and reception operations when a transmit receive start switch input is detected None None Port initialization None void port_init void Initializes the ports None None Stop processing for active peripheral functions after a reset r_init_stop_module h void R_INIT_StopModule void Configures the setting to enter the module stop state None None Transition to the module stop state is not performed in the sample code Refer to the RX63N Group RX631 Group Initial Setting Rev 1 00 application note for details of this function R_INIT_NonExistentPort Outline Header Declaration Description Arguments Return Value Remarks Nonexistent port initialization r_init_non_existent_port h void R_INIT_NonExistentPort void Initializes port direction registers for ports that does not exist in products with less than 176 pins None None The number of pins in the sample code is set for the 176 pin package PIN_SIZE 1 76 After this function is called when writing in byte units to the PDR registers or PODR registers which have nonexistent ports set the corresponding bits for nonexistent ports as follows set the I O select bits in the PDR registers to 1 and set the output data store bits in the PODR registers to 0 Refer to the RX63N Group RX631 Group Initial Setting Rev 1 00 application note for details of this function RO1AN1064EJ0100 Rev 1 00 Apr 05 2013 Page 14 of 26 RE
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11. AC t ee source DMAC1 DMSAR register The address of the trnbuf 0 Set DMAC1 transfer count DMAC1 DMCRA register lt DMAC_CNT DMAC1 DMCNT register lt 01h Enable DMA transfers DTE bit 1 Start SCI9 transmission and SCI9 SCR register SCI9 SCR register F4h reception TEIE bit 1 Enables TEI interrupt requests RE bit 1 Enables serial reception operation TE bit 1 Enables serial transmission operation RIE bit 1 Enables RXI and ERI interrupt requests TIE bit 1 Enables TXI interrupt requests Set up I O port functions SEET P H B7 bit lt 1 PB7 TXD9 Used as a peripheral function pin 7 GEN12 register Enao e ERIS imterruptireguesi ENG bit lt 1 Enables SCI9 ERI9 GROUP12 interrupt requests Enable GROUP12 interrupt IEROE register request IEN2 bit lt 1 Enables ICU GROUP12 SCI9 ERIQ interrupt requests i IER1E register EE IEN1 bit lt 1 Enables SCI9 RXI9 interrupt requests IER1E register Ena E tore mca neues IEN2 bit lt 1 Enables SCI9 TXI9 interrupt requests return Figure 5 9 SCI9 Transmission and Reception Start RO1AN1064EJ0100 Rev 1 00 Page 23 of 26 Apr 05 2013 RENESAS RX63N Group RX631 Group Clock Synchronous SClc Communication Using the DMACA 5 8 8 DMACO Transfer Complete Interrupt Handler Figure 5 10 shows the flowchart for the DMACO transfer complete interrupt handler Set reception complete flag Transmission complete IER1E register IEN1
12. AC1 dmact_init DMAST register 01h Enable DMAC start DMST bit 1 A IERO9 register Disable IRQ15 interrupt request IEN7 bit lt 0 OTET IRQFLTE1 register Disable IRQ15 digital filter FLTEN15 bit lt 0 IRQFLTC1 register Set up IRQ15 sampling clock FCLKSEL15 1 0 bits 01b PCLKB 8 PWPR register Set IRQ15 port BOWI bit 0 Enables writing the PFSWE bit PWPR register PFSWE bit lt 1 Enables writing the PFS register PO7PFS register ISEL bit lt 1 Sets up use as the IRQ15 input pin PWPR register PFSWE bit lt 0 Disables writing the PFS register PWPR register BOWI bit lt 1 Disables writing the PFSWE bit IRQCR15 register lt 04h IRQMD 1 0 bits 01b Falling edge Set IRQ15 detection method IR079 register Clear IRQ15 interrupt request IR flag 0 IRQFLTE1 register Enable IRQ15 digital filter FLTEN15 bit lt 1 return Figure 5 5 Peripheral Function Initialization R01AN1064EJ0100 Rev 1 00 Page 19 of 26 Apr 05 2013 RENESAS RX63N Group RX631 Group Clock Synchronous SCilc Communication Using the DMACA 5 8 4 SCI9 Initialization Figure 5 6 shows the flowchart for the SCI9 initialization sci9_init Disable SCI9 interrupt requests EROE register IEN2 bit lt 0 Disables ICU GROUP12 SCI9 ERIQ interrupt requests GEN12 register ENG bit 0 Disables SCI9 ERI9 GROUP1 2 interrupt requests IER1E register IEN1 bit lt 0 Disables SCI9 RXI9 interrupt requests IEN2
13. NESAS RX63N Group RX631 Group R_INIT_Clock Outline Header Declaration Description Arguments Return Value Remarks peripheral_init Outline Header Declaration Description Arguments Return Value sci9_ init Outline Header Declaration Description Arguments Return Value dmaco0_init Outline Header Declaration Description Arguments Return Value dmaci1_init Outline Header Declaration Description Arguments Return Value RO1AN1064EJ0100 Rev 1 00 Apr 05 2013 Clock Synchronous SClc Communication Using the DMACA Clock initialization r_init_clock h void R_INIT_Clock void Initializes the clock None None The sample code selects processing which uses PLL as the system clock without using the sub clock Refer to the RX63N Group RX631 Group Initial Setting Rev 1 00 application note for details of this function Peripheral function initialization None void peripheral_init void Initializes the peripheral functions used None None SCI9 initialization None void sci9_init void Initializes SCI9 None None DMACO initialization None void dmac0_init void Initializes DMACO None None DMAC1 initialization None void dmac1_init void Initializes DMAC1 None None Page 15 of 26 RENESAS RX63N Group RX631 Group sci9_ start Outline Header Declaration Description Arguments Return Value Clock Synchronous GClc Communication Using the DMACA Starts SCI9 transmission an
14. TDR register is not updated when the last bit of the 256th byte is transmitted a TEI9 interrupt request is generated During TEI9 interrupt handling the TEI9 interrupt is disabled and the transmission complete flag is set to 1 transmission complete If the reception complete flag is 1 reception complete transmission and reception are disabled Execution is then repeated from step 2 above Figure 5 1 shows the timing chart for the transmission operation RO1AN1064EJ0100 Rev 1 00 Page 7 of 26 Apr 05 2013 RENESAS RX63N Group RX631 Group Clock Synchronous SCic Communication Using the DMACA 3 I i H f I I I I i P 1 l H f I 1 I H I i I I H I H 1 L I l I f 1 I 1 A I 1 L 1 1 I H f I I I L D 1 1 1 I U i H I Li I 1 H 1 b o 4 4 amp Transmit receive start switch input pin 2 1 1 i 1 1 1 IRQ15 interrupt IR flag Transmission complete flag SCI9 SCR TE bit SCI9 SCR TIE bit SCI9 SCR TEIE bit ee ee eee elen ee EEN Set to 0 after 256 A transfers complete DMAC1 DMCNT DTE bit sles Za Set to 0 by the acceptance of the interrupt DMAC11 interrupt IR flag a eis TEI interrupt IEN bit TEIQ interrupt IR flag TXIQ interrupt IEN bit tan Not set to 1 here because TXI9 interrupt IR flag the SCI9 SCR TIE bit is 0 RAM gt TDR DMA transfer SCI9 TDR register SCI9 TSR register Transmit
15. TEIE bit 0 Disables TEI interrupt requests RE bit 0 Disables serial reception operation TE bit 0 Disables serial transmission operation RIE bit 0 Disables RXI and ERI interrupt requests TIE bit 0 Disables TXI interrupt requests Check IR flag Reads the IR243 register IR flag 0 No interrupt request occurred 1 An interrupt request occurred return Note 1 After writing a value to the TEIE bit verify that the written value can be read Figure 5 12 SCI9 Transmission Complete Interrupt 5 8 11 Handler Group 12 Interrupt Handler SCI9 Reception Error Interrupt Figure 5 13 shows the flowchart for the Group 12 interrupt handler SCI9 reception error interrupt Excep_ICU_GROUP12 Handle SCI9 reception error This sample code does not perform the SCI9 receive error handling it simply executes an infinite loop Add a program if required Figure 5 13 Group 12 Interrupt Handler SCI9 Reception Error Interrupt RO1AN1064EJ0100 Rev 1 00 Apr 05 2013 Page 25 of 26 RENESAS RX63N Group RX631 Group Clock Synchronous SCic Communication Using the DMACA 6 Sample Code Sample code can be downloaded from the Renesas Electronics website 7 Reference Documents User s Manual Hardware RX63N Group RX631 Group User s Manual Hardware Rev 1 50 ROLUH0041EJ The latest version can be downloaded from the Renesas Electronics website Technical Update Technical News The latest inform
16. When operating in slave mode if the interrupts used in this application are forced to wait for extended periods due to for example the handling of other interrupts this code may not operate correctly 5 2 File Composition Table 5 1 lists the files used in the sample code Files generated by the integrated development environment are not included in this table Table 5 1 Files Used in the Sample Code File Name Outline Remarks main c Main processing r_init_stop_module c Stops peripheral modules that are operating after a reset r_init_stop_module h Header file for r_init_stop_module c r_init_non_existent_port c Initialization for ports that do not exist r_init_non_existent_port h Header file for r_init_non_existent_port c r_init_clock c Initialization for clock r_init_clock h Header file for r_init_clock c 5 3 Option Setting Memory Table 5 2 lists the option setting memory configured in the sample code When necessary set a value suited to the user system Table 5 2 Option Setting Memory Configured in the Sample Code Symbol Address Setting Value Contents FFFF FF8Fh to FFFF FF8Ch FFFF FFFFh Stops IWDT after a reset Stops WDT after a reset FFFF FF8Bh to FFFF FF88h FFFF FFFFh Disables voltage monitoring 0 resets after a reset Disables HOCO oscillation after a reset FFFF FF83h to FFFF FF80h FFFF FFFFh Little endian RO1AN1064EJ0100 Rev 1 00 Page 11 of 26 Apr 05 2013 RENESAS
17. ansmission and reception SCI9 SMR register lt 81h formats CKS 1 0 bits 01b PCLKB 4 CM bit 1 Operates in clock synchronous mode SCI9 SCMR register lt F2h SMIF bit 0 Serial communications interface mode SINV bit 0 No transmit or receive data inversion SDIR bit 0 LSB first Set bit rate SCI9 BRR register lt 77 77 125 48 MHz 8x2x38400 bps 1 IPR241 register IPR 3 0 bits lt 0001b Sets the SCI9 RXI9 TXI9 and TEI9 interrupts to priority level 1 IPR114 register IPR 3 0 bits lt 0001b Sets the ICU GROUP12 SCI9 ERI9 interrupts to priority level 1 Set interrupt priority level Figure 5 6 SCI9 Initialization RO1AN1064EJ0100 Rev 1 00 Page 20 of 26 Apr 05 2013 RENESAS RX63N Group RX631 Group Clock Synchronous SCic Communication Using the DMACA 5 8 5 DMACO Initialization Figure 5 7 shows the flowchart for the DMACO initialization dmac0_init Disable DMACOI interrupt IER18 register requests IEN6 bit lt 0 DMACO DMCNT register lt 00h Disable DMA transfers DTE bit 0 DMRSRO register lt 241 Set p start factor DMRS 7 0 bits 11011100b Set the DMACO start request RXI9 vector number Set add g d DMACO DMAMD register 0080h sence in DARA 4 0 bits 00000b Does not set up an extended repeat area DM 1 0 bits 10b Increment SARA 4 0 bits 00000b Does not set up an extended repeat area SM 1 0 bits 00b Fixed address DMACO DMTMD register lt 0001h
18. ansmit data storage area to the TDR register and that data is transmitted If a reception completes an RXI9 interrupt request is generated and it functions as a DMACO transfer request DMACO is used to transfer the receive data to the receive data storage area When the transfer of transmit data has been performed 256 times a DMAC1 interrupt is generated This disables the TXI9 interrupt and enables the TEI9 interrupt When the transfer of receive data has been performed 256 times a DMACO interrupt is generated This disables the RXI9 interrupt and sets the reception complete flag to 1 If the transmission complete flag is 1 at this time SCI transmit receive operations are disabled When 256 bytes of transmissions and 256 bytes of receptions have been completed a TEI9 interrupt is generated This disables the TEI9 interrupt and sets the transmission complete flag to 1 If the reception complete flag is at this time SCI transmit receive operations are disabled The settings of the peripheral functions are listed below SCI9 e Communication mode Clock synchronous e SCK9 pin Internal clock output master e Clock source PCLKB 4 e Transfer rate 38 400 bps BRR register setting PCLKB 8x2x38 400 bps 1 e Transmit operation Enabled e Receive operation Enabled e Data transfer direction LSB first e Interrupts used Transmission complete interrupt TEI9 Transmit data empty interrupt TX19 Receive data full interrupt RXI9
19. ation can be downloaded from the Renesas Electronics website User s Manual Development Tools RX Family C C Compiler Package V 1 01 User s Manual Rev 1 00 R20UT0570EJ The latest version can be downloaded from the Renesas Electronics website Website and Support Renesas Electronics website http www renesas com Inquiries http www renesas com contact RO1AN1064EJ0100 Rev 1 00 Page 26 of 26 Apr 05 2013 RENESAS RX63N Group RX631 Group Application Note REVISION HISTORY Clock Synchronous SClc Communication Using the DMACA Description Date bn Page 1 00 aa Apr 05 2013 First edition issued All trademarks and registered trademarks are the property of their respective owners General Precautions in the Handling of MPU MCU Products The following usage notes are applicable to all MPU MCU products from Renesas For detailed usage notes on the products covered by this document refer to the relevant sections of the document as well as any technical updates that have been issued for the products 1 Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual The input pins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of LSI an associated shoot through current flows internally and malfunctions oc
20. bit lt 0 Disables SCI9 TXI9 interrupt requests IEN3 bit lt 0 Disables SCI9 TEI9 interrupt requests Disable transmission reception SCI9 SCR register lt 00h and interrupt requests TEIE bit 0 Disables TEI interrupt requests RE bit 0 Disables serial reception operation TE bit 0 Disables serial transmission operation RIE bit 0 Disables RXI and ERI interrupt requests TIE bit 0 Disables TXI interrupt requests Set up I O port functions PWPR register BOWI bit 0 Enables writing the PFSWE bit PWPR register PFSWE bit lt 1 Enables writing the PFS register PB5PFS register lt OAh PSEL 4 0 bits 01010b PB5 pin function selection SCK9 PB6PFS register lt OAh PSEL 4 0 bits 01010b PB6 pin function selection RXD9 PB7PFS register lt OAh PSEL 4 0 bits 01010b PB7 pin function selection TXD9 PWPR register PFSWE bit 0 Disables writing the PFS register PWPR register BOWI bit lt 1 Disables writing the PFSWE bit PORTB PMR register B5 bit 1 PB5 SCKQ Used as a peripheral function pin B6 bit 1 PB6 RXD9 Used as a peripheral function pin SCI9 SCR register CKE 1 0 bits lt SCK_CLK Internal clock The SCK9 pin is used as the clock output pin SCI9 SIMR1 register IICM bit lt 0 Serial interface mode SCI9 SPMR register CKPH bit 0 No clock phase delay CKPOL bit lt 0 No clock polarity inversion Select clock Set operating mode Set clock phase and polarity Set tr
21. ctronic equipment and industrial robots etc High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems and safety equipment etc Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury artificial life support devices or systems surgical implantations etc or may cause serious property damages nuclear reactor control systems military equipment etc You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application for which it is not intended Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics 6 You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges 7 Although Renesas Elec
22. cur due to the false recognition of the pin state as an input signal become possible Unused pins should be handled as described under Handling of Unused Pins in the manual 2 Processing at Power on The state of the product is undefined at the moment when power is supplied The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied In a finished product where the reset signal is applied to the external reset pin the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified 3 Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited The reserved addresses are provided for the possible future expansion of functions Do not access these addresses the correct operation of LSI is not guaranteed if they are accessed 4 Clock Signals After applying a reset only release the reset line after the operating clock signal has become stable When switching the clock signal during program execution wait until the target clock signal has stabilized When the clock signal is generated with an external resonator or from an external osc
23. d reception None void sci9_start void Starts the SCI9 transmission and reception operation None None Excep_DMAC_DMACOI Outline Header Declaration Description Arguments Return Value DMACO transfer complete interrupt handler None void Excep_DMAC_DMACOI void Disables the RXI9 interrupt and sets the reception complete flag If the transmission complete flag is 1 it disables SCI9 transmission and reception None None Excep_DMAC_DMAC1I Outline Header Declaration Description Arguments Return Value Excep_SCI9_TEI9 Outline Header Declaration Description Arguments Return Value Excep_ICU_GROUP12 Outline Header Declaration Description Arguments Return Value Remarks RO1AN1064EJ0100 Rev 1 00 Apr 05 2013 DMAC 1 transfer complete interrupt handler None void Excep_DMAC_DMAC1I void Disables the TXI9 interrupt and enables the TEI9 interrupt None None SCI9 transmission complete interrupt handler None void Excep_SCI9_TEI9 void Disables the TEI9 interrupt and sets the transmission complete flag If the reception complete flag is 1 it disables SCI9 transmission and reception None None Group 12 interrupt handler SCI9 receive error interrupt None void Excep_ICU_GROUP 12 void Handles group 12 interrupts SCI9 receive error interrupt None None This sample code does not perform the SCI9 receive error handling it simply executes an infinite loop Add a program if requ
24. e above application note are used by the sample code in this application note The revision number shown is the one used when this application note was written If there is a more recent version use the latest version Check the Renesas Electronics Corporation web site to verify and download the latest version RO1AN1064EJ0100 Rev 1 00 Apr 05 2013 Page 4 of 26 RENESAS RX63N Group RX631 Group Clock Synchronous SCic Communication Using the DMACA 4 Hardware 4 1 Hardware Configuration Figure 4 1 shows a connection example RX63N group Communication device Switch input SW input P07 IRQ15 Figure 4 1 Connection Example 4 2 Pins Used Table 4 1 lists the pins used and their functions Table 4 1 Pins Used and Their Functions Pin Name UO Function PO7 IRQ15 Input Transmit receive start switch input PB5 SCK9 Output SCI9 clock output PB6 RXD9 Input SCI9 receive data input PB7 TXD9 Output SCI9 transmit data output RO1AN1064EJ0100 Rev 1 00 Page 5 of 26 Apr 05 2013 RENESAS RX63N Group RX631 Group Clock Synchronous SCic Communication Using the DMACA 5 Software This sample code implements automatic SCI transmission and reception operations by using the DMAC When the transmit receive start switch is pressed a SCI transmit receive operation is started If transmission is enabled and a TXIO interrupt request occurs it functions as a DMAC1 transfer request DMAC1 transfers data in the tr
25. e code Table 5 5 Functions Used in the Sample Code Clock Synchronous GClc Communication Using the DMACA Function Name Outline main Main processing port_init Port initialization R_INIT_StopModule Stop processing for active peripheral functions after a reset R_INIT_NonExistentPort Nonexistent port initialization R_INIT_Clock Clock initialization peripheral_init Peripheral function initialization sci9_ init SCI9 initialization dmaco0_init DMACO initialization dmac1_init DMAC1 initialization sci9_start Starts SCI9 transmission and reception Excep_DMAC_DMACOI DMACO transfer complete interrupt handler Excep_DMAC_DMAC1I DMAC1 transfer complete interrupt handler Excep_SCI9_TEI9 Excep_ICU_GROUP12 RO1AN1064EJ0100 Rev 1 00 Apr 05 2013 SCI9 transmission complete interrupt handler Group 12 interrupt handler SCI9 receive error interrupt RENESAS Page 13 of 26 RX63N Group RX631 Group 5 7 Clock Synchronous SClc Communication Using the DMACA Function Specifications The following tables list the sample code function specifications main Outline Header Declaration Description Arguments Return Value port_init Outline Header Declaration Description Arguments Return Value R_INIT_StopModule Outline Header Declaration Description Arguments Return Value Remarks Main processing None void main void After initialization this
26. e in preparing the information included in this document but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein 3 Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others 4 You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration modification copy or otherwise misappropriation of Renesas Electronics product 5 Renesas Electronics products are classified according to the following two quality grades Standard and High Quality The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal ele
27. es 5 A2 PUSS EE 5 Bes SOMWALCS ee eege eege E E gleegdeue geesde eege Ze oe ET 6 5 1 Operational OVErView sireisas nn enika annia nadak daai atana aaa iaa ikia H SLL Transmit Operation eenegen aaa naa dE Gatien aA H 5 1 2 Reception Operation 9 5 2 File CGompeogiton EES EE A ee a AE Ea 11 5 3 Option Setting Memory cccccececeeeeece cece eeeeaeeeeeeeeeaeeeceaeeeeaaesaeeceaeeesaaesseaaesdeneeseaeessaeeseaeeeeenees 11 E Deele E 12 DO MV ANMADIC sn a E a S E S eege 12 OO nee 13 5 7 F ncton Specifications ssissnisiioiiiki aai ida 14 96 e Ve CN 17 5 8 1 Mam Steen e EE 17 D82 PO MmtthaliZAtlON saranin kainen EN ESN AAE R 18 5 8 3 Peripheral Function Iotalzaton ce eececeeeeceeeeeeeeeeeeeeeneeeeeeaeeeeeeaeeeeeeaeeeeeeaeeeeeenaeeeeneaa 19 5 84 SCIQMMTANZATION E 20 58 5 DMACO Ital ZatiOnny eege cabot seceteeeshesn ses shedtevadec cndukbadsdeeuslscs ened dhsveddecdehgedueeeseaccseas 21 586 DM Initialization sissandi a eaaa 22 5 8 7 SCI9 Transmission and Reception Start cceccccccecceeececeeeeeeeeeeeeeaeeseaeeseeeeeseaeeesaeeeeeeeees 23 5 8 8 DMACO Transfer Complete Interrupt Handler 24 5 8 9 DMAC1 Transfer Complete Interrupt Handler 24 5 8 10 SCI9 Transmission Complete Interrupt Handler 25 5 8 11 Group 12 Interrupt Handler SCI9 Reception Error Intern 25 le El EE 26 te Reterence DOCuments s essesi E didle detiae sd diastase ees 26 RO1AN1064EJ0100 Rev 1 00 Page 2 of 26 Apr 05 2013 RENESAS RX63N Group RX631 Gr
28. illator during a reset ensure that the reset line is only released after full stabilization of the clock signal Moreover when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress wait until the target clock signal is stable 5 Differences between Products Before changing from one product to another i e to a product with a different part number confirm that the change will not lead to problems The characteristics of an MPU or MCU in the same group but having a different part number may differ in terms of the internal memory capacity layout pattern and other factors which can affect the ranges of electrical characteristics such as characteristic values operating margins immunity to noise and amount of radiated noise When changing to a product with a different part number implement a system evaluation test for the given product Notice 1 Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information 2 Renesas Electronics has used reasonable car
29. ired Page 16 of 26 RENESAS RX63N Group RX631 Group Clock Synchronous SCic Communication Using the DMACA 5 8 Flowcharts 5 8 1 Main Processing Figure 5 3 shows the flowchart for the main processing Disable maskable interrupts flag lt 0 Initialize ports port_init After a reset stop operating peripheral functions R_INIT_StopModule Initialize nonexistent ports R_INIT_NonExistentPort Initialize clocks R_INIT_Clock Initialize peripheral functions peripheral_init Enable maskable interrupts I flag lt lt 1 Store transmit data in RAM trnbuf 0 to trnbuf 255 lt 00h to FFh Set transmission and reception trn_end_flag lt 1 Transmission complete complete flags rcv_end_flag lt 1 Reception complete W Transmit receive Reads the IRO79 register start switch input IR flag 0 No IRQ15 interrupt request 1 There is an IRQ15 interrupt request IR079 register Clear IRQ15 interrupt request IR flag lt 0 Wait for transmission and Reads the trn_end_flag 0 Transmission in progress reception complete 1 Transmission complete Reads the rcv_end_flag 0 Reception in progress 1 Reception complete Clear transmission and reception Im end Tag lt 0 Transmission in progress complete flags rcv_end_flag lt 0 Reception in progress Start SCI9 transmission and reception sci9_start Figure 5 3 Main Processing RO1AN1064EJ0100 Rev 1 00 Page 17 of 26 Apr 05 2013 RENESAS
30. le TEI9 interrupt requests Enables the SCI9 TEI9 interrupt request Note 1 After writing a value to the TIE bit verify that the written value can be read Figure 5 11 DMAC1 Transfer Complete Interrupt Handler RO1AN1064EJ0100 Rev 1 00 Apr 05 2013 Page 24 of 26 RENESAS RX63N Group RX631 Group Clock Synchronous SCic Communication Using the DMACA 5 8 10 SCI9 Transmission Complete Interrupt Handler Figure 5 12 shows the flowchart for the SCI9 transmission complete interrupt handler Excep_SCI9_TEI9 An interrupt Check the occurred source of the interrupt request TEIE bit Reads the SCI9 SCR register 0 Disables TEI interrupt request 1 Enables TEI interrupt request Reads the SCI9 SSR register No interrupt occurred TEND flag Disable TEI9 interrupt requests Disable interrupt requests Set transmission complete flag Reception complete Set I O port functions Disable SCI9 transmission and reception 0 Character transmission in progress 1 Character transmission completed IER1E register IEN3 bit lt 0 Disables SCI9 TEI9 interrupt requests SCI9 SCR register TEIE bit lt 0 Disables TEI interrupt requests trn_end_flag 1 Transmission completed Reads the rcv_end_flag 0 Reception in progress 1 Reception completed PORTB PMR register B7 bit 0 Used as the PB7 TXD9 general purpose UO port SCI9 SCR register lt SCI9 SCR register amp 03h
31. nous SCilc Communication Using the DMACA 2 Operation Confirmation Conditions The sample code accompanying this application note has been run and confirmed under the conditions below Table 2 1 Operation Confirmation Conditions Item Description Microcontroller used R5F563NBDDFC RX63N Group Operating frequency Main clock 12 MHz PLL 192 MHz Main clock divided by 1 and multiplied by 16 System clock ICLK 96 MHz PLL divided by 2 Peripheral module clock B PCLKB 48 MHz PLL divided by 4 Operating voltage 3 3 V Integrated development environment Renesas Electronics Corporation High performance Embedded Workshop Version 4 09 01 C compiler Renesas Electronics Corporation C C Compiler Package for RX Family V 1 02 Release 01 Compiler options cpu rx600 output obj CONFIGDIR FILELEAF obj debug nologo The integrated development environment default settings are used iodefine h version Version 1 50 Endian order Little endian Operating mode Single chip mode Processor mode Supervisor mode Sample code version Version 1 00 Board used Renesas Starter Kit for RX63N Product number ROKS50563NCOO0BE 3 Reference Application Note For additional information associated with this document refer to the following application note e RX63N Group RX631 Group Initial Setting Rev 1 00 ROLAN1245EJO100_RX63N The initialization functions from th
32. ompletes a DMACOI interrupt request is generated During DMACOI interrupt handling the RXI9 interrupt is disabled and the reception complete flag is set to 1 reception complete If the transmission complete flag is 1 transmission complete transmission and reception are disabled Execution is then repeated from step 2 above Figure 5 2 shows the timing chart for the transmission operation RO1AN1064EJ0100 Rev 1 00 Page 9 of 26 Apr 05 2013 RENESAS RX63N Group RX631 Group Clock Synchronous SCic Communication Using the DMACA Transmit receive start switch input pin IRQ15 interrupt IR flag Reception complete flag SCI9 SCR RIE bit SCI9 SCR RE bit jj I See 4 Set to 0 after 256 DMA DMACO DMCNT i transfers complete DTE bit g i I I i Su Set to 0 by the acceptance DMACOI interrupt IR Bai the interrupt flag qn RXI9 interrupt IEN bit RXI9 interrupt IR flag RDR gt RAM DMA transfer SCI9 RDR register data254 data255 HGP DDR automatic transfer SCI9 RSR register Undefined pes eT f data255 Receive data input to the Reception of 256 bytes Figure 5 2 Reception Operation Timing Chart R01AN1064EJ0100 Rev 1 00 Page 10 of 26 Apr 05 2013 RENESAS RX63N Group RX631 Group Clock Synchronous SCic Communication Using the DMACA Notes on Embedding the Sample Code in the User System When embedding the sample code from this application note in the actual system note the following e
33. oup Clock Synchronous SCic Communication Using the DMACA 1 Specifications This sample program performs clock synchronous serial transmission and reception using the SCI module The transmit data is stored in advance in a RAM transmit data storage area and is transferred using a DMAC The receive data is transferred to the RAM receive data storage area using a DMAC Serial communication is started when a falling edge is detected on the interrupt request pin IRQ15 e Transfer rate 38 400 bps e Communication format 8 bits LSB first e Clock input output Clock output master e Transmission reception operation Transmission and reception can be performed at the same time Table 1 1 lists the peripheral function used and their applications and figure 1 1 shows the block diagram Table 1 1 Peripheral Functions and Their Applications Peripheral Function Application SClc channel 9 SCI9 Clock synchronous serial transmission and reception DMACA channel 0 DMACO Transfer of SCI receive data to RAM DMACA channel 1 DMAC1 Transfer of RAM transmit data to the SCI module IRQ15 Start trigger for serial transmission or reception Internal RAM storage area Transmit data Transmit data storage area Data transfer Transmit block Receive block Transmit enable receive enable Figure 1 1 Block Diagram RO1AN1064EJ0100 Rev 1 00 Page 3 of 26 Apr 05 2013 RENESAS RX63N Group RX631 Group Clock Synchro
34. tart switch input 2 Transmit receive start switch input detection When a transmit receive start switch input is detected the IRQ15 interrupt IR flag is set to 0 After verifying that transmission and reception have completed by checking the transmission complete flag and the reception complete flag the transmission complete flag is set to 0 transmission in progress The DMACI transfer source address and transfer count are set and DMA transfers are enabled The SCI9 SCR TEIE TIE RIE TE and RE bits are all set to 1 at the same time to enable transmission and reception operations The TXI9 interrupt IR flag is set to 1 by the SCI9 TCR TIE and TE bits being set to 1 at the same time 3 Data transfer start When the TXIO interrupt is enabled DMAC1 is started and the TXI9 interrupt IR flag is set to 0 The first byte of transmit data is transferred from the RAM transmit data storage area to the SCI9 TSR register 4 Data transmission start Data is transferred from the SCI9 TDR register to the SCI9 TSR register the TXI9 interrupt IR flag is set to 1 and the first byte of transmit data is output from the TXD9 pin DMAC1 is started by the TXI9 interrupt request and the second byte of transmit data is transferred 5 DMACII interrupt When the 256th data transfer completes a DMAC1I interrupt request is generated The TXI9 interrupt is disabled and the TEI9 interrupt is enabled during DMAC1I interrupt handling 6 TEI9 interrupt Since the SCI9
35. tronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or systems manufactured by you 8 Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations 9 Renesas Electronics products and technology may not be used for or incorporated into an
36. v tENE SAS APPLICATION NOTE RX63N Group RX631 Group DE Clock Synchronous SClc Communication Using the DMACA Ape CS ea Abstract This application note describes a method for clock synchronous serial communication using the RX63N and RX631 s DMA controller DMAC and serial communication interface SCI Products e RX63N Group 177 and 176 pin versions ROM capacity 768 KB to 2 MB e RX63N Group 145 and 144 pin versions ROM capacity 768 KB to 2 MB e RX63N Group 100 pin version ROM capacity 768 KB to 2 MB e RX631 Group 177 and 176 pin versions ROM capacity 256 KB to 2 MB e RX631 Group 145 and 144 pin versions ROM capacity 256 KB to 2 MB e RX631 Group 100 pin version ROM capacity 256 KB to 2 MB When using this application note with other Renesas MCUs careful evaluation is recommended after making modifications to comply with the alternate MCU RO1AN1064EJ0100 Rev 1 00 Page 1 of 26 Apr 05 2013 RENESAS RX63N Group RX631 Group Clock Synchronous SCic Communication Using the DMACA Contents er 3 2 Operation Confirmation Conditions cccccceesceceeeeeeeeeeeeeeeeeeeeseaeeeeaaeseeeeeseaeeseaaeseeeeeseeeessaeeeseeeeenees 4 3 Reference Application Note cccccccescccceeseeceeeeeeeceeeseeeceeeeneeceeesaeceeesneeeeeeneeaeeesneeeeeesneeseeessenseeennaes 4 As THROWN ET 5 4 1 Hardware Configuration ccccccccccceeeeceeeeceeeeeeaeeeeeaeeeeneeceaeeeeaaesgeneeseaeeeeeaesdeaaeseeeeseaeeeeaeseeneee
37. y products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction When exporting the Renesas Electronics products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations 10 It is the responsibility of the buyer or distributor of Renesas Electronics products who distributes disposes of or otherwise places the product with a third party to notify such third party in advance of the contents and conditions set forth in this document Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics products 11 This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics 12 Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its
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