Technical Description
Contents
1. 7 RXDO GPIOAO UART 0 async input 8 GND Ground 9 VCC Power input 10 GND Ground 11 PPS O GPIOA7 1PPS signal output 12 GND Ground 13 XRESET Active low async system reset 14 FCLK GPIOA4 Pre divided clock output of UART 1 15 SPI2XCS2 GPIOB21 SPI2 chip select2 2nd boot select 16 SPI2XCS3 I O GPIOB22 SPI2 chip select3 Boot Select 17 GND Ground 18 TCAP1 GPIOA1 1 Timer TMG1 capture input 19 TINO GPIOA8 Timer TMGO external clock input 20 TIN1 GPIOA10 Timer TMG1 external clock input 21 GND Ground 22 TCAPO GPIOA9 Timer TMGO capture input 23 PM1 GPIOA6 Pulse measurement input 1 24 PMO GPIOA5 Pulse measurement input 0 25 GND Ground 26 MMCCMD I O GPIOA13 MMC command bus UI indicator B 2r SPI1XCSO 2 EES e GE EE 28 MMCCLK O GPIOA12 MMC clock output 29 SPHCLK O GPIOB13 SPI1 clock 30 MMCDAT I O GPIOA14 MMC data bus UI indicator A 31 GND Ground 32 SPI1SDO O GPIOB14 SPI1 data output 33 GND Ground 34 SPI1SDI GPIOB15 SPI1 data input Wake up input 35 GND Ground Fastrax www fastraxgps com 2010 04 23 Page 30 of 38 ITO3 Technical Description 27 doc 36 SPI2CLK I O GPIOB16 SPI2 clock output in master mode 37 GND Ground 38 SPI2SDI GPIOB18 SPl2 data input On Off control input 392. 21 4 13 MMC bus pins 6 8 oi 21 4 14 Mechanical dimensions and contact numbering 21 4 15 Suggested pad layout eeesseeeeeseeeeeeeeeeeeeeennnnne nnn 23 Fastrax 2010 04 23 Page 5 of 38 ITO3 Technical Description 27 doc REFERENCE DESIQN cci ccce eet e De eee esc crea 24 5 1 Minimum Application Circuit Diagram eeeeeernnnnn 24 5 2 Enhanced Application Circuit Diagram eeereeeeeneee 25 5 3 PCB HEGER 26 ITO3 APPLICATION BOARD 2 ceceseceseeennennennnnnnnnnnnnnnnennnnnnnnnnnenenenene 28 DCL General Ee 28 6 2 I O Card Terminal COMME CHOL ccccceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeseeeeeeeeeeeeeee 28 6 3 Bill Of Materlals eee eene ceccuseseeccuaesececuasseaestess 30 6 4 Application Board Circuit Drawing eene 31 6 5 Application Board Components layout eeerereneeree 32 6 6 Application Board Artwork layer 1 eeeeereeeenn 32 6 7 Application Board Artwork layer 2 eeeeeennne 33 6 8 Application Board Artwork layer 3 eene 33 6 9 Application Board Artwork layer 4 eeeeneeeennn 34 HANDLING INSTRUCTIONS eee tnnt 35 7 1 TE EE 35 7 2 Suggested Reflow solde
3. Bypass Cep fer seme regulators REL MASSTST die a vun cw E RENS 1 TCAPI CON RENS Prem TINI CON Z20R RENE C 28 gt mg ron E neue EE CH maen cou 2108 SS RENS A Se PPS CON END Sirxesn SEHCLK Send Senso MMCCLK GND MMCCMD MCDA T END SPIZCLIc XRESET END San spizspo EH Ban VDDRF GND aPuxcSO SPHCLK Sensu SPITSU MNECLK uucemp MMCDAT SPI2CLK XR SET spiasai sPI2sbO SPIZXG TCAP ze Drei TIN TIND 2 e vc St GND td Bd D Lost EI ens Pee E Wi KE eo St END ru Con ES RENS E Ce run ron JUR RENS D Pee vDbbiG FCLK CON A388 RENS A D8 C Rxbo cou Zeg spI2xcs3_coN ml eqng 2 cqug coug a cqug s conz 10 CH coug e CONI M rage coug 20 coug 22 von H copz 25 lt co 28 FCLK EON SPI2XOS3 CON TCAP Con vm Con TCAPO CON Cat ICON MMCCHD CON Vue con MMCDAT CON SPHiSBO CON SPISDI_CON SPIZCLK CON zeen CON SPI2500 CON copz 30 H 32 cong 34 e copz 36 38 EES iTRAXOS ITRAXGS_MOBULE_VER_D at BEN3 B LEER TXDO CON 2208 cow Rr hzMCKSSO022 INE DEEN e mmm CON ZZOR RENS D is rxm mm 270R RF INPUT MCX SQ ohm edge mount ve rxbi cov CQNP 3 mam cov EQN2 5 TxD0 CON CQN2 7 Rxbo c
4. www fastraxgps com 2010 04 23 Page 10 of 38 ITO3 Technical Description 27 doc 2 2 Absolute maximum ratings Table2 General specifications Item Min Max unit Operating and storage temperature 40 85 C Power dissipation 500 mW Supply voltage VDDDIG 0 3 3 6 V Supply voltage VDDRF 0 3 3 6 V Current on any I O pin except antenna 30 30 mA input Current output on antenna input 0 100 mA Input voltage on any input connection 0 3 VDDDIG V 0 3 ESD voltage RFIN Machine Model 160 V RFIN input power 15 dBm Note that module is Electrostatic Sensitive Device ESD LL NV www fastraxgps com Fastrax 3 1 3 2 3 3 2010 04 23 Page 11 of 38 ITO3 Technical Description 27 doc OPERATION Operating modes After power up IT03 boots from the internal Flash memory for normal operation Modes of operation e Navigation Idle mode e Sleep mode e Programming mode Navigation Idle mode The IT03 receiver enters Navigation mode after it has powered up By default it will start navigation automatically after power up or reset in Auto Start mode Auto Start mode means that all available aiding information will be used The module operates as long as the power supply is available Idle mode means that the navigation is stopped but the processor remains active Navigation Idle mode is also referred as Normal Mode The standard firmware su
5. information to calculate pseudo ranges B 8 O Long blink 80 Pseudorange information available but not navigating B 8 O Continuously Navigating Valid fix high state 15 O Low state No valid fix 15 O High state Valid fix available The UI Indicators are updated synchronously at 1 Hz rate The high state duty cycle is either 0 i e continuously logic low 20 Short blink 80 Long blink or 100 i e continuously logic high Pin 15 SPI2SDO GPIOB17 indicates when a fix is available the pin is logic high when location fix is valid and logic low when the location fix is invalid 4 6 3 On Off control input pin 14 With the standard firmware the module can be commanded to Sleep mode by the On Off control input pin 14 SPI2SDI GPIOB18 or by a specific command During Sleep mode only the real time clock is running and the current consumption is reduced to about 20 uA Note that the worst case delay from the On Off Control high to low transition to achieve Sleep mode and reduced current drain is 300 ms The standard firmware stores the last known good position LKG and any Log data to the internal Flash memory before entering the Sleep mode Fastrax www fastraxgps com On Off Control 2010 04 23 Page 18 of 38 ITO3 Technical Description 27 doc Table6 On Off control 1 0 Signal description pin 14 High Normal navigating mode delay from Sleep mode 3 state ms Low st
6. 9k ohm pull down 34 GPIOA9 Pull down GPIO input 9k ohm pull down 35 GPIOA8 Pull down GPIO input 9k ohm pull down 36 GPIOA10 Pull down GPIO input 9k ohm pull down 37 GPIOA11 Pull down GPIO input 9k ohm pull down I O GPIO mode 4 7 Antenna input pin 21 4 7 1 Active GPS antenna 4 8 Signal description The module supports passive and active antennas The antenna input impedance is 50 ohms The input provides also a bias supply during normal navigation operation The antenna bias voltage is the same as the VDDRF supply In the Sleep mode the antenna bias voltage is cut off internally The maximum tolerated antenna bias current is 100mA It is current limited only by the external regulator supplying VDDRF The VDDRF supply current should be externally limited to 150 mA max NOTE Passive antennas with short circuit to GND should be DC blocked externally with a series capacitor 18pF 1nF The customer may use an external active GPS antenna for e g in mobile or indoor usage It is suggested the active antenna has a net gain including cable loss in the range from 6 dB to 32 dB PPS output pin 33 The PPS output provides a pulse per second signal which can be used for timing purposes The default PPS mode is Roving i e timing pulse is available after valid fix based on the current valid fix position The operating mode pulse length and polarity are configurable via NME
7. Low High SPI1 boot Low Low UART Port 0 boot Normally after XRESET low to high transition the appropriate boot selection should be kept active for at least 30 us However after connection of VDDDIG and VDDRF the desired boot selection should be kept active for at least 100 ms which is due to the internal POR delay on the XRESET signal NOTE To ensure normal operation during system reset and power on the Boot Select pin 16 SPI2XCS3 GPIOB22 requires an external pull up resistor connected to VDDDIG e g 4 7 kohm Respectively pin 17 SPI2XCS2 GPIOB21 should be left open or connected to a pull down resistor e g 4 7 kohm Fastrax www fastraxgps com 4 6 2 2010 04 23 Page 17 of 38 ITO3 Technical Description 27 doc UI Indicators pins 8 9 15 The standard firmware includes three GPIO outputs reserved as drivers for User Interface UI Indicators These outputs can be used for example to drive LEDs which give information on the state of the receiver UI Pin Indicator number Table5 Ul Indicators I O Operation High Signal description ratio 96 A 9 O Continuously Power Off or Sleep mode low state 9 O Short blink 20 Normal mode Navigation stopped 9 O Long blink 80 Normal mode Navigation started 8 O Continuously Navigation stopped or not tracking low state satellites B 8 O Short blink 20 Tracking satellites but not enough
8. MHz Master Clock e 1574 40 MHz Local Oscillator of the RF down converter www fastraxgps com Fastrax 2 2 1 2010 04 23 Page 9 of 38 ITO3 Technical Description 27 doc SPECIFICATIONS General Table1 General specifications Receiver GPS L1 C A code SPS Channels 12 Update rate 5 Hz 1 Hz default Supply voltage range VDDRF 2 7V 3 3 V low ripple 2mV RMS max Supply voltage range VDDDIG 42 7V 43 8 V Power consumption 100 mW typical without antenna bias Antenna net gain range 0 32 dB Antenna bias voltage Same as VDDRF Antenna bias current Must be limited externally by VDDRF supply to 150mA max Operating and temperature storage 40 C 85 C Serial port configuration Port 0 NMEA default iT ALK optional Port 1 iTalk Serial data format 8 bits no parity 1 stop bit Serial data speed 600 1200 2400 4800 9600 14400 19200 28800 38400 57600 115200 230400 460800 921600 baud NMEA 4800 default iTalk 115200 default I O signal levels CMOS compatible low state 0 0 0 3xVDDDIG high state 0 7 1 0xVDDDIG I O sink source capability per contact 4 mA max PPS modes Off Survey Static Roving default Accessory I O functionality with GPIO shared 2xCapture Timers 2xPulse Measurement Inputs 1xSPI bus MMC bus Fastrax
9. REGULATOR Er ca Bypass Cap for same regulators GNU SPHX Cs TCAPI 3E Fi SFHCLEK TINI 5 3FHSDD TING 4 SPIHASDI TCAPO i3 MMCCND Pit ERU E MMEDAT PO GND BC SCHER ar 3FI2ULEK ROC RESET gt XRESET VDDDIC R7 330R RB 330R VODRF GND RF INPUT i L ITRAXOJ Figure 7 Enhanced Application Circuit Diagram 5 3 PCB layout issues The suggested 4 layer PCB build up is presented in the following table Table8 Suggested PCB build up 1 Signal Ground with keep out below IT03 2 Ground plane 3 Signal Ground or VDD plane 4 Signal short traces Ground Fastrax www fastraxgps com 2010 04 23 Page 27 of 38 ITO3 Technical Description_27 doc Routing signals directly under the module should be avoided This area should be dedicated to keep out for traces and ground copper except for via holes which can be placed close to the pad under the module If possible the amount of VIA holes underneath the module should be also minimized For a multi layer PCB the first inner layer below the IT03 is suggested to be dedicated for the ground plane Below this ground layer other layers with signal traces are allowed It is always better to route very long signal traces in the inner layers of the PCB In this way the trace can be easily shielded with ground areas from above and below The series resistors at the I O pins should be placed
10. e 1is factory code e Qis last digit of the year e g 2009 e 02 is month e g February e 01 is incremental number of the production batch during the month Serial number is unique for each module having 10 digits including tester code last two digits of the year julian date code and incremental number Fastrax www fastraxgps com 2010 04 23 Page 37 of 38 ITO3 Technical Description 27 doc Direction of Feed 330 00 Module Orientation Mark 0090000009000900 090090090009009000900090000 400 00 MIN 400 00 MIN TRAILER LEADER MATERIALS Reel PS Black Conductive Carrier Tape PS Black Conductive Cover Tape PET Antistatic Tape and Reel 7 _Tape and Reel Specifications Fastrax Ltd Figure 9 TOS3 Tape and Reel www fastraxgps com Im Fastrax 2010 04 23 Page 38 of 38 ITO3 Technical Description_27 doc Contact Information Fastrax Ltd Street Address Valimotie 7 01510 Vantaa FINLAND Tel 358 0 424 733 1 Fax 358 0 9 8240 9691 http www fastraxgps com E mail Sales sales fastraxgps com Support support fastraxgps com www fastraxgps com Fastrax
11. secondary functionality is listed as Alternative GPIO in Table 3 With the standard firmware there are dedicated GPIO connections which are Boot Select UI Indicators and the control inputs These shall be described in the following chapters Fastrax www fastraxgps com 2010 04 23 Page 16 of 38 ITO3 Technical Description 27 doc 4 6 Dedicated GPIO 4 6 1 Boot Select pin 16 The boot source is defined in the internal boot ROM sector by using pins 16 GPIOB22 SPI2XCS3 and 17 GPIOB21 SPI2XCS2 After a power up or a system reset these pins are internally configured to a 9kohm ohm pull down mode for 300 clock cycles 10 us after which their logic states are read Thus if there is nothing connected to pin 16 or 17 these pins will be pulled low and the software will be loaded from UART Port 0 The boot source internal Flash memory UART Port 0 or SPI1 bus is processed according to Table 5 For normal module operation pin 16 must be pulled high to VDDDIG with a 4 7k ohm pull up resistor Pin 17 can be left floating Pin 16 is referred as Boot Select in this document It should be connected in the application in order to enable the hardware based re programming Table4 Boot source selection Pin 17 I O Boot source High High External boot sector Flash in case of failure continue with SPI1 boot High Low External boot sector Flash in case of failure continue with UART Port 0 boot
12. very near to the IT03 module In this way the risk for the local oscillator leakage is minimized For the same reason the by pass capacitors C1 and C2 should be connected very close to the module with short traces to I O contacts and to the ground plane Place the GND via holes as close to the capacitor as possible Connect the GND soldering pads of IT03 to ground plane with short traces to via holes which are connected to the ground plane Use preferably two VIA holes per GND pad The RF input should be routed clearly away from other signals This minimizes the possibility of interference The proper width for the 50 ohm transmission line impedance depends on the dielectric material of the substrate and on the height between the signal trace and the first ground plane With an FR 4 material the width of the trace is about two times the substrate height A board space free of any traces should be covered with copper areas GND In this way a solid RF ground is achieved throughout the circuit board Several VIA holes should be used to connect the ground areas between different layers Additionally it is important that the PCB build up is symmetrical on both sides of the PCB core This can be achieved by choosing identical copper content on each layer and adding copper areas to routing free areas If the circuit board is heavily asymmetric the board may bend during the PCB manufacturing or re flow soldering Bending can cause soldering failures bet
13. will send the new firmware to the processor HW booting is utilized by keeping the Boot Select input pin 16 SPI2XCS3 GPIOB22 at logic low during power up or system reset Now the GPS module boots from the serial data Port 0 sends hex 55 U string at 9600 baud and waits the for the boot loader commands from the host an application running on the host This mode is required when there is no existing firmware stored into the internal Flash memory It is recommended to support hardware based re programming HW booting in an ITO3 application This is done by adding Boot Select and XRESET control inputs into the design See the reference design www fastraxgps com Fastrax 4 1 CONNECTIVITY Connection assignments 2010 04 23 Page 13 of 38 ITO3 Technical Description_27 doc The I O connections are available as soldering pads with castellated via holes on the bottom side of the module These pads are also used to attach the module on the motherboard in the application All unused I O pins should be left open floating Table 3 Full system connection description of ITO3 Some pins can function as GPIO pins or in a special mode depending on the software configuration Signal I O Alternative Signal description name GPIO name GND FERE Ground 2 SPI1XCSO O GPIOB10 SPI1 chip select 0 GPIO reserved for future use Do not connect 3 SPI1CLK O GP
14. 2XCS3 GPIOB22 in such a way that it can be toggled to logic low for a firmware update through serial Port 0 In normal operation Boot Select is pulled high with a resistor R1 in Figure 6 ITO3 supports also software based on the fly programming This does not require toggling of the Boot Select signal However this method is not completely protected against unexpected problems during the re programming session Because of this the use of Boot Select in the design is recommended The low drop out linear regulator LDO U2 supplies 2 8 V voltage to the RF and analog parts VDDRF and the digital supply VDDDIG is taken directly from the main supply which in this case is from 3 0 to 3 3 V due to the small drop out voltage across U2 The linearly regulated power supply is needed for VDDRF because the maximum allowed ripple voltage for VDDRF is 2 mV RMS The external regulator U2 can be omitted if such a supply is available that meets the specified ripple voltage All the digital signals are routed away from the module through series resistors R2 R3 In this way the local oscillator LO signal leakage that is present in the I O contacts of the GPS module is suppressed Although the LO leakage is very small at the I O contacts of the module it may still interfere with the GPS reception especially when the antenna is located very near to these signal routes For the same reason capacitors C1 and C2 should be connected very close to
15. 3 4 Operating modes esseeeeesesssseeeesenene enn nnnnnnnnnnn nnn nnn nnns 11 3 2 Navigation Idle mode eene nennen 11 3 3 Navigation Idle mode eene nennen 11 3 4 Programming mode eeeeseseeeeeeeee eee nnnnnn nnn nnnn nnn rnnnnnn 12 4 CONNECTIVITY de S 13 4 4 Connection assignments Leeseeseesseeeeeee nennen nnne 13 4 2 Power supply pins 18 27 eere 14 4 3 Reset pin 12 ee EENREEERR ERR EEN EEN REESEN EE nnnm nena 15 4 4 Wath dO ciscciccccsccccccsscctccusscecccuss cee ccuasceccousscesccuascesccuasceeccuastececueaceecouass 15 4 5 Shared functionality eeeeeeeeeeeeeeeeeeeeen eene nennen nnne nnn 15 4 6 Dedicated GRO ee gege Anette heii 16 4 6 1 Boot Select pin 16 16 4 6 2 Ul Indicators pins 8 9 ID 17 4 6 8 On Off control input pin 14 17 4 6 4 Wakeup control input mH 18 4 6 5 Sleep mode and WO 18 4 7 Antenna input pin 21 ceeeeeeeeeeeeee eee eee eee eeeee ee eeeeeeeseeseeeeeeeseneeseesenees 20 E ADA Active GPS ateDfidisensengdeneniDo aser nS e a Rar oC RR dead 20 48 PPS output pin 33 sisirin aen aa aaae 20 P 4 9 Serial Ports wissen innit eee aie 21 g 4 10 III C aana 21 i 4 11 Capture timers pins 34 37 eeeeeeeeeeeeeeeeeeeeee nennen 21 4 12 Pulse measurement inputs pins 30 31
16. A or iTALK Other modes are Static Survey and Off see ref 1 for details Fastrax www fastraxgps com 4 9 4 10 4 11 4 12 4 13 4 14 2010 04 23 Page 21 of 38 ITO3 Technical Description 27 doc Serial ports The device supports UART communication via Port 0 RXDO amp TXDO and Port 1 RXD1 amp TXD1 With the standard firmware Port O is configured to NMEA by default and secondary to iTALK protocol Port O is also used when the device is booting from the serial port With the standard firmware Port 1 is configured for iTALK communication by default and secondary to RTCM The serial port logic levels are CMOS compatible Thus they are not directly compatible with RS 232 logic levels Use an external level converter to provide RS 232 levels if needed Refer to ref 7 for supported data speeds SPI bus The SPH in reserved internally for the RF down converter and externally for a custom boot mode Only the SPI2 device master is available for SDK users enabling SPI communication Capture timers pins 34 37 Two general purpose timers are available for SDK users with a custom firmware TMGO and TMG1 have configurable prescalers and clock cycle counts The clock input is selectable between three sources and there is a capture mode to count external events Each timer also has a programmable delay referenced to the internal epoch pulse TME This makes it possible to have a specified delay between inte
17. GND Ground 40 SPI2SDO O GPIOB17 SPI2 data output UI indicator C Pin Signal Alternative GPIO Signal description name name 6 3 Bill of Materials Manufacturer Mig code Package Parttype Description SR SR 0402 Caapacitor_ X7R 10 so 0202 Tf Capactor X7R10 0702 capacitor NPO 10 XSR6 3V SOCKET STRIP 40 PINS MCX SMD female GPS Receiver Resistor 5 D LLL 1 Do 22 2 0402 Resistor 5 MAS9161AGA2 T TSOT 5 Regulator LDO Philips ARV241 0603 4 Resistor Array Fastrax www fastraxgps com 6 4 Application Board Circuit Drawing Change Reason EGO no 2010 04 23 Page 31 of 38 ITO3 Technical Description 27 doc Date Review Date Appr SPHXCSO Con SPIICLK_GON reng raw ren cou MMCCLK Em WicCib Cou MMCDAT CON SPI2CLK CON XRESET GON SPIZSDI EON SPIZXCES CON SPIZXCSP CON HOLE sm CN CN DEEN M 3 0me Drawn 11 6 2003 aes E REG MASSIt cun Bypose Cap for seme regulators REMI A TA 270R C ei aOR RENI E sPnxcso senso Zong DEE UR E REN2 A gt CR lt Meck TZR ER Co map Zeg RENZ C SERIE sensor MMCDAT 2208 REN2 D i s SPIBCLK Zomm RENA A es XRESET 2208 RENA R iF 270R RENA 5 Ze saso Zong REN4 0 IR eisen splaxces izaR C L sriexese E Review Appr Board Design PP CIRCUIT DIAGRAM
18. I O bus and supports several external devices including timers pulse measurement inputs and an MMC bus All the peripherals have a shared functionality with general purpose input output GPIO signals Firmware features include e g build in data logger for position storage to embedded flash memory The antenna input supports passive and active antennas and provides also an internal antenna bias supply This document describes the electrical connectivity and main functionality of the ITO3 hardware 1 1 Block Diagram uN8021 RF Front End uN8130 Baseband Processor ADDR BUS VQ IF INPUTS DATA BUS 4 LNA BPF LNA SPI INTF BUS CTRL Fb Loop filter VDDRF RESET UART 0 amp 1 442 te FCLK 48 CLKIN SPI 1a 2 BOOT SEL MMC BUS lt gt PPS OUTPUT H PM 0 amp 1 INPUT RICINTF Teapg a 4 INPUT TIN 0 amp 1 INPUT VDDRF z RF IN wor 16 3574MHz TCXO 3276BHz XTAL DESEN GPIOB 24 D I BEEN 7 GPIOB 25 RFXEN GPIOB 26 LNA ON OFF uN8021 ON OFF TCXO ON OFF VDDDIG lator VDDCORE www fastraxgps com Figure 1 Block diagram 1 2 Frequency Plan Clock frequencies generated internally at the IT03 receiver Fastrax 2010 04 23 Page 8 of 38 ITO3 Technical Description 27 doc e 32768 Hz Real Time Clock RTC e 16 3574
19. INO GPIOA8 Timer TMGO external clock input 36 TIN1 GPIOA10 Timer TMG1 external clock input 37 TCAP1 GPIOA1 1 Timer TMG1 capture input Signal vol Alternative Signal description name GPIO name Note 1 The input has internal 18kohm pull up resistor Note 2 The input has internal 9kohm pull down resistor Note 3 The input has internal 100kohm pull up resistor Power supply pins 18 27 The IT03 module requires two separate power supplies VDDRF for the RF parts and VDDDIG for digital parts and I O bus Note that VDDDIG supply input contains internal ceramic 1uF low ESR 0 010hm by pass capacitor Use a power supply that is specified for low ESR lt 0 010hm output capacitor loads VDDDIG and VDDRF should be powered up at the same time within a few ms NOTE VDDDIG power supply should be compatible with low ESR 0 010hm ceramic capacitors Fastrax www fastraxgps com 4 3 4 4 4 5 2010 04 23 Page 15 of 38 ITO3 Technical Description 27 doc VDDRF must be linearly regulated having a low ripple 2mV RMS max The typical current drain is 24 mA in Normal Navigation mode Note that VDDRF is also provided internally at the antenna input as an active antenna bias NOTE VDDRF supply current should be limited externally below 150 mA max NOTE VDDRF supply voltage should have a low ripple 2mV RMS max The VDDDIG supply may be shared wi
20. IOB13 SPI1 clock 4 SPI1SDO O GPIOB14 SPI1 data output 5 SPHSDI GPIOB15 SPI1 data input Wake up input 2 6 MMCCLK O GPIOA12 MMC clock output 7 GND Ground 8 MMCCMD I O GPIOA13 MMC command bus UI indicator B 9 MMCDAT I O GPIOA14 MMC data bus Ul indicator A 10 GND Ground 11 SPI2CLK I O GPIOB16 SPI2 clock output in master mode 12 XRESET Active low async system reset 3 13 GND Ground 14 SPI2SDI GPIOB18 SPI2 data input On Off control input 1 15 SPI2SDO O GPIOB17 SPI2 data output Ul indicator C 16 SPI2XCS3 I O GPIOB22 SPI2 chip select3 Boot Select Pull high with external 4 7kohm resistor 17 SPI2XCS2 O GPIOB21 SPI2 chip select2 2nd boot select 18 VDDRF VDD for RF circuits 19 GND Ground 20 GND Ground 21 RFIN RF input antenna bias output Fastrax www fastraxgps com 4 2 2010 04 23 Page 14 of 38 ITO3 Technical Description 27 doc 22 GND Ground 23 TXD1 O GPIOA3 UART 1 async output 24 RXD1 GPIOA2 UART 1 async input 25 TXDO O GPIOA1 UART 0 async output 26 GND Ground 27 VDDDIG VDD for digital circuits 28 RXDO GPIOAO UART 0 async input 29 FCLK O GPIOA4 Pre divided clock output of UART 1 30 PMO GPIOA5 Pulse measurement input 0 31 PM1 GPIOA6 Pulse measurement input 1 32 GND Ground 33 PPS O GPIOA7 1PPS signal output 34 TCAPO GPIOA9 Timer TMGO capture input 35 T
21. Technical Description 27 doc Figure3 Contact numbering top view through the package Fastrax www fastraxgps com 2010 04 23 Page 23 of 38 ITO3 Technical Description 27 doc Figure A Pad dimensions bottom view 4 15 Suggested pad layout www fastraxgps com Figure 5 Suggested pad layout top view through the package Dimensions are in mm Fastrax 2010 04 23 Page 24 of 38 ITO3 Technical Description 27 doc 5 REFERENCE DESIGN 5 1 The idea of the reference design is to give a guideline for the applications using the IT03 GPS module In the following two chapters the reader is exposed to design rules he should follow when designing an ITO3 based application By following the rules one ends up having an optimal design with no unexpected behavior caused by the PCB itself In fact these guidelines are quite general in nature and can be utilized in any PCB design related to RF techniques or high speed logic Minimum Application Circuit Diagram The Minimum Application supports communication through the UART Port 0 NMEA or iTALK Other required signals are the antenna input supply voltages for VDDRF and VDDDIG and a pull up resistor for the Boot Select Also it is a good practice to make the IT03 application to support hardware based re programming of the module firmware Due to this one should connect Boot Select pin 16 SPI
22. at RFIN I QJ Avoid also ultrasonic exposure due to internal crystal and SAW components The module meets the requirements of Directive 2002 95 EC of the European Parliament and of the Council on the Restriction of Hazardous Substance RoHS For details contact Fastrax support Suggested Reflow soldering profile Use pre heating at 150 180 C for 60 120 sec Suggested peak reflow temperature is 235 245 C for SnAg3 0Cu0 5 alloy Absolute max reflow temperature is 260 C For details see Fastrax document Soldering Profile ref 3 Moisture sensitivity Note that the ITO3 is moisture sensitive at MSL 3 see the standard IPC JEDEC J STD 020C The module must be stored in the original moisture barrier bag or if the bag is opened the module must be repacked or stored in a dry cabin according to the standard IPC JEDEC J STD 033B Factory floor life in humid conditions is 1 week for MSL 3 Tape and reel One reel contains 500 modules Marking Module marking includes type and batch codes and serial number Fastrax www fastraxgps com 2010 04 23 Page 36 of 38 ITO3 Technical Description 27 doc Type code is e g IT0316 341D STD 3278 where e 110316 is ITO3 with internal 16 Mbit flash memory e 341D is SDK revision 3 4 1 and D is incremental firmware release revision e STD is firmware configuration code e 3278 is BOM Bill of Materials revision code Batch code is e g 190201 where
23. ate Sleep mode delay from Normal mode 300 ms max NOTE With the standard firmware the On Off control input pin 14 SPI2SDI GPIOB18 has an internal 18k ohm pull up resistor connected to VDDDIG and the signal can be left unconnected for normal operation During Sleep mode the input is switched internally to pull down 9kohm resistor 4 6 4 Wakeup control input With the standard firmware the module can be wake up from sleep state by the Wake Up control input SPI1SDI GPIOB15 pin 5 depending on the sleep mode wakeup mask Wake Up input is normally used only when the module has entered sleep state using the specific serial command Wake up interrupt is generated by a low high low pulse to the Wake Up control input The pulse length should be at least 20 ms The input has an internal 9kohm pull down resistor and can be left unconnected for normal operation 4 6 5 Sleep mode and I O During the Sleep mode almost all the I O pins are configured as inputs with internal 100k ohm pull down resistors In order to reduce current leakage there are few exceptions see Table 9 Table7 Pin states in Sleep mode default firmware EN Pin mode I O GPIO Signal description 1 GND Ground Fastrax www fastraxgps com 2010 04 23 Page 19 of 38 ITO3 Technical Description 27 doc 2 GPIOB10 Pull
24. down GPIO input 9k ohm pull down 3 GPIOB13 Pull down GPIO input 9k ohm pull down 4 GPIOB14 Pull down GPIO input 9k ohm pull down resistor 5 GPIOB15 Pull down GPIO input keeper 6 GPIOA12 Pull down GPIO input 9k ohm pull down 7 GND Ground 8 GPIOA13 Pull down GPIO input 9k ohm pull down 9 GPIOA14 Pull down GPIO input 9k ohm pull down 10 GND Ground 11 GPIOB16 Pull down GPIO input 9k ohm pull down 12 XRESET Active low async system reset 13 GND Ground 14 GPIOB18 Pull down GPIO input pull down Stays as pull up if NMEA Sleep command was used in Normal mode 15 GPIOB17 Pull down GPIO input 9k ohm pull down 16 GPIOB22 Pull down GPIO input 9k ohm pull down 17 GPIOB21 Pull down GPIO input 9k ohm pull down 18 VDDRF VDD for RF circuits 19 GND Ground 20 GND Ground 21 RFIN RF input antenna bias output 22 GND Ground 23 GPIOA3 Pull up GPIO input 18k ohm pull up 24 GPIOA2 Pull up GPIO input 18k ohm pull up 25 GPIOA1 Pull up GPIO input 18k ohm pull up 26 GND Ground 27 VDDDIG VDD for digital circuits 28 GPIOAO Pull up GPIO input 18k ohm pull up 29 GPIOA4 Pull down GPIO input 9k ohm pull down 30 GPIOA5 Pull down GPIO input 9k ohm pull down 31 GPIOA6 Pull down GPIO input 9k ohm pull down Fastrax www fastraxgps com 2010 04 23 Page 20 of 38 ITO3 Technical Description 27 doc 32 GND Ground 33 GPIOA7 Pull down GPIO input
25. oN CQNg 8 vno cow 1 PPS CON XRESET_caN ca CONj 15 sriz oS2 CON vo CONQ 79 rio con von Cu NZ z3 en CON mopjes uu copg 27 raren enn EEN cogn o DIER u caj SCH CON2 39 ET Cooperatar s doe na FASTRAX WWW lastraxgps com Fastrax 2010 04 23 Page 32 of 38 ITO3 Technical Description 27 doc 6 5 Application Board Components layout 6 6 Application Board Artwork layer 1 www fastraxgps com Fastrax 2010 04 23 Page 33 of 38 ITO3 Technical Description 27 doc 6 7 Application Board Artwork layer 2 oo oo ooo oO oo 6 8 Application Board Artwork layer 3 WWW fastraxgps com 2010 04 23 Page 34 of 38 ITO3 Technical Description 27 doc 6 9 Application Board Artwork layer 4 www fastraxgps com Fastrax 2010 04 23 Page 35 of 38 ITO3 Technical Description 27 doc 7 HANDLING INSTRUCTIONS 7 1 7 2 7 3 7 4 7 5 Assembly The IT03 module supports only assembly and soldering in a reflow process on the top side of the PCB Suggested solder paste stencil height is 150um minimum to ensure sufficient solder volume Note that module is Electrostatic Sensitive Device ESD Rated voltage is 160V max Machine Model at antenna input RFIN signal NOTE Note that module is Electrostatic Sensitive Device ESD rating 160V max Machine Model
26. positioning A Q Y ESA REV 2 7 Technical Description Fastrax IT03 OEM GPS Receiver This document describes the electrical and main functionality of the Fastrax ITO3 hardware April 23 2010 Fastrax Ltd www fastraxgps com Fastrax 2010 04 23 Page 2 of 38 ITO3 Technical Description 27 doc TRADEMARKS Fastrax is a registered trademark of Fastrax Ltd All other trademarks are trademarks or registered trademarks of their respective holders COPYRIGHT 2003 2010 Fastrax Ltd DISCLAIMER This document is compiled and kept up to date as conscientiously as possible Fastrax Ltd cannot however guarantee that the data are free of errors accurate or complete and therefore assumes no liability for loss or damage of any kind incurred directly or indirectly through the use of this document The information in this document is subject to change without notice and describes only generally the product defined in the introduction of this documentation Fastrax www fastraxgps com 2010 04 23 Page 3 of 38 ITO3 Technical Description 27 doc CHANGE LOG Rev Notes Date 1 1 Preliminary documentation 2003 08 05 1 2 SPI2SDO UO direction in 3 2 2003 08 28 1 3 Major update 2003 11 17 1 4 Updated I O pin usage 2004 01 21 1 5 Updated I O pin usage and application circuit 2004 02 02 1 6 Check by SW team 2004 05 27 Let Added mois
27. pports versatile configuration of various operating configurations e g Logging position data etc for further details see ref 1 The navigation can be stopped by sending a proper NMEA or iTALK message see also ref 7 Navigation Idle mode The Sleep mode means low power operation during which no other activity other that the internal real time clock RTC is present The module enters Sleep mode via a special control message ref 1 or by the On Off Control input The exit from the Sleep mode to the Normal mode happens in the following situations e an elapsed time e an RS 232 break signal or a dummy input character to selected serial port the low input state should exceed 20ms e an interrupt from the On Off Control input low to high transition e an interrupt from the Wake up input low high low pulse gt 20ms Since the internal RTC keeps the GPS time estimate the module performs the fastest possible navigation start depending on the availability of valid satellite position data Fastrax www fastraxgps com 2010 04 23 Page 12 of 38 ITO3 Technical Description 27 doc 3 4 Programming mode The module enters Programming mode by two methods HW booting or upgrading the firmware on the fly by a dedicated NMEA or iTalk command see ref 1 The on the fly upgrading requires only the serial Port 0 The downloading will start by sending a special serial port command after which the utility running on the host
28. ring profile ecce 35 7 3 Moisture sensitivity eeeeeeeeeeeeeeeee nennen nennen nennen 35 TA Tape and reel eere etre ttti eren een irr ene 35 7 5 rim mm 35 www fastraxgps com Fastrax 2010 04 23 Page 6 of 38 ITO3 Technical Description 27 doc COMPLEMENTARY READING The following reference documents are complementary reading for this document Ref File name Document name 1 PRO NMEA html Fastrax NMEA Protocol Specification 2 uN8130T UM pdf uN8130 User s manual 3 Reflow soldering Soldering Profile profile pdf www fastraxgps com Fastrax 2010 04 23 Page 7 of 38 ITO3 Technical Description_27 doc GENERAL DESCRIPTION Fastrax IT03 is a GPS receiver module for the OEM market segment It integrates the GPS chip set from Atheros the RF down converter uN8021 and the processor uN8130 The processor includes all base band functions needed for GPS signal acquisition tracking and navigation Dedicated high performance search engine architecture enables a rapid search of visible satellites A 12 channel tracking unit insures that positioning is possible even in severe conditions such as weak signals in urban canyons The processor provides also an internal watchdog timer The ITO3 module interfaces to the customer s application via a versatile
29. rrupts generated by the internal TME epoch TMGO and TMG1 For details see ref 2 Pulse measurement inputs pins 30 31 The two pulse measurement PM inputs are available for SDK users with a custom firmware PM inputs can be used to measure with great accuracy how long an input stays high or low For details see ref 2 MMC bus pins 6 8 9 The MMC bus is available for SDK users with a custom firmware The MMC unit implements a standard 3 wire Multi Media Card serial bus interface and provides control and data register for easy usage of the bus Both stream and block mode data transfers are supported The CRC is calculated automatically for transmitted commands and data blocks also received responses and data blocks are checked for correct CRC The MMC unit has a 64 bit data buffer and is capable of stopping bus clock to prevent buffer overflow and underflow situations For details see ref 2 Mechanical dimensions and contact numbering Board size is 22 0mm width x 23 3mm length x 2 6mm height 3 1mm max General tolerance is 0 3mm I O contacts are using castellated via holes which allows also hand soldering and visual inspection of solder wetting Fastrax www fastraxgps com 2 6 0 8 GND 1 SPHXCSO 2 SPHCLK 3 SPHSDO 4 SPHSDI 5 MMCCLK 6 MMCCMD B MMCDAT 8 SPIZSDI 14 SPI2500 15 SPI2XCS3 16 SPI2XCS2 17 VDDRF 18 GND 19 Dimensions 1 5mm 45deg 2010 04 23 Page 22 of 38 ITO3
30. th any available supply that meets the specified voltage range A typical current is 12 mA in Normal Navigation mode but it may peak up to 40 mA for short durations The VDDDIG supply voltage ripple should be below 40mV RMS Reset pin 12 The system reset input pin 12 XRESET is an active low asynchronous reset The processor boots after an XRESET low to high transition The XRESET input contains a 100k ohm pull up resistor an open source Power on Reset POR circuit and a Schmitt trigger in order to eliminate the effect of noise The POR is connected in parallel with the XRESET input and it overrides XRESET during power up For normal operation the XRESET input can be left unconnected The module will independently handle the reset during power on However to enable the hardware re programming it is advisable to connect the XRESET input for example to an open collector or an open source control output Watchdog The processor contains a watchdog peripheral which resets the processor if not refreshed frequently enough Basically the watchdog is a 16 bit counter with enabling disabling and restarting controls The watchdog counter is clocked with the frequency of 128 Hz Shared functionality All the UO pins have a shared functionality These pins can be programmed either to have a special function PM SPI MMC etc or a general purpose I O GPIO function Each signal is named according to the special functionality but also the
31. the module with short traces to I O contacts and to ground plane Additionally there must be another capacitor C3 4 7uF or bigger from VDDDIG to the ground This capacitor can be located further away If a signal from the ITOS3 is not needed the corresponding pin can be left open Fastrax www fastraxgps com 2010 04 23 Page 25 of 38 ITO3 Technical Description_27 doc VDORF uz VOUT 2 8V REGULATOR CND al Lc CA m Byposs Cup for some regulators ihn R3 4230F iE SEI a SPlaxeS3 TXDI qa SFI2YCS2 GND VODRF RF IW RF INPUT ITRAYOS Figure 6 Minimum Application Circuit Diagram Note that there is a DC voltage present at the RF input when the module is operating in Normal mode This voltage is equal to VDDRF If a passive antenna with short circuit to the GND is used an external series DC block capacitor 18pF must be used 5 2 Enhanced Application Circuit Diagram A more versatile functionality can be achieved by adding the On Off control for the Sleep mode and the secondary UART Port 1 Note that there is also a Wake up input in pin 5 SPI1SDI GPIOB15 One should also support hardware re programming of ITO3 by adding Boot Select control pin 16 SPI2XCSS GPIOB22 See Chapter 5 1 for more details www fastraxgps com Fastrax 2010 04 23 Page 26 of 38 ITO3 Technical Description 27 doc C5 Gn 2 a KI 43 8v
32. ture sensitivity information 2004 06 16 1 8 Contact 17 in page 13 modified chapter 6 1 2004 09 30 1 9 Wake up pin states chapt 4 6 ref design 2004 12 02 2 0 Tables 3 amp 4 chapt 4 6 5 figures 6 amp 7 2005 02 23 2 1 Added iTrax03 Application Board documentation 2005 09 01 2 2 Added pin description to chapter 6 2005 09 06 2 3 Fixed some typing errors 2005 11 28 2 4 Added recommendations for wiring unused GPIO pins 2006 06 30 abandoned 2 5 PCB upgrade module name change to IT03 corrected 2009 05 27 internal pull up own resistor values corrected Wakeup control input interrupt signal type to pulse 2 6 Added disclaimer and marking codes 2010 03 16 2 7 Added notes and spec on ESD ultrasonic sensitivity 2010 04 23 and RoHS updated disclaimer Fastrax www fastraxgps com 2010 04 23 Page 4 of 38 ITO3 Technical Description_27 doc CONTENTS 1 GENERAL DESCRIPTION 0 cccccccceeeceeeceeeceeeceeeeeeeeeeeseeeeeeeeeeeeeeeseeeeeeeeeeeeeeeeees 7 1 1 Block Diagram eei KSEAEE EE eEEES EE EE EE ee 7 1 2 Frequency Plan ecrire ee cenetdeceecedyseceuayseesncetieeuenaytersecet 7 2 ddeljieuielPm 9 2 1 General enceinte ecekacoeet ues Een nena ENEE gsx ee eege 9 2 2 Absolute maximum ratings eere nnn 10 3 DRERATION m 11
33. ween the ITO3 connection pads and the application board pads Fastrax www fastraxgps com 6 2010 04 23 Page 28 of 38 ITO3 Technical Description 27 doc ITO3 APPLICATION BOARD 6 14 General The IT03 Application Board is intended for easy evaluation of the ITO3 OEM GPS module and it is especially intended as a sub system for the Evaluation Kit It consists of the PCB board on which the surface mountable IT03 module is attached and two regulators which provide two separate supply voltages 2 8V The I O Card Terminal connector provides all the available connectivity to the system connector of the Evaluation Kit The MCX RF connector provides the access to the Antenna input ITRAXO03 Application Board Power Regulators System iTRAX03 Connector Module Serial Resistors lt gt Antenna Connector Figure 8 TOS Application Board Block Diagram 6 2 O Card Terminal connector The following signals are available at the I O Card Terminal connector CON2 Table9 Card Terminal Connections Signal Alternative GPIO Signal description name name 1 TXD1 O GPIOA3 UART 1 async output 2 GND Ground 3 RXD1 GPIOA2 UART 1 async input 4 GND Ground 5 TXDO O GPIOA1 UART 0 async output 6 GND Ground Fastrax www fastraxgps com 2010 04 23 Page 29 of 38 ITO3 Technical Description 27 doc
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