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1. 2channels Individual channel patterns can be set Skew between channels is within 20ps SMB connector Differential PECL Skew between patterns is within 100ns 1 External trigger mode Any bit length in a multiple of 32 of 32bit 256kbits per Ich 2 Continuous mode Any bit length in a multiple of an even number of 32bit 256kbits per Ich 1 External trigger mode 2 Continuous mode Frequency is counted by internal standard clock Measurement accuracy is 50ppm Measurement range is from 0 1MHz to 3040 0MHz 1 FPGA normal operation display 2 Pattern outputting also combining with alarm output 3 Frequency judgment of input RF clock Asynchronous serial communication 9600bps 8 bit 1 stop bit non parity Signal level 3 3VCMOS 3 3V single power 0 2V max 1200mA 100mm x 80mm 0 60 degree C 30 470 degree C 3 Digital Signal Technology 2 3 Output wave example 3Gbps PCIExpress Compliance pattern 0 0 Gars 10 0 kpts RAR AAR RAR AAAS OVE OVE 6 H O am t flees _ _ H ala lt 495 0 ps 4 0 gt Zuma 3 Memory configuration Pattern memory CHO hati feist Asynchronous 256 kii F pattem outpu Seta 5Akhit CH CH pattern output Copied ta a pattern memory Save command when the power is turned on APG 3G has a pattern memory and a Flash memory The pattern memory is volatile and its data is lost when the power is turned OFF The Flash memory is non volatile2. dumping is done from the first address of CHO sequentially and after ending dumping of CHO subsequently dumping is done sequentially from the first address of CH1 Every 32 bits are dumped on one line CHO PATTERN MEMORY CR LF XXXX_XXXX CR LF XXXX_XXXX CR LF CH1 PATTERN MEMORY CR LF XXXX_XXXX CR LF XXXX_XXXX CR LF 10 Digital Signal Technology 8 3 3 Command related to the start and stop of pattern output 1 CNT command When CNT CR LF is entered pattern output is started in the continuous repetition mode When pattern output is started in the continuous repetition mode the LED2 lights Bit synchronization between 2 channels may be lost due to exogenous noise or the like When bit synchronization is lost the LED2 flashes In addition whether synchronization between bits is lost or not can be confirmed with the START command When synchronization between bits is lost enter CNT CR LF again to eliminate bit synchronization loss 2 TRG command When TRG CR LF is entered pattern output is started in the external trigger mode When an external trigger is set the set pattern is output once When pattern output is started in the external trigger mode the LED2 flashes Bit synchronization between 2 channels may be lost due to exogenous noise or the like When bit synchronization is lost the LED2 flashes In addition whether synchronization between bits is lost or cannot be confirmed
3. with the START command When synchronization between bits is lost enter CNT CR LF again to eliminate bit synchronization loss 3 STOP command When STOP CR LF is entered pattern output is stopped and the LED2 lights off 8 3 4 Command related to the flash memory 1 SAVE command When SAVE CR is entered information of the currently set pattern memory content pattern length HIGH LOW limit of an input frequency pattern burst stopping repetition mode external trigger mode is written in a flash memory When the power is turned on these pieces of information are read out and set When the SAVE command is executed in the repetition mode or the external trigger mode the repetition mode external trigger mode is set when the power is turned on next time Unless correctly written the following response returns FLASH ERROR CR LF 2 ERASE command When ERASE CR is entered data stored in the flash memory is erased Unless data in the flash memory is correctly erased the following response returns FLASH ERROR CR LF 11 Digital Signal Technology 3 RD F command When RD F CR LF is entered data in the FLASH memory is dumped When interrupting dumping enter S As shown below dumping is done from the first address of CHO sequentially and after ending dumping of CHO subsequent dumping is done sequentially from the first address of CH1 Every 32 bits are dumped on one line CHO FLASH MEMO
4. RY CR LF XXXX_XXXX CR LF XXXX_XXXX CR LF CH1 FLASH MEMORY CR LF XXXX_XXXX CR LF XXXX_XXXX CR LF 8 3 5 Command related to setting parameters readout 1 STAT command When STAT CR LF is entered a frequency of an input clock frequency limit set bit length continuous repetition external trigger stopping status of synchronization between channels are output sequentially The response is as follows RF_IN dddd dMHz CR LF FRQ LO dddd dMHz CR LF FRQ_Hl dddd dMHz CR LF LENGTH 0xXXXXXXXX CR LF CNT CR LF or TRG CR LF or STOP CR LF Clock Error CR LF or no message When Clock Error is returned there occurs a bit synchronization error between channels therefore send the CNT command and the TRG command again to eliminate synchronization loss between 2 channels 8 3 6 Other command 1 HELP command When HELP CR LF is entered a list and description of each command are output 12 Digital Signal Technology 8 3 7 Precautions for input clock APG 3G measures a frequency of the input clock at the time when the CNT command or the TRG command is entered and adjusts hardware for data based on the measured frequency When changing the frequency of the input clock in the process of the continuous repetition mode and the external trigger mode send the CNT command and the TRG command again In addition when saving data in the CNT mode or TRG
5. Signal Technology 10 Factory default settings Data is written in the Flash memory at the time of factory shipment so as to output the compliance pattern of PCIExpress described in 8 Command setting example Data other than pattern data is written as follows FRQ_LO 0000 0MHz FRQ_LHI 3000 0MHz LENGTH 0x00000028 CNT mode 11 Shipping inspection 100 inspection shall be performed for the electrical specification in 2 1 12 Warranty If any defect is found due to the manufacturer s improper production or design within one year after delivery repair or replacement shall be performed at the manufacturer s responsibility Digital Signal Technology Inc assumes no liability for damages that may occur as a result of handling by users even though the warranty period 13 Accessories For power supply J7 on PCB 2P connector cable 1 piece For asynchronous serial communication J10 on PCB 3Pconnector cable 1 piece Spacer screw 4 sets 14 Others 14 1 This product which employs a CMOS device may be easily damaged by static electricity DS Technology Inc assumed no liability for damages that may occur as the result of handling by users even through the above warranty period 14 2 Do not supply over voltage power supply or module may be damaged DS Technology Inc assumes no liability for damages that may occur as the result of handling by users even though the above warranty period Descriptions of this manual are subject to cha
6. User s Manual PRBS Pattern Generator Part No APG 3G Digital Signal Technology Inc 1 7 30 Higashi Benzai Asaka Saitama 351 0022 Japan TEL 81 48 468 6094 FAX 81 48 468 6210 WEE http www dst co jp en Email info dst co jp CO NO OO fF W N b O A U N gt O Contents General description Specification Memory configuration Explanation for pattern output mode Outer dimension Connector Description of LEDs on board How to control by synchronous serial data Examples for how to set commands Factory default settings Shipping inspection Warranty Accessories Others Digital Signal Technology 1 General description Independent 2 outputs are provided which can be set different patterns 2 Specification 2 1 Electrical specification 1 Input clock 2 Trigger input 3 Pattern output 4 Clock output 5 Output bit length 6 Bit trigger output mode 8 Frequency counter 7 LED on board 8 Control 9 Power requirements 10 Outer dimensions 2 2 Environmental condition 1 Operating temp range 2 Storage temp range SMB connector 50 ohm single end AC coupling Sine wave 30MHz 3000MHz 3dBm 3dBm Square wave 2KHz 3000MHz 3dBm 3dBm Shutdown startup time is within 4nS Duty ratio 50 10 SMB connector 3 3V CMOS Pulled up internally at 10K ohm There is a jitter of 5nS up to pattern output start relative to trigger input SMB connector Differential PECL
7. and its data is held even when the power is turned OFF If any pattern is stored in the Flash memory data in the Flash memory is copied to a pattern memory when the power is turned on If no data is stored in the Flash memory the pattern memory is cleared to O when the power is turned on After storing data in a pattern memory in asynchronous serial save it in the Flash memory with the SAVE command Patterns of CHO and CH1 are 4 Digital Signal Technology output from the pattern memory Refer to the description of the command for details of the above operation 4 The explanation of pattern output mode 4 1 Description of external trigger mode External trigger Clock CHO CHI In this mode the L level of the external trigger terminal is detected and data of a pattern memory is output only once The bit pattern of a specified bit length is output from the head of the pattern memory Refer to the description of the command for writing to the pattern memory and setting a bit length If the trigger becomes the Low level before the bit pattern output is completed pattern output is restarted at the time when the trigger becomes the Low level The external trigger terminal is pulled up inside and can be put to an external trigger only by connecting a push on switch or the like There is a jitter of 5nS from a time Re start from the head detected trigger during pattern OT iT 2t 3 4p sp epopiy 27 37 4q 5 e POT TT 27 3
8. ital Signal Technology Refer to the description of the command for setting LowLimit or HighLimit 8 Control by asynchronous serial communication data How to set from a PC serial port RS 232C is explained below 8 1 Communication specification Speed 9600bps Data bits 8 bits Stop bits 1 bit Parity None Flow control None Logic Level 3 3V CMOS 8 2 RS 232C connection The logic level of APG 3G serial communication is 3 8V CMOS which cannot be directly connected to RS 232C level such as PC serial port Level conversion between RS 232C and 3 3V CMOS is needed As an option our level converter LVC 232C is available for your convenience Please refer to our Home Page http dst co jp en manuals lvc232c pdf 8 3 Definition of command A character string enclosed by means ASCII code and CR and LF are control codes meaning OD hex and OA hex _ underscore means a space If any invalid command is entered INVALID DATA CR LF is returned Characters to be entered shall be entered in uppercase If a normal command is entered CR LF is returned In addition the entered data is echoed back 8 3 1 Command related to frequency counter 1 FRQ LO command FRQ LO_dddd d CR LF dddd d The LOW limit of the entered frequency shall be set in units of MHz When the frequency becomes higher than the set LOW limit LED2 lights off Even if the frequency judgment function is not
9. mode connect the input clock before turning on the power because the TRG mode or CNT mode is set when turning on the power next time When a clock is entered from SG bit synchronization between 2 channels may be lost due to transient phenomenon of SG when parameters such as frequency output level output ON OFF of SG are changed When there occurs any bit synchronization loss the LED2 flashes then send the CNT command and the TRG command to eliminate synchronization loss between 2 channels Loss of bit synchronization can be confirmed even with the STAT command Bit synchronization between 2 channels may be also lost due to exogenous noise or the like It is recommended to periodically monitor bit synchronization loss with the STAT command or by visual check of LED2 8 3 8 Precautions when continuously setting data When sending commands at high speeds APG 3G may omit any data because it does not perform TE SHI flow control When processing of each command is completed a prompt of is returned then send the next command after confirming reception of this prompt 9 Command setting example Acommand setting example is described as an example of a pattern to output a compliance pattern of PCIExpress in the continuous pattern output mode As shown in the figure a compliance pattern of 40 bits is output from CHO and a pattern for trigger is output from CH1 Clock CHI 1 Turn on the power and return the following me
10. nge without notice No portion of this manual can be reproduced without the permission of Digital Signal Technology Digital Signal Technology assumed no liability for damages that may occur as a result of handling by users The contents of this manual do not apply to the warranty in executing an industrial property or other rights nor permission for the right of execution Digital Signal Technology assumes no responsibility for the third party s industrial property occurred from using the circuits described in this manual
11. p 4p sp ep opi 27 374 ts IA when the external trigger is on to start of pattern output In the external trigger mode only bit length in a multiple of 32 bits can be set Add a dummy 0 behind the desired bit pattern and set a bit length in a multiple of 32 bit 2 bit L 1 dummy 0 bit length in a multiple of 32 bits 5 Digital Signal Technology 4 2 Description of continuous repetition mode The set pattern is repeatedly output A bit pattern is output from the head of the pattern memory and the output returns to the head when the specified bit length is reached Refer to the description of the command for setting the pattern memory and bit length In the continuous mode a bit length of an odd number and a bit length not larger than 32 bits cannot be set When setting a bit length of an odd number and not larger than 32 bits couple some of the desired bit patterns to set a bit length of an even number not less than 32 bits bit length of an even number not les than 32 bits 5 Outer dimension 100mm 90mm p gt 4 0 3 2mm JP1 7 A gt a Ow C TRG RESERVED CHO P J J2 J9 J10 CHON _ J O a C ASYNC CH1_P E J4 80mm O ji RESERVED CHIN 3 70mm J7 O PWR LED3 LED2 2 LED1 li J8 ARFI J6 J5 3 CLK N CLK_P Q 6 Digital Signal Technology 6 Connector 6 1 Connector names and descri
12. ption Connector number Name Description JP1 RESERVED Not used This connector must be opened Ji CHO P PECL positive output SMB for CHO J2 CHO N PECL negative output SMB for CHO J3 CHI P PECL positive output SMB for CHO J4 CHIN PECL positive output SMB for CHO J5 CLK_P PECL positive output SMB for Clock J6 CLK_N PECL positive output SMB for Clock J7 PWR Power supply terminal Part No DF1BZ 2P 2 5DSA Manufacturer Hirose J8 RF_IN Clock input SMB J9 RESERVED Not used This connector must be opened J10 ASYNC Asynchronous serial communication control Part No DF1BZ 3P 2 5DSA Manufacturer Hirose J11 TRG Input pin under external trigger mode 6 2 J7 Connecter pin assignment Part No DF1BZ 2P 2 5DSA Manufacturer Hirose Pin number Name Description 1 3 3V Supply 3 3V 2 GND GND 6 3 J10 Connecter pin assignment Part No DF1BZ 3P 2 5DSA Manufacturer Hirose Pin number Name Description 1 GND GND 2 RXD Receiving port Host APG 3G 3 TXD 7 Description of LEDs on board LED1 Lights when FPGA is normally starting Transmitting port Host APG 3G LED2 Lights in the continuous repetition mode and the external trigger mode This flashes when any error occurs in bit synchronization between 2 channels of pattern output LED3 Can be used for simple diagnosis of input clock quality as a result of frequency judgment for input clock This lights in the case of LowLimit lt frequency of input clock lt HighLimit 7 Dig
13. set it does not relate to pattern output operation To set 2400 1MHz enter the following data FRQ LO_ 2400 1 CR LF 8 Digital Signal Technology 2 FRQ HI command FRQ HI _ddddd d CR LF dddd d The HIGH limit of an input frequency shall be set in units of MHz When the frequency becomes lower than the set HIGH limit the LED2 lights off Even if the frequency judgment function is not set it does not relate to pattern output operation To set 2400 1MHz enter the following data FRQ HI 2400 1 CR LF 8 3 2 Command related to pattern memory writing 1 PSO BRAM CSD command This is a data transmission command set to the CHO pattern memory When PSO CR LF is entered the pattern memory acceptable status for a command CHO is set in Further transmit the PDATA command subsequently BRAM_xxxx_xXxxx CR LF BRAM_xxxx_xXxxx CR LF BRAM_xxxx_xxxx CR LF BRAM_xxxx_xXxxx CR LF For xxxx data shall be specified in hexadecimals of 4 digits 4 digits Data is stored sequentially from previously transmitted data in the pattern memory from the first one In addition data of hexadecimals of 4 digits 4 digits is stored in a pattern memory with MSB first After completing transmission of the pattern transmit CSD CR LF Data transmission to the pattern memory is completed with CSD CR LF Even if the data has not reached 256kbit at the time transmission of data for a pattern memory is comple
14. ssage when initialization is normally completed DST APG 3G Ver1 0A CR LF 2 Connect the input clock and confirm that the desired frequency is obtained with the STAT command 13 Digital Signal Technology STAT CR LF 3 Set a frequency limit so that the frequency judgment function of the LED3 can be used It is recommended to set a frequency limit with some allowance in consideration of variation in frequency of clock source used and measurement accuracy of frequency counter in this equipment In addition even if the frequency judgment function is not set it does not relate to pattern output operation FRQ LO_dddd d CR LF FRQ HI_dddd d CR LF 3 Send data of 40 bits to a pattern memory of CHO PSO CR LF BRAM_3EAA_AC15 CR LF BRAM_5500_0000 CR LF CSD CR LF 4 Send data to a pattern memory of CH1 In CH1 only the first one bit is 1 therefore the BRAM command is used only once PS1 CR LF BRAM_8000_0000 CR LF CSD CR LF 5 Set a pattern length LENGTH_0000_0028 CR LF 6 Start pattern output in the continuous repetition mode CNT CR LF 7 Save in the flash memory SAVE CR LF In the flash memory information of pattern memory content pattern length continuous repetition external trigger stopping and frequency limit are stored Output of a compliance pattern of PCIExpress is started immediately when the power is turned on next time 14 Digital
15. ted transmission of the pattern can be interrupted by transmitting CSD CR LF When no pattern data is stored in the Flash memory the pattern memory is initialized to O when the power is turned on When intentionally using 0 data it is unnecessary to transmit data to the pattern memory For example when setting a bit pattern as shown in the figure enter as follows PSO CR LF BRAM_3EAA_AC15 CR LF BRAM_5500_0000 CR LF CSD CR LF 9 Digital Signal Technology 2 PS1 BRAM CSD command This is a data transmission command set to the CH1 pattern memory Similar to CHO transmit PS1 CR LF BRAM_xxxx_xXxxx CR LF BRAM_xxxx_xxxx CR LF BRAM_xxxx_xXxxx CR LF BRAM_xxxx_xXxxx CR LF CSD CR LF sequentially to set a command to CH1 3 CLEAR command When CLEAR CR LF is entered pattern memories of both of CHO and CH1 are cleared to 0 4 LENGTH command When LENGTH_xxxx_xxxx CR LF is entered a pattern length is set For xxxx xxxx specify a pattern length in 8 digit hexadecimal APG 3G has a memory of 256kbit however outputs patterns by bit number of head set in LENGTH CHO and CH1 cannot be individually set for the LENGTH command For example when setting 40 bits enter the following data LENGTH 0000 0028 CR LF 5 RD P command When RD P CR LF is entered data of a pattern memory is dumped When interrupting dumping enter S As shown below
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