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LC870N00 SERIES USER`S MANUAL

1. Exo Hx FESD 00000000 rw IICR INTILH INTILV INTUIF INTOLH INTOLV INTOIF wro Fese 00000000 scr INTSHEG INT3LEG INT3IF INT2HEG INT2LEG mrar INT2IE Bits 7 6 and 0 of PITST FE47 are reserved for test purposes They must always be set to 0 3 5 Port 1 3 2 3 Related Registers 3 2 3 1 Port 1 data latch P1 1 Thislatch is an 8 bit register that controls port 1 output data and pull up resistors 2 When this register is read with an instruction data at pins P10 to P17 is read in If P1 FE44 15 manipulated using the NOTI CLRI SET1 DBZ DBNZ INC or DEC instruction the contents of the register are referenced instead of the data at the pin 3 1 data can always be read regardless of the I O state of the port Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE44 0000 0000 R W Pl P17 P16 P15 P14 P13 P12 P11 P10 3 2 3 2 Port 1 data direction register P1DDR 1 This register is 8 bit register that controls the I O direction of port 1 data 1 bit units Port P1n is placed in output mode when bit PInDDR is set to 1 and in input mode when bit PInDDR is set to 0 2 When PInDDR is set to 0 and bit PIn of the port 1 data latch is set to 1 port PIn becomes input with a
2. 3 21 343 Circuit Configuration eee eee ee eer eee eee eee eee eee eee ee ee eee ee ee ee 3 23 3 4 4 Related Registers 3 28 3 5 Base Timer BT Furssususrssesssssusenesssasusenesususenesssasesessesesessusesesessesesesseses 3 33 3 5 1 Overview Fursuesusussassususenensasusessusasessesssessssessssusenensasenessesuseseeses 3 33 3 5 2 Functions errr errr errr rere rr rrr rere rrr rere reer ere ee eee ee eee ee eee ee ee ee 3 33 3 5 3 Circuit Configuration eee eee eee ee eee ree eee eee ee ee eee eee eee eee ee eee ee 3 33 3 5 4 Related Registers Furrsssrurssessssusenessasusessuseasesessesssessensssusesessasssese 3 34 3 6 Serial Interface 1 SIO1 3 37 3 6 1 Overview 3 37 3 6 2 Functions 3 37 3 6 3 Circuit Configuration
3. 3 4 3 2 2 Functions 3 4 3 2 3 Related Registers Furssasusrssessssusenensusussneususensususesessesuseseesesesseseses 3 6 3 2 4 Options Fasessssuressssusenesseseusessususesessessususessususenessasesesseseseseenessoss 3 1 1 3 2 5 HALT and HOLD Mode Operation 3 1 1 3 3 Timer Counter 0 TO Fesesurusassusausenessasusessesssessssessusueesessuasesessesesesesses 3 1 2 3 3 1 Overview Furssesusrssassssausenensasusessususensenssessssessssusenensasesessessseseeses 3 1 2 3 3 2 Functions Furusususrssessssusenensasusessususesessussusessensususesessasusessesesesesses 3 1 2 3 3 3 Circuit Configuration Fassuuresessususessususenenseasusessusasesensesusessessseseeses 3 1 3 3 3 4 Related Registers 3 1 8 34 Timer 1 T1 Fusrsrurusensusasesessasusessesusessenesusususensususensususesessesssessesessoee 3 21 3 4 1 Overview 3 21 342 Functions
4. 3 38 3 6 4 SIO1 Communication Examples 3 42 3 6 5 Related Registers Furrsssssssessususenensaususessususesessesssessensssusenessesssese 3 46 3 7 AD Converter ADC1 0 eer rere rere errr errr rere rere errr reer reer er ee ee eee eee eee eee ee 3 48 3 7 1 Overview 3 48 3 7 2 Functions Fursuesususraessususenessasusessususenessessussusessssusenessasusesseseseseeses 3 48 3 7 3 Circuit Configuration Furssssussssessessssssessssssenessususescsususenessusesessesssese 3 49 3 7 4 Related Registers Furrsesrsrssassssusenensasusessususesessesssessensssusesensesesese 3 49 3 7 5 AD Conversion Example Fasrssusuresessausasessususessesssessssessssusesessesesese 3 53 Contents 37 6 Hints on the Use of the ADC mne 3 54 3 8 Motor Control PWM MCPWM2 HH HMM 3 56 3 8 1 ILLE 3 56 382 Functions nnn r nennen rennen nnn nn nnne nnno nn nara 3 56 3 8 3 Circuit Configuration mmm 3 57 3 8 4 Related Registers mmm 3 60 3 8 5 MP2OTi MP2OTi Output Port Settings 0 1 3 65 3 8 6 Timing Charts mme 3 66 3 9 Analog Comparator HH 3 70 301 ssseeese eene nnne run 3 70 3 9 2 Funct
5. bit 7 INT3 rising edge detection control INT3LEG bit 6 INT3 falling edge detection control INT3HEG INT3LEG INT3 Interrupt Conditions P11 Pin Data No edge detected Falling edge detected 0 0 E 1 o Rising cage desea INTSIF bit 5 INT3 interrupt source flag This bit is set when the conditions specified by INT3HEG and INT3LEG are satisfied When this bit and the INT3 interrupt request enable bit INT3IE are set to 1 an interrupt request to vector address 001BH is generated This bit must be cleared with an instruction as it is not cleared automatically 3 9 Port 1 INTSIE bit 4 INT3 interrupt request enable When this bit and INT3IF are set to 1 an interrupt request to vector address 001BH is generated INT2HEG bit 3 INT2 rising edge detection control INT2LEG bit 2 INT2 falling edge detection control INT2HEG INT2LEG INT2 Interrupt Conditions P10 Pin Data No edge detected Falling edge detected 0 0 9 7 1 o ising sige desea INT2IF bit 1 INT2 interrupt source flag This bit is set when the conditions specified by INT2HEG and INT2LEG are satisfied When this bit and the INT2 interrupt request enable bit INT2IE are set to 1 a HOLD mode release signal and an interrupt request to vector address 0013H are generated The interrupt flag however cannot be set by a rising edge occurring when the P10 data that is establ
6. E CE Feso 0000 0000 RA i0 bit AD mode mwa ADD aoma aw Fesa 0000 0000 RA 10 bit AD conversion result L DATAL DATAL DATALO ADRLS Fess 0000 0000 RW 10 bit AD conversion result H patar omae DATAS DATAS DATA2 DATA DATA0 either en FE5C Feb 0000 0000 ww O O irr Ire mr mov IWIOIE AI 3 Address Initial Value R W LC870N00 Remarks BIT8 BIT7 BIT6 BITS BIT4 BIT3 BIT2 BITI BITO 0000 0000 R W 123CR INT3HEG INTSLEG INTSIF INT2HEG INT2LEG INT2IF INT2IE FESF 00000 0000 Rw BUZDIV STOHCP STOLCP BTIMGI BTIMCO BUZON NFSEL STOIN qu vlc su get LE Feet 11111 1111 j j eee o 111111114 LER uM po Een p p j j p WI NES C EN j Fees 141111114 EXER 5 ee _ EN RA WDTSLO _ ANAK HNIC i rer mnn Ld LL I T TI
7. 2 3 8 2 Functions 1 PWM output The PWM period is controlled by the 10 bit counter that runs on the system clock and by the value of the PWM period setting register The low level width of PWM is controlled by the PWM match count setting register NPWM is an inverted PWM signal with a dead time The dead time is controlled by the dead time setting register PWM and NPWM signals are output from pins POO and 01 as MP2OTO and MP2OTO respectively MP2OTO and MP2OTO are controlled by the MCPWM2 output mode select register Similarly PWM NPWM signals are output from pins P02 and P03 as 2 and 2 1 respectively MP2OTI and MP2OTI are controlled by the MCPWM2 output mode select register MP20T0 2 MP2OTI and MP2OTI are forced to stop output by an external input INTO INT 1 comparator 1 2 2 Interrupt generation An end of cycle interrupt request is generated at the end of each cycle if the end of cycle interrupt enable bit is set An end of half cycle interrupt request is generated at the end of each half cycle if the end of half cycle interrupt enable bit is set End of cycle and end of half cycle interrupt sources are used for automatic start mode operation of the AD converter 3 It is necessary to manipulate the following special function registers to control the motor control PWM 2 e MP2CR MP2ICR 2 MP2PDL MP
8. AI 4 LC870NO0 APPENDIX I Address Initial Value R W LC870N00 Remarks BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BITI BITO FE7D FE7E 0000 0000 FSRO FLASH control Bit 4 is ERA FSROB7 FSROB6 FSAERR FSWOK INTHIGH FSLDAT FSPGL FSWREQ Fix to 0 Fix to 0 FEF 00000000 Rw Base timer control Brst Bron BICI BTCIO BTIFO BTIEO Il ou s pe qu jJ j a b 12 24 11 15 4 Ht p ed MEER FEO resi FE92 m 1 FE94 rtos FE96 0000 0000 FE97 HHHH HHOO FE98 FE99 FE9A FE9B FE90 FE9 FE FE FE94 FE FEO6 FE97 FE98 FE99 FE9A Address Initial Value R W LC870N00 Remarks BIT8 BIT7 BIT6 BITS BIT4 BIT3 BIT2 BITI BITO FE9C H000 0000 R W MP2DT M2DT6 M2DT5 M2DT4 M2DT3 M2DT2 M2DT1 M2DT0 RA ww oo Wes Were W20TEOB woreo m C LLL i i frees ie ia Ce a 0000 RA cem 1 ee m Fear 0000 cem owzour cues owezit omo 0000 RW PREV CPIVRSL3 cervis 0000 RW cR REN CP2V
9. 3 8 3 4 PWM period setting register MP2PDL MP2PDH 10 bit register with a match buffer register 1 This register stores the match data that sets the PWM period It is provided with a 10 bit match buffer register An end of cycle interrupt source or an end of half cycle interrupt source is set when the value of this match buffer register matches the value of the 10 bit counter 2 The match buffer register is updated as follows The match buffer register is loaded with the contents of MP2PDL and MP2PDH when the state of the M2PWMEN bit MCPWM2 control register bit 7 is switched from 0 to 1 3 8 3 5 10 bit counter Start stop Stop start is controlled by the 0 1 value of the M2PWMEN bit MCPWM2 control register bit 7 2 Count clock The output of the operation clock generator circuit 3 Reset When the value of the PWM period setting match buffer register matches the value of the 10 bit counter 3 57 MCPWM2 3 8 3 6 PWM match count setting register MP2MTL MP2MTH 1 2 10 bit register with a match buffer register This register stores the match data that sets the PWM match count It is provided with a 10 bit match buffer register The state of the PWM signal changes when the value of this match buffer register matches the value of the 10 bit counter The match buffer register is updated as follows The match buffer register is loaded with the contents of MP2MTL and MP2MTH when the state of the M2PW
10. J3 M2MT9 0 1 M2PD9 0 When the AD automatic start mode is set the next AD automatic start signal issued while AD conversion is in progress cannot be accepted To start the next automatic start processing after terminating the existing AD conversion when the AD automatic start mode is set clear bit 1 AD conversion end flag of the ADCRC register No further automatic start signals can be accepted when bit 1 of the ADCRC register is set to 1 3 67 MCPWM2 3 8 6 2 Mode 1 0 1 i 0 M2OPLB The polarity of MP20Ti MP2OTi outputs is positive M2OPL a E 33 2 o 3 85 2 A o s 5 gt SNe GARR OBR TO Ra oe Seem sre Be TuTpBe EEPBSeREERERBRPT RET va A S cu 8 a 9 lt x _ 2 5 LESE ES Bas Pode eles ates TR eS So isa Kt A eure mim Bote abe eee Dye ee m c Eb emm bec ort Ne ee eh ee lt 5 Luke Leg 1 N N o ii 1 50 1 50 dt 1 OD OD So zx EE E setae NEC E 255 82599 82592 82555605 5 A 2 CRUS 5 o 98B og 5 5 SSH 5 5 Q 5 95455 5 V V V V E Q N f bn di o
11. Interrupt request accepted Interrupt request from INTO Reset entry conditions to INT2 established Reset entry conditions established Returned mode Normal mode Notel HALT mode Notel Data changed on exit PCON register bit 0 0 PCON register bit 1 0 Note 1 The microcontroller switches into the reset state if it exits the current mode on the establishment of reset entry conditions Note 2 Some serial transfer functions are suspended Table 4 3 2 Pin States and Operating Modes This series On Exit Reset Time Normal Operating Mode HALT Mode HOLD Mode from HOLD Input 00 03 Input mode Input output pull up resistor Pull up resistor off controlled by a program P10 P17 Input mode Input output pull up resistor Pull up resistor off controlled by a program 4 12 LC870NO0 Chapter 4 Reset state entry conditions Low level applied to the RES pin Reset signal generated by watchdog timer HOLD mode entry conditions PCON register FEO7H bit 1 set to 1 e HOLD mode All oscillators stopped Since OCR register bits 1 and 4 are cleared medium speed RC oscillator starts oscillation and designated as the system clock when CPU exits HOLD mode CPU and peripheral modules are stopped HOLD mode release conditions INTO or INT1 level interrupt request generated INT2 interrupt request generated Reset entry conditions established No
12. Start stop Stop start is controlled by the 0 1 value of TIHRUN timer 1 control register bit 7 Count clock Depends on the operating mode T1LONG Prescaler Count Clock 2 Tcyc p 1 o 1 j The O aruni e TIL match signal 256 x TILPRC count x Tcyc Prescaler count Determined by the TIPRC value The count clock for T1H is output at intervals determined by the prescaler count T1HPRE T1HPRC2 T1HPRC1 T1HPRCO 1 Prescaler Count Timer 1 low byte T1L 8 bit counter Start stop Stop start is controlled by the 0 1 value of TILRUN timer 1 control register bit 6 Count clock TIL prescaler output clock Match signal A match signal is generated when the count value matches the value of the match buffer register Reset When the counter stops operation or a match signal occurs in mode 0 or mode 2 Timer 1 high byte T1H 8 bit counter Start stop Stop start is controlled by the 0 1 value of TIHRUN timer 1 control register bit 7 Count clock prescaler output clock Match signal A match signal is generated when the count value matches the value of the match buffer register Reset When the counter stops operation or a match signal occurs in mode 0 mode 2 or mode 3 Timer 1 match data register low byte T1LR 8 bit register with a match buffer register This register is used to store the match data for TIL It has an 8 bit match buffer register A match
13. 1 870 00 Chapter T1L prescaler T1H prescaler Invert T1PWMH output 2 Reload Reload TILR T ag set flag set lt 16 bit programmable timer gt Figure 3 4 3 Mode 2 Block Diagram T1LONG 1 T1PWM 0 lt Match buffer T1PWML output Set Invert T1PWMH output Comparator register Reload Reload lt Wd T1LCMP T1HCMP TILR flag set T1HR flag set 16 bit programmable timer gt Figure 3 4 4 Mode 3 Block Diagram T1LONG 1 T1PWM 1 3 27 3 4 4 Related Registers 3 4 41 Timer 1 control register T1CNT 1 This register is an 8 bit register that controls the operation and interrupts of TIL and T1HRUN bit 7 count control When this bit is set to 0 timer 1 high byte T1H stops on a count value of 0 The match buffer register of has the same value When this bit is set to 1 timer 1 high byte T1H performs the required count operation T1LRUN bit 6 T1L count control When this bit is set to 0 timer 1 low byte TIL stops on a count value of 0 The match buffer register of has the same value as TILR When this bit is set to 1 timer 1 low byte T1L performs the required count operation T1LONG bit 5 Timer 1 bit length select When this bit is set to 0 timer 1 high and low order bytes serve as independent 8 bit timers When this bit is set to 1 timer 1 serves as a 16 bit tim
14. 3 Theregister sets the division ratio of the oscillator clock to be used as the system clock to i 4 2 35 High speed RC oscillation control register OCR3 1 bit register 1 Thisregister controls the start stop operations of the high speed RC oscillator circuit 4 2 3 6 System clock divider control register CLKDIV 3 bit register 1 This register controls the operation of the system clock divider circuit b gai 2 4 8 16 32 64 N i 1 1 The division ratios of pg are available 4 6 LC870NOO Chapter 4 CLKCB4 Y CLKSGL CLKDV2 to 0 iah Main clock FRCSTART gt gh speed RC oscillator System clock SCLK Divider 2 9 2 a Selector Internal medium RC clock 5 speed RC oscillator fSCLK System clock frequency fCYC Cycle clock frequency Minimum instruction cycle fCYC fSCLK 3 Fig 4 2 1 System Clock Generator Block Diagram 4 2 4 Related Registers 4 2 41 Power control register PCON 1 Thisregister is a 2 bit register used to specify the operating mode normal HALT HOLD See Section 4 3 Standby Function for the procedures to enter and exit the operating modes Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE07 HHHH R W PCON PDN IDLE Bits 7 to 2 These bits do not exist They are always read as 1 PDN bit 1 HOLD mode setting
15. J register x NPWM 1 1 i 1 gt _ lt 1 ple 1 pog 1 I M2DT6 M2DT6 gt M2MT9 0 M2MT9 0 gt r i sa i 0 is i M2MT9 0 M2MT9 0 gt 1 M2PD9 0 i When the AD automatic start mode is set the next AD automatic start signal issued while AD conversion is in progress cannot be accepted To start the next automatic start processing after terminating the existing AD conversion when the AD automatic start mode is set clear bit 1 AD conversion end flag of the ADCRC register No further automatic start signals can be accepted when bit 1 of the ADCRC register is set to 1 3 69 CMP 3 9 Analog Comparator CMP 3 9 4 Overview This series of microcontrollers is provided with two channels of internal analog comparator circuit that accepts an external input The output of the analog comparator can be used to force the MCPWM2 output to stop 3 9 2 Functions 1 Analog comparator Generates out of pin P13 the result of comparing the minus input from pin P12 with the plus input from pin P11 Generates out of pin P15 the result of comparing the minus input from pin P17 with the plus input from pin P16 2 Interrupt generation Generates a comparator 1 interrupt request on detection of the rising falling edge of the comparator 1 output if the comparator 1 interrupt enable bit is set Generates a comparator 2 interrupt request on detection of the risin
16. X level interrupt requests are always enabled regardless of the state of this bit XFLG bit 6 X level interrupt flag R O This bit is set when an X level interrupt is accepted and reset when execution returns from the processing of the X level interrupt This bit is read only No instruction can rewrite the value of this bit directly HFLG bit 5 H level interrupt flag R O This bit is set when an H level interrupt is accepted and reset when execution returns from the processing of the H level interrupt This bit is read only No instruction can rewrite the value of this bit directly LFLG bit 4 L level interrupt flag R O This bit is set when an L level interrupt is accepted and reset when execution returns from the processing of the L level interrupt This bit is read only No instruction can rewrite the value of this bit directly Bits 3 2 These bits do not exist They are always read as 1 XCNT1 bit 1 0000BH interrupt level control flag A in this bit sets all interrupts to vector address 0000BH to the L level 0 in this bit sets all interrupts to vector address 0000BH to X level XCNTO bit 0 00003H interrupt level control flag A in this bit sets all interrupts to vector address 00003H to the L level 0 in this bit sets all interrupts to vector address 00003H to X level 4 3 Interrupt 4 1 4 2 Interrupt priority control register IP 1 This register is an 8
17. bit 1 Noise filter time constant select NFSEL NFON Noise Filter Time Constant 1 0 0 STOIN bit 0 Timer 0 count clock input port select This bit selects the timer 0 count clock signal input port When this bit is set to 1 a timer 0 count clock is generated when an input that satisfies the INT3 interrupt detection conditions is supplied to P11 When this bit is set to 0 a timer 0 count clock is generated when an input that satisfies the INT2 interrupt detection conditions is supplied to P10 3 2 4 Options Two user options are available 1 CMOS output with a programmable pull up resistor 2 N channel open drain output with a programmable pull up resistor 3 2 5 HALT and HOLD Mode Operation When in HALT or HOLD mode port 1 retains the state that is established when HALT or HOLD mode is entered 3 11 TO 3 3 Timer Counter 0 TO 3 3 1 Overview The timer counter 0 TO incorporated in this series of microcontrollers is a 16 bit timer counter that provides the following four functions 1 Mode 0 8 bit programmable timer with a programmable prescaler with an 8 bit capture register x 2 channels 2 Mode I 8 bit programmable timer with a programmable prescaler with an 8 bit capture register 8 bit programmable counter with an 8 bit capture register 3 Mode 2 16 bit programmable timer with a programmable prescaler wi
18. top b Clock 9 lt lt Low output Internal on falling edge of 8th 8 Operation start SIIRUN T 1 1 on left side 1 on right No start bit on falling released on falling edge of SILEND With start bit i on rising edge of when and SIIEND 0 Period 2 to 512 lt 8 to 2048 lt 2 to 512Tcyc 2 to 512Tcyc lt Tcyc Tcyc SIIRUN Set Instruction lt 1 Start bit Instruction Already set Already set Start bit bit 5 Instruction detected 2 Start bit detected Clear End of lt End of stop lt 1 1 processing bit Stop Stop condition condition detected detected 2 2 When Ack 1 arbitration detected lost Note 1 Set End of lt End of stop lt 1 lt 1 processing bit Rising edge Falling edge of 9th clock of 8th clock 2 2 Stop Stop condition condition detected detected SIIEND bit 1 Note 1 If internal data output state H and data port state L conditions are detected on the rising edges of the first to Sth clocks the microcontroller recognizes a bus contention loss and clears SIIRUN and also stops the generation of the clock at the same time Continued on next page 3 39 SIO1 Table 3 6 1 Transfer Receive SHREC 0 SHREC 1 Transfer SIO1 Operations and Operating Modes cont Synchronous Mode 0 UART Mode 1 Receive SHREC 0 SHREC 1 Bus Master Mode 2 Transfer Receive SI1REC 0 SIREC 1 Bus Slave Mode 3 Transfer SI1REC
19. un bn 9 S 25 R un 8 g s EI amp 38 8 a lt Soft processing ADSTART ADCRC bit 2 AD automatic conversion started 3 68 LC870N00 Chapter Notes The PWM period M2PD9 to M2PDO is set to 1 2 cycle The dead time MP2OTi MP20Ti 0 i 0 1 is inserted at the following timings 1 An MCPWM2 operation is started 2 The MCPWM2 output mode is changed If the MCPWM2 output mode is set to 100 or 111 the dead time is inserted at the timings 3 4 and 5 below in addition to the above mentioned timings 1 and 2 3 Immediately before the rising edge of PWM and immediately after the falling edge 4 The duty cycle is changed from a point other than around 100 M2MT9 to 2 2M2DT6 to M2DTO to around 10096 M2MT9 to M2MTO M2DTO to M2DTO M2MT9 0 Match buffer M2MT9 0 M2DT6 0 M2MT9 0 lt M2DT6 0 register PWM 1 NPWM _ gt gt lt M2DT6 0 i M2DT6 0 M2DT6 0 1 1 M2MT9 0 M2MT9 0 gt m M2MT9 0 M2MT9 0 M2PD9 0 5 The dead time is inserted when the duty cycle is changed from around 100 M2MT9 to M2MTO lt M2DT6 to M2DTO to a point other than around 100 M2MT9 to 2 2M2DT6 to M2DTO In the case of 5 the dead time may be longer than in normal cases 2 times maximum M2MT9 0 Match buffer M2MT9 0 lt M2DT6 0 M2MT9 0 M2DT60 1
20. 0 Receive SI1REC 1 SIIOVR Set 1 lt bit 2 Falling edge of clock detected when SIIRUN 0 2 SIIEND set conditions met when SHEND 1 ss gemi Shifter data update SBUFI shifter at beginning of operation Shifter gt SBUFI bits O to 7 Automatic update of SBUFI bit 8 1 lt Falling edge of clock detected when SIIRUN 0 2 SIIEND set conditions met when SIIEND 1 SBUF1 shifter at beginning of operation When 8 bit data transferred data Input data read in on stop bit When 8 bit 1 lt SIIEND set conditions met when SIIEND 1 SBUFI shifter at beginning of operation Rising edge of 8th clock received Input data read in on rising edge of 9th clock Data input n Data 8 bit shift register SIOSF1 output Clock Y At time At time operation transfer ends starts SBUF1 FE35h bit7 bit6 bit5 bit4 bit bit2 bit0 SIO1 output control gt P13 port latch 1 lt Falling edge of clock detected when SIIRUN 0 2 SIIEND set conditions met when SHEND 1 3 Start bit detected SBUFI shifter at beginning of operation Rising edge of 8th clock Input data read in on rising edge of 9th clock P13 output control SIO1 output control gt P14 port latch P14 output control Clock Clock generator circuit ii M
21. 0000 tn i 4 i iB 1933 8 7199 A B X 0000 0000 RM S Sp Sp Sp 53 52 00000000 RA ts SPi4 SPI3 spiz SPI SPO 59 R T T r T SP0 SP LKSG LKCB NER 0000000 R TL rs 0000 0000 R WM FEt4 0000000 Rw TOR Fes 0000 0000 Ra TUR FEI6 XXX XXX R Timer 0 capture register L Resmo E esu OHRU TOHIE OLRUN OLON TOHI SPO O P Feoc HHHH Hooo RM Oe asa ce eel FEE OHHOHHOH RA 068 0 0 0 0 0 Resto gg 22 ee eee al TOLRUN TOLONG TOLIE T L 3 3 U ee a iim CLKCB4 o TOHCMP TOPRR4 T 3 3 X TOLIE T T L N 1 6 6 1 6 T 4 T T T N N E 6 5 2 5 2 5 2 5 K 2 C T T T G E TOHR7 T TOHR5 TOHR4 T TOHR2 T 5 3 2 5 3 2 G o P TOW Tons TOHS TOH2 P pem T T uo nox R Timer 0 capture register ri 0000 0000 aw rw 4 ris 0000 0000 rm 41 0000 0000 R rt H rus n
22. 004BH is generated when this bit and CMP2IF are set to 1 3 73 CMP 3 9 4 3 Comparator 1 internal reference voltage control register CP1VR 1 Thisregister is a 6 bit register that controls the internal reference voltage of comparator 1 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO FEA2 0000 R W CPIVR CPVREF2 CPIVREN CP1VRSL3 CP1VRSL2 CP1VRSL1 CP1VRSLO CPVREF2 bit 7 Internal reference voltage range setting Setting this bit to 0 selects the larger internal reference voltage range Setting this bit to 1 selects the smaller internal reference voltage range CP1VREN bit 4 Comparator 1 minus input select When this bit is set to 0 the minus input of comparator 1 is selected as the external input from P12 When this bit is set to 1 the minus input of comparator 1 is selected as the internal reference voltage of comparator 1 CP1VRSL3 to CP1VRSLO bits 3 to 0 Comparator 1 internal reference voltage setting 1 When CPVREF2 0 Comparator 1 internal reference voltage Set value 1 x VDD x 0 64 16 2 When CPVREF2 1 Comparator 1 internal reference voltage Set value 1 x VDD x 0 64 64 Notes The CPVREF2 setting is common to comparators I 2 The selection of the minus input CP1VREN and the internal reference voltage setting CPVREF2 CPIVRSL3 to CPIVRSLO must be performed while the comparator is stopped CPAPIEN 0 CPAP2EN 0 The internal refe
23. Disable is selected in the LVD reset function options When not using the internal reset circuit set the POR release level to the lowest level 1 67V that will not affect the minimum guaranteed operating voltage Note 3 No operating current flows when the POR reset state is released Note 4 See the notes in paragraph 2 of subsection 4 6 6 when selecting a POR release level that is lower than the minimum guaranteed operating voltage 1 67V 4 22 LC870NO0 Chapter 4 e Selection example 1 Selecting the optimum LVD reset level to keep the microcontroller running without resetting it until VDD falls below 2 7V according to the set s requirements Set the LVD reset function option to Enable and select 2 51V as the LVD reset level option Set operating range VDD 2 7V LVD release voltage LVDET LVHYS SVS SS Hs FS SS eue reset voltage LVDET Typ 2 51 e Selection example 2 Selecting the optimum LVD reset level that meets the guaranteed operating conditions VDD 2 7V Tcyc 250ns Set the LVD reset function option to Enable and select 2 81V as the LVD reset level option Microcontroller guaranteed operating range VDD 2 7 to 5 5V Tcyc 250ns LVD release voltage LVDET LVHYS LVD reset voltage LVDET Typ 2 81V Lower limit operation guarantee voltage VDD 2 7V Tcyc 250ns e Selection example 3 Disabling the internal reset circuit and using an external reset IC that can detect and react at 3 0V
24. Pin Connection Requirements ete 1 8 1 7 Recommended Unused Pin Connections eee eee ee eee eee eee rere 1 8 1 8 Port Output Types mrsnananansesseuausansnuyuesesuuuanensensesauanansessunauuausensenesunanseseus 1 8 1 9 User Option Table eee eee eee eee eee eee eee ee eee eee eee eee eee eee 1 9 Chapter 2 Internal Configuration nur iter user itur sor qata aisles on 2 1 2 1 Memory Space eee ere eer eee eee ee eee rere eee eee ee ee eee ee eee eee eee ee ee 2 1 2 2 Program Counter PC ee eee eee eee ee eee ee eee eee eee eee ee er eee 2 1 2 3 Program Memory ROM Pee ee eee ee eee eee eee ee eee eee eee eee eee eee ee 2 2 24 Internal Data Memory RAM LL ma 2 2 2 5 Accumulator A Register ACC A eee eee eee eee eee eee eee ee eee ee eee ee 2 3 2 6 B Register B eee eee eee eee ee eee eee eee eee eee eee eee eee ree ee eee 2 3 2 7 G Register C ee eee eee eee eee ee eee ee ee eee eee ee eee eee eee eee ee ee ee eee 2 4 2 8 Program Status Word PSW Ln 2 4 2 9 Stack Pointer SP 2 5 2 10 Indirect Addressing Registers nn 2 5 2 11 Addressing Modes A ZA 2 6 2 1 1 1 Immediate Addressing eee eee eee eee eee eee ee eee eee ee ee eee 2 6 2 11 2 Indirect Register Indirect Addressing Rn 8 2 7 2 11 3 Indirect Register C Register Indirect Addressing 2 7 2 11 4 Indirect Register RO Offset Value Indirect Addressi
25. R W Name BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE36 0000 0000 R W SBRI SBRG17 SBRG16 SBRGI5 SBRG14 SBRG13 SBRGI2 SBRGI1 SBRGIO ADC10 3 7 AD Converter ADC10 3 7 1 Overview This series of microcontrollers incorporates a 10 bit resolution AD converter that has the features listed below It allows the microcontroller to capture analog signals easily 1 10 bit resolution 2 Successive approximation 3 AD conversion mode selection resolution switching 4 6 channel analog input 5 Conversion time selection 6 Automatic reference voltage generation control 3 7 2 Functions 1 Successive approximation The AD converter has a resolution of 10 bits Some conversion time is required after starting conversion processing The conversion results are transferred to the AD conversion result registers ADRLC ADRHC 2 AD conversion selection resolution switching The AD converter supports two AD conversion modes 10 and 8 bit conversion modes so that the appropriate conversion resolution can be selected according to the operating conditions of the application The AD mode register ADMRC is used to select the AD conversion mode 3 6 channel analog input The signal to be converted is selected using the AD control register ADCRC from 6 types of analog signals input from 4 Conversion time selection The AD conversion time can be set from 1 1 to 1 128 frequency division ratio
26. WDT triggered reset occurs This flag can be rewritten with an instruction FIXO bit 6 Test bit This bit is available for testing purposes and must always be set to 0 WDTRUN bit 5 WDT operation control Setting this bit to 0 stops the WDT operation Setting this bit to 1 starts the WDT operation 4 18 1 870 00 Chapter 4 IDLOP1 bit 4 standby mode operation select IDLOPO bit 3 IDLOP1 IDLOPO WDT Standby Mode Operation Continue count operation 1 Suspend count operation while retaining the count value See Figure 4 5 2 for details of WDT operating modes WDTSL2 bit 2 bit 1 Overflow time select WDTSLO bit 0 WDTCT Set Count Number and Overflow WDTSL2 WDTSL1 WDTSLO Generation Time Example Count Number Low speed RC Clock 1024 34 1ms 4096 137ms 8192 273ms 16384 546ms 32768 1 09s 65536 2 18s 131072 4 37s Time values in the Low speed RC Clock column of the table refer to the time for a WDTCT overflow to occur when the low speed RC oscillation frequency is 30kHz typical The low speed RC oscillation frequency varies from IC to IC For details refer to the latest SANYO Semiconductors Data Sheet Note The WDTCNT is initialized to 00H when a low level is applied to the external RES pin or a reset is triggered by the internal reset POR LVD function Bits 4 to 0 of the WDTCNT are not initialized however when a WDT triggered reset oc
27. bit 0 T1L interrupt request enable control An interrupt request is generated to vector address 002BH when this bit and TILCMP are set to 1 Note TIHCMP and TILCMP must be cleared to O with an instruction 3 4 4 2 Timer 1 prescaler control register T1PRR 1 This register sets up the count values for the timer 1 prescaler 2 When the register value is changed while the timer is running the change is reflected in the prescaler operation at the same timing when the match buffer register for the timer is updated Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO FE19 0000 0000 R W TIPRR TIHPRE TIHPRC2 TIHPRCI TIHPRCO TILPRE TILPRC2 TILPRCI TILPRCO T1HPRE bit 7 Timer 1 prescaler high byte control T1HPRC2 bit 6 Timer 1 prescaler high byte control bit 5 Timer 1 prescaler high byte control T1HPRCO bit 4 Timer 1 prescaler high byte control T1HPRE T1HPRC2 T1HPRC1 T1HPRCO T1H Prescaler Count T1LPRE bit 3 Timer 1 prescaler low byte control T1LPRC2 bit 2 Timer 1 prescaler low byte control TA1LPRC 1 bit 1 Timer 1 prescaler low byte control TA1LPRCO bit 0 Timer 1 prescaler low byte control TILPRE T1LPRC2 T1LPRC1 T1LPRCO T1L Prescaler Count 3 29 3 4 4 3 Timer 1 low byte T1L 1 This is a read only 8 bit timer It counts up on the prescaler output clock Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4
28. can be transmitted via pin P17 3 Interrupt generation An interrupt request to vector address 001BH is generated if an interrupt request is generated by the base timer when the interrupt request enable bit is set The base timer can generate two types of interrupt requests base timer interrupt 0 and base timer interrupt 1 4 Itis necessary to manipulate the following special function registers to control the base timer BTCR ISL PIDDR P1 PIFCR Address Initial Value R W Name BIT8 BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO FE7F 0000 0000 BTCR BTFST BTON BTCIO BTIFI BTIEI BTIFO BTIEO 3 5 3 Circuit Configuration 3 5 3 1 8 bit binary up counter 1 This counter is an up counter that receives as its input the signal selected by the input signal select register ISL It generates a buzzer output signal base timer interrupt 1 flag set signal etc The overflow from this counter serves as the clock for the 6 bit binary counter 3 5 3 2 6 bit binary up counter 1 This counter is a 6 bit up counter that receives as its input the signal selected by the input signal select register ISL or the overflow from the 8 bit counter and generates set signals for base timer interrupts O and 1 The switching of the input clock is accomplished by the base timer control register BTCR 3 33 3 5 3 3 Base timer input clock source 1 Theclock input to the base timer fBST can be selected fr
29. conversion result registers ADRHC ADRLC 3 7 3 3 Multiplexer 1 MPX1 1 Multiplexer 1 is used to select the analog signal to be subject to AD conversion from 6 channels 3 7 3 4 Automatic reference voltage generator circuit 1 This circuit consists of a ladder resistor network and a multiplexer MPX2 and generates the reference voltage that is supplied to the comparator circuit Generation of the reference voltage is automatically started when an AD conversion starts and automatically stopped when the conversion ends The reference voltage output ranges from VDD to VSS 3 7 4 Related Registers 3 7 4 1 AD control register ADCRC 1 Thisregister is an 8 bit register that controls the operation of the AD converter AD AD AD AD AD AD FESS 0009 0000 ADORE CHSEL3 CHSEL2 CHSEL1 CHSELO APOD START ENDF ADIE ADCHSEL3 bit 7 ADCHSEL2 bit 6 ADCHSEL1 bit 5 ADCHSELO bit 4 AD conversion input signal select These 4 bits are used to select the signal to be subject to AD conversion AD AD AD AD CHSEL3 CHSEL2 CHSEL1 CHSELO 0 0 0 0 P10 ANO Signal Input Pin o o o mam o o o o o rom o 1 o was 3 49 ADC10 ADCRS bit 3 Fixed bit This bit must always be set to 0 ADSTART bit 2 AD converter operation control This bit starts 1 or stops 0 AD conversion processing Setting this bit to 1 starts AD conversion The bit is r
30. cycle i lt 2 12 0 100 gt 000 gt 1 1 K i DAT 08 j Buffer register lt M20MDi2 0 101 001 gt MP20Ti Pm 1 MP2OTIi E i lt M20MDi2 0 1 0 010 gt Buffer register 1 MP20Ti ie es 8 01 MP20Ti E lt M20MDi2 0 1 1 001 gt M20MDi2 0 Buffer register un MP2OTi E EE CE O A lt ues M2DT6 0 lt AD automatic start mode timing gt ADMDO ADMRC bit 3 1 M2PDRQ Soft processing Soft processing Soft processing 1 1 1 1 MAAEN 1 1 i ADSTART ADCRC bit2 AD automatic AD automatic conversion started conversion started 3 66 LC870NO00 Chapter Notes The PWM period M2PD9 to M2PDO is set to 1 cycle The dead time MP2OTi MP20Ti 0 i 0 1 is inserted at the following timings 1 MCPWM2 operation is started 2 MCPWM2 output mode is changed If the MCPWM2 output mode is set to 100 or 111 the dead time is inserted at the timings 3 and 4 below in addition to the above mentioned timings 1 and 2 3 Immediately before the rising edge of PWM and immediately after the falling edge 4 The duty cycle is changed from 0 M2MT9 to 2 2M2PD9 to M2PDO to near 100 M2MT9 to M2MT0 lt M2DT6 to M2DTO M2MT9 0 i 1 1 Match buffer X M2MT9 0z M2PD9 0 X 2 79 0 lt 2076 0 X register 1 PWM I 1 NPWM E NoDT 0 M2MTO9 0 gt M2MT9 0
31. flag PDN Operating Mode 0 Normal or HALT mode 1 This bit must be set with an instruction When the microcontroller enters HOLD mode all oscillations high medium speed RC are suspended and bits 1 and 4 of the OCR register are cleared When the microcontroller exits HOLD mode medium speed RC oscillator starts operation and is designated as the system clock source The high speed RC oscillator stops operation 2 15 cleared when a HOLD mode release signal INTO INT2 or a reset signal occurs 3 BitO is automatically set when PDN is set 4 7 System Clock IDLE bit 0 HALT mode seiting flag 1 Setting this bit places the microcontroller into HALT mode 2 This bit is automatically set when bit 1 is set 3 This bit is cleared on acceptance of an interrupt request or on receipt of a reset signal 4 2 4 3 Oscillation control register OCR 1 This register is a 3 bit register that controls the operation of the oscillator circuits and selects the system clock Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO FEOE OHHOHHOH R W CLKSGL CLKCB4 RCSTOP CLKSGL bit 7 Clock division ratio select 1 When this bit is set to 1 the clock selected by bit 4 is used as the system clock as is 2 When this bit is set to 0 the clock having a division ratio of 2 of the clock selected by bit 4 is used as the system clock Bits 6 5 3 2
32. is running 4 4 2 Functions This series of microcontrollers provides the following three types of reset functions 1 External reset via the RES pin The microcontroller is reset without fail by applying a low level to the RES pin for 200us or longer Note however that low level of a small duration less than 200us is likely to trigger a reset The RES pin can serve as a power on reset pin when it is provided with an external time constant element 2 Internal reset The internal reset function is available in two types the power on reset POR that triggers a reset when power is turned on and the low voltage detection reset LVD that triggers a reset when the power voltage falls below a certain level Options are available to set the power on reset release level to enable use and disable non use the low voltage detection reset function and to set its threshold level 3 Reset function using a watchdog timer The watchdog timer of this series of microcontroller can be used to generate a reset by the internal low speed RC oscillator at a predetermined time interval An example of a reset circuit is shown in Figure 4 4 1 The external circuit connected to the reset pin shows an example that the internal reset function is disabled and an external power on reset circuit is configured Interior of microcontroller Exterior of microcontroller Watchdog Internal low speed timer WDT RC oscillator Int reset
33. is set to level detection capture signals are generated at an interval of 1 Tcyc as long as the detection level is present at P15 When this bit is set to 0 a timer OH capture signal is generated when an input that satisfies the INT3 interrupt detection conditions is supplied to P11 1 870 00 Chapter 3 STOLCP bit 6 Timer OL capture signal input port select This bit selects the timer OL capture signal input port When this bit is set to 1 a timer OL capture signal is generated when an input that satisfies the INTO interrupt detection conditions is supplied to P14 If the INTO interrupt detection mode is set to level detection capture signals are generated at an interval of 1 Tcyc as long as the detection level is present at P14 When this bit is set to 0 a timer OL capture signal is generated when an input that satisfies the INT2 interrupt detection conditions is supplied to P10 BTIMC1 bit 5 Base timer clock select BTIMCO bit 4 Base timer clock select BTIMC1 BTIMCO Base Timer Input Clock 0 Inhibited Cycle clock 0 mo d Timer counter 0 prescaler output BUZON bit 3 Buzzer output select This bit enables the buzzer output fBST 16 or fBST 256 When this bit is set to 1 a signal that is obtained by dividing the base timer clock by 16 or 256 is sent to port P17 as buzzer output When this bit is set to 0 the buzzer output is fixed high NFSEL bit 2 Noise filter time constant select NFON
34. lt 16 bit programmable timer gt with programmable prescaler Figure 3 3 3 Mode 2 Block Diagram TOLONG 1 TOLEXT 0 Capture Capture trigger TOCAH TOCAL Registers 01 FE5Dh Capture I23CR and ISL External Clock FE5Fh need setting input Set in register ISL FE5Fh Match TOLCMP Match buffer register TOHCMP Relaod flag set TOHR TOLR lt 6 bit programmable counter Figure 3 3 4 Mode 3 Block Diagram TOLONG 1 TOLEXT 1 3 17 To 3 3 4 Related Registers 3 3 4 1 Timer counter 0 control register TOCNT 1 Thisregister is an 8 bit register that controls the operation and interrupts of TOL and TOH Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE10 0000 0000 R W TOCNT TOLRUN TOLONG TOLEXT TOHCMP TOHIE TOLCMP TOHRUN bit 7 TOH count control When this bit is set to 0 timer counter 0 high byte TOH stops on a count value of 0 The match buffer register of TOH has the same value as TOHR When this bit is set to 1 timer counter 0 high byte TOH performs the required counting operation The match buffer register of TOH is loaded with the contents of TOHR when a match signal is generated TOLRUN bit 6 TOL count control When this bit is set to 0 timer counter 0 low byte TOL stops on a count value of 0 The match buffer register of TOL has the same value as TOLR When this bit is set to 1
35. mode 2 The match buffer register is updated as follows When it is inactive TOHRUN O the match buffer register matches TOHR When it is active TOHRUN 1 the match buffer register is loaded with the contents of TOHR when a match signal is generated Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO 15 0000 0000 R W TOHR TOHR7 TOHR6 TOHRS TOHR4 TOHR3 TOHR2 TOHRI TOHRO 3 19 e 3 3 4 7 Timer counter 0 capture register low byte TOCAL 1 This register is a read only 8 bit register used to capture the contents of timer counter 0 low byte TOL on an external input detection signal Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO FEI6 XXXX XXXX R TOCAL TOCAL7 TOCAL6 TOCALS TOCALA TOCAL3 TOCAL2 TOCALI TOCALO 3 3 4 8 Timer counter 0 capture register high byte TOCAH 1 This register is a read only 8 bit register used to capture the contents of timer counter 0 high byte TOH on an external input detection signal Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE17 XXXX XXXX R TOCAH TOCAH7 TOCAH6 TOCAHS TOCAH4 TOCAH3 TOCAH2 TOCAHI TOCAHO 3 20 LC870NO00 Chapter 3 4 Timer 1 T1 3 4 1 Overview The timer 1 T1 incorporated in this series of microcontrollers is a 16 bit timer that provides the following four functions 1 2 3 4 3 4 2 1 2 3 Mode 0 8 bit program
36. see also paragraph 1 of Subsection 4 6 7 Set the LVD reset function option to Disable and select 1 67 as the POR release level option Set operating range VDD 3 1V External 3 0V detection circuit POR release voltage PORRL Typ 1 67V Note 5 The operation guarantee values voltage operating frequency shown in the examples vary with the microcontroller type Be sure to see the latest SANYO Semiconductors Data Sheet and select the appropriate setting level 4 23 Internal Reset 4 6 5 Sample Operating Waveforms of the Internal Reset Circuit 1 2 Waveform observed when only POR is used LVD not used Reset pin Pull up resistor Rggs only POR release voltage PORRL Undefined state POUKS RES There exists an undefined state POUKS before the transistor starts functioning normally The POR function generates a reset only when power is turned on starting at the VSS level The reset release voltage in this case may have some range Refer to the latest SANYO Semiconductors Data Sheet for details No stable reset will be generated if power is turned on again when the power level does not go down to the VSS level as shown in a If such a case is anticipated use the LVD function together as explained in 2 or implement an external reset circuit A reset is generated only when the power level goes down to the VSS level and power is turned on again after this condition co
37. set to 1 port POn becomes an input with a pull up resistor Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE41 HHHH 0000 R W PODDR PO3DDR PO2DDR POIDDR POODDR Port 0 Register Data Port POn State Internal Pull up POn POnDDR Input Output Resistor Enabled Open OFF a Disabled Disabled enabled Hoe 3 CMOS N channel open drain 3 1 3 3 Port 0 function control register POFCR 1 Thisregister is a 4 bit register that controls the multiplexed pin outputs of port 0 Address Initial Value R W Name BIT7 6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE42 HHHH 0000 R W POFCR CLKOEN CKODV2 CKODVI CLKOEN bit 3 This bit controls the output data of pin P02 It is disabled when 2 is in input mode When P02 is in output mode 0 Carries the value of the port data latch 1 Carries the OR of the system clock output and the value of the port data latch CKODV2 bit 2 CKODV1 bit 1 CKODVO bit 0 These bits define the frequency of the system clock to be placed at P02 000 Frequency of source oscillator selected as system clock 001 1 2 of frequency of source oscillator selected as system clock 010 1 4 of frequency of source oscillator selected as system clock 011 1 8 of frequency of source oscillator selected as system clock 100 1 16 of frequency of source oscillator selected as system clock 101 1
38. sg lr e Lee cel cioe e Er cns RSEN IRE DR ENT loe rec sw Loos oe ap tiae lec ge reme The output of comparator 1 and comparator 2 is set low when each comparator is stopped P17FCR bit 7 P17 function control timer 1 PWMH or base timer buzzer output control This bit controls the output data at pin P17 When P17 is placed in output mode P17DDR 1 and P17FCR is set to 1 the EOR of the timer 1 PWMH output or base timer buzzer output data and the port data latch is placed at pin P17 PWMH output from timer 1 or buzzer output from the base timer can be selected by controlling BUZON ISL FESF bit 3 3 7 Port 1 P16FCR bit 6 P16 function control timer 1 PWML output control This bit controls the output data at pin P16 When P16 is placed in output mode P16DDR 1 and P16FCR is set to 1 the EOR of the timer 1 PWML output data and the port data latch is placed at pin P16 P15FCR bit 5 P15 function control SIO1 clock output control This bit controls the output data at pin P15 When P15 is placed in output mode PISDDR 1 and CP2OUTEN is set to 0 and PI5FCR is set to 1 the OR of the SIO1 clock output data and the port data latch is placed at pin P15 P14FCR bit 4 P14 function control SIO1 data output control This bit controls the output data at pin P14 When P14 is placed in output mode PI4DDR 1 and P14FCR is set to 1 the OR of the SIO1 output data and the port data latch i
39. signal T Internal reset circuit POR LVD Figure 4 4 1 Sample Reset Circuit Block Diagram 4 14 LC870N00 Chapter 4 4 4 3 Reset State When a reset is generated by the RES pin internal reset circuit or watchdog timer the hardware functional blocks of the microcontroller are initialized by a reset signal that is in synchronization with the system clock Since the system clock is switched to the internal medium speed RC oscillator when a reset occurs hardware initialization is also performed immediately even when the power is turned on The system clock must be switched to the main clock when the main clock is stabilized The program counter is initialized to OOOOH on a reset See Appendix A D Special Function Register SFR Map for the initial values of the special function registers SFR Notes and precautions The stack pointer is initialized to 0000H Data RAM is not initialized by a reset Consequently the contents of RAM are undefined when power is turned on When using the internal reset function it is necessary to implement and connect an external circuit to the reset pin according to the user s operating environment Be sure to review and observe the operating specifications circuit configuration precautions and considerations discussed in Section 4 6 Internal Reset Function 4 15 WDT 4 5 Watchdog Timer WDT 4 5 1 Overview This series of microcontrollers is provided wit
40. signal is generated when the value of this match buffer register matches the value of timer 1 low byte TIL The match buffer register is updated as follows e When it is inactive TILRUN O the match buffer register matches TILR When it is active TILRUN 1 the match buffer register is loaded with the contents of TILR when the value of reaches 0 3 24 LC870NO00 Chapter 3 4 3 8 Timer 1 match data register high byte T1HR 8 bit register with a match buffer register 1 This register is used to store the match data for T1H It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register matches the value of timer 1 high byte T1H 2 The match buffer register is updated as follows e When it is inactive TIHRUN O the match buffer register matches TI HR When it is active TIHRUN 1 the match buffer register is loaded with the contents of when the value of T1H reaches 0 3 4 3 9 Timer 1 low byte output T1PWML 1 The TIPWML output is fixed at a high level when TIL is inactive If TIL is active the TIPWML output is fixed at a low level when TILR FFH 2 When TIPWM timer 1 control register bit 4 is set to 0 timer 1 low byte output is a toggle output whose state changes on a match signal 3 When TIPWM timer 1 control register bit 4 is set to 1 timer 1 low byte output is a PWM output that is cleared on a TIL overflow and set on a T1L m
41. source and the PWM clock can be selected by setting M2CKD2 to M2CKD0 MCPWM2 control register bits 2 to 0 When this bit is set to 1 the source clock of the system clock is selected as the PWM clock source Setting M2CKD2 to M2CKD0 MCPWM2 control register bits 2 to 0 is then invalid and the frequency division ratio is fixed to 1 1 2 bit 3 MP20T1 output pin control Setting this bit to 0 disables the 2 output Setting this bit to 1 enables the MP2OT1 output from pin 20 1 bit 2 MP2OT1 output pin control Setting this bit to 0 disables the MP2OT1 output Setting this bit to 1 enables the MP2OTI output from pin P02 M2OTEOB bit 1 MP2OTO output pin control Setting this bit to 0 disables the MP2OTO output Setting this bit to 1 enables the MP2OTO output from pin POI M2OTEO bit 0 MP2OTO output pin control Setting this bit to 0 disables the MP2OTO output Setting this bit to 1 enables the MP2OTO output from pin POO Notes The setting of M2CKSL cannot be changed while the MCPWM2 is running M2PWMEN 1 If M2CKSL is to be set to 1 use a system clock frequency division ratio of 1 2 by setting CLKSGL oscillation control register bit 7 to 0 and CLKDV2 to CLKDVO system clock divider control register bits 2 to 0 to 000 Any other setting is inhibited e Since MP20Ti MP2OTi i 0 1 are logically ORed with the port latch data on output the port latch data must be
42. timer counter 0 low byte TOL performs the required counting operation The match buffer register of TOL is loaded with the contents of TOLR when a match signal is generated TOLONG bit 5 Timer counter 0 bit length select When this bit is set to 0 timer counter 0 high and low order bytes function as independent 8 bit timers counters When this bit is set to 1 timer counter 0 functions as a 16 bit timer counter A match signal is generated when the count value of the 16 bit counter comprising TOH and TOL matches the contents of the match buffer registers of TOH and TOL TOLEXT bit 4 TOL input clock select When this bit is set to 0 the count clock for TOL is the match signal for the prescaler When this bit is set to 1 the count clock for TOL is an external input signal TOHCMP bit 3 TOH match flag This bit is set when the value of TOH matches the value of the match buffer register for TOH and a match signal is generated while is running TOHRUN 1 Its state does not change if no match signal is generated Consequently this flag must be cleared with an instruction In the 16 bit mode TOLONG 1 a match must occur in all 16 bits of data for a match signal to occur TOHIE bit 2 TOH interrupt request enable control When this bit and TOHCMP are set to 1 an interrupt request to vector address 0023H is generated TOLCMP bit 1 TOL match flag This bit is set when the value of TOL matches the value of the match buffer r
43. 0 These bits do not exist They are always read as 1 CLKCBA bit 4 System clock select 1 CLKCBA is used to select the system clock 2 CLKCBA is cleared at reset time or when HOLD mode is entered CLKCB4 System Clock 0 Medium speed RC oscillator High speed RC oscillator RCSTOP bit 1 Internal medium speed RC oscillator circuit control 1 Setting this bit to 1 stops the internal medium speed RC oscillator circuit 2 Setting this bit to O starts the internal medium speed RC oscillator circuit 3 When a reset occurs this bit is cleared and the oscillator circuit is enabled for oscillation 4 When the microcontroller enters HOLD mode this bit is cleared The oscillator starts oscillation and is designated as the system clock source when the microcontroller exits HOLD mode 4 243 High speed RC oscillation control register OCR3 1 This register is a 1 bit register that controls the operation of the high speed RC oscillator circuit and selects the main clock Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 2 BIT1 BITO FE7C HOHH HHHH R W OCR3 FRCSTART FRCSTART bit 6 High speed RC oscillation start control 1 Alinthis bit starts the high speed RC oscillator circuit 2 this bit stops the high speed RC oscillator circuit 3 This bit is cleared when the microcontroller enters HOLD mode Note When switching the system clock secure an oscillation stabiliz
44. 0 0000 R W SCONI SIIMI SIIMO SIIRUN SIIREC SIIDIR SIIOVR SIIEND SIE SI1M1 bit 7 SIO1 mode control SI1MO bit 6 SIO1 mode control Table 3 6 2 5101 Operating Modes SH 0 Operating Mode Synchronous 8 bit SIO UART 1 stop bit no parity SIT RUN bit 5 SIO1 operation flag 1 Alinthis bit indicates that SIO1 is running 2 See Table 3 6 1 for the conditions for setting and clearing this bit SI REC bit 4 SIO1 receive transmit control 1 Setting this bit to 1 places SIO1 into receive mode 2 Setting this bit to 0 places 5101 into transmit mode SI DIR bit 3 MSB LSB first select 1 Setting this bit to 1 places SIO1 into MSB first mode 2 Setting this bit to 0 places SIO1 into LSB first mode SI OVR bit 2 SIO1 overrun flag 1 This bit is set when the falling edge of the input clock is detected with SITRUN 0 in mode 1 2 or 3 2 This bit is set if the conditions for setting SITEND are established when SILEND 1 3 In mode 3 this bit is set when the start condition is detected 4 This bit must be cleared with an instruction SIT END bit 1 Serial transfer end flag 1 This bit is set when serial transfer terminates see Table 3 6 1 2 This bit must be cleared with an instruction SI1IE bit 0 SIO1 interrupt request enable control When this bit and SITEND are set to 1 an interrupt request to vector address 003BH is generated 3 46 1 870 00 Chapter 3 6 5 2 Serial b
45. 000 R W TICNT TIHRUN TILRUN TILONG TIPWM TIHIE TILCMP 1H nm rur nme rms Note 1 The output of TIPWML is fixed at a high level if TIL is stopped If TIL is running the output of TIPWML is fixed at a low level when TILR FFH The output of TIPWMH is fixed at a high level if T1H is stopped If T1H is running the output of TIPWMH is fixed at a low level when TIHR FFH 3 22 LC870NO0 Chapter 3 4 3 Circuit Configuration 3 4 81 Timer 1 control register TICNT 8 bit register 1 This register controls the operation and interrupts of TIL and 3 4 3 2 Timer 1 prescaler control register T1PRR 8 bit counter 1 This register sets the clocks for TIL and 3 4 3 3 Timer 1 prescaler low byte 8 bit counter 1 Start stop Stop start is controlled by the 0 1 value of TILRUN timer 1 control register bit 6 2 Countclock Depends on the operating mode Mode T1LONG T1PWM T1L Prescaler Count Clock 2 Tcyc _ 1 o o 1 Jj 2211 eye 3 Prescaler count Determined by the TIPRC value The count clock for T1L is output at intervals determined by the prescaler count T1LPRE T1LPRC2 T1LPRC1 T1LPRCO T1L Prescaler Count 3 23 3 4 34 Timer 1 prescaler high byte 8 bit counter 1 2 3 4 3 4 3 5 2 3 4 3 4 3 6 2 3 4 3 4 3 7 2
46. 1 value of TOLRUN timer counter 0 control register bit 6 Count clock Either a prescaler match signal or an external signal must be selected through the 0 1 value of TOLEXT timer counter 0 control register bit 4 Match signal A match signal is generated when the count value matches the value of the match buffer register 16 bits of data must match in the 16 bit mode Reset When the counter stops operation or a match signal is generated Timer counter 0 high byte 8 bit counter Start stop Stop start is controlled by the 0 1 value of TOHRUN timer counter 0 control register bit 7 Count clock Either a prescaler match signal or a TOL match signal must be selected through the 0 1 value of TOLONG timer counter 0 control register bit 5 Match signal A match signal is generated when the count value matches the value of the match buffer register 16 bits of data must match in the 16 bit mode Reset When the counter stops operation or a match signal is generated Timer counter 0 match data register low byte TOLR 8 bit register with a match buffer register This register is used to store the match data for TOL It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register matches the value of the low order byte of timer counter 0 16 bits of data must match in the 16 bit mode The match buffer register is updated as follows When it is inactive TOLRUN 0 the
47. 1234H PUSH 349 Loads the stack with byte data 34H ADD 56H Adds byte data 56H to the accumulator BE 78H L1 Compares byte data 78H with the accumulator for a branch 2 6 LC870N00 Chapter 2 2 11 2 Indirect Register Indirect Addressing Rn In indirect register indirect addressing mode it is possible to select one of the indirect registers RO to R63 and use its contents to designate an address in RAM or SFR When the selected register contains for example 2 it designates C register Example When R3 contains 123H RAM address 6 23H RAM address 7 01H LD R3 Transfers the contents of RAM address 123H to the accumulator 11 STW R3 Transfers the contents of the BA register pair to RAM address 123H PUSH R3 Saves the contents of RAM address123H in the stack SUB R3 Subtracts the contents of RAM address 123H from the accumulator DBZ R3 L1 Decrements the contents of RAM address 123H by 1 and causes a branch if Zero 2 11 3 Indirect Register C Register Indirect Addressing Rn C In the indirect register C register indirect addressing mode the result of adding the contents of one of the indirect registers RO to R63 to the contents of the C register 128 to 127 with MSB being the sign bit designates an address in RAM or SFR For example if the selected indirect register contains FE02H and the C register contains 1 the address B register FE02H 1 FEO1H i
48. 1V 2 01V 2 31V 2 51V 2 81V 3 79V and 4 28V can be selected by setting options 1 3 Standby function HALT mode Halts instruction execution while allowing the peripheral circuits to continue operation 1 Oscillators do not stopped automatically 2 There are three ways of releasing HALT mode lt 1 gt Low level input to the reset pin lt 2 gt Generating a reset by the watchdog timer or low voltage detection lt 3 gt Generating an interrupt HOLD mode Suspends instruction execution and the operation of the peripheral circuits 1 Thehigh medium speed RC oscillators automatically stop operation 2 There are three ways of releasing HOLD mode lt 1 gt Low level input to the reset pin lt 2 gt Generating a reset by the watchdog timer or low voltage detection lt 3 gt Establishing an interrupt source at least at one of INTO INT1 and INT2 INTO and INTI HOLD mode release is available only when level detection is set On chip debugger function Supports software debugging with the microcontroller mounted on the target board Data security function flash versions only Protects the program data stored in flash memory from unauthorized read or copy Note This data security function does not necessarily provide absolute data security e Package form SSOP16 225 mil lead free and halogen free product Development tools On chip debugger TCB87 Type C LC87F0N04A Programming board Package Pr
49. 2PDH MP2MTL MP2MTH MP2DT MP2CR2 3 56 LC870NO0 Chapter Address Initial BIT7 BIT6 BITS BIT4 BIT3 BIT2 BITO FE90 00000000 2 M2PWMEN M2PWMMD M20PL m20PLB 2 M2CKD2 2 1 M2CKD0 FE92 Hooo Hooo Rw MP2OMDO M2OMDI2 M2OMD02 M2OMD01 M2OMD00 reos HHHHHHOO R w reo Rw rw Mpapr woprs M2DT3 M2DT2 M2DTI FE9D rw Mp2cr2 morei M2OTEOB M2OTEO 3 8 3 Circuit Configuration 3 8 3 1 MCPWM2 control register MP2CR 8 bit register 1 This register controls the operation of the MCPWM2 the output polarity the AD converter automatic start mode and the frequency division ratio of the operation clock 3 8 3 2 2 interrupt control register MP2ICR 8 bit register 1 Thisregister controls MCPWM2 interrupt processing 2 Theregister also controls the forced output stop of MCPWM2 3 8 3 3 Operation clock generator circuit 1 This circuit generates an operation clock whose frequency is a 1 1 1 2 1 4 1 8 1 16 or 1 32 frequency division of the system clock under control of the PWM clock frequency division ratio select register
50. 3 o 1 1021 o Opo ot ee f f e CMP10OUT bit 3 Comparator 1 output data Reading this bit makes the comparator 1 output data available This bit is read only A 0 is read when comparator is stopped CMP1EG bit 2 Comparator 1 interrupt source control Setting this bit to 0 selects the falling edge detection mode for the comparator 1 interrupt source Setting this bit to 1 selects the rising edge detection mode for the comparator 1 interrupt source The setting in this bit is invalid when comparator 1 is stopped CMP1IF bit 1 Comparator 1 interrupt source This bit is set when the comparator output edge set by the comparator interrupt source control is detected The bit is not set however if comparator is stopped This flag must be cleared with an instruction CMP1IE bit 0 Comparator 1 interrupt enable control An interrupt request to vector address 004BH is generated when this bit and CMPIIF are set to 1 3 72 LC870NO0 Chapter 3 9 4 2 Comparator 2 control register CPAPCR2 1 This register is a 6 bit register that is used to control the operation and interrupts of comparator 2 Address Initial Value R W Name BIT7 BIT6 BITS BIT4 2 BIT1 BITO FEA1 0000 R W 2 CPAP2EN CP20UTEN CMP2OUT CMP2EG CMP2IF CMP2IE Bit 3 CMP20UT is read only CPAP2EN bit 7 Compar
51. 32 of frequency of source oscillator selected as system clock 110 1 64 of frequency of source oscillator selected as system clock 111 Inhibited lt Notes on the use of the clock output function gt Follow notes 1 to 3 given below when using the clock output function Anomalies may be observed in the waveform of the port clock output if these notes are violated 1 Do not change the frequency division setting of the clock output when CLKOEN bit 3 is set to 1 Do not change the settings of CKODV2 to CKODVO bits 2 to 0 2 Do not change the system clock selection when CLKOEN bit 3 is set to 1 Do not change the setting of CLKCBA bit 4 of the OCR register 3 CLKOEN will not go to 0 immediately even when the user executes an instruction that loads the POFCR register with data that sets the state of CLKOEN bit 3 from 1 to 0 CLKOEN is set to 0 at the end of the clock that is being output on detection of the falling edge of the clock Accordingly when changing the clock frequency division setting or changing the system clock selection after setting CLKOEN to 0 with an instruction be sure to read the CLKOEN value in advance and make sure that it is 0 3 2 LC870NO00 Chapter 3 3 1 4 Options Two user options are available 1 CMOS output with a programmable pull up resistor 2 N channel open drain output with a programmable pull up resistor 3 1 5 HALT and HOLD Mode Operation When in HALT or HOLD mode port 0 retains th
52. BIT2 BIT1 BITO FE97 HHHH HH00 MP2MTH 2 79 2 8 M2MT9 to 2 0 PWM match count setting These bits define the PWM match count value PWM match count value Set value x 10 bit counter clock period Note Bits M2MT9 to M2MTO are loaded into the buffer register when the state of the 2 bit MCPWM2 control register bit 7 is switched from 0 to 1 and at the end of every cycle 3 8 4 8 Dead time setting register MP2DT 1 This register is a 7 bit register that is used to set the dead time Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE9C 000 0000 R W MP2DT M2DT6 M2DT5 M2DT4 M2DT3 M2DT2 2 M2DTO M2DT6 to M2DTO Dead time setting These bits define the dead time Dead time Set value x 10 bit counter clock period Notes Bits M2DT6 to M2DTO are loaded into the buffer register when the state of the M2JPWMEN bit MCPWM2 control register bit 7 is switched from 0 to 1 Set M2DT6 to M2DTO lt M2PD9 to M2PDO 3 63 MCPWM2 3 8 4 9 2 control register 2 MP2CR2 1 This register is a 5 bit register that controls the PWM clock and output pins Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE9D OHHH 0000 R W MP2CR2 M2CKSL M2OTEIB M2OTEI M2OTEOB M2OTEO M2CKSL bit 7 PWM clock source select When this bit is set to 0 the system clock is selected as the PWM clock
53. BIT3 BIT2 BIT1 BITO FEIA 0000 0000 R TIL TIL7 T1L6 TILS TILA TIL3 TIL2 TILI TILO 3 4 4 4 Timer 1 high byte T1H 1 This is a read only 8 bit timer It counts up prescaler output clock Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEIB 0000 0000 R 6 5 4 T1H3 T1H2 T1HO 3 4 4 5 Timer 1 match data register low byte T1LR 1 This register is used to store the match data for TIL It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register matches the value of timer 1 low byte 2 The match buffer register is updated as follows When it is inactive TILRUN O the match buffer register matches TILR When it is active TILRUN 1 the match buffer register is loaded with the contents of TILR when the value of TIL reaches 0 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO FEIC 0000 0000 R W TILR TILR7 TILR6 TILRS TILR4 TILR3 TILR2 TILRI TILRO 3 4 4 6 Timer 1 match data register high byte T1HR 1 This register is used to store the match data for T1H It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register matches the value of timer 1 high byte 2 The match buffer register is updated as follows When it is inactive TIHRUN O the match buffer register matches e When it is active TIHR
54. Base timer interrupt 1 period control BTFST BTC11 BTC10 Base Timer Interrupt 0 Period Base Timer Interrupt 1 Period 0 0 0 16384fBST 32fBST Lm T j nr ____ 1 0 1 E _ 1 o Gr fBST The frequency of the input clock selected by the input signal select register ISL BTIF1 bit 3 Base timer interrupt 1 flag This flag is set at the interval of the base timer interrupt 1 period that is defined by BTFST BTC11 and BTC10 This flag must be cleared with an instruction BTIE1 bit 2 Base timer interrupt 1 request enable control Setting this bit and BTIFI to 1 generates an interrupt request to vector address 001BH BTIFO bit 1 Base timer interrupt 0 flag This flag is set at the interval of the base timer interrupt 0 period that is defined by BTFST BTC11 and BTC10 This flag must be cleared with an instruction BTIEO bit 0 Base timer interrupt 0 request enable control Setting this bit and BTIFO to 1 generates an interrupt request to vector address 001BH Notes Note that BTIF1 is likely to be set to 1 when BTC11 and BTC10 are rewritten If HOLD mode is entered while running the base timer when the cycle clock is selected as the base timer clock source the base timer is subject to the influence of unstable oscillations caused by the main clock when they are started following the release of HOLD mode resulting in an erroneous count from the base tim
55. CMOS 8 BIT MICROCONTROLLER LC870N00 SERIES 2 USER S MANUAL REV 1 00 ON Semiconductor Digital Solution Division Microcontroller amp Flash Business Unit ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries LLC SCILLC SCILLC owns the rights to a number of patents trademarks copyrights trade secrets and other intellectual property A listing of SCILLC s product patent coverage may be accessed at www onsemi com site pdf Patent Marking pdf SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or
56. CON OCR CLKDIV OCR3 Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO FE07 HHHH R W PCON PDN IDLE nooo ww ev jexem mec L L T 4 20 3 Circuit Configuration 4 2 3 1 Internal medium speed RC oscillator circuit conventional RC oscillator circuit 1 The medium speed RC oscillator circuit oscillates according to the internal resistor and capacitor at 1MHz typical 2 clock from medium speed RC oscillator is designated as the system clock after the reset 15 released or HOLD mode is exited 4 2 3 2 High speed RC oscillator circuit 1 The high speed RC oscillator circuit oscillates according to the internal resistor and capacitor 2 source oscillation frequency is 20MHz The highest clock rate setting is 1OMHz that is obtained by dividing the source oscillation frequency by 2 3 Thecircuit toggles out a clock each time the counter value matches the preset count value 4 2 3 3 Power control register PCON 2 bit register 1 Thisregister specifies the operating mode normal HALT HOLD 4 2 3 4 Oscillation control register OCR 3 bit register 1 Thisregister controls the start stop operations of the oscillator circuits 2 This register selects the system clock
57. D mode All oscillations are suspended The microcontroller suspends the execution of instructions and its peripheral circuits stop processing HOLD mode is entered by setting bit 1 of the PCON register to 1 In this case bit 0 of the PCON register HALT mode setting flag is automatically set When a reset occurs or a HOLD mode release signal INTO INT1 or INT2 occurs bit 1 of the PCON register is cleared and the microcontroller switches into HALT mode Note Do not allow the microcontroller to enter HALT or HOLD mode while AD conversion is in progress Make sure that ADSTART is set to 0 before placing the microcontroller into one of the above mentioned standby modes 4 3 3 Related Register 4 3 3 1 Power control register PCON 2 bit register 1 Thisregister is a 2 bit register that specifies the operating mode normal HALT HOLD Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEO7 HHHH R W PCON PDN IDLE Bits 7 to 2 These bits do not exist They are always read as 1 4 10 LC870NO0 Chapter 4 PDN bit 1 HOLD mode setting flag Operating Mode 0 Normal or HALT mode 1 This bit must be set with an instruction When the microcontroller enters HOLD mode all oscillations medium speed RC and high speed RC are suspended and bits and 4 of the OCR register are cleared When the microcontroller exits HOLD mode medium speed RC oscillator resumes
58. DLOPI and IDLOPO are set to 1 In this case WDTRUN is cleared Clearing the WDTCT When the watchdog timer starts operation WDTCT counts up When this WDTCT overflows a WDT reset occurs To run the program in normal mode it is necessary to periodically clear WDTCT before WDTCT overflows Execute the following instruction to clear WDTCT while it is running MOV 55H WDTCNT Detecting a runaway condition Unless the above mentioned instruction is executed periodically WDTCT overflows because the watchdog timer is not cleared If an overflow occurs the watchdog timer considers that a program runaway has occurred and triggers a WDT reset In this case WDTRSTF WDTCNT bit 7 is set After a WDT reset occurs the program execution restarts at address 0000H 4 5 6 Notes on the Use of the Watchdog Timer To realize ultra low power operation using HOLD mode it is necessary to disable the watchdog timer from running in HOLD mode by setting IDLOPI and IDLOPO to 1 or 2 When setting IDLOP1 and IDLOPO to 0 or 3 several uA of operating current flows at all times because the internal low speed RC oscillator circuit continues oscillation even in HOLD mode If standby mode HALT HOLD is entered when the watchdog timer is running with IDLOP1 and IDLOPO set to 2 the low speed RC oscillator circuit stops oscillation and the watchdog timer stops counting and retains the count value When the microcontroller subsequently exits standby mode the low spe
59. Division Microcontroller amp Flash Business Unit
60. ITRUN transfer a start bit SBUFI 8 bits stop bit H 5 Checking address data after an interrupt Read SBUFI SBUFI has been loaded with serial data from the data I O port even in transmission mode When SBUFI is read in the data about the position of the stop bit is read into bit 1 of the PSW Check for an acknowledge by reading bit 1 of the PSW If a condition for losing the bus contention occurs see Note 1 in Table 3 6 1 no interrupt will be generated as SITRUN is cleared in that case If there is a possibility of a condition for losing the bus contention such as the presence of a separate master mode device find out such condition by for example performing timeout processing using a timer module 3 43 SIO1 6 7 8 9 10 3 6 4 4 2 3 Sending data Load SBUFI with output data e Clear SILEND and exit interrupt processing transfer SBUFI 8 bits stop bit H Checking transmission data after an interrupt Read SBUFI SBUFI has been loaded with serial data from the data I O port even in transmission mode When SBUFI is read in the data about the position of the stop bit is read into bit 1 of the PSW Check for an acknowledge by reading bit 1 of the PSW fa condition for losing the bus contention occurs see Note 1 in Table 3 6 1 no interrupt will be generated as 1 is cleared in that case If there is a possibility of a condition for losing the bus conten
61. LEND and 5 then exit interrupt processing Return to step 4 when repeating processing Bus slave mode mode 3 Setting the clock Setup SBRI to set the acknowledge data setup time Setting the mode Set as follows SIIMO 1 SIIMI 1 SIIDIR SIIIE 1 SIIREC 0 Setting up ports Set up the clock port P15 and data port P14 as N channel open drain output by specifying the option Set P14 P1 bit 4 and P15 P1 bit 5 to 0 Set PIAFCR PIFCR bit 4 and PISFCR 1 bit 5 to 1 Set PIADDR PIDDR bit 4 and PISDDR PIDDR bit 5 to 1 3 44 4 5 6 7 LC870NO00 Chapter Starting communication waiting for an address e Set SIITREC 2 e SIIRUN is automatically set on detection of a start bit Perform a receive operation 8 bits then set the clock output to 0 on the falling edge of the 8th clock after which an interrupt occurs Checking address data after an interrupt Detecting a start condition sets SILOVR Check SIITRUN 1 and 1 to determine if the address has been received 5 is not automatically cleared Clear it by instruction Read SBUF1 and check the address If no address match occurs clear SILRUN and SIIEND and exit interrupt processing then wait for a stop condition detection at in step 8 Receiving data Clear SILEND and exit interrupt processing If a receive sequence has been performed send an acknowledge and release th
62. MEN bit MCPWM2 control register bit 7 is switched from 0 to 1 The match buffer register is loaded with the contents of MP2MTL and MP2MTH at the end of a cycle 3 8 3 7 Dead time setting register MP2DT 7 bit register with a buffer register 2 This register stores the data that sets the dead time It is provided with a 7 bit buffer register The NPWM signal is generated by this buffer register 10 bit counter and PWM match buffer register The buffer register is updated as follows The buffer register is loaded with the contents of MP2DT when the state of the M2PWMEN bit MCPWM2 control register bit 7 is switched from 0 to 1 3 8 3 8 PWM signal generator circuit The PWM NPWM signals are generated by the values of the 10 bit counter dead time setting buffer register and PWM match count setting match buffer register 3 8 3 9 2 output mode select register MP2OMDO 2 3 8 3 10 6 bit register with a buffer register This register stores the data that selects the output mode of the MCPWM2 It is provided with a 6 bit buffer register This buffer register is used to control MP2OTi MP2OTY outputs 1 0 1 The buffer register is updated as follows The buffer register is loaded with the contents of 2 when the state of the MZ2PWMEN MCPWM2 control register bit 7 is switched from 0 to 1 The buffer register is loaded with the contents of 2 at the end of a
63. Mrbuzerowpu AD input ANA CMP2IB input Timer 1LPWM output f Pia INTOTOLOPISIOT detainput gt Pi INTSTOINTOHCP AD S rroo nas S Port1 Block Diagram Option Output type CMOS or N channel OD selectable in 1 bit units AII 3 Port Block Diagrams ISL FE5F INTI ul Noise filter m D Timer capture signal L Int request to Timer 0 clock input vector 00013 I23CR FEBE CELER Int request to vector 0001B _ L INT2 gt _T Timer 0L capture signal INT1 L level Int request to vector 00003 Int request to vector 0000B INTO _ 7 gt L level External Interrupt Block Diagram AII 4 Important Note This document is designed to provide the reader with accurate information in easily understandable form regarding the device features and the correct device implementation procedures The sample configurations included in the various descriptions are intended for reference only and should not be directly incorporated in user product configurations ON Semiconductor shall bear no responsibility for obligations concerning patent infringements safety or other legal disputes arising from prototypes or actual products created using the information contained herein LC870N00 SERIES USER S MANUAL Rev 1 00 February 16 2012 ON Semiconductor Digital Solution
64. O FE12 0000 0000 R TOL TOL7 TOL6 TOLS TOL4 TOL3 TOL2 TOL1 TOLO 3 3 4 4 Timer counter 0 high byte 1 This is a read only 8 bit timer counter It counts the number of match signals from the prescaler overflows occurring in TOL Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE13 0000 0000 R TOH TOH7 TOH6 TOH5 TOH4 TOH3 TOH2 TOHI TOHO 3 3 4 5 Timer counter 0 match data register low byte TOLR 1 This register is used to store the match data for TOL It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register matches the value of the low order byte of timer counter 0 16 bits of data must match in the 16 bit mode 2 The match buffer register is updated as follows When it is inactive TOLRUN 0 the match buffer register matches TOLR When it is active TOLRUN 1 the match buffer register is loaded with the contents of TOLR when a match signal is generated Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE14 0000 0000 R W TOLR TOLR7 TOLR6 TOLRS TOLR4 TOLR3 TOLR2 TOLRI TOLRO 3 3 4 6 Timer counter 0 match data register high byte TOHR 1 This register is used to store the match data for TOH It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register matches the value of the high order byte of timer counter 0 16 bits of data must match in the 16 bit
65. RSL3 GP2vRst2 99240611 p FEM FEAS FEA6 FEA7 FEA8 FEA9 FEAA FEAB LC870NO0 APPENDIX I Address Initial Value R W LC870N00 Remarks BIT8 BIT7 BIT6 BITS BIT4 BIT3 BIT2 BITI BITO FEBC AI 8 LC870NO0 APPENDIX II Function outputs 3 0 PO FE40 bits 3 0 03 00 PODDR FE41 bits 3 0 W PODDR Function Output MP20T1 output 20 1 output system clock output MP20TO output 20 0 output Port 0 Block Diagram Option Output type CMOS or N channel OD selectable in 1 bit units AII 1 Port Block Diagrams Function outputs 7 6 P1FCR FE46 W P1FCR Low PU P1 44 bits 7 6 P17 P16 Special input P17 P16 P1DDR FE45 bits 7 6 Function 2 outputs 5 3 Function outputs 5 3 P1FCR FE46 bits 5 3 gt abet W P1FCR C ad Low PU R P1FCR P1 FE44 bits 5 3 cmos E W P1 C Q Nch OD OR P15 P13 lt lt Special input P15 P13 R P1 P1DDR FE45 bits 5 3 D Q W P1DDR C R P1DDR AII 2 LC870NO0 APPENDIX II Function output 4 P1FCR FE46 bit 4 D E Low PU R P1FCR 1 FE44 bit 4 one Pin Nch 14 lt lt Special input P14 L P1DDR FE45 bit 4 D Q W P1DDR C R P1DDR Low PU P1 FE44 P12 P10 Special input P12 P10 P1DDR FE45 W P1DDR Special input AD input ANS CMP2IAC TmeriHPW
66. SB LSB first select Baudrate generator Serial transfer end flag SBR1 FE36h Overrun flag Y Vv SIO1 output control ae P15 port latch P13 lt lt P15 P15 output control bit7 bite bit5 bit4 bit3 bit2 bit SCON1 FE34h ea Interrupt request Figure 3 6 1 5101 Mode 0 Synchronous 8 bit Serial I O Block Diagram SI1M1 0 511 0 0 3 40 LC870NO0 Chapter 3 Start bit additional circuit Shift input Start stop bit additional circuit At time operation starts LSB MSB first select Shift input 8 bit shift register SIOSF1 Shift clock transfer ends Stop bit data input SIO1 output control gt gt m P13 P13 port latch P13 output control SBUF1 FE35h Stop bit input clock Clock generator circuit Baudrate Set SEND when generator stop bit data ends SBR1 FE36h SIO1 output trol D potes P14 output control Overrun flag Em SCON1 FE34h Interrupt request Figure 3 6 2 SIO1 Mode 1 Asynchronous Serial UART Block Diagram SI1M1 0 SI1M0 1 3 41 SIO1 3 6 4 SIO1 Communication Examples 3 6 4 1 Synchronous serial communication mode 0 1 Setting the clock Setup SBR1 when using an internal clock 2 Setting the mode Set as follows SIIMO 0 SIIMI O SIIDIR SITE 1 3 Setting up the ports a
67. The AD mode register ADMRC and AD conversion result register low byte ADRLC are used to select the conversion time for appropriate AD conversion 5 Automatic reference voltage generation control The AD converter incorporates a reference voltage generator circuit that automatically generates the reference voltage when an AD conversion starts and stops generation when the conversion ends For this reason set reset control of reference voltage generation is not necessary Also there is no need to supply the reference voltage externally 6 Itis necessary to manipulate the following special function registers to control the AD converter ADCRC ADMRC ADRLC ADRHC Address Initial Value BIT4 AD CHSEL3 CHSEL2 CHSELI CHSELO FE58 0000 0000 3 48 1 870 00 Chapter 3 7 8 Circuit Configuration 3 7 3 1 AD conversion control circuit 1 This circuit runs in two modes 10 and 8 bit AD conversion modes 3 7 3 2 Comparator circuit 1 The comparator circuit consists of a comparator that compares the analog input signal with the reference voltage and a control circuit that controls the reference voltage generator circuit and the conversion results The conversion end flag ADENDF of the AD control register ADCRC is set when an analog input channel is selected and the AD conversion terminates in the conversion time designated by the conversion time control register The conversion results are placed in the AD
68. UN 1 the match buffer register is loaded with the contents of when the value of T1H reaches 0 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BITO FE1D 0000 0000 R W TIHR TIHR7 TIHR6 5 4 2 TIHRO 3 30 1 870 00 Chapter Match buffer register value Modes 0 2 I E Match signal Interrupt flag set T1PWML T1PWMH FFH Counter value Mode 1 iL LL n o o A o c c Ev ux I o 2 a amp 5 2 o oO gt 3 31 Match buffer register value Mode 3 T1H Match signal Interrupt flag set T1PWMH FFH Counter value I a I o o T o c c 9 o gt ea o gt 5 2 o A o T gt 3 32 LC870NO0 Chapter 3 5 Base Timer BT 3 5 1 Overview The base timer BT incorporated in this series of microcontrollers is a 14 bit binary up counter that provides the following two functions 1 14 bit binary up counter 2 Buzzeroutput function 3 5 2 Functions 1 14 bit binary up counter A 14 bit binary up counter can be constructed using an 8 bit binary up counter and a 6 bit binary up counter These counters can be cleared under program control 2 Buzzer output function The buzzer output can be controlled using the input signal select register ISL The buzzer output
69. VSS1 Power supply IO Porto 0 UO 4 bit I O port P00 to P03 O can be specified in 1 bit units Pull up resistors can be turned on and off in 1 61 units Pin functions P00 MP20TO MCPWM2 output P01 2 MCPWM2 output P02 2 MCPWM2 output system clock output P03 2 1 MCPWM2 output Porti 1 UO 8 bit I O port Yes P10 to P17 T O can be specified in 1 units mE Pull up resistors can be turned on and off in 1 bit units Pin functions P10 ANO AD convertor input port INT2 input HOLD release input timer 0 event input timer OL capture input P11 ANI AD convertor input port INT3 input input with noise filter timer 0 event input timer capture input CMP 1 7 input P12 AN2 AD convertor input port CMP1 input P13 5101 data output AN3 AD converter input port CMP1 output P14 5101 data input bus I O INTO input HOLD release input timer OL capture input P15 5101 clock I O INTI input HOLD release input timer capture input CMP2 output P16 Timer 1 PWML output AN4 AD convertor input port CMP2 input P17 Timer 1 PWMH output ANS AD converter input port CMP2 input buzzer output Interrupt acknowledge type me Rising amp Rising Falling Falling x x O O External reset input internal reset output OWP0 VO On chip debugger dedicated pin 1 7 1 6 On chip Debugger Pin Con
70. X gt H gt L When interrupts of the same level occur at the same time the interrupt with the lowest vector address is given priority 7 Itis necessary to manipulate the following special function registers to enable interrupts and to specify their priority IE IP Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE08 0000 HH00 R W IE IE7 XFLG HFLG LFLG XCNTI XCNTO 41 3 Circuit Configuration 4 1 3 1 Master interrupt enable control register IE 6 bit register 1 Thisregister enables and disables H and L level interrupts 2 The interrupt level flag of the register can be read 3 The register selects the level L or X of interrupts to vector addresses 00003H and 0000BH 4 1 3 2 Interrupt priority control register IP 8 bit register 1 This register selects the level H or L of interrupts to vector addresses 00013H to 0004BH 4 2 LC870NOO0 Chapter 4 4 1 4 Related Registers 4 1 4 1 Master interrupt enable control register IE 1 This register is 6 bit register for controlling the interrupts Bits 6 to 4 are read only Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE08 0000 00 R W IE IE7 XFLG HFLG LFLG XCNTO IE7 bit 7 H L level interrupt enable disable control A 1 in this bit enables H and L level interrupt requests to be accepted A 0 in this bit disables H and L level interrupt requests to be accepted
71. address 123H to the accumulator 3 byte instruction 11 STW 123H Transfers the contents of the BA register pair to RAM address 123H PUSH 123H Saves the contents of RAM address 123H in the stack SUB 123H Subtracts the contents of RAM address 123H from the accumulator DBZ 123 11 Decrements the contents of RAM address 123H by 1 and causes a branch if zero 2 8 LC870N00 Chapter 2 2 11 6 ROM Table Look up Addressing The LC870000 series microcontrollers can read 2 byte ROM data into the BA register pair at once using the LDCW instruction Three addressing modes Rn Rn C and off are available for this purpose In this case only Rn is configured as 17 bit registers 128K byte space For models with banked ROM it is possible to reference the ROM data in the ROM bank 128K bytes identified by the LDCBNK flag bit 3 in the PSW Consequently when looking into the ROM table on a series model with banked ROM execute the LDCW instruction after switching the bank using the SET1 CLR1 instruction so that the LDCBNK flag designates the ROM bank where the ROM table resides Examples TBL DB 34H DB 12H DW 5678H LDW TBL Loads the BA register pair with the TBL address CHGP3 TBL gt gt 17 amp 1 Loads LDCBNK in PSW with bit 17 of the TBL address Note 1 CHGP1 TBL gt gt 16 amp 1 Loads in PSW with bit 16 of TBL address STW RO Loads indirect register RO with the TBL address bits 16 to 0 LDCW lI Reads t
72. and to control the conversion time 2 Since the data in this register is not established during an AD conversion the conversion results must be read out only after the AD conversion is completed Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FESA 0000 0000 R W ADRLC DATAL3 DATAL2 DATALI DATALO ADRL3 ADRL2 ADTM2 3 51 ADC10 DATALS bit 7 DATAL2 bit 6 DATAL1 bit 5 Fixed bit This bit must always be set to 0 Low order 2 bits data of AD conversion results DATALO bit 4 Fixed bit This bit must always be set to 0 ADRLS bit 3 Fixed bit This bit must always be set to 0 ADRL2 bit 2 Fixed bit This bit must always be set to 0 ADRL 1 bit 1 Fixed bit This bit must always be set to 0 ADTN2 bit 0 AD conversion time control This bit and ADTMI bit 1 and ADTMO bit 0 of the AD mode register ADMRC are used to control the conversion time See the subsection on the AD mode register for the procedure to set up the conversion time Note The conversion result data contains some errors quantization error combination error Be sure to use only valid conversion results based on the specifications provided in the latest SANYO Semiconductors Data Sheet 3 7 4 4 AD conversion result register high byte ADRHC 1 This register is used to hold the high order 8 bits of the results of an AD conversion that is performed in the 10 bit AD convers
73. atch signal 3 4 3 10 Timer 1 high byte output TTPWMH 1 The TIPWMH output is fixed at a high level when is inactive If T1H is active the TIPWMH output is fixed at a low level when TIHR FFH 2 When TIPWM is set to 0 or TILONG is set to 1 the timer 1 high byte output is a toggle output whose state changes on a T1H match signal 3 When TIPWM is set to 1 and TILONG is set to O timer 1 high byte output is a PWM output that is cleared on a T1H overflow and set on a T1H match signal 3 25 Clock 2Tcyc gt T1H prescaler T1H T1PWML output Clock 2Tcyc TIL prescaler TIL Clear Clear Match buffer register Match buffer register Reload Bead 3 TiLR T1LCMP flag set flag set lt 8 bit programmable timer gt 8 bit programmable timer gt Figure 3 4 1 Mode 0 Block Diagram T1LONG 0 T1PWM 0 lock lock 1 29 T1L prescaler 1Tcyc T1H prescaler Overflow Reset T1PWML output Set Match buffer Match buffer register lt oe T1LCMP T1HCMP flag set lt 8 bit PWM lt 8 bit PWM gt Figure 3 4 2 Mode 1 Block Diagram T1LONG 0 T1PWM 1 register Overflow Invert T1PWMH output Reset T1PWMH output Set 2Tcyc gt Clock 1 gt Clock T1L prescaler T1H prescaler Match buffer register
74. ate the following special function registers to control timer counter 0 TO TOCNT TOPRR TOL TOH TOLR TOHR TOCAL TOCAH PIDDR ISL IO1 CR D3CR Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE10 0000 0000 R W TOCNT TOHRUN TOLRUN TOLONG TOLEXT TOHCMP TOHIE TOLCMP TOLIE 00000000 rons rons XXXXXXXX TOCAL TOCAL7 TOCALG TOCALS TOCALA TOCAL3 TOCAL2 Tocar 3 3 3 Circuit Configuration 3 3 3 1 Timer counter 0 control register TOCNT 8 bit register 1 Thisregister controls the operation and interrupts of TOL and TOH 3 3 3 2 Programmable prescaler match register TOPRR 8 bit register 1 Thisregister stores the match data for the programmable prescaler To 3 3 3 3 1 2 3 4 3 3 3 4 2 3 4 3 3 3 5 2 3 4 3 3 3 6 2 3 3 3 7 2 Programmable prescaler 8 bit counter Start stop This register runs in modes other than HOLD mode Count clock Cycle clock period 1 Tcyc Match signal A match signal is generated when the count value matches the value of register TOPRR period 1 to 256 Tcyc Reset The counter starts counting from 0 when a match signal occurs or when data is written into TOPRR Timer counter 0 low byte TOL 8 bit counter Start stop Stop start is controlled by the 0
75. ation time of 100us or longer after the high speed RC oscillator circuit switches from the oscillation stopped to oscillation enabled state 4 8 LC870N00 Chapter 4 4 244 System clock divider control register CLKDIV 1 This register controls the frequency division processing of the system clock Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEOC HHHH H000 R W CLKDIV CLKDV2 CLKDV1 CLKDVO Bits 7 to 3 These bits do not exist They are always read as 1 CLKDV2 bit 2 CLKDV1 bit 1 These bits define the division ratio of the system clock CLKDVO bit 0 CLKDV2 CLKDV1 CLKDVO Division Ratio 2 I 1 8 16 32 i 64 4 9 Standby 4 3 Standby Function 4 3 4 Overview This series of microcontrollers supports two standby modes 1 HALT and HOLD modes that are used to reduce current consumption at power failure time or in program standby mode In standby mode the execution of all instructions is suspended 4 3 2 Functions 1 HALT mode The microcontroller suspends the execution of instructions but its peripheral circuits continue processing Some serial transfer functions are suspended HALT mode is entered by setting bit 0 of the PCON register Bit 0 of the PCON register is cleared and the microcontroller returns to the normal operating mode when a reset occurs or an interrupt request is accepted 2 HOL
76. ator 2 operation control CPAP2EN Comparator 2 Stop 0 CP2OUTEN bit 5 Comparator 2 output P15 control When this bit is set to 0 the comparator 2 output P15 is not output When this bit is set to 1 the comparator 2 output P15 is output The output however is kept low when comparator 2 is stopped CP2OUTEN P15FCR P15 P15 Pin Data in Output Mode P15DDR 1 Value of port data latch P15 SIO1 clock output data High output High output 0 0 o ER RES a i j CMP20OUT bit 3 Comparator 2 output data Reading this bit makes the comparator 2 output data available This bit is read only A 0 is read when comparator 2 is stopped CMP2EG bit 2 Comparator 2 interrupt source control Setting this bit to 0 selects the falling edge detection mode for the comparator 2 interrupt source Setting this bit to 1 selects the rising edge detection mode for the comparator 2 interrupt source The setting in this bit is invalid when comparator 2 is stopped CMP2IF bit 1 Comparator 2 interrupt source This bit is set when the comparator 2 output edge set by the comparator 2 interrupt source control is detected The bit is not set however if the comparator 2 is stopped This flag must be cleared with an instruction CMP2IE bit 0 Comparator 2 interrupt enable control An interrupt request to vector address
77. bit register that selects the level H L of interrupts to vector addresses 00013H to 0004BH Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE09 00000000 IP4B IP43 IP3B IP33 IP2B IP23 Interrupt Interr Level Vector Address terrupt Leve L 0004BH 00043H IP43 0003BH IP3B 00033H IP33 0002BH IP2B 00023H IP23 0001BH 00013H 4 4 LC870NOO Chapter 4 4 2 System Clock Generator Function 4 2 1 Overview This series of microcontrollers incorporates two systems of oscillator circuits 1 a medium speed RC oscillator and a high speed RC oscillator as system clock generator circuits The medium speed RC and high speed RC oscillator circuits have internal resistors and capacitors so that no external circuit is required The system clock can be selected from these two types of clock sources under program control 4 2 2 Functions 1 System clock select Allows the system clock to be selected under program control from two types of clocks generated by the medium speed RC oscillator and high speed RC oscillator 2 System clock frequency division Divides the frequency of the oscillator clock selected as the system clock and supplies the resultant clock to the system as the system clock The frequency divider circuit has two stages The first stage allows the selection of division ratios of i and The second stage allows the
78. curs Note The WDTCNT is disabled for writes once the WDT starts operation WDTRUN set to 1 If the instruction MOV 55 WDTCNT is executed in this case the WDTCT is cleared and counting is restarted at a count value of 0 The WDTCT is not cleared when it is loaded with 55H with any other instruction Note The low speed RC oscillator circuit is started by setting WDTRUN bit to 1 Once the oscillator starts oscillation an operating current of several uA flows at all times For details refer to the latest SANYO Semiconductors Data Sheet 4 19 WDT 4 5 5 Using the Watchdog Timer Code a program so that instructions for clearing the watchdog timer periodically are executed 1 2 3 Starting the watchdog timer lt 1 gt Set the time for a reset to occur to WDTSL2 to WDTSLO WDTCNT bits 2 to 0 lt 2 gt Set the standby mode operation HALT HOLD to IDLOP1 and IDLOPO WDTCNT bits 4 and 3 3 After 17 and lt 2 gt load WDTRUN WDTCNT bit 5 with 1 The watchdog timer starts functioning when WDTRUN is set to 1 Once the watchdog timer starts operation WDTCNT is disabled for writes it is only possible to clear WDTCT and read WDTCNT Consequently the watchdog timer can never be stopped with an instruction The function of the watchdog timer is stopped only when a low level is applied to the external reset pin a reset by the internal reset POR LVD function occurs or standby mode is entered when I
79. cycle All bits are cleared when an external input INT0 INT 1 l comparator 2 selected by the MCPWM2 interrupt control register is detected PWM output generator circuit 2 channels The MP2OTi MP2OTi signals are generated by the PVM NPWM signals and by the values of the dead time setting buffer register and the MCPWM2 output mode select buffer register i 0 1 3 58 LC870NO0 Chapter Dead time setting register Load Buffer register To PWM output block PWM period setting register Load Match buffer register System clock Operation clock 10 bit counter E generator circuit INTO interrupt source INT1 interrupt source Forced output stop signal To PWM Comparator 1 interrupt source Comparator 2 interrupt source generator circult output block To period interrupt and AD converter To PWM output block Select 2 interrupt control register Figure 3 8 1 MCPWM Block Diagram 1 PWM match count setting register Load Match buffer register PWM signal PWM output MP20Ti generator circuit generator circuit MP2OTi i 0 1 10 bit counter value Dead time setting buffer register value MCPWM output mode select register Load Buffer register Clear all bits Clear all bits n Forced output stop signal Figure 3 8 2 MCPWM 2 Block Diagram 2 3 59 MCPWM2 3 8 4 Related Registers 3 8 4 1 MCPWM2 c
80. d an interrupt request to vector address 000BH are generated This bit must be cleared with an instruction as it is not cleared automatically INT1IE bit 4 INT1 interrupt request enable When this bit and INTIIF are set to 1 a HOLD mode release signal and an interrupt request to vector address 000BH are generated INTOLH bit 3 INTO detection polarity select INTOLV bit 2 INTO detection level edge select INTOLH INTOLV INTO Interrupt Conditions P14 Pin Data 0 Falling edge detected Low level detected 0 71 0 Rising edge detected INTOIF bit 1 INTO interrupt source flag This bit is set when the conditions specified by INTOLH and INTOLV are satisfied When this bit and the INTO interrupt request enable bit INTOIE are set to 1 a HOLD mode release signal and an interrupt request to vector address 0003H are generated This bit must be cleared with an instruction as it is not cleared automatically INTOIE bit 0 INTO interrupt request enable When this bit and INTOIF are set to 1 a HOLD mode release signal and an interrupt request to vector address 0003H are generated 3 2 3 5 External interrupt 2 3 control register I23CR 1 This register is an 8 bit register that controls external interrupts 2 and 3 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FESE 0000 0000 R W D3CR INT3HEG INT3LEG INT3IF INT3IE INT2HEG INT2LEG INT2IF INT2IE
81. d highest level X The interrupt function will not accept any interrupt requests of the same level or lower level than that of the interrupt that is currently being processed Interrupt priority When interrupt requests to two or more vector addresses occur at the same time the interrupt request of the highest level takes precedence over the other interrupt requests Among the interrupt requests of the same level the one whose vector address is the lowest has priority Interrupt request enable control The master interrupt enable register can be used to control the enabling disabling of H and L level interrupt requests nterrupt requests of the X level cannot be disabled Interrupt disable period Interrupts are held disabled for a period of 2Tcyc after a write is made to the IE FEO8H or IP 9 register or HOLD mode is released No interrupt can occur during the interval between the execution of an instruction that loads the PCON FE07H register and the execution of the next instruction No interrupt can occur during the interval between the execution of a RETI instruction and the execution of the next instruction 4 1 Interrupt 6 Interrupt level control Interrupt levels can be selected on a vector address basis Table of Interrupts Vector Selectable Interrupt Sources Address Level 00003H XorL 00013H INT2 TOL 0001BH INT3 base timer nor OCS Priority level
82. dressing modes These addressing modes use 64 2 byte indirect registers RO to R63 allocated to RAM addresses 0 to 7EH The indirect registers can also be used as general purpose registers e g for saving 2 byte data Naturally these addresses can be used as ordinary RAM 1 byte 9 bits units if they are not used as indirect registers RO to R63 are system reserved words to the assembler and need not be defined by the user 2 5 RAM Reserved for system Address 7FH R63 upper 7EH R63 lower R63 7EH p 02H R1 lower R1 2 01H RO upper 00H RO lower 0 0 Figure 2 10 1 Allocation of Indirect Registers 2 11 Addressing Modes LC870000 series microcontrollers support the following seven addressing modes 1 Immediate Immediate data refers to data whose value has been established at program preparation assembly time 2 Indirect register Rn indirect 0 n S 63 3 Indirect register Rn C register indirect 0 lt n lt 63 4 Indirect register RO Offset value indirect 5 Direct 6 ROM table look up 7 External data memory access The rest of this section describes these addressing modes 2 11 1 Immediate Addressing The immediate addressing mode allows 8 bit 1 byte or 16 bit 1 word immediate data to be handled Examples are given below Examples LD 12H Loads the accumulator with byte data 12H Ll LDW 1234 Loads the BA register pair with word data
83. e clock port after the lapse of SBR1 value 1 3 x Tcyc When stop condition is detected is automatically cleared and an interrupt is generated Then clear SILEND to exit interrupt processing and return to 2 in step 4 Perform a receive operation 8 bits then set the clock output to 0 on the falling edge of the 8th clock after which an interrupt occurs The clock counter is cleared if a start condition is detected in the middle of receive processing in which case another 8 clocks are required to generate an interrupt Read SBUFI and store the read data Note Bit 8 of SBUF is not yet updated because the rising edge of 9th clock has not yet occurred Return to in step 6 when continuing receive processing Sending data Clear SIIREC Load SBUFI with output data Clear SIIEND and exit interrupt processing Send an acknowledge for the preceding receive operation and release the clock port after the lapse of SBR1 value 1 3 x Tcyc 1 e Perform a send operation 8 bits and set the clock output to 0 on the falling edge of the 8th clock after which an interrupt occurs 2 e Go to 3 in step 7 when SIIRUN is set to 1 When SII RUN is set to 0 implying an interrupt from 4 in step 7 clear SUEND and SIIOVR and return to 1 in step 4 3 e Read SBUFI and check send data as required Note Bit 8 of SBUF I is not yet updated because the rising edge of 9th clock has not yet occurred Load SBUFI with
84. e state that is established when HALT or HOLD mode is entered 3 3 Port 1 3 2 Port 1 3 2 1 Overview Port 1 is an 8 bit I O port equipped with programmable pull up resistors It is made up of a data latch a data direction register a function control register and a control circuit The I O direction is set by the data direction register in 1 bit units Port 1 can also be used as a serial interface I O timer 1 PWM output base timer buzzer output or an analog comparator output by manipulating the function control register Port 1 can also be used as an external interrupt pin and can release HOLD mode As a user option either CMOS output with a programmable pull up resistor or N channel open drain output with a programmable pull up resistor can be selected as the output type in 1 bit units 3 2 2 Functions 1 2 3 4 5 6 I O port 8 bits P10 to P17 The port output data is controlled by the port 1 data latch P1 FE44 and the I O direction is controlled by the port 1 data direction register PIDDR FE45 Each port bit is provided with a programmable pull up resistor Interrupt input pin function P14 and P15 are assigned to INTO and respectively and are used to detect low or high level or low or high edge and to set the interrupt flag P10 and P11 are assigned to INT2 and INT3 respectively and are used to detect low high both edges and to set the interrupt flag Tim
85. ed RC oscillator circuit resumes oscillation and the watchdog timer restarts counting If the period between release from standby mode and entry into the next standby mode is less than low speed RC oscillator clock x 4 however the low speed RC oscillator circuit may not stop oscillation even when the CPU enters standby mode In such a case the standby mode is on several of operating current flows because the low speed RC oscillator circuit is active though the watchdog timer count operation is suspended To minimize the standby power requirement of the set code the program so that an interval of low speed RC oscillator clock 4 or longer be provided between release from standby mode and entry into the next standby mode Note that the oscillation frequency of the low speed RC oscillator may fluctuate See the latest SANYO Semiconductors Data Sheet for details 4 20 4 6 4 6 1 LC870NO0 Chapter 4 Internal Reset Function Overview This series of microcontroller incorporates internal reset functions called the power on reset POR and low voltage detection reset LVD The use of these functions contributes to a reduction in the number of externally required reset circuit components reset IC etc 4 6 2 1 2 4 6 3 Functions Power on reset POR function POR is a hardware feature that generates a reset to the microcontroller at power on time This function allows the user to select the POR release level by
86. egister for TOL and a match signal is generated while TOL is running TOLRUN 1 Its state does not change if no match signal is generated Consequently this flag must be cleared with an instruction In the 16 bit mode TOLONG 1 a match must occur in all 16 bits of data for a match signal to occur TOLIE bit 0 TOL interrupt request enable control When this bit and TOLCMP are set to 1 an interrupt request to vector address 0013H is generated Notes TOHCMP and TOLCMP must be cleared to 0 with an instruction When the 16 bit mode is to be used TOLRUN and TOHRUN must be set to the same value at the same time to control operation TOLCMP and TOHCMP are set at the same time in the 16 bit mode LC870N00 Chapter 3 3 4 2 Timer 0 programmable prescaler match register TOPRR 1 Thisregister is an 8 bit register that is used to define the clock period Tpr of timer counter 0 2 The count value of the prescaler starts at 0 when TOPRR is loaded with data 3 1 x Tcyc Tcyc Period of cycle clock Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO 11 0000 0000 R W TOPRR TOPRR7 TOPRR6 TOPRR5 TOPRR4 TOPRR3 TOPRR2 TOPRRI TOPRRO 3 3 4 3 Timer counter 0 low byte TOL 1 This is a read only 8 bit timer counter It counts the number of match signals from the prescaler external signals Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT
87. en the respective operations are performed 2 1 Table 2 2 1 Values Loaded in the PC Operation PC Value BNK Value Inter Reset 00000H wr mm So INTI 0000BH INT2 TOL 00013H 0 HE INT3 timer OBH 0 0 0 0 0 TIR o 0 0 0 0 D 000433H instructions BZW BNZW BP BN BPC nb Number of instruction bytes Return instructions PC16 to 08 SP BNK is set 7 to 00 SP 1 to bit 8 of A TOH SP denotes the contents of SP 1 RAM address designated by the value of the stack pointer SP Standard instructions NOP MOV ADD PC PC nb Unchanged nb Number of instruction bytes 2 3 Program Memory ROM This series of microcontrollers has a program memory space of 256K bytes but the size of the ROM that is actually incorporated in the microcontroller varies with the type of the microcontroller The ROM table look up instruction LDC can be used to reference all ROM data within the bank Of the ROM space the 256 bytes in ROM bank 0 IFF00H to 1FFFFH for this series are reserved as the option area Consequently this area is not available as a program area 2 4 Internal Data Memory RAM This series of microcontrollers has an internal data memory space of 64K bytes but the size of the RAM that is actually incorporated in the microcontroller varies with the type of the microcontroller Nine bits are used to access addr
88. ence voltage value of comparator 2 as determined by the values of CP2VRSL3 to CP2VRSLO is a typical value Refer to the latest SANYO Semiconductors Data Sheet for variations in voltage values 3 75 7 3 76 LC870NOO0 Chapter 4 4 Control Functions 4 1 4 1 1 Interrupt Function Overview This series of microcontrollers has the capability to control three levels of multiple interrupts i e low level L high level H and highest level X The master interrupt enable and interrupt priority control registers are used to enable or disable interrupts and to determine the priority of interrupts 4 1 2 Functions 1 2 3 4 5 Interrupt processing Peripheral modules generate an interrupt request to the predetermined vector address when the interrupt request and interrupt request enable flags are set to 1 When the microcontroller receives an interrupt request from a peripheral module it determines the interrupt level priority and interrupt enable status If the interrupt request is legitimate for processing the microcontroller saves the value of PC in the stack and causes a branch to the predetermined vector address The return from the interrupt routine is accomplished by the RETI instruction which restores the old state of the PC and interrupt level Multilevel interrupt control The interrupt function supports three levels of interrupts that is the low level L high level H an
89. er When entering HOLD mode therefore it is recommended that the base timer be stopped 3 5 4 2 Input signal select register ISL 1 This register is a 9 bit register that controls the timer 0 input noise filter time constant the buzzer output and base timer clock Address Initial Value R W BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FESF 00000 0000 ISL BUZDIV STOHCP STOLCP BTIMCI BTIMCO BUZON NFSEL NFON STOIN BUZDIV bit 8 Buzzer output frequency division ratio select When this bit is set to 1 the signal obtained by dividing the base timer clock by 256 is sent as the buzzer output When this bit is set to 0 the signal obtained by dividing the base timer clock by 16 is sent as the buzzer output STOHCP bit 7 Timer OH capture signal input port select STOLCP bit 6 Timer OL capture signal input port select These 2 bits have nothing to do with the control function of the base timer 3 35 bit 5 Base timer clock select BTIMCO bit 4 Base timer clock select BTIMC1 BTIMCO Base Timer Input Clock 0 Inhibited Cycle clock 0 2 2 1 0 hibited BUZON bit 3 Buzzer output This bit enables the buzzer output fBST 16 or fBST 256 When this bit is set to 1 a signal that is obtained by dividing the base timer clock by 16 or 256 is sent to port P17 as the buzzer output When this bit is set to 0 the buzzer output is fixed at a hi
90. er with a 16 bit capture register 16 bit timer that supports PWM toggle output 8 bit timer with an 8 bit prescaler with toggle output x 2 channels 8 bit PWM with an 8 bit prescaler x 2 channels 16 bit timer with an 8 bit prescaler with toggle output toggle output also possible from the low order 8 bits 16 bit timer with an 8 bit prescaler with toggle output The low order 8 bits can be used as a PWM 1 1 Base timer 1 Theclock can be selected from the system clock or timer 0 prescaler output 2 Interrupt can be generated at eight specified time intervals e SIO SIOI 8 bit asynchronous synchronous serial interface Mode 0 Synchronous 8 bit serial I O 2 or 3 wire configuration 2 to 512Tcyc transfer clock Mode 1 Asynchronous serial I O half duplex 8 data bits 1 stop bit 8 to 2048Tcyc baudrate Mode 2 Bus mode 1 start bit 8 data bits 2 to 512Tcyc transfer clock Mode 3 Bus mode 2 start detection 8 data bits stop detection AD converter 10 bits x 6 channels e 10 8 bit AD converter resolution selectable Automatic start function in conjunction with the motor control PWM interrupt source Remote control receiver circuit multiplexed with the P11 INT3 e Noise rejection function noise filter time constant selectable from I Tcyc 32Tcyc 128Tcyc Clock output function id uode 1 e Capable of generating a clock with a frequency of 1 5 3 jg 32 Or Gq Of the source clock
91. er 0 count input function A count signal is sent to timer 0 each time a signal change that sets the interrupt flag is supplied to a port selected from P10 and P11 Timer OL capture input function A timer OL capture signal is sent each time a signal change that sets the interrupt flag is supplied to a port selected from P10 and P14 When a selected level of signal is input to P14 that is specified for level triggered interrupts a timer OL capture signal is generated at 1 cycle intervals for the duration of the input signal Timer 0H capture input function A timer OH capture signal is sent each time a signal change that sets the interrupt flag is supplied to a port selected from P11 and P15 When a selected level of signal is input to P15 that is specified for level triggered interrupts a timer OH capture signal is generated at 1 cycle intervals for the duration of the input signal HOLD mode release function When the interrupt flag and interrupt enable flag are set by INTO INTI or INT2 a HOLD mode release signal is generated releasing HOLD mode The CPU then enters HALT mode main oscillation by CR oscillator And when the interrupt is accepted the CPU switches from HALT mode to normal operating mode 3 4 1 870 00 Chapter 3 When a level of signal that sets an interrupt flag is input to P14 or P15 that is specified for level triggered interrupts in HOLD mode the interrupt flag is set In this case if the corresponding in
92. er since the timer 1 high byte T1H counts up at the interval of the timer 1 low byte T1L Independent match signals are generated from TIH and TIL when their count value matches the contents of the corresponding match buffer register regardless of the value of this bit T1PWM bit 4 T1 output mode select This bit and TILONG bit 5 determine the output mode of TI TIPWMH and TIPWML as summarized in Table 3 4 1 Table 3 4 1 Timer 1 a T1PWMH T1PWML Mode T1LONG TTPWM o PWMH PWML Toggle Period T1HR 1 x TIHPRC count Toggle Period TILR 1 x TILPRC count TL x 4 x Tcyc n x 4x Tcyc WEE sie Period 256 x TIHPRC count x Tcyc ie Period 256 x TILPRC count x Tcyc 2 1 Toggle Period T1HR 1 x TIHPRC count Toggle Period T1LR 1 x TILPRC count output x TIPWML period output x 4 x Tcyc Toggle Period T1HR 1 x TIHPRC count PWM A output x TIPWML period x 2 output Period 256 x TILPRC count x T1HCMP bit 3 T1H match flag This flag is set if TIH reaches 0 when T1H is active TIHRUN 1 This flag must be cleared with an instruction 3 28 LC870NO0 Chapter T1HIE bit 2 T1H interrupt request enable control An interrupt request is generated to vector address 002BH when this bit and TIHCMP are set to 1 T1LCMP bit 1 T1L match flag This flag is set if TIL reaches 0 when TIL is active TILRUN 1 This flag must be cleared with an instruction T1LIE
93. ernal pull up resistor Option selector circuit The option selector circuit is used to configure the LVD options This circuit selects whether to Enable use or Disable non use the LVD and selects its detection levels See subsection 4 6 4 External capacitor Cres Pull up resistor Regs After the reset signal from the internal reset circuit is released the reset period is further stretched according to the external CR time constant This enables the microcontroller to avoid repetitive entries and releases of the reset state from occurring when power on chatter occurs The circuit configuration shown in Figure 4 6 1 in which the capacitor Cars and pull up resistor are externally connected is recommended when both POR and LVD functions are to be used The recommended constant values are Cres 0 022uF and 510k Q The external pull up resistor Rees must always be installed even when the set s specifications inhibit the installation of the external capacitor Cres 4 21 Internal Rres 510 Cres 0 022uUF Reset Interior of microcontroller Reset Power on reset POR Low voltage detection reset LVD Options Pulse stretcher Figure 4 6 1 Internal Reset Circuit Configuration 4 6 4 Options The POR and LVD options are available for the reset circuit 1 LVD Reset Function Options Enable Use Disable N
94. eset automatically when the AD conversion ends The amount of time specified by the conversion time control register is required to complete the conversion The conversion time is defined using three bits i e the ADTM2 bit 0 of the AD conversion result register low byte ADRLC and the ADTMI bit 1 and ADTMO bit 0 of the AD mode register ADMRC If ADMDO ADMRC register bit 3 is set to 1 automatic start mode this bit is set when an AD automatic start signal from the MCPWM circuit is detected automatic start Setting this bit to 0 stops the AD conversion No correct conversion results can be obtained if this bit is cleared when AD conversion is in progress Never clear this bit or place the microcontroller in HALT or HOLD mode when AD conversion is in progress ADENDF bit 1 AD conversion end flag This bit identifies the end of AD conversion It is set to 1 when AD conversion is terminated Then an interrupt request to vector address 0043H is generated if ADIE is set to 1 If ADENDF is set to 0 it indicates that no AD conversion is in progress This flag must be cleared with an instruction ADIE bit 0 AD conversion interrupt request enable control An interrupt request to vector address 0043H is generated when this bit and ADENDF are set to 1 Notes Setting ADCHSEL3 to ADCHSELO to 0110 to 1111 is prohibited Do not place the microcontroller in HALT or HOLD mode with ADSTART set to 1 Make sure that ADSTART
95. esses 0000H to FDFFH of the 128K ROM space and 8 or 9 bits are used to access addresses FE00H to FFFFH The 9th bit of RAM is implemented by bit 1 of the PSW and can be read and written The 128 bytes of RAM from 0000H to 007FH are paired to form 64 2 byte indirect address registers The bit length of these indirect registers is normally 16 bits 8 bits x 2 When they are used by the ROM table look up instruction LDC however their bit length is set to 17 bits 9 high order bits 8 low order bits As shown in Figure 2 4 1 the available instructions vary depending on the RAM address The efficiency of the ROM used and a higher execution speed can be attempted using these instructions properly 2 2 LC870N00 Chapter 2 FFFFH FFOOH aaah SFR space FEOOH FDFFH uu Stack space 0200H 01FFH 0100H 0000H Reserved for system Note Some registers are 9 bit lt gt 9 bit A 1 Bit instruction direct long Bit instruction direct short Non bit instruction direct long indirect 16 bit operation instruction direct indirect gt gt 1 1 1 1 1 1 Non bit instruction direct short Figure 2 4 1 RAM Addressing Map When the value of the PC is stored in RAM during the execution of a subroutine call instruction or interrupt assuming that SP represents the current value of the stack pointer the value of BNK and the low order 8 bits of the 17 bit PC are stored in RAM addre
96. etting this bit to 1 enables comparator triggered forced output stop operation M2ERSL bit 5 External interrupt triggered forced output stop event select Setting this bit to O selects the INTO interrupt source as the trigger for forced output stop processing Setting this bit to 1 selects the INTI interrupt source as the trigger for forced output stop processing M2EREN bit 4 External interrupt triggered forced output stop control Setting this bit to 0 disables external interrupt triggered forced output stop operation Setting this bit to 1 enables external interrupt triggered forced output stop operation M2HPDRQ bit 3 End of half cycle interrupt source This bit is set when a match is detected between the values of the PWM period setting register and the 10 bit counter in mode 1 This bit is not set in mode 0 This flag must be cleared with an instruction M2HPDEN bit 2 End of half cycle interrupt enable control An interrupt request to vector address 003BH is generated when this bit and M2HPDRQ are set to 1 M2PDRQ bit 1 End of cycle interrupt source This bit is set when a match is detected between the values of the PWM period setting register and the 10 bit counter in mode 0 In mode 1 this bit is set when two match occurrences between the values of the PWM period setting register and the 10 bit counter are detected This flag must be cleared with an instruction M2PDEN bit 0 End of cycle interrupt enable control An
97. f an addition or subtraction and cleared to 0 otherwise There are some instructions that do not affect this flag at all PSWB5 PSWBA bits 5 and 4 User bits These bits can be read and written through instructions They can be used by the user freely LDCBNK bit 3 Bank flag for the table look up instruction LDCW This bit designates the ROM bank to be specified when reading the program ROM with a table look up instruction 0 ROM ADR 0 to 1FFFF 1 ROM ADR 20000 to OV bit 2 Overflow flag OV is set to 1 when an overflow occurs as the result of an arithmetic operation and cleared to 0 otherwise An overflow occurs in the following cases 1 When MSB is used as the sign bit and when the result of negative number negative number or negative number positive number is a positive number 2 When MSB is used as the sign bit and when the result of positive number positive number or positive number negative number is a negative number LC870N00 Chapter 2 3 When the high order 8 bits of a 16 bits x 8 bits multiplication is nonzero 4 When the high order 16 bits of a 24 bits x 16 bits multiplication is nonzero 5 When the divisor of a division is 0 There are some instructions that do not affect this flag at all P1 bit 1 RAM bit 8 data flag is used to manipulate bit 8 of 9 bit internal data RAM 0000H to FDFFH Its behavior varies depending on the instruction executed See Table 2 4 1 f
98. ft register SIOSF1 8 bit shift register This register is a shift register used to transfer and receive SIO1 data This register cannot be directly accessed with an instruction It is accessed via SBUFI SIO1 data register SBUF1 9 bit register The low order 8 bits of SBUFI are transferred to SIOSFI at the beginning of data transfer At the end of data transfer the contents of SIOSFI are placed in the low order 8 bits of SBUFI In modes 1 2 and 3 since the 9th input data is placed in bit 8 of SBUF1 it is possible to check for a stop bit etc SIO1 baudrate generator SBR1 8 bit reload counter This is a reload counter for generating internal clocks The generator can generate clocks of 2 to 512 Tcyc in modes 0 and 2 and clocks of 8 to 2048 Tcyc in mode 1 3 38 1 870 00 Chapter Table 3 6 1 5101 Operations and Operating Modes Bus Master Mode 2 Bus Slave Mode 3 Transfer Receive Transfer Receive Transfer Receive Transfer Receive 0 SHREC 1 SI1REC 0 SHREC 1 SI1REC 0 SHREC 1 0 SHREC 1 None None Output Input See 1 and 2 Not required Not required See 2 below Low Low below Data output 8 8 8 8 8 8 8 Shift data 1 s Shift data 1 s Shift data 1 Shift data 175 8 Data input 8 8 lt lt 8 lt Input pin Input pin Input pin Input pin S it None Output Input Input Output Input High H L H L SBUF1 bit8 H L L
99. g falling edge of the comparator 2 output if the comparator 2 interrupt enable bit is set The comparator 1 and comparator 2 interrupt sources are used to force the MCPWM2 output to stop 3 It is necessary to manipulate the following special function registers to control the analog comparator e CPAPCRI CPAPCR2 CPI VR CP2VR Initial Value RW Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEAO 0000 CPAPCRI CPAPIEN CPIOUTEN CMPIOUT CMPIEG CMPIIF CMPIIE Ere onon mw crwrcrz crarsex cmourew cwrzour curzec curar curar rex ww crve U epivees epivasra epivesu eeivesti epivesro reas ammo ono ww crave U kervievjerzvesus proves ojcrovesui erzvnsuo Bit 3 1 CMP20UT is read only 3 9 3 Circuit Configuration 3 9 3 1 Comparator 1 control register CPAPCR1 6 bit register 1 Thisregister controls the operation and interrupts of comparator 1 3 9 3 2 Comparator 2 control register CPAPCR2 6 bit register 1 Thisregister controls the operation and interrupts of comparator 2 3 9 3 3 Comparator 1 internal reference voltage control register CP1VR 6 bit register 1 Thisregister controls the internal reference voltage of comparator 1 3 9 3 4 Comparator 2 internal reference voltage control register CP2VR 5 bit register 1 Thisregister controls the internal reference voltage
100. gh level NFSEL bit 2 Noise filter time constant select NFON bit 1 Noise filter time constant select STOIN bit 0 Timer 0 count clock input port select These 3 bits have nothing to do with the control function of the base timer 3 36 3 6 3 6 1 1 870 00 Chapter Serial Interface 1 SIO1 Overview The serial interface 1 SIO1 incorporated in this series of microcontrollers is provided with the following four functions 1 2 3 4 3 6 2 2 3 4 5 6 Address Mode 0 Synchronous 8 bit serial I O 2 or 3 wire system 2 to 512 Tcyc transfer clock Mode 1 Asynchronous serial half duplex 8 data bits 1 stop bit 8 to 2048 Tcyc baudrate Mode 2 Bus master start bit 8 data bits 2 to 512 Tcyc transfer clock Mode 3 Bus slave start detection 8 data bits stop detection Functions Mode 0 Synchronous 8 bit serial I O Performs 2 or 3 wire synchronous serial communication The clock may be an internal or external clock The period of the internal clock is programmable within the range of 2 to 512 Tcyc Mode 1 Asynchronous serial UART Performs half duplex 8 data bits 1 stop bit asynchronous serial communication The baudrate is programmable within the range of 8 to 2048 Tcyc Mode 2 Bus master SIO1 is used as a bus master controller The start conditions are automatically generated but the stop conditions must be generated by manipulating ports Clock synchr
101. h a watchdog timer WDT that has the following functions 1 Capable of generating an internal reset on an overflow of a timer that runs on a WDT dedicated low speed RC oscillator clock 2 Operation when the microcontroller enters standby mode can be selected from three modes continue count operation suspend operation and suspend count operation while retaining the count value 4 5 2 Functions 1 Watchdog timer function The 17 bit up counter WDTCT runs on a low speed RC oscillator clock A WDT reset internal reset signal is generated when the overflow time selected from 8 time values that is selected by the watchdog timer control register WDTCNT is reached At this time the reset detection flag RSTFLG is set Since the WDTCT can be cleared by a program it is necessary to code the program so that the WDTCT can be cleared at regular intervals Since WDT used in this series of microcontrollers uses a dedicated low speed RC oscillator the system continues operation even when the system clock is stopped due to a program runaway making it possible to detect system runaway conditions The WDT operation mode on entry into standby mode can be selected from three modes i e continue count operation suspend operation and suspend count operation while retaining the count value If continue count operation is selected an operating current of several is always flowing in the IC because the low speed RC oscillator circ
102. he ROM table B 78H 12 MOV 1 Loads register with 01H LDCW RO C Reads the ROM table B 78H 12 INC C Increments the C register by 1 LDCW I RO0 Reads the ROM table B 56H ACC 78H Note 1 LDCBNK bit 3 of PSW needs to be set up only for models with banked ROM 2 11 7 External Data Memory Addressing LC870000 series microcontrollers can access external data memory space of up to 16M bytes 24 bits using the LDX and STX instructions To designate a 24 bit space specify the contents of the B register 8 bits as the highest order byte of the address and the contents 16 bits of Rn Rn C or RO off either one as the low order bytes of the address Examples LDW 934569 Sets up the low order 16 bits STW R5 Loads the indirect register R5 with the low order 16 bits of the address MOV 12H B Sets up the high order 8 bits of the address LDX 1 Transfers the contents of external data memory address 123456H to the accumulator 2 9 2 12 Wait Sequence 2 12 1 Wait Sequence Occurrence This series of microcontrollers does not have a wait sequence that automatically suspends execution of instructions 2 12 2 What is a Wait Sequence 1 When a wait request occurs out of a factor explained in Subsection 2 12 1 the CPU suspends the execution of the instruction for one cycle during which the required data is transferred This is called a wait sequence 2 The peripheral c
103. ignals from P15 INTI TOHCP and P11 INT3 TOHCP timer OH capture input pins Capture data Contents of timer counter 0 high byte TOH Table 3 3 1 Timer counter 0 TOL Count Clocks Mode TOLONG TOLEXT TOH Count Clock TOL Count Clock TOH TOL Count Clock 0 0 0 TOPRR match signal TOPRR match signal La o r Pre teh signal 3a o e Capture trigger Registers 101 FE5Dh I23CR FE5Eh and ISL FE5Fh need setting TOHCMP flag set TOLCMP flag set Match buffer register Reload TOLR 8 bit programmable timer gt programmable timer with with programmable programmable prescaler Figure 3 3 1 Mode 0 Block Diagram TOLONG 0 TOLEXT 0 o o Capture trigger gt Registers 101 FE5Dh I23CR FEBEh ISL FE5Fh need setting External Capture input gt TOL in register ISL FE5Fh Match buffer register TOLCMP flag set _ TOHCMP flag set programmable counter PON pregrammsbie Umer 2 with programmable prescaler Figure 3 3 2 Mode 1 Block Diagram TOLONG 0 TOLEXT 1 3 16 LC870N00 Chapter Clock Clear roe Match TOPRR Capture trigger TOCAH TOCAL Registers I01CR FE5Dh I23CR FE5Eh and ISL lear FE5Fh need setting Match TOLCMP Match buffer register TOHCMP flag set TOHR TOLR
104. ime determined by the formula is required in the second and subsequent conversions Detecting AD conversion end flag Monitor ADENDF bit 1 of the AD control register ADCRC until it is set to 1 Clear the conversion end flag ADENDF to 0 after confirming that the ADENDF flag bit 1 is set to 1 Reading the AD conversion results Read the AD conversion result register high byte ADRHC and AD conversion result register low byte ADRLC Since the conversion result data contains errors quantization error combination error be sure to use only valid conversion results based on the specifications provided in the latest SANYO Semiconductors Data Sheet Send the above read data to application software processing Return to step 4 to repeat conversion processing 3 53 ADC10 3 7 6 1 2 3 4 5 6 7 8 9 Hints on the Use of the ADC The conversion time that the user can select varies depending on the frequency of the cycle clock When preparing a program refer to the latest edition of SANYO Semiconductors Data Sheet to select an appropriate conversion time Setting ADSTART to 0 while conversion is in progress will stop the conversion operation Do not place the microcontroller in HALT or HOLD mode while AD conversion processing is in progress Make sure that ADSTART is set to 0 before putting the microcontroller into HALT or HOLD mode ADSTART is automatically reset and the AD conver
105. interrupt request to vector address 003BH is generated when this bit and M2PDRQ are set to 1 Note Both comparator triggered forced output stop processing and external interrupt triggered forced output stop processing can be used at the same time 3 61 MCPWM2 3 8 4 3 2 output mode setting register 0 MP2OMDO 1 This register is 6 bit register that sets the output mode of the MCPWM2 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE92 H000 H000 R W 2 0 IM20MD12 M2OMD11 M20MD10 M20MD02 M2OMDOI 2 00 M20MD12 to M2OMD10 bits 6 to 4 2 1 20 1 output mode settings M20MD12 to 2 1 20 1 M20MD10 Output Output 20 002 to 20 0 MP2OTO M2OMDO0O Output Notes The inversion of 2 i 0 is output when M2O0PL 1 The inversion of MP2OTi i 0 1 is output when M2OPLB 1 e Bits M20MDI2 to 2 10 M20MD02 to 2 are loaded into the respective buffer registers when the state of the MZ2PWMEN bit MCPWM 2 control register bit 7 is switched from 0 to I and at the end of every cycle All of bits M2OMDI2 to M20MDIO and 20 02 to M20MDODO are cleared when the MCPWM2 15 forced to an output stop by an external input INTO INT1 comparator I comparator 2 3 62 LC870N00 Chapter 3 8 4 4 PWM period setting register low byte MP2PDL 1 This register is an 8 bit register
106. ion mode The register stores the entire 8 bits of an AD conversion that is performed in 8 bit AD conversion mode 2 Since the data in this register is not established during an AD conversion the conversion results must be read out only after the AD conversion is completed Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FESB 0000 0000 R W ADRHC DATA6 DATAS DATA4 DATA3 DATA2 DATAI DATAO 3 52 3 7 5 3 7 5 1 2 3 4 5 6 LC870NO00 Chapter AD Conversion Example 10 bit AD conversion mode Setting up the 10 bit AD conversion mode Set the ADMD3 bit 6 of the AD mode register ADMRC to 0 Setting up the conversion time To set the conversion time to 1 32 frequency division set ADTM2 bit 0 of the AD conversion result register low byte ADRLC to 1 ADTMI bit 1 of the AD mode register ADMRC to 0 and ADTMO bit 0 of the AD mode register ADMRC to 1 Setting up the input channel When using AD channel input AN5 set ADCHSEL3 bit 7 of the AD control register ADCRC to 0 ADCHSEL2 bit 6 to 1 ADCHSEL1 bit 5 to 0 and ADCHSELO bit 4 to 1 Starting AD conversion Set ADSTART bit 2 of the AD control register ADCRC to 1 The conversion time is doubled when the AD conversion is performed for the first time after a system reset or after the AD conversion mode is switched from 8 bit to 10 bit AD conversion mode The conversion t
107. ions nnne nnn nnn nre nnn nn nnne nnno nona 3 70 3 9 3 Circuit Configuration mmm 3 70 3 9 4 Related Registers mH 3 72 Chapter 4 Control 4 1 4 1 Interrupt Function meme 4 1 41411 4 1 44 2 Functions rrr rennen nnn nnne nnn nnne nonne anon nnn 4 1 4 1 3 Circuit Configuration mmm 4 2 4 1 4 Related Registers mH 4 3 4 2 System Clock Generator 4 5 421 ILL TD 4 5 422 FunctiOns rrr nnne ru nennen nnn nnn nennen neenon rana 4 5 4 2 3 Circuit Configuration 4 6 4 2 4 Related Registers se 4 7 4 3 Standby Function eMe 4 10 43 1 4 10 4 32 FunctiOnS rrr rennen nnn 4 10 4 3 3 Related Register mmm e 4 10 44 Reset Function rrr ern enn nenne nennen nonna 4 14 441 Overview rn hr ener nennen urna nnne nne nnn nah eoru rona 4 14 44 2 FunctiOns rrr nnne ene nn nnne nnne nonno rona 4 14 44 3 Reset State nenne nennen nora 4 15 4 5 Watchdog Timer mme 4 16 45 1 rennen eeina 4 16 4 5 2 Functions rrr nenne nune nen nnn nnn nnn nonno nho rna ann 4 16 4 5 3 Circuit Configuration mmm 4 16 3 Contents 4 5 4 Related Registe
108. ircuits such as timers and PWM continue processing during the wait sequence 3 A wait sequence extends over no more than two cycles 4 microcontroller performs wait sequence when it is in HALT or HOLD mode 5 Note that one cycle of discrepancy is introduced between the progress of the program counter and time once a wait sequence occurs 2 10 LC870N00 Chapter 2 Table 2 4 1 Chart of State Transitions of Bit 8 RAM SFR and P1 Instruction Bit 8 RAM SFR P1 PSW Bit 1 Remarks LD LDW up F REGS pr LDW REGL8 lt P1 lt REGH8 PICREGE PUSHW REG8 lt RAM8 POP_P X XCHW IN IN D DECW DEC 17 bits PUSH BA RAMH8 lt P1 8 lt REGH8 lt P1 REGL8 PI PI REGHS INC 9 bits P1 lt REG8 after INC 9 bits computation INC 17 bits REGL8 lt low byte of CY P1 lt REGH8 after INC 17 bits computation DEC 9 bits P1 REGS after DEC 9 bits computation REGL8 lt low byte of CY inverted computation REGE PI P1 lt RAM8 P1 lt bitl when PSW is popped REGH8 lt RAMH8 REGL8 lt RAML8 lt P1 bitl when high order address of PSW is popped 1 lt bit 1 Bit 8 ignored P1 lt REGH8 after DEC 17 bits DBNZ DEC 9 bits P1 lt REG8 DEC 9 bits check low order 8 bits D SET1 NOTI CH C CW EC BZ C BP DEC 9 bits P1 lt REG8 DEC 9 bits check lo
109. is confined in an 8 bit address space the part of the address data addressing outside the 8 bit address space is ignored and the contents of OFEO1H B register are placed in the ACC as the result of the computation OFFO1H amp OFFH 0FEO0H 2 7 2 11 4 Indirect Register RO Offset Value Indirect Addressing off In this addressing mode the results of adding the 7 bit signed offset data off 64 to 63 to the contents of the indirect register RO designate an address in RAM or SFR If RO contains 2 and off has a value of 7EH 2 for example the A register FEO2H 2 FE00H is designated Examples When contains 123H RAM address 0 23H RAM address 1 01H LD 10H Transfers the contents of RAM address 133H to the accumulator 11 STW 10H Transfers the contents of the BA register pair to RAM address 133H PUSH 10H Saves the contents of RAM address 133H in the stack SUB 10H Subtracts the contents of RAM address 133H from the accumulator DBZ 10H L1 Decrements the contents of RAM address 133H by 1 and causes a branch if Zero Notes on this addressing mode gt The internal data memory space is divided into three closed functional areas as explained in Section 2 1 namely 1 system reserved area FFOOH to FFFFH 2 SFR area to FEFFH and 3 RAM stack area 0000H to FDFFH Consequently it is not possible to point to a different area using an offset value from the ba
110. is set to 0 before putting the microcontroller into HALT or HOLD mode 3 7 4 AD moder register ADMRC 1 Thisregister is an 8 bit register for controlling the operating mode of the AD converter Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE59 0000 0000 R W ADMRC ADMD4 ADMD3 ADMD2 ADMDI ADMDO ADMR2 ADTMI ADTMO ADMD4 bit 7 Fixed bit This bit must always be set to 0 bit 6 AD conversion mode control resolution select This bit selects the AD converter resolution between 10 bit AD conversion mode 0 and 8 bit AD conversion mode 1 When this bit is set to 1 the AD converter operates as an 8 bit AD converter The conversion results are placed only in the AD conversion result register high byte ADRHC the contents of the AD conversion result register low byte ADRLC remain unchanged When this bit is set to 0 the AD converter operates as a 10 bit AD converter The conversion results are placed in the AD conversion result register high byte ADRHC and the high order 2 bits of the AD conversion result register low byte ADRLC ADMD2 bit 5 Fixed bit This bit must always be set to 0 ADMD1 bit 4 Fixed bit This bit must always be set to 0 3 50 1 870 00 Chapter ADMDO bit 3 AD start mode select This bit sets the AD start mode to either soft start 0 or automatic start mode 1 When this bit is set to 1 AD conversion is started when an AD a
111. ished when HOLD mode is entered is in the high state or by a falling edge occurring when P10 data that is established when HOLD mode is entered is in the low state Consequently to release HOLD mode with P10 it is recommended that P10 be used in the both edge interrupt mode This bit must be cleared with an instruction as it is not cleared automatically INT2IE bit 0 INT2 interrupt request enable When this bit and INT2IF are set to 1 a HOLD mode release signal and an interrupt request to vector address 0013H are generated 3 2 3 6 Input signal select register ISL 1 This register is a 9 bit register that controls the timer 0 input noise filter time constant buzzer output and base timer clock select FESF 0000 0000 R W ISL _ BUZDIV STOHCP STOLCP BTIMCI BTIMCO BUZON NFSEL NFON STOIN BUZDIV bit 8 Buzzer output frequency division select This bit selects the frequency division ratio of the clock for the buzzer output When this bit is set to 1 the signal obtained by dividing the base timer clock by 256 is output When this bit is set to 0 the signal obtained by dividing the base timer clock by 16 is output STOHCP bit 7 Timer OH capture signal input port select This bit selects the timer OH capture signal input port When this bit is set to 1 a timer OH capture signal is generated when an input that satisfies the INTI interrupt detection conditions is supplied to P15 If the INTI interrupt detection mode
112. llers has the following three types of memory space 1 Program memory space 256K bytes 128K bytes x 2 banks 2 Internal data memory space 64K bytes 0000H to FDFFH out of 0000H to FFFFH is shared with the stack area 3 External data memory space 16M bytes External data memory space Address Address Program memory space FFFFFFH 3FFFFH Internal data memory space Add ROM bank 1 EFFEN Reserved for 16 system 1 1 FEFFH 1FFFFH SFR 8 61 some 9 bit 1 1 ROM bank 0 yee 128KB RAM Stack 64 i 9 bit config 00000H 0000H 000000H Note SFR is the area in which special function registers such as the accumulator are allocated see Appendix A I Figure 2 1 1 Types of Memory Space 2 2 Program Counter PC The program counter PC is made up of 17 bits and a bank flag BNK The value of BNK determines the bank The low order 17 bits of the PC allows linear access to the 128K ROM space in the current bank Normally the PC advances automatically in the current bank on each execution of an instruction Bank switching is accomplished by executing a Return instruction after pushing necessary addresses onto the stack When executing a branch or subroutine instruction when accepting an interrupt or when a reset is generated the value corresponding to each operation is loaded into the PC Table 2 2 1 lists the values that are loaded into the PC wh
113. mable timer with an 8 bit prescaler with toggle output x 2 channels Mode 1 8 bit PWM with an 8 bit prescaler x 2 channels Mode 2 16 bit programmable timer with an 8 bit prescaler with toggle output The low order 8 bits can be used as a timer with toggle output Mode 3 16 bit programmable timer with an 8 bit prescaler with toggle output The low order 8 bits can be used as a PWM Functions Mode 0 8 bit programmable timer with an 8 bit prescaler with toggle output x 2 channels Two independent 8 bit programmable timers and T1H run on a clock that is obtained by dividing the cycle clock by 2 TIPWML and TIPWMH generate a signal that toggles at the interval of TIL and T1H periods respectively Note 1 TIL period TILR 1 x TILPRC count x 2 Tcyc TIPWML period period x 2 T1H period TIHR 1 x TIHPRC count x 2 Tcyc TIPWMH period T1H period x 2 Mode 1 8 bit PWM with an 8 bit prescaler x 2 channels Two independent 8 bit PWMs TIPWML and TIPWMH run on the cycle clock TIPWML period 256 x TILPRC count x Tcyc TIPWML low period TILR 1 x TILPRC count x Tcyc TIPWMH period z 256 x TIHPRC count x Tcyc TIPWMH low period TIHR 1 x TIHPRC count x Tcyc Mode 2 16 bit programmable timer with an 8 bit prescaler with toggle output The low order 8 bits can be used as a timer with toggle output Functions as a 16 bit programmable timer that counts the number of signals obtained by di
114. match buffer register matches TOLR When it is active TOLRUN 1 the match buffer register is loaded with the contents of TOLR when a match signal is generated Timer counter 0 match data register high byte 8 bit register with a match buffer register This register is used to store the match data for TOH It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register matches the value of the high order byte of timer counter 0 16 bits of data must match in the 16 bit mode The match buffer register is updated as follows When it is inactive TOHRUN 0 the match buffer register matches TOHR When it is active TOHRUN 1 the match buffer register is loaded with the contents of TOHR when a match signal is generated 3 14 3 3 3 8 1 2 3 3 3 9 1 2 LC870N00 Chapter Timer counter 0 capture register low byte TOCAL 8 bit register Capture clock External input detection signals from P14 INTO TOLCP and P10 INT2 TOLCP timer OL capture input pins when TOLONG timer counter 0 control register bit 5 is set to 0 External input detection signals from P15 INTI TOHCP P11 INT3 TOHCP timer OH capture input pins when TOLONG timer counter 0 control register bit 5 is set to 1 Capture data Contents of timer counter 0 low byte TOL Timer counter 0 capture register high byte TOCAH 8 bit register Capture clock External input detection s
115. nd SIIREC bit 4 Clock Port P15 Internal clock Output Data Output Port Data I O Port P13 P14 SHREC Data transmission only Output 0 Data transmission reception 2 wire N channel open drain output 4 Setting up output data e Write output data into SBUFI in data transmission mode SII REC 0 5 Starting operation Set SIITRUN 6 Reading data after an interrupt e Read SBUF1 SBUFI has been loaded with serial data from the data I O port even in transmission mode e Clear SIIEND and exit interrupt processing Return to step 4 when repeating processing 3 6 4 2 Asynchronous serial communication mode 1 1 Setting the baudrate Setup SBRI 2 Setting the mode Set as follows SIIMO 1 SIIMI 0 SIIDIR SIIIE 1 3 Setting up the ports Data output Port P13 Data I O Port P14 Data transmission reception 2 wire Output Input Data transmission reception 1 wire EET AE N channel open drain output 4 Starting transmission Set SITREC to 0 and write output data into SBUFI Set SITRUN 3 42 LC870NO00 Chapter Note Use the SIO1 data port P14 when using the SIOI transmission only in mode 1 In mode 1 transmission is automatically started when a falling edge of receive data is detected While mode 1 is on the falling edge of data is always detected at the data I O port P14 Consequently if the transmit port is assigned to the data output port P13 it i
116. nection Requirements Install and connect a limiting resistor 1000 to the on chip debugger dedicated OWPO on the user board and pull the pin down 100K Q It is recommended to install a dedicated connector to accept the cable to the debugging tool TCB87 Type C The connector must accommodate three lines i e VSS1 OWPO and VDDI Connector for the debugging tool VDDI OWPO 100K Q VSSI 1 7 Recommended Unused Pin Connections Recommended Unused Pin Connections Software P00 to P03 Output low P10 to P17 Pin 1 8 Port Output Types The table below lists the types of port outputs and the presence absence of a pull up resistor Data can be read into any input port even if it is in output mode Option Port Selected Option Type Output Type Pull up Resistor Units of P00 to 1 bit Programmable 1 N channel open drain Programmable P10 to P17 1 bit CMOS Programmable N channel open drain Programmable 1 8 LC870NO0 Chapter 1 1 9 User Option Table Option to be Flash ROM Option Selected Applied on Version in Units of CMOS 1 bit N channel open drain Option Option Selection to Low voltage Detection function Port tt dices P10 to P17 1 bit i N channel open drain Enable Use detection reset Disable Non use 1 9 1 10 LC870N00 Chapter 2 2 Internal Configuration 2 1 Memory Space This series of microcontro
117. ng off 2 8 2 11 5 Direct Addressing dst mH 2 8 2 11 6 ROM Table Look up Addressing mH 2 9 2 11 7 External Data Memory Addressing etter eres 2 9 2 12 Wait Sequence ROREM SERRE RR 2 10 242 1 Wait Sequence Occurrence 2 10 2 12 2 What is a Wait 2 10 3 Peripheral System Configuration Aena S midi ias Gana ne da 3 1 3 1 Port 0 eer eter rere er rere eer er reer eee eee ee eee eee ee eee ee ee ee ee ee eee ee ee eee 3 1 3 1 1 Overview 3 1 Contents 3 1 2 Functions 3 1 3 1 3 Related Registers Murshesusrsysassssssesnensususensususensusasesensususesecsseseseeseses 3 1 3 1 4 Options Fasrsusruressusausesensususessususenensusesesseusssensenessuasusessususescssesesese 3 3 3 1 5 HALT and HOLD Mode Operation 3 3 3 2 Port 1 rrr rere err rere reer eee reer eee ee ee eee eee ee ee eee ee eee 3 4 3 2 1 Overview
118. nous synchronous SIO interface a 10 bit 6 channel AD converter with a 10 8 bit resolution selector two channels of analog comparator circuit a motor control 10 bit PWM a watchdog timer an internal reset circuit a system clock frequency divider and 14 source 9 vector interrupt function This series of microcomputers is optimal for small motor control devices 1 2 Features Flash ROM Capable of on board programming with a supply voltage range of 2 8 to 5 5V 128 byte block erase Can be written in 2 byte units 4608 x 8 bits 4096 512 bytes RAM 128 x 9 bits e Minimum bus cycle time 100 0ns at 1OMHz Note The bus cycle time here refers to the ROM read speed e Minimum instruction cycle time Tcyc 300ns at 1OMHz Ports Normal withstand voltage I O ports Ports whose input output can be specified in 1 bit units 12 POn Pin Reset pin 1 RES Power pins 2 VSSI VDD1 On chip debugger dedicated port 1 OWPO e Timers Timer 16 bit timer counter with a capture register Mode 0 Mode 1 Mode 2 Mode 3 e Timer 1 Mode 0 Mode 1 Mode 2 Mode 3 8 bit timer with an 8 bit programmable prescaler with an 8 bit capture register x 2 channels 8 bit timer with an 8 bit programmable prescaler with an 8 bit capture register 8 bit counter with an 8 bit capture register 16 bit timer with an 8 bit programmable prescaler with a 16 bit capture register 16 bit count
119. ntinues for 100 or longer as shown in b Waveform observed when both POR and LVD functions are used Reset pin Pull up resistor only LVD hysteresis width LVD release voltage LVHYS LVDET LVHYS LVD reset voltage LVDET yas dove doe vaya overs acp TE 1 ET 1 Reset period Ta I Reset period I U gt 1 Tail gt gt V ae Undefined state LVUKS 1 There also exists an undefined state LVUKS before the transistor starts functioning normally when both POR and LVD functions are used Resets are generated both when power is turned on and when the power level lowers The reset release voltage and entry voltage in this case may have some range Refer to the latest SANYO Semiconductors Data Sheet for details A hysteresis width LVHYS is provided to prevent repetitions of reset release and entry cycles near the detection level 4 24 LC870NO0 Chapter 4 4 6 6 Notes on the Use of the Internal Reset Circuit 1 When generating resets only with the internal POR function When generating resets using only the internal POR function do not short the reset pin directly to VDD as when using it with the LVD function Be sure to use an external capacitor of an appropriate capacitance for operation of the circuit and a pull up resistor Regs or the pull up resistor alone Test the circuit extensively under the anticipated power su
120. of comparator 2 3 70 1 870 00 Chapter 3 9 3 5 Comparator 2 channels 1 These analog comparator circuits receive external inputs as their input signals Comparator 1 P11 To comparator 1 interrupt CMP10OUT and P13 CMP1 internal reference voltage Comparator 1 control register Comparator 1 internal reference voltage control register Comparator 2 To comparator 2 interrupt CMP2OUT and P15 CMP2 internal reference voltage Comparator 2 control register Comparator 2 internal reference voltage control register Figure 3 9 1 Analog Comparator Block Diagram 3 71 Q U 3 9 4 Related Registers 3 9 4 1 Comparator 1 control register CPAPCR1 1 This register is 6 bit register that is used to control the operation and interrupts of comparator 1 Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO 0000 R W CPAPCRI CPAPIEN CPIOUTEN CMPIOUT CMPIEG CMPIIF Bit 3 CMPIOUT is read only CPAP1EN bit 7 Comparator 1 operation control CPAP1EN Comparator 1 Stop 0 CP10OUTEN bit 5 Comparator 1 output P13 control When this bit is set to 0 the comparator 1 output P13 is not output When this bit is set to 1 the comparator 1 output P13 is output The output however is kept low when comparator 1 is stopped CP1OUTEN P13FCR P13 P13 Pin Data in Output Mode P13DDR 1 Value of port data latch P1
121. ogramming Board 55 16 225 mil W87F0NS 1 4 1 870 00 Chapter 1 1 3 Pinout RES 11 C P03 MP20T14 VSS1 2 P02 MP20T1 CKO OWPO 3 14 1 2 P10 ANO INT2 TOLCP TOIN _ 5 12 P17 AN5 TIPWMH CMP2IA BUZ 11 1 1 6 11 P16 AN4 T1PWML CMP21B P12 AN2 CMP1IA 7 10 P15 SCK1 INT1 TOHCP CMP20 P13 S01 AN3 CMP10 8 9 P14 SI1 SB1 INTO TOLCP SANYO SSOP16 225 mil lead free and halogen free product A ojr2 P12 AN2 CMPIIA P13 SO1 AN3 CMP10 tA x 1 5 1 4 System Block Diagram Interrupt control gt IR PLA Standby control gt lt Flash ROM ay o 9 gt 5 E lt PC B o Reset circuit 9 register LVD POR y Credi lt register Bus interface ALU SIO1 lt D Port 0 meo omes INTO to INT2 RAM seme INT3 w noise filter Analog Stack pointer 2 C comparator On chip debugger 1 6 1 870 00 Chapter 1 1 5 Pin Functions Name Description Option
122. om two sources the cycle clock and timer 0 prescaler via the input signal select register ISL Set in ISL FE5Fh register 16TBST 256TBST 8 bit counter Buzzer output Selector Tcyc 1TBST Selector Timer 0 prescaler 256TBST 16384 64TBST 6 bit counter gt BTIFO flag set Selector BTIF1 flag set Selector 2048 8 5 Figure 3 5 1 Base Timer Block Diagram 3 5 4 Related Registers 3 5 41 Base timer control register BTCR 1 Thisregister is an 8 bit register that controls the operation of the base timer 0000 0000 BTC10 BTIEO BTFST bit 7 Base timer interrupt 0 period control This bit is used to select the interval at which base timer interrupt 0 is to occur When this bit is set to 1 the base timer interrupt O flag is set when an overflow occurs in the 6 bit counter The interval at which overflows occur is 64fBST When this bit is set to 0 the base timer interrupt 0 flag is set when an overflow occurs in the 14 bit counter The interval at which overflows occur is 16384fBST This bit must be set to 1 when high peed mode is to be used BTON bit 6 Base timer operation control When this bit is set to 0 the base timer stops when the count value reaches 0 When this bit is set to 1 the base timer continues operation 3 34 1 870 00 Chapter 3 BTC11 bit 5 Base timer interrupt 1 period control BTC10 bit 4
123. on use 2 LVD Reset Level Option 3 POR Release Level Option Typical value of Min operating Typical value of Min operating selected option VDD value selected option VDD value 1 67V 1 8V 1 91V 2 1V 1 97V 2 1V 2 01V 2 2 2 07V 2 2V 2 31V 2 5V 2 37V 2 5V 2 51V 2 7V 2 57V 2 7V 2 81V 3 0V 2 87V 3 0V 3 79V 4 0V 3 86V 4 0V 4 28V 4 5V 4 35V 4 5 The minimum operating VDD value specifies the approximate lower limit of the VDD value beyond which the selected POR release level or LVD reset level cannot be effected without generating a reset lt gt lt 2 gt lt 3 gt LVD reset function option When Enable is selected a reset is generated at the voltage that is selected by the LVD reset level option Note 1 In this configuration an operating current of several always flows in all modes When Disable is selected no LVD reset is generated Note 2 In this configuration no operating current will flow in all modes See the sample operating waveforms of the reset circuit shown in Subsection 4 6 5 for details LVD reset level option The LVD reset level can be selected from 7 level values only when Enable is selected in the LVD reset function options Select the appropriate detection level according to the users operating conditions POR release level option The POR release level can be selected from 8 level values only when
124. onization is used Since it is possible to verify the transfer time bus data at the end of transfer this mode can be combined with mode 3 to provide support for multi master configurations The period of the output clock is programmable within the range of 2 to 512 Tcyc Mode 3 Bus slave SIO1 is used as a slave device of the bus Start stop condition detection processing is performed but the detection of an address match condition and the output of acknowledge require program intervention SIOI can generate an interrupt by forcing the clock line to a low level on the falling edge of the 8th clock for recognition by a program Interrupt generation An interrupt request is generated at the end of communication if the interrupt request enable bit is set It is necessary to manipulate the following special function registers to control the serial interface 1 5101 SCONI SBUFI SBRI PIDDR Initial Value R W Name BIT8 BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO FE34 0000 0000 R W SCONI SIIMI SIIMO SIIRUN SII REC SIIDIR SIE Fese 0000 0000 ser SBRGI7 SBRGI6 SBRGIS SBRGI4 SBRGI3 SBRGI2 SBRGIO 3 37 SIO1 3 6 3 3 6 3 1 3 6 3 2 2 3 6 3 3 2 3 6 3 4 2 Circuit Configuration SIO1 control register SCON1 8 bit register This register controls the operation and interrupts of 5101 SIO1 shi
125. ontrol register MP2CR 1 This register is an 8 bit register that controls the operation of the MCPWM2 the output polarity the AD converter automatic start mode and the frequency division ratio of the operation clock Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO FE90 0000 0000 R W MP2CR M2PWMEN M2PWMMD 2 M2OPLB M2AAEN M2CKD2 M2CKDI M2CKDO M2PWMEN bit 7 MCPWM 2 operation control Setting this bit to 0 stops the MCPWM2 operation Setting this bit to 1 starts the MCPWM2 operation M2PWMNMD bit 6 MCPWM2 mode control Setting this bit to 0 causes the MCPWM2 to run in edge aligned PWM mode mode 0 Setting this bit to 1 causes the MCPWM2 to run in center aligned PWM mode mode 1 M2OPL bit 5 MP2OTi output polarity control i20 1 When this bit is set to 0 positive polarity MP2OTi signals are output When this bit is set to 1 negative polarity 2 signals are output M2OPLB bit 4 MP2OTi output polarity control i0 1 When this bit is set to 0 positive polarity MP2OTi signals are output When this bit is set to 1 negative polarity MP2OTi signals are output M2AAEN bit 3 AD converter automatic start mode control Setting this bit to 0 disables automatic start mode operation of the AD converter by the PWM period Setting this bit to 1 enables automatic start mode operation of the AD converter by the PWM period The AD automatic start signal is generated a
126. option only when Disable of the low voltage detection reset function is selected It is necessary to use the below mentioned low voltage detection reset function together with this function or configure an external reset circuit if there are possibilities that chatter occurs or a momentary power loss occurs at power on time Low voltage detection reset LVD function This function when used together with the POR function can generate a reset when power is turned on and when the power level lowers As a user option Enable use or Disable non use and the detection level of this function can be specified Circuit Configuration The internal reset circuit consists of the LVD pulse stretcher circuit capacitor discharging transistor external capacitor pull up resistor Regs or pull up resistor Rggs alone The circuit diagram is provided in Figure 4 6 1 Pulse stretcher circuit The pulse stretcher circuit stretches the POR and LVD reset signals It is used to stretch the internal reset period and discharge the external capacitor Cggs connected to the reset pin The stretching time lasts from 30us 100ps e Capacitor Cres discharging transistor This is an N channel transistor used to discharge the external capacitor connected to the reset pin If the capacitor Cres is not to be connected to the reset pin it is possible to monitor the internal reset signal by connecting only the ext
127. or details PARITY bit 0 Parity flag This bit shows the parity of the accumulator A register The parity flag is set to 1 when there is an odd number of 1 s in the A register It is cleared to 0 when there is an even number of 175 2 9 Stack Pointer SP LC870000 series microcontrollers can use RAM addresses 0000H to FDFFH as a stack area The size of RAM however varies depending on the microcontroller type The SP is 16 bits long and made up of two registers SPL at address FE0A and SPH at address FEOB It is initialized to OOOOH a reset The SP is incremented by 1 before data is saved in stack memory and decremented by 1 after the data is restored from stack memory Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEOA 0000 0000 R W SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SPO The value of the SP changes as follows 1 When the PUSH instruction is executed SP SP 1 RAM SP DATA 2 When the CALL instruction is executed SP SP 1 RAM SP ROMBANK ADL SP SP 1 RAM SP ADH 3 When the POP instruction is executed DATA RAM SP SP SP 1 4 When the RET instruction is executed ADH RAM SP SP SP 1 ROM BANK ADL RAM SP SP SP 1 2 10 Indirect Addressing Registers LC870000 series microcontrollers are provided with three addressing schemes Rn Rn C off which use the contents of indirect registers indirect addressing modes See Section 2 11 for the ad
128. oscillation and is designated as the system clock source 2 PDN is cleared when a HOLD mode release signal INTO INT 1 or INT2 or a reset signal occurs 3 BitO is automatically set when PDN is set IDLE bit 0 HALT mode setting flag 1 Setting this bit places the microcontroller into HALT mode 2 When bit 1 is set this bit is automatically set 3 This bitis cleared on acceptance of an interrupt request or on receipt of a reset signal Standby Table 4 3 1 Standby Mode Operations Item Mode Reset State HALT Mode HOLD Mode Entry conditions RES applied PCON register PCON register Reset from watchdog timer Bit 1 0 Bit 1 1 Bit 071 Data changed on entry Initialized as shown in If WDT register FE79h If WDT register FE79h separate table bits 4 3 0 1 WDTCNT bit 5 bits 4 3 0 1 WDTCNT bit 5 is cleared is cleared PCON bit 0 turns to 1 OCR register FEOE bit 4 is cleared Internal medium speed RC Running State established at entry time Stopped oscillation High speed RC oscillation Stopped State established at entry time Stopped Initialized Stopped Stopped I O pin state See Table 4 3 2 lt RES Undefined Data preserved Data preserved When watchdog timer reset Data preserved Stopped State established at entry time Stopped Peripheral modules except Stopped State established at entry time Stopped base timer Note 2 Exit conditions Entry conditions cancelled
129. other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner Contents Chapter 1 OverViGQW 2 02 322 0222 o es ner re S me eer er ee 1 1 1 1 Overview eee eee eee eee eee eee ee eee ree eee eee eee eee eee eee eee eee 1 1 1 2 Features Memuurussassssusenesnsusenensuasuseassususesessususessesessessenssessssessssusesssssee 1 1 1 3 Pinout eee eee eee eee eee eee eee eee eee eee eee ere eee eee ee eee ee eee ee eee eee eee 1 5 1 4 System Block Diagram eee eee eee eee eee eee ee ee eee ee eee eee eee ee 1 6 1 5 Pin Functions eee ee eee eee eee ee eee ee eee eee eee eee eee ee eee eee eee eee ee eee 1 7 1 6 On chip Debugger
130. pply conditions to verify that resets are reliably generated Microcontroller RRES Reset CRES From POR Figure 4 6 2 Reset Circuit Configuration Using Only the Internal POR Function 2 When selecting a release voltage level of 1 67V only with the internal POR function When selecting an internal POR release level of 1 67V connect the external capacitor Cres and pull up resistor of the values that match the power supply s rise time to the reset pin and make necessary adjustments so that the reset state is released after the release voltage exceeds the minimum guaranteed operating voltage Alternatively set and hold the voltage of the reset pin at a low level until the release voltage exceeds the minimum guaranteed operating voltage When POR release level is 1 67V Min guaranteed operating voltage Reset VIH level 1 1 1 1 Undefined state LVUKS Figure 4 6 3 Sample Release Level Waveform in Internal POR Only Configuration 4 25 Internal Reset 3 When voltage fluctuations or momentary power loss shorter than several hundred us is anticipated The response time measured from the time the internal LVD detects a power voltage drop at the option selected level until it generates a reset signal is defined as the minimum low voltage detection width TLvDW as shown in Figure 4 6 4 Refer to the latest SANYO Semiconductors Data Sheet for details If voltage fluctuation
131. pull up resistor Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE45 0000 0000 R W PIDDR PI7DDR PI6DDR PISDDR P14DDR P13DDR P12DDR P11DDR PIODDR Register Data Port Pin State Internal Pull up Input Resistor Enabled OFF 0 0 Enh EM Enabled Internal pull up resistor Enabled High open CMOS N channel open drain 3 6 1 870 00 Chapter 3 3 2 3 3 Port 1 function control register P1FCR 1 Thisregister is an 8 bit register that controls the multiplexed pin outputs of port 1 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE46 0000 0000 R W PIFCR PI6FCR PISFCR PI4FCR P13FCR PI2FCR PIOFCR 2 CP1OUTEN CPAPCR2 CPAPCR1 P1nFCR FEA1h bit 5 FEAOh bit 5 Pin Pin Data in Output Mode P1nDDR 1 Value of port data latch P17 Timer 1 PWMH or base timer buzzer data inverted data 1 1 1 1 1 The high data output at the pins that are selected as N channel open drain output by configuring options is represented by an open circuit nier Eee loce e d ee ple 2 p nc EE RE Wa u HE UNE sai ly EE E px o poe pe 4 dul e og lo d pou fut
132. r PODDR FE41 Each port bit POO to is provided with a programmable pull up resistor 2 Multiplexed pin function 2 is also used as the system clock output and to P03 are also used as the motor control PWM output The motor control PWM output is explained in 3 8 Motor Control PWM Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO FE40 HHHH 0000 R W P01 POO PO P02 Dro wv _exor exoov 3 1 3 Related Registers 3 1 3 1 Port 0 data latch PO 1 Thislatch is a 4 bit register for controlling port 0 output data 2 When this register is read with an instruction data at pins POO to is read in If PO FE40 is manipulated using the NOTI CLRI SET1 DBZ DBNZ INC or DEC instruction the contents of the register are referenced instead of the data at the pin 3 Port data can always be read regardless of the I O state of the port Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO 4 HHHH 0000 R W PO P03 P02 1 POO 3 1 3 2 Port 0 data direction register PODDR 1 This register is a 4 bit register that controls the I O direction of port 0 data in 1 61 units Port POn is placed in output mode when bit POnDDR is set to 1 and in input mode when bit POnDDR is set to 0 2 When bit POnDDR is set to 0 and bit POn of port 0 data latch is
133. r eee eee eee eee eee eee eee eee eee ee eee eee eee eee eee ee ee 4 18 4 5 5 Using the Watchdog Timer Gi 4 20 4 5 6 Notes on the Use of the Watchdog Timer ees 4 20 4 6 Internal Reset Function 4 21 4 6 1 Overview eee eee eee eee eee eee eee eee ee ee ee ee er re i 4 21 4 6 2 Functions eee eee eee ere ee ree eee eee ee ee eee eee eee eee eee eee eee eee eee reer eee 4 21 4 6 3 Circuit Configuration eee ee ree eee eee ee ee eee ee ee ree ee rr 4 21 4 6 4 Options eee eee eee eee eee ee eee eee eee eee eee eee ee ee ee eee ee ee re re ey 4 22 4 6 5 Sample Operating Waveforms of the Internal Reset Circuit 4 24 4 6 6 Notes on the Use of the Internal Reset Circuit 8 4 25 4 6 7 Notes to be Taken When Not Using the Internal Reset Circuit 4 27 Appendixes A I Special Function Register SFR HMM Al 1 7 1 Port Block Diagrams emm All 1 4 1 1 1 LC870NO0 Chapter 1 Overview Overview LC870NO0 series is an 8 bit microcontroller that centered around CPU running at a minimum bus cycle time of 100 0ns integrates on a single chip a number of hardware features such as 4 5K byte flash ROM onboard programmable 128 byte RAM an on chip debugger a 16 bit timer counter may be divided into 8 bit timers a 16 bit timer may be divided into 8 bit timers an asynchro
134. rence voltage value of comparator I as determined by the values of CP1VRSL3 to CPIVRSLO is a typical value Refer to the latest SANYO Semiconductors Data Sheet for variations voltage values 3 9 4 4 Comparator 2 internal reference voltage control register CP2VR 1 Thisregister is a 5 bit register that controls the internal reference voltage of comparator 2 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEA3 0000 R W CP2VR CP2VREN CP2VRSL3 CP2VRSL2 CP2VRSL 1 CP2VRSLO CP2VREN bit 4 Comparator 2 minus input select When this bit is set to O the minus input of comparator 2 is selected as the external input from P17 When this bit is set to 1 the minus input of comparator 2 is selected as the internal reference voltage of comparator 2 CP2VRSL3 to CP2VRSLO bits 3 to 0 Comparator 2 internal reference voltage setting 1 When CPVREF2 0 Comparator 2 internal reference voltage Set value 1 x VDD x 0 64 16 2 When CPVREF2 1 Comparator 2 internal reference voltage Set value 1 x VDD x 0 64 64 3 74 LC870NO00 Chapter Notes e The CPVREF2 setting comparator 1 internal reference voltage control register bit Z is common to comparators 1 and 2 The selection of the minus input CP2VREN and the internal reference voltage setting CPVREF2 CP2VRSL3 to CP2VRSLO must be performed while the comparator is stopped CPAPIEN 0 CPAP2EN 0 The internal refer
135. revent through current Reset IC Microcontroller CMOS type Reset From POR Figure 4 6 7 Sample Reset Circuit Configuration Using a CMOS Type Reset IC 4 27 Internal Reset 2 When configuring the external POR circuit without using the internal reset circuit The internal POR is activated when the power is turned on even if the internal reset circuit is not used as in case 1 in Subsection 4 6 7 When configuring an external POR circuit with a capacitor Cres value of 0 1uF or larger to obtain a longer reset period than with the internal POR however be sure to connect an external diode Dars as shown in Figure 4 6 8 Microcontroller Reset Connect an From POR external diode Figure 4 6 8 Sample External POR Circuit Configuration 4 28 Appendixes Table of Contents e Special Function Register SFR Appendix ll Port 0 Block Diagram Port 1 Block Diagram External Interrupt Block Diagram LC870NO0 APPENDIX I Address Initial Value R W LC870N00 Remarks BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 0 0 007 XXXX XXXX R W RAM128B 9 bit long oos onte m 1 CE EI ms D 0000 0000 ww SSCS Ps04 LK Ov Pr PARIY m wmuo wm m m ww i IE Xu Wu uu Xon 0000
136. s X gt H gt L When interrupts of the same level occur at the same time the interrupt with the lowest vector address is processed first Subroutine stack levels Up to 64 levels The stack is allocated in RAM e High speed multiplication division instructions 16 bits x 8 bits 5 Tcyc execution time 24 bits x 16 bits 12 Tcyc execution time 16 bits 8 bits 8 Tcyc execution time 24 bits 16 bits 12 Tcyc execution time Oscillator circuits Internal oscillator circuits 1 Medium speed RC oscillator circuit For system clock 1MHz 2 High speed RC oscillator circuit For system clock 10MHz 3 Low speed RC oscillator circuit For watchdog timer 30kHz System clock divider function Low consumption current operation possible The minimum instruction cycle can be selected from among 300ns 600ns 1 215 2 4us 4 8 5 9 6us 19 2us 38 4us and 76 8 5 at a main clock rate of 1OMHz Internal reset circuit Power on reset POR function 1 POR is generated only at power on time 2 The POR release level can be selected from 8 levels 1 67V 1 97V 2 07V 2 37V 2 57V 2 87V 3 86V and 4 35V by setting options Low voltage detection reset LVD function 1 LVD and POR functions are combined to generate resets when power is turned on and when the power voltage falls below a certain level 2 The use non use of the LVD function and the low voltage detection level 7 levels 1 9
137. s designated Examples When R3 contains 123H and the C register contains 02H LD R3 C Transfers the contents of RAM address 125H to the accumulator 11 STW R3 C Transfers the contents of the BA register pair to RAM address 125H PUSH R3 C Saves the contents of RAM address 125H in the stack SUB R3 C Subtracts the contents of RAM address 125H from the accumulator DBZ R3 L1 Decrements the contents of RAM address 125H by 1 and causes a branch if zero lt Notes on this addressing mode gt The internal data memory space is divided into three closed functional areas as explained in Section 2 1 namely 1 system reserved area FFOOH to FFFFH 2 SFR area to FEFFH and 3 RAM stack area 0000H to FDFFH Consequently it is not possible to point to a different area using the value of the C register from the basic area designated by the contents of Rn For example if the instruction LD R5 C is executed when R5 contains and the C register contains 1 since the basic area is 3 RAM stack area OOOOH to the intended address OFDFFH 1 OFEO0H lies outside the basic area and OFFH is consequently placed in the ACC as the result of LD If the instruction LD R5 C is executed when R5 contains OFEFFH and the C register contains 2 since the basic area is 2 SFR area FEOOH to FEFFH the intended address OFEFFH 2 OFFO1H lies outside the basic area In this case since SFR
138. s likely that data transmission is started unexpectedly according to the changes in the state of P14 5 Starting receive operation Set SIIREC to 1 Once SII REC is set to 1 do not attempt to write data to the SCONI register until the flag is set Detect the falling edge of receive data 6 Reading data after an interrupt Read SBUF1 SBUFI has been loaded with serial data from the data I O port even in transmission mode When SBUFI is read in the data about the position of the stop bit is read into bit 1 of the PSW Clear and exit interrupt processing Return to step 4 when repeating processing Note Make sure that the following conditions are met when performing continuous receive operation in mode 1 UART The number of stop bits is set to 2 or greater Clearing of SITEND during interrupt processing terminates before the next start bit arrives 3 6 4 3 Bus master mode mode 2 1 Setting the clock Setup SBRI 2 Setting the mode Set as follows SIIMO 0 SIIMI 1 SIIDIR 5 1 SUREC 0 3 Setting up the ports Set up the clock port P15 and data port P14 as N channel open drain output by specifying the option Set P14 P1 bit 4 and P15 P1 bit 5 to 0 Set PIAFCR PIFCR bit 4 and PISFCR PIFCR bit 5 to 1 Set PIADDR PIDDR bit 4 and PISDDR PIDDR bit 5 to 1 4 Starting communication sending an address Load SBUFI with address data Set S
139. s or momentary power loss shorter than this minimum low voltage detection width is anticipated be sure to take the preventive measures shown in Figure 4 6 5 or other necessary measures LVD release voltage LVD reset voltage LVDET Microcontroller Figure 4 6 5 Example of Momentary Power Loss or Voltage Fluctuation Countermeasures 4 26 LC870NO0 Chapter 4 4 6 7 Notes to be Taken When Not Using the Internal Reset Circuit 1 When configuring an external reset IC without using the internal reset circuit The internal POR function is activated and the capacitor Cres discharging N channel transistor connected to the reset pin turns on when power is turned on even if the internal reset circuit is not used For this reason when connecting an external reset IC adopt a reset IC of a type whose detection level is not lower than the minimum guaranteed operating voltage level and select the lowest POR release level 1 67V that does not affect the minimum guaranteed operating voltage The figures provided below show sample reset circuit configurations that use reset ICs of N channel open drain and CMOS types respectively Reset IC Microcontroller Several hundred N channel open drain type Reset From POR Figure 4 6 6 Sample Reset Circuit Configuration Using an N channel Open Drain Type Reset IC Insert a protective resistor of several to dozens of kQ to p
140. s placed at pin P14 When SIO1 is active SIO1 input data is read from P14 regardless of I O state of P14 P13FCR bit 3 P13 function control SIO1 data output control This bit controls the output data at pin P13 When P13 is placed in output mode P13DDR 1 and CPIOUTEN is set to 0 and is set to 1 the OR of the SIO1 output data and the port data latch is placed at pin P13 P12FCR bit 2 P12 function control This bit must always be set to 0 P11FCR bit 1 P11 function control This bit must always be set to 0 P10FCR bit 0 P10 function control This bit must always be set to 0 3 2 34 External interrupt 0 1 control register 101CR 1 Thisregister is an 8 bit register that controls external interrupts 0 and 1 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FESD 0000 0000 R W IOICR INTILH INTILV INTIIE INTOLH INTOLV INTOIF INTOIE INT1LH bit 7 INT1 detection polarity select INT1LV bit 6 INT1 detection level edge select INT1LH INT1LV INT1 Interrupt Conditions P15 Pin Data 0 Falling edge detected Low level detected 0 421 1 o Rsmegedeel 3 8 1 870 00 Chapter 3 INT1IF bit 5 INT1 interrupt source flag This bit is set when the conditions specified by INTILH and INTILV are satisfied When this bit and the INTI interrupt request enable bit INTIIE are set to 1 a HOLD mode release signal an
141. selected as the system clock Analog comparator 2 channels Analog comparator interrupt Reference level generator circuit built in Motor control 10 bit PWM Supports full bridge circuit control Capable of generating complementary PWM output Dead time can be set Forced output stop function using an external input or analog comparator output Edge aligned or center aligned mode can be selected e Watchdog timer Capable of generating an internal reset on an overflow of a timer running on the WDT dedicated low speed RC oscillator clock 30kHz WDT operation on entry into standby mode can be selected from three modes continue operation suspend operation and suspend operation while retaining the count value e Interrupts 14 sources 9 vector addresses 1 Provides three levels low L high H and highest X of multiplex interrupt control Any interrupt request of the level equal to or lower than the current interrupt is not accepted 2 When interrupt requests to two or more vector addresses occur at the same time the interrupt of the highest level takes precedence over the other interrupts For interrupts of the same level the interrupt with the lowest vector address has priority 1 2 LC870N00 Chapter 1 Vector Level Interrupt Source 00003H XorL INTO 00013H INT2 TOL 0001BH INT3 base timer 7 wem Het o wee Hor ac 1 Priority level
142. selection of division ratios of and 3 Oscillator circuit control Allows the start stop control of the two systems of oscillators to be executed independently through instructions 4 Oscillator circuit states and operating modes Mode Clock Medium speed High speed RC RC Oscillator Oscillator System Clock Reset Running Stopped Medium speed RC oscillator Stopped Medium speed RC oscillator Programmable Programmable Programmable HALT State established at State established at State established at entry time entry time entry time HOLD Stopped Stopped Stopped Immediately after Running Stopped Medium speed RC oscillator exit from HOLD mode See Section 4 3 Standby Function for the procedures to enter and exit the operating modes e Reset Medium speed RC oscillator started High speed RC oscillator stopped e HOLD mode All oscillators stopped Since the OCR register bits 1 and 4 are cleared the medium e Normal operating mode speed RC oscillator is started Start stop of oscillators and designated as the system programmable clock when HOLD mode is released Since the OCR3 register bit 6 is cleared the high speed RC oscillator is stopped when HOLD mode is released e HALT mode All oscillators retain the state established when HALT mode is entered 4 5 System Clock 5 1015 necessary to manipulate the following special function registers to control the system clock P
143. set indirect instruction the C register stores the offset data 128 to 127 to the contents of an indirect register The C register is allocated to address FEO2H of the internal data memory space and initialized to on a reset Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO FE02 0000 0000 R W CREG CREG7 CREG6 CREGS CREG4 CREG3 CREG2 CREGI CREGO 2 8 Program Status Word PSW The program status word PSW is made up of flags that indicate the status of computation results a flag to access the 9th bit of RAM and a flag to designate the bank during the LDCW instruction The PSW is allocated to address FEO6H of the internal data memory space and initialized to on a reset Address Initial Value R W Name BIT7 BIT6 BITS BIT4 2 BIT1 BITO FE06 0000 0000 R W PSW CY AC PSWBS5 PSWB4 LDCBNK OV CY bit 7 Carry flag CY is set to 1 when a carry occurs as the result of a computation and cleared to 0 when no carry occurs There are following 4 types of carries 1 Carry resulting from an addition 2 Borrow resulting from a subtraction 3 Borrow resulting from a comparison 4 Carry resulting from a rotation There are some instructions that do not affect this flag at all AC bit 6 Auxiliary carry flag AC is set to 1 when a carry or borrow occurs in bit 3 bit 3 of the high order byte during a 16 bit computation as the result o
144. set to 0 3 64 LC870NO0 Chapter 3 8 5 2 MP2OTi Output Port Settings i20 1 1 The relationship between the port settings and pin states for enabling the MP2OTO output from pin 00 is summarized below Register Data M2OTEO 0 Low Lo 10 1 1 1 High open CMOS N channel open drain 2 The relationship between the port settings and pin states for enabling MP2OTO output from pin P01 is summarized below Register Data P01 State P01 PO1DDR M2OTEOB 0 1 0 Low Lo i i MP20TO 1 X High open CMOS N channel open drain 3 relationship between the port settings and pin states for enabling the MP2OTI output from pin P02 1s summarized below POO State Register Data PO2DDR M2OTE1 1 0 Low c obo MPO 1 1 X High open CMOS N channel open drain 4 Therelationship between the port settings and pin states for enabling the MP2OT1 output from pin P03 is summarized below P02 State Register Data 20 1 1 0 Low State 1 i x High open CMOS N channel open drain 3 65 MCPWM2 3 8 6 Timing Charts 3 8 6 1 Mode 0 The polarity of MP2OTi MP2OTi outputs is positive M2OPL M2OPLB 0 i 0 1 1 1 1 1 M2PWMEN 1 1 L gt lt 20 6 0 1 M2DT6 0 M2MT9 0 i lt gt M2PD9 0
145. sic area designated by the contents of RO For example if the instruction LD 1 is executed when RO contains since the basic area is 3 RAM stack area 0000H to the intended address OFDFFH 1 lies outside the basic area and OFFH is placed in the ACC as the results of LD If the instruction LD 2 is executed when RO contains OFEFFH since the basic area is 2 SFR area FEOOH to FEFFH the intended address OFEFFH 2 OFFO1H lies outside the basic area In this case since SFR is confined in an 8 bit address space the part of the address data addressing outside the 8 bit address space is ignored and the contents of OFEO1H B register are placed in the ACC as the result of computation OFFO1H amp OFFH 0FEO0H 2 11 5 Direct Addressing dst Direct addressing mode allows a RAM or SFR address to be specified directly in an operand In this addressing mode the assembler automatically generates the optimum instruction code from the address specified in the operand the number of instruction bytes varies according to the address specified in the operand Long middle range instructions identified by an L M at the end of the mnemonic are available to make the byte count of instructions constant align instructions with the longest one Examples LD 123H Transfers the contents of RAM address 123H to the accumulator 2 byte instruction LDL 123H Transfers the contents of RAM
146. ss SP 1 and the high order 9 bits in SP 2 after which SP is set to SP 4 2 Accumulator A Register ACC A The accumulator ACC also called the A register is an 8 bit register that is used for data computation transfer and I O processing It is allocated to address FEOOH of the internal data memory space and initialized to 00H on a reset Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO 0 0000 0000 R W AREG AREG7 AREG6 AREG5 AREG4 AREG3 AREG2 AREGI AREGO 2 6 B Register B The B register is combined with the ACC to form a 16 bit arithmetic register during the execution of a 16 bit arithmetic instruction During a multiplication or division instruction the B register is used with the ACC and C register to store the results of computation In addition during an external memory access instruction LDX or STX the B register designates the high order 8 bits of the 24 bit address The B register is allocated to address FEO1H of the internal data memory space and initialized to 00H on a reset Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO FEO1 0000 0000 R W BREG BREG7 BREG6 BREGS BREG4 BREG3 BREG2 BREGI BREGO 2 3 2 7 Register The register is used with ACC and register to store results of computation during execution of a multiplication or division instruction In addition during a C register off
147. stion or of other channels Take the following measures to prevent a reduction in conversion accuracy due to noise interferences Be sure to add external bypass capacitors of several uF plus thousands of pF near the VDD1 and VSS1 pins as close as possible desirably 5 mm or less Add external low pass filters RC or capacitors most suitable for noise reduction very close to the analog input pins To avoid any adverse coupling influence use a ground that is free of noise interference as the ground for the capacitors rough standard values are less than 5 C 1000 pF to 0 luF Do not lay analog signal lines close to in parallel with or in a crossed arrangement with digital pulse signal lines or signal lines in which large current changes can occur Shield both ends of analog signal lines with noise free ground shields Make sure that no digital pulses are applied to or generated out of the pins adjacent to the analog input pin that is being subject to conversion 3 54 10 11 12 13 14 LC870NO00 Chapter Correct conversion results may not be obtained because of noise interference if the state of port outputs is changing To minimize the adverse influences of noise interference it is necessary to keep line resistance across the power supply and the VDD pins of the microcontroller at a minimum This should be kept in mind when designing an application circuit Adjust the amplitudes of the vol
148. t pins The contents of TOH are captured into the capture register TOCAH on external input detection signals from P15 INTI TOHCP and P11 INT3 TOHCP timer 0H capture input pins TOL period TOLR 1 TOH period TOHR 1 x TOPRR 1 x Tcyc 3 12 LC870N00 Chapter 3 Mode 2 16 bit programmable timer with a programmable prescaler with a 16 bit capture register Timer counter 0 serves as a 16 bit programmable timer that runs on the clock with a period of 1 to 256 Tcyc from an 8 bit programmable prescaler The contents of TOL and TOH are captured into the capture registers TOCAL and TOCAH at the same time on external input detection signals from P15 INTI TOHCP and P11 INT3 TOHCP timer OH capture input pins TO period TOHR TOLR 1 x TOPRR 1 x Tcyc 16 bits 4 3 16 bit programmable counter with a 16 bit capture register Timer counter 0 serves as a 16 bit programmable counter that counts the number of external input detection signals from pins P10 INT2 TOIN and P11 INT3 TOIN The contents of TOL and TOH are captured into the capture registers TOCAL and TOCAH at the same time on external input detection signals from P15 INTI TOHCP and P11 INT3 TOHCP timer OH capture input pins TO period TOHR TOLR 1 16 bits 5 Interrupt generation TOL or TOH interrupt request is generated at the counter interval for TOL or TOH if the interrupt request enable bit is set 6 Itis necessary to manipul
149. t the timing when the end of cycle interrupt source is set in mode 0 and at the timing when the end of half cycle interrupt source is set in mode 1 M2CKD2 to M2CKDO bits 2 to 0 PWM clock frequency division ratio select These bits select the clock of the 10 bit counter M2CKD2 to M2CKDO 10 bit Counter Clock 000 1 1 system clock 01 1 2 system clock 010 1 4 system clock Notes The settings of M2JPWMMD M2CKD2 to M2CKDO cannot be changed while the MCPWM2 is running M2PWMEN 1 The settings of M2CKD2 to M2CKDO are invalid when M2CKSL MCPWM2 control register 2 bit 7 is set to l 3 60 LC870N00 Chapter 3 8 4 2 interrupt control register MP2ICR 1 This register is 8 bit register that controls PWM interrupt and forced output stop processing Address Initial Value R W BIT7 BIT6 BITS BIT4 2 BIT1 BITO FE91 0000 0000 R W MP2ICR M2CRSL 2 M2ERSL M2EREN M2HPDRQ M2HPDEN M2PDRQ M2PDEN M2CRSL bit 7 Comparator triggered forced output stop event select Setting this bit to 0 selects the comparator 1 interrupt source as the trigger for forced output stop processing Setting this bit to 1 selects the comparator 2 interrupt source as the trigger for forced output stop processing M2CREN bit 6 Comparator triggered forced output stop control Setting this bit to 0 disables comparator triggered forced output stop operation S
150. tage at the oscillator pin and the I O voltages at the other pins so that they fall within the voltage range between VDD and VSS To obtain valid conversion data perform conversion operations several times discard the maximum and minimum values of the conversion results and use an average of the remaining data When the state of bit 3 of the ADMRC register AD automatic start mode AD soft start mode is changed during conversion processing the AD converter switches into the new mode after the conversion processing is finished The AD converter will not accept the next AD automatic start signal while it is in the AD automatic start mode To initiate the next automatic start sequence after the end of an AD conversion when the automatic AD start mode is on clear bit 1 of the ADCRC register AD conversion end flag The AD converter will not accept any next AD automatic start signal if bit 1 of the ADCRC register is set to 1 The AD converter can be subjected to soft AD start or forced stop control even when the automatic AD start mode is set 3 55 MCPWM2 3 8 Motor Control PWM MCPWM2 3 8 4 Overview The motor control PWM MCPWM2 incorporated in this series of microcontrollers is provided with a 10 bit counter and generates 2 channels of positive negative PWM outputs with a dead time 2 2 2 1 2 1 set by a register It can be forced to stop output by an external input INTO INT 1 comparator 1
151. te 1 All modes Reset Medium speed RC oscillator started High speed RC oscillator stopped All registers initialized Normal operating mode Start stop of oscillators programmable CPU and peripheral modules run normally HALT mode All oscillators retain the state established when HALT mode is entered CPU stopped Peripheral modules keep running HALT mode entry condition PCON register FEO7H bit 1 set to 0 and bit O to 1 Reset state cancellation condition Lapse of predetermined time after reset entry conditions are cancelled HALT mode release conditions Interrupt request accepted Note 2 Reset entry conditions established Note 1 Note 1 The CPU enters the reset state when the reset entry conditions are established Note 2 The CPU cannot return from HALT mode since no interrupt request can be accepted unless its interrupt level is higher than the interrupt level that placed the CPU into HALT or HOLD mode Interrupt level at which the CPU entered HALT or HOLD mode HALT mode Interrupt request level that can release No interrupt request present L level H level X level X H and L levels X and H levels None unable to release with interrupt Fig 4 3 1 4 13 Standby Mode State Transition Diagram Reset 4 4 Reset Function 4 4 1 Overview The reset function initializes the microcontroller when it is powered on or while it
152. ter stops operation if a reset is triggered while AD conversion processing is in progress When conversion is finished the AD conversion end flag ADENDF is set and at the same time the AD converter operation control bit ADSTART is reset The end of conversion condition can be identified by monitoring ADENDF An interrupt request to vector address 0043H is generated at the end of conversion by setting ADIE The conversion time is doubled in the following cases The AD conversion is performed in the 10 bit AD conversion mode for the first time after a system reset The AD conversion is performed for the first time after the AD conversion mode is switched from 8 bit to 10 bit AD conversion mode The conversion time determined by the formula given in the paragraph entitled Conversion time calculation formulas is required in the second and subsequent conversions or in AD conversions that are performed in the 8 bit AD conversion mode The conversion result data contains some errors quantization error combination error Be sure to use only valid conversion results based on the specifications provided in the latest SANYO Semiconductors Data Sheet Make sure that only input voltages that fall within the specified range are supplied to pins P10 ANO to P13 AN3 P16 AN4 and 7 5 Application of a voltage higher than VDD or lower than VSS to an input pin may exert an adverse influence on the conversion value of the channel in que
153. terrupt enable flag is set HOLD mode is released When a signal change that sets an interrupt flag is input to P10 in HOLD mode the interrupt flag is set In this case HOLD mode is released if the corresponding interrupt enable flag is set The interrupt flag however cannot be set by a rising edge occurring when the P10 data that is established when HOLD mode is entered is in the high state or by a falling edge occurring when P10 data that is established when HOLD mode is entered is in the low state Consequently to release HOLD mode with P10 it is recommended that P10 be used in the both edge interrupt mode 7 Multiplexed pin functions P17 is also used as the timer 1 PWMH base timer buzzer output P16 as the timer 1 PWML output P15 to P13 as SIO1 I O P10 to P13 P16 and P17 as the analog input channel ANO to ANS and P11 to P13 P15 to P17 as analog comparator I O Interrupt Input Timer 0 Count Capture HOLD Mode Signal Detection Input Input Release L level H level Timer OL Enabled Note P15 L edge H edge LL mew Enabled Note Note P14 and PIS HOLD mode release is available only when level detection is set Address Initial Value R W Name BIT8 BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO FE44 0000 0000 R W P11 P10 res ooon inor Pror riens rises Ptappa oppa vimos unes oops Feas 00000000 R W PIFCR PITFCR PIGFCR PI4FCR PI3FCR PI2FCR PIIFCR PIOFCR
154. th a 16 bit capture register 4 3 16 bit programmable counter with a 16 bit capture register 3 3 2 Functions 1 Mode 0 8 bit programmable timer with a programmable prescaler with an 8 bit capture register x 2 channels Two independent 8 bit programmable timers TOL and TOH run on the clock with a period of 1 to 256 Tcyc from an 8 bit programmable prescaler The contents of TOL are captured into the capture register TOCAL on external input detection signals from P14 INTO TOLCP and P10 INT2 TOLCP timer OL capture input pins The contents of TOH are captured into the capture register TOCAH on external input detection signals from P15 INTI TOHCP and P11 INT3 TOHCP timer 0H capture input pins TOL period TOLR 1 x TOPRR 1 x Tcyc TOH period TOHR 1 x TOPRR 1 x Tcyc Tcyc Period of cycle clock 2 1 8 bit programmable timer with a programmable prescaler with an 8 bit capture register 8 bit programmable counter with an 8 bit capture register TOL serves as an 8 bit programmable counter that counts the number of external input detection signals from pins P1O INT2 TOIN and P11 INT3 TOIN TOH serves as an 8 bit programmable timer that runs on the clock with a period of 1 to 256 Tcyc from an 8 bit programmable prescaler The contents of TOL are captured into the capture register TOCAL on external input detection signals from P14 INTO TOLCP and P10 INT2 TOLCP timer OL capture inpu
155. that is used to set the PWM period Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE94 0000 0000 R W MP2PDL M2PD7 M2PD6 M2PD5 M2PD4 M2PD3 M2PD2 M2PDI M2PDO 3 8 4 5 PWM period setting register high byte MP2PDH 1 This register is a 2 bit register that is used to set the PWM period Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE95 HHHH HH00 R W MP2PDH M2PD9 M2PD8 M2PD9 to M2PDO PWM period setting These bits define the PWM period PWM period Set value x 10 bit counter clock period Notes Bits M2PD9 to M2PD0 are loaded into the buffer register when the state of the M2JPWMEN bit MCPWM2 control register bit 7 is switched from 0 to 1 Setting these bits to O00h is inhibited The setting of M2PDO is invalid and bit 0 of the buffer register is fixed at 0 when M2CKSL MCPWM2 control register 2 bit 7 is set to 1 3 8 4 6 PWM match count setting register low byte MP2MTL 1 This register is an 8 bit register that is used to set the PWM match count value Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE96 0000 0000 R W MP2MTL M2MT7 M2MT6 2 5 M2MT4 M2MT3 M2MT2 N2MTI M2MTO 3 8 4 7 PWM match count setting register high byte MP2MTH 1 This register is a 2 bit register that is used to set the PWM match count value Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3
156. the latest SANYO Semiconductors Data Sheet 4 5 3 2 WDT counter WDTCT 17 bit counter 1 Start stop Start stop is controlled by the 1 0 value of WDTRUN When WDTRUN is set to 1 and IDLOPI and IDLOPO WDTCNT bits 4 and 3 are set to 2 the microcontroller enters standby mode 2 Count clock The low speed RC oscillator clock 3 Overflow Generated when the WDTCT count value matches the count value designated by WDTSL2 to WDTSLO WDTCNT bits 2 to 0 Generates the WDT reset and the WDTRUN clear signals and WDTRSTF WDTRUN bit 7 set signal 4 Reset When WDTRUN is set to 0 or WDTRUN is set to 1 and instruction MOV 55H WDTCNT is executed See Figure 4 5 2 for details on WDT operation WDTRUN Oscillation control WDT counter WDTRUN WDTCT Low speed RC Clock oscillator circuit Oscillation stopped WDTRST 1 WDTRUN clear signal WDT reset signal RSTFLG set signal 4 WDTSL2 0 IDLOP1 0 2 Standby mode WDTRST 0 IDLOP1 0 1 WDTRUN clear signal Standby mode entered Figure 4 5 1 Watchdog Timer Operation Block Diagram 4 17 WDT Operation performed when IDLOP1 0 are set to 0 or 3 continue count operation os WDTSL2 0 set count value WDTCT Count value 0 i H Time set in WDTSL2 0 WDT operation started MOV 55H WDTCNT WDT reset signal generated WDTRUN 1 instruction executed WDTRUN cleared to 0 Low speed RC WDTCT cleared to 0 RSTFLG set
157. the next output data Clear and exit interrupt processing Release the clock port after the lapse of SBR1 value 1 3 x Tcyc Return to 1 in step 7 when an acknowledge from the master is present L e When there is no acknowledge presented from the master H SIO1 recognizing end of data transmission automatically clears and releases the data port However in a case that restart condition comes just after the event SITREC must be set to 1 before exiting the interrupt 5 is for detecting a start condition and is not set automatically It may disturb the transmission of address from the master if there is an unexpected restart just after slave transmission when SIIREC is not set to 1 by instruction 4 e When a stop condition is detected an interrupt is generated and processing returns to 2 in step 7 3 45 8 Terminating communication Set 5 Return to in step 6 to cause communication to automatically terminate To forcibly terminate the communication clear SITRUN and SI1END release the clock port An interrupt occurs when a stop condition is detected Then clear SILEND and SILOVR and return to 2 in step 4 3 6 5 Related Registers 3 6 5 1 SIO1 control register 5 1 1 Thisregister is an 8 bit register that controls the operation and interrupts of SIOI Address Initial Value R W Name BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE34 000
158. tion such as the presence of a separate master mode device find out such condition by for example performing timeout processing using a timer module Return to step 6 when continuing data transmission Goto step 10 to terminate communication Receiving data Set 5 to 1 Clear SIIEND and exit interrupt processing receive 8 bits output SBUFI bit 8 acknowledge Reading received data after an interrupt Read SBUFI Return to step 8 when continuing data reception Go to in step 10 to terminate processing At this moment SBUFI bit 8 data has already been output as acknowledge data and the clock for the master side has been released Terminating communication e Manipulate the clock output port 5 0 P1ISDDR 1 P1520 and set the clock output to 0 Manipulate the data output port P14FCR 0 P14DDR 1 P14 0 and set the data output to 0 Restore the clock output port into the original state PISFCR 1 PISDDR 1 P15 0 and release the clock output Wait for all slaves to release the clock and for the clock to be set to 1 Allow for a data setup time then manipulate the data output port 4 0 P14DDR 1 P14 1 and set the data output to 1 In this case the SIO1 overrun flag SCONI FE34 bit 2 is set but this will exert no influence on the operation of SIOI Restore the data output port into the original state set PI4FCR to 1 then PIA4DDR to 1 and P14 to 0 Clear SI
159. to 1 oscillator started Low speed RC oscillator stopped Operation performed when IDLOP1 0 are set to 1 suspend operation Standby mode entered WDTSL2 0 set count value WDTCT Count value 0 A WDT operation started WDTRUN cleared to 0 WDTRUN 1 Low speed RC Low speed RC oscillator stopped oscillator started Operation performed when IDLOP1 0 are set to 2 suspend count operation while retaining the count value Standby mode entered Standby mode exited Overflow Low speed RC oscillator Low speed RC oscillator Stopped started WDTCT Count value 0 Time set in WDTSL2 0 Standby mode time WDT operation started WDT reset signal generated WDTRUN 1 WDTRUN cleared to 0 Low speed RC RSTFLG set to 1 oscillator started Low speed RC oscillator stopped Figure 4 5 2 Sample Watchdog Timer Operation Waveforms 4 5 4 Related Register 4 5 41 WDT control register WDTCNT 1 This register is used to manipulate the reset detection flag to select the standby mode operation to select the overflow time and to control the operation of the WDT Address Initial Value RW Name BIT7 BIT6 5 BIT4 BIT3 BIT2 BIT1 BITO FE79 0000 0000 R W WDTCNT RSTFLG FIXO WDTRUN IDLOPI IDLOPO WDTSL2 WDTSLI WDTSLO RSTFLG bit 7 WDT reset detection flag This bit is cleared when a reset is triggered by applying a low level to the external RES pin or by using the internal reset POR LVD function This bit is set when a
160. ua rus m ru R m mw mw nm mw ne rm ric 0000 0000 RA Tu Tn rt rus riw rip rw O l rw nee ree Address Initial Value RW LC870N00 Remarks BIT8 BIT7 BIT6 BITS BIT4 BIT3 BIT2 BITI BITO FETE FE34 0000 0000 Rw f sim siwo SIREC SIIDIR SITOVR SITEND SITE FE36 00000000 RW SBRGI7 SBRGIG SERGIS SBRGI4 SBRGI3 SBRGI2 SBRGI1 SERGIO LAE c s EE s 12441111 41112 22274 7 507052 ee j ER qoo qoo 111414 4 1 AI 2 LC870NO0 APPENDIX I Address Initial Value R W LC870N00 Remarks BIT8 BIT7 BIT6 BITS BIT4 BIT3 BIT2 BITI BITO ELE Po PR POIDDR PO0DDR oz eal A E S F ae s P P Pr Pro ib PHDDR PISDDR 200 PIIDDR sa a j TT OA eo s FE47 OOHH HHHO HE ON sssi ami E E ERES E EE
161. uffer 1 SBUF1 1 Serial buffer 1 is a 9 bit register used to store data to be handled during SIO1 serial transfer 2 The low order 8 bits of SBUFI are transferred to the data shift register for data transmission reception at the beginning of transfer processing and the contents of the shift register are placed in the low order 8 bits of SBUFI when 8 bit data is transferred 3 In modes 1 2 and 3 bit 8 of SBUFI is loaded with the 9th data bit that is received data about the position of the stop bit Address Initial Value R W Name BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE35 00000 0000 SBUFI 5 8 SBUFI7 SBUF16 SBUFI5 SBUFIA SBUFI3 SBUF12 SBUF11 SBUFIO 3 6 5 3 Baudrate generator register SBR1 1 Thisregister is an 8 bit register that defines the baudrate of the SIO1 Modes 0 1 2 2 Loading this register with data causes the baudrate generating counter to be initialized immediately 3 The baudrate varies from mode to mode Modes 0 2 TSBRI SBRI value 1 x 2 Tcyc Value range 2 to 512 Tcyc Mode 1 TSBRI SBRI value 1 x 8 Tcyc Value range 8 to 2048 Tcyc 4 When in mode 3 it sets up the acknowledge data set up time See 3 6 4 3 6 7 When setting to mode 3 time that clock port is released after SILEND is cleared is SBRI value 1 3 x Tcyc SBR1 0 is inhibited Set this value to meet the opponent device s data set up time Address Initial Value
162. uit continues oscillation even in standby mode For details refer to the latest SANYO Semiconductors Data Sheet 2 It is necessary to manipulate the following special function register to control the watchdog timer WDT WDTCNT Address Initial Value RAW Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO FE79 0000 0000 R W WDTCNT RSTFLG WDTRUN IDLOP IDLOPO WDTSL2 WDTSLI WDTSLO 4 5 3 Circuit Configuration 4 5 3 1 WDT control register WDTCNT 8 bit register 1 This register is used to manipulate the reset detection flag to select operation in standby mode to select the overflow time and to control the operation of the WDT Note The WDTCNT is initialized to 00H when a low level is applied to the external RES pin or a reset is triggered by the internal reset POR LVD function Bits 4 to 0 of the WDTCNT are not initialized however when a WDT triggered reset occurs Note The WDTCNT is disabled for writes once the WDT is started WDTRUN set to I If the instruction MOV 55H WDTCNT is executed in this case the WDTCT is cleared and counting is restarted at a count value of 0 The WDTCT is not cleared when it is loaded with 55H with any other instruction 4 16 1 870 00 Chapter 4 Note The low speed RC oscillator circuit starts oscillation by setting the WDTRUN bit WDTCNT bit 5 to 1 Once oscillation is started an operating current of several uA flows at all times For details refer to
163. utomatic start signal from the MCPWM circuit is detected When this bit is set to 0 AD conversion is started by setting bit 2 ADSTART of the AD control register ADCRC The automatic start mode is described in Section 3 8 Motor Control PWM ADMR2 bit 2 Fixed bit This bit must always be set to 0 ADTM1 bit 1 bit 0 These bits and ADTM2 bit 0 of the AD conversion result register low byte ADRLC define the conversion time ADREG ADMRC Register Register AD Frequency Division Ratio AD conversion time control 1 1 Conversion time calculation formulas 10 bit AD conversion mode Conversion time 40 AD division ratio 2 x 1 3 x Tcyc 8 bit AD conversion mode Conversion time 28 AD division ratio 2 x 1 3 x Tcyc Notes The conversion time is doubled in the following cases 1 The AD conversion is performed in the 10 bit AD conversion mode for the first time after a system reset 2 The AD conversion is performed for the first time after the AD conversion mode is switched from 8 bit to 10 bit AD conversion mode The conversion time determined by the above formula is required in the second and subsequent conversions or in AD conversions that are performed in the 8 bit AD conversion mode 3 7 4 3 AD conversion result register low byte ADRLC 1 This register is used to hold the low order 2 bits of the results of an AD conversion performed in the 10 bit AD conversion mode
164. viding the cycle clock by 2 Since interrupts can occur from the low order 8 bit timer T1L at the interval of period the low order 8 bits of this 16 bit programmable timer can be used as the reference timer TIPWML and TIPWMH generate a signal that toggles at the interval of TIL and 1 periods respectively Note 1 TIL period TILR 1 x TILPRC count x 2 Tcyc TIPWML period period x 2 period 1 x TIHPRC count x period TIPWMH period T1 period x 2 3 2 4 Mode 3 16 bit programmable timer with an 8 bit prescaler with toggle output The low order 8 bits can be used as a PWM A 16 bit programmable timer runs on the cycle clock The low order 8 bits run as PWM TIPWML having a period of 256 Tcyc TIPWMH generates a signal that toggles at the interval of T1 period Note 1 TIPWML period 256 x TILPRC count x Tcyc TIPWML low period TILR 1 x TILPRC count x Tcyc T1 period TIHR 1 x TIHPRC count x TIPWML period TIPWMH period period x 2 5 Interrupt generation A TIL or T1H interrupt request is generated at the counter period for TIL or T1H if the interrupt request enable bit is set 6 Itis necessary to manipulate the following special function registers to control timer 1 T1 TICNT TIL TILR TIHR TIPRR PIDDR Address Initial Value R W BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO FE18 0000 0
165. w order 8 bits MUL24 8 lt 1 DIV24 Bit 8 of RAM address for storing results is set to 1 Note A I is read if the processing target is an 8 bit register no bit 8 Legends REGS REGHS8 REGLS RAMS RAMHS8 RAMLS Bit 8 of a RAM or SFR location Bit 8 of the high order byte of a RAM or SFR location bit 8 of the low order byte Bit 6 of a RAM location Bit 8 of the high order byte of a RAM location bit 8 of the low order byte 2 12 1 870 00 Chapter 3 3 Peripheral System Configuration This chapter describes the internal functional blocks peripheral system of this series of microcontrollers except the CPU core RAM and ROM Port block diagrams are provided in Appendix A II for reference 3 1 Porto 3 1 1 Overview Port 0 is a 4 bit I O port equipped with programmable pull up resistors It is made up of a data latch a data direction register a function control register and a control circuit The I O direction and the pull up resistor are set by the data direction register in 1 bit units As a user option either CMOS output with a programmable pull up resistor or N channel open drain output with a programmable pull up resistor can be selected as the output type in 1 bit units 3 1 2 Functions 1 TO port 4 bits POO to P03 The port output data is controlled by the port 0 data latch PO FE40 and the I O direction is controlled by the port 0 data direction registe

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