STD 7000 7803 Z-80 Processor Card USER`S MANUAL
Contents
1. gt WEE cms e cud REFRESH pU TSLAV TSLSH STATUS 15 NANOSECONDS SYMBOL PARAMETER MIN TYP MAX TAVDV Address valid before data valid access time 580 MEMRQ R0 __ REFRESH STATUS 15 el CLOCK Low state TAVME Address valid before MEMRQ active Fetch 1600 TMLMH MEMRQ pulse width 2 Refresh 1400 TAVRL Address valid before R0 active 11651 TRLRH RD pulse width 1 370 Data Bus in high impedance read TRLOZ mode after RD active 50 TDVCL Data Bus setup time before clock transition ends T2 85 0 impedance LICLDX Data Bus hold time after 2 Ti TCLFL REFRESH active after start of T3 F200 TFLFH REFRESH pulse width 2222710 TSLAV STATUS 1 active after address valid HL Oo TSLSH STATUS 1 pulse width 5 800 X Address valid after start of Tl in any memory or 1 0 machine cycle Figures through FIGURE S OPCODE FETCH AND MEMORY REFRESH MACHINE CYCLE 10 ADDRESS BUS 0 15 MEMRQ RD DATA BUS 00 07 DATA BUS 00 07 NANOSECONDS SYMBOL PARAMETER MIN TAVDV Address valid to data valid read cycle access time 745 Address valid to write high write cycle access time 740 valid to M2. HH mn ill LE __ FIGURE 31E INSTRUCTION DIAGNOSTIC TABLE Pro Log M824 System Analyzer The M824 is a logic signal analyzer designed specifically for program debugging and hardware troubleshooting in Z80 based systems such as the 7803 Processor Figure 32 below summarizes the ability of the M824 to capture format and display the information available from all the time states within 280 machine cycle at any instruction step in the program The M824 operates in dynamic single step and breakpoint modes tracks interrupts and DMA operations can pick instructions out of nested loops for display and trigger other test equipment with program instruction synchronization The M824 is portable and clips onto the 280 on the 7803 eliminating the need for test probes and a long setup procedure INSTRUCTION CYCLE 18 SYSTEM ANALYZER 280 FIGURE 32 M824 ANALYZER 505555004 em _ 610 y O o warre lt 2 2 moe Q 805 ACK O lo PAGE St LINE NOT FOUND AODRESS INTERRUPT ion AUTOMATIC ese uction MESS INSTRUCTIONS nnn PAGE 55 39 29 par ue
3. 210201 2 1111 illi 1111 11 1 11111 11 11111111 5 1 1 MACHINE CYCLES i 46 INSTRUCTION DIAGNOSTIC TABLE FIGURE 31A gris ss 15 MACHINE CYCLES ls g gt 9 5 F H 2 8 sz 28 od 52 sis SE ci Ge 8 is jij BE i Hi ss x 1 Hi i iu 8 ss di iii i viva INSTRUCTION DIAGNOSTIC TABLE FIGURE ee 5 BN i ER i TEM 403 11111111 111111 HET TT eek TAATA TATA EEE 11111 3 1 4 dh bh VLYG 91 48 Di INSTRUCTION DIAGNOSTIC TABLE FIGURE ii st MEIEEEEET14338 NN 3 M aT ar LT aI ct gen diim tuu rome Im m TE FEPFFTPTTI 49 INSTRUCTION DIAGNOSTIC TABLE FIGURE
4. EXTERNAL INPUT n ADURESS CYCLE 9 0 1 DISPLAY ADOAESS a oness LATCH ors ENABLE TRIGGER TRIGGER 51 APPENDIX 7803 USER STRAPPING OPTIONS new 7803 applications system characteristics such as memory mapping are often arbitrary The as shipped configuration of the 7803 is recommended to minimize system assembly costs as well as field service and repair documentation efforts Most other Pro Log Series 7000 cards can be used with the 7903 without any jumper changes Jumper wire strapping options are provided on the 7803 to allow processor upgrading in existing applications firmware and compatibility with similar cards from other manufacturers The strapping options for the 7803 are identified by the letters A through F the Schematic Pro Log document 103218 Assembly Diagram 103219 and silkscreened letters on the 7803 circuit card The options include a Clock jumpers A and output clock to STD BUS or input external clock signal in place of the 7803 s crystal b Mapping and Bank Control jumpers 8 E remap or disable the onboard RAM and EPROM memory sockets and allow external control of 1 0 and memory bank selection IOEXP and MEMEX lines Clock Figure 33 Output Some devices and instruments require access to the system clock Jumper A Figure places the system clock on STD BUS pin 43 Note that the clock
5. T3 TRQ NANOSECONDS SYMBOL PARAMETER TQLCH 5 WAITRQ setup time prior to clock high T2 TCHOX WAITRQ hold time after clock high in T2 IL Low state High state FIGURE 12 WAIT STATE INSERTION IN OPCODE FETCH MEMORY READ AND MEMORY WRITE MACHINE CYCLES WAIT state insertion in all memory cycles is similar to the Opcode Fetch Memory Read and Memory Write cycles shown in 3 9 While WAITRQ is sampled halfway through time state T2 in these cycles however it is sampled at different times in 1 0 and interrupt acknowledge cycles 1 0 machine cycles sample WAITRQ at the rising edge of CLOCK during TW the single wait state inserted automatically by the Z80 in 1 0 cycles User inserted wait states occur after TW and prior to T3 Interrupt machine cycles sample WAITRQ at the rising edge of CLOCK during TWB the second wait state inserted automatically by the 280 during interrupt acknowledge cycles User inserted wait states occur after TWB and prior to T3 15 BUS REQUEST O The BUSRQ input and BUSAK output allow Direct Memory Access DMA operations giving another system controller card access to the 7803 s peripheral cards Figure 13 shows the timing for these signals 222 Last cycle af current First cycle of instruction next instrution Avai 1 TX TX TX 1
6. Low active iL Low state High state Valid Impedance X Don t care NANOSECONDS SYMBOL PARAMETER PORT ADDRESS 4 TAVIL TILIH TRLDZ TOVCH NS gt TCHDX NOVO lt 4 TAVWL si TWLWH TDVWH DATA out _ TAVDVG Address valid to data valid input cycle moj Address valid to WR high output cycle 11530 TAVIL Address valid to 10 5 active 1300 345 TILIH 10 pulse width 11000 TAVRL Address valid to RD active 300 355 pulse width 00 0 1000 TRLDZ Data Bus in high impedance read mode after RD low 50 100 TOVCH Input data setup time before clock high in T3 95 TCHDX Input data hold time after clock high in T3 O TAVWL Address valid to WR active 300 335 TWLWH WR pulse width 1 1000 0 2 Output data valid after address valid 1 300 Output data setup time before rising edge 220110701 TWHDX Output data hold time after WR rising edge TW WAIT state inserted automatically 280 1 0 cycles Note FIGURE YO INPUT PORT READ AND OUTPUT PORT WRITE MACHINE CYCLES 13 SSS MACHINE CYCLE mn m mw m LAST 1 CLOCK Ad VS ALLS
7. axe Designates Active Low Level Logic Clock Generator The 7803 s clock oscillator serves as the primary timing element in a 7803 based system The oscillator s output is divided by two to drive the Z80 microprocessor producing the time state clock The time state clock s period is the shortest program related period of interest in the system Instruction execution times are computed as whole multiples of the time state clock period Section 5 The 7803 is shipped with a crystal installed which sets the system s time state period If desired the user can substitute a slower crystal or replace the crystal with TTL compatible clock signal generated elsewhere Details of this option are given in Appendix A CRYSTAL OR RESULTING EXTERNAL CLOCK TIME STATE 400 ns 7803 time state fastest allowable rate for 280 device FIGURE 6 CLOCK OSCILLATOR FREQUENCY RANGE Slowest recommended rate for Z80 device Bus Timing Specifications An understanding of the 7803 s signal timing characteristics is necessary for the selection speed compatible memory devices 1 0 functions other peripheral STD BUS cards for real time logic analysis of 7803 based STD BUS card systems The 7803 s timing characteristics are established by its 280 microprocessor with additional delays added by LSTTL buffers The basic operations performed by the 7803 and the signals controlling these operations a
8. RETURN FROM INTERRUPTS LOAD INTERRUPT REGISTER TO OR FROM ACCUMULATOR MALT LOAD REFRESH REGISTER OR FROM ACCUMULATOR ADDRESS MACHINE FIGURE 24 8 280 INSTRUCTION TIMING SUMMARY 36 Instruction Timing Example The execution time for any routine or program segment is found by totalling all of the time states in all of the instructions executed The factors affecting the execution time of a program segment are a The clock frequency which determines the time state period Section b The specific instructions used which determine the number of time states in the segment Figure 24 The instantaneous Flag Register bit states which summarize processor conditions when the conditional instructions jump jump to subroutine return from subroutine are executed Figure Zl d The number of instruction loops within the instruction sequence and the number of times each loop is executed loop iterations the program segment has more than one entrance or exit every combination of routes through the segment that are used by the program should be considered The following example shows how to compute execution times in a program segment The Z80 is programmed to generate a series of five short pulses at an output port bit line Determine the overall execution time of the program segment and the period of the pulses generated the output port bit lines are low when
9. SEQUENCE RELATIVE 4001658 d 1 2 ume 4 Dow 08 m ow cm 4m um m 9 m x lt gt 280 PROGRAMMING MODEL 15 18 280 Architecture 280 architecture Figure 15 consists of l6 bit Instruction Register l6 bit Program Address Counter a 16 bit Stack Pointer two 16 01 Index Registers 8 bit Interrupt Page Register and two bank selectable sets of General Purpose Registers plus two bank selectable Arithmetic Logical Units ALUs A 6 bit Flag Register in each ALU bank holds processor condition code information An 8 011 autocounting Refresh Register supports dynamic RAMs Instruction Register The 16 bit Instruction Register provides storage and decoding for instruction opcodes as they are received from program memory The Z80 executes all of the 8080 instructions as a subset of instructions with 8 bit one byte opcodes and adds a large number of additional instructions of which most have 16 bit two byte opcodes The processor receives the first opcode byte from memory and decodes it to determine if a second opcode byte follows The instructions with 2 byte opcodes are identified by a first byte equal to hexadecimal CB DD ED or The complete instruction word may consist of address or d
10. SECTION 7 PROGRAM AND HARDWARE DEBUGGING O Microprocessor Logic State Analysis An attempt at monitoring the execution of a microprocessor program in real time using a conventional multitrace oscilloscope will be found to be impossible for practical purposes The capacity of the scope and the operator will be quickly exhausted by the following characteristics a P d addr Data is transferred as byte parallel information the address bus is 2 bytes wide Individual bits on these busses have little meaning in program debugging It is neces sary to see the full content of both busses at once and a hexadecimal display of numeric values is much more meaningful than binary waveforms b Display Trigger Qualification As many as 20 signals combined address and control signals may be used simultaneously to qualify the enabling of peripheral memory card for example In order to capture this event the test instrumentation must also be trigger qualified by the same group of signals Conventional oscilloscopes lack the number of trigger channels and operating modes needed to interface with a processor system such as the 7803 c Data Bus Voltage Levels and Timing The 7803 and all of its peripheral cards in a given system will drive the Data Bus at different times and will do so with a variety of logic high and logic low levels all of which are different but within specification This presents two problems 1 ope
11. 27 ADJUST Ere ROTATE CARRY ROTATE ACC MULTIPLE D67 WITH MEMORY LOAD ACC FROM REFSH LOAD ACC DIRECT INPUT OUTPUT INSTRUCTIONS BLOCK WORD FORWARD FORWARD BACXWARO INPUT OIRECT FROM PORT Px ACC a 078 TERI mE BY TO REGISTER NAMED Dwe MACHINE CONTROL INSTRUCTIONS moo cope OPERATION OISABLE INTERRUPT ED46 INTERRUPT MODE 0 EDSE INTERRUPT MODE 2 LDA EDS LOAD ACC FROM INTERRUPT REG RETURN FROM INTRO 00 NO OPERATION E BM te LOAD ACC FROM REFRESH REG ee HALT MOVE MEMORY WORD FROM HL TO DE INCREMENT FORWARD OR DECREMENT BACXWARD DE HL COUNT BC IF BLOCK REPEAT UNTIL BC 0 COMPARE WITH ML RESULT TO INCREMENT FORWARD OR OECREMENT BACKWARD HL DECRSMENT COUNT IF BLOCK REPEAT UNTIL ACC HL OR 9 INPUT FROM PORT DEFINED SY C STORE IN ML INCREMENT FORWARD OR BACKWARO HL DECREMENT COUNT BLOCK REPEAT UNTRA B OUTPUT DATA FROM ML TO PORT DEFINED BY INCREMENT FORWARO OR DECREMENT BACKWARD OECREMENT BLOCK REPEAT UNTIL 6 FIGURE 2 0 27 DECREMENT p IF B JUMP TO Z80 INSTRUCTION SET AUTOMATIC MEMORY OP
12. Execution times of 8080 identical instructions vary due to the number of time states required for execution some more some less in the Z80 and 8085 even if the processors are all operated at the same clock rate Consequently programmed timing such as count and test time delays will generally require modi f cation Flag Register bit 2 is the PV Parity oVerflow flag in the Z80 and parity only in the 8080 8085 The added overflow function is for signed binary arithmetic Since the parity and overflow functions are unrelated occuring at different times in most programs incompatibility does not usually result However the flag s activity is different overall and the program should be examined for sensitivity to the PV flag Except for the differences noted the 280 resets to 3080 compatibility and its additional features must be deliberately invoked by the program 22 STD INSTRUCTION MNEMONICS The STD Instruction Mnemonics are a standard set of processor instruction abbreviations suitable for use as an assembly language for writing programs These mnemonics are standard in that they do not change but keep the same meaning regardless of the processor they are applied to They are also standard in that they are derived from a set of easily understood rules The instruction mnemonic is an abbreviated action statement containing an operator locator and a qualifier plus a supplemental and separate modifier OP
13. Taste Last CLOCK BUSAK Floating BUSSES note NANOSECONDS SYMBOL PARAMETER a Low active Z Low impedance Drivers on TJKBZ Busses float after BUSAK active 22 35 65 BUSAK inactive after clock rising edge last DMA cycle _ TKHBD Busses driven after BUSAK inactive NOTE Busses refers to the Address Bus 0 15 the Data Bus 00 07 and the Control Bus lines MEMRQ 10805 805 INTAK REFRESH MCSYNC STATUS 15 and SYSRESET Other Control Bus lines are not floated FIGURE 13 BUSRO BUSAK DMA MACHINE CYCLES 16 Mechanical The 7803 meets all STD BUS mechanical specifications Refer to the Series 7000 Technical Manual for outline dimensions Environmental FIGURE 14 PARAMETER MAX Free Air Ambient o Operating Temperature Absolute Nonoperating Free Air Ambient 40 75 Celsius Temperature Relative Humidity ee 15119 Absolute Nonoperating Relative Humidity 100 Noncondens i ng ENVIRONMENTAL SPECIFICATIONS 17 280 ARCHITECTURE AND INSTRUCTION SET SECTION 4 Prat manic d INTERRUPT PAGE VECTOR 1 OYMAMIC MEMORY PROGRAM COUNTER LG Fo 1
14. Tc L INTRQ INTAK DATA BUS 00 07 LEGEND CLOCK Q iNTAK D DATA BUS L level High level 2 High impedance X j Don t care SYMBOL PARAMETER cree ae instruction cycle prior to interrupt 130 TCLOL iNTRQ hold time after clock lw ol m TKLKH INTAK pulse width INTAKE pulsa Widths KLOZ Data Bus in high impedance read after E2 INTAK low 35 75 DVCL Data Bus setup time prior to clock low cLox Data Bus hold time after clock low 4 Notes 1 Two WAIT states are automatically inserted by the Z80 to allow for priority chain propagation time 2 In interrupt mode 1 INTAK is asserted but the data bus is ignored 3 The above time state sequence assumes that the ENI enable interrupt instruction is in effect 4 INTAK 10808 plus buffer delays FIGURE I INTERRUPT REQUEST ACKNOWLEDGE CYCLE 14 WAIT REQUEST The WAITRQ input allows the 7803 to enter the WAIT state in any memory 1 0 or interrupt acknowledge cycle while a slow memory device responds or until a control function such as an analog to digital converter finishes WAITRQ can also be used to single step the 7803 Figure 2 shows the required timing for the WAITRQ input 14 CYCLE T2 TWAIT USER 1
15. 280 INSTRUCTION SET 25 MAMIPULATION ce 8 Zz if the selected bit 1 clear the 2 fag if the selected bit 9 set the 2 96 qeser 0 wb Clear the selected bit 66 FOCSrree SET 1 9 0 Set ihe selected bit ADO PAIR TQ THE M L PAIR AOO w CARRY TO HL SUBTRACT PAIR w CARRY FROM HL ADO TO INDEX REGISTER ADO PAIR TO INDEX REGISTER IY j O FE INCREMENT AEGISTER PAIR pe pep v accen som MOT LOAN ACC INDIRECT ame jet TM 0021608 219 6 LOAD PAIR IMMEDIATE LOPO Ped FOZAMLMP LOAD PAIR OIRECT FROM MEMORY ded dl 0065 PUSH PAIR STACK 2 Pe ee BANK SELECT REGISTERS o ee 3 EXCHANGE PAIR OE WITH ML LOAD STACK POINTER WITH PAIR EXCHANGE PAIR WITH TOP OF STACK JUMP CONDITION TO mime JUMP RELATIVE PC SUBROUTINE CONDITION mime RETURN FROM SUBROUTINE FIGURE 1Q 780 INSTRUCTION SET O 26 ACCUMULATOR CARRY CONTROL ste CLEAR ACC CARRY CLEAR CARRY FLAG SET CARRY FLAG COMPLEMENT CARRY COMPLEMENT ACC LOGICAL COMPLEMENT ACC ARITHMETIC
16. and compound instructions Figure 21 shows the bit organization of the 8 bit and 16 bit registers the effect of the shift and rotate instructions the allocation of memory by certain instructions and the action of the flags instructions not listed in the Flag Summary have no effect on the flags Figure 22 shows relative addressing constants SBIT LOAD STORE LOAD REGISTER A LOAD REGISTER 8 31111 LOAD REGISTER LDO LOAD REGISTER D LDE LOAD REGISTER E Lon LOAD REGISTER HHHH 71 STN 0071 bordi T STORE REGISTER INDIRECT FOTO 71 72 7 74 LOAD MEMORY IMMEDIATE F036rr dd BIT ARITHMETIC 00340 INCREMENT REGISTER 003 REGISTER 0086 DOSE SUB FROM 00 SUS w BOAROW FROM ACC LOGIC 0 6 6dd WiTH ACC DOAEn EEdd EXCLUSIVE OR WITM ACC 0006 FE do ROTATE SHIFT DOCS 08 ROTATE REGISTER ARITHMETIC FOCBrroe 8 SETS FLAGS O0Carri6 ROTATE REGISTER CARRY OOCRert amp ARITHMETIC 9 811 SETS FLAGS OOCBrr2s OOCSr2E oceana rocan smeT ONT LOGER M IE MOOWWER WILL BE EITHER ML 1 OR IY FIGURE 18
17. 1 0 Request is active c 1 0 Expansion is active d RD read is active to select an input port WR write is active to select an output port The 8 bit input ports provide a means for reading data or status lines into the processor to take part in programmed operations The 8 bit output ports provide a means for outputting program generated data or control states Typical input and output port circuits are shown in Figure 23 42 SYSRESET 744532 BUS BUFFERS OUTPUT PORT 9 07 9 07 07 2 oes aA EN pes 4 lt 2 Spe GLITCH 5 el Ta FREE USER O dem Nara 22 A Rl dem 22 mere bens nan dom RST CARD SELECT DECODERS INPUT PORT 87 5 9 07 161795244 4 9 561 4 e uade s A in rs ME A3 23 74L532 31 zur y io PORT SELECT DECODERS 0578 050 055 2 25 053 27 0823 0514 i 0502 FIGURE 29 TYPICAL INPUT amp OUTPUT PORT IMPLEMENTATION This figure illustrates the Bus interface and 1 0 port address decoding circuitry and device types typically used to implement 1 0 ports Pro Log s 7500 7600 and 7900 Series 1 0 modules are similar to this example 43
18. 1 6 4 4 11 6 us The total period of each pulse is 7 2 11 6 18 8 us 38 SECTION MEMORY AND 1 0 MAPPING AND CONTROL Memory Addressing The 7803 s l6 bit Address Bus can directly address 65 536 byte 64K memory A specific memory location is addressed when these conditions are met a The Address Bus contains the specific address of the memory location 0000 through FFFF hexadecimal b MEMRQ memory request and RD read or WR write control signals are active MEMEX memory expansion is active Other factors affecting the 7803 s control of its memory are a In the Interrupt Acknowledge Cycle the 7803 issues INTAK in place of the memory enable signals when responding to INTRQ This causes the interrupting device to provide an instruction or vector to the 7803 over the STD Data Bus b The 7803 can pause to wait for a slow memory mapped device or be single stepped by inserting WAIT states in memory access machine cycles See WAITRQ Section c The 7803 can disconnect from the STD BUS and enter the C WAIT state while Direct Memory Access DMA operations are conducted by an alternate system controller card DMA is controlled by the BUSRQ BUSAK Bus Request Bus Acknowledge signals typical memory implementation iscshown in Figure 2 12K Byte Onboard Memory The 7803 card combined EPRUM ROM and RAM memory the card which is large enough to store the progra
19. HL MEMORY INDEXED OR 1Y1 REGISTER MEMORY INDIRECT HL MEMORY INDEXED IX 1 REGISTER MEMORY INDIRECT HL MEMORY INDEXED IX OR IY ACCUMULATOR REGISTER ACCUMULATOR MULTIPLE WITH MEMORY HL MEMORY INDIRECT HL MEMORY INDEXED IX OR IY ADD TO HL ADDO SUBTRACT WITH CARRY TO HL AGO TO X OR IY INCREMENT OECREMENT PAIR EXCEPT OR INCREMENT OECREMENT OR IY LOAD IMMEDIATE TO 8C DE 32 LOAD IMMEDIATE TO IX OR IY LOAD HL TO OR FROM MEMORY DIRECT LOAD 3P IX OR IY OR FROM MEMORY DIRECT LOAD SP WITH HL LOAD SP WITH OR iY PULL AF 8C DE HL PULL IX OR iy WITH ML OF STACK WITH OF STACK WITH IY INPUT OR OUTPUT DIRECT INPUT OR OUTPUT INDIRECT 35 BYTES CYCLES STATES O4us 025us INSTRUCTION O s JUMP TO INTERRUPT 1t 37 t1 44 27 OIRECT ANY CONDITION 3 83 10 40 gt 3 12 48 309 2 3 2 4a 30 2 2 7 28 j 179 3 5 1 17 48 425 3 5 17 68 425 wormer 3 3 19 40 250 d 40 350 30 3 j n 44 1 275 Nor MET 1 10 sS 20 125 MOVE wORO BLOCK INPUT OR OUTPUT INPUT OUTPUT TO MEMORY INTERRUPT ENAGBLE OISABLE INTERRUPT SET INTERRUPT
20. PARTS UST TED NOTES 304 and USER S MANUAL PRO LOG 2411 Garden Road Monterey California 93940 Telephone 408 372 4593 TWX 910 360 7082 1067778 400 11 81
21. Sus in Out High Order Oata Bus Low Order Address Bus High Order Accress Bus Low Order Address Bus 5 High Order Address Bus Low Order Address Sus High Order Address Bus ADORESS Low Order Address Bus High Order Adaress Bus Low Order Address Bus High Order Address Bus Low Order Address Bus High Order Address Sus Low Order Address Bus Migh Order Address Low Order Address Sus High Order Address Bus Write to Memory or 1 0 RO Read to Memory or 1 0 IORQ Address Select MEMRO Memory Address Select IOEXP Expansion GNO MEMEX Memory Expansion REFRESH Retresh Timing MCSYNC CPU Machine Cycle Sync STATUS 1 CPU Status STATUS 0 CPU Status BUSAK Bus Acknowiedge BUSRO Bus Request INTAK interrupt Acknowiedge INTRQ Interrupt Request Wait Request NMIRQ interrupt SYSRESET System Reset 5 Push Button Aeset Clock from Processor AUX Timing EXT CLOCK Pnonty Chain Priority Chao in AUX Ground AUX GNO AUX Ground Bussed AUX Positive 12 OC AUX V AUX negaiss 12 vons OC Low Levei Active indicator STD BUS Pin Utilization by 7803 Since the STD BUS standard does not specify timing or require that all available pins be used the timing and signal allocation assumes many of the characteristics of the microprocessor type used The timing characteristics of the 7803 are those of its 280 micr
22. of time states in any given machine cycle is fixed the user can insert one or more WAIT states in the cycle WAIT states are added by driving the 7803 s WAITRQ line active during the T2 time state in the machine cycle where the WAIT state is desired Section for timing The WAIT state is a do nothing time period that can be used to interface slow memorjes to the 7803 or to cause the processor to pause while a slow system function such as an analog to digital converter or arithmetic processor completes its task The effect of holding WAITRQ active indefinitely is to halt the processor when WAITRQ is released the processor resumes operation with no change in its internal data or control states Note that the 280 adds one WAIT state to all 1 0 access machine cycles automatically Additional WAIT states can be added by the user if desired Naturally the addition of WAIT states must be included in the computation of program execution time in real time control applications Each WAIT state requires one full time state clock period 33 Mode Direct Memory Access DMA operations are controlled by driving the 7803 s BUSRQ line active when sampled at the end of any time state The processor will complete the current instruction then float its Data Bus Address Bus and many Control Bus lines Figure BUSAK then goes active The BUSAK output signifies that the 7803 s 3 state bus drivers are in the OFF condition al
23. output driver is not floated during DMA operations Input external clock can be used to drive the 7803 s clock oscillator This should be TTL compatible signal in the range of to 5 MHz with a 25 to 75 duty cycle The 7803 s clock circuit will divide this signal s frequency in half producing time states in the range 2000 ns to 400 ns The external clock input signal is assigned STD BUS pin 50 CNTRL Remove the following components from the 7803 Crystal Yl 2 2K resistors R3 and 84 1000 pF capacitor C5 Replace C5 with a wire jumper Add wire jumper F Figure shows the clock circuit before and after theiexternal clock input modification Mapping Figure 34 The 7803 s onboard memory sockets can occupy the lower quadrant of memory 0000 3FFF hexadecimal as shipped or the upper quadrant COOO FFFF or be disabled Figure summarizes these selections and shows the jumpers required to obtain them Bank Selection Figure 33 Jumpers D and E hold MEMEX and IOEXP respectively active by connecting the bus traces to ground on the 7803 card At least one additional 64K memory bank and one 256 1 0 port bank could be enabled on the same motherboard by employing memory and 1 0 cards which regard MEMEX and ILEXP as high level active signals 52 O 3 dINT X m 3 5 ue pe 5 3 Schematic 5 coordinates 5 86 7 8 33 PCO 38 37 36 35 clocks 9 d na Interna
24. program on the Stack using the SP as a memory pointer then jumps to memory address location 0066 hexadecimal Any return from sub routine instruction may be used to resume the interrupted program but a special RTN Return from nonmaskable interrupt instruction is included to inform any Z80 peripheral chips in the system that the interrupt is over INTRQ Maskable interrupt request can be disabled and enabled by the program and can operate in one of three modes 1 Mode 0 is identical to the 8080 interrupt system The processor issues INTAK interrupt acknowledge which is used as an enable signal by the interrupting device During INTAK the interrupting device places an instruction opcode on the 7803 Data Bus which the processor will execute Either a I byte or 2 byte opcode may be used If the opcode 13 part of multi byte instruction one or two additional bytes must be placed on the Bus following the opcode for example a jump instruction consists of l byte opcode and two addional bytes of jump address information Note The 280 will execute one interrupt acknowledge cycle and issue one INTAK pulse for a one byte opcode or two cycles with two INTAK pulses for a 2 byte opcode However it will not generate INTAK during any subsequent cycles that may be required by the specific instruction being executed 2 Mode 1 is the implied vector mode with the implied vector address equal to 0038 hexadecimal In Mode 1 any IN
25. 2000 23FF Note 2 2400 27FF 2800 2BFF 017 021 2000 2FFF 00 EFFF UNUSABLE 3000 3FFF FOOO FFFF Note 3 Notes 1 Refer to Appendix A for remapping option 2 of RAM two 2114 devices mapped addresses 2000 23FF are supplied with the 7803 3 Maximum 7803 addressing range is 60K 12K onboard memory plus 48K on external memory cards when the 7803 onboard memory is used If the onboard memory is disabled Appendix A maximum system memory size without bank selection is 64K and no mapping restrictions are imposed by the 7803 FIGURE 21 7803 ONBOARD MEMORY SOCKETS ADDRESS MAPPING 40 SUS BUFFER T SELECT DECODERS s mE 2 8 zi 1 Lv at as ae at 9 ar 2946244 0 mennar 3 wwen MOVES MEMORY IN Ho ELS ASSEMBLY 102714 SCHEMATIC 7 7702 PARTS LIST 102715 Hur APER EPROM MEMORY EVES P7 CARD 5 E Input Output 1 0 Port Addressing The 7803 can address up to 256 each input ports and output ports The port address appears on the low order half of the Address Bus A0 A7 and is repeated on the high order half of the Address Bus 8 15 A specific 1 0 port is addressed when the following conditions are met a The Address Bus 0 7 contains the specific address of the 1 0 port 00 through FF hexadecimal b 10805
26. ELATIVE OFFSET ADDRESS FOR 0 THAU 127 COUNTS 10 40 11 41 12 42 13 43 15 16 17 18 19 18 1C 10 18 1 48 49 50 51 8 SEIERE R 102 103 104 105 106 8 138 8888 8585 8 8 8 8 8 8 8 8 28888 8686788 44 68 50 5 gt 108 109 110 111 40 4 4F 9959 9809 gt 55 0 687 6 6485 586 62608268 RRSBSBSBBARRRBANB 55 565 55 8 a 52 88 COUNT ZERO AT SECOND ADORESS AFTER JUMP MNEMONIC ADORESS FOR 0 THAU 126 COUNTS OF CF BF AF DE CE oc 88 AA 09 89 9 08 7 87 06 6 05 04 2 N 5 C4 A4 C3 A3 A2 A1 2 2 01 C1 00 90 96 m 45 5 6532 866634 SB2 RBFERRSRSEBSSESRSBBES COUNT ONE AT FIRST ADDRESS AFTER JUMP MNEMONIC FIGURE 22 DECIMAL HEXADECIMAL RELATIVE OFFSET TABLES 29 Interrupts 7803 has two interrupt request inputs which are accessable at the STD 805 backplane NMIRQ pin 46 and INTRQ pin 44 The characteristics of these interrupts are NMIRQ Nonmaskable interrupt request cannot be disabled by the program The processor stores the address of the next instruction in its
27. EMRQ active i 75 ET E Low active L Low state High state bats Bus in high impedance read mode after RD low Input data setup time before clock high in T3 J TCHDX Input data hold time after clock high in T3 Co ed Iul Address valid to WRZ active aol pulse width 400 Output data valid after address valid 11300 Output data setup time before rising edge ae ee Output data hold time after WR rising edge FIGURE 4 MEMORY READ EXCEPT OPCODE AND MEMORY WRITE MACHINE CYCLES 11 Note onboard memory read operations Section 6 the Data Bus does not enter the high impedance read mode Instead the 7803 drives data fetched from the onboard memory sockets onto the STD Data Bus to facilitate logic state analysis at the motherboard The access time for onboard memory devices may not exceed the values shown for TAVDV in Figure 9 The state of the Data Bus prior to is unspecified for an onboard read operation 12 ge CYCLE T2 T3 T TW Note CLOCK 22 72 ADDRESS BUS 0 7 10805 RD DATA BUS DO D7 WR DATA BUS 00 07 AO A7 D 00 07 1 80 Mj WR CLOCK
28. ERATIONS REGISTERS C E L dM REGISTERS 8 D M NOTE This table shows how the processor allocates memory automatically when certain instructions are executed For example the PLP instruction pulls a line address or low order register C E F L increments the SP then pulls a page address or high order register 8 0 and increments the SP again leaving the SP two counts higher than its initial value FLAG SUMMARY SUA SCA CMAA ANA ORA CLC AJA CHAL SEC ALA RRA RLAC RRAC ARLIC RAxC SL2A SAZA IPWF 1 8 OPWS POF 1 MVWF CPWE CPWB NOTES 2 D P C FLAG CHANGES ACCORDING TO OPERATION RESULT 0 1 FLAG ASSUMES SPECIFIC LOGIC STATE SHOWN FLAG 1 IF ENI EFFECT ELSE 9 CTR PV FLAG 1 IF COUNTER Q ELSE 9 FLAG UNOEFINED SLANK NO CHANGE 28 SHIFT ROTATE SUMMARY SHIFT DIRECTION RLzA RRxA RLA RRA 8 BIT ROTATE ALZC AR2C ALAC ARAC 9 GIT ROTATE REGISTER ORGANIZATION 158 58 A B C D H L I R Ports 5 8 0 1 LSB 3 2 REGISTERS SP REGISTER PAIRS HL FIGURE 24 SUPPL MENTARY INFORMATION INSTRUCTION T FORWARD R
29. ERATOR INSTRUCTION DESCRIPTION ar sd Peters rom Subroutine RAINER poe EOE CC ST ETT Load indirect using to Subrouti ss _ taser 1 The operator is a unique two letter abbreviation that suggests the action 2 The locator follows the operator and designates the operand or data to be operated on instruc tions without operands ignore the locator 3 The qualifier states the addressing mode provides further qualifying information tor compound instructions 4 The modifier carries detailed support informa tion labels conditions addressing and data The operator locator and qualifier letters arestrung together to form the instruction mnemonic The modifier when needed stands alone either in its Own separate column or separated by spaces or additional lines in written text Figure 19 Examples of instruction Mnemonic Structure 23 The following table lists the STD mnemonic operations locators modifiers qualifiers and other notation used in the instruction tables for the Z80 in this section STANDARD j ame 4 WITH CARRY AOJUST DECIMAL BANK SELECT CLEAR COMPARE OISABLE ENABLE MALT INCREMENT INPUT FROM PORT JUMP TO INT
30. ERRUPT JUMP JUMP TO SUBROUTINE LOAD MOVE MEMORY NO OPERATION OUTPUT TO PORT INCLUSIVE PUSH PULL VIA LEFT RIGHT RESET RETURN VIA STACK T se STORE 44 27 25 FIGURE 17 ACCUMULATOR REGISTER GENERAL 3 817 REGISTERS FLAG REGISTER Set if Subtract Parity Overttow Flag State ot indicated flag ACCUMULATOR FLAGS PAIRED GENERAL AEGISTER PAIRS 16 81 DATA POINTERS REGISTERS ANY REGISTER PAIR ANY SINGLE REGISTER MEMORY ADORESSED INOIRECTL Y CONTENTS OF A MEMORY LOCATION INTERRUPT NONMASKABLE INTERRUPT SUBROUTINE PROGRAM COUNTER POINTER gag lt amp 5244 STD Mnemonics 24 WITH CARRY ANO JUMP OIRECT ADORESS OR DECIMAL IMMEDIATE DATA INDIRECT AOORESS AOORESS RELATIVE ADQORESS TOP OF STACK WORO FORWARD SLOCX FORWARO WORD SACXWARO BLOCK SACXWARO ARITHMETIC LOGICAL MOOE OR MULTIPLE UNCONDITIONAL NONMASKAGLE INTERRUPT MOST SIGNIFICANT SIT LEAST SIGNIFICANT BIT JUMP CONDITION PORT ADORESS MEMORY LINE ADORESS 10 6 ADORESS RELATIVE OFFSET SIT DATA 16 017 DATA The 280 Instruction Set Figures 18 19 and 20 show the full Z80 instruction set with STD mnemonics and hexadecimal operation codes The tables are grouped by 8 bit register operations 16 bit register pair operations ALU Accumulator and Carry program address control 1 0 machine control
31. HE STD BUS The STD BUS standardizes the physical and electrical aspects of modular 8 bit microprocessor card systems providing a dedicated orderly interconnect scheme The STD 805 is dedicated to internal communication and power distribution between cards with all external communication made via 1 0 connectors which are suitable to the application The standardized pinout and 56 connector lends itself to a bussed motherboard that allows any card to work in any slot As the system processor and primary system control card the 7803 is responsible for maintaining the signal functionality defined by the STD BUS standard A complete copy of the STD BUS standard is contained in the SERIES 7000 STD BUS TECHNICAL MANUAL available from Pro Log Corporation 2411 Garden Road Monterey California 93940 STD BUS Summary The 56 STD BUS is organized into five functional groups of backplane signals 1 Logic Power Bus pins 1 6 2 Data Bus pins 7 14 3 Address 8us pins 15 30 4 Control Bus pins 31 52 5 Auxilary Power pins 53 56 Figure 2 shows the organization and pinout of the STD BUS with mnemonic function and signal flow relative to the 7803 Processor card cur oe DES m mm RETO 5 Voits OC Bussed 5 Voits OC Digital Ground Bussed Digital Ground 5 Voits OC 5 Voits OC In Out High Order Oata In Out High Order Data In Out High Order Oata
32. INT ks Synchronous processor halt WAIT NMIRQ in Nonmaskable interrupt request NMI YSRESET 47 Out System power on and pushbutton Onboard one shot reset output PBRESET 18 in Pushbutton reset input CLOCK jw Time state clock 1 2 crystal Onboard oscillator frequenc CNTRL External clock input 2 times desired time state frequency PCI PCO 52 51 Priority chain PCI shorted to no other 7803 connection BUSRQ Low level active Output buffer disabled when BUSAK active Denotes equivalent Z80 signal name FIGURE 3 7803 CONTROL BUS SIGNALS Q 7803 Processor Status MCSYNC STATUS 1 MCSYNC and STATUS 15 signals provide status information which 15 peculiar to the Z80 microprocessor These signals are useful for displaying processor status in logic signal analyzers and can be used to drive 280 peripheral chips and systems designed to work with the Z80 specifically The use of these signals is not recommended in systems where microprocessor device type independence is a design goal MCSYNC is obtained by ORing the read write and interrupt acknowledge signals Thus MCSYNC occurs once in each machine cycle Section 3 and can be used to allow a logic signal analyzer to select a specific cycle within a multi cycle instruction for analysis The timing of MCSYNC varies according to machine cycle type STATUS 15 is equivale
33. TRQ results in a subroutine jump to 0038 3 Mode 2 is the supplied vector mode The user preloads Register I with the page address of an interrupt vector lookup table which is part of the program When the interrupt is acknowledged by the processor a single INTAK pulse is issued which causes the interrupting devic e to place the correct memory line number of the interrupt vector lookup table onto the STD Data Bus The processor will then go to the lookup table at the address supplied by the peripheral read a 16 51 memory address from two sequential entries in the table line address followed by page address and jump to that location in memory 30 INTRQ is enabled by the instruction and disabled by any of the following a Power on or reset b The DSI instruction Previous response to INTRQ d Previous response to NMIRQ 280 Peripheral Chip Considerations When used with 280 peripheral chips such as the or 510 these considerations and others may apply a n Mode 2 the l byte vector supplied by the interrupting device must be an even number with bit 0 0 This is a requirement of the peripheral chips not the 7803 which will accept odd or even vectors b In Mode 0 with either JS or Jl instructions inserted and in Modes and 2 the interrupt routine should be terminated with RTI for INTRQ or RTN for NMIRQ instructions These execute like RTS in the 7803 but the special opcodes infor
34. _ 25 PRO LOG CORPORATION STD 7000 7803 Z 80 Processor Card USER S MANUAL Son atte eS The information this document is provided for reference only Pro Log does assume any liability arising out of the application or use of the information or products described herein This document may contain or reference information and products protected by copyrights or patents and does not convey any license under the patent rights of Pro Log nor the rights of others Printed in U S A Copyright 1981 by Pro Log Corporation Monterey CA 93940 All rights reserved However any part of this document may be reproduced with Pro Log Corporation cited as the source 7803 Z 80 Processor Card USER S MANUAL DIL PRO LOG CORPORATION 1191 7803 USER S MANUAL TABLE OF CONTENTS SECTION gt TITLE PAGE PRODUCT OVERVIEW 1 2 THE STD BUS 2 STD BUS Summary 7803 Pin Utilization Control Bus Signal Table Processor Status Signals Dynamic RAM Control 3 7803 SPECIFICATIONS 6 Power Requirements Drive Capability and Loading Clock Generator Timing Specifications and Waveforms Mechanical Environmental 4 280 ARCHITECTURE AND INSTRUCTION SET 18 280 Programming Model Program Compatibility with 8080 8085 STD Instruction Mnemonics Z80 Instruction Set Interrupts 5 PROGRAM INSTRUCTION TIMING 32 Introduction Machine Cycles WAIT Sta
35. ata information in addition to a l byte or 2 byte opcode The full instruction may be up to four bytes 32 bits long Additional words of multi byte instructions bypass the instruction register These words may be be immediate data for registers a memory or 1 0 port address for direct addressing or an offset address for indexed relative addressing Program Address Counter PC The l6 bit Program Address Counter keeps track of the location of the next instruction to be executed from the program memory The PC increments automatically for each instruction word unless the instruction is a jump or subroutine return which modifies the count by loading a new address Stack Pointer SP A l6 bit auto counting Stack Pointer provides the address of the subroutine return address stack location in RAM memory The SP is used for controlling subroutines and interrupts and can also be used to push and bull data in memory at high speed Subroutine return addresses are automatically stored on the stack when a jump to subroutine instruction is executed and are retrieved when a return from subroutine instruction is executed 280 mode and 2 interrupts are treated as subroutine jumps taking advantage of the SP s return address storage and retrieval ability All of the General Purpose Register Pairs and the ALU registers can be stored and retrieved from memory using the SP as an indirect address register The resulting 16 bit data movement and au
36. available from Zilog 10460 Bubb Road Cupertino CA 95014 280 Dynamic Interfacing Techniques available from Mostek 1215 W Crosby Rd Carrollton TX 75006 SECTION 3 7803 SPECIFICATIONS Requirements RECOMMENDED m LIMITS E een ps e mn FIGURE 4 7803 POWER SUPPLY SPECIFICATION NOTES 1 In order to guarantee correct operation the following power supply considerations apply a Vcc rise must be monotonic rising from 40 50 Volt to 44 75 Volts in 10 ms or less b If Vcc drops below 4 75 Volts at any time it must be reduced to less than 0 50 Volt before restoration to the specified operating range RAM sockets on the 7803 are loaded Subtract 75 per 2716 EPROM and 50 mA 21141 RAM for each device not used 2 Ice specification assumes that all EPROM and 21141 devices require 10 milliseconds minimum after initial power on for stabilization of internal bias oscillators The 7803 s power on reset one shot provides adequate stabilization delay only if Vcc risetime is less than 10 milliseconds Drive Capability and Loading The 7803 s STD 805 Edge Connector Pin List Figure 5 gives input loading and output drive capability in LSTTL toads as defined by the SERIES 7000 TECHNICAL MANUAL In general input lines and disabled 3 state outputs present 5 LSTTL inout loads maximum one LSTTL or MOS input plus 4 7K p
37. c logical and load store operations that can be performed on the General Purpose Register Pairs can generally be performed on the Index Registers although fewer instructions apply to and IY than to the BC DE and HL pairs Input_and Output Ports 1 0 1 0 is mapped independently of memory with separate control signals and instructions The OPA instruction writes data from the Accumulator to output ports and the IPA instruction reads data from input ports to the Accumulator A specific port is specified by the second byte of the instruction allowing up to 256 each 8 bit input and output ports the 7803 all 1 0 ports are provided on separate cards Communication with the ports be direct from memory using HL as an address pointer when the Z80 s Compound Instructions below are used Compound Instructions The Z80 s instruction set contains several compound instructions which perform multiple functions with or without automatic looping These are implied sequence instructions which execute a fixed sequence of other instructions in the instruction set They perform block multiple byte moyes within memory search memory and input or output to or from memory fo the 1 0 ports Register C as a port address pointer HL as a memory address pointer One compound instruction performs automatic count and jump functions for loop control alone The compound instructions require approximately as much eine instruction s
38. ct address registers for operations with other 8 bit registers memory and the Accumulator n arithmetic operations carries and borrows are propagated from the low order 8 bit register into the high order register automatically Arithmetic Logical Unit ALU ALU consists of an 8 bit Accumulator Register Register A and a 6 bit condition code or Fhag Register Register plus arithmetic logical shift and control circuitry needed to execute the program instructions The A and F register are treated as the AF Register Pair for push and pull operations involving the Stack Pointer Register The ALU is duplicated in two banks with bank switching accomplished by a single instruction similar to the General Purpose Registers The enabled ALU provides add and subtract with or without carry AND OR Exclusive OR compare shift rotate and byte complement operations ALU operations are performed on the Accumulator from other registers or memory with direct indirect indexed or immediate addressing The Accumulator is the primary register for 1 0 communication The Accumulator can decimally adjusted and allows 4 bit nibble swap operations with memory for Binary Coded Decimal BCD arithmetic Register F contains the following flags C Carry Borrow from Accumulator bit 7 arithmetic or rotate D Carry for BCD arithmetic from Accumulator bit 3 Specifies whether last operation was subtract allowing different algo
39. equences they replace but offer program memory savings by eliminating instruction storage for common program functions Interrupt The Z80 offers three interrupt modes 0 identical to the 8080 interrupt system implied vector interrupt Restart at 0038 always 2 supplied vector interrupt with a single byte supplied by the interrupting device In interrupt mode 2 the content of the Interrupt I Register s the vector page address and the byte supplied by the interrupting device s the vector Tine address Together they form l6 bit memory address which is the indirect address of the interrupt service routine for that device Mone WwTEKR UPT in FORMATION 13 AT THE EVD Of THIS SECTION Refresh Register R 280 contains 8 bit Refresh Register which is used to address dynamic RAM devices external to the 7803 card In conjunction with the REFRESH control signal the processor can automatically refresh dynamic RAMs during the opcode fetch portion of the instruction cycle This function is applicable primarily to certain dynamic RAM devices available from the manufacturers of the 280 chip 21 280 Program Compatibility with 8080 8085 Both the 280 and the 8085 include al of the 8080 instructions as subset and these instructions are all machine language compatible Programs written exclusively in 8080 opcodes will execute on the 280 wi th the following considerations 1
40. es on the following pages are used with a logic signal analyzer They show the type of data on the Data Bus for time states 72 and T3 within each machine cycle and the machine cycles within any giyen instruction This information is useful when debugging a program or troubleshooting the 7803 or any hardware under the 7803 s control In addition to expected data and processor status for Tl T2 and T3 the TIME STATES column in each machine cycle shows the total number of time states for that cycle If there are one or more time states after T3 the processor is performing an internal operation the signals at the Z80 chip pins are either unchanged from T3 or undefined with no new information available until the next Because of the size the 280 instruction set the Instruction Diagnostic Tables are separated into the following sheets by instruction type INSTRUCTION CATEGORY INSTRUCTION TYPE GURE 8 Bit Memory Carr Data dal s erm Logical 31A E CNET Decrement 31B 16 Bit Add 5 Sire 1 Decrement 31 Da ta Push 6 Pull Bank Select compound Block Memory Move Search 31D Block 1 0 310 Machine Contro Halt NOP FIGURE 30 INSTRUCTION DIAGNOSTIC TABLES INDEX 45
41. l clock with clock output on STD BUS GINT X 7 NMI 3 8 15 vie CNTRU SO 4 280 1 3 e 40 PCO 39 PA I 58 m g INS COKE L504 35 External clock drive with clock output removed from STD BUS FIGURE 35 Jumper options for external clock drive and clock output Note Some 7803 versions prior to May 1980 use 1 2 3 notation instead of A B C Jumper pad locations JUMPERS ON CARD WIRING SDE 53 MEMORY ADDRESS ASSIGNMENT JUMPER WIRES _ ge sai 0000 FFF 2000 2FFF 3000 3FFF OPEN JUMPER 000 0FFF 000 000 JUMPER 744532 6 Schematic coordinates 84 5 Jumper shown shipped position FIGURE 34 ONBOARD MEMORY MAPPING OPTIONS 54 APPENDIX 8 55 DOCUMENTATI ON RPORATION 2803 SSOR CARD 67 REFRESH 1 4 4 4 4 3 Ad Gh Bh 2h amp a 8 5 5 5 3 4 8 3 853 56 49 fens oe Pew ery yes MENTA INDICATE Pin NO SOCKETS 1 FOR 4561 PROCEDURES GEE 04 NOTES UNLERS OTHERWISE SPECIFIED e Ew SCHEMATIC
42. lowing an alternate system controller card to operate the 7803 s memory 1 0 and other peripheral cards Internally the 280 is halted a manner similar to the WAIT state with internal data and control states unaffected by the DMA operation BUSRQ can be held active indefinitely but the dynamic RAM refresh operation is halted during DMA operations Note the 7803 s onboard memory sockets are not accessable in DMA mode and the processor can t be interrupted by INTRQ NMIRQ Instruction Timing Table The table in Figure 24 shows the actual number of memory bytes machine cycles and time states required for all of the Z80 instructions Two time state periods are included for convenience with the full execution time of the instructions shown for each 34 8 BIT DATA 16 BIT DATA LOAD STORE INSTRUCTION ACCUMULATOR CAARY ADO SUBTRACT LOGICAL INCREMENT OECREMENT FIGURE 24 280 INSTRUCTION TIMING SUMMARY OESCRIPTION REGISTER TO REGISTER IMMEDIATE TO REGISTER ACCUMULATOR TO OR FROM MEMORY DIRECT ACCUMULATOR TO OR FROM MEMORY INDIRECT BC OE ML REGISTER TO OR FROM MEMORY INDIRECT HL IMMEDIATE TO MEMORY INDIRECT HL REGISTER TO OR FROM MEMORY INDEXED X OR Iv IMMEDIATE TO MEMORY INOEXED IX OR 1Y ACCUMULATOR TO OR FROM INTERRUPT OR REFRESH AJAD CMAL CLAC CLC SEC CMAA REGISTER IMMEDIATE MEMORY INOIRECT HL MEMORY INDEXED IX OR 1Y AEGISTER MEMORY INOIRECT
43. m and variable data required in many applications without the nee for additional external memory cards The card is shipped with IK of RAM and sockets which allow the user to add up to 8K of EPROM or masked devices and 72 expand the RAM to The onboard memory sockets have addressing restrictions Figure 27 and are not accessatle in operations The onboard memory is organized as follows a EPROM ROM sockets provide capacity for four 2716 or equivalent single 5V supply EPROM devices which can be mixed in any combination with 2316 or equivalent masked ROMs Each device is a 2048 byte 2K read only memory for a total capacity of 8192 8K bytes All of these devices are supplied by the user b RAM and RAM Sockets provides two 21141 or equivalent RAM devices organized as a 1024 1K memory and sockets for six additional user supplied 2114 RAMs The 2114 15 1024 4 device and two chips are required for each of RAM added to the card The total RAM capacity of the 7803 with all sockets loaded is 4096 4K bytes Figure 27 summarizes the addressing options for each of the memory chip sockets MEMORY DEVICE FULL HEXADECIMAL ADDRESS FIELD 5 DESIGNATION AS SHIPPED USER OPTION Note 0000 07FF 000 C7FF 0800 OFFF C800 CFFF 1000 17 0000 D7FF 1800 IFFF 0800 000 E400 E7FF E800 EBFF U20 U24 019 023 018 022
44. m the peripheral chips that the interrupt routine is over The peripheral chips then respond by restoring the state of the serial Priority Chain is recommended that the user thoroughly acquaint himself with all the characteristics of any peripheral chips4before attempting the program design 31 SECTION 5 PROGRAM INSTRUCTION TIMING Introduction The execution of a program instruction is a sequential process The time state clock is used to step the Z80 through a specific sequence for each instruction type The execution time for each instruction is the total of the time states needed by the instruction with the time state period set by the processor s clock oscillator An understanding of the 280 5 instruction execution timing is important in real time programming where the program s execution rate is precisely matched to the speed requirements of the application When using a signal or logic analyzer a knowledge of the time state sequence makes it possible to predict the data and control states present on the STD BUS backp ane and at the Z80 chip pins at any given instant in the execution of a program Figure 31 Machine Cycles Each transaction between the 280 and its memory and 1 0 ports requires a distinct time period called a machine cycle Machine cycles are composed in turn of time states with specific activity occurring in each time state Although the number of time states and machine cycles vary among different ty
45. nt to the Z80 s signal which denotes the opcode fetch or interrupt acknowledge cycle is ANDed with IORQ internally to produce INTAK and externally with MEMRQ to denote opcode fetch De Note that the 280 has both I byte and 2 byte opcodes 2 byte opcodes are identified by a first byte equal to CB DD ED FD hexadecimal Accordingly the processor asserts STATUS 15 in each opcode byte or twice per instruction cycle for these instructions Dynamic RAM Control REFRESH The Z80 microprocessor chip is specifically designed for refreshing standard 16 dynamic RAM chips with multiplexed address lines and 4K x 1 or 16K x internal organization These devices can be refreshed transparently uring the opcode fetch memorv cycle without complex processor synchronization circuitry and without delaying processor instruction execution time The REFRESH output signal occurs during T3 and T4 of the opcode fetch cycle fig 8 and is used to indicate that a memory refresh address is present on the Address Bus The address is composed of a presettable autocounting 7 bit address 0 6 which is the lower seven bits of the Z80 s R Refresh Register and an eighth bit A7 which is the R Register s most significant bit and is program settable in the high or low state For information on dynamic RAM refreshing refer to the following publications Interfacing 16 Pin Dynamic RAMs to the Z80A Microprocessor
46. oprocessor with LSTTL buffering added to enhance the card s drive capability The allocation of STD BUS lines for the 7803 is given below Logic Power Bus 5V pins 1 2 and Logic Ground Pins 3 4 supply operating power to the 7803 Pins 5 and 6 are open 2 Data Bus Pins 7 through 14 form 8 bit bidirectional 3 state data bus as shown in Figure 2 High level active data flows between the 7803 and its peripheral cards over this bus When the 7803 fetches data from its onboard memory sockets this data also appears on the STD Data Bus Except during Direct Memory Access DMA operations the 7803 controls the direction of data flow with its MEMRQ IORQ RD and INTAK control signal outputs Peripheral cards are required to release the data bus to the high impedance state except when addressed and directed to drive the data bus by the 7803 The 7803 releases the Data Bus when BUSAK is active in response to RIISRNX as in DMA operations 3 Address Bus Pins 15 through 30 form a l6 bit 3 state address bus as shown in Figure The 7803 drives high level active l6 bit memory addresses over these lines and 8 1 0 port addresses over the eight low order address lines A0 through A7 on pins 15 17 19 21 23 25 27 and 29 The 7803 releases the Address Bus when BUSAK is active in response to BUSRQ as in DMA operations Control Bus Pins 3l through 52 provide control signals for memory 1 0 inter
47. pes of instructions they are precisely predictable for any given instruction Figure 23 is a timing diagram for the STAD STore Accumulator Direct instruction This instruction requires four machine cycles through M4 with a total of 13 Q time states Four machine cycles are necessary because the instruction accesses memory four times INSTRUCTION CYCLE MACHINE CYCLE T T2 T3 TIME STATE T T2 T3 T 2 T T2 CLOCK CYCLE MEMORY READ MEMORY READ MEMORY READ THE ADDRESS CONTENTS OF THE THE ADDRESS PC 1 THE ADORESS c 29 elec pat LR PROGRAM COUNTER POINTS TO POINTS TO THE SECOND POINTS TO THE DIRECT AOD ADDRESS BUS yg FIRST BYTE OPCODE OF THE BYTE OF THE Byrn HE INSTRUCTION INSTRUCTION oF me Lew HIGH ORDER BYTE OF ACCUMULAT 415 808 nro HOM THE THE DIRECT ADORESS output to memor FIGURE 23 PROCESSOR TIMING FOR STAD INSTRUCTION 32 The first machine cycle in the instruction in Figure 23 is used to read and decode the operation code opcode from program memory is called the opcode fetch cycle and can be identified by an active pulse on the STATUS 15 output from the 7603 also at the pin on the 280 chip Many 280 instructions use 2 byte opcodes If the first byte has a hexadecimal value of CB DD ED or FD a second byte is required The Program Counter is incremented and the Ml c
48. rator will find it difficult to identify the source of any given waveform on the scope display 2 order to see a specific data segment the Data 845 the operator will find it necessary to synchronize the display with the processor s software program rather than with the voltage output of any one element of system hardware The logic state analyzer solves these problems by displaying formatted high low or numeric logic states rather than analog waveforms and by offering enough trigger channels andcoincedence logic to allow literal program display synchronization A logic state analyzer is considered an essential troubleshooting aid for both program development and system maintenance in any 7803 based system where the needs of the Manufacturing Test and Field Service organizations are important considerations The logic state analyzer performs these basic functions a Tracks the actual instruction sequence as the program executes facilitating program debugging b Monitors control states and data passing between the processor and the system it controls allowing the system external to the processor card to be observed at the same time as the program flow using the same display Provides a multi qualified trigger to a conventional oscilloscope when analog measurements are unavoidable e g propagation delay through a suspected memory device O 44 Instruction Diagnostic Tables The Instruction Diagnostic Tabl
49. re shown in Figure 7 OPERATION WAVEFORM Read from memory 8 and 9 MEMRQ 10805 RD Read from an input port Figure 10 0 7 10805 WR 5 A0 A7 INTAK Read an interrupt instruction vector Figure response to INTRQ only FIGURE 7 53 7803 OPERATIONS RD The waveforms on the following pages show timing measurements as a 5 letter code as follows First letter is always for Timing measurement Second letter is the abbreviation of the signal which starts the measurement 1 Third letter is the condition of the start signal H High Fourth letter is the abbreviation of the signal which ends the measurement AwAddress bus TCHAVe Fifth letter is the condition of the end signal VeValid For example TCHAV stands for Time from Clock High until Address Valid Specific abbreviations are given in the Legend on each page of the specification In the case af the Clock it is necessary to note which time state is of interest refer to figures 8 through 13 eau MACHINE CYCLE 12 T3 T4 TI f CLOCK TCLAV 27 TAVDV ADORESS BUS 0 15 INSTRUCTION ADDRESS REFRESH ADDRESS ja _ MEMRQ TAVML 7 TRLRH i TRLDZ TCLDX TOVCL cl DATA BUS 00 07
50. rithm for BCD operations 2 Zero resulted from the last Accumulator operation 5 Sign for signed binary arithmetic same as Accumulator bit 7 Parity Overflow signed binary arithmetic dual function flag function depending on last instruction shows whether NTRO is enabled when tested after the LDAI instruction Figure 21 The C Z S and PV flags can be tested by the conditional jump and subroutine return instructions Special instructions allow the C flag to be set cleared and complemented When pushed pulled on the Stack via the Stack Pointer as part of the AF register pair the F register occupies 8 bits with the state of bits 3 and 5 unspecified The states of the six flags can be preset by pulling program prepared bits into Register the states of the untestable flags D N can be determined by pushing Register F onto the Stack then pulling the Stack data into a General Purpose register Index Registers IX and IY The 16 bit Index Registers are used as indirect memory address registers The address supplied by IX and 1 is modified by relative offset which is one byte of the multibyte indexed instructions The O Index Registers address memory to allow memory bytes to take part in the arithmetic 20 and logical operations described above for the single 8 bit General Purpose Registers When modifying the address content of the Index Registers IX and IY 2258 ted as Register Pairs The arithmeti
51. rupt and fundamental system operations Figure 3 summarizes these signals and shows how they are derived from Z80 signals The 7803 releases the Control Bus during BUSAK in response to BUSRQ except for the following output signals MEMEX IOEXP BUSAK PCO CLOCK 5 Auxilary Power Bus Pins 53 through 56 are not used by the 7803 and are electrically open The 7803 meets all of the signal requirements of the STD BUS standard Detailed timing information and specifications are in Section 5 MNEMONIC PIN IN OUT FUNCTION HOW 290 Write to memory or 1 0 Read from memory 1 0 RD 10805 33 0 7 hold valid 1 0 address 110805 MEMRO KEKE 0 15 hold valid memory IOEXP 35 oue 1 0 expansion control User removeable ground MEMEX 56 out Memory expansion control User removeable ground rerresH 37 Out Dynamic RAM refresh control RFSH MCSYNC 38 One pulse per machine cycle RO WR 10805 1 STATUS 1 dou Active during opcode fetch M1 STATUS 0 Not used Electrically open BUSAK ptt Acknowledges BUSRO BUSAK BUSRQ Bus request for DMA synchronous processor halt and INTAK 43 Out Acknowledges INTRQ and replaces RD3 MEMRQ to read 10 15 1 interrupt vector _ _ 3 state driver disable INTRQ lin Maskable interrup t request
52. tes DMA Mode Instruction Timing Table Instruction Timing Example 6 MEMORY AND 1 0 MAPPING AND CONTROL 39 Memory Addressing 12K Byte Onboard Memory Input Output Port Addressing 7 PROGRAM AND HARDWARE DEBUGGING 44 Microprocessor Logic State Analysis Instruction Diagnostic Tables M824 System Analyzer APPENDIX A 7803 STRAPPING OPTIONS 52 APPENDIX 8 SCHEMATIC AND ASSEMBLY DIAGRAMS 55 7803 Z 80 PROCESSOR CARD This card combines a buffered and fully expandable 2 80 microprocessor with onboard RAM and PROM sockets The 7803 includes 1K byte of RAM with sockets for up to 4K bytes and sockets for up to 8K bytes of ROM or EPROM An STD BUS system using the 7803 card can be expanded to the full Z 80 memory and 1 capability The 7803 STD BUS interface may be disabled for applications FEATURES e Z 80 Processor e 4096 bytes RAM capacity 2114 e 1024 bytes RAM included e 8192 bytes ROM capacity onboard 2716 EPROM 3 State Address Data Control Bus Crystai controlled 400 ns ciock Power on reset or pushbutton reset input Dynamic RAM refresh control All IC s socketed e Single 5V operation e Use Pro Log D1004 1Kx8 memories two 2114L s DATA BUS NMIRO Q INTRO PROCESSOR 7 SHADING INOICATES SOCKETS ONLY FIGURE DATA BUS 00 07 ADORESS BUS 0 15 INDICATES ACTIVE LOW LOGIC 7803 BLOCK DIAGRAM SECTION TWO T
53. the segment is entered only the bit 7 line is of interest ae a 1 2 3 4 5 SET LOOP COUNT lt 5 WAVEFORM GENERATED PULSE OUTPUT LINE ONCE FIGURE 2 5 INSTRUCTION SEGMENT TIMING EXAMPLE 37 In the example in Figure six of the program segment s nine instructions are within the loop We are executed five times each Three of the instructions 1081 OPA are outside the loop and executed only once FLOW DIAGRAM TIMES TIME EXECUTION TIME IN FUNCTION PERFORMED INSTRUCTIONS crates 400 NS 7803 SYSTEM Set 2 8 us count 5 Pulse output line once Lo OP Test for end Leave output line low FIGURE Zo SAMPLE TIMING CALCULATION The total execution time for the instructions performed once outside the loop is 2 8 1 6 4 4 8 8 us One pass through the loop requires 1 6 4 4 2 8 4 4 1 6 4 0 18 8 us The loop is repeated five times so the total execution time for the program segment is 8 8 5 18 8 102 8 us The period of the pulses is found by adding the time the pulse 15 to the time the pulse is high The pulse is low from the end of the first OPA instruction to the end of the second 2 8 4 4 7 2 us The pulse is high from the end of the second OPA instruction until the end of the first around the loop or until the end of the third OPA the fifth time through the loop 1 6 4 0
54. tomatic increment decrement of the SP offer fast memory data manipulation The current memory address in the SP can be brought into the HL Register Pair for arithmetic manipulation then restored to the SP by the program General Purpose Registers Two identical banks of General Purpose Registers are provided in the 290 Each consists of six B bit registers B C D E H L which can also be treated as three l6 bit Register Pairs BC DE HL The banks can be switched by a single instruction providing fast interrupt response by saving the time required to store the register content in memory Or they can be used as general fast access data storage in non interrupt applications 19 The instruction set allows individual 8 bit registers to be loaded from other register loaded and stored in memory indirectly or loaded immediately from the second byte of the instruction All registers can be incremented and decremented added to or subtracted from the Accumulator perform logic with the Accumulator shifted or rotated arithmetically or logically Each bit in each register can be addressed separately for testing setting and clearing Register C can be used for indirect 1 0 port addressing The three l6 bit register pairs can be loaded immediately from the second and third bytes of the instruction incremented and decremented stored directly in memory added or subtracted to the HL pair and the Index Registers and used as indire
55. ullup resistor Output lines can drive a minimum of 50 LSTTL loads Pins which are unspecified in Figure 5 are electrically open Exceptions to the general loading rules are a PSRESET input which is 15 LSTTL loads b CLOCK output which can drive 10 LSTTL loads c PCI and PCO which are connected together but to nothing else on the 7803 SSE aes 58 E EI EIE s5 24 0 15 50 5 5 FIGURE 5 7803 STD BUS EDGE CONNECTOR PINOUT AND LOADING STD 7203 EDGE CONNECTOR PIN LIST PIN NUMBER PIN NUMBER OUTPUT LSTTL DRIVE OUTPUT LSTTL DRIVE INPUT LOADS INPUT BEEN LOADS 5 S O 04 14013 5 00 PAIS 161 15 5 PAZ 0 25 8 PAIS 50 201 19 so EE 8 2315 p 5 9 mema s 5 as 5 io 7 Memex TW wr se ss ow Is so as a7 5 5 REFRESH sTaruso 5 srArus 1 5 6 55 151 vae s CAuxGND 51 5 Axan
56. ycle is repeated to read the rest of the opcode STATUS 15 is asserted a second time Each cycle requires a minimum of four time states through Th in Figure 25 but this may be stretched to up to 11 time states in some instructions allowing time for the instruction to fully execute if no additional machine cycles are needed The shortest instructions use one machine cycle with four time states the longest require six machine cycles two opcode fetches plus M2 through M5 for additional memory accesses with a total of 23 time states When the 280 interprets the first opcode byte during MI it will add additional machine cycles to the instruction if it finds that a The instruction has a 2 byte opcode and or b The instruction has or 2 additional bytes of data memory address port address or relative offset appended to the opcode and or c The instruction requires the processor to access memory or an 1 0 port as part of the function performed by the instruction For example the STAD instruction in Figure 23 is a 3 byte instruction l byte opcode plus l6 bit memory address in the two bytes appended to the opcode and STAD is an instruction whose function is to store data in memory Therefore STAD requires 4 machine cycles with used to read the opcode M2 and M3 used to read the specified memory address and used to perform the operation of storing data in memory WAIT States Although the minimum number
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