CAD Tool and Compiler Repository for Reconfigurable Computing
Contents
1. 1 Download the ABC tar file from the download link given in Table 1 This flow uses version abc70930 which was the most recently updated version available to this publication as we shall see later this flow suffers from one crucial problem that may be resolved in later editions Untar the file gt tar xvf abc70930 tar After these files are untarred you should have a folder abc 70930 with a readme file that guides you in converting the code into a Linux format this procedure is unnecessary if you are using a Windows OS These conversion instructions are rewritten below cd abc70930 dos2unix Makefile Makefil dos2unix depends sh depends sh chmod 755 depends sh VM MM Now on both operating systems you can generate the abc executable gt make The following command may be more appropriate on Solaris machines gt gmake The readme file also suggests a number of solutions to resolving any errors that you encounter although the errors are not listed the solutions were copied into Table 2 Suggested Solution Run all code through dos2unix Try the following sequence of actions a In the Makefile remove flags from the libs line LIBS b Remove src base main libSupport c from src base main module make c Comment calls to Libs_Init and Libs End in src base main mainInit c Link with gcc rather than g In the Makefile replace LD g with LD gcc 1m Install the readline library f2. lag gdb spin point no lag lib rcg mhaines ODIN verilog 20040606 gt odin tech lib xml lag dynamic debug file rcg mhaines ODIN verilog 20040606 gt odin dynamic debug file xml lag optimization file rcg mhaines ODIN verilog 20040606 tgt odin optimization file xml out odin out blif Fh ct Fh ct Fh Fh Fh Th Ih Note the variables flag lib flag dynamic debug file and flag optimization file must point to the paths where tech lib xmi dynamic debug file xml and optimization_file xml are located if they do not already The variable out odin out b1lif can be changed to give your output file a different name The flag vpr indicates that ODIN will generate a BLIF netlist 4 Once config file txt has been configured as shown in step 3 above we can run the synthesis tool to generate the BLIF netlist Execute the following command gt ivl C lt name of configuration file gt temp v Example gt ivl C config file txt temp v If everything goes well you should have the desired BLIF file in your directory by now In this case it produces an output file called odin out blif Next we pack the BLIF output from ODIN to net format using T VPACK as shown gt t vpack exe lt input blif gt lt output net gt lut size lt K gt no clustering Example gt t vpack exe odin out blif tv out net lut size 4 no clustering If everything works out well you will have tv out
3. T VPACK User s Manual http www eecg toronto edu vpr 2008 P Jamieson and J Rose A Verilog RTL Synthesis Tool for FPGAs International Conference on Field Programmable Logic and Applications 2005 Quartus II University Interface Program Tutorial Altera Corporation 2005 Known limitations 1 This flow cannot handle memory blocks 2 These benchmark circuits suffer from certain problems Circuit Problem Solution sv chip0 Line is too long for Break input buffer input buffer into several lines sv chipl Names are too long Make shorter names
4. the optimized BLIF format netlist into logic blocks Next we use VPR to place and route these logic blocks onto an FPGA whose architecture is specified by an architecture file the output is the placement of the logic blocks and the routing of the circuit on the FPGA This flow is summarized in Figure 2 Verilog File Architecture File Placed and Routed Circuit Figure 2 ODIN gt ABC to optimize gt VPR Flow summary Flow Procedure The flow requires access to the executable binaries for ivl ivipp abc t vpack and vpr The following is a sample PATH variable setting that exports these to the PATH environment variable it can be written in a bashrc file Path for t vpack executable binary PATH S PATH rcg mhaines vpr_5_beta TOOLS T VPACK_HET Path for vpr executable binary PATH S PATH rcg mhaines vpr_5_beta TOOLS VPR_HET Path for ivlpp executable binary PATH S PATH rcg mhaines ODIN verilog 20040606 ivlpp Path for executable binary PATH S PATH rcg mhaines ODIN verilog 20040606 Path for abc executable binary PATH S PATH rcg mhaines abc70930 We illustrate the flow using the benchmark diffeq_paj_convert which you can download from the CAD Tool and Compiler Repository provided by the University of Massachusetts Amherst and the University of Wisconsin Madison 1 Copy the Verilog file into the directory where you wi
5. 60 folder and untar the quip_designs file gt cd quip_v60 benchmarks gt gunzip quip_designs tar gz gt tar xvf quip_designs tar 3 DESIGN FLOWS This paper describes the following design flows gt ODIN gt T VPACK gt VPR 5 0 gt ODIN gt ABC gt T VPACK gt VPR 5 0 gt ODIN gt ABC gt VPR 5 0 gt ODIN gt ABC gt QUIP Note 1 The BLIF gate level netlist format has the following limitations Black boxes such as DSP blocks and RAM are not supported Asynchronous signals are not supported Unconnected inputs of LUTs are replaced with null gt Arithmetic carry chains are not supported unless they are converted into gates 3 1 DESIGN FLOW 1 ODIN 5 T VPACK 5 VPR 5 0 We begin this design flow by using ODIN to synthesize a Verilog file into a netlist of look up tables and flip flops in BLIF format This netlist is unpacked so T VPACK is used to pack the netlist into logic elements 3 After packing the netlist the circuit is placed onto a specified FPGA architecture using the VPR 5 0 tool suite Finally the circuit is optimally routed on the FPGA using VPR VPR can perform many types such as detailed and global or combined global routing 3 This entire flow is summarized in Figure 1 Verilog File NY Architecture File Placed and Routed Circuit Figure 1 ODIN gt T VPACK gt VPR Flow summary Flow Procedure The flow requires access to the ivl ivlpp t vpack and vpr executable b
6. CRI CRD Collaborative Research CAD Tool and Compiler Repository for Reconfigurable Computing CAD Flows IV Version 0 3 10 30 2008 Document Revision History Date Changed By Version Comments 06 18 2008 Michael Haines 0 1 Initial Draft 07 07 2008 Michael Haines 0 2 Benchmarks Updated 10 30 2008 Deepak 0 3 References updated Unnikrishnan CONTENTS AINT RO U O TON seca ta Pe ice RI lated soa A adiada cla poa Pad A a asthe tenet snes dd 4 2 FPGA CAD LOOIS e e A Eua Dna LE ida cds an paro das iS 4 2 1 ODIN RTL Compiler Icarus Tool Suite eeeeeseeeseeeeeeeeeneeeaeeeneeens 4 D2 ABC Synthesis Tool santeta NS RD dt Rie a E oa isd 7 23 VPR Tool SUE ae te tere urns EE aa aaa eea ae a aT a ad o da 8 OAD G0 AI EE E EE TAA A EAS AE 9 J DESIGN ESO Wess e o AEA TU eee lag 9 3 1 Design Flow 1 ODIN gt T VPACK gt VPR 5 0 10 3 2 Design Flow 2 ODIN gt ABC to optimize gt VPR 5 0 13 3 3 Design Flow 3 ODIN gt ABC to optimize and map gt VPR 5 0 17 3 4 Design Flow 4 ODIN gt ABC QUIP ccccccceesecsseeseceseeseeeeesseeseeneeeeees 21 A RESULTS semean an ra a aa a di dn Ca E ara N ESATE 24 1 INTRODUCTION The FPGA CAD design flows presented in this paper are part of the compiler repository and collaborative research on CAD tools for reconfigurable computing The goal of this research is to develop an infrastructure that will provide a number of end
7. FH h Eh Fh Fh Note the variables flag lib flag dynamic debug file and flag optimization file must point to the path where your tech_lib xml dynamic debug file xml and optimization file xml1 are located The variable out odin_out blif indicates the name of your output file which you can change The flag vpr indicates that ODIN will be configured to generate a BLIF netlist Once config file txt has been configured as shown in step 3 above run the synthesis tool to generate the BLIF netlist as shown gt ivl C lt name of configuration file gt temp v Example gt ivl C config file txt temp v If everything goes well you should have the desired BLIF file in your directory by now here it is named odin out blif To optimize the BLIF netlist you may need to use a script defined in the abc rc resource in the abc 70930 directory Copy abc rc into the active directory gt cp abc70390 abe re abc rc 10 11 12 18 Because we are using ABC to map the BLIF netlist you may prefer to write a new file called abc Mapper txt in the same directory before running ABC Copy the following line about 30 40 times into the file choice fpga If you want to print statistics on any line in the file add ps to that line Start ABC by running the abc executable gt abc From the prompt first read the un optimized BLIF file gt UC Berkeley ABC 1 01 compiled Ju
8. Flow Block Path Width eee Routing Path Array Delay Area Delay diffeg pai 1 90 x 90 112 992 ns 12 243 10 3 41103 10 119 643 ns convert 2 133 x 133 304 039 ns 12 530 67 10 7 34920 10 314 377 ns 3 83 x 83 78 1775 ns 20 206 67 10 3 76124 10 86 5717 ns Pea 1 48x48 19 6508 ns l Bates 2 53x53 53 7059ns 10 84 2740 630 931 60 8692 ns e 33x33 15 4285ns 12 326710 476 537 17 1117 ns 206x206 63 6324 ns j 261x261 181 11 ns 14 2043 6340 28721440 206 573 ns i 162 x 162 45 2814 ns 20 _787 32 10 __14 2713 10 __51 2737 ns Table 3 Results of proposed design flows 1 2 and 3 on three benchmark circuits cf fir_ 24_16_16 N Note 1 All three benchmarks are available in the CAD Tool and Compiler Repository provided by the University of Massachusetts Amherst and the University of Wisconsin Madison Note 2 Two of the benchmarks were unable to be compiled through the VPR 5 0 router when they were unoptimized the reason for this is currently unknown but it is believed to be because of a limitation of VPR 5 0 REFERENCES 1 2 3 4 5 UMass Amherst Reconfigurable Computing Group CRI CRD Collaborative Research CAD Tool and Compiler Repository for Reconfigurable Computing CAD Flows 2008 Berkeley Logic Synthesis and Verification Group ABC A System for Sequential Synthesis and Verification Release 70930 http www eecs berkeley edu alanmi abc V Betz J Rose VPR and
9. GN FLOW 3 ODIN gt ABC to optimize and map gt VPR 5 0 This flow is very similar to the one described above First ODIN is used to synthesize a Verilog design into a netlist in BLIF We then use ABC to optimize the circuit and to map the circuit which it was also designed to do The differences between the results of this flow and the previous flow will determine whether ABC should be used to this extent Next T VPACK packs the mapped netlist file into logic units made of look up tables and flip flops so that VPR can place the circuit on an FPGA according to the netlist file and to a specified architecture The flow finishes when VPR routes the circuit on the FPGA Some of the typical routings offered by the VPR tool are global or combined global and detailed routing of the circuit 3 This flow is summarized in Figure 3 Verilog File NY Optimized and Mapped BLIF netlist NY Architecture File Placed and Routed Circuit Figure 3 ODIN gt ABC to optimize and map gt VPR Flow Summary Flow Procedure This flow requires access to the executable binaries for ivl ivlpp abc t vpack and vpr Export these in the PATH environment variable The following is a example file of a PATH variable setting that can be written in a bashrc file Path for t vpack executable binary PATH S PATH rcg mhaines vpr 5 beta TOOLS T VPACK HET Path for vpr executable binary PATH S PATH rcg mha
10. ad blif lt name of blif file gt Optimize the BLIF file with one of the scripts defined in abc rc as shown abc 02 gt resyn2rs Next source abc Mapper txt to map the circuit abc 20 gt source abc Mapper txt Write out the optimized netlist and quit ABC abc 740 gt write_blif lt name_of_output_blif_file gt abc 740 gt quit Next we need to add two parameters to the latches so that we can use T VPACK to pack the optimized BLIF output into net format Open the output BLIF file which is 18 14 15 abc out blif in this case and change every latch in the output BLIF file to include the reset signal and clock signal abc 20 gt quit gt vim abc out blif Example Change Before latch n3365 hetero REGISTER 2158 7227 out 2 After latch n3365 hetero REGISTER 2158 7227 out re barrel32 clk 0 2 Save the BLIF file Now pack the optimized and mapped BLIF file to net format using T VPACK gt t vpack exe lt input blif gt lt output net gt lut size lt K gt no clustering Example gt t vpack exe abc out blif tv out net lut size 4 no clustering If everything works out well you will have the file tv out net available now it can be fed into the VPR placement and routing tools Next we use VPR to place the circuit VPR needs the net file as well as an architecture file to describe the circuit Several architecture files are available in the CAD Tool and Compiler Repository from
11. d link given in Table 1 Untar the installation files gt tar xvf odin tar To install ODIN you will also need to download and install the following tools gt binutils BFD version 2 13 2 http ftp gnu org gnu binutils gt GCC 3 2 gcc version 3 2 http mirrors usc edu pub qnu gcc gcc 3 2 gt gdb GNU gdb 5 3 http www filewatcher com m gdb 5 3 tar bz2 11198721 0 0 html gt gperf gperf 2 7 2 http ftp gnu org gnu gperf gt libxml libxml2 2 6 2 http www gtlib gatech edu pub gnome sources libxml2 2 6 To install these tools begin by exporting the paths containing the configure executables of gperf and libxml2 to your PATH variable Example PATH S PATH rcg mhaines gperf 2 7 2 src PATH S PATH rcg mhaines libxml2 2 6 2 Copy the ivl executable located in verilog 20040606 BIN lib ivl to the verilog 20040606 directory Example cp rcg mhaines ODIN verilog 20040606 BIN lib ivl ivl rcg mhaines ODIN verilog 20040606 ivl Now export the ivl and ivlpp executables to your PATH variable Example PATH S PATH rcg mhaines ODIN verilog 20040606 ivlpp PATH S PATH rcg mhaines ODIN verilog 20040606 You should now be able to access the configure executables for gperf and libxml2 as well as the ivl and ivlpp executables from anywhere in your environment Navigate to tgt odin directory within the ODIN source directory i e ODIN verilog 20040606 gt cd rcg mhaines ODIN ver
12. ilog 20040606 tgt odin Edit the makefile gt vim Makefile Change the directories for I L and prefix to the directories where you are installing ODIN and to where the appropriate libraries are located In particular edit the following lines Line 26 Change prefix to the location where you wish to install ODIN Example prefix rcg mhaines ODIN verilog 20040606 tgt odin PETER_BIN Line 35 Change the include directories to point to the appropriate libxml and ODIN include paths Example INCLUDE DIR I rcg mhaines ODIN verilog 20040606 tgt odin PETER LIB include I ODIN verilog 20040606 tgt odin I rcg mhaines libxml2 2 6 2 include libxml Line 59 Change the LIBS path to point to your appropriate libxml library directories Example LIBS LPETER_LIB lpeters L rcg mhaines libxml2 2 6 2 lxml2 1z lpthread 1m Line 156 Uncomment the line CC ggdb shared o S S OBJS S TGTLDFLAGS LIBS INCLUDE_DIR 10 11 12 18 14 Save the makefile Make the installation gt make This should compile the ODIN sources located in the tgt odin SRC directory You should now have a file named odin tgt in your tgt odin directory To test whether ODIN has been setup correctly navigate to the SAMPLE FILES directory located inside the tgt odin directory and edit the makefile Example cd SAMPLE FILES gt vim config fi
13. inaries Export paths for these in the PATH environment variable The following is a sample PATH variable setting which may be written in a bashrc file and can be sourced whenever necessary Path for t vpack executable binary PATH S PATH rcg mhaines vpr_5_beta TOOLS T VPACK_HET Path for vpr executable binary p P TH S PATH rcg mhaines vpr 5 beta TOOLS VPR HET ath for ivlpp executable binary ATH PATH rcg mhaines ODIN verilog 20040606 ivlpp U D Path for ivl executable binary PATH S PATH rcg mhaines ODIN verilog 20040606 We illustrate the flow using the benchmark diffeqg paj convert available from the CAD Tool and Compiler Repository provided by the University of Massachusetts Amherst and the University of Wisconsin Madison 1 Copy the Verilog file into the directory where you wish to create the flow gt cp diffeqg paj convert v flow_results 2 Run the preprocessor tool on the design gt ivlpp v o temp v lt name_of_verilog_file gt Example gt ivlpp v o temp v diffeq_paj_convert v This creates a file called temp v 3 To configure ODIN to output a BLIF netlist we need to change several parameters in config_file txt which you can find in the SAMPLE_FILES folder of the tgt odin directory Open config file txt and edit it as follows functor synth functor syn rules functor cprop functor nodangle t dll lag DLL odin tgt lag vpr lag arch vpr
14. ines vpr 5 beta TOOLS VPR HET Path for ivlpp executable binary PATH S PATH rcg mhaines ODIN verilog 20040606 ivlpp Path for executable binary PATH S PATH rcg mhaines ODIN verilog 20040606 Path for abc executable binary PATH S PATH rcg mhaines abc70930 We illustrate the flow using the benchmark diffeq_paj_convert which you can find in the CAD Tool and Compiler Repository provided by the University of Massachusetts Amherst and the University of Wisconsin Madison 1 Copy the Verilog file into the directory where you wish to create the flow gt cp diffeqg paj convert v flow_results 2 Run the preprocessor tool on the design gt ivlpp v o temp v lt name_of_verilog_file gt Example gt ivlpp v o temp v diffeq_paj_convert v This creates a file called temp v in the active directory 3 To configure ODIN to output a BLIF netlist we need to configure several options in the configuration file config file txt Open config file txt and edit it as follows functor synth functor syn rules functor cprop functor nodangle t dll lag DLL odin tgt lag vpr lag arch vpr lag gdb_spin_point no lag lib rcg mhaines ODIN verilog 20040606 tgt odin tech lib xml lag dynamic debug file rcg mhaines ODIN verilog 20040606 gt odin dynamic debug file xml lag optimization file rcg mhaines ODIN verilog 20040606 tgt odin optimization_file xml out odin_out blif Fh c
15. ld All from the Build menu Finally run your demo program It will require a single parameter which can be either a BLIF file or a PLA file you can find several BLIF files and a sample PLA file in the examples folder gt demo examples apex4 pla You should now have a result b1if file in the abc 70930 directory 2 3 VPR Tool Suite Download the tar file for the VPR tool suite from the download link available in Table 1 Untar the file gt tar xvf vpr 5 beta tgz 2 Navigate to the VPR_HET directory and make the vpr executable gt cd vpr_5_beta TOOLS VPR_HET gt make 3 Similarly make the T VPACK executable gt cd T VPACK HET gt make If you encounter difficulty with making these executables you should be able to find sufficient help in the VPR documentation 2 4 QUIP QUIP is an acronym for Quartus University Interface Program QUIP provides sample code data files and documentation to access the Quartus Il CAD toolset at different stages of a typical CAD flow QUIP works under a Windows platform Download the executable from the QUIP download link given in table 1 quip download v60 tar After downloading untar the file There is enough documentation available inside the package to guide your installation of QUIP 5 1 The flows presented in this paper use QUIP benchmarks To access them first untar the file if you have not already Next navigate to the benchmarks directory of the quip_v
16. le txt Change the following variables Change the flag 1ib variable to point to the location of tech 1ib xm1 You should be able to find this file in the tgt odin directory Example flag lib rcg mhaines ODIN verilog 20040606 tgt odin tech lib xml Change the flag dynamic debug file variable to point to the location of dynamic debug file xm1 which should also be in the tgt odin directory Example flag dynamic debug file rcg mhaines ODIN verilog 20040606 tgt odin dynamic debug file xml Change the flag optimization file variable to point to the location of optimization file xml This should also be in the tgt odin directory Example flag optimization file rcg mhaines ODIN verilog 20040606 tgt odin optimization file xml Save config file txt Run the ivlpp executable on a Verilog file of your choice The MICROBENCHMARKS folder contains a number of Verilog files from which to choose ivlpp v o temp v lt name_of_your_verilog_file gt Example ivlpp v o temp v MICROBENCHMARKS bm_dagl_log v This generates a file named temp v 15 Next run the ivl executable on temp v according to the specifications in config file txt gt ivl C config file txt temp v This shall create the structural gate level netlist file called temp synthesized v Later we will change many more parameters in config file txt so that ODIN generates netlists in BLIF format 2 2 ABC Synthesis Tool
17. les Export paths to each of these in the PATH environment variable the following code shows how this can be set in a bashrc file Path for ivlpp executable binary PATH S PATH rcg mhaines ODIN verilog 20040606 ivlpp Path for executable binary PATH S PATH rcg mhaines ODIN verilog 20040606 Path for ABC executable binary PATH S PATH rcg mhaines abc70930 We illustrate the flow using the benchmark diffeq_paj_convert which the CAD Tool and Compiler Repository provides 1 Copy the Verilog file into the directory where you wish to create the flow gt cp diffeqg paj convert v flow_results Run the preprocessor tool on the design gt ivlpp v o temp v lt name of verilog file gt Example gt ivlpp v o temp v diffeq paj convert v This creates a file called temp v in the active directory To configure ODIN to output a BLIF netlist we need to change configure several options in the configuration file config file txt Open config file txt and edit it as shown functor synth functor syn rules functor cprop functor nodangle t dll lag DLL odin tgt lag vpr lag arch vpr lag gdb spin point no lag lib rcg mhaines ODIN verilog 20040606 gt odin tech lib xml lag dynamic debug file rcg mhaines ODIN verilog 20040606 gt odin dynamic debug file xml lag optimization file rcg mhaines ODIN verilog 20040606 tgt odin optimization file xml out odin out blif th cE
18. mmand gt ivl C lt name of configuration file gt temp v Example gt ivl C config file txt temp v If everything goes well you should have the desired BLIF file in your directory by now The name of this BLIF file is specified by config file txt here it is odin out blif To optimize the BLIF netlist we use ABC You will need to use the abc rc resource in the abc 70930 directory so copy abc rc into the active directory gt cp abc70930 abc rc abc rc Now run the abc executable gt abc From the ABC prompt read the un optimized BLIF file UC Berkeley ABC 1 01 compiled Jun 6 2008 12 38 36 abc 01 gt read blif lt name of blif file gt Optimize the BLIF netlist with a script defined in abc rc as shown abc 02 gt resyn2rs Write out the optimized netlist abc 20 gt write blif lt name of blif file gt Example abc 20 gt write blif abc out blif Next we need to add two parameters to the latches so that we can use T VPACK to pack the optimized BLIF output into net format After you quit out of ABC change every latch in the output BLIF file to include the reset signal re and clock signal abc 20 gt quit gt vim abc out blif Example change Before latch n3365 hetero REGISTER 2158 7227 out 2 After latch n3365 hetero_REGISTER_2158_7227_out re barrel32 clk 0 2 Save the BLIF file Now run T VPACK to pack the BLIF file 12 18 gt t vpack exe lt inpu
19. n 6 2008 12 38 36 abc 01 gt read_blif lt name_of_blif_file gt Use one of the scripts defined in abc rc to optimize the BLIF netlist abc 02 gt resyn2rs Next source abc Mapper txt to map the circuit abc 20 gt source abc Mapper txt ABC can be used to convert the result into a Verilog file You do not need to write the optimized BLIF file to do this instead type the following command abc 740 gt write verilog lt verilog output file gt The following example writes the Verilog file in the abc70930 folder Notice that the output file has the same name as the benchmark QUIP requires that the file and the top module have the same name and ABC will maintain the original name of the top module abc 740 gt write verilog abc70930 diffeq paj convert v Quit out of ABC and create a new directory in Windows Copy the Verilog file which is diffeq paj convert v in this case to the new directory Create a new Quartus Project Add the Verilog file to the project and run the compilation If you encounter any difficulty you should be able to find sufficient help in the Quartus II Tutorial 5 4 RESULTS Table 3 gives the placement and routing results obtained after compiling three benchmark circuits with the first three CAD flows presented in this paper Note that Flow 1 corresponds to the first flow presented Flow 2 to the second and Flow 3 to the third Benchmark Placement Routing Logical Critical F Total Critical Circuit
20. net available for the VPR tool suite Next we use VPR to place the circuit VPR needs the net file as well as an architecture file to describe the FPGA Several architecture files are available in the CAD Tool and Compiler Repository from which this documentation was probably downloaded You may use any of them as input architecture file to the VPR placement tool because we selected the no clustering option k4 n1 xml works best A sample command to place a circuit is shown gt vpr tv out net vpr 5 beta VPR ARCH FILES HET ARCH FILES W MULT k4 nl xml vpr p vpr r nodisp full stats inner num 1 place only You can find more details on using the vpr executable in the VPR manual 3 If the circuit is placed successfully you will have a p file in your directory Finally we route the circuit A sample command to route the circuit is as shown gt vpr tv out net vpr 5 beta VPR ARCH FILES HET ARCH FILES W MULT k4 nl xml vpr p vpr r nodisp full stats fast max router iterations 10 router algorithm breadth first route type detailed route only The VPR manual 3 can provide details on how to use VPR for routing 3 2 DESIGN FLOW 2 ODIN 5 ABC to optimize gt VPR 5 0 We also begin this design flow by using ODIN to synthesize a Verilog design file into a BLIF format netlist Before passing the BLIF file to T VPACK however we use ABC to optimize it T VPACK then packs
21. rom http tiswww case edu php chet readline ritop htm if your Linux distribution does not already have it Table 2 Possible Solutions to Problems in Compiling ABC You should now have an abc executable in the abc 70930 directory If you wish to convert ABC into a static library before using it in this flow open the file src base main main c and uncomment the line define _LIB This is not recommended typically it results in the error undefined reference to main gt vim src base main main c Next if you are using a Unix based OS run the following commands to make the libabc a file gt chmod 755 depends sh gt make libabc a If you are using a Windows OS double click on abclib dsw to open Visual Studio and then select Rebuild All from the Build menu To test whether ABC is installed properly you can build a small demo program described on the ABC website 2 Begin by copying the libabc a file into the abc 70930 directory if it is not already there Next if you are using a Unix based OS run the following two commands to build the demo program Note you should have demo c from having untarred the abc tar file you do not need to download it separately gt gcc Wall g c demo c o demo o gt gcc g o demo demo o lm ldl rdynamic lreadline ltermcap libabc a If you are using a Windows OS double click on abctestlib dsw to open Visual Studio From there select Rebui
22. sh to create the flow gt cp diffeqg paj convert v flow_results 2 Run the preprocessor tool on the design gt ivlpp v o temp v lt name of verilog file gt Example gt ivlpp v o temp v diffeq_paj_convert v This creates a file called temp v in the active directory 3 To configure ODIN to output a BLIF netlist we need to configure several options in the configuration file config file txt Open config file txt and edit is as follows functor synth functor syn rules functor cprop functor nodangle t dll lag DLL odin tgt lag vpr lag arch vpr lag gdb spin point no lag lib rcg mhaines ODIN verilog 20040606 tgt odin tech lib xml lag dynamic debug file rcg mhaines ODIN verilog 20040606 gt odin dynamic debug file xml lag optimization file rcg mhaines ODIN verilog 20040606 tgt odin optimization_file xml out odin_out blif Fh ct Fh FH FH Fh Th Ih Note the variables flag lib flag dynamic debug file and flag optimization file must point to the path where tech lib xmi dynamic debug file xml and optimization file xml files located The 10 11 variable out odin out blif indicates the name of the output file which you can change The flag vpr indicates that ODIN will be configured to generate a BLIF netlist Once config file txt has been configured as shown in step 3 above we can run the synthesis tool to generate the BLIF netlist Execute the following co
23. t blif gt lt output net gt lut size lt K gt no clustering Example gt t vpack exe abc out blif tv out net lut size 4 no clustering If everything works out well you will now have a file named tv out net Next we use VPR to place the circuit VPR needs the net file previously generated as well as an architecture file to describe the circuit Several architecture files are available in the CAD Tool and Compiler Repository from which this documentation was probably downloaded You may use any of them as input architecture file to the VPR placement tool because we selected the no clustering option k4 n1 xml works best A sample command to place a circuit is shown gt vpr tv out net vpr 5 beta VPR ARCH FILES HET ARCH FILES W MULT k4 nl xml vpr p vpr r nodisp full stats inner num 1 place only More details on using VPR can be found in the VPR manual 3 If the circuit is placed successfully you will have a p file in your directory Finally the circuit needs to be routed for which we use VPR again A sample command to route the circuit is as shown gt vpr tv out net vpr 5 beta VPR ARCH FILES HET ARCH FILES W MULT k4 nl xml vpr p vpr r nodisp full stats fast max router iterations 10 router algorithm breadth first route type detailed route only You can find more details and options on how to use VPR for routing in the VPR manual 3 3 3 DESI
24. t Fh FH FH Fh Fh Ih Note the variables flag lib flag dynamic debug file and flag optimization file must point to the path where tech lib xmi 10 11 12 dynamic debug file xml and optimization file xml are located The variable out odin_out blif indicates the name of the output file which your can change The flag vpr variable indicates that ODIN will be configured to generate a BLIF netlist Once config file txt has been configured as shown in the step above we can run the synthesis tool to generate the BLIF netlist as shown gt ivl C lt name of configuration file gt temp v Example gt ivl C config file txt temp v If everything goes well you should have the desired BLIF file in your directory by now here it would be odin out blif To optimize the BLIF netlist we use ABC You may find that you need to use the abc rc resource for this so copy abc rc into the active directory gt cp abc70930 abc rc abc rc ABC can also be used to map the BLIF netlist so before running ABC make a new file called abc Mapper txt in the same directory Copy the following line about 30 40 times into the file choice fpga If you want to print statistics on any line in the file add ps to that line Start ABC by running the abc executable gt abc From the prompt read the un optimized BLIF file UC Berkeley ABC 1 01 compiled Jun 6 2008 12 38 36 abc 01 gt re
25. to end design flows consisting of academic compilers CAD tools and interfaces The objective of the four flows presented in this paper is to improve the performance of the flows presented in 1 primarily to replace the antiquated synthesis tool SIS with a newly developed synthesis tool ABC 2 and to update the back end tool VPR 3 The new flows should be able to handle multipliers integrated onto the hardware and used by the circuits The ODIN RTL Compiler 4 is still used for RTL synthesis and the backend tools VPR and Quartus II 5 finalize the integration Documentation on the sources of these tools on the installation procedures and on their performance is provided 2 FPGA CAD Tools These academic compilers and CAD tools develop the design flows gt RTL Synthesis ODIN RTL Compiler Icarus Tool Suite gt ULogic Synthesis Technology Mapping and BLIF to Verilog Conversion ABC gt Placement and Routing VPR QUIP Tool Download Link ODIN http www eeca toronto edu jayar software odin download html ABC http www eecs berkeley edu alanmi abc abc htm VPR 5 0 http www eecg toronto edu vpr terms html QUIP http www altera com education univ research unv quip htm l Table 1 Links to software that develop the flows described later Here is a brief installation procedure for the tools 2 1 ODIN RTL Compiler Icarus Tool Suite 1 2 Download the ODIN software from the downloa
26. which this documentation was probably downloaded You may use any of them as input architecture file to the VPR placement tool because we selected the no clustering option k4 n1 xml works best A sample command to place a circuit is shown gt vpr tv out net vpr 5 beta VPR ARCH FILES HET ARCH FILES W MULT k4 nl xml vpr p vpr r nodisp full stats inner num 1 place only You can find more details on using VPR in the VPR manual 3 If the circuit is placed successfully you will have a p file in your directory Finally route the circuit A sample command to route the circuit is as shown gt vpr tv out net vpr 5 beta VPR ARCH FILES HET ARCH FILES W MULT k4 nl xml vpr p vpr r nodisp full stats fast max router iterations 10 router algorithm breadth first route type detailed route only More details and options on how to use VPR for routing can be found in the VPR manual 3 3 4 DESIGN FLOW 4 ODIN 5 ABC 5 QUIP This flow also begins by synthesizing the Verilog design into a BLIF netlist with the ODIN RTL Compiler Next ABC optimizes and maps the netlist before converting it into a Verilog file Lastly QUIP is used to compile the modified Verilog file This flow is summarized in Figure 4 Verilog File Optimized and Mapped Verilog File Figure 4 ODIN gt ABC gt QUIP Flow Procedure This flow requires access to the ivl ivlpp and abc executab
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