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1. R Beuchat E Users Rene rb laboratories trunk Enonces_Doc MSP430_ LaboDocuments Labo MSP430 2 0 docx Cr le 18 09 14 Impression le 18 09 14 Modifi le 18 09 14 22 09 Version 1 4 Processor Architecture Laboratory EPFL 2 MSP430 1 1 Clock Unified clock System The explanations are done for the MSP430F5437 version Search on the documentation the difference for the MSP430G2553 ACLK_REQEN ACLK_REQ y SELA OSCOFF 3j oo XT1 Fault i ie ie i Detectio AE DIVPA OSC sia Divider act a d 32 768Hz i Divider N POT i i ACLK i i 121418116132 REFocLk 32 768Hz W eee e 32 768Hz MCLK_REQEN MCLK_REQ 000 SELM _ CPUOFF FLLREFCLK 1 off Reset gt 10 bit MCLK Homer rent Frequency Integrator e e E 1 048576 MHz RATES SMCLK_REQEN t 2 8141 32 768 1 SMCLK REQ D N 1 FLLREFCLK REFDIV Iliff SEES SMCLKOFF io SMCLK MODOSC_REQ Unconditonal MODOSC XT2 Oscillator requests MODCLK EN MODOSC Figure 3 Unified Clock System UCS block schematic MSP430F5437 An oscillator of 32 768 Hz is connected on input P7 0 and P7 1 so these pins are not available for other purposes That s the XIN XOUT quartz connection for XT1CLK in the TI documentation A high frequency signal 16 MHz XT2 could be connected to the pins P5 2 and P5 3 but it is not available in the WSN4U board The FLL Frequency Locked Loop is able to c
2. ADC124S051 is a 12 bit Analog to Digital Converter it has 4 input channels and uses SPI bus in order to output the analog value The challenge in this case is to properly set up the SPI communication and to control the A D channels to start the conversion In order to connect the extension A D board to the microcontroller we should use a specific cable shown in the figure 8 below r r r r i 4 lt S te Figure 13 Connection between the external A D board and the microcontroller Required Documentation e ADC124S051 Datasheet http moodle epfl ch mod resource view php inpopup true amp id 43731 1 e A D extension board schematic http moodle epfl ch mod resource view php id 437321 Manipulation 6 ADC Analogue to Digital Converter gt Select one of the 2 methods to acquire an analog signal from an external potentiometer and write the corresponding function to do so 1 7 ADC to control PWM The objective of this section is to use the A D value to control the PWM duty The A D converter should be read every 50ms The conversion period should be done using interruptions Manipulation 7 Timer ADC PWM GPIO and interruption gt Use interruption to enable the ADC converter in order to start a conversion of the potentiometer value internal ADC12 module or external A D with SPI interface gt Use another interruption routine to catch the result and change the PWM value accordingly gt Make ademoto an assi
3. CCIFGD USCI_A Receive Transmit UCAZRXIFG UCAZTXIFG a ah C om DMAOIFG DMATIFG DMAZIFG OMA CI Mashable orreen o PAN TAICCROCCIFGO Mashable OFFE2h 49 PIIFG O to PIIFG 7 PIV Maskable OFFOEn a USCLAI 1 ReceivelTransmi UCAIRXIFG UCAITXIFG UCATIV 3 __Maskable OFFDGh d6 USCI_B1 Receive Transmit UCBIRXIFG UCBITXIFG UCBIIV 3 J menase f orroa E USCI_A3 Receive Transmit UCASRXIFG UCAITXIFG UCASIV IT 2 Maskabie OFFDan a UCESRXIFG UCB3TXIFG UCB3IV P2IFG 0 to P2IFG 7 PRIV RTICRDYVIFS RTCTEVIFG RTCAIFG Fron o Figure 11 General interrupt architecture fromTI 1 Multiple source flags 2 A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space Non maskable the individual interrupt enable bit can disable an interrupt event but the general interrupt enable cannot disable it 3 Interrupt flags are located in the module 4 Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary To maintain compatibility with other devices it is recommended to reserve these locations R Beuchat E Users Rene rb laboratories trunk Enonces_ Doc MSP430_ LaboDocuments Labo MSP430 2 0 docx Processor Architecture Laboratory EPFL 12 MSP430 1 6 ADC The following manipulation intends to read an an
4. E Users Rene rb laboratories trunk Enonces_Doc MSP430_ LaboDocuments Labo MSP430_2_0 docx Processor Architecture Laboratory EPFL 8 MSP430 1 4 2 PWM generation Use the TimerBO to generate periodic pulse with pulse width modulation PWM mode A period of 10 ms is to be generated and the duty cycle should be programmed as a function parameter Study the different modes available on the Timer B to generate a PWM pulse Timer Block l Group 11 TBIFG Load Logic l l TBSSEL ID IDEX Timer Clock Mc 9 9 3 15 0 2 TBxCLK 00 Divider Divider 16 bit Timer Count l a beg ey gt TexR R R EQUO ACLK o4 V28 1 48 Mode a Clear 8 10 12 16 I SMCLK 10 CNTL l gt o 11 gt l I TBCLR I l l 00 l TBCLGRP I 10 Set TBxCTL i sd ee eee ee ee ee F EQUO CCRO CCR1 CCR2 CCR3 CCR4 CCRS5 el l CCR6 cM cov i 2 scs ccieB 01 Mode EY S iia u Timer Clock YCC 11 ip I CLLD l Load Logic l p I vcc l l EQUO gt gt UP DOWN CAP Set TBxCCR6 CCIFG I l l l l l l OUTE Signal l l I 3 3 l l l l OUTMOD ee a h Figure 8 TimerB block schematic from ti not available on G2 Manipulation 4 TimerB0 PWM or TimerA for G2553 gt Use the TimerBO to generate a PWM pulse using the CCR comparator to operate in the proper manner The PWM pulse must have a period of 10 ms Use an oscilloscope to view and vali
5. Processor Architecture Laboratory EPFL 1 MSP430 MSP430 I O WSN4U MSP430 Laboratory Goal Understand the operation of the MSP430 peripherals Resource MSP430F5437 Microcontroller or MSP430G2553 Microcontroller Prerequisites MSP430 Base Course Theory Equipment gt WSN4U board Extension board gt MSP430FETUSN IF USB JTAG interface gt or the MSP430G2 LaunchPad board gt Code Composer Studio cross development tools Duration 6h 1 Introduction The objective of this laboratory is to understand how to operate some of the programmable interfaces available on a microcontroller specifically on the MSP430 family part number F5437 or G2553 The microcontroller MSP430F5437 is available on the WSN4U board from epfl lap the MSP430G2553 on the LaunchPAD board from ti The final demonstration of this laboratory divided in 3 sessions is to be able to convert an analog signal using an Analog to Digital A D converter using the internal A D fig 1 or an external A D connected to the microcontroller using the SPI bus fig 2 The microcontroller outputs a signal using Pulse Width Modulation PWM with signal width proportional to the analog input An oscilloscope and or Logic Analyzer are used to display the PWM output as well as other useful signals uP Program Figure 1 General system block schematic internal ADC uP ATD PWM Program Figure 2 General system block schematic external ADC on SPI
6. RSELx i SELS om SCG LL Puls ii ie mider oneal by UZIA Faic SMCLK Sub System Clock Figure 5 1 Basic Clock Module Block Diagram MSP430F2xx NOTE t Device Specific Clock Variations Not all clock features are available on all MSP430x2 x devices MSP430G22x0 LFXT1 is not present XT2 is not present ROSC is not supported MSP430F20xx MSP430G2xx1 MSP430G2xx2 MSP430G2xx3 LFXT1 does not support HF mode XT is not present ROSC is not supported MSP430x21x1 Internal LP LF oscillator is not present XT2 is not present ROSC is not supported MSP430n2 1x2 XT is not present MSP430F22xx MSP430x23x0 XT2 is not present Figure 4 Unified Clock System UCS block schematic MSP430F2xx MSP430G2xx3 LFXT1 does not support HF mode XT2 is not present ROSC is not supported R Beuchat E Users Rene rb laboratories trunk Enonces_Doc MSP430_ LaboDocuments Labo MSP430 2 0 docx Processor Architecture Laboratory EPFL 4 MSP430 1 2 GPIO The microcontroller MSP430F5437 used in the WSN4U board has 8 I O ports Port1 to Port8 which pins can be used as standard I O function or as peripheral function Depending on the port some specific registers are used to configure the pin function The table below summarizes the shared functions for the MSP430F5437 microcontroller Port 2 O P2 0 to P2 7 O P8010 PB The figure 4 below illustrates how a typical I O port is organized inside the microcontroller and the respecti
7. alog value from a potentiometer using one of the following methods e Using the internal A D programmable interface of the MSP430 microcontroller with a potentiometer connected to an I O port e Using an external extension A D board that communicates through SPI bus 1 6 1 ADC on MSP430 The MSP430F5437 microcontroller has 12 input channels that can be sampled by a 12 bit internal A D converter A15 A12 on Port7 7 Port7 4 and A7 A0O on Port6 and could be used to measure 4 internal voltages In order to program the A D module take a look on the TI documentation in order to perform a single conversion on one channel with an external potentiometer connected to it REFOUT REFBURST REFON V mere ve ADCI2SR i oai C INCHx OAh m A 15V or2 5 Vex Vase Van ON disklini Ref x i AM o gt i ia ay 11 10 01 09 SREM ADC1205C 4 a SREFO see Note A SREF2 u ADCI20N ADC12SSELx ADC 12DIVx ADCI2PDW Divider A ie 42 bit ADC Core Convert ADCIZ5C Timer sources SAMPCON see Note B INCH 0Bh Ref x R CSTARTADDx CONSEQx T i Figure 12 ADC12 module block schematic fromTI Nice to study and use Isn t it R Beuchat E Users Rene rb laboratories trunk Enonces __Doc MSP430_LaboDocuments Labo MSP430_2_0 docx Processor Architecture Laboratory EPFL 13 MSP430 1 6 2 External ADC using SPI Using this option an external board that contains the ADC124S051 A D is used The
8. ate a pulse of minimum width by software using C programming language gt Test the solution using an oscilloscope or a logic analyzer Compare the results obtained using software measurements counting clock cycles in the Debugger and the oscilloscope measurements Required Documentation O a MSP430x5xx family full documentation User s GuideFile http moodle epfl ch pluginfile php 1580215 mod_resource content 1 Doc_composants MSP430x2xx_slau144j pdf O MSP430x2xx family full documentation User s GuideFile http moodle epfl ch pluginfile php 1580215 mod_resource content 1 Doc_composants MSP430x2xx_slau144j pdf O 1 MSP430F543x Datasheet from tiFile http moodle epfl ch pluginfile php 90218 1 mod_resource content 1 Doc_composants MSP430F543x_Datasheet_slas612c 2 pdf O MSP430G3xx Datasheet from tiFile http moodle epfl ch pluginfile php 1580216 mod_resource content 2 Doc_composants msp430g2553 pdf Manipulation 2 GPIO Chenillard gt Elaborate a program to do a chenillard function on Port8 bits 1 to 6 on WSN or Port2 bits O to 5 on LaunchPAD rotation of value 1 in the port bits 1 3 Watch Dog Timer During the procedure of power up a watchdog timer is initiated After 32 ms the watchdog timer will reset the CPU if not serviced A specific access needs to be done before a programmable expiration time For debugging purposes it is recommended to deactivate the watchdog The WDTCTL register is a
9. d as counter The main block of the Timer Module is a 16 bit free running counter that can be configured to count up or down TAxR The TAxCCRy register is used to compare a desired value with the free running counter OxFFFF is the maximum upper value The TAxCCRy CCIFG flag is used to indicate when the counter reach the desired value and could generate an interruption if properly configured The figure 3 below shows the general architecture of the Timer unit TASSEL ID IDEX Timer Clock MC 16 bit Timer y foray i 7 gt TAXR cols ow cov CCIBA CCI6B Ssccl Set TAxCCR6 CCIFG Output D Set Q OUT6 Signal Unita FO D OUTMOD EQUO ifi Timer Clock j Reset Figure 7 Timer A block schematic from TI By using the Compare function a delay can be easily programmed The clock dividers can be used in order to achieve a desired counting range As exercise and using the Compare functionality you have to write a function that has a delay parameter as input in number of ms that program correctly the TAxCCR register and actively polls the Compare CCIFG Flag The MSP430G2 has only TimerA functionality search on the User Manual the differences and the pins assignment Manipulation 3 TimerA0O delay gt Use the TimerA1 to realize a delay function where the input parameter is a delay in ms Program this function using the CCR comparator R Beuchat
10. date the results R Beuchat E Users Rene rb laboratories trunk Enonces_Doc MSP430_ LaboDocuments Labo MSP430 2 0 docx Processor Architecture Laboratory EPFL 9 MSP430 1 5 TimerA0O with interruption It is possible to use the TimerAO with Output compare function to generate a periodic interruption A vector table has the address of every interrupt routine that needs to be called for a specific Interrupt Request The address for the TimerAO is OxFFEC entry 54 in decimal Each entry is 16 bits and the table start at address OxFF80O so OxFF80 2 54 OxFFEC A specific compilation pragma is used by the compiler to specify the interrupt service routine and the corresponding vector address The entry points for the interruption vectors are specified in the msp430f5437 h file define TIMERO BO VECTOR 60 1u OxFFF8 Timer B7 CCO define TIMERO Bl VECTOR 59 1u DxPeeo Taner By Cel 6 Te define TIMERO AO VECTOR 54 1u OxFFEC Timer0 A5 CCO define TIMERO Al VECTOR 53 lu OxXFFEA TimerO A5 CC1 4 TAO define TIMER1 AO VECTOR 49 lu OxFFE2 Timerl A3 COO define TIMER1 Al VECTOR 48 1u OxFFEO Timerl A3 CC1 2 TAI a Specification of an interrupt routine in Code Composer 4 pragma vector TIMERO Al VECTOR interrupt void TimerA0 void Interruption function for TAIFG something to do TAOCTL amp TAIFG Clear TAIFG flag in TAOCTL register In order to enabl
11. e global interrupts the following instruction must be executed bis SR register GIE Enter global Interrupt Manipulation 5 Interruption on TimerA0 gt Use the TimerA0d to generate periodic interrupt of 50 ms Toggle a GPIO on each interrupt Use an oscilloscope to view and validate the results IRQ Interrupt Service Requested q IRACC Interrupt Request Accepted POR Figure 9 TimerA B Interrupt Request Ack block schematic TAxCCRO TBxCCRO from ti Same functionality for the other CCRn R Beuchat E Users Rene rb laboratories trunk Enonces_Doc MSP430_ LaboDocuments Labo MSP430 2 0 docx Processor Architecture Laboratory Timer interrupt vectors Timer 10 Vector address OxFF80 2 Priority EPFL MSP430 Symbol Name Priority Priority Teo TencoRG coFGo_ orFFFs mea Highest active in TBOIV OxFFF6 TBOCCRI1 TBOCCR2 TBOCCRS TBOCCR4 TBOCCRB TBOCCR6 TBOCTL CCIFG1 CCIFG2 CCIFG3 CCIFG4 CCIFGS5 CCIFG6 TBIFG One address for sources 7 TIMERO BI _VECTOR Tmo TaacoRe coirGo OwFFEC Highest active in TAOIV TAOCCR1 TAOCCR2 TAOCCRS TAOCCR4 TAOCTL CCIFG1 CCIFG2 CCIFG3 CCIFG4 TAIFG OxFFEA One address for sources 5 TIMERO Al _ VECTOR TAT Tacoma _ ccioo oF menje Highest active in TATIV 1 5 1 nian prioriti R Beuchat TA1CCR1 TA1CCR2 TAICTL CCIFG1 CCIFG2 TAIFG OxFFEO One address sources fo
12. hange the frequency of the FLLREFCLK input with a Digitally Controlled Oscillator DCO The DCOCLK and DCOCLKDIV frequencies are given by e fbcocLk D N 1 x fELLREECLK n reset fpcocik 2 097152 MHz o focociKpIv N 1 x fELLREECLK n reset fococLkoiv 1 048576 MHz gt MCLK SMCLK R Beuchat E Users Rene rb laboratories trunk Enonces_Doc MSP430_ LaboDocuments Labo MSP430 2 0 docx Processor Architecture Laboratory EPFL 3 MSP430 with e D 1 2 4 8 16 or 32 UCSCTL2 FLLD bits 14 12 reset 001 gt 2 e N 1 1023 UCSCTL2 FLLN bits 9 0 reset 000011111 gt 31 1 e n 1 2 4 8 12 16 UCSCTL3 FLLREFDIV bits 2 0 reset 000 gt 1 The figure 1 presents the general view of the unified clock system block and the reset default values for the MSP430F5437 version The registers are UCSCTLO gt UCSCTL8 The OSC block top left in the figure could output 3 frequency signals e XT1ICLK 32 768 Hz from external quartz e VLOCLK 10 kHz Low frequency e REFOCLK 32 768 Hz internally generated Clk used by default gt reset on ACLK The FLL block middle left in the figure could output 2 frequency signals e DCOCLK e DCOCLKDIV gt DCOCLK divided by 1 2 4 8 16 or 32 depending on FLLD register Internal rig yep VLOCLK DIVA Oscillator gt C XOUT E a _ XT2IN l loniy wi Main System Clock i XT2 not present on chip y a i SERR xT2 Oscilator MODx DCOR SCGO
13. password protected register used in the configuration of the watchdog timer Any read write operation in the WDTCTL register must use word instructions and write accesses must include the write password 0x5A WDTPW in the upper byte Have a look on the MSP430 full documentation for registers descriptions and use Stop the watchdog timer WDTCTL WDTPW WDTHOLD some other useful selections Periodically clear an active watchdog and specify the delay for next period WDTCTL WDTPWt WDTIS2 WDTIS1 WDTCNTCL Change watchdog timer interval WDTCTL WDOTPWAWDITCNTCITSSE ly Change WDT to interval timer mode clock 8192 interval clear counter WDTCTL WDTPW WDTCNTCL WDTTMSEL WDTIS 8192 1 4 Timer In the family MSP430F5437 two different 16 bit timer modules are present TimerA 2 blocks and TimerB e TimerAd is available on o Port1 5 Port1 0 TA0 4 TA0 0 TAOCIk o Port8 4 Port8 0 TA0 4 TA0 0 e TimerAt1 is available on R Beuchat E Users Rene rb laboratories trunk Enonces_ Doc MSP430_ LaboDocuments Labo MSP430 2 0 docx Processor Architecture Laboratory EPFL 6 MSP430 o 6Port2 3 Port2 0 TA1 2 TA1 0 TA1Clk o Port7 3 TA1 2 o Port8 6 Port8 5 TA1 1 TA1 0 e TimerB is available on o Port4 7 Port4 0 TBOCIk TB6 TBO Pond Poni TimerAd Pone Ponz TimerAt_ CCIxB CCIxA C Pona imerso Input Capture Pa Input Input Capture COXE oe Capture ee m CCIxA CCIxB TBOCIK If the Input Ca
14. pture mode is used the user should select the source of the input signal as for Timer A there are 2 sources pins available CCIxA and CCIxB As an output with Timer functionality the corresponding bit in the GPIO PxSEL must be programmed for the associated peripheral mode and not GPIO this for each corresponding bit as 1 by default the GPIO mode is selected Ponti Timerad Pona J Timerat_ Input Input GOIA Capture eee Capture p Device Pinot MSP430G2x13 and MSP430G2x53 20 Pin Devices TSSOP and PDIP pwec of 1 2010 DVSS P1 0 TAGCLK ACLK AOMCAD Oi 2 DO XIN P 6 TAO 1 PWT AO OY UCADR X D UCADSOMIVATICAT OR 3 AOUTIP T P1 ATA0 UCADTAD UCADSIMO A2 CA2 Oi 4 TEST SBWTCK P1 3a ADC1O0CLK CAOUT VREF VEREF A3 CA3 Of 5 bap 1670 RST NMIUSBWTDIO P1 4 SMCLK UCBOSTE UCAODCLK VREF VEREF HA4 CA4 TCK Oi 6 TOP VIEW J P17 CAOUTUCBOSIMO UCBOSDAVAT ICATITDO TDI P1 5 TAO O UCBOCLE UCADS TEAS CAS TMS Oi 7 1410 P1 6 TAO 1 UCBOSOMIUCBOSCL AS CAG TDITCLEK P 0 TA1 0 Of 8 1310 P2 5 TA1 2 io 12710 P2 4 TA1 2 P 1 741 1 Of 110 P2 3 TA1 0 P2 2 TA1 1 0O i NOTE ADC10 ts available on MSP430G2x53 devices only NOTE The pulldown resistors of port P3 should be enabled by setting PAREN 1 Figure 6 Pinning og MSP430G2x53 20 pins R Beuchat E Users Rene rb laboratories trunk Enonces_Doc MSP430_ LaboDocuments Labo MSP430 2 0 docx Processor Architecture Laboratory EPFL 7 MSP430 1 4 1 TimerA use
15. r General Interruption architecture Password violations F RST NMI BOR POR PUC circuit 3 TIMER1 Al _VECTOR System NMI User NMI Module A int Module B_int Interrupt daisy chain and vectors Module _C_ int VAB 6LSBs Module _D_int Figure 10 General interruption architecture from TI E Users Rene rb laboratories trunk Enonces_ Doc MSP430_ LaboDocuments Labo MSP430 2 0 docx Processor Architecture Laboratory EPFL 11 MSP430 1 5 2 General Interruption architecture a m SYSTEM WORD INTERRUPT SOURCE INTERRUPT FLAG INTERRUPT ADDRESS PRIORITY System Reset Power Up External Reset E Watchdog Timeout Password WDTIFG KEYY SYSRSTIVJ eset OFFFEh 63 highest Violation Flash Memory Password Violation PM Password Violation get on SVMLIFG SVMHIFG DLYLIFG DLYHIFG Vacant Memory Access VLRLIFG VLRHIFG VMAIFG JMBNIFG Non inask able OFFFCh 67 l i L i JTAG Mailbox JMBOUTIFG SYSSNMV User NMI Oscillator Fault NMIIFG OFIFG ACCVIFG SYSUNIV I Non maskable OFFFAh Binet asc ed LE TBO TECCRO CCIFGO Maskable OFFF8h TBCCRI CCIFG1 TECCRE CCIFGE THRIFG Tey a4 Maskable QOFFF6h Watchdog Timer_A Interval Timer WOTIFG Maskable DFFFah EJ Mode UCAORXIFG UCADTXIFG UGAON Maekable orff 7 8 at Recent B0 Receive Transmit UCBORXIFG UCBOTXIFG UCABOIV 13 ese oS ADGA ADCIPIFGO ADCIZIFGIS ADCI2zIvy Maskabla OFFEEh 55 _ TAOCCRO
16. stant and display the result on an oscilloscope R Beuchat E Users Rene rb laboratories trunk Enonces_Doc MSP430_ LaboDocuments Labo MSP430 2 0 docx
17. ve registers that should be configured for the proper operation of each pin Port P8 P8 0 to P8 7 Input Output With Schmitt Trigger Pad Logic P amp sRENx ee ra i I l a a L F P8DIRx a Direction 0 Input 1 Output I PsOUTx Module X OUT PaSEL x ps o TAo 0 Pa 1 TA0 1 Ps 2 TAO 2 P3 3 TAQ 3 P3 4 TA0 4 PsiN x q Pa s TA1 0 Ps 6 TA1 1 i Pa 7 ModuexN 2D i Figure 5 Internal architecture of the Port 8 PspSx m 0 Low drive 1 High drive Depending on the I O port several registers should be configured in order to achieve the desired function The table below summarizes the main registers and their configuration Configuration Direction Register Read Value Register 0 gt Low 1 gt High E PxOUT Write Value Register 0 gt Low 1 gt High Doo PxSEL Function Selection Register 0 gt I O 1 gt Peripheral ee eee i select pull up down 0 gt Pull down 1 gt Pull up Output Drive Strength Register 0 Reduced 1 gt Full FM le wre In the table above x represents a specific register for Port 1 P1 If enabled PXOUT PxREN Resistor Enable Register R Beuchat E Users Rene rb laboratories trunk Enonces_Doc MSP430_ LaboDocuments Labo MSP430 2 0 docx Processor Architecture Laboratory EPFL 5 MSP430 Manipulation 1 GPIO gt Using the WSN4U board schematic and TI MSP430 documentation program an I O port to gener
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