QPLL User Manual - Nevis Laboratories
Contents
1. QPLL version 2 is 100 pin compatible with version 1 Except for operation mode 2 see QPLL operation modes the two versions are functionally identical Users that already developed boards based on version 1 will be able to simply replace each QPLL by a QPLL2 ASIC changes e The frequency select bus was expanded to 6 bits e Pins autoRestart and reset become dual function Manual changes e Section OPERATION expanded e Section Timing new e Section Crystal specification new e Section Power supply sensitivity new e Section PCB Layout recommendations expanded e Section Procedure to verify the PCB parasitic capacitance new Version 0 3 e Dielectric thickness corrected in Figure 9 recommend layout Version 0 2 e Legend corrected in Figure 9 recommend layout Version 0 1 Section PCB Layout recommendations added to the manual VERSION 1 0 3 QPLL MANUAL PRELIMINARY INTRODUCTION The QPLL is a Quartz crystal based Phase Locked Loop Its function is to act as a jitter filter for clock signals operating synchronously with the LHC bunch crossing clock Two frequency multiplication modes are implemented 120 MHz and 160 MHz modes In the 160 MHz mode the ASIC generates three clock signals synchronous with the reference clock at 40 MHz 80 MHz and 160 MHz while in the 120 MHz mode the synthesized frequencies are 40 MHz 60 MHz and 120 MHz In both cases the highest frequenc2. and the other one with the input set to 1 In absolute value the slopes of both curves are less than 0 13 Hz mV at Vaa 2 5 V Notice that the dependence on the power supply increases once the ASIC is powered with a voltage smaller than 2 3 V Such a regime of operation should be avoided In other to keep some operation margin it is recommended that the minimum power supply voltage should not be reduced bellow 2 4 V This is valid for operation both in the PLL mode and on the Clock Source mode VERSION 1 0 17 QPLL MANUAL PRELIMINARY PCB LAYOUT RECOMMENDATIONS The QPLL is based on a Voltage Controlled Quartz Crystal Oscillator VCXO The frequency of oscillation of such circuit is essentially imposed by the quartz crystal resonance frequency However the circuit capacitance which includes the layout parasitics will also have an influence In the case of a VCXO this manifests itself in two ways first the oscillation frequency is not exactly the quartz crystal resonance frequency but higher called the loaded oscillation frequency and second the frequency pulling capability of the circuit is affected by the total circuit capacitance in particular by the minimum capacitance achievable To cope with any frequency uncertainty the crystal is specified for a given load capacitance This gives the manufacturer the capability of tuning the crystal to a specific circuit Concerning the pulling range one could be tempted to think that
3. adding as much variable capacitance as possible would be a solution to increase the frequency pulling ability of the circuit However in the limit of an infinite load capacitance the oscillation frequency tends to the crystal resonance frequency In this limit the frequency sensitivity to capacitance variations is very small and the VCXO has thus a small pulling ability The solution is thus to work on the extreme of low capacitances where the frequency sensitivity is maximised Figure 8 illustrates these concepts for a practical crystal in this figure C12 represents the crystal package capacitance 800 Frequency offset due to C12 700 This is the maximum frequency deviation 00 Can limited by the external parasitics 3 pF 400 Af ppm f 100 ppm 100 AC C Figure 8 Circuit capacitance versus frequency pulling ability We are thus faced with two problems first minimise the parasitic capacitances introduced by the circuit layout so that the pulling range does not get degraded and second make sure that the circuits built by the QPLL users display a load capacitance which is identical to the specified crystal load capacitance It is thus strongly recommended that the users adopt the layout represented in Figure 9 for the 1 This would be a good solution if the capacitance could be strictly varied from a very small to a large value However in practical circuits a large maximum value also implies a relatively lar
4. bit That is after a given range is selected by the bits f Select lt 5 0 gt see Figure 2 the clock input can be used to choose between the maximum and minimum oscillation frequencies of 1 This picture will be updated once the final quartz crystals will be available It is used here only as an example The frequency range is not the target range VERSION 1 0 7 QPLL MANUAL PRELIMINARY that range Setting the clock input to a 1 selects the maximum frequency while setting it to 0 selects the minimum frequency Warning Mode 1 should never be used for standalone operation QPLL as a simple clock generator In that mode and in the absence of a reference clock the QPLL is constantly executing frequency calibration cycles and its clock outputs are constantly having frequency jumps Any QPLL trying to lock to such a signal will never achieve a stable lock Mode 2 is thus the only mode recommended to implement a standalone clock source using a QPLL VERSION 1 0 8 QPLL MANUAL PRELIMINARY QPLL Signals autoRestart 5V compatible CMOS input with internal pull up resistor The functionality of this signal depends on the state of the externalContro signal if externalControl 0 autoRestart 0 Automatic restart of the PLL is disabled A frequency calibration cycle will only occur after a reset autoRestart 1 Automatic restart is enabled A frequency calibration cycle will occur each
5. cutting accuracy process temperature and power supply variations upon reset or loss of lock the ASIC goes through a frequency calibration procedure In principle this is an automatic procedure that in most applications should be transparent to the user However in some situations like for example chip or system testing the user might want to control it The signals that are relevant to this function are externalControl autoRestart and f Select lt 5 0 gt If the externalControl signal is set to 1 then the automatic calibration procedure is disabled and the VCXO centre frequency is set by the signals f Select lt 5 0 gt otherwise the free running VCXO frequency is automatically determined Please note that when the externa Control signal is set to 1 the signals autoRestart and rese become f Select lt 4 gt and f Select lt 5 gt respectively The QPLL contains a lock detection circuit that monitors the lock state of the phase locked loop If the PLL is detected to be unlocked a frequency calibration cycle is initiated to lock the PLL This feature can be disabled by forcing the signal autoRestar to 0 In this case a frequency calibration cycle is only started if a reset is applied to the IC When externalControl is forced to 0 the locked signal reports the locked status of the PLL In this case the lock detection logic filters the random behaviour of th
6. input to 1 This will give max for that range The average of these two frequencies f min and f max must be within f Luc 25 ppm Please note all the frequency measurements mentioned above need to be done with an absolute accuracy of at least a few parts per million ppm Although most laboratory frequency meters are capable of providing such relative accuracy they are rarely that accurate in absolute terms The solution in that case is to feed the frequency meter with a precise clock signal from a calibrated frequency standard like for example a GPS based frequency source At CERN we are equipped to do such precise frequency measurements and we can help users that aren t equipped to do so in their own labs 1 Number to be confirmed once the crystals will be received from the manufacturer VERSION 1 0 20
7. time the PLL is detected to be unlocked or after a reset if externalControl 1 autoRestart becomes f Select lt 4 gt cap VCXO decoupling node A 100 nF capacitor must be connected between this pin and ground Inductance of the interconnection must be minimized error 2 5V CMOS output This signal indicates that an SEU has occurred Since SEU events are dealt with automatically by the ASIC logic this signal will be active only during the period in which the error condition will persist A SEU on the QPLL logic circuits will not affect the operation of the PLL externalControl 5V compatible CMOS input with internal pull down resistor externalControl 0 The VCXO centre frequency is set by the automatic frequency calibration procedure externalControl 1 The VCXO free running frequency is set by the input signals f Select lt 5 0 gt f Select lt 3 0 gt 5V compatible CMOS inputs with internal pull down pull up resistors f Select lt 3 gt lt pull up f Select lt 2 gt lt pull down f Select lt 1 gt lt _ pull down f Select lt O gt lt pull down These signals including f Select lt 5 4 gt control the VCXO free running oscillation frequency when the signal externalContro is set to 1 If externalControl is set to 0 these signals have no influence on the IC operation inCMOS 5V compatible CMOS clock input with internal pull down resistor This is th
8. In this case the slope of the curve is 0 72 ps mV for the nominal power supply voltage QPLL2 Relative delay measurement reference is delay V 2 5 V 2 5 2 6 2 7 2 4 2 3 Vag M 2 2 2 1 relative measurement In this measurement the reference clock is fed to the LVDS input Figure 6 Phase error as function of the power supply voltage 16 VERSION 1 0 QPLL MANUAL PRELIMINARY VCXO free running oscillation frequency The QPLL can run stand alone as a clock source see Operation as a Clock Source When running in this mode there is no external reference to be tracked and the VCXO will produce a frequency which is essentially dependent on the quartz crystal being used and on the ASIC settings chosen However since no reference signal is being tracked the power supply voltage will have some influence on the oscillator frequency QPLL2 Relative frequency measurement reference is frequency V 2 5 V e data clockin 0 fit clockin 0 data clock in 1 fit clock in 1 Frequency offset Hz Figure 7 VCXO Oscillation frequency as function of the power supply voltage relative measurement Figure 7 displays the VCXO oscillation frequency offset as function of the power supply voltage The measurements are made relative to the VCXO frequency when the power supply voltage is 2 5V Notice that two curves are plotted one corresponding to the reference clock in put set to O
9. L Package 19 lvds40MHz 4 exteralControl oo eae CIS vdd 5 autoRestart fa Select lt 4 gt 17 gnd 6 reset f Select lt 5 gt 16 lvWds160MHz 7 fa Select lt 3 gt 15 lvds160Mkz Biggin tt tt I oo gt oa i 1 oO N w CH D Oo fy oe Ga 898 5 5S HU EE 2 2 oO 2 O og S or A t y Figure 4 QPLL2 pinout Pin assignments Pin Number Signal Name Signal type 1 inLVDS Input LVDS 2 inLVDS Input LVDS 3 inCMOS Input CMOS 5V compatible 4 externalControl Input CMOS 5V compatible 5 autoRestart f Select lt 4 gt Input CMOS 5V compatible 6 reset fySelect lt 5 gt Input CMOS 5V compatible 7 foSelect lt 3 gt Input CMOS 5V compatible 8 error Output 2 5 V compatible 9 locked Output CMOS 2 5 V VERSION 1 0 12 QPLL MANUAL PRELIMINARY 10 gnd Power 11 vdd Power 12 lvds80MHz Output LVDS 13 lvds80MHz Output LVDS 14 fyoSelect lt 2 gt Input CMOS 5V compatible 15 lvds160MHz Output LVDS 16 lvds160MHz Output LVDS 17 gnd Power 18 vdd Power 19 lvds40MHz Output LVDS 20 lvds40MHz Output LVDS 21 foSelect lt 1 gt Input CMOS 5V compatible 22 vdd Power 23 cap Power 24 xtal1 Analogue Quartz crystal 25 gnd power 26 xtal2 Analogue Quartz crystal 27 mode Input CMOS 5V compatible 28 foSelect lt 0 gt Input CMOS 5V compatible VERSION 1 0 13 QP
10. LL MANUAL PRELIMINARY CRYSTAL SPECIFICATION A quartz crystal will be provided with each QPLL The main characteristics of the crystal are given on the following table Pos Description Symbol Typ Min Max Unit 1 Crystal type Inverted mesa AT Cut 2 Resonance mode Fundamental 3 Load Frequency FL 160 314744 MHz 4 Load Capacitance CL 5 5 pF 5 Frequency Tolerance at 25 C AFL FL 18 18 ppm 6 Motional Capacitance C1 4 2 fF 7 Static Capacitance Co 2 8 pF 8 Drive Level P 100 uw 9 Operating Temperature Range OTR 0 60 C 10 Series Resistance at 25 C Rs 35 Ohm 11 Drift over OTR AFL FL 10 10 ppm 12 Aging first year AFL FL 3 ppm 13 Package type SMD ceramic 14 Package surface 29 6 mm 15 Package height 1 75 Mm Table 4 Quartz crystal specification 1 This spec needs a 100 frequency verification over temperature range 5 C intervals Value to be confirmed VERSION 1 0 14 QPLL MANUAL PRELIMINARY POWER SUPPLY SENSITIVITY Some of the QPLL characteristics are power supply voltage dependent namely the VCXO free running oscillation frequency and the static phase error Both of these variables have an influence on the jitter performance It is thus advisable to keep the noise levels on the power supply to the minimum possible The numbers given below will help the user to form an opinion on how much noise ca
11. NCE library The footprint is available in the VERSION 1 0 19 QPLL MANUAL PRELIMINARY library CNSPECIAL under the name QPLL For the package type the LPCC option must be used A GBR file containing the layout represented above can be found on the QPLL home page see PCB layout Procedure to verify the PCB parasitic capacitance There are two alternative ways to verify that the PCB has been correctly designed The first and simplest is to check the circuit lock range This can be done by sweeping the input frequency arround the LHC frequency By approaching the LHC frequency from below the lower locking frequency can be obtained Similarly by approaching the LHC frequency from above the upper locking frequency can be determined The LHC frequency Duc must be well centred within these two limits For these measurements the frequency sweep should be done in digital steps allowing at each frequency step time enough for a calibration cycle to be executed The second method consists in measuring the free running oscillation frequency of the PLL The following procedure needs to be applied set the signal externa Contro to 1 and the signals fypSelect lt 5 0 gt to 10011 1 binary Then measure the output frequency while the reference clock input is forced to 0 This will give the minimum oscillation frequency f min for the selected frequency range Then repeat the measurement forcing the reference clock
12. QPLL MANUAL PRELIMINARY QPLL Manual Quartz Crystal Based Phase Locked Loop for Jitter Filtering Application in LHC Paulo Moreira CERN EP MIC Geneva Switzerland 2004 01 26 Version 1 0 Technical inquires Paulo Moreira cern ch preliminary VERSION 1 0 1 QPLL MANUAL PRELIMINARY Introduction 4 Features ee E ee ee See cca bn vance Eege EE ee Ee ee A OPERATION 5 QPLL operation MOdES 2 wiciiceiecieccedeecetievecsla sie d e levee Gaveecla eve ege aiveeclaseieees 6 Moge A E AEI AE e geed e gedeien 6 ModE To raan eege AER Ae td eteateeneeet 6 Mode Agenda 7 QPLEL S Ee aE E E A T se suceay se cedeed sweets sueevecddenenders eceeetas 9 Re BE 11 QPLL pinout 12 Pin ASSIQMIMENUS 2 cece secetec seat gege A A AE EE EES 12 Crystal specification 14 Power supply sensitivity 15 Static phase Srl ces at cde eae cee d aah e aaiae d aaa ae a da dadaa ani adaa dadana dccTesedusuesutedeectes 15 VCXO free running oscillation frequenCy s ssssssssennenrennnnnnnnnnnnunnnnnnnnnnnnnnnnnnnnnnnnnnnnna 17 PCB Layout recommendations 18 Procedure to verify the PCB parasitic Capacitance cccccssesseeeeeceeeeeseeseceneeeeeeees 20 VERSION 1 0 2 QPLL MANUAL PRELIMINARY Summary of Changes Version 1 0 This version of the manual reflects the changes that were introduced in the second version of the QPLL To avoid any confusion with the previous version these chips are now marked as QPLL2
13. document reading In fact these numbers should be interpreted to be the exact multiples of the LHC bunch crossing clock frequency VERSION 1 0 4 QPLL MANUAL PRELIMINARY OPERATION The QPLL uses the LHC bunch crossing clock as the reference frequency This signal can be feed to the ASIC either in CMOS or LVDS levels please refer to Figure 1 Selection of which input to use is simply done by forcing the unused clock input to logic level 0 notice the use of the OR function in the reference clock signal path in the block diagram The three clock outputs are LVDS signals and their frequency depends on the mode input When mode is set to 0 the output clock frequencies are 40 MHz 60 MHz and 120 MHz otherwise the frequencies are 40 MHz 80 MHz and 160 MHz Since the highest clock frequency is obtained directly from the Voltage Controlled Crystal Oscillator VCXO different crystals are required for operation in one of the two frequency multiplication modes A crystal is provided by CERN with each QPLL for operation in the 160MHz mode 160 MHz 120 MHz LVDS IN 80 MHz 60 MHz CMOS IN Mode External Control IT Select lt 3 0 gt Auto Restart f Select lt 4 gt Reset f Select lt 5 gt Vdd Cap Voltage regulator Figure 1 QPLL2 block diagram The use of a VCXO in the QPLL allows to achieve low jitter figures but imposes the limitation of a small frequency lock range To cope with crystal
14. e internal PLL lock indication However if the externa Control signal is set to 1 the Locked signal will have a random behaviour during loss of lock and lock acquisition VERSION 1 0 5 QPLL MANUAL PRELIMINARY The logic circuits controlling the PLL use redundant logic techniques to cope with Single Event Upsets SEU The error flag indicates momentarily that one SEU has occurred These errors are dealt with automatically requiring no action from the user QPLL operation modes The QPLL operation modes are controlled by the state of the signals externalControl and autoRestart as indicated on Table 1 externalControl autoRestart Mode 0 0 0 0 1 1 1 D 2 Table 1 QPLL operation mode selection Mode 0 In this mode the QPLL frequency calibration logic is active but a frequency calibration cycle is only executed after a reset Mode advantages Once a first frequency calibration cycle has been executed with the reference clock present the QPLL will keep the frequency calibration settings until another reset is applied This allows the QPLL to acquire lock relatively fast 250 us when compared with mode 1 where a frequency calibration is executed every time lock is lost 180 ms This mode can be particularly useful in radiation environments where both the reference clock and the QPLL analogue circuits can be subject to single event upsets Mode disadvantages Becau
15. e CMOS reference clock input When in use inLVDS and inLVDS must be set to logic levels 0 and 1 respectively inLVDS and inLVDS LVDS clock inputs These signals are the LVDS reference clock inputs When in use inCMOS must be held at logic level 0 locked 2 5V CMOS output This signal reports the PLL locked status if externalControl 0 In this case the lock indication is filtered by the QPLL lock detection logic giving a stable indication during loss of lock lock acquisition or during lock if externalControl 1 VERSION 1 0 9 QPLL MANUAL PRELIMINARY In this case the lock indication state reflects the instantaneous lock indication provided by the PLL The signal will display a random behaviour during loss of lock or lock acquisition Lvds40MHz Ivds40MHz LVDS output 40MHz clock output Ivds80MHz Ilvds80MHz LVDS output mode 0 60 MHz clock signal with 120 MHz quartz crystal mode 1 80 MHz clock signal with 160 MHz quartz crystal Ivds160MHz Ilvds160MHz LVDS output mode 0 120 MHz clock signal with 120 MHz quartz crystal mode 1 160 MHz clock with 160 MHz quartz crystal mode 5V compatible CMOS input with internal pull up resistor mode 0 120 MHz frequency multiplication mode 120 MHz quartz crystal required mode 1 160 MHz frequency multiplication mode 160 MHz quartz crystal requ
16. ge minimum value That is the ratio between the minimum and maximum capacitance cannot be freely chosen VERSION 1 0 18 QPLL MANUAL PRELIMINARY interconnections between the QPLL and the quartz crystal Failing to do so it might result in the best case in a reduced or asymmetrical lock range and in the worst case in the impossibility to lock to the LHC frequency It is thus the user responsibility to follow the recommended layout for the interconnections between the quartz crystal and the QPLL as close as possible From a simple parallel plate capacitance calculation each interconnection between the chip and the crystal crystal and IC soldering pads plus the PCB track contributes a capacitance to ground of about 0 47pF This value can be used as a guideline to design the PCB However in any case the user should check that the QPLL locking range is well centred arround the LHC frequency using the procedure described in the following section Length of each track between soldering pads edge to edge Length 4 93 mm Top view 3 49 mm Su Cross section example First wiring level 35 um 800 um Substrate FR4 s 4 4 1 MHz Ki This dielectric thickness has e to be respectec Ground plane Other wiring level s Figure 9 Recommend layout for the QPLL and crystal interconnection To facilitate the CAD work a schematic capture symbol and the layout footprint of the ASIC are available in the CERN CADE
17. ired reset 5V compatible CMOS input if externalControl 0 Active low reset signal It initiates a frequency calibration cycle and lock acquisition if externalControl 1 reset becomes f Select lt 5 gt xtal1 xtal2 Quartz crystal connections pins VERSION 1 0 10 QPLL MANUAL PRELIMINARY Timing The QPLL timing diagram is illustrated in Figure 1 The values for the several clock outputs are given in Table 2 and Table 3 INCMOS InLVDS InLVDS Lvds 1 60MHz Lvds80MHz Lvds40MHz INLVDS INLVDS INCMOS Cmos40MHz ta T pam ta V Lvds40MHz Se H Lvds40MHz ae lun se Lvds80MHz d Lvds8OMHz i t He Lvds1 60MHz d4 n wasieomz AL LA JL CL LL CL Figure 3 QPLL timing definitions CMOS clock reference input mm mem 1 6 Table 2 Output delays referenced to the CMOS clock input LVS clock reference input winrar a 1 8 1 8 Table 3 Output delays referenced to the LVDS clock input VERSION 1 0 11 QPLL MANUAL PRELIMINARY QPLL PINOUT The QPLL is packaged in a 28 pin 5mm x 5mm Leadless Plastic Chip Carrier LPCC 28 with 0 5 mm pin pitch Additional package information can be obtained from the ASAT web site http www asat com Spow Z CDD 9S pub GZ LIO pZ doo Z PPA ZZ T lt 0 gt 400 188 8Z 1 inLVDS 21 f Select lt 1 gt 2 inlVDS 20 Ivds40MHz 3 INCMOS QPL
18. n be tolerated on the power supply without incurring performance degradation Static phase error The PLL inside the QPLL ASIC is a control loop that tries to maintain zero phase error between the reference clock and the internally generated VCXO clock However both these clocks propagate through clock buffers that introduce a non zero delay between the two signals see Timing More over since these buffers are external to the PLL control loop their power supply dependence is not compensated for Variations in the power supply will result thus in a varying phase delay between the two clock signals QPLL2 Relative delay measurement reference is delay V 2 5 V 300 ee Phase error ps H Figure 5 Phase error as function of the power supply voltage relative measurement In this measurement the reference clock is fed to the CMOS input Figure 5 displays a typical curve for the static phase error as a function of the power supply voltage In this case the CMOS clock input is used as the clock reference input The measurement is relative that is the phase error introduced by varying the power supply is measured relative to the static phase error when the power supply voltage is 2 5 V the nominal power supply voltage The curve displays a slope of 0 24 ps mV at 2 5 V Similarly Figure 6 displays the static phase error when the VERSION 1 0 15 PRELIMINARY QPLL MANUAL LVDS input is used
19. referable VERSION 1 0 6 QPLL MANUAL PRELIMINARY Mode 2 In this mode the QPLL frequency calibration logic is inactive The QPLL can be used as a PLL or as a standalone clock generator Operation as a PLL The user must centre the VCXO operation range arround the reference clock frequency by setting the bits fpSelect lt 5 0 gt As shown in Figure 2 the settings should be such that the centre of the analogue range is as close as possible to the operation frequency Mode advantages None Mode mainly used for chip characterization and production testing Mode disadvantages Requires the user to constantly keep track of any changes of circuit characteristics for example crystal aging and operation conditions like power supply voltage and temperature Digital Control Crystal 1 min center 40 08 TT TTT TTT E E a e N Analogue range for N 40 D S finan for Clock Input ne 3 40 075 nme fe fOr TEE a Senn d lt f gt f fj 2 reference f Select lt 5 0 gt 40 40 0 i 0 10 20 30 40 50 60 70 f Select lt 5 0 gt Figure 2 VCXO frequency as function of the digital control bits foSelect lt 5 0 gt Operation as a Clock Source The QPLL can be used as a standalone crystal oscillator whose frequency can be tuned by the control bits fo gt Select lt 5 0 gt In this case the QPLL is simply operated without a reference clock In this mode the clock input can be used as an extra frequency select
20. se the frequency calibration settings are maintained during operation only the QPLL analogue range is available to coupe with the reference clock drifts and changes in the power supply voltage and temperature please see Figure 2 for clarification of the terms used In mode 0 the system where the PLL is integrated must guaranty that the QPLL lock signal is constantly monitored In the case of loss of lock and if the QPLL does not regain lock after a pre established delay a reset must be applied so that a new calibration cycle is executed Mode 1 In this mode the QPLL frequency calibration logic is active a frequency calibration cycle is executed after a reset or each time lock is lost Mode advantages This mode requires minimum monitoring from the system in where the QPLL is integrated The QPLL constantly monitors its lock state and executes a frequency calibration cycle every time loss of lock is detected This mode displays the largest tracking range in relation to the reference frequency drifts and the largest tolerance to power supply and temperature variations Mode disadvantages In principle this should be the preferred mode of operation However in radiation environments this mode can lead to relatively large dead times 180 ms since a calibration cycle will be executed each time the reference clock or the analogue circuitry of the QPLL will be disturbed by a single event upset In those circumstances mode 0 might be p
21. y is generated directly from a Voltage Controlled Crystal Oscillator VCXO and the lower frequencies are obtained by synchronous division The two frequency multiplication modes require Quartz crystals cut to the appropriate frequencies Features Phase Locked Loop based on a Voltage Controlled Crystal Oscillator Designed to frequency and phase lock to the LHC master clock f 40 0786 MHz Locking range A 3 7 KHz arround f 40 0786 MHz Loop bandwidth lt 7 KHz Locking time including a frequency calibration cycle mode 1 180 ms Locking time excluding a frequency calibration cycle mode 0 250 us Two frequency multiplication modes o x1 x2 and x4 o x1 1 5 and x3 Output jitter lt 50 ps peak to peak for an input signal jitter less than 120 ps RMS Reference clock input levels o LVDS o CMOS single ended 2 5 V to 5 V compatible Three LVDS clock outputs Package LPCC 28 5 mm x 5 mm 0 5 mm pitch Power supply voltage 2 5V nominal allowed operation range 2 4V to 2 7V Phase error sensitivity to the power supply voltage less than 0 72 ps mV VCXO free running frequency sensitivity to the power supply 0 14 Hz mV typical Power consumption 100 mW Radiation tolerant 0 25 um CMOS technology Crystal A quartz crystal is provided with each QPLL 1 Please note that frequency numbers in this document are often rounded to the nearest integer This is just a simplification to facilitate
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