1260-13 Module Specification
Contents
1. 48 Chans vc gCilannel VO 96 Chans vec Jeanne vo Readback Y Readback Y Readback Peada MWe SE OD nd ema er TM yt acl lybact ici gt Control CR Ta Control 7 TS gt Control ij es Dy lt Internal Tri State Internal Tri State Internal EN l Gnd Gnd eg Gnd 114HVOC v 1140C N 114CMOS TTL E 48 PIN CARD 1 260 1 1 4 INTERFACE en connectoR BLOCK DIAGRAM CONNECTOR e Parallel Input Readback d le to Latches I Serial 8x96 MF eer xterna Converter 8x48 HVOC Fiyback Tri State 114CMOS TTL See Channel WO Control f Y Internal Tri State 114HVOC anne Information Logic Core VATE Output Driver Stage Gnd Serial Output to lla Latches a Control e Parallel 8x96 Converter 8x48 HVOC J External Synchronous Clock Clock Polarity Busy Polarity Busy Figure 2 2 Block Diagram Mating connector accessories are available Mating Connectors 160 Pin Connector Kit with backshell and pins Astronics Test Systems P N407664 160 Pin Cable Assembly 6 Ft 24 AWG P N 407408 001 The 160 Pin Connector Kit consists of a connector housing and 170 crimp pins After wire attachment the pin is inserted into the housing and will snap into place providing positive retention The suggested hand tool for the crimp pins is P N 990898 The corresponding pin removal tool is P N 9908992. Figure 1 2 The 1260 114CMOS Specifications 1 4 Astronics Test Systems Publication No 980824 114 Rev A Specifications CMOS TTL Astronics Test Systems Max Chan Input Voltage Chan Output Current Min High Output Voltage Max Low Output Voltage Available I O Channels Channel Synchronization Synchronous Trigger Handshake Polarity Synchronous Busy Handshake Polarity Shock Vibration Bench Handling Cooling Temperature Operating Non operating Relative Humidity Altitude Operating Non operating Power Requirements 5 VDC Weight Mean Time Between Failures MTBF Mean Time to Repair 1260 114 User Manual 5 5 VDC 8 mA maximum gt 3 8 VDC O 8 mA lt 0 44 VDC Q 8 mA 96 Bi directional I O Asynchronous Synchronous or Mixed User Programmable User Programmable 309 11 ms L sine wave 0 013 in P P 5 55 Hz 4 in 45 See 1260 100 cooling data 0 C to 55 C 40 C to 75 C 85 5 non condensing at lt 30 C 10 000 feet 15 000 feet 1 A maximum with all channels sourcing maximum loads 6 oz 0 21 kg gt 100 000 hours MIL HDBK 217E lt 5 minutes MTTR Specifications 1 5 1260 114 User Manual Power Dissipation CMOS TTL Specifications 1 6 Publication No 980824 144 Rev A The cooling of the Adapt a Switch carrier is dependent upon the chassis into which it is installed The carrier can nominally dissipate approximately 100 W Even wi
3. get a handle for the 1260 01T error viOpen hd1RM RI1260 01 DESC VI NULL VI NULL amp hd11260 if error lt 0 1 error handling code goes here form the offset for control register 0 note that the base A24 Address for the 1260 01T Module Operation 3 14 Astronics Test Systems Publication No 980824 114 Rev A 1260 114 User Manual is already accounted for by VISA calls vilIn8 and viOut8 module address shifted 10 places module address x 1024 portA_addr MOD_ADDR_114 lt lt 10 1 offset portA_addr PORT_NUMBER lt lt 1 error viOut8 vi VI A24 SPACE offset DATA ITEM if error lt 0 return error close the VISA session error viClose hdl1260 if error lt 0 error handling code goes here Astronics Test Systems Module Operation 3 15 1260 114 User Manual Publication No 980824 114 Rev A This page was left intentionally blank Module Operation 3 16 Astronics Test Systems Publication No 980824 114 Rev A 1260 114 User Manual Chapter 4 OPTIONAL ASSEMBLIES 407664 Connector Kit 160 Pin Comp vri utide G vad bris de Sees ae ib 4 3 407408 001 Cable Assy 160 Pin 6 ft 2AAMWCG 4 4 Astronics Test Systems Optional Assemblies 4 1 1260 114 User Manual Publication No 980824 114 Rev A This page was left intentionally blank Optional Assemblies 4 2
4. etetett EM S RE N H en Figure 1 4 The 1260 114HVOC Specifications 1 10 Astronics Test Systems Publication No 980824 114 Rev A Specifications High Current Voltage Open Collector Astronics Test Systems Max Chan Input Voltage Chan Output Current High Output Voltage Max Low Output Voltage Available I O Channels Channel Synchronization Synchronous Trigger Handshake Polarity Synchronous Busy Handshake Polarity Shock Vibration Bench Handling Cooling Temperature Operating Non operating Relative Humidity Altitude Operating Non operating Power Requirements 5 VDC Weight Mean Time Between Failures MTBF Mean Time to Repair 1260 114 User Manual 50 VDC 1 5 A maximum 2 lt Voh lt 50 VDC lt 0 5 VDC 1 5A 48 open collector channels Asynchronous Synchronous or Mixed User Programmable User Programmable 30g 11 ms 1 2 sine wave 0 013 in P P 5 55 Hz 4 in 45 See 1260 100 cooling data 0 C to 55 C 40 C to 75 C 85 5 non condensing at lt 30 C 10 000 feet 15 000 feet 0 5 A maximum 6 oz 0 21 kg gt 100 000 hours MIL HDBK 217E lt 5 minutes MTTR Specifications 1 11 1260 114 User Manual Power Dissipation High Current Voltage Open Collector Specifications 1 12 Publication No 980824 144 Rev A The cooling of the Adapt a Switch carrier is dependent upon the chassis into which it is installed The carr
5. plug in design providing for ease of replacement e Data Driven embedded descriptor allowing immediate use with any Option 01T switch controller regardless of firmware revision level e rr rr I ME 1 rrvrrerr prererertd Lrerererre vrrrrrrey S n hide HAH H NK V S A B eE a TT LE S SS Ki rr d i H Ges AAA EK 5 ver tener ma ze lich 017 O19 Figure 1 1 The 1260 114TTL Astronics Test Systems Specifications 1 1 1260 114 User Manual Specifications TTL Specifications 1 2 Max Chan Input Voltage Chan Output Current Min High Output Voltage Max Low Output Voltage Available I O Channels Channel Synchronization Synchronous Trigger Handshake Polarity Synchronous Busy Handshake Polarity Shock Vibration Bench Handling Cooling Temperature Operating Non operating Relative Humidity Altitude Operating Non operating Power Requirements 5 VDC Weight Mean Time Between Failures MTBF Mean Time to Repair Publication No 980824 144 Rev A 5 5 VDC 30 mA maximum gt 2 VDC Q 15 mA lt 0 5 VDC 24 mA 96 Bi directional I O Asynchronous Synchronous or Mixed User Programmable User Programmable 30g 11 ms 1 2 sine wave 0 013 in P P 5 55 Hz 4 in 45 See 1260 100 cooling data 0 C to 55 C 40 C to 75 C 85 5 non condensing at lt 30 C 10 000 feet 15 000 feet 2 5 A maximum wit
6. J3 13H NIVHIS OL 35070 SY QW3H ONIMJOT NOLLISOd sour 9 HALLIT NOISIASY LNJHHNO ANY 1100 8020 HJANNN 1HVd TVOVH HLIM A3LLN3QI ONY ATEINSSSV 3718V0 OVE S NOLLOJLOHA NOLLVOIJILNIJI YO4 WALI OM MNIHHS HV3TO HLIM HJAOD FF WALI ONIGNL MNIHHS MOTIJA NO NI MOV A 378M30NI DNISN NMOHS SV S318V9 AJILNJJI SIMENISSV JTAVO I LVHVdIS OML ONIMVIN 4TVH NI 3718V0 JHL Um 1S3L SJSSVd ASSY HALV 910156 JHNOJVOHA 1531 ONISN ASSY ITAVO LSL ONILSAL 30 3Sv3 HOJ SHiVd NI UI 38 OL Suv SYI 0L WALD EMT MNIHHS SNISN NMOHS Sv NOLLWINSNI 318 9 3IVNINHJL SNOLLO3NNOO ONY SLNAWNDISSV LOVINOD HOS LSITSHIM 33S I SLON Astronics Test Systems Optional Assemblies 4 4
7. module does not monitor these operations and does not keep track of the port states on the 1260 114 module in this mode A conceptual view of the register based mode is shown in Figure 3 2 below Read from A24 Address base address 0x401 1260 114 Figure 3 2 Register Based Mode of Operation Astronics Test Systems Since the 1260 01T switch controller does not keep track of port and control register states during the register based mode it is advisable to use either the message based or the register based mode consistently and use the chosen mode exclusively throughout the application program In general the message based mode of operation is easier to use with utility software such as the National Instruments VXI Interactive Control VIC program The message based mode allows the user to send ASCII text commands to the 1260 01T and to read replies from the 1260 01T In addition some features such as synchronous port operation are available only in the message based mode An added benefit of message based operation is that it obviates the need to manually configure control registers on the 1260 114 controlling such things as port data direction since these are handled automatically by the 1260 01T Module Operation 3 3 1260 114 User Manual Publication No 980824 114 Rev A The register based mode provides faster and more direct control of the 1260 114 In this mode direct port and contr
8. 12 Astronics Test Systems Publication No 980824 114 Rev A 1260 114 User Manual Astronics Test Systems Writing to a port location is a straightforward process Setting a bit high in a port register causes the port to output a high logic level on the port pin corresponding to that bit In the case of an open collector version this same operation would cause the pull down transistor to activate It is especially important to realize that a single write operation controls eight separate control lines or output devices simultaneously Therefore if only a single bit change is desired the following process must be observed 1 Read the register first inverting the bit pattern if necessary 2 Mask the appropriate bit with an AND operation and a byte mask with all undesired bits set to a 1 and the desired bit set to a 0 or 1 depending on whether the bit is to be set or cleared in the desired register 3 Write the masked data back into the register As simple as this may seem a number of products reported as faulty and sent back for repair are nothing more than the result of inappropriate register accesses Reading a 1260 114 register has a few details that must also be considered Depending on what version of the 1260 114 is used some registers when read provide data that is inverted from that written to the register in an earlier operation Tables 3 1 through 3 8 indicate whether bit inversion occurs for a
9. Astronics Test Systems Publication No 980824 114 Rev A 1260 114 User Manual Assembly 407664 Connector kit 160 Pin Crimp Rev Date 7 30 98 Revision A Component Description U M Qty Read REF 1 602258 116 CON CAB RCP160C 100S EEA 1 000 2 602258 900 TRMCRP SNP U F26 20G EEA 170 000 Astronics Test Systems Optional Assemblies 4 3 Publication No 980824 114 Rev A 1260 114 User Manual REV A 1 SH 407408 001 DWG NO w ZEJ Nid d EE EE EE EEN S fo g NMOHS JON 3178V0 8 4 MIIA SOTd 8 07022 zla 025022 4 Ca ez La s t fk Lei ZEJNId y oh R SGEN 7558 Reece SEH Bees No e Reese 131800 R 131840 Ra ke Et Gi KOREN ran gt gt mami Reese fo Besse BERRE GH BERRE GH Gah Gah Geh 7 REJ ams I DECH Kai Ve nau fy Reece maan 10080407 s SOTd 091 Reese Reese 4 Je Resse ER Bess v RERA RRRA eeu soe 2 V l YN SO WW Nd av soaz NMOHS LON 3780 VV MIIA a1gISSOd SV LJMOVHA
10. Relief 456673 Additional Manual 980824 114 Astronics Test Systems Specifications 1 13 1260 114 User Manual Publication No 980824 144 Rev A This page was left intentionally blank Specifications 1 14 Astronics Test Systems Publication No 980824 114 Rev A 1260 114 User Manual Chapter 2 INSTALLATION INSTRUCTIONS Unpacking and Inspection Installation Astronics Test Systems 1 Remove the 1260 114 module and inspect it for damage If any damage is apparent inform the carrier immediately Retain shipping carton and packing material for the carriers inspection 2 Verify that the pieces in the package you received contain the correct 1260 114 module option and the 1260 114 Users Manual Notify Customer Support if the module appears damaged in any way Do not attempt to install a damaged module into a VXI chassis 1 The 1260 114 module is shipped in an anti static bag to prevent electrostatic damage to the module Do not remove the module from the anti static bag unless it is in a static controlled area Installation of the 1260 114 Switching Module into a 1260 100 Carrier assembly is described in the Installation section of the 1260 100 Adapt a Switch Carrier Manual Installation Instructions 2 1 1260 114 User Manual Publication No 980824 114 Rev A Module The 1260 114 is a 96 channel 48 channel for HVOC version i S digital I O plug in for the Adapt a Switch Series Its architecture Conf
11. from 7 through 12 in the following pattern 10 11 12 Front View Module Addresses for 7 through 12 Operating Modes Module Operation 3 2 When setting module addresses for Adapt a Switch Carriers and conventional 1260 Series modules be sure that no address is used by more than one plug in or 1260 Series module For instructions on setting module addresses for a conventional 1260 Series module see the label on the side panel of the module The 1260 114 may be operated either in message based mode or in register based mode In the message based mode the 1260 01T switch controller interprets commands sent by the slot 0 controller and determines the appropriate data to send to the control registers of the 1260 114 module If the A24 VXI base address for the 1260 100 Adapt A Switch carrier is assumed to be at 0x804000A for example purposes and the 1260 114 occupies the module 0 slot Figure 3 1 below provides a conceptual view of the message based mode of operation for a read operation on port 1 Astronics Test Systems Publication No 980824 114 Rev A 1260 114 User Manual PC MXI DIG INP 1 1 Read from A24 Address base address 0x401 VXIbus 1260 01T 1260 114 Figure 3 1 Message Based Mode of Operation PC MXI In the register based mode the user writes directly to the port registers on the 1260 114 module The 1260 01T command
12. full rated current run through every path In addition temperatures are typically not run at the rated maximum Using the 25 rule the power dissipated by each plug in should be no more than 8W If all six slots are used simultaneously this would amount to a total dissipation of 48Watts Additionally if fewer plug in modules are used more power may be dissipated by the remaining cards By using a chassis with high cooling capacity such as the 1261B almost any configuration may be realized Specifications 1 9 1260 114 User Manual Publication No 980824 144 Rev A i Z The 1260 114HVOC is a plug in switch module developed for the Introduction 1260 100 Adapt a Switch Carrier It switches 48 open collector High channels at 50V and 1 5 A per channel The 1260 114HVOC Cu rrent Voltage includes the following features Open Collector e Standard Adapt a Switch plug in design providing for ease Version of replacement e Data Driven embedded descriptor allowing immediate use with any Option 01T switch controller regardless of firmware revision level HAAT EG ryverrerr HALIL E F rezana EI ate ay a ECH ji SME wall H AAA IMU NE ss 400d op 88 I 4 HAAL gt ws a 60963 12700 MATTE KEN si NN r H me HE AAA V 2 Lrrverreee wm wal 08 KE Ga o ini H HAL GS I de t HALIL vererrer 8 EZ HAD Te W I eer HAAL H A m HAL kk 2 I 2 gt rrrverey HALTE S CG
13. particular register and whether it occurs in all versions of the 1260 114 or for only select versions The VISA I O library may be used to control the module The VISA function viOut8 is used to write a single 8 bit byte to a control register while viln8 is used to read a single 8 bit byte from the control register The following code example shows the use of viOut8 to update the 1260 114 module Module Operation 3 13 1260 114 User Manual Publication No 980824 114 Rev A 1260 114 Example Code include lt visa h gt This example shows a 1260 01T at logical address 16 and a VXI MXI interface define RI1260 01 DESC VXI 16 For a GPIB VXI interface and a logical address of 77 the descriptor would be GPIB VXI 77 this example shows a 1260 114 with module address 7 port 1 and write data of OxAA define MOD ADDR 114 7 define PORT_NUMBER 1 define DATA ITEM OxAA void example operate 1260 114 void ViUInt8 creg_val ViBusAddress portA_addr offset ViSession hdl1260 VISA handle to the 1260 01T ViSession hdlRM VISA handle to the resource manager ViStatus error VISA error code open the resource manager this must be done once in application program error viOpenDefaultRM amp hd1RM if error lt 0 error handling code goes here
14. power supply pulls up the collector output of the transistor through the external load Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Module Operation 3 9 1260 114 User Manual Publication No 980824 114 Rev A Table 3 5 Control Register 1 Functionality of the 1260 114 Module Register Table Control Register 1 Module Version TTL and CMOS As written to register bits normally read inverted unless external port tri state pin is 0 in which case bit will always read a 1 OC and HVOC Module Operation 3 10 w S IGJOTRAJOIN JOJN OIU AIO N 0O S 5 PILLE LE 2 gt Functionality Description Port A Input Port Port B Input Port Port C Input Port Port D Input Port Port E Input Port Port F Input Port Port G Input Port Port H Input Port sch sch S sch 1 Not Use Port A Output Port Port B Output Port Port C Output Port Port D Output Port Port E Output Port Port F Output Port Port G Output Port Port H Output Port d Not Used Not Used Not Used Not Used Not Used Not Used Not Used Astronics Test Systems Publication No 980824 114 Rev A 1260 114 User Manual Table 3 6 Control Register 2 Functionality of the 1260 114 Module Register Table Control Register 2 Module Version TTL and CMOS As written to register bits 0 3 normally read inverted unless external port
15. solicit guotations from a competitive source or used for manufacture by anyone other than Astronics Test Systems The information herein has been developed at private expense and may only be used for operation and maintenance reference purposes or for purposes of engineering evaluation and incorporation into technical specifications and other documents which specify procurement of products from Astronics Test Systems TRADEMARKS AND SERVICE MARKS All trademarks and service marks used in this document are the property of their respective owners e Racal Instruments Talon Instruments Trig Tek ActivATE Adapt A Switch N GEN and PAWS are trademarks of Astronics Test Systems in the United States DISCLAIMER Buyer acknowledges and agrees that it is responsible for the operation of the goods purchased and should ensure that they are used properly and in accordance with this document and any other instructions provided by Seller Astronics Test Systems products are not specifically designed manufactured or intended to be used as parts assemblies or components in planning construction maintenance or operation of a nuclear facility or in life support or safety critical applications in which the failure of the Astronics Test Systems product could create a situation where personal injury or death could occur Should Buyer purchase Astronics Test Systems product for such unintended application Buyer shall indemnify and hold Astronics Test Systems i
16. then the overall carrier dissipation is approximately 10 W which is well within the cooling available in most commercial VXIbus chassis In practice rarely are more than 25 of the module s channels energized simultaneously and rarely is full rated current run through every path Using the 25 rule the power dissipated by each plug in should be no more than 0 5 W If all six slots are used simultaneously this would amount to a total dissipation of 2 5Watts Additionally if fewer plug in modules are used more power may be dissipated by the remaining cards By using a chassis with high cooling capacity such as the 1261B almost any configuration may be realized Astronics Test Systems Publication No 980824 114 Rev A 1260 114 User Manual Intr ion The 1260 1140C is a plug in switch module developed for the troductio 1260 100 Adapt a Switch Carrier It switches 96 open collector Standard Open channels at 200 mA per channel The 1260 1140C includes the Collector Version following features e Standard Adapt a Switch plug in design providing for ease of replacement e Data Driven embedded descriptor allowing immediate use with any Option 01T switch controller regardless of firmware revision level z ra ef rt ereere prerrrrrer AAA ICH EK 4 JI 00 DH D s Ee veer rr HAAL HILL LZ NW HAAL rr rm 8 MM m SG AAA my JA SS UTE MI lesesal S dh Sg Va H
17. 1260 Series modules are always on odd numbered A24 addresses For port registers the 1260 114 reads and writes to the same location For control registers the 1260 114 writes to one location but reads back from another Table 3 1 provides offsets relative to the base address of the module for all port and control registers of the 1260 114 To obtain the absolute address where data is to be written or read from the base address is added to the offset Base A24 1260 114 Address offset absolute address So for our example base A24 address computed earlier the following absolute addresses would apply for the operations indicated 205C01 Port 0 read or written at this location 205019 Control Register 1 written at this location 205E03 Control Register 1 read at this location Before explaining the particulars of reading and writing to port and control registers it is necessary to understand how the registers interact with the 1260 114 Table 3 2 provides a detailed explanation of each register and how it interacts with the 1260 114 module Astronics Test Systems Publication No 980824 114 Rev A 1260 114 User Manual Table 3 1 Register Offset Addresses of the 1260 114 Module Register Register Offsets to Add to Base Module Address Name Write Location hexadecimal Read Location hexadecimal Port A Port 0 0x01 0x01 Port B Port 1 0x03 0x03 Port C Port 2 0x05 0x05 P
18. A sTRONICS TEST SYSTEMS RACAL INSTRUMENTS 1260 114 HIGH DENSITY DIGITAL UO PLUG IN Publication No 980824 114 Rev A Astronics Test Systems Inc 4 Goodyear Irvine CA 92618 Tel 800 722 2528 949 859 8999 Fax 949 859 7139 atsinfo astronics com atssales astronics com atshelpdeskQastronics com http www astronicstestsystems com Copyright 1998 by Astronics Test Systems Inc Printed in the United States of America All rights reserved This book or parts thereof may not be reproduced in any form without written permission of the publisher THANK YOU FOR PURCHASING THIS ASTRONICS TEST SYSTEMS PRODUCT For this product or any other Astronics Test Systems product that incorporates software drivers you may access our web site to verify and or download the latest driver versions The web address for driver downloads is http Awww astronicstestsystems com support downloads If you have any questions about software driver downloads or our privacy policy please contact us at atsinfo astronics com WARRANTY STATEMENT All Astronics Test Systems products are designed to exacting standards and manufactured in full compliance to our AS9100 Quality Management System processes This warranty does not apply to defects resulting from any modification s of any product or part without Astronics Test Systems express written consent or misuse of any product or part The warranty also does not apply to fuses software non rech
19. D 12 B3 D3 F3 GND GND 13 B4 D4 F4 Hi Z Fly G Hi Z Fly H 14 B5 D5 F5 GND GND 15 B6 D6 F6 GND GND 16 B7 D7 F7 GND GND 17 GO GND 1 10 GND t KO GND Hi Z Fly Hi Z Fly J 18 G1 GND 11 GND K1 GND GND GND 19 G2 GND I2 GND K2 GND t GND GND 20 G3 GND I3 GND K3 GND GND GND 21 G4 GND 14 GND K4 GND Hi Z Fly K Hi Z Fly L 22 G5 GND I5 GND K5 GND GND GND 23 G6 GND 16 GND t K6 GND GND GND 24 G7 GND IZ GND t K7 GND GND GND 25 HO GND f JO GND LO GND EXTBUSY EXTCLKIN 26 H1 GND J1 GND L1 GND GND GND 27 H2 GND J2 GND L2 GND GND GND 28 H3 GND J3 GND L3 GND GND GND 29 H4 GND J4 GND L4 GND GND GND 30 H5 GND J5 GND L5 GND GND GND 31 H6 GND J6 GND L6 GND GND GND 32 H7 GND J7 GND L7 GND GND GND t For the 1260 114HVOC version these pins are tied to ground For the 1260 114TTL and 1260 114CMOS these pins act as external tri state inputs active low for the indicated ports For the 1260 1140C and 1260 114HVOG these pins connect to the fly back protection diodes assigned to the indicated ports Pins for Ports G L are not connected in the 1260 114HVOC version Installation Instructions 2 4 Astronics Test Systems Publication No 980824 114 Rev A 1260 114 User Manual
20. OUWALD vrrreerrer de A min emi mleli Figure 1 3 The 1260 1140C Astronics Test Systems Specifications 1 7 1260 114 User Manual Specifications Standard Open Collector Specifications 1 8 Max Chan Input Voltage Chan Output Current High Output Voltage Max Low Output Voltage Available I O Channels Channel Synchronization Synchronous Trigger Handshake Polarity Synchronous Busy Handshake Polarity Shock Vibration Bench Handling Cooling Temperature Operating Non operating Relative Humidity Altitude Operating Non operating Power Requirements 5 VDC Weight Mean Time Between Failures MTBF Mean Time to Repair Publication No 980824 144 Rev A 32 VDC 200 mA maximum 5 lt Voh lt 32 VDC lt 1 5 VDC 200 mA 96 open collector channels Asynchronous Synchronous or Mixed User Programmable User Programmable 30g 11 ms 1 2 sine wave 0 013 in P P 5 55 Hz 4 in 45 See 1260 100 cooling data 0 C to 55 C 40 C to 75 C 85 5 non condensing at lt 30 C 10 000 feet 15 000 feet 0 5 A maximum 6 oz 0 21 kg gt 100 000 hours MIL HDBK 217E lt 5 minutes MTTR Astronics Test Systems Publication No 980824 114 Rev A 1260 114 User Manual Power Dissipation Standard Open Collector Astronics Test Systems The cooling of the Adapt a Switch carrier is dependent upon the chassis into which it is installed The c
21. Spe iticationse GMOS TE sise ei GEN Power Dissipation OMOS TTE EE Introduction Standard Open Collector Version ssssssseeeesssseernrrnrtrsstrenrrrrnrrssereserrrrnrnnnesnet Specifications Standard eler UE Power Dissipation Standard Open Collector nn Introduction High Current Voltage Open Collector Version 1 Specifications High Current Voltage Open Collector ssnsssesssesennrrneesserrenerrnnnrssrrrrnernnee nn 1 Power Dissipation High Current Voltage Open Collector ssssssssserrnneesseeenrrrrrrsserrrrerrn 1 About MI BE erone bere o o eki ee deeg rege 1 Ordering IN ONA ON aa ea ae Osean a Ee ene 1 EE TR INSTALLATION INSTRUCTIONS iv innse deepens aden da Galea ae Ga irer Unpacking and Inspection Luvuadsse aaa ENEE Dee Nee eee Installation RAGE Module ee Wie uration vaner Seeds From Panel Gomes Astronics Test Systems 1260 114 User Manual Publication No 980824 114 Rev A Ee RE e TEE 2 5 Ee E 3 1 MODULE OPERATION eee ed a aa ia 3 1 Setting the Module Address sise aii stuns aa ei AA ARE HA PEDALE Pa Ek Pla k EEA KAVE AKA Oki plave iki laj ali 3 1 Rene BEE 3 2 Operating In Message Based Mode AANEREN 3 4 Port Descriptors For The 1260 1114 3 4 Reply To The MOD LIST Gommand uueuasesmeormnnmrvnm kia obi ki Sege es 3 5 Operating The 1260 114 in Register Based Mode AAA 3 5 1260 114 Example Code EE 3 14 DES 4 1 OPTIONAL ASSEMBLIES guarder erre Rn 4 1 ii A
22. The 160 Pin Cable Assembly uses 24 AWG cable with crimp pins to mate with the 1260 114 The other cable end is un terminated Refer to Table 2 1 for channel to pin mapping information Installation Instructions 2 5 1260 114 User Manual Publication No 980824 114 Rev A This page was left intentionally blank Installation Instructions 2 6 Astronics Test Systems Publication No 980824 114 Rev A 1260 114 User Manual Chapter 3 MODULE OPERATION Setting the The Option 01T switch controller identifies each Adapt a Switch plug in or conventional 1260 Series module by a module address Module Address that is unique to that module The module address is a number from 1 through 12 inclusive The module address assigned to the 1260 114 depends on the carrier slot into which the 1260 114 is inserted and on the position of the logical address DIP switch on the carrier side panel The switch has two settings e 1 6 closed When the switch is set to this position the module addresses of the plug ins in the 1260 100 Carrier are from 1 through 6 The module with address 1 is in the left slot of the top row The plug ins are addressed in the following pattern Front View Module Addresses for 1 through 6 Astronics Test Systems Module Operation 3 1 1260 114 User Manual Publication No 980824 114 Rev A e 7 12 open When the switch is set to this position the module addresses of the plug ins in the 1260 100 Carrier are
23. ality of the 1260 114 Module 3 12 Astronics Test Systems iii 1260 114 User Manual Publication No 980824 114 Rev A This page was left intentionally blank iv Astronics Test Systems Publication No 980824 114 Rev A 1260 114 User Manual DOCUMENT CHANGE HISTORY Revision Date Description of Change Revised per EO 29566 Revised format to current standards Company A 02 10 09 name revised throughout manual Manual now revision letter controlled Added Document Change History Page v Back of cover sheet Revised Warranty Statement Return of Product Proprietary Notice and Disclaimer to current standards Removed No change 03 19 09 Reshipment Instructions in Chap 2 1 and removed Chap 5 Information Now appears in first 2 sheets behind cover sheet Updated table of contents to reflect changes made Astronics Test Systems v 1260 114 User Manual vi Publication No 980824 114 Rev A This page was left intentionally blank Astronics Test Systems Publication No 980824 114 Rev A 1260 114 User Manual Chapter 1 SPECIFICATIONS The 1260 114TTL is a plug in switch module developed for the Introducti ons 1260 100 Adapt a Switch Carrier It switches 96 digital channels TTL Version that are compliant to both level and current specifications for TTL logic The 1260 114TTL includes the following features e Standard Adapt a Switch
24. argeable batteries damage from battery leakage or problems arising from normal wear such as mechanical relay life or failure to follow instructions This warranty is in lieu of all other warranties expressed or implied including any implied warranty of merchantability or fitness for a particular use The remedies provided herein are buyer s sole and exclusive remedies For the specific terms of your standard warranty contact Customer Support Please have the following information available to facilitate service 1 Product serial number 2 Product model number 3 Your company and contact information You may contact Customer Support by E Mail atshelpdesk astronics com Telephone 1 800 722 3262 USA Fax 1 949 859 7139 USA RETURN OF PRODUCT Authorization is reguired from Astronics Test Systems before you send us your product or sub assembly for service or calibration Call or contact Customer Support at 1 800 722 3262 or 1 949 859 8999 or via fax at 1 949 859 7139 We can also be reached at atshelodesk astronics com If the original packing material is unavailable ship the product or sub assembly in an ESD shielding bag and use appropriate packing materials to surround and protect the product PROPRIETARY NOTICE This document and the technical data herein disclosed are proprietary to Astronics Test Systems and shall not without express written permission of Astronics Test Systems be used in whole or in part to
25. arrier can nominally dissipate approximately 100 W Even with all channels driven to maximum outputs up to six 1260 1140C plug ins may be used together in a 1260 100 without exceeding the maximum allowable power dissipation of the carrier If the 1260 1140C will be used in conjunction with other cards the 1260 1140C dissipation should be computed and summed with the total worst case dissipation of the remaining modules For example a 1260 1140C module would dissipate the following energy Quiescent power dissipation 0 75W maximum Channel dissipation Vol current 96 channels energized current path resistance 96 channels energized Total Power Dissipation Quiescent Channel Assuming all 96 channels are sinking a maximum current of 200 mA and a path resistance of 0 5 Q Total power dissipation 1 5 0 200 A 96 0 200 A 0 5 Q 96 0 75W 31 5 W at 55 C This exceeds the acceptable power dissipation for an individual plug in module If five additional modules are likewise loaded then the overall carrier dissipation is approximately 188 W which is above the typical cooling capabilities of the carrier and most chassises in a two slot configuration Therefore using a fully loaded Adapt a Switch carrier with these cards operating at the maximum extreme is not permissible In practice however rarely are more than 25 of the module s channels energized simultaneously and rarely is
26. e address gt lt first port gt lt last port gt The following examples illustrate the use of the port descriptors for Astronics Test Systems Publication No 980824 114 Rev A 1260 114 User Manual Reply To The MOD LIST Command Operating The 1260 114 in Register Based Mode Astronics Test Systems the 1260 114 DIG OUTP 8 0 234 Writes 234d to port 0 at module address 8 DIG INP 3 1 Reads port 1 at module address 3 The 1260 01T returns a reply to the MOD LIST command This reply is unique for each different 1260 series switch module The syntax for the reply is lt module address gt lt module specific identification string gt The lt module specific identification string gt for the 1260 114 depends on the version For the TTL CMOS standard open collector and high voltage current open collector the strings are respectively 1260 114TTL DIGITAL INPUT OUTPUT TTL MODULE 1260 114CM DIGITAL INPUT OUTPUT CMOS MODULE 1260 1140C DIGITAL INPUT OUTPUT OPEN COLLECTOR MODULE 1260 114HV DIGITAL INPUT OUTPUT HIGH VOLTAGE OPEN COLLECTOR MODULE So for a 1260 114TTL whose lt module address gt is set to 8 the reply to this query would be 8 1260 114TTL DIGITAL INPUT OUTPUT TTL MODULE In register based mode the 1260 114 is operated by directly writing and reading to p
27. gister 3 Functionality of the 1260 114 Module Register Table Control Register 3 Module Version Bit Functionality Description 0 0 Disable Interrupts 1 Enable Interrupts 1 0 Ext Busy Active Low 1 Ext Busy Active High 2 0 Ext Clock Active Edge 1 Ext Clock Active Edge 3 0 Reserved 1 Reserved TTL CMOS OC and 4 0 Reserved 1 Reserved HVOC 5 0 Ext Trigger Not Active 1 Ext Trigger Active Read Read Only Only 6 0 Interrupt Service Required 1 Interrupt Service Not Read Only Required Read Only 7 0 Module Is Asserting 1 Module Is Not Asserting Interrupt Line Read Only Interrupt Line Read Only Table 3 8 EPROM Descriptor Functionality of the 1260 114 Module Register Table EPROM Descriptor Register Module Version Functionality Description This register each time read advances a memory pointer to the next memory location in an EPROM To reset this pointer to the beginning simply read the ID register and the memory pointer resets to zero The descriptor register contains a long string of data typically used by the Adapt a Switch carrier for configuration purposes Additionally this data has the card identification string for the specific type of card i e 1260 114TTL or 1260 114CMOS These identification strings are located at EPROM memory locations 0x23 0x34 w pr TTL CMOS OG and HVOC AJO G JRJOJNJa jo Module Operation 3
28. h all channels sourcing maximum current 6 oz 0 21 kg gt 100 000 hours MIL HDBK 217E lt 5 minutes MTTR Astronics Test Systems Publication No 980824 114 Rev A 1260 114 User Manual Power Dissipation TTL Astronics Test Systems The cooling of the Adapt a Switch carrier is dependent upon the chassis into which it is installed The carrier can nominally dissipate approximately 100 W Even with all channels driven to maximum outputs up to six 1260 114 TTL plug ins may be used together in a 1260 100 without exceeding the maximum allowable power dissipation of the carrier If the 1260 114TTL will be used in conjunction with other cards the 1260 114TTL dissipation should be computed and summed with the total worst case dissipation of the remaining modules For example a 1260 114TTL module would dissipate the following energy Quiescent power dissipation 4 25W maximum Channel dissipation Vec 2 25 current 96 channels energized current path resistance 96 channels energized Total Power Dissipation Quiescent Channel Assuming all 96 channels are sourcing a maximum current of 30 mA and a path resistance of 19 Total power dissipation 5 VDC 2 25 0 030 A 96 0 030 A 1 Q 96 4 25 W 12 25 W at 55 C This is acceptable power dissipation for an individual plug in module If five additional modules are likewise loaded then the overall carrier dissipat
29. ier can nominally dissipate approximately 100 W Even with all channels driven to maximum outputs up to six 1260 114 TTLHVOC plug ins may be used together in a 1260 100 without exceeding the maximum allowable power dissipation of the carrier If the 1260 114HVOC will be used in conjunction with other cards the 1260 114HVOC dissipation should be computed and summed with the total worst case dissipation of the remaining modules For example a 1260 114HVOC module would dissipate the following energy Quiescent power dissipation 0 75W maximum Channel dissipation Rds current 48 channels energized current path resistance 48 channels energized Total Power Dissipation Quiescent Channel Assuming all 48 channels are sinking a maximum current of 1 5 A and a path resistance of 0 030 Q Total power dissipation 1 5 A 0 060 O 48 1 5 A 0 070 Q 48 0 75W 15 W at 55 C This is acceptable power dissipation for an individual plug in module If five additional modules are likewise loaded then the overall carrier dissipation is approximately 89 W which is well within the cooling available in most commercial VXIbus chassis In practice rarely are more than 25 of the module s channels energized simultaneously and rarely is full rated current run through every path Using the 25 rule the power dissipated by each plug in should be no more than 3 75 W If all six slots are used simu
30. iguration permits any 8 bit port to be defined through software as in input or output in either asynchronous or synchronous operational mode For the open collector versions the ports can be used as inputs by setting the transistors in an off state The 1260 114 has one 160 pin front panel connector labeled Front Panel J200 It is a 160 pin modified DIN style with 0 025 sguare posts Connectors as pins It has one pin for each input and one for each output See Figure 2 1 for pin numbering Table 2 1 shows the mapping of channel numbers to connector pins Information about available mating connectors is provided immediately after Table 2 1 Installation Instructions 2 2 Astronics Test Systems Publication No 980824 114 Rev A 1260 114 User Manual sch MM GO P OO OO AJ o Figure 2 1 Front Panel Connector Pin Numbering Astronics Test Systems Installation Instructions 2 3 1260 114 User Manual Publication No 980824 114 Rev A Table 2 1 1260 114 Front Panel Connections Connector Pin Descriptions Pin Row A Row B Row C Row D Row E 1 AO CO EO Hi Z Fly A Hi Z Fly B 2 A1 C1 E1 GND GND 3 A2 C2 E2 GND GND 4 A3 C3 E3 GND GND 5 A4 C4 E4 Hi Z Fly C Hi Z Fly D 6 A5 C5 E5 GND GND 7 A6 C6 E6 GND GND 8 A7 C7 E7 GND GND 9 BO DO FO Hi Z Fly E Hi Z Fly F 10 B1 D1 F1 GND GND 11 B2 D2 F2 GND GN
31. ion is approximately 74 W which is well within the cooling available in most commercial VXIbus chassis In practice rarely are more than 25 of the module s channels energized simultaneously and rarely is full rated current run through every path Using the 25 rule the power dissipated by each plug in should be no more than 3 W If all six slots are used simultaneously this would amount to a total dissipation of 18Watts Additionally if fewer plug in modules are used more power may be dissipated by the remaining cards By using a chassis with high cooling capacity such as the 1261B almost any configuration may be realized Specifications 1 3 1260 114 User Manual Publication No 980824 144 Rev A i The 1260 114CMOS is a plug in switch module developed for the Introduction 1260 100 Adapt a Switch Carrier It switches 96 digital channels CMOS TTL that are compliant to both level and current specifications for Version CMOS The 1260 114CMOS is also TTL level compliant but at a reduced sink and source current For applications requiring TTL level compliance at higher currents the 1260 114TTL should be selected The 1260 114CMOS includes the following features e Standard Adapt a Switch plug in design providing for ease of replacement e Data Driven embedded descriptor allowing immediate use with any Option 01T switch controller regardless of firmware revision level WAR r Ss ta gt HUE IL Sr a a
32. ltaneously this would amount to a total dissipation of about 23Watts Additionally if fewer plug in modules are used more power may be dissipated by the remaining cards By using a chassis with high cooling capacity such as the 1261B almost any configuration may be realized Astronics Test Systems Publication No 980824 114 Rev A About MTBF The 1260 114 MTBF is 783 668 hours calculated in accordance 1260 114 User Manual with MIL HDBK 217E Ordering Listed below are part numbers for both the 1260 114 switch d module and available mating connector accessories Each 1260 Information 114 uses a single mating connector ITEM DESCRIPTION PART 1260 114TTL Switch Module Switch Module 96 Channel TTL Digital 407661 001 Output Consists of P N 405145 001 PCB Assy P N 980824 114 Manual 1260 114CMOS Switch Module Switch Module 96 Channel CMOS 407661 002 Digital Output Consists of P N 405145 002 PCB Assy P N 980824 114 Manual 1260 1140C Switch Module Switch Module 96 Channel Standard 407661 003 Open Collector Output Consists of P N 405145 003 PCB Assy P N 980824 114 Manual 1260 114HVOC Switch Module Switch Module 48 Channel High 407661 004 Current Voltage Open Collector Output Consists of P N 405145 004 PCB Assy P N 980824 114 Manual 160 pin Mating Connector 160 Pin Conn Kit with pins 407664 Cable Assy 6ft Sleeved 160 Pin Cable Assy 6 Ft 24 AWG 407408 001 Connector Bracket Bracket Strain
33. ol register operations are processed in less than 9 microseconds not counting software overhead inherent in I O libraries such as VISA For further information about message based vs register based comparisons consult the 1260 01T User s Manual for further details Operating In Message Based Mode Port Descriptors For The 1260 114 Module Operation 3 4 The standard 1260 01T commands are used to operate the 1260 114 module These commands are described in the 1260 01T User s Manual Each 1260 01T port command uses a port descriptor also referred to as a channel descriptor in some documentation to select the port s of interest The syntax for a port descriptor is the same for all 1260 series modules In general the following syntax is used to select a single port lt module address gt lt port gt Where e lt module address gt is the address of the 1260 114 module This is a number is in the range from 1 through 12 inclusive e lt port gt is the 1260 114 port to operate This is a number in the range from 0 through 11 inclusive for the 1260 114TTL 114CMOS and 114OC versions and 0 through 5 inclusive for the 1260 114HVOC Multiple individual ports may be specified using the following port descriptor syntax lt module address gt lt portl gt lt port2 gt poe lt portN gt data A range of ports may be specified using the following channel descriptor syntax lt modul
34. ort D Port 3 0x07 0x07 Port E Port 4 0x09 0x09 Port F Port 5 0x0B 0x0B Port G Port 6 0x0D 0x0D Port H Port 7 OxOF OxOF Port I Port 8 Ox11 Ox11 Port J Port 9 0x13 0x13 Port K Port 10 0x15 0x15 Port L Port 11 0x17 0x17 ID Read Only 0x201 Control Register 1 0x19 0x203 Control Register 2 0x1B 0x205 Control Register 3 Ox1D 0x207 EPROM Descriptor Read Only 0x301 Astronics Test Systems Module Operation 3 7 1260 114 User Manual Publication No 980824 114 Rev A Table 3 2 ID Register Functionality of the 1260 114 Register Table ID Register Module Version Bit Functionality Description 0 ke 2 TTL CMOS OC and 3 Always Reads 0x00 HVOC 4 Read Only 5 E 7 Table 3 3 Ports A F Register Functionality of the 1260 114 Module Register Table Ports A F w Module Version Functionality Description Each port is an 8 bit register where the lowest order bit corresponds to lowest order connector pin of the port group A 1 written to any bit drives the appropriate output driver high while a 0 drives the appropriate output driver low If a port is read the data will appear identical to what was written to the register TTL and CMOS Each port is an 8 bit register where the lowest order bit corresponds to lowest order connector pin of the port group A 1 written to any bit enables the appropriate open collector output tran
35. ort and control registers on the 1260 114 module To access the various registers the following details must be assembled to generate an absolute address that can be wrote or read from The port and control registers are located in the VXlbus A24 Address Space The A24 address for a port or control register depends on 1 The A24 Address Offset assigned to the 1260 01T module by the Resource Manager program The Resource Manager program is provided by the VXIbus slot 0 controller vendor The A24 Address Offset is placed into the Offset Register of the 1260 01T by the Resource Manager 2 The lt module address gt of the 1260 114 module This is a Module Operation 3 5 1260 114 User Manual Module Operation 3 6 Publication No 980824 114 Rev A value in the range from 1 and 12 inclusive 3 The 1260 114 port or control register to be written to or read from Each register on the 1260 114 has a unigue offset from the base address The base A24 address for the 1260 114 module may be calculated by A24 Offset of the 1260 01T 1024 x Module Address of 1260 114 The A24 address offset is usually expressed in hexadecimal A typical value of 20400015 is used in the examples that follow A 1260 114 with a module address of 7 would have the base A24 address computed as follows Base A24 Address of 1260 114 20400016 40016 X 710 205C00 6 The port and control registers for Adapt a Switch plug ins and conventional
36. sistor while a 0 disables the appropriate open collector output transistor If a port is read the data will appear inverted from what was written to the register assuming the external power supply pulls up the collector output of the transistor through the external load OC and HVOC AJOJGJ RJO PO JOJHJOJCUJR OI jo Module Operation 3 8 Astronics Test Systems Publication No 980824 114 Rev A 1260 114 User Manual Table 3 4 Ports G L Register Functionality of the 1260 114 Module Register Table Ports G L Module Version TTL and CMOS OC HVOC 4 5 MER 7 MURE rele 2 3 4 Astronics Test Systems Functionality Description Each port is an 8 bit register where the lowest order bit corresponds to lowest order connector pin of the port group A 1 written to any bit drives the appropriate output driver high while a 0 drives the appropriate output driver low If a port is read the data will appear identical to what was written to the register Each port is an 8 bit register where the lowest order bit corresponds to lowest order connector pin of the port group A 1 TC a written to any bit enables the appropriate open collector output transistor while a disables the appropriate open collector output transistor If a port is read the data will appear inverted from what was written to the register assuming the external
37. stronics Test Systems Publication No 980824 114 Rev A 1260 114 User Manual List of Figures Figure 1 1 The 126021 TAT EE 1 1 Figure 1 2 The 1260 114CM0OS rrrennnrnnrronnnrnnrrnnnnrnnrrnnnnrnnrnnnsnrnnrnnnnennennrnennnrnnrnensnrnnrneesesnnrnensee 1 4 Figure 1 3 Th 1260 11 AO Gans ae denne ene decantation 1 7 Fig r 1 4 NEE e e Le 1 10 Figure 2 1 Front Panel Connector Pin Numbering nn 2 3 Figure 2 2 Block DAGEN aa cece eens SN o ae eb ess STR 2 5 Figure 3 1 Message Based Mode of Operation ane 3 3 Figure 3 2 Register Based Mode of Operation 3 3 List of Tables Table 2 1 1260 114 Front Panel Connechons ee 2 4 Table 3 1 Register Offset Addresses of the 1260 114 Module 3 7 Table 3 2 ID Register Functionality of the 1260 7114 EEN 3 8 Table 3 3 Ports A F Register Functionality of the 1260 114 Module 3 8 Table 3 4 Ports G L Register Functionality of the 1260 114 Module 3 9 Table 3 5 Control Register 1 Functionality of the 1260 114 Module 3 10 Table 3 6 Control Register 2 Functionality of the 1260 114 Module 3 11 Table 3 7 Control Register 3 Functionality of the 1260 114 Module 3 12 Table 3 8 EPROM Descriptor Function
38. th all channels driven to maximum outputs up to six 1260 114CMOS plug ins may be used together in a 1260 100 without exceeding the maximum allowable power dissipation of the carrier While the cooling of the Adapt a Switch carrier is dependent upon the chassis into which it is installed the carrier can normally dissipate approximately 100 W Care must be taken then in the selection and loading of the plug in modules used in the carrier With the 1260 114CMOS it is not possible to fully load the carrier with these cards drive every channel at full load and exceed the power dissipation capabilities of the Adapt a Switch carrier If the 1260 114CMOS will be used in conjunction with other cards the 1260 114CMOS dissipation should be computed and summed with the total worst case dissipation of the remaining modules For example a 1260 114CMOS module would dissipate the following energy Quiescent power dissipation 0 75W maximum Channel dissipation Vec 3 8 current 96 channels energized current path resistance 96 channels energized Total Power Dissipation Quiescent Channel Assuming all 96 channels are sourcing a maximum current of 8 mA and a path resistance of 10 Total power dissipation 5 VDC 3 8 0 008 A 96 0 008 A 1 O 96 0 75 W 1 7 W at 55 C This is acceptable power dissipation for an individual plug in module If five additional modules are likewise loaded
39. tri state pin is 0 in which case bit will always read a 1 Functionality Description O Port Input Port 1 Port Output Port 0 Port J Input Port 1 Port J Output Port 0 Port K Input Port 1 Port K Output Port 0 Port L Input Port 1 Port L Output Port Bits 4 7 control whether ports A L act in synchronous or asynchronous mode Bits 4 7 enable synchronous mode for the port specified and all lower order ports while higher ports are set to asynchronous mode i e 0x0 all ports asynchronous OxB all ports synchronous 0x3 ports A C synchronous OC Not Used Not Used Not Used Not Used Bits 4 7 control whether ports A L act in synchronous or asynchronous mode Bits 4 7 enable synchronous mode for the port specified and all lower order ports while higher ports are set to asynchronous mode i e 0x0 all ports asynchronous OxB all ports synchronous 0x3 ports A C synchronous HVOC Not Used Not Used Not Used Not Used Astronics Test Systems Bits 4 7 control whether ports A F act in synchronous or asynchronous mode Bits 4 7 enable synchronous mode for the port specified and all lower order ports while higher ports are set to asynchronous mode i e 0x0 all ports asynchronous 0x6 all ports synchronous 0x3 ports A C synchronous Module Operation 3 11 1260 114 User Manual Publication No 980824 114 Rev A Table 3 7 Control Re
40. ts officers employees subsidiaries affiliates and distributors harmless against all claims arising out of aclaim for personal injury or death associated with such unintended use FOR YOUR SAFETY Before undertaking any troubleshooting maintenance or exploratory procedure read carefully the WARNINGS and CAUTION notices A CAUTION This eguipment contains voltage hazardous to RISK OF ELECTRICAL SHOCK human life and safety and is capable of inflicting DO NOT OPEN personal injury If this instrument is to be powered from the AC line mains through an autotransformer ensure the common connector is connected to the neutral earth pole of the power supply Before operating the unit ensure the conductor green wire is connected to the ground earth conductor of the power outlet Do not use a two conductor extension cord or a three prong two prong adapter This will defeat the protective feature of the third conductor in the power cord i Maintenance and calibration procedures sometimes call for operation of the unit with CAUTION power applied and protective covers removed Read the procedures and heed warnings gjeng to avoid live circuit points Before operating this instrument 1 Ensure the proper fuse is in place for the power source to operate 2 Ensure all other devices connected to or in proximity to this instrument are properly grounded or connected to the protective third wire earth ground If the instr
41. ument fails to operate satisfactorily shows visible damage has been stored under unfavorable conditions has sustained stress Do not operate until performance is checked by qualified personnel EC Declaration of Conformity Astronics Test Systems 4 Goodyear Irvine CA 92618 declare under sole responsibility that the 1260 114TTL Digital UO Module P N 407661 001 1260 114MOS Digital UO Module P N 407661 002 1260 1140C Digital UO Module P N 407661 003 1260 114HVOC Digital OModule P N 407661 004 They conform to the following Product Specifications Safety EN61010 1 1993 A2 1995 EMC EN61326 1997 A1 1998 Supplementary Information The above specifications are met when the product is installed in an Astronics Test Systems certified enclosure with faceplates installed over all unused slots as applicable The product herewith complies with the requirements of the Low Voltage Directive 73 23 EEC and the EMC Directive 89 336 EEC modified by 93 68 EEC Irvine CA November 06 2002 EG ngineering Director This page was left intentionally blank Publication No 980824 114 Rev A 1260 114 User Manual Table of Contents EE ON IN SOS SO SPECIFICATIONS siva ere o a a aire ad ee Adal litrodu tioni TEL NES HTG Specifications TILL aker eee eee eten Power Dissipation PUL sina a ka ee ie ANG pa rike eder be liki na niende kn senket Introduction CMOS TTL Versions casi Sat je Poka obo jale ea okol a ee bei le
Download Pdf Manuals
Related Search