appendix a an1062: using the qspi for analog data aquisition
Contents
1. O gt O REQUEST A D CHANNEL 4 GET CHAN REQUEST A D CHANNEL 6 GET CHAN REQUEST A D CHANNEL 3 GET CHAN REQUEST A D CHANNEL 4 GET CHAN REQUEST A D CHANNEL 6 GET CHAN REQUEST A D CHANNEL 3 GET CHAN REQUEST A D CHANNEL 4 GET CHAN TRANSFER TO PORT REQUEST A D CHANNEL 6 GET CHA REQUEST A D CHANNEL 3 GET CHA REQUEST A D CHANNEL 4 GET CHA REQUEST A D CHANNEL 6 GET CHA REQUEST A D CHANNEL 3 GET CHA REQUEST A D CHANNEL 4 GET CHA REQUEST A D CHANNEL 6 GET CHA REQUEST A D CHANNEL 3 GET CHA FFFD4E 8 BIT NO DELAYS PCS1 0 w NEL 3 RESULT NEL 4 RESULT NEL 6 RESULT NEL 3 RESULT NEL 4 RESULT NEL 6 RESULT NEL 3 RESULT NEL 4 RESULT NEL 6 RESULT NEL 3 RESULT NEL 4 RESULT NEL 6 RESULT NEL 3 RESULT NEL 4 RESULT NEL 6 RESULT _ RECEIVE RAM ADDR CONTENTS FFFD00 1 A D CHANNEL 6 RESULT FFFD02 3 A D CHANNEL 3 RESULT FFFD04 5 A D CHANNEL 4 RESULT X x X x X x FFFDIC D PORT INPUT DATA 0 FFFD1E F LAST A D CHANNEL DATA NOTE WRTO 0 WREN 1 INITIAL NEWQP F ENDQP 2 r PRIMARY QUEUE SUBQUEUE r PRIMARY QUEUE Figure A 11 Example Subqueue Structure and Operation Flow MOTOROLA AN1062 USING THE QSPI FOR ANALOG DATA AQUISITION QSM A 18 REFERENCE MANUAL2. 11 channel A D converters They are designed for connection to a microcomputer system with channel selection and conversion results being conveyed through a serial inter face port They require only 14 mW from a single 5 V power supply and yield 1 LSB accuracy over the 40 to 125 C range The reference voltage can be anywhere from 2 5 V to Vpp and the analog input voltage may range from Vss to The MC145050 and MC145051 are 10 bit converters whereas the MC145040 and MC145041 are 8 bit converters The MC145040 and MC145050 use external clock sources to perform the conversion the MC 145041 and MC145051 use internal RC os cillators The parts using external oscillators guarantee faster conversion rates be cause internal oscillator frequency must be limited to guarantee reasonable yield despite manufacturing tolerances The remaining A D converter description refers specifically to the MC145050 since it is the converter used in the examples presented QSM AN1062 USING THE QSPI FOR ANALOG DATA AQUISITION MOTOROLA REFERENCE MANUAL A 1 Figure A 1 shows the pinout of the 145050 It has 13 analog pins consisting of 11 analog inputs labeled ANO AN 1 1 and two voltage reference inputs labeled Vag an alog ground and positive reference voltage Power is supplied through the Vss and Vpp pins and is a nominal 5 V The MC145050 requires an external clock to be supplied on the A D CLK pin to regulate the data conversion Chan
3. Motorola Inc 1990 4 10 Bit A D Converters with Serial Interface MC145050 D Motorola Inc 1990 MOTOROLA AN1062 USING THE QSPI FOR ANALOG DATA AQUISITION QSM A 12 REFERENCE MANUAL 00000080 00000040 00000020 00000010 00000008 00000004 00000002 00000001 00000008 00000004 00000002 00000001 00008000 00000400 00008000 00000100 00004000 00000100 00000080 fffffcl4 fffffc18 fffffclc fffffclf 00000008 0000000F 0000000 00080f0E KOK ROK RK RK RK RK RK RK RK RK RK RK KK KK KK RK KK KK KK RK KK k k KKK KKK KK KK KK KK KK KK KK KK KK KK KKK KKK KK KKK KOK ROK RK RK RK kk RK KK RK RK RK RK RK KK RK RK RK KK KK RK RK KK KK KK KK KK KK KK KK KK KK KK KK KK KK KK KKK KKK KKK Example showing use of to control 3 A D conversions All timing numbers assume system clock frequency of 16 000 MHz ck Ck k k k k k k k k k k k k k k kk k k k ck ck ck k k k ck ck ck k ck k ck k k k k k k k k k k k ck k k k k k k k k k k FRR k k k k k k k k k k k k k k k k k k k k k k k k k k k k k QUA TES KOK KK RK RK RK RK RK RK RK RK RK RK RK RK KK ck ck ckck ck ck ckck ck ck ckck ck ck ckck ck ck ckck ck ck ckck ck ck ckck ck ck ckck ck ck ckck ck ck ckckckckckckckckck kk ok X okkck kx CONT BITSE DT DSCK PCS3 PCS2 51 PCSO REGCSO SCK MOSI MISO MSTR BITS SPE DSCKL WREN ENDO SPIF KERRAK QPDRW SPCRO SPCR2 SPSR KKK QPDR
4. QSPI to Control A D Conversions 2 MHz A D Sheet 3 of 4 QSM AN1062 USING THE QSPI FOR ANALOG DATA AQUISITION MOTOROLA REFERENCE MANUAL A 15 0000504C 6146 BSR B LOPRESS generate fuel pressure warning 0000504C 600C BRA B CHKTEMP speeds up interrupt service routine 00005050 303C 0145 CHKRCV MOVE W 325 D0 constant for recovered fuel pressure 00005054 B078 FDOO CMP W FUELPSI DO test if A D pressure result is above minimum 00005058 6202 BHI B CHKTEMP 0000505A 6138 BSR B PRESSOK cancel fuel pressure warning The following code segment will control x a temperature using a 5 count deadband 0000505c 3038 4000 CHKTEMP MOVE W SETPT DO get temperature setpoint 00005060 5840 SUBO W 5 D0 compute lower threshold 00005062 8078 FD02 CMP W TEMP DO compare with A D result 00005066 6508 BCS B OK1 branch if actual temp is above threshold 00005068 6100 002A BSR HEATON activate heater 0000506c 6000 001 BRA DOVOLTS speeds up interrupt service routine 00005070 3038 4000 OK1 MOVE W SETPT DO get temperature setpoint 00005074 5 40 ADDQ W 5 D0 compute upper threshold 00005076 BO78 FDO2 CMP W EMP DO compare with A D result 0000507 6204 BHI B DOVOLTS branch if actual temp is below threshold 0000507c 6100 0016 BSR HEATON activate heater The following code segment will measure voltage on A D channel 4 and scale the result into millivolts 00005080 303C 1388 DOVOLTS MOVE W VREF DO load scale numerator VREF 5000
5. at least 10 300 2 500 1 31 ms A minimum setup time from CS to SCK is 2 A D CLKs 425 ns Since this value is 1 425 ms and is the larger value the DSCKL field in QSPI SPCR1 must be programmed to provide at least this amount of delay The MC68332 User s Manual see Reference 2 states the formula for DSCKL as follows delay time DSCKL system clock frequency Solving for DSCKL gives DSCKL 1425 ns 62 5 ns 22 8 Rounding up to the nearest whole delay there are 23 DSCKL units for a total delay of 1 4375 ms Also the DSCK bit must be set in each command control byte that governs a transfer to the MC145050 otherwise the standard delay of one half SCK period will be used in this case 250 ns For a successful conversion to occur a delay of 44 A D CLKs must elapse from the last falling edge of SCK to the next assertion of CS The QSPI always provides a one half SCK delay after the last SCK edge before the CS pins change state The delay time before the next CS assertion must then be 44 500 ns 250 ns 21 75 ms The equation for delay between transfers is delay time 32 DTL system clock frequency thus it follows that QSM AN1062 USING THE QSPI FOR ANALOG DATA AQUISITION MOTOROLA REFERENCE MANUAL A 9 DTL system clock frequency delay time 32 therefore DTL 16 109 Hertz 21 75 10 seconds 32 DTL 10 88 which rounds up to 11 Plugging DTL 11 into the original equation gi
6. be handled by simply waiting a known amount of time until the first result has been updated Using a different approach start the queue from entry F and then transfer and loop on entries O 1 and 2 Queue entry F executes once whereas entries 0 2 will repeat in definitely causing the invalid data word from the A D converter to be stored in unused RAM associated with queue entry F After SPIF in the SPSR is set all A D result lo cations will contain valid data From then on the CPU merely reads the latest A D re sults from their fixed locations effectively making the serial A D converter appear to the CPU as a parallel memory mapped peripheral Having fixed locations for each channel s result allows the programmer to equate them with sensor names making software easier to write and maintain especially when compared to serial systems funneling all results through a single receive register The example in Figure A 9 shows an interrupt service routine which will generate a warning if fuel pressure drops below a specific level To cancel the warning the pres sure must increase above a second threshold Similarly a heating element is con trolled to maintain an operator specified temperature within a given range Finally an MOTOROLA AN1062 USING THE QSPI FOR ANALOG DATA AQUISITION QSM A 10 REFERENCE MANUAL unknown voltage is measured scaled into millivolts then displayed on an LED out Again note that the CPU just rea
7. bits CPOL CPHA 0 0 baud 2MHz 23 DSCKL SPE 11 start QSPI DSCK 1 4375 uS DTL 22 uS INQSO 10000 INQS1 form into long word 2 ENDO WREN S F wrap endq 2 SF 0000 nothing special same as RESET state INQS2 10000 INQS3 form into long word addresses and initialization values RO FFFFFD20 transmit RAM entry 0 FFFFFD24 transmit RAM entry 2 FFFFFD3E transmit RAM entry F E N N wn FFFFFD40 control RAM entry 0 FFFFFDAF control RAM entry F RO RECEIVE RAM KKK KKK KKK KKK KKK KK KKK FUELPS1 TEMP VOLTAGE SFFFFFDOO 0 OSPI location of A D pressure result SFFFFFDO2 QSPI location of A D temperature result FFFFFD04 2 QSPI location of A D voltage result KOK KK RK RK KK koko KKK KK KKK KKK KK KKK KKK KK KK KKK KKK KKK QSPI TRANSMIT RAM INITIALIZATION CONSTANTS KOK KKK KKK RK KKK KKK KKK KKK KK KK KKK KKK KK KK KK KK KK KKK EQU EQU EQU EQU TXRO1 OF X F F X 3 64 4 64 6 64 6 64 EQU multiply entry sensor A D channel 3 addressO temperature A D channel 4 address1 voltage A D channel 6 address2 pressure A D channel 6 addressF pressure TXRO 10000 TXR1form into a LONG WORD A D address by 64 to put the LSB into bit 6 of the 10 bit transfer MSB of the 4 bit A D address will be MSB of 10 bit transfer NOTE transmit queue entry 0 requests a conversion on A D channel 3 the temperature sensor This resul
8. on the pins of the MC145050 This timing sequence corresponds to the timing sequence illustrated in Figure 9 of Reference 4 Although not the fastest method for sampling the A D con verter this timing sequence allows efficient use of the MC145050 on a bus in conjunc tion with other peripherals During A D conversion the QSPI can select and exchange data with another device maximizing overall serial bandwidth The timing for 10 clock transfer not using CS may be slightly faster but if it is used with other peripherals the QSPI must wait for the conversion to be completed For successful operation power supply decoupling and wiring should be carefully con sidered The 0 1 mF decoupling capacitor should be placed as close as possible to the Vpp and Vss pins A nearby decoupling capacitor is also needed between the VREF and Vag pins Separate lines should be run to the Vper and Vag inputs since any cur QSM AN1062 USING THE QSPI FOR ANALOG DATA AQUISITION MOTOROLA REFERENCE MANUAL A 7 rent drain will cause IR voltage drop in the traces If an active IC is being powered by the same trace the switching current transients can cause enormous errors As the timing diagram shows the MC145050 requires valid data on the DIN pin during the rising edge of SCK The data is allowed to change on the falling edge of SCK This determines the clock polarity and phase values that need to be programmed into the QSPI CPOL 0 CPHA 0 lt SCK
9. APPENDIX AN1062 USING THE QSPI FOR ANALOG DATA AQUISITION By Craig Shaw A 1 Introduction To effectively use digital microcontroller units MCUs in an analog world analog in formation must be converted into digital form In all applications fast accurate and inexpensive conversion is desirable Minimizing printed circuit board space and inter connections is also desirable NOTE This application note can be applied to any MCU i e MC68332 MC68HC16Z1 etc containing queued serial peripheral interface QSPI circuitry The MC68332 lacks any direct analog to digital A D conversion capabilities This de ficiency is easily and inexpensively remedied by connecting the QSPI to an external serial A D converter This application note presents hardware and software examples detailing use of the QSPI with multichannel 8 and 10 bit A D converters specifically the MC145040 and the MC 145050 It describes design methodology for obtaining maximum A D through put using one or more A D converters It also discusses how to simultaneously use other peripherals with the QSPI and how to determine overall system performance A 2 Operation of the MC145040 and MC145050 Family A D Converters The following paragraphs give a brief overview of the Motorola serial A D converters For a more thorough treatment of the subject refer to Reference 3 and Reference 4 The 145040 MC145041 MC145050 MC 145051 are low cost ratiometric
10. D CHANNEL 4 GET CHANNEL 3 RESULT REQUEST A D CHANNEL 6 GET CHANNEL 4 RESULT REQUEST A D CHANNEL 3 GET CHANNEL 6 RESULT REQUEST A D CHANNEL 4 GET CHANNEL 3 RESULT REQUEST A D CHANNEL 6 GET CHANNEL 4 RESULT FFFD40 1 0 BIT DSCK DT ENABLES PCS0 0 FFFD41 1 0 BIT DSCK DT ENABLES PCS0 0 FFFD24 5 A D MUX ADDR 6 FFFD42 1 0 SIT DSCK DT ENABLES PCS0 0 RECEIVE RAM ADDR CONTENTS FFFD00 1 A D CHANNEL 6 RESULT FFFD02 3 A D CHANNEL 3 RESULT FFFD04 5 A D CHANNEL 4 RESULT X x x x X x FFFDI E F A D INVALID DATA NOTE 0 WREN 1 NEWQP F Z Figure A 10 Example Queue Structure and Operation Flow QSM REFERENCE MANUAL AN1062 USING THE QSPI FOR ANALOG DATA AQUISITION MOTOROLA A 17 TRANSMIT RAM ENTRY NUMBER ADDR CONTENTS 0 FFFD20 1 A D MUX ADDR 3 1 FFFD22 3 A D MUX ADDR 4 2 FFFD24 5 A D MUX ADDR 6 3 X x X x X X FFFD3C D OUTPUT PORT FFFD3E F A D MUX ADDR 6 X DON T CARE UNUSED CONTROL RAM ADDR CONTENTS FFFD40 10 BIT DSCK DT ENABLES PCSO 0 FFFD41 10 BIT DSCK DT ENABLES PCSO 0 FFFD42 10 BIT DSCK DT ENABLES PCSO 0 X x X X X X FFFDAF 10 BIT DSCK DT ENABLES PCS0 0 ENTRY NUMBER QSPI OPERATION FLO ENDQP ENDQP WRITE NEWQP E NORMAL QUEUE RESUMES ENDQP ENDQP ON O
11. OPAR ODDR INOPDR INOPAR INODDR INOPORT OSPI bit definitions EQU EQU EQU EQU EQu EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU 80 control RAM structure 40 20 10 08 04 02 01 08 QPDR QPAR QDDR 04 02 01 8000 SPCRO 400 8000 5 1 100 4000 SPCR2 100 80 SPSR OSPI register addresses EQU EQU EQU EQU SFFFFFC14 QPDR as aligned WORD SFFFFFC18 control register 0 SFFFFFC1C control register 2 SFFFFFCIF OSPI status register Control register initialization values EQU EQU EQU EQU REGCSO PCSO default value 1 REGCS0 SCK MOSI MISO pins assigned to QSPI REGCS0 SCK NOSI QSPI output pins INOPDR 100 INQPAR 100 INQDDR form into a LONG WORD just what s needed for this example Figure A 9 Use of QSPI to Control A D Conversions 2 MHz A D Sheet 1 of 4 QSM AN1062 USING THE QSPI FOR ANALOG DATA AQUISITION REFERENCE MANUAL MOTOROLA A 13 0000a804 0000970B a804970B 0000420F 00000000 420 0000 fffffD20 fffffD24 fffffD3E fffffD40 fffffD4AF fffffD00 fffffD02 fffffD04 000000C0 00000100 00000180 00000180 00000100 TXRO 1 TXR2 SPCRO INOSO 11051 INQSO1 SPCR2 INOS2 INOS3 INQS23 KARERE TXRAMO TXRAM2 TXRAMF CRAMO CRAMF SPCR1 EQU EQU EQU SPCR3 EQU EQU EQU RAM EQU EQU EQU EQU EQU 10 BITS MSTR 4 master 10
12. PERIOD 500 ns 1 M 2 VALID CHIP SELECT VALID CHIP SELECT na 1 CS HOLD CONVERTB lt 44 A D CLKS lt gt QSPI DATA SETUP TIME 22 us 1 2 s 8 9 1 2 3 l4 1 1 SAMPLE MUX ADDRESS y on lt m KXON _ 1 s i sur ATTO TTO E sm Yin 1 ee MUX ADDRESS A CONVERSION RESULT c MUX ADDRESS B FROM PREVIOUSLY SELECTED MUX CONVERSION RESULT ADDRESS NOT SHOWN 2 A D CLKS 300 ns 1 3 us CS VALID TO DOUT DRIVEN Figure A 8 MC14050 Conversion and Transfer Timing A 5 Timing Considerations One factor determining overall system speed is the source impedance of the signal be ing measured The impedance limits the maximum SCK clock frequency because the SCK frequency is what determines the actual sample interval For more information on source impedance effect on clock frequency refer to Reference 4 A source imped ance of less than 1000 ohms is assumed so that sample interval is not a constraint Calculate the maximum SCK frequency according to the following procedures Ac cording to Reference 4 the minimum pulse high and low widths twh tw are both 190 ns the maximum propagation delay from SCK to DOUT tppL tp jj is 240 ns and the minimum setup time from DIN to SCK tg A D is 100 ns Assuming a QSPI minimum data setup time tsu Q MISO to SCK of 10 ns to meet QSPI input data timing requirements the mini
13. ds the latest conversion results The total time to complete the entire queue is calculated as follows no of bits SCK period DSCKL period DTL period 10 500 ns 1 4375 ms 22 ms 28 4375 ms time per wap no of entries time per entry 3 28 4 85 3 ms The of the oldest result is calculated as follows time per entry maximum age time per entry of entries 1 sample time sample time 6 SCK period 6 500 ns ms maximum age 28 4 ms 3 1 3 ms 116 75 ms The maximum age equation accounts for the fact that the analog level may change while sampling conversion and transfer occurs If the sample time is not considered the oldest data is simply the sum of the time per wrap and the time per entry because the A D result data always emerges on the transfer following the transfer requesting the conversion A 7 Other Useful Concepts If the QSPI is to be used to control another peripheral in addition to an A D converter it may be advisable to interleave the transfers to the two peripherals Interleaving can improve the overall serial transfer rate queue entries per second by constructively utilizing the time ordinarily wasted waiting for a conversion If faster data acquisition is necessary this concept can also apply to a second A D converter The conversion workload must be split between the two A D converters so that one is sampling while the other is converting reducing t
14. he average time between conversions from 28 4 ms to 14 2 ms If three A D converters are employed the time drops to 9 5 ms If a fourth A D converter is used the total acquisition time is reduced to the theoretical minimum value 7 5 ms The theoretical minimum is the sum of the transfer time 5 ms the minimum DSCK time 1 4375 ms and the minimum delay after transfer 1 0625 ms Another useful feature of the QSPI is the ability to support subqueues Subqueues are formed when the normal queue execution sequence is altered to perform a special task Often the special task needs attention as soon as possible Afterward it is usu ally desirable to resume execution of the previously defined queue An example would be the continuous scanning of three A D converter channels as previously described but upon detection of an interrupt quickly setting an output port to a given value After the output data is transferred the QSPI should continue scan ning the three A D channels This operation is easy due to the branching capability of QSM AN1062 USING THE QSPI FOR ANALOG DATA AQUISITION MOTOROLA REFERENCE MANUAL A 11 QSPI While the QSPI is operating writing to the NEWQP field lower byte of SPCR2 will cause the QSPI to complete the transfer already in progress then exe cute the transfer specified by NEWQP Normal operation transferring queue entries in sequence continues from the point indicated by NEWQP If a new ENDQP value is a
15. igure A 6 QSPI Programmer s Model Serial peripheral control register 3 SPCR3 controls self test and program debug functions which will not be discussed in this application note The serial peripheral sta tus register SPSR contains two status fields of importance for this application The completed queue pointer CPTQP field contains the queue entry number that was most recently completed The QSPI finished flag SPIF bit is set when the CPTQP matches the ENDQP which indicates that the specified queue has been completed and the QSPI has either shut down or wrapped to the designated point MOTOROLA AN1062 USING THE QSPI FOR ANALOG DATA AQUISITION QSM A 6 REFERENCE MANUAL A 4 Basic System Implementation The schematic diagram shown in Figure A 7 depicts the basic minimal serial A D data acquisition system The only extraneous logic required for this system is the 2 MHz oscillator The oscillator can be used to supply a number of other peripheral devices as well as additional A D converters Also the oscillator can be eliminated entirely and an MC145051 can be used in place of the MC145050 however the speed of the con versions would be reduced V QSM QSPI MC68332 PRESSURE 11 ANALOG INPUTS VOLTAGE TEMPERATURE gt gt mom FP FSF FS A D CLK 2 MHz OSCILLATOR Figure A 7 Basic Serial A D Data Acquisition System The timing diagram see Figure A 8 shows significant events
16. ime Otherwise the first clock pulse is delayed one half of an SCK period This delay is necessary because some peripherals require a relatively long period of time to respond SCK MOSI TO SLAVE MISO FROM SLAVE PROGRAMMABLE FEATURES NUMBER OF BITS X DELAY BEFORE FIRST CLOCK Y DELAY BETWEEN TRANSFERS CLOCK RATE POLARITY DATA PHASE SHIFT CHIP SELECT PATTERN Figure A 5 Basic QSPI Master Mode Timing Diagram MOTOROLA AN1062 USING THE QSPI FOR ANALOG DATA AQUISITION QSM A 4 REFERENCE MANUAL If DT is set a user specified delay elapses before the next serial transfer is begun Otherwise the QSPI executes the next transfer as soon as possible approximately 1 ms when the MC68332 operates at 16 778 MHz This delay is useful if a peripheral needs time to perform a function that affects subsequent serial transfers One example might be to wait for an A D converter to perform a conversion The remaining element in the control byte is the bits per transfer enable BITSE bit If BITSE is set the transfer length is a user specified value ranging from eight to 16 bits If BITSE is cleared the transfer length will default to eight bits Figure A 6 represents a programmer s model of the QSPI The QSM data direction register QDDR determines whether a given QSPI pin is an input or an output When read the QSM port data register QPDR provides the logic level present on a QSM input pin or the data latched in an out
17. k k k k k k k k k k k k k k k k k k k k k ORG 55000 Initialize TRANSMIT RAM STARTMOVE L TXRO1 TXRAMOentries 0 1 MOVE W TXR2 TXRAM2 entry 2 MOVE W TXRF TXRAMF entry F Initialize CONTROL RAM MOVE L CRXL CRAMO entries 0 1 2 3 3 is superfluous MOVE B CRXB CRAMF entry F Initialize QSPI control registers START transfers MOVE L INQPORT QPDRWsetup OPDR QPAR QDDR 420F 0000 MOVE L INQS23 SPCR2 setup SPCR2 SPCR3 A804 970B MOVE L INQSO1 SPCRO setup SPCRO SPCR1 start 0007 WAIT BTST B 7 SPSR wait until a valid conversion result BEQ B WAIT is available for all channels x All data available continue on to main program KKK k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k Kk k k k Kk Kk k KK k k Kk k k k Kk k k k k k k k k KKK KK k k k k k k k k k k kk CPU data ACGUPSTELON EK OE RAK RAR EO EUR e k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k Kk k k k k K k k k K Kk k kk k KKK KKK x The following code could be periodically executed in response id to a real time interrupt The interrupt could even be generated by the upon completion of each queue 0117 INTSRV MOVE W 279 D0 load constant for minimum fuel pressure FDOO CMP W FUELPSI DO test if A D pressure result is below minimum BCS B CHKRCV Figure A 9 Use of
18. leted used if DT is set Serial peripheral control register 2 SPCR2 specifies five queue control functions The new queue pointer value NEWQP field determines which queue entry is to be trans ferred first More queue entries are sequentially transferred until the entry specified by the ending queue pointer ENDQP field is completed If the wrap enable WREN bit is set transfers continue either at queue entry 0 or at the entry specified by the NEW QP field The point the queue wraps to entry 0 or NEWQP is determined by the wrap to WRTO bit The SPI finished interrupt enable SPIFIE bit is an interrupt en able If set an interrupt will be generated upon completion of the queue entry specified by the ENDQP field QSM AN1062 USING THE QSPI FOR ANALOG DATA AQUISITION MOTOROLA REFERENCE MANUAL A 5 MSB LSB A QSM MODULE CONTROL SUPERVISOR DATA SPACE RAREDWITHSOR Y SUPERVISOR OR UNRESTRICTED DATA SPACE RECEIVE RAM 16 WORDS TRANSMIT RAM 16 WORDS CONTROL RAM 16 BYTES 5 9 8 7 6 5 4 3 2 1 0 sPCRo MSTR BITS CPOL CPHA BAUD SPCR1 SPE DSCKL DTL SPCR2 sPiFiE WREN WRTO ENDQP SPCR3 LOOPQ HALT SPIF MODF HALTA SPSR RECEIVE BAM OCIO RECEIVE DATA UP 16 BITS LSB JUSTIFIED TRANSMIT Lesa TRANSMIT DATA UP TO 16 BITS LSB JUSTIFIED RAM 08 NOTE Shading denotes not used area F
19. lso written its value is used to determine the end of the queue There is no implicit return mechanism but if the queue is properly structured the original operation will re sume automatically Figure A 9 shows the queue structure and operation flow that demonstrates this ca pability Assuming the QSPI is already in operation scanning A D channels 3 4 and 6 when the interrupt arrives the software merely sets up the QSPI RAM associated with the special event then writes 0E to the lower byte of SPCR2 This procedure causes the QSPI to complete the present transfer then transfer queue entries E and F Since ENDQP is still two the QSPI will then transfer entries 0 1 and 2 then wrap back to entry 0 The software never has to modify any control registers or respond to QSPI interrupts because the original queue is resumed automatically For minimum la tency the program should initialize the control RAM and the transmit RAM if possi ble for the special operation before the operation is to occur to initiate the subqueue transfer A 8 References The following are resources which contain further information on the topics discussed in this application note 1 Harman Thomas L The Motorola MC68020 and MC68030 Microprocessors Assembly Language Interfacing and Design Englewood Cliffs NJ Prentice Hall 1989 2 MC68332 User s Manual MC68332 UM AD Motorola Inc 1990 3 8 Bit A D Converters with Serial Interface MC145040 D
20. mV 00005084 COf8 FD04 MULU W VOLTAGE DO multiply by A D channel 4 conversion result 00005088 E088 LSR L 8 D0 divide by 256 0000508a E488 LSR L 2 D0 divide by 4 total of divide by 1024 0000508c 4241 CLR W D1 0000508e D141 ADDX W 1 round for maximum accuracy result 00005090 6102 BSR B DISPV display voltage on a digital readout 00005092 4E73 RTE return from interrupt service routine 00005094 LOPRESS EQU dummy subroutines 00005094 PRESSOK EQU 00005094 HEATON EQU 00005094 HEATOFF EQU 00005094 DISPV EQU 00005094 E75 RTS 0 Error s 0 Warning s Figure A 9 Use of QSPI to Control A D Conversions 2 MHz A D Sheet 4 of 4 MOTOROLA AN1062 USING THE QSPI FOR ANALOG DATA AQUISITION QSM A 16 REFERENCE MANUAL ENTRY NUMBER 0 1 ENDQP gt 2 3 X 4 X E X NEWQP gt F X DON T CARE UNUSED X X X ENTRY NUMBER START NEWQP ENDQP gt TRANSMIT RAM ADDR CONTENTS FFFD20 1 A D MUX ADDR 3 FFFD22 3 A D MUX ADDR 4 FFFD3E F A D MUX ADDR 6 nm X X CONTROL RAM ADDR CONTENTS X X x FFFD4F 10 BIT DSCK DT ENABLES PCSO 0 QSPI OPERATION FLOW REQUEST A D CHANNEL 6 GET UNDEFINED DATA REQUEST A D CHANNEL 3 GET CHANNEL 6 RESULT REQUEST A D CHANNEL 4 GET CHANNEL 3 RESULT REQUEST A D CHANNEL 6 GET CHANNEL 4 RESULT SET SPIF AFTER COMPLETION OF ENTRY 2 REQUEST A D CHANNEL 3 GET CHANNEL 6 RESULT REQUEST A
21. mum clock pulse width is the greater of tPLH tsu Q or teur La Q This yields 250 ns MOTOROLA AN1062 USING THE QSPI FOR ANALOG DATA AQUISITION QSM A 8 REFERENCE MANUAL Assuming a QSPI maximum data delay time t44 Q SCK to MOSI of 10 ns to meet MC145050 input data timing requirements the minimum clock pulse width is the great er Of twh tw Or tqg Q ts A D This figure is 190 ns Data hold times on both the QSPI and the MC145050 are too minimal to present a problem since data is not allowed to change until one half SCK period after the latch is triggered The minimum SCK period must be twice the largest minimum clock pulse width since the QSPI generates a symmetrical SCK waveform This number is 500 ns indicating a maximum SCK frequency of 2 MHz The MC68332 will be clocked at a system clock frequency of 16 MHz allowing an SCK frequency of exactly 2 MHz The BAUD field value can be found from the following equation BAUD system clock frequency 2 desired SCK frequency Therefore the BAUD field should be programmed to BAUD 16 MHz 2 2 MHz 4 Another parameter that must be determined is the minimum time that must elapse be tween asserting the MC145050 CS pin and providing the first SCK pulse According to Reference 4 the maximum propagation delay from CS to DOUT driven 21 tpZH is 2 A D CLKs 300 ns Assuming a QSPI input data setup time of 10 ns and an A D CLK frequency of 2 MHz the total delay must be
22. nel selection and conversion results are transferred through the digital serial communication pins A serial transfer synchronizing clock must be fed into the SCLK input pin when the chip select CS pin is driven low The address to be converted is serially transmitted into the DIN pin and the conversion results are serially shifted out the DOUT pin The 145050 is designed to be used in conjunction with multiple serial devices ona common bus consequently the DOUT pin is driven only when CS is asserted The serial protocol employed is Motorola SPI which is compatible with the National Semi conductor Microwire system and the Texas Instrument TMS370 series SPI units The Motorola queued serial module QSM also contains a QSPI that efficiently imple ments this protocol A 15 A 18 DIGITAL SERIAL 17 COMMUNICATION PINS A pour 16 J A ANALOG INPUTS 5 MC145050 ANO AN10 ig AID CONVERSION AID CLK CLOCK INPUT A UP TO 2 MHz POWER SUPPLY 5 V NOMINAL lt m m o VOLTAGE REFERENCES lt gt Figure A 1 MC145050 Pinout A 3 Fundamentals of QSPI Operation The following paragraphs give a brief overview of the QSPI as it applies to the exam ples that are presented A more detailed description of the QSPI is contained in Sec tion 5 of MC68332 User s Manual see Reference 2 The QSPI is an intelligent synchronous serial interface with a 16 entry full duplex queue It can c
23. ontinuously scan up to 16 independent peripherals and maintain a queue of the most recently acquired information with no central processor unit CPU MOTOROLA AN1062 USING THE QSPI FOR ANALOG DATA AQUISITION QSM A 2 REFERENCE MANUAL intervention It features variable word lengths programmable selects and select able data clock phase relationship The baud rate and the delay between transfers are also programmable The QSPI has a maximum transfer speed of one fourth the MC68332 system clock speed Since the QSPI is capable of operation as a master or as a Slave all pins are bidirec tional Figure A 2 shows a typical master mode configuration The slave peripherals are selected via the peripheral chip select pins PCS 0 3 and the serial clock is pro vided by the SCK pin QSPI output data is presented on the master out slave in MOSI pin and input is taken from the master in slave out MISO pin PCS3 QSPI PCS2 PERIPHERAL SUBMODULE CHIP SELECTS PCSO SS J SCK SERIAL CLOCK MOSI QSPI DATA OUT MISO QSPI DATA IN Figure A 2 Master Mode Representation of the QSPI One of the most powerful elements of the QSPI is its queue Figure A 3 depicts the structure of the QSPI queue RAM The queue may contain up to 16 entries each con sisting of a transmit word a receive word and a command control byte The transmit and receive words are from 8 to 16 bits long and are LSB justified For any given queue entry the transmit and
24. put pin When written the write data is latched into the output register The QSM pin assignment register QPAR controls whether a pin is to be controlled by the QSPI is to function as a general purpose I O pin Serial peripheral control register 0 SPCRO specifies six different functions The mas ter slave mode select MSTR bit if set causes the QSPI to operate as the controller of the SPI transfer The wired OR mode for QSPI pins WOMQ bit if set causes all QSPI outputs to function in an open drain mode requiring external pull up resistors The bits per transfer BITS field allows the programmer to specify the number of bits in a non default transfer used if BITSE is set The clock polarity CPOL bit deter mines the polarity of the SCK output and the clock phase CPHA bit dictates the da ta s phase relationship to the SCK The serial clock baud rate BAUD field determines the QSPI SCK frequency from 33 kHz to 4 2 MHz with the MC68332 system clock frequency at 16 778 MHz Serial peripheral control register 1 SPCR1 specifies three different functions Setting the QSPI enable SPE bit causes the QSPI to begin operation clearing SPE causes operation to stop immediately SPE is automatically cleared by the QSPI when it com pletes all specified transfers The DSCKL field allows the programmer to set the non default delay before SCK used if DSCK is set The DTL field controls the non default delay after the transfer is comp
25. receive words are the same length COMMAND CONTROL N y WORD WORD BYTE Figure A 3 Organization of the QSPI Ram QSM AN1062 USING THE QSPI FOR ANALOG DATA AQUISITION MOTOROLA REFERENCE MANUAL A 3 An important subset of the queue RAM is the command control RAM Figure 4 shows a breakdown of a single command control byte and Figure A 5 depicts a basic QSPI master mode timing diagram The control byte allows the programmer to cus tomize each serial transfer to the specific needs of the targeted peripheral Chip select patterns are stored in the PCS 0 3 bit fields of each applicable control byte and are driven onto the chip select pins when the specified transfer begins If set the continue CONT bit allows the QSPI to continue driving the programmed chip select value until the beginning of the next transfer This procedure has the effect of concatenating mul tiple serial transfers to a single peripheral and allowing more than 16 bits per ex change If the CONT bit is clear a user defined default value is driven onto the chip select pins between serial transfers COMMAND i PERIPHERAL CONTROL BITS CHIP SELECT BITS COMMAND CONTROL BYTE Figure A 4 Command Control Byte The PCS to SCK delay DSCK and delay after transfer DT bits enable user defined delays before and after the specified transfer If DSCK is set the first clock following the chip select assertion is delayed by a user specified amount of t
26. t will be returned into receive RAM in queue entry 1 The A D result always gets transmitted on the A D transfer following its request Figure A 9 Use of QSPI to Control A D Conversions 2 MHz A D Sheet 2 of 4 MOTOROLA 14 AN1062 USING THE QSPI FOR ANALOG DATA AQUISITION QSM REFERENCE MANUAL 00000070 00007070 70707070 00001388 00004000 VARIABLE 00005000 00005000 21FC FD20 00005008 31FC 0000500e 31FC 00005014 21FC FD40 0000501c 11FC 00005022 21FC FC14 0000502a 21FC FC1C 00005032 21FC FC18 0000503a 0838 00005040 67 8 00005042 303c 00005046 8078 0000504a 6504 00 0100 0180 FD24 0180 70 70 70 70 00 70 FD 4F 00 08 OF OE kk k k k k k k k K k k k k ck ck lt k ck k K ck k k k k k k k k k k k k k k k k k K QSPI CONTROL RAM INITIALIZATION CONSTANTS k k k k k k k k k k k k k k k k k k K k k k K k k k k k k k k k k k k k k k k k k k KKK CRXB EQU BITSE DSCK DT 10 bits both delays same for all transfers CRXW EQU CRXB 100 CRXBform into a WORD CRXL EQU CRXW 10000 CRXWform into a LONG WORD Misc VREF EQU 5000 VREF is 5000 millivolts SETPT EQU 4000 address of temperature setpoint variable KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK KKK k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k RHKKKKKKKAKKAKK K XOSPT initialization and startup kk k k k k k k k ck k k k k k k k ck K k k k K ck K k k k k K K k k k K k k k
27. ves an actual delay of 22 ms A 6 QSPI Initialization and Operation Since the fastest throughput is possible when using 10 bit transfers the BITS field in SPCRO must be set to ten Additionally the BITSE bit must be set in each command control byte associated with a transfer to the MC145050 To simplify the example assume conversions are only wanted from A D channels 3 4 and 6 Those channels will be sampled repeatedly and each channel will have a separate fixed memory address where the most recently acquired result will always be available to the CPU The WREN bit in SPCR2 and the first three queue entries will be used The transmit RAM must contain the A D multiplexer address to be converted and the receive RAM will hold the conversion results Figure A 9 is an assembly language listing showing how the QSPI is configured to perform the stated functions The first portion of the program is definitions followed by initialization The QSPl is then activated The program waits until all conversions have been performed once before utilizing the results Figure A 10 shows the setup and operation of the queue RAM in this example It is important to note that the conversion data requested by one queue entry is not shifted out until the next transfer thus the data is stored in the receive RAM corresponding to the latter transfer Also the very first transfer of output data from the A D converter is invalid and should be ignored This issue can
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