UM10755 - NXP Semiconductors
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1. VGA CONNECTOR2 15V GA CO CTO 4 7uH 3 3V fc 39 38 36 35 VGA2 O 1 5 21 e gt 5 2 DP VGA1 E H _ gt __________ PTN3355 6x6 DV Sync Z 35 e DP INTF e AUX mm in Socket DDC_120 3 bk Ri lt 0 gt HPD 12C_BUS JTAG DDC _12C SM_BUS sEEPROM CFG um10755_bd Fig 1 ULT DP VGA application board block diagram UM10755 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved User manual Rev 1 19 January 2015 4 of 19 NXP Semiconductors U M1 0755 PTN3355 e DP to VGA bridge IC application board rex ULT DPVGA DEMO age BRD RI A um10755_appboard Fig 2 PTN3393 application board UM10755 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved User manual Rev 1 19 January 2015 5 of 19 NXP Semiconductors U M1 0755 PTN3355 e DP to VGA bridge IC application board J en PTN3355 vy DIER o BRD DL D a ET FEN Q enoj um10755_3355appboard Fig 3 PTN3355 application board 2 3 PTN3355 ULT DP VGA application board features Stuff options for PT3393 or PTN3355 e Groups of jumpers for pin configuration Other jumpers for test options e One reset button e Power LED e HPD LED e One 12C2. O08 Er e E y 1 Y SZ SS SS AAR ES TO MEASURE IC POWER vc 5S528g0 APPLY EXTERNAL PWR TO PIN1 w E 5 B NORMAL OP PIN2 PIN3 e El 2 6 PLACE NEAR PIN 27 VDDA_3V3 3 T g d 1 30 RSET 2 VDDA33_DNW yoo RSE RSET e Se ISLA gt DOCK IN 2 8 29 one SCH 4 DOCK_IN gt TOSCA AUR 4 CFGO DOCK_INLDOCAP_AL 8 8 GRN2 gt gt GRN2 sust SCH 3 AUX_P gt AUX P 3J aux P DS sas GRN1 L ORN gt gt GRN Cu SCH NN AUX N A AUKN j VODA23_DA aus 22 VODA DAG 3V3_IC VDD_3V3 VDD_3V3 1 2 VDDE33 5 ope 19 Som Bwr b BLU Ris x Gas nd LDOCAP_AUX RIO o f a S H MLO P 6 i p pee 25 HSYNC ise EE Soup MLO_P gt Y MLO_P a SYN HSYNC1 Zus sou SCH 3 MLO_N yuen Zy meo n MLO_N see veer gt gt VSYNC sou EE 8 VDDA15 DP Ncl 2 DDC_SCL2 BEES gt gt pDc_scL2 SCH 2 me ma Soup Mur pe uti E a boc_soa DEG Spa H DG SpA gt gt DDC_SDA SCH 2 4 1 SCH MAN MLN 10 min a 10 vDDE33_10 L I HPD e d 3 VDD_3V3 DDC_SDA2 TERED TERED SCH 3 HPD een VBUCK_1V5 ge 8h 32 A be A DDC_SDAZ scH CFG3 TDO 9 2 R 5 a 8 REMOVE L2 PLACE SE ESP E 358 E E CURRENT METER ACCROSS SCH 4 CFG5_TCK g ores T z 9 sl Es a Se 2 3V3_IC AND VDD_3V3 d i ESCHER 9 SCH MS sCLUTDI amp H ca cto SZ SS SS SS SS Sg o MS_SDA TMS SCH 4 MS_SDA TMS amp af OtuF al 0 01uF PTN3355 H 2 2 2 5 2 2 amp CLK_O E NE N S HER ESN Ml d i ai PLACE NEAR PIN 21 Y NE of al PAra d RST_N Za ol of 2 Si TP_WHITE PLACE NEAR PIN 8 xj al el 2 S 8 a SE A S 10 TT ont 8
3. UM10755 PTN3355 e DP to VGA bridge IC application board Rev 1 19 January 2015 User manual Document information Info Content Keywords PTN3355 PTN3393 DisplayPort eDP VGA bridge application board Abstract This user manual presents demonstration application board capability of interfacing an embedded DisplayPort source to VGA output The application board nicknamed ULT DPVGA is intended for use as an evaluation and customer demonstration tool as well as a reference design NXP Semiconductors UM10755 Revision history PTN3355 e DP to VGA bridge IC application board Rev Date Description 4 20150119 Initial version Contact information For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com UM10755 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved User manual Rev 1 19 January 2015 2 of 19 NXP Semiconductors U M1 0755 iP PTN3355 e DP to VGA bridge IC application board Introduction UM10755 1 1 PTN3355 is a low power DisplayPort to VGA bridge IC with an integrated 1 2 VGA switch PTN3355 consumes approximately 200 mW of power for video streaming in WUXGA resolution and 890 uW of power in low power mode The VGA output is powered down when there is n
4. 2 HIGH WP for S EEPROM 2 3 2 3 LOW No WP S EEPROM JP10 CFG3 FLT TDO 1 2 HIGH Support FLT 2 3 2 3 LOW or OPEN No FLT support 6 Power options PTN3355_ 3393 application board can be powered by three different methods 6 1 DP 1 0 cable Set JP3 2 to J8 1 to select DP power Fig 7 Power by DP 1 0 cable um10755_powerbydp 6 2 3 3 V power adapter Set JP3 pin 2 to pin 1 to select 3V3 power adapter UM10755 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved User manual Rev 1 19 January 2015 11 of 19 NXP Semiconductors U M1 0755 PTN3355 e DP to VGA bridge IC application board um10755_powerby3v3 Fig 8 Power by 3 3 V power adapter 6 3 External power source Set JP3 pin 2 to pin 3 to select external 3 3V power supply Clip 3 3V power lead to TP5 and clip ground lead to GND test point UM10755 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved User manual Rev 1 19 January 2015 12 of 19 UM10755 PTN3355 e DP to VGA bridge IC application board NXP Semiconductors RES Rg ER Ne ai ULT DPVGA DEMO TI um10755_extpwrsrc Fig 9 Power by external 3 3 V power supply 1 of 2 NXP Semiconductors N V 2015 All rights reserved 13 of 19 All information provided in th
5. DNL S Lb a 1 3225 OSC TXC AU 27 000MBE cs css c12 c3 C14 7 2 2uF_10V au DNL DNL 2 2uF_10V 0 1uF 0 01uF a a AL 1 2 CONI iar MIRRA a n 3 PLACE NEAR PIN 36 as SY vBuckivs ST S PLACE NEAR PIN 38 Kaes NT ee 5 LDOCAP_DIG Pl VDD_3V3 PLACE NEAR PIN 1 fs VD 29 DNL ES elt IC SCH 4 TESTMODE gt gt 2 3V3_PWR 3V3 d E J Je g es G d A a 2 2uF_10V FB LDOCAP_AUX DOCK_IN VDDE33 2 g E of of 3 al 4a 8 lt 7 5 Ce 2 2uF 10V Al P LACE NEAR PIN 36 El LDOCAP_AUX al a RED2 ler DNL D a 2 Er gt gt RED2 SCH 2 ES ir es DNL al a RED 2 a DOCK IN u 2 ey S RED SCH 2 0171 001uF Keg D I a 3 8 8 5 go 3 a a a m N7 PLACE NEAR PIN 2 ut de sde PLACE NEAR PIN 5 HEADER 3 SENGS 258822538030 Teg ed gO g EE 2 TO MEASURE IC POWER ae RS ERO i APPLY EXTERNAL PWR TO PIN1 E o SZ S E EE S E a S 8 LACE NEA NORMAL OP PIN2 PIN3 VDDA_3V3 DOCK_IN oe el ar Wea E ce A Ke Ba ee er D 24 VDDA33_DNW vona33_aux a Jig 8 RSET AsEr 22 RSET E VERE gt 28 SCH 4 DOCK_IN gt 7 z7 q POCI N Da CFGOIDOCK INLDOCAB_AUX B 8 Nc gpa 22 SBN2 gt gt GRN2 SCH2 3 SCH AUX_P Se Rg D 3 aux P auxe cen ep V BR gt gt GRN SCH 2 SCH 3 AUS N AUX N DNE 4 AUX_N AUX_N vonAs3_PAC BLUZ in BLU2 sust 3V3_IC vDD_3V3 VDD ava HEES lune e Pex See au L BU Ss Boa 33 10 VDD 3V3 SCH 3 w r E MATE Sd mio P MLO_P iiai async HgyNc1 H Dm gt gt HSYNC SC SCH Way GE ZA wan MLO_N vom ysynci PA VSYNG Zus sou VBUC
6. 0755 PTN3355 e DP to VGA bridge IC application board 4 4 Bottom assembly drawings of the PTN3355 Application Board ES su H H T36 Fig 6 PTN3355 application board bottom assembly drawings um10755_botass 5 Connector specifications 5 1 Connectors and jumpers Table 1 Connectors and jumpers Jumper number Jumper name Connector name Manufacturer Part number J1 DP CONN SINK DP RCPT 20 POS Molex 47272 0001 J2 POWER JACK CONN JACK POWER CUI PJ 102A 2 1MM PC J3 J4 VGA_CONN CONN D SUB RCPT EDAC 634 015 274 992 15POS HD R A J5 J7 HEADER 4 CONN HEADER 100 Sullins PBCO4SAAN SINGL STR 4POS UM10755 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved User manual Rev 1 19 January 2015 9 of 19 NXP Semiconductors UM10755 PTN3355 e DP to VGA bridge IC application board Table 1 Connectors and jumpers continued Jumper number Jumper name Connector name Manufacturer Part number J6 HEADER 2x5 CONN HEADER 100 Sullins PBCO5DAAN DUAL STR 10POS J8 J10 J11 CON1 CONN HEADER 200 Sullins PBCO1SAAN SINGL STR 1POS JP1 JP3 JP4 JP5 JP6 HEADER 3 CONN HEADER 100 Sullins PBCO3SAAN JP7 JP8 JP9 JP10 SINGL STR 3POS JP2 HEADER 2 CONN HEADER 100 Sullins
7. 8 References UM10755 1 2 3 4 5 6 Data Specification PTN3355 pdf 14 July 2014 Schematic PTN3355_1 14_CONFIDENTIAL pdf BOM PTN3355_ONLY_REV14_BOM xls AN11413 PTN3393 PTN3355 rev4 pdf AN11415 PTN3355 rev1 pdf Allegro layout PTN3393 DEMO BOARD_REV1_305 PD12 0592_PCB_07 27 2012 brd All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved User manual Rev 1 19 January 2015 17 of 19 NXP Semiconductors UM10755 9 Legal information PTN3355 e DP to VGA bridge IC application board 9 1 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information 9 2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information NXP Semiconductors takes no responsibility for the content in this document if provided by an in
8. K 1V5 8 vDDA15_DP wei nc2 ppo sos H2 POG SOLE Zepp ez SCH 2 me ma SO wuar Kee 24 ur mP a poc_spa DDC_sDA1 22 DDC_SDA gt gt DDC_SDA SCHSA d SCH MLI_N Ke 104 wan MLIN 3 Y voDD32_10 VDDE33_0 L I E Eg 3 HPD 23 3 3 VDD_3v3 DDC SDA2 THE PA Sou HPD A VBUCK_1VS 52888828 4 Cp Le Zone op SCHI CFG3 TDO B E E g og REMOVE L2 PLACE SEHR SOTO 3 3058 3 aad CURRENT METER ACCROSS SCHIA CFGS_TCK SFG Tek z 9 sl KS ad RS PO ES 1 2 TDL33 bk SE gEER Se g 2 SCH 4 MS_SCL TDI Kiemen AR E a 6 SE E S a oe fo 7 al scha ms soamms ME SDAMUS ER E PTN3393 Ja eae aaa dao TRST N PLACE NEAR PIN 21 SCH 4 TRST_N lt ei BEER si Y RSR a Y RSTN D ad a 3 TP_WHITE PLACE NEAR PIN 8 d a e AS Si a GER S c22 SS Be au TE J DDC_SCL me aj PESE Y ppc scl SCH 2 4 swi I KS e 3 1 RSTN PI A VDD_3V3 VDDA_DP DDC_SDA2 Pl CLK_O_33 4 2 TERNAL PULL UP 0 o a s 2 PB SPST MOM El ST c18 7 el HPD el 2 2uF_10V cu DNL l RST SW d OtuF VDD 3V3 DNL DNL e lt 7 a EN PTN3393 DPVGA Demo Board Stuff Option HSYNC2 EES Document Number ev HSYNC2 SCH 2 PLACE NEAR MS_SDA TMS EE at 1 0 ale nesday July 25 eet Wednesday July 25 2012 Bh 2 of 5 um10755_3393stuffing p1eoq uoneosijdde 9 96p11q WHA 01 da SSEENLd SSZOLINN SJOJONPUODIWIIS dXN enueu sn sLoz lenuer 6L Aen s awIejosip ebaj 0 jos qns s juaunsop SU ul papinord uo ELO 61 JO OL SSZOLWN H Pamasa Su IV G LOZ N
9. LODE SEL Sne sc SCH 2 4 T swt 5 Y El 3 1 RSTN TRST_N Fe VDD_3V3 VDDA_DP DDC_SDA2 1 2 CLK_O_33 4 2 INTERNAL PULL UP o Re Ya a z PB SPST MOM al IME SEA E c18 HPD one li 2 2uF_10V E RST SW el VDD_3v3 ge a i A PER Pe PTN3355 DPVGA Demo Board Stuff Option HSYNC2 ize Document Number ev Cen HSYNC2 SCH 2 PLACE NEAR PIN 14 MS SDANTAS See SCH pa ate Monday January 13 2014 ies 2 o Fig 12 PTN3355 stuffing option design um10755_3355stuffing p1eoq uonesidde 21 36p11q WHA 01 da GGECNLd SSZOLINN SJOJONPUODIWIIS dXN NXP Semiconductors UM10755 PTN3355 e DP to VGA bridge IC application board 7 3 PTN3355_PTN3393 stuffing options table Table 3 PTN3355_PTN3393 stuffing options table Location Function Value PTN3355 PTN3393 C6 0 1uF Load No Load C7 1uF Load No Load C16 2 2UF_10V No Load Load C17 0 01uF No Load Load C19 0 1uF Load No Load R7 0 Ohm Load No Load R9 0 Ohm No Load Load R10 0 Ohm Load No Load R11 12 0K 1 No Load Load R1 10K No Load No Load R5 10K No Load No Load R6 0 Ohm for PTN3355 Load No Load 10K for PTN3393 R3 0 Ohm No Load Load L1 4 7uH Load No Load C3 4 7uF Load No Load R4 0 Ohm Load No Load R17 0 Ohm Load No Load C22 1uF No Load Load R12 0 Ohm No Load Load R13 0 Ohm Load No Load R15 0 Ohm Load No Load R16 0 Ohm Load No Load R21 0 Ohm No Load Load R18 0 Ohm Load No Load
10. N SIOJOMPUOAWIS AN O 7 2 PTN3355 stuffing REMOVE R62 PLACE CURRENT METER ACCROSS ct PVDD33 VBUCK_1V5 AND J9 VBUCK_1V5 3V3_10 VDD_3v3 9 VDD 3v3 VDDA_3V3 VCORE S S GAS DOUBLE FOOTPRINT FOR Y1 o o S 2016 AND 3225 e eg d E 4 a Y vo st Y PARTS TO TEST 2016 XTAL LENNA Ee A eo 7 y ie i 3225 XTAL ECS 270 20 33 FB co 7 o FB E Per z 1 3225 OSC TXC AU 27 000MBE cs css O tuF 1uF cr2 ms GEM al ail Ww al N Ess 2 2uF_10V Our al al 2 2uF_10V 0 1uF 0 01uF L1 ji BEZ al a al al al Y D PLACE NEAR PIN 36 es VUEN 108 ke PLACE NEAR Ka brg El LDOCAP_DIG Es VDD_3V3 PLACE NEAR PIN 1 g Enz S 2 i SCH 4 TESTMODE X P a 3V3_PWR 3V3 VDD_8V30 a a T al B al al z a LDOCAP_AUX DOCK_IN VDDE33 RI EE E gt al aj 8 al OO A KE El LDOCAP_AUX al S _ RED2 2 c9 Al E gt gt RED2 SCH 4 de Kass 1 2 ol al a RED DOCK IN a R7 7 has Zen SCH 2 VDDA_DA KC 3 g gl dadd al gl al s Fe SY PLACE NEAR PIN 2 ut Mks Sar ce Es E ES WE PLACE NEAR PIN 5 pa HEADER 3 GER SS SR SS s
11. PBCO2SAAN SINGL STR 2POS 5 2 Cables e DP 1 0 cable to power the application board e DP 1 1 cable for DP communication only e VGA cable 5 3 Jumper settings Table 2 Jumper settings Jumper number Signal Names Jumper Settings Default Setting JP1 3V3_IC 1 2 select external power to measure 2 3 2 3 select 3 1 power source JP2 HPD_ON 1 2 Enable HPD LED 1 2 OPEN Disable HPD LED JP3 J8 3V3_FB 1 2 Select 3V3 power adapter 1 2 2 3 Select external power supply JP3 2 to J8 1 Select DP power JP4 TESTMODE 1 2 HIGH CFG 5 1 JTAG PINS 2 3 2 3 LOW CFG 5 1 CONFIG PINS 12C 40H OPEN CFG 5 1 CONFIG PINS 12C COH JP5 CFG5_TCK 1 2 HIGH 33 MHZ XTAL is used OPEN OPEN 27 MHZ XTAL is used 2 3 LOW 25 MHZ XTAL is used JP6 DOCK_IN 1 2 HIGH Select VGA2 OPEN 2 3 LOW or OPEN Select VGA1 JP7 CFG1 MS_SCL TDI CFG1 CFG2 2 3 11 Compliant HPD behavior MS Bus is used 10 Non compliant HPD behavior UM10755 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved User manual Rev 1 19 January 2015 10 of 19 NXP Semiconductors UM10755 PTN3355 e DP to VGA bridge IC application board Table 2 Jumper settings continued Jumper number Signal Names Jumper Settings Default Setting JP9 CFG2 MS_SDA TMS 01 Non compliant HPD behavior 2 3 00 Compliant HPD behavior MS bus is not used JP8 WP 1
12. cripti0N o oooo Co layout of PTN3355 with PTN3393 Block dragoram ooo PTN3355 ULT DP VGA application board TOO 2 ci ee he ceed Hardware requirementS Board specifications General description o PCB stack UPS Top assembly drawings of the PTN3355 Application Boa Bottom assembly drawings of the PTN3355 Application Board Connector specifications Connectors and jumpers Cables 29 cia a Jumper settings oo oooooo Power Options ooooooomoomomo NS Cable caresser tetra 3 3 V power adanter nanana External power source Stuffing options 00 e eee eee PTN3393 Stuffing o ooo PTN3355 stuffing o oooo PTN3355_PTN3393 stuffing options table References 2000s cece eee eee Legal informati0N ooooo oo Definitions cee ee Disclaimer S e prone NIE EENS EN ete Trademarks Content as eene cee ene tae cares AER E Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information NXP Semiconductors N V 2015 All rights reserved For more information please visit http Avww nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 19 January 2015 Document identifier UM10755
13. d its suppliers accept no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product UM10755 All information provided in this document is subject to legal disclaimers design It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer s Customer is responsible for do
14. e i SS 53 09 2 5 9 5 5 5 9 mils 1002 10 101 26 Q Prepreg 4 70 mils copper 1 40 mils 47 20 mils copper 1 40 mils Prepreg 4 70 mils z copper plating 0 70 mis 943 mils gt 50Q 10 3099 5 9 5 5 5 9 mils gt 1000 10 101 26 Q 3 55 mils gt 75Q 10 um10755_pcbstackup Fig 4 ULT DP VGA Application Board PCB Stack Up example UM10755 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved User manual Rev 1 19 January 2015 70f 19 UM10755 NXP Semiconductors PTN3355 e DP to VGA bridge IC application board 4 3 Top assembly drawings of the PTN3355 Application Board Ki E CH Ll ai A Lal i L10 L11 si g ca g F a 8 H CH g bai A GO vd E fa fo te je Gs al Je a sl ej Je e apa n a 2 oe OG Bi E E ess 055 EN v a w R26 625 faa el ea es E pe DIEN DCH E Ei a d a H hold ee ES cag R56 um10755_topass Fig 5 PTN3355 application board top assembly drawings UM10755 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved User manual Rev 1 19 January 2015 8 of 19 NXP Semiconductors UM1
15. even if advised of the possibility of such damages Notwithstanding any damages that customer might incur for any reason whatsoever including without limitation all damages referenced above and all direct or general damages the entire liability of NXP Semiconductors its affiliates and their suppliers and customer s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars US 5 00 The foregoing limitations exclusions and disclaimers shall apply to the maximum extent permitted by applicable law even if any remedy fails of its essential purpose Translations A non English translated version of a document is for reference only The English version shall prevail in case of any discrepancy between the translated and English versions 9 3 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners NXP Semiconductors N V 2015 All rights reserved User manual Rev 1 19 January 2015 18 of 19 NXP Semiconductors UM10755 10 Contents PTN3355 e DP to VGA bridge IC application board 1 1 EN 2 2 2 3 4 1 4 2 4 3 4 4 5 1 5 2 5 3 6 1 6 2 6 3 7 1 7 2 7 3 9 1 9 2 9 3 10 Introduction oooooooccnnoo oo PUMPOSES ciii a ra i n fe General des
16. formation source outside of NXP Semiconductors In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors an
17. header bringing out 12C pins SCL SDA GND to interface with a 12C Bird dongle to program Flash over 12C and debug e One I2C header for DDC control e One JTAG for FW download One 3V3 power adapter jack e Test point for external power supplies 3 3 V 1A e Option to power from DP connector e Jumper to select between 3 power sources e Two VGA connectors selectable by jumper setting UM10755 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved User manual Rev 1 19 January 2015 6 of 19 NXP Semiconductors U M1 0755 PTN3355 e DP to VGA bridge IC application board 3 Hardware requirements e Item 1 e DP sources of Intel AMD Apple e Item 2 VTG5225 DP or DPT 200 DP sources with DP 1 1 or DP1 0 cable e Item 3 DPA 400 AUX analyzer e Item 4 Different native resolution monitors e Item 5 FS2 with 2x5 JTAG connection for FW download e Item 6 12C Bird with 1x4 header connection for s EEPROM R W 4 Board specifications 4 1 General description e Layers 4 layers expected trace ground VCC trace e Size 3 5 x 4 5 e Material FR4 e Thickness 62 mil e Impedance 50 ohm single end 75 ohm single end RGB 100 ohm differential on DP and AUX signal pairs 4 2 PCB stack ups PCB Stack Up Thickness mil Impedance Single DIFF j gt 0 copper plating 0 70 mils Sp e
18. ing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from competent authorities Evaluation products This product is provided on an as is and with all faults basis for evaluation purposes only NXP Semiconductors its affiliates and their suppliers expressly disclaim all warranties whether express implied or statutory including but not limited to the implied warranties of non infringement merchantability and fitness for a particular purpose The entire risk as to the quality or arising out of the use or performance of this product remains with customer In no event shall NXP Semiconductors its affiliates or their suppliers be liable to customer for any special indirect consequential punitive or incidental damages including without limitation damages for loss of business business interruption loss of use loss of data or information and the like arising out the use of or inability to use the product whether or not based on tort including negligence strict liability breach of contract breach of warranty or any other theory
19. is document is subject to legal disclaimers Rev 1 19 January 2015 UM10755 User manual NXP Semiconductors U M1 0755 PTN3355 e DP to VGA bridge IC application board NO R56 R57 BD28 um10755_pwrext3v3 Fig 10 Power by external 3 3 V power supply 2 of 2 UM10755 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved User manual Rev 1 19 January 2015 14 of 19 enueu sn sLoz lenuer 6L Aen s awIejosip ebaj 0 jos qns s juaunJop SU u papinold uo ELO 6L JO SL SSZOLWN H Pamasa Su Iv G LOZ NN SIOJOMPUOAWIS AN O Stuffing options 7 1 PTN3393 stuffing REMOVE R62 PLACE PVDD33 CURRENT METER ACCROSS VBUCK 1V5 Ci 3v3_10 VDD VDD_3v3 VDDA_8V3 veore VBUCK_iV5 AND J S A 1112 DOUBLE FOOTPRINT FOR Y1 i la hi 9 i vi Lb 2016 AND 3225 een bo gt y 12pF yt PARTS TO TEST 2016 XTAL 1 2 ca 7 cs ig co BM OF i 3225 XTAL ECS 270 20 33 ge FE Ou AE AR
20. o valid DisplayPort source data being transmitted PTN3355 is suitable for Ultra Low Power Notebook and other low power devices PTN3355 also offers a second VGA port for docking design PTN3355 is powered from a 3 3 V power source and generates 1 5 V through an internal step down switch regulator and buck converter for internal core usage and DAC usage For cost saving the external inductor for the buck converter can be removed the internal LDO can supply 1 5 V for core usage and DAC usage without any re work However using LDO consumes twice as much as the buck converter about 400 mW This document describes the user manual of PTN3355 ULT DP VGA application board including e Overall PCB connectors jumpers and power supplies e Equipment Tools that this board will be interfacing with for board testing e System level connections such as cables and connectors that this board will be plugged into This application board is intended to demonstrate the bridging capabilities of PTN3355 on low power DP to VGA conversion Purposes This document is for internal engineers to evaluate the performance of PTN3355 and to develop firmware including collecting and verifying system level features performances functionalities such as e Verify power management schemes e Power sequence e Power consumption measurement during various operating modes e Allow access to test points and jumpers for measurement and configuration purposes e Flash ove
21. r AUX and MS DC e Programming and debug test via MS DC For marketing to demonstrate ULT DP VGA to customers in the field e Functional and interoperability test e This board should be connected to a DP or an eDP source e This board can be powered by an external 3V3 power adapter or e External power supplies with 3 3V 1A or e DP 1 0 cable that carries 3V3 power All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved User manual Rev 1 19 January 2015 3 of 19 NXP Semiconductors U M1 0755 PTN3355 e DP to VGA bridge IC application board For customers to evaluate PTN3355 Use DC to change configuration 2 General description 2 1 Co layout of PTN3355 with PTN3393 This application board is designed to evaluate PTN3393 first then PTN3355 later with component stuffing variation An HVQFN40 socket footprint is reserved in preparation for socket installation to test and program ICs Due to the bulky socket footprint the bulk converter design has to be placed on the back side to be close to PTN3355 Also due to co layout for two ICs extra components are necessary for stuffing option Hence the layout is not optimal as if only PTN3355 is placed without the socket The placement can be dramatically improved in a real application 2 2 Block diagram A KA
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