NB3N3020DTGEVB Evaluation Board User`s Manual
Contents
1. NB3N3020DTGEVB Evaluation Board User s Manual Device Name NB3N3020DTG TSSOP 16 Board Name NB3N3020DTGEVB Description The NB3N3020DTG is a high precision low phase noise selectable clock multiplier The device takes a 5 27 MHz fundamental mode parallel resonant crystal or a 2 210 MHz LVCMOS single ended clock source and generates a differential LVPECL output and a single ended LVCMOS LVTTL output at a selectable clock output frequency which is a multiple of the input clock frequency Three tri level Low Mid High LYCMOS LVTTL single ended select pins set one of 26 possible clock multipliers An LVCMOS LVTTL output enable OE tri states clock outputs when low This device is housed in 5 mm x 4 4 mm narrow body TSSOP 16 pin package See datasheet NB3N3020 D www onsemi com The NB3N3020DTGEVB Evaluation board is designed to provide a flexible and convenient platform to quickly program evaluate and verify the performance and operation of the NB3N3020DTG TSSOP 16 device under test ae a ua W tha CLK2 Semiconductor http onsemi com EVAL BOARD USER S MANUAL Board Features Crystal source or external input clock source SMA One 25 MHz crystal is supplied e A TSSOP 16 NB3N3020DTG device is installed Separate supply connectors for VDD GND and VEE GND SMAGND 0 V banana jacks and Anvil Clips Contents2. O SMAGND 17 9 VEE on 5016 BJ2 Cll VEE SMAGND Da VEE VDD VEE VDD 3S6 ms fd p 2 14 615 C16 C17 c3 C4 cis C2C cs 6 on 7 JJ i 3 a 4 g s 3 SMAGND VEE SMAGND SMAGND SMAGND SMAGND SMAGND SMAGND Place at DUT pin 1 Place at DUT pin 11 Place at DUT pin 15 Figure 9 Schematic http onsemi com 8 NB3N3020DTGEVB APPENDIX 3 BILL OF MATERIALS LAMINATION STACKUP AND ASSEMBLY NOTES BILL MATERIAL Vale Description BJ3 ITT E B E a 1 4 32 THREAD ELECTRONICS C2 C3 C5 C8 C14 C 01ufd 0402 AVX Corporation 04023C103KAT2A CAP CERM 01UF 10 25V X7R 16 018 021 3 C1 C4 C6 C11 C15 01ufd 0603 Murata GRM188R71H103KA01D CAP CER 10000PF 50V 10 X7R C17 019 C20 C22 5 910 9 19 919 9 14 915 SULLINS STCO2SYAN CONN JUMPER SHORTING TIN ELECTRONICS CORP 12 10 J1 J2 J3 J4 J5 J6 J8 Emerson Network 142 0701 801 Johnson SMA Connector Side Launch 99 9 16 917 Power Connectivity Solutions 13 4 J7 J11 J18 J19 SMT KEYSTONE 5016 PC TEST POINT ANVIL COMPACT SMT ELECTRONICS Y1 Crystal Socket BOTTOM Ampere 2 330808 8 RECEPTACLE FOR LEADED CRYSTAL Receptacle 0 013 0 21 30AU Standoff Nylon Standoff o O Standoff 0402 NOTINSTALLED O INSTALLED a R3 R4 R5 R6 R7 AE INSTALLED R8 R11 R15 Top Silkscreen Top Plat
3. Agilent 14534 250 ps 1 Signal Generator Agilent 33250A or HP8133 or or equivalent equivalent 7 Phase noise Analyzer Agilent E5052B or 2 Tektronix TDS8000 Oscilloscope equivalent 3 Power Supply Agilent 6624A or AG6626A DC or equivalent Step 2 Lab Set Up Procedure 4 Digital Voltmeter Agilent 34410A or 34401 or 1 Test Supply Setup equivalent Board and Device Power Supply Connections are 5 Matched Cables gt 20 GHz SMA connectors shown in Table 1 VDD VEE and GND and may Storm or Semflex or equivalent be connected by banana jacks or anvil clip test points Table 1 POWER SUPPLY CONNECTIONS Anvil Clip Banana Jack Test Point Comments VDD VDD1 and VDD2 are shorted by R12 11 SINGLE SUPPLY OPERATION Vpp 3 3 V must be used to sense the outputs LYPECL outputs CLK2 GND 0 0 V Vee 0 0 V and CLK2b must be terminated with 50 Q into a VTT type Single supply operation may be accomplished by current sinking supply of Vpp 2 0 V per Figure 6 High shunting GND SMAGND and VEE DUTGND Input Impedance probes must be used to sense the signal levels and output levels are not shifted but High Impedance Probes et BJ1 BJ1 BJ1 BJ2 J3 NB3N3020 LYCMOS CLE CLK2 LWV PECL High Impedance Probes CLK2b 7 500 S gt R 500 Sinking supply Figure 6 Typical Device Termination Setup and Termination for Single Ended Operation High Impedance Scope or Probes SPLIT SU
4. All Supply pins must be connected for proper operation Negative Supply DUT GND All Supply pins must be connected for proper operation CLK LVCMOS LVCMOS Output LVCMOS Pp VEMOS Output Ss Positive a pin All Supply pins must be connected for proper operation CLK2 2 LVPECL Output True LVPECL Output CLK2b CLK2b LVPECL LVPECL Output Invert LVPECL ps Invert LVPECL Output Positive pins All Supply pins must be connected for proper operation LVCMOS Input Input pin OE2 accepts LYVCMOS levels to control LYVPECL Output CLK2 and CLK2b when LOW forces CLK1 LOW and CLK2b HIGH open pin defaults to HIGH http onsemi com 7 NB3N3020DTGEVB APPENDIX 2 SCHEMATIC SEL2 5 SMAGND VEE jis Die SELi TP_5016 11 T5016 VEE Ba SHH 0 has SMAGND R12 313 9 e a J11 118 VDD VOD VEE VDO 7 SMAGND SELO SMAGND 13 5016 By Ho 50 R7 RS 130 Ohms 82 Ohms E gt 6 4 oO VEE a 2 z WV v c smacno EE y 5 SMAGNOD X1 CLK y C42 CLK2B N N N SMAGND w 5 7 N C41 aig 8 2 a SMAGND ny VEE 33 2 Ohms SMAGND 115 ea g 12 amp C10 0865 R4 0 Ohms R5 0 Ohms l
5. Description Board Features Board Layout Maps Test and Measurement Setup Procedures Appendix 1 Pin to Board Connection Information Appendix 2 Schematic Appendix 3 Bill of Materials Lamination Stackup Figure 1 NB3N3020DTGEVB Evaluation Board Semiconductor Components Industries LLC 2014 January 2014 Rev 2 Publication Order Number EVBUM2063 D GND ANVIL Connector X1 CLK X2 SEL2 NB3N3020DTGEVB BOARD LAYOUT GND Jack Connector VDD ANVIL Connector VDD ANVIL Connectors Kon ny CY OE2 7 saduetr DIS a Fj k Po CLK2 ae CLE TS 3 Me 5 9 ek no a we w BY ere ma Tam CLK2B ct _ u Go lt ir PE S dai 1 z a Dy Je e VEE ANVIL Connector Th J 11 VEE Jack Connector 7 L Figure 2 FRONT Board Layout SELI Figure 3 FRONT Layer Design http onsemi com 2 NB3N3020DTGEVB GND Jack Connector VDD Jack j Crystal Connector sS 2 oe CER s X1 CLK 2 gfi RS i gees CLK gfi S lt SEL2 Sy sas b VEE Jack Ld ra Connector a Va l OEI SELO SELI r Figure 4 BACK Board Layout MADE S E Figure 5 BACK Layer Design http onsemi com 3 NB3N3020DTGEVB TEST AND MEASUREMENT SET UP AND PROCEDURE Step 1 Equipment 6 Time Transition Convertor
6. PPLY OPERATION VDD 2 0 V GND 0 0 V LVPECL outputs CLK2 and CLK2b directly to a 50 Q VEE 1 3 V input impedance counter or oscilloscope or use of Low For offset or split supply operation the VDD supply is Impedance probes per Figure 7 All input and output levels offset 1 3 V to 2 0 V with respect to GND SMAGND and will be offset or shifted 1 3 V The LVCMOS output CLK1 VEE is set to 1 3 V for 3 3 V supply span operation Supply will be properly terminated but also offset or shifted 1 3 V variance is done by adjusting the VEE supply 4570 Split Low Impedance 50 Q probes must be used to sense the supply operation offers the advantage of connecting the signal levels http onsemi com 4 NB3N3020DTGEVB NBSNSO20 L CMOS CLE1 LV PECL F 500 gt CLKa 7 508 Low Impedance Scope or Probe Figure 7 Typical Device Termination Setup and Termination for Split Supply Operation 50 Q Low Impedance Scope or Probes 2 Inputs see Appendix 1 Device Pin to Board Connection Information SINGLE SUPPLY OPERATION VDD 3 3 V GND 0 0 V VEE 0 0 V For a Single Ended input to X1 CLK operation remove the crystal loading caps C41 and C42 and bridge the small topside trace gap from the device input pin to the SMA connector by installing R14 a Zero Q resistor Do not install R16 Do not drive X2 Use a LVCMOS Clock amplitude signal from 2 MHz to 210 MHz which satisfies datasheet VIH a
7. SEL2 may be set to either VDD HI VEE LO or floated open MID to program the output frequency of operation per datasheet Table 2 Jumpers may be removed to drive SELO 1 2 directly with 1 5 V offset datasheet VIH VIL or VIM levels Note SELO 1 2 inputs will default to VDD 2 MID when left floating open All input and output levels will be offset or shifted 1 3 V Inputs OE1 and OE2 may be jumpered to VEE GND for a LOW level DISABLED using J15 OE1 or 112 OE2 If floated open jumper removed pin will default to a HIGH level ENABLED High Impedance probes must be used to sense the signal levels All input and output levels will be offset or shifted 1 3 V http onsemi com 5 NB3N3020DTGEVB 3 Outputs LVPECL outputs CLK2 CLK2b SINGLE SUPPLY OPERATION VDD 3 3 V GND 0 0 V VEE 0 0 V Externally connect LVPECL outputs CLK2 and CLK2b through a 50 Q terminating resistor to a VTT current sinking regulated supply set to VDD 2V per Figure 6 High Impedance probes must be used to sense the signal levels SPLIT SUPPLY OPERATION VDD 2 0 V GND 0 0 V VEE 1 3 V Externally connect LVPECL outputs CLK2 and CLK2b directly to a counter or scope with 50 Q input impedance or use Low Impedance Probes 50 Q per Figure 7 NOTE THE READINGS OF THE OUTPUT VOLTAGE LEVELS WILL BE OFFSET 1 3 V VEE Figure 8 Alternative Device Termination Setup for On Board Termination Alternatively use of a VTT cur
8. contact your local Email orderlit onsemi com Phone 81 3 5817 1050 Sales Representative EVBUM2063 D
9. d for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT N American Technical Support 800 282 9855 Toll Free Semiconductor Website www onsemi com Literature Distribution Center for ON Semiconductor USA Canada P O Box 5163 Denver Colorado 80217 USA Europe Middle East and Africa Technical Support Order Literature http www onsemi com orderlit Phone 303 675 2175 or 800 344 3860 Toll Free USA Canada Phone 421 33 790 2910 Fax 303 675 2176 or 800 344 3867 Toll Free USA Canada Japan Customer Focus Center For additional information please
10. ing Top Metal Inner 1 GND SaaS SSS Bottom Plating SS Inner 2 POWER sg a ae aioe Bottom Silkscreen Figure 10 Lamination Stack http onsemi com 9 NB3N3020DTGEVB ON Semiconductor and are registered trademarks of Semiconductor Components Industries LLC 50110 SCILLC owns the rights to a number of patents trademarks copyrights trade secrets and other intellectual property A listing of SCILLC s product patent coverage may be accessed at www onsemi com site pdf Patent Marking pdf SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intende
11. nd VIL to drive X1 CLK Input tr tf transition edges should be about 250 ps Use a TTC Time transition Convertor such as Agilent 14534 250 ps or equivalent if needed to slow faster edges Termination of a signal generator may be accomplished by placing a 50 Q resistor to GND at location C42 The mounted crystal does not need to be removed for Single Ended input operation For Crystal operation use a fundamental Parallel Resonant crystal see Datasheet section on Recommended Crystal Parameters from 5 MHz to 27 MHz The board is supplied with a thru hole 25 MHz crystal installed but alternatively has the tabs for a surface mount crystal The Crystal mount is located on the back underside of the board and is permanently connected to the device inputs by traces Crystal Load capacitors C41 and C42 of 27 uF are mounted Device frequency is selected by three level inputs SELO SEL1 SEL2 Jumpers J10 SELO J13 SEL1 and J14 SEL2 may be set to either VDD HI VEE LO or floated open MID to program the output frequency of operation per datasheet Table 2 Jumpers may be removed to drive SELO 1 2 directly with spec VIH VIL or VIM levels Note SELO 1 2 inputs will default to VDD 2 MID when left floating open High Impedance probes must be used to sense the signal levels Inputs OE1 and OE2 may be jumpered to VEE GND for a LOW level DISABLED using J15 OE1 or J12 OE2 If floated open jumper removed pin will defaul
12. rent sinking regulated supply may be avoided by populating R6 82 2 and R7 130 Q to terminate CLK2 and populating R2 82 Q and R3 130 2 to terminate CLK2b as per Figure 8 Alternative Device Termination Setup for On Board Termination High Impedance probes must be used to sense the signal levels High Impedance Probes Alternatively LVPECL outputs CLK2 and CLK2b may be terminated on the board by populating R6 82 2 and R7 130 2 to terminate CLK2 and populating R2 82 2 and R3 130 Q to terminate CLK2b as per Figure 6 High Impedance probes must be used to sense the signal levels NOTE THE READINGS OF THE OUTPUT VOLTAGE LEVELS WILL BE OFFSET 1 3 V http onsemi com 6 NB3N3020DTGEVB APPENDIX 1 DEVICE PIN TO BOARD CONNECTION INFORMATION SEE CURRENT DATASHEET Table 2 DEVICE PINS TO BOARD CONNECTION Device Device Pin Board Pin Name Connection Description 1 VDD Positive Supply Positive Supply pin All Supply pins must be connected for proper operation X1 CLK X1 CLK Crystal Oscillator Input from Crystal Single ended Clock Input Interface 3 2 2 Crystal Oscillator Output to drive Crystal Interface SEL2 SEL2 Tri Level Input Frequency select input 2 Tri Level Input Frequency select input 1 SELO SELO Tri Level Input Frequency select input 0 LVCMOS Input Input pin OE1 accepts LVCMOS levels to control CLK1 tri states CLK1 when LOW open pin defaults to HIGH Negative Supply DUT GND
13. t to a HIGH level ENABLED High Impedance probes must be used to sense the signal levels SPLIT SUPPLY OPERATION VDD 2 0 V GND 0 0 V VEE 1 3 V For a Single Ended input to X1 CLK operation remove the crystal loading caps C41 and C42 and bridge the small topside trace gap from the device input pin to the SMA connector by installing R14 a Zero Q resistor Do not install R16 Do not drive X2 Use 1 3 V offset LYCMOS Clock amplitude signal from 2 MHz to 210 MHz which satisfies datasheet VIH and VIL to drive X1 CLK Input tr tf transition edges should be about 250 ps Use a TTC Time Transition Convertor such as Agilent 14534 250 ps or equivalent if needed to supply proper edges Termination of a signal generator may be accomplished by placing a 50 Q resistor to GND at location C42 The mounted crystal does not need to be removed for Single Ended input operation For Crystal operation use a fundamental Parallel Resonant crystal see Datasheet section on Recommended Crystal Parameters from 5 MHz to 27 MHz The board is supplied with a thru hole 25 MHz crystal installed but alternatively has the tabs for a surface mount crystal The Crystal mount is located on the back underside of the board and is permanently connected to the device inputs by traces Crystal Load capacitors C41 and C42 of 27 uF are mounted Device frequency is selected by 3 level inputs SELO SEL1 SEL2 Jumpers J10 SELO J13 5 1 and 114
Download Pdf Manuals
Related Search