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CMX7164 Multi Mode Modem

1. 1 00E 01 Equalised 1 00E 02 Not Equalised S 1 00E 03 1 00E 04 1 00E 05 t H 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 Signal To Noise Ratio dB Figure 83 4 QAM Signal to Noise Performance Equalised and Non Equalised 1 00E 01 Equalised 1 00E 02 Not Equalised 1 00E 03 BER 1 00E 04 1 00E 05 1 00E 06 160 18 0 20 0 220 240 260 280 300 320 340 36 0 Signal To Noise Ratio dB Figure 84 16 QAM Signal to Noise Performance Equalised and Non Equalised 2012 CML Microsystems Plc Page 97 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 1 00E 00 1 00E 01 1 00E 02 BER 1 00E 03 1 00E 04 1 00E 05 200 210 220 230 240 250 260 27 0 280 29 0 30 0 Signal To Noise Ratio dB Figure 85 64 QAM Signal to Noise Performance Equalised and Non Equalised Figure 83 Figure 84 and Figure 85 show that equaliser training improves the received signal performance in all cases 4 QAM 16 QAM and 64 QAM We can see that without equalisation 16 QAM signals have a residual bit error rate even with a high signal level as the non equ
2. Figure 32 Channel Filtered UO Figure 33 Channel Filtered UO Signals Signals with I Q DC Offset Estimate Note The images of receive diagnostic modes shown above are idealised In practice when using the Output and Q Output signals to view diagnostics the transitions between constellation point are not instantaneous Using an analogue oscilloscope is the best way to observe these diagnostic signals See e 11 1 18 Modem Mode and Control 6B write e 11 1 10 Signal Control 61 write 6 4 13 Data Transfer The payload data is transferred to and from the host via the C BUS Command and Rx Data FIFOs each of which provide efficient streaming C BUS access FIFO fill level can be determined by reading the Receive FIFO Level and Modem Command FIFO Level and controlled using FIFO Control 50 write 2012 CML Microsystems Plc Page 43 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 register Interrupts may be provided on FIFO fill thresholds being reached or successful transfer of a block of host requested FIFO data between CMX7164 modem and FIFOs Each FIFO word is 16 bits with the least significant byte LSByte containing data and the most significant MSByte containing control information The control information indicates to the CMX7164 what type or how much data is in the LSByte for example if the byte belongs to a header block or contains only 4 valid
3. Link Quality Detect RY Symbol Raw Mode Data RF Rx VQ nnel Pulse De Mapper Demod ping Filters 4 16 or RY DO Channel Decoder Host E C U Coded Mode Data Beer ue Coded Mode Pw c BAG i Construct Frame E 3 Add Preamble 4 RFTx 1 Q Mod Pulse shaping maar Framesync and Tails lt Raw Mode Data S Link Quality Detect We w Symbol Raw Mode Data gt DE DN Demod Channel Filters Reb Erde Buffer FSK RZ Pulse Channel Decoder y Host Shaping Coded Error Correct 2 uc Filter Mode Data Detect Sr Coded Mode Data SE M Sm e Py Frame Add lt lt RFTx VO Mod CNZM Preamble Framesync Pulse and Tal Raw Mode Data Shaping Filter Figure 3 Fl 1 x Fl 2 x Block Diagram UO Tx and Rx Auto Frame Sync Detect Link Quality Detect T SUDO Raw Mode Data RF Rx Channel Filters Xo e mapper Demod NIP 2 or 4 FSK RV Pulse Channel Decoder o Host Shaping Coded Error Correct 2 UC Filter Mode Data Detect o Coded Mode Data Mod1 Construct M ce 2 Frame Add RFT AOI AX Ki Preamble Mod2 Pulse Wee Raw Mode Data Shaping Filter Figure 4 Fl 1 x Fl 2 x Block Diagram two point Tx with I Q Rx D 7164 FI 1 x Fl 2 x Fl 4 x 9 2012 CML Microsystems Plc Page 12 CMX7164 Multi Mode Modem CMX7164 Signal List GPIOB BOOTEN1 BOOTEN2 DVSS DVDD 3V3 SSOUT2 RESETN GPIOC GPIOD DVSS NC NC NC AVDD IOUTPUTP
4. 66 8 1 7 164AFE2 x Modulation Ee tenta meus 67 8 2 TA6AFE2 x Radio Interface s oreet ene tnn ua 67 8 21 WO Transmit and Q Receive Intertaces sese eee eee eee eee eee 68 8 2 2 Two point Modulation Transmit with UO Receive Interface sese eee eee eee 69 8 3 7164Fl 2 x Formatted Data 4 FSK On sees eee 70 8 4 7164F1 2 x Typical Transmit Performance AA 71 8 5 7164Fl 2 x Typical Receive Performance AA 76 8 5 1 Signal to Noise and Co channel Pertomance sse eee eee eee eee eee eee 76 8 5 2 Adjacent Channel Pertommance eee eee eee eee eee eee eee 80 8 5 8 Receiver Dynamic Range sss sese e sese ee sese eee ee essere enserre ennenen 80 T164Fl 4 x TE EN 9 1 TA64FI A x Modulatlon 5 c pcd er ehe riesen eee he Pre E Rd 81 9 2 7164Fl 4 x Radio Interface neue et tete aci teet er fr fet rer 82 9 2 1 eas BeTa e eee esee be ted rede inei tete tt niae Ree Par ia ER ndi 82 9 3 7164Fl 4 x Formatted Data aooaa aiina annaua aadA A EREE enne tnmen tnmen nn nnne nnn 83 9 4 7164Fl 4 x Receiver Response Equaliser A 84 9 5 7164Fl 4 x Typical Transmit Performance essen 86 9 6 7164Fl 4 x Typical Receive Performance AA 91 9 6 1 Signal to Noise and Co channel Pertomance sese eee eee eee eee eee ee eee 91 9 6 2 Adjacent Channel Pertommance sese eee eee eee eee eee eee 95 9 6 3 Receiver Dynamic Range ss csyxr ses svevszes yst vrss gy svg vye nennen arger nnne nnns 96 9 6 4 Receiver Response Equali
5. H Eye Diagram Deviation Deviation for 3 symbol 2 85 kHz Figure 56 Tx Modulation Spectra 4FSK 19 2kbps 9 6ksymbols s I Q Modulation 2012 CML Microsystems Plc Page 72 D 7164 FI 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 RBW 500 Hz RF Att 30 dB Ref Lvl VBW 5 kHz 0 dBm SWT 1 435 S Unit dBm Modulation Spectrum Comparison of 4 FSK inner trace and 2 FSK outer trace both at 19 2kbps with the same deviation setting in CMX7164 d liau Span 67 kHz CF 450 MHz Meas Signal Ref Lvl SR 9 6 kHz Eye I 0 dBm Demod 2FSK S L SE ZE f N 7 VL d d KI A VAA Eye Diagram A C IY NET A 0 SYMBOLS 4 Figure 57 Tx Modulation Spectra 2FSK 19 2kbps UO Modulation 2012 CML Microsystems Plc Page 73 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 Spectrum Analyser Vector Signal Analyser IC 1 IOUTPUT Mod1 or QOUTPUT Mod2 i CMX7164 E ME RF Signal Generator DC FM Modulation Input Buffer Amplifier if required to drive RF signal generator modulation input Figure 58 Tx Spectrum and Modulation Measurement Configuration for Two point Modulation Using the test system sho
6. Notes 50 Denotes output impedance of the driver of the auxiliary input signal to ensure lt 1 bit additional error under nominal conditions 51 Typical based on 9 6MHz Xtal or external oscillator 52 Guaranteed monotonic with no missing codes 54 Specified between 2 5 and 97 5 of the full scale range 55 Calculated from the line of best fit of all the measured codes 2012 CML Microsystems Plc Page 106 D 7164 FI 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 10 1 4 7164Fl 1 x Parametric Performance Details in this section represent design target values and are not currently guaranteed For the following conditions unless otherwise specified External components as recommended in section 4 Maximum load on digital outputs 30pF Clock source 19 2MHz 0 002 20ppm clock input Tame 40 C to 85 C AVpp DVpp 3 0V to 3 6V Reference signal level 308mV rms at 1kHz with AVpp 3 3V Signal levels track with supply voltage so scale accordingly Signal to Noise Ratio SNR in bit rate bandwidth Input stage gain OdB Output stage attenuation OdB All figures quoted in this section apply to the device when loaded with FI 1 x only The use of other valid Function Images can modify the parametric performance of the device DC Parameters Notes Min Typ Max Unit Supply Current Rx Mode Dilnn 8ksymbols s search for FS 61 10 3 mA Dipp 9 6ksymbols s search for FS 61 10 8 m
7. IOUTPUTN QOUTPUTP QOUTPUTN AVSS DACREF NC 2012 CML Microsystems Plc Description General Purpose I O The combined state of BOOTEN1 and BOOTEN2 upon RESET determine the Function Image load interface The combined state of BOOTEN1 and BOOTEN2 upon RESET determine the Function Image load interface Negative supply rail ground for the digital on chip circuits 3 3V positive supply rail for the digital on chip circuits This pin should be decoupled to DVSS by capacitors mounted close to the supply pins SPI Slave Select Out 2 Logic input used to reset the device active low General Purpose I O General Purpose I O Negative supply rail ground for the digital on chip circuits Do not connect Positive 3 3V supply rail for the analogue on chip circuit Levels and thresholds within the device are proportional to this voltage This pin should be decoupled to AVSS by capacitors mounted close to the device pins Negative supply rail ground for the analogue on chip circuits Do not connect Do not connect Positive 3 3V supply rail for the analogue on chip circuit Levels and thresholds within the device are proportional to this voltage This pin should be decoupled to AVSS by capacitors mounted close to the device pins Differential outputs for channel P is positive N is negative Together these are referred to as the Output When the 7164 FI 1 or FI 2 is in two point modulation mode the
8. Output is used as Mod 1 Differential outputs for Q channel P is positive N is negative Together these are referred to as the Q Output When the 7164 FI 1 or FI 2 is in two point modulation mode the Output is used as Mod 1 Negative supply rail ground for the analogue on chip circuits DAC reference voltage connect to AVSS Do not connect Page 13 D 7164 FI 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 NC NC NC VBIAS IINPUTP IINPUTN ADCREF QINPUTP QINPUTN AUXADC 1 AUXADC2 AUXADC3 AUXADCA AVDD AVSS AUXDAC 1 AUXDAC2 AUXDAC3 AUXDACA DVSS DVCORE DVDD3V3 NC 2012 CML Microsystems Plc Description Do not connect Do not connect Do not connect Internally generated bias voltage of approximately AVpp 2 If Vous iS powersaved this pin will be connected via a high impedance to AVpp This pin must be decoupled to AVss by a capacitor mounted close to the device pins Differential inputs for channel signals P is positive N is negative Together these are referred to as the Input ADC reference voltage connect to AVss Differential inputs for Q channel signals P is positive N is negative Together these are referred to as the Q Input Auxiliary ADC input 1 Auxiliary ADC input 2 Auxiliary ADC input 3 Auxiliary ADC input 4 Positive 3 3V supply rail for the analogue on chip circuit Levels and thresholds within the device are p
9. Notes Min Typ Max Unit XTAL CLK 20 Input Logic 1 70 DVpp Input Logic 0 30 DVpp Input Current Vin DVpp 40 UA Input Current Vin DVss 40 UA C BUS Interface and Logic Inputs Input Logic 1 70 DVpp Input Logic 0 30 DVpp Input Leakage Current Logic 1 or 0 11 1 0 1 0 uA Input Capacitance 7 5 pF C BUS Interface and Logic Outputs Output Logic 1 lop 2mA 90 DVpp Output Logic 0 eo 5mA 10 DVpp Off State Leakage Current 11 1 0 1 0 UA VBIAS 21 Output Voltage Offset wrt AVpp 2 loi lt 1uA 2 AVpp Output Impedance 50 kQ Notes 20 Characteristics when driving the XTAL CLK pin with an external clock source 21 Applies when utilising Vgias to provide a reference voltage to other parts of the system When using VpgiAs as a reference VgiAs must be buffered Vgias must always be decoupled with a capacitor as shown in section 3 PCB Layout Guidelines and Power Supply Decoupling 2012 CML Microsystems Plc Page 103 D 7164 FI 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 AC Parameters Notes Min Typ Max Unit XTAL CLK Input High Pulse Width 30 15 ns Low Pulse Width 30 15 ns Input Impedance at 9 6MHz Powered up Resistance 150 kQ Capacitance 20 pF Powered down Resistance 300 kQ Capacitance 20 pF Xtal Start up Time from powersave 20 ms SYSCLK1 2 Output
10. read register for bit 9 Tx Last Tail 1 Wait until the burst ends The burst has completed with all data and tail bits having been modulated It is now possible to transition to other modes or transmit another burst using the Modem Mode and Control 6B write register The procedure described above can be adapted making transmission of different numbers of bytes bits or coded blocks possible Basic Receive Operation Reception of raw data bytes uses the following procedure C BUS Operation Action Description Write 8000 to FIFO Control 50 write Flush the Command FIFO To ensure that no data is remaining from previous data reception Write 1400 to the Modem Command FIFO Word see Modem Command FIFO Data Control 48 49 and 4A write Select 4 byte data block reception repeat forever Selects blocks of data bytes to be received after frame sync is detected 4 bytes in each at which point the host will be notified This will continue until the mode is changed 2012 CML Microsystems Plc Page 29 D 7164 FI 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 C BUS Operation Action Description Write 0033 to Rx Tracking 66 write Select tracking modes Selects automatic IO dc offset correction and symbol timing tracking Write 0401 to Modem Mode and Control 6B write Start reception Initiates a fr
11. 10 2 12 8 4 8 4 7164Fl 2 x Typical Transmit Performance Using the test system shown in Figure 55 the 7164Fl 2 x internal PRBS generator was used to modulate the RF vector signal generator Some typical results are shown in the following figures The desired deviation was achieved by adjusting the CMX7164 peak deviation using register 61 l Se RF Vector Spectrum Analyser Signal Vector Signal Analyser CMX7164 VQ Generator Q Output Inputs L deg gt O Buffer Amplifiers if required to drive RF signal generator modulation inputs Figure 55 Tx Spectrum and Modulation Measurement Configuration for UO Operation 2012 CML Microsystems Plc Page 71 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 Marker 1 T1 RBW RF Att 30 dB Ref Lvl 13 82 dBm VBW 0 dBm 449 99993387 MHz SWT Unit dBm 49 9999338 4 PWR ACR ACP Jow ATI OI PEP PR G er Hoy OA Wu Gd il Center 450 MHz 7 5 kHz Span 75 kHz Modulation Spectrum EN 300 113 Adjacent Channel measurement for 25kHz channel ACP 72dB limit is 60dB Integration window 16kHz Peak deviation 3 symbol 2 85kHz CF 450 MHz Meas S Ref Lvl SR 9 6 kHz Eye Ref Lvl 0 dBm Demod 4FSK 0 dBm 450 MHz Meas Signal 9 6 kHz Frequency Demod AFSK
12. 257 49 mHz 157 49 maz Pk Amplitude Droop 3 72 dD eym Rhe Factor 0 2953 IQ Offset 4 352 1 IQ fmbaience 1 17 8 Constellation Diagram Receiver filtered Error Vector Figure 72 Tx Modulation Spectra 16 QAM 18ksymbols s UO Modulation into CMX998 2012 CML Microsystems Plc Page 88 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 Marker 1 T1 11 62 dim s XY Ret Lei 30 dBm 449 99742064 Miz Offset REW VBW SWT 14 62 a akda Gei 25 Cencer 450 MHz 6 6 kHz Span 65 KEZ 64 QAM Modulation spectrum with 18ksymbols s Adjacent Channel measurement for 25kHz channel ACP 75dB Integration window 16kHz Figure 73 Tx Modulation Spectra 64 QAM 18ksymbols s UO Modulation into CMX998 For a particular baud rate we can see that the spectral shape and adjacent channel power measurements for each QAM type are almost identical This is to be expected as each is generated using the same filters The average power generated will vary though as each type of QAM used has a different peak to mean ratio and the CMX7164 transmits each with the same peak power 2012 CML Microsystems Plc Page 89 D 7164 Fl 1 x FI 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 Marker 1 T1 RBW 200 Hz RF Att 2
13. 300 113 1 0E 02 404M Blox Typs 7 1 0 03 BER 1 0E 04 1 0E 05 Signal to Noise dB Figure 77 4 QAM Performance with Different Coding Schemes 2012 CML Microsystems Plc Page 92 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 1 0E 02 7 1 0E 03 BER 1 0E 04 Signal to Noise dB Figure 78 16 QAM Performance with Different Coding Schemes 1 0E 02 1 0E 03 BER 1 0E 04 1 0E 05 Signal to Noise dB Figure 79 64 QAM Performance with Different Coding Schemes The required performance of a modem may be assessed in terms of either Bit Error Rate BER or Packet Error Rate PER The performance of both measures is affected by coding type and block size but the PER also depends on the size of the packet Short packets with strong coding will exhibit a much lower PER then a long packet with no coding A comparison of PER vs BER for 4 QAM modulation is shown in 2012 CML Microsystems Plc Page 93 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 Figure 80 based on packets of 182 bytes The same comparisons for 16 QAM and 64 QAM are shown in Figure 81 and Figure 82 respectively Regulatory standards for radio modem designs using the 7164Fl 4 x commonly use either BER or PER to assess the receiver performance Typical BER assessment values are 5 1 or 0 1 whereas PER is most often assessed at 20 It will be observed from Figure
14. 7 80 y H 0 00 0 05 J J 0 18 0 25 0 30 K 0 20 L 0 30 0 40 0 50 Top View L1 0 0 15 P 0 50 T 0 20 Bei NOTE i A amp Bare reference data and do rel uu Y K not include mold deflash or protrusions B S T All dimensions in mm d P E g Angles are in degrees Y B Exposed 2 Index Area 1 Index Area 2 C H ur T B Metal Pad D S A A b gt 2 d BY in L1 L PP o Pint Bahe aronan hea 1 Dot Dot Chamfer Bottom View A Index Area 1 is located directly above Index Area 2 Index Area 2 Depending on the method of lead termination at the edge of the package pull back L1 may be present L minus L1 to be equal to or greater than 0 3mm The underside of the package has an exposed metal pad which should ideally be soldered to the pcb to enhance the thermal conductivity and mechanical strength of the package fixing Where advised an electrical connection to this metal pad may also be required Figure 89 Mechanical Outline of 64 pin VQFN Q1 Order as part no CMX7164Q1 k D C A DIM MIN TYP MAX D A 9 80 10 20 xt B 9 80 10 20 C 1 40 1 60 B E D 11 80 12 20 i E 11 80 12 20 zd H 0 05 0 15 J 0 17 0 27 x L 0 45 0 75 PINT 7 P we T 0 09 0 20 X 0 T Y 11 13 NOTE A amp B are reference data and do not include mold deflash or protrusions All dimensions in mm Angles are in degrees Co Planarity of leads within 0 1mm Figure 90 Mechanical Outline of 64 pin LQFP L9 Order as
15. 80 that a 4 QAM modem using no coding raw mode with 182 byte packets will achieve 20 PER at just over 13dB SNR while 1 BER is achieved at 9 5dB SNR With formatted block type 6 see Table 5 approximately 7dB SNR gives 1 BER and 20 PER It is recommended that designers assess the performance of the 7164Fl 4 x with the correct bit rate coding packet size etc for their particular application having in mind the regulatory requirements that may apply and paying careful attention to the test methods that will be used BER wo w 1 D u n w D oo g v ug u D p S EK 8 3 amp 3 D D u u o u m u m m om m m m m rmm OI 1 n s H ii Signal to Noise dB Figure 80 Comparison of BER and PER for 4 QAM Modulation 2012 CML Microsystems Plc Page 94 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 1 0E 03 BER 1 0E 04 Hu ur RS 88 m m D w ou u w a m m mn 1 um w A Signal to Noise dB Figure 81 Comparison of BER and PER for 16 QAM Modulation 1 0E 02 1 0E 03 BER D 1 0E 04 a u R ow Y om o h o U oo W m w RR 8888 2 0 au d d w Signal to Noise dB Figure 82 Comparison of BER and PER for 64 QAM Modulation 9 6 2 Adjacent Channel Performance The 7164Fl 4 x provides excellent rejection of adjacent signals present on the UO inputs Assessment of the adjacent channel rejection
16. Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 Byte 8 Byte 9 Byte 10 CRCI Byte 11 Q bytes Data Bytes Data Bytes 10 12 Data Bytes Tl a ie aa tri bits FEC TRELLIS CODING DECODING ERROR CORRECTION 4 level symbols Over air gn ccc e 0 geg 0000 0 o em gen 3 SE ed LAST signal INTERMEDIATE BLOCKS oe symbols eeee e e 9000090989 is 24 66 66 66 66 LE FRAME gt PREAMBLE FRAME cf Frame Sync 1 j je 43 3 43 3 1 1 3 3 3 1 3 3 1 3 1 3 1 3 sent first last Symbol Sync at least 24 symbols of 3 3 3 3 sequence Figure 53 Formatted Data Over Air Signal Format The Header block is self contained as it includes its own checksum CRC1 and would normally carry information such as the address of the calling and called parties the number of following blocks in the frame if any and miscellaneous control information 2012 CML Microsystems Plc Page 70 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 The Intermediate block s contain only data the checksum at the end of the Last block CRC2 also checks the data in any preceding Intermediate blocks This c
17. CRC for error detection plus error correction 9 1 7164FI 4 x Modulation The 7164Fl 4 x produces QAM modulation with three options 4 16 or 64 QAM see Figure 65 In each case the signal is Root Raised Cosine filtered The same filter is applied in receive to remove inter symbol interference Due to the way the signal is produced there is no deviation to select instead only the baud rate may be altered This has a direct effect on the signal bandwidth A baud rate of 18ksymbols s is typical of a 25kHz channel spacing and provides QAM Variant Bits per Symbol Base Over air Bit Rate Raw Mode Over air Bit 18ksymbols s Rate 18ksymbols s 4 QAM 2 36kbps 32kbps 16 QAM 4 72kbps 64kbps 64 QAM 6 108kbps 96kbps 4 4 4 e e e e e e da omo da dn da ome din an L og lli a E wa ofa ute of fda che oe of D e LU e D e e e 010101 010100 010000 010001 00000 000000 000100 000101 010 000 0000 0010 e o o o e e e o e e e e 110 100 0100 0110 da da vn da dn in dr vn n win vn vn l de da da du e e e e e e L L e L e e e L 11 01 ad ii cuc 290 ds eminem em ii t de cta 4 QAM Mapping 16 QAM Mapping 64 QAM Mapping Figure 65 QAM Mappings The signal spectrum is identical in bandwidth when using 4 16 or 64 QAM however the peak to mean of each modulation type does vary 4 QAM has a peak to mean of 5 3dB a 0 2 or 3 8dB a 0 35 16 QAM has a peak to mean of 7 8dB a
18. Cartesian Feedback Loop DC Calibration are both available from the CML website www cmlmicro com and should be referred to for a more in depth understanding of the need for dc offset calibration The CMX7164 performs automatic dc offset calibration as either part of a transmit sequence or in a separate calibration stage DC offset calibration determines the dc offset that should be applied to the Output and Q Output signals by the CMX7164 to minimise carrier leakage The results of calibration will be held by the CMX7164 for use in later transmissions and are made available to the host The interface is required to be as shown in Figure 19 CMX998 DC Calibration Interfaces a Input A Output lt Q Input A Q Output DCMEAS B AuxADC2 gt CMX998 CMX7164 SPI Thru Port uc pum In C Chip Sel SSOUT1 PA Cnr D AuxDAC RAMDAC a A The CMX7163 and Q Outputs are used to provide dc levels which are adjusted to make the error I Q measurements equal to the Reference UO measurements B AuxADC2 is used to sample DCMEAS To measure Reference signals and error signals C The SPI Thru Port is used to control the CMX998 selecting Reference 1 Q and Error UO as measurements as well as high gain low gain modes of the CMX998 D The RAMDAC is typically used to ramp up the PA Control voltage after calibration is complete This is not a part of the calibration sequence but may be active as part o
19. DVSS i BOOTEN2 nic DVpp i DVSS pvpp 3 3v Dies 1 DVDD 3 3V DVCORE 1 8V i SSOUT2 DVSS 1 C20 C21 22248 eS C28 m C22 T RESETN appen AUXDACA y II 3 Dies DVss GPIOC AUX DAC3 j DVss Dies Dies EE S AERE GPIOD AUX DAC2 Se DVss DVSS AUX DAC1 AVpp scm SSS sim aaa aE ae AVSS AVDD 3 3V AVDD 3 3V i 3s AVSS AUX ADC4 C23 Ca nic AUX ADC3 Ass Ce ego nic AUX ADC2 Aas Ass Ass i AVDD 3 3V AUX ADG AVpp 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AVss i i a ajz o u a z uja z QJBHHEEE SBHBE EE EIE 2 GEES 8 e e a j Elele i ziele i C31 Analogue Ground Plane i Ass AVss i 1 Ue Send ot ACELERAR LER T EM LEVE C20 10uF C26 22uF C21 10nF C27 10nF C22 10nF C28 10nF C23 10uF C29 10uF C24 10nF C30 10nF C25 10nF C31 100nF Figure 5 CMX7164 Power Supply and De coupling Notes To achieve good noise performance AVpp and Voss decoupling and protection of the receive path from extraneous in band signals is very important It is recommended that the printed circuit board is laid out with a ground plane in the CMX7164 analogue area to provide a low impedance connection between the AVSS pins and the AVpp and Vous decoupling capacitors 2012 CML Microsystems Plc Page 16 D 7164 Fl 1 X FI 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 4 External Components 4 1 Xtal Interface XTAL CLOCK C1 50 C2 49 X1 For frequency range s
20. Here the device is in receive and searching for a frame M Yes Sync as well as I note Carrier sense begins a monitoring RSSI Carrier sensing oe Yes IRQ FS Received Y Rx Process No A Yes IRQ CS abort No Tx Process Yes 2012 CML Microsystems Plc IRQ FS Received Yes Y Rx Process Figure 17 Carrier Sense Page 36 D 7164 Fl 1 x FI 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 6 4 10 The Transmit Sequence The CMX7164 is capable of being configured to provide the following features 1 Selecting Tx mode results in transmission starting directly on entry to Tx mode or is delayed until GPIOA is used as an input trigger 2 Selecting carrier sense mode will result in behaviour as in point 1 followed by a carrier sense period where transmission is delayed reception continues until a carrier sense period is completed and no activity is sensed on the channel 3 Selecting Tx calibration will cause CMX998 cartesian loop dc calibration to be carried out prior to transmission as part of the programmable transmit sequence See section 6 4 11 CMX998 DC Offset Calibration for details 4 Once started transmission can be configured to be a simple modulation output or can include a programmable sequence of events including RAMDAC ramp
21. I Q Transmit Only sees eee eee eee eee 37 6 4 12 Other Modem Modes AAA 39 6 4 19 Data Transter i ce I eee t e Ret De be oo leeks ERR CER ERR eee RS die 43 6 4 14 Data B utferltig 6a at e e te De ERE HU RE eR ena 45 6 4 15 Raw RRR TL eode mt on Er oo leeks ge pore ate 46 6 4 16 Formatted Data Transfer 46 6 4 17 Pre loading Commande nennen nnne enne 46 6 4 18 GPIO Pin Operation 46 6 4 19 Auxiliary ADC Operation 46 6 4 20 Auxiliary DAC RAMDAC Operation 47 2012 CML Microsystems Plc Page 4 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 7 8 9 10 09 42 T1 SEI Tint E GE 47 6 422 SPI C BUS AGO HTH 48 6 5 Digital System Clock Generator 50 6 5 1 Main Clock Operation 50 6 5 2 System Clock Operation 51 6 6 Signal Level Optimisation sese eee eee eee 52 6 6 1 Transmit eg ul 52 6 6 2 Receive Path ETT 52 6 7 C BUS Register Gummam eene nnnm enne nnns 53 7164F1 1 x a 54 7 1 ALE Tei EE Ae TE le IER 54 7 2 7164Fl 1 x Radio Interface seiv ea dania niia a aranea ta ERAAN eene nnne nennen 54 7 2 1 WO Transmit and UO Receive Interfaces 54 7 2 2 Two point Modulation Transmit with UO Receive Interface 55 7 3 7164Fl 1 x Formatted Dallasiin ins aane iaiia ener nnne nennen 57 7 4 7164Fl 1 x Typical Transmit Performance A 58 7 5 7164Fl 1 x Typical Receive Performance AA 63 7 5 1 Signal to Noise and Co channel Pertomance sse eee eee eee eee eee eee 63 TIG4FI 2 X Features
22. Output accordingly ErrorlHi Read Errorl assuming High gain and adjust the Output accordingly Iterate go to ErrorQHi after a delay for corrected signals to settle Tidyup Restore the CMX998 to its stage pre calibration ready to output modulation Note Despite no modulation being produced the Tx Done flag of IRQ Status 7E read register will be set at the completion of the CMX998 DC Offset Calibration task The timings of each calibration step can be configured using Program Block 5 Burst Tx Sequence To reduce calibration time a calibration sequence may be configured that omits some stages of the calibration process However there must always be a Setup and TidyUp stage and if ErrorQHi and ErrorlHi are included then the high gain stage must be included as well The registers used during Tx dc offset calibration are 11 1 18 Modem Mode and Control 6B write 11 2 7 Program Block 5 Burst Tx Sequence 11 1 30 I Q Offset 75 76 read 11 1 8 UO Output Control 5D 5E write 6 4 12 Other Modem Modes Tx Preamble In Tx mode a transmit preamble feature is provided to aid setup the preamble may be programmed to any useful repeating 8 bit pattern 2012 CML Microsystems Plc Page 39 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 Tx PRBS In Tx mode a fixed PRBS pseudo random bit sequence or a repeated preamble transmission is provided and may be used for test and alignment A 511 bit PR
23. T R Radio Receiver Receive Processing QINPUT H Transmit Processing IOUTPUT QOUTPUT MOD1 MOD2 Reference Y e g VCTCXO IL 65 2 I LD Control veo Voltage Input Figure 10 CMX7164 Two point Tx I Q Rx 2012 CML Microsystems Plc Page 21 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 6 Detailed Descriptions 6 1 Xtal Frequency The CMX7164 is designed to work with a Xtal or an external frequency oscillator within the ranges specified in section 10 1 3 Operating Characteristics Program Block 1 see User Manual must be loaded with the correct values to ensure that the device will work to specification with the user selected clock frequency A table of configuration values can be found in Table 13 supporting baud rates up to 20ksymbols s when the Xtal frequency is 9 6MHz or the external oscillator frequency is 9 6 or 19 2 MHz Rates other than those tabulated within this range are possible see section 11 2 3 Program Block 1 Clock Control Further information can be provided on request The modem can operate with a clock or Xtal input frequency tolerance of 50ppm The receive performance will be compromised as the system tracks so a maximum tolerance of 20ppm is recommended 6 2 Host Interface A serial data interface C BUS is used for command status and data transfers between the CMX7164
24. a frame sync the gain will also be backed off when the signal is considered large this ensures that after frame sync is detected there is headroom for the amplitude to increase a little If the signal is sensed to be small for a period of time the gain can also be increased The threshold for what is considered a small or large signal requiring a gain change the time for which it should remain small and the time to allow a gain adjustment to take effect is programmable The overall system is shown below HOST uP X CMX7164 NG RF Receiver IC Input TR Nj A Clip Level X Sense Q Input p Local Oscillator Baseband Gain Local ro Quadrature Control Register AGC Gain C BUS Control SEIT Port Step Select LNA Gain Control Registers C BUS control of external Register devi Figure 35 AGC using SPI Thru Port Controlling the external device as shown in Figure 35 causes the gain to step suddenly This in itself may cause a short burst of errors so once signal is being received it may be desirable to ensure that the gain is not changed unnecessarily This is typically the case with short bursts of data where it is likely that the signal amplitude will remain constant throughout the burst To help achieve this various AGC automatic modes are provided o Manual Gain Controlled manually always allowing
25. bits The control and data bytes may be written or read together using the Receive FIFO Word and Modem Command FIFO Word registers or individually using their byte wide registers Word wide FIFO writes involve writing 16 bit words to the Modem Command FIFO Word register using either a single write or streaming C BUS The whole word written is put into the Command FIFO with the upper byte interpreted as control and the lower byte as data This causes the control byte to be held in the Command FIFO Control Byte register Byte wide FIFO writes involve writing to the Modem Command FIFO Data Byte register using either single access or streaming C BUS This causes the Modem Command FIFO Control Byte MSByte and data written to the Modem Command FIFO Data Byte LSByte registers to be put into the command FIFO as one word The control byte can be written separately as a single byte this does not result in anything being added to the FIFO or is preserved from a previous 16 bit Modem Command FIFO Data Byte write Likewise a word read from the Rx Data FIFO will return the Receive FIFO Control Byte in the MSByte and the Receive FIFO Data Byte at the top of the FIFO in the LSByte Both registers will be updated so that when read next time they will provide details of the next item in the FIFO Reading the Receive FIFO Control Byte only will not change the FIFO content Reading the Receive FIFO Data Byte only will provide the data and remove the item from the FI
26. e Added information about receive dynamic range e Corrected and clarified scaling of Tx output fine control 2012 CML Microsystems Plc Page 9 D 7164 FI 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 3 e Remove information indicating that a reset with no FI load is possible See 15 4 11 sections 11 1 1 Reset Operations 7 3 Function image loading e FIFO level interrupts to the host require re arming using 50 FIFO control See 11 1 4 FIFO Control 50 e Include description for UO Input dc correction loop gain See 11 1 10 Signal control 61 e Spectrum figure ACP mislabeled as for 25kHz when it is for 12 5kHz See fig 58 e Expand description of Fl 2 4FSK deviation configuration See 11 1 10 Signal control 61 e Include over air symbol sequence for FI 2 2FSK and 4FSK and FI 4 data See 7 4 15 11 1 3 and 11 1 26 Specifically this matters for bit wise transfers indicating which bits are valid e Default values in 11 1 9 to be changed 07FF becomes 0400 0801 becomes 0C00 e Addition of Tx Done flag set on completion of DC Calibration to 7 4 11 11 1 18 and 11 1 36 Also indicate that AuxADC paths etc in 7 4 11 are fixed permanently by changing the description assumed to required e Figure 34 to show Main PLL out sourced directly from the Xtal in Idle mode e Update Figure 3 and correct minor typographical errors Fig 43 2 e Clarify text at the end of section 12 3 2 22 3 11 e Change b11 to
27. for details 9 Note that the CMX7164 provides significant channel filtering itself but further rejection of unwanted signals is desirable in most applications to improve receiver dynamic range and prevent blocking or products generating intermodulation products reaching the low power back end of the receiver 2012 CML Microsystems Plc Page 84 D 7164 FI 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 Figure 68 Received 4 and 16 QAM signals no equalisation Figure 69 Received 4 and 16 QAM signals with equalisation Results when using the Receiver Response Equaliser are shown in section 9 6 4 Receiver Response Equaliser Performance See e 11 1 18 Modem Mode and Control 6B write e 11 2 13 Program Block 11 Receiver Response Equaliser Fl 4 x only e 13 9 Fl 4 x Receiver Response Equaliser Training Sequence 2012 CML Microsystems Plc Page 85 D 7164 Fl 1 x FI 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 9 5 7164Fl 4 x Typical Transmit Performance The 7164Fl 4 x transmits QAM modulation using an UO interface The modulation may be evaluated using a test system as illustrated in Figure 70 Tx Spectrum and Modulation Measurement Configuration for UO Operation Output O Spectrum Analyser pec Sm CMX998 Vector Signal Analyser CMX7164 vq Transmitter Board Q Output Inputs gt Figure 70 Tx Spectrum and Modulation Measurement Configuration for UO
28. held low during a data transfer and kept high between transfers The C BUS interface is compatible with most common uC serial interfaces and may also be easily implemented with general purpose uC I O pins controlled by a simple software routine Section 10 2 C BUS Timing gives detailed C BUS timing requirements Note that due to internal timing constraints there may be a delay of up to 60us between the end of a C BUS write operation and the device reading the data from its internal register 2012 CML Microsystems Plc Page 22 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 C BUS single byte command no data CSN SCLk IIIIIIIIIIIIIIIT e CDATA 7 6 5 4 3 2 140 MSB Address LSB RDATA Hi Z C BUS n bit register write CSN Note The SCLK line may be high or low at the start and end of each transaction Steet ee eee SCLK CDATA 7 le 5 4 S3 2 1 0 n 1 n 2 n 3 2 1 o0 MSB Address LSB MSB Write data LSB RDATA Hi Z C BUS n bit register read CSN SCLK IIIIIIITIIIIIIIII Ls TUUL CDATA 7 6 5 4 3 2 1 0 MSB Address LSB RDATA Hiz ndln2 n3 2 1 0
29. input from the uC C BUS chip select input from the uC wire Orable output for connection to the Interrupt Request input of the uC This output is pulled down to DVsg when active and is high impedance when inactive An external pull up resistor is required Internally generated digital core voltage of approximately 1 8V This pin should be decoupled to DVss by capacitors mounted close to the device pins SPI Master Out Slave In SPI Slave Select Out 1 SPI Master In Slave Out SPI Slave Select Out 0 SPI Serial Clock General Purpose I O On this device the central metal pad which is exposed on the Q1 package only may be electrically unconnected or alternatively may be connected to Analogue ground AVss No other electrical connection is permitted Notes IP Input PU PD internal pull up pull down resistor of approximately 75kQ OP Output BI Bidirectional TSOP 3 state Output PWR Power Connection NC No Connection should NOT be connected to any signal 2012 CML Microsystems Plc Page 15 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 3 PCB Layout Guidelines and Power Supply Decoupling Digital Ground Plane 2 S j DVss DVss C BUS f S wc i z G E E E S aja E x d 2 i lt 3 gl 3 a S z 2 3 3 51 B Bl a 2 i Active low reset from 3 3B E 3 E 8 g 8 o g S S S S S i 1 supervisor IC or RC circuit Se a 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DUSS j DVpp BOOTEN1
30. interfering signal is used as it is specified in ETSI standard EN 300 113 for co channel tests 1 00E 01 B 1 00E 02 a 1 00E 03 8 8 2 8 4 8 6 8 8 9 9 2 9 4 9 6 9 8 10 Co Channel Rejection dB Figure 63 Modem Co channel Rejection with FM Interferer as EN 300 113 2012 CML Microsystems Plc Page 79 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 8 5 2 Adjacent Channel Performance The 7164 FI 2 x provides excellent rejection of adjacent signals present on the UO inputs Assessment of the adjacent channel rejection ACR performance of the modem is normally made in terms of BER or PER for a given ratio between the wanted signal on channel and larger interferer on the adjacent channel Detailed measurement methods vary depending on the standards in use in particular whether the wanted signal is raised above the sensitivity limit and where the reference is taken The figures quoted here are based on the measurement method from EN 300 113 The BER curve shown in Figure 64 is based on the difference between the interferer 400Hz FM modulation 1 5kHz deviation and the power of the wanted signal for 4 8ksymbols s 1 00E 02 B 1 00E 03 a 1 00E 04 60 61 62 63 64 65 66 67 68 Adjacent Channel Rejection dB Figure 64 ACR Rejection Performance The results in Figure 64 are typical of what may be achieved with 7164Fl 2 x and a typical UO radio receiver with
31. mode when not actively processing signals The device includes a Xtal clock generator with phase locked loop and buffered output to provide a System Clock output if required for other devices Block diagrams of the device are shown in section 2 Block Diagrams Tx Functions Automatic preamble and frame sync insertion simplifies host control UO analogue outputs 7164F1 4 HO or two point modulation analogue outputs 7164 FI 1 or FI 2 Pulse shape filtering RAMDAC capability for PA ramping control Tx trigger feature allowing precise control of burst start time Tx burst sequence for automatic RAMDAC ramp and Tx hardware switching Carrier sense for listen before talk operation Raw and formatted channel coded data modes Flexible Tx coded data block size up to 416 bytes 7164FI 4 12 bytes 7164Fl 2 18 bytes 7164FI 1 Rx Functions e Automatic frame sync detection simplifies host control UO analogue inputs Rx channel filtering and pulse shape filtering Channel estimation and equalisation Tracking of symbol timing and input UO dc offsets AGC using SPI Thru Port Raw and formatted channel coded data modes Flexible Rx coded data block size up to 416 bytes 7164FI 4 12 bytes 7164FI 2 18 bytes 7164FI 1 Auxiliary Functions e Two programmable system clock outputs e Four auxiliary ADCs with six selectable input paths e SPI Thru Port for interfacing to synthesisers Cartesian loop IC CMX998 direct conversion receiver C
32. or Signal Control 61 write registers This should be sufficient for most applications however if additional filtering is required it can be done at the input to the device The input impedance of the UO Input pins varies with the input gain setting see section 10 1 3 Operating Characteristics 4 5 GPIO Pins All GPIO pins are configured as inputs with an internal bus hold circuit after the Function Image has been loaded This avoids the need for users to add external termination pullup pulldown resistors onto these inputs The bus hold is equivalent to a 75kQ resistor either pulling up to logic 1 or pulling down to logic 0 As the input is pulled to the opposite logic state by the user the bus hold resistor will change so that it also pulls to the new logic state The internal bus hold can be disabled or re enabled using programming register P1 20 in Program Block 1 Clock Control 2012 CML Microsystems Plc Page 18 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 5 General Description 5 1 CMX7164 Features The CMX7164 is intended for use in half duplex modems Transmission takes the form of a data burst consisting of preamble frame sync and data payload followed by a tail sequence Reception may utilise the preamble to assist with signal acquisition but is then followed by frame sync detection and data decoding A flexible power control facility allows the device to be placed in its optimum powersave
33. root raised cosine filtered with a 0 2 0 35 or a user programmable filter contact CML Technical Support for further information The 7164Fl 4 x supports up to 96kbps in a 25kHz channel with channel estimation and equalization to provide robust performance under realistic channel conditions The 7164FI 4 x supports zero IF I Q transmit and receive QAM data is over air compatible with the CMX 7163FI 4 x Within this Datasheet and the accompanying User Manual any reference to Fl1 x Fl 2 x or Fl 4 x is intended to refer to 7164Fl1 x 7164Fl 2 x or 7164FI 4 x respectively Forward error correction and raw modes are available and support user defined packet structures to support a range of applications For greater flexibility in Fl 4 x only different rate FEC modes are provided Receive signal quality measurement is supported making a useful assessment of link conditions High performance digital IF filters may be reconfigured to support multiple channel spacings via host command This feature may eliminate the need to switch between multiple discrete IF filters An integrated analogue interface supports direct connection to zero IF UO radio transceivers with few external components no external codecs are required 2012 CML Microsystems Plc Page 2 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 Intelligent auxiliary ADC DAC and GPIO sub systems perform valuable functions and minimise host interaction and ho
34. signal is used as it is specified in ETSI standard EN 300 113 for co channel tests 1 00E 01 1 00E 02 4 1 00E 04 3 5 4 4 5 Co Channel Rejection dB Figure 49 Modem Co channel Rejection with FM Interferer as EN 300 113 8 7164Fl 2 x Features The 7164Fl 2 x uses a 2 or 4FSK modulation scheme with a configurable over air bit rate up to 20kbps ie 10ksymbols s In each case the modulating signal is root raised cosine filtered with a filter alpha of 0 2 Raw data can be transferred in addition to formatted data blocks Formatted data blocks may be of variable length up to 12 bytes and support a combination of 16 bit or 32 bit CRC for error detection plus trellis coding for error correction The modulation scheme and coding is designed to produce a signal that is over the air compatible with the CML FX MX919B and CMX7143 7143F1 2 x modems 2012 CML Microsystems Plc Page 66 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 8 1 7164Fl 2 x Modulation The 4FSK scheme running at 2 4ksymbols s 4 8kbps can be used to fit inside a 6 25kHz channel bandwidth a rate of 9 6ksymbols s 19 2kbps can be used in 25kHz bandwidth channels Similarly the 2FSK scheme running at 2 4ksymbols s 2 4kbps can be used to fit inside a 6 25kHz channel bandwidth a rate of 9 6ksymbols s 9 6kbps can be used in 25kHz bandwidth channels A 12 5kHz channel bandwidth is possible with data rates in between these extremes Cha
35. the Function Image is loaded the CMX7164 can be set into one of four main modes using the Modem Mode and Control 6B write register Idle mode for configuration or low power operation Transmit mode for transmission of raw or formatted data Receive mode for detection and reception of bursts containing raw or formatted data Carrier sense mode for attempting to transmit if the channel is free otherwise continuing to receive These four modes are described in the following sections All control is carried out over the C BUS interface either directly to operational registers in transmit receive and carrier sense modes or for parameters that are not likely to change during operation using the Programming Register 6A write in Idle mode To conserve power when the device is not actively processing a signal place the device into Idle mode Additional power saving can be achieved by disabling unused hardware blocks however most of the hardware power saving is automatic Note that Vgias must be enabled to allow any of the Input or Output blocks to function It is only possible to write to the Programming register whilst in Idle mode See 11 1 17 Programming Register 6A write 11 1 18 Modem Mode and Control 6B write 11 2 Programming Register Operation 11 1 24 VBIAS Control B7 write 6 4 4 Normal Operation Overview In normal operation after the CMX7164 is configured the appropriate mode must be selected and data p
36. the bandwidth occupied This relationship can be used to select the maximum baud rate for a given channel bandwidth 2012 CML Microsystems Plc Page 90 D 7164 Fl 1 X FI 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 9 6 7164FI 4 x Typical Receive Performance 9 6 1 Signal to Noise and Co channel Performance The performance of the 7164Fl 4 x when receiving is shown in the following graphs It should be noted that error rate performance depends on the modulation rate whether 4 QAM 16 QAM or 64 QAM is in use the coding type selected and the block size The 7164Fl 4 x supports multiple combinations of these factors and it is beyond the scope of this document to provide data for every combination however graphs are provided showing a selection of representative cases ranging from best case performance maximum coding and block size to worst case where no coding is used raw mode Formatted block types 0 6 and 7 See Table 5 and section 9 3 7164Fl 4 x Formatted Data for details show different levels of error correction performance formatted block type 7 giving the best performance see Table 5 In all of the following graphs Figure 75 Figure 82 the data rate is 18ksymbols s which is typical of the rate that may be achieved in a 25kHz RF channel The selected transmit and receive filters had a 0 2 The signal to noise ratio is calculated as SNR Mean signal power 174 NF 10 logio RxBW Where NF receiver noise
37. up down and GPIO On Off Each of these operations can be selected independently of the others The following diagram illustrates transmit operation Time Modem Control Mode Mei Mode CS or Tx Reception l l 8 Active if mode CS Inactive if Active High nada Carrier Sense Tx Trigger Input GPIOA Tx on Outputs i l GPIOA D E i RAMDAC E c Output 1 Modulation Preamble Data Tail Out N Sync Payload Bits Transmit d Calibration Cal Awaiting Tx Carrier Sense CMX9 Receive GPIOA if cause abort to Offset on off if configured Configured Rx at any point Cal 9 Figure 18 Transmit Sequence 6 4 11 CMX998 DC Offset Calibration UO Transmit Only When transmitting in UO mode the CMX7164 may be interfaced to a CMX998 Cartesian Loop IC The CMX998 is used to provide linearisation of the power amplifier used to transmit the modulation produced by the CMX7164 If the signal produced by the CMX7164 when no modulation is present does not exactly 2012 CML Microsystems Plc Page 37 D 7164 FI 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 match the dc reference of the CMX998 carrier leakage will result This worsens the transmitted signal quality DC offset calibration is intended to significantly reduce the carrier leakage The CMX998 Cartesian Feedback Loop Transmitter datasheet and an application note CMX998
38. write 11 1 8 Modem Command FIFO Data Control 48 49 and 4A write 11 1 26 Receive FIFO Data Control 4C 4D 4E read 11 1 25 Modem Command FIFO Level 4B read 11 1 27 Receive FIFO Level 4F read 11 1 4 FIFO Control 50 write Note The Command FIFO and Command Buffer will automatically be flushed when a carrier sense attempt to transmit results in the CMX7164 reverting to receive mode This is to avoid accidentally processing transmit commands pre loaded by the host as receive commands This is the only situation in which the FIFOs or buffers will be flushed other than by direct host instruction 6 4 14 Data Buffering To expand the buffering capabilities of the CMX7164 two internal buffers are provided A Command buffer which buffers commands from the control FIFO which are yet to be processed An Rx data buffer which buffers received data yet to be loaded into the Rx data FIFO Transfer between the FIFOs and their respective buffers will occur during transmission reception and Idle mode Such transfer is not instantaneous so the FIFO fill levels should be used to indicate how much data the host may read or write at any time The Internal Buffer Fill Level 70 read register allows the buffer fill levels to be read their contents will be flushed when the respective FIFO is flushed See e 11 1 4 FIFO Control 50 write e 11 1 28 Internal Buffer Fill Level 70 read 2012 CML Microsystems Plc Page 45 D 7164_Fl 1
39. x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 Note The Command FIFO and Command Buffer will automatically be flushed when a carrier sense attempt to transmit results in the CMX7164 reverting to receive mode This is to avoid accidentally processing transmit commands pre loaded by the host as receive commands This is the only situation in which the FIFOs or buffers will be flushed other than by direct host instruction 6 4 15 Raw Data Transfer When transferring raw data the FIFO Control byte indicates the amount of data that will be transferred in a block before the CMX7164 interrupts the host Byte and bit wise transfers are possible providing the facility to transmit or receive a burst of arbitrary length not just a whole number of bytes It is suggested that data is transferred in the maximum size blocks possible until the end of a burst where the remaining bits or bytes can be transferred in a single transaction of the required size When using byte wise or bit wise transfers the most significant bit of the data byte is transmitted or received first When using bit wise transfers with a bit count of less than 8 the most significant bits are used In all cases the bits are combined into symbols according to the selected modulation type It is also possible to ignore the concept of blocks of data whilst in raw mode Instead a transmission can just be treated as a series of bytes to transmit and FIFO levels level IRQs used to ma
40. 0 SYSCLK1 DIVIDER SYSCLK1 SYSCLKDIV1 b11 6 SYSCLK2 DIVIDER SYSCLK2 Q SYSCLKDIV1 b12 SYSCLKCON b5 4 Figure 38 Digital System Clock Generation Schemes See e 11 2 3 Program Block 1 Clock Control 2012 CML Microsystems Plc Page 51 D 7164 FI 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 6 6 Signal Level Optimisation The internal signal processing of the CMX7164 will operate with wide dynamic range and low distortion only if the signal level at all stages in the signal processing chain is kept within the recommended limits For a device working from a 3 3V supply the signal range which can be accommodated without distortion is specified in 10 1 3 Operating Characteristics Signal gain and dc offset can be manipulated as follows 6 6 1 Transmit Path Levels For the maximum signal out of the UO Outputs the signal level at the output of the modem block is set to be OdB the Fine Output adjustment has a maximum attenuation of 6dB and no gain whereas the Coarse Output adjustment has a variable attenuation of up to 14 2dB and 6dB gain The signals output from Output and Q Output may be independently inverted Inversion is achieved by selecting a negative value for the linear Fine Output adjustment When transmitting UO format signals inverting one of the UO pair has a similar effect to swapping with Q DC offsets may be added to the signal however care must be taken that the combin
41. 0 2 or 6 4dB a 0 35 64 QAM has a peak to mean of 9dB 020 2 or 7 5dB a 0 35 The difference between the base over air rate and the raw mode rate which is the actual user data rate in raw mode at 18ksymbols s is due to some symbols being used internally by the modem to perform channel equalisation A further implication of this is that any transmission must contain a multiple of 16 symbols the CMX7164 will automatically pad as necessary 2012 CML Microsystems Plc Page 81 D 7164 FI 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 9 2 7164Fl 4 x Radio Interface QAM modulation requires control of both phase and amplitude in the transmitter and to measure both phase and amplitude in the receiver Therefore the 7164Fl 4 x offers UO transmit and UO receive interfaces This is shown in Figure 66 using the CMX992 for reception and the CMX9988 for transmit with RF power amplifier linearisation The internal functions of the CMX7164 when operating in this mode are shown in Figure 2 HOST S E Au ME ciere ed tee t t cacao Tis estera GPIOn uP I i I CAE 7 t NS Tap LNAEnable 1 A CMX7164 m i GH e l e lel GPIO d X HE ol re LNA LO 2x ADC C BUS Q0 Q Input A CMX992 A Thru C BUS
42. 0 dB e Lvl 6 40 dBm VBW l kHz 30 dBm 445 55742084 MHz SWT 4 2 s Unit dBm 30 31 dB Offset Y GK MD 16 QAM Modulation spectrum 445 997421084 MHz E CHEW To Bm with 9ksymbols s ACH Ug 76 56 Op 1o ACH 74 20 a Adjacent Channel measurement for 12 5kHz channel D x ACP 76dB 10 exr Integration window 8kHz 20 40 50 co co ell A 9 eu 70 Center 450 MHz 3 35 kHz Span 33 5 kHz R er aso Nn neas OD ar avn US RR Cansvellacion Z Ret Lv SR 9 Vecto ac aua Denod 160AM 35 dbi Demod 1 5 31 aD Otfsec TL BURST NOT FOUND REA 1 97 Constellation Diagram Receiver filtered a 1666667 NOT FOUND REAL 4 166666 ext cr 450 MHz Pel iul sp 9 KNS SymbolsEcrors a5 dba Desod Le0An 31 an offeec Symbol Table o 00100011 01101110 11000112 01101100 00000010 ao 00011100 11000010 10100000 01110000 00111111 n Sp 12100010 110010601 000000131 00001011 061910101 Error Summary Error Veetor Mag 2 49 4 tms 5 71 4 Pk ac syn o Magnitude Error 1 56 4 ems 4 51 Pk at syn o Phaze Error 1 71 deg rna 5 62 deg Pk at syn 124 Freq Error 81 54 wHz 81 54 mHr Pk Amplitude Droop 9 02 db sym Rho Factor 0 9991 IQ Offset 0 25 1 IQ Imbalance 6 97 amp Error Vector Figure 74 Tx Modulation Spectra 16 QAM 9ksymbols s UO Modulation into CMX998 Comparing Figure 72 and Figure 74 demonstrates that changing baud rate simply scales the transmitted spectrum halving baud rate will halve
43. 4 x only The use of other valid Function Images can modify the parametric performance of the device DC Parameters Notes Min Typ Max Unit Supply Current Rx Mode Dilnn 9 6ksymbols s search for FS 80 15 7 to 21 0 mA Dipp 18ksymbols s search for FS 80 24 1 to 34 1 mA Dipp 9 6ksymbols s FS found 11 0 mA Dipp 18ksymbols s FS found 15 4 mA Alpp AVpp 3 3V 7 7 mA Tx Mode 81 Dipp 9 6ksymbols s 7 5 mA Dipp 18ksymbols s 11 1 mA Alpp AVpp 3 3V 8 0 mA Notes 80 A lower current is measured when searching for Framesync1 a higher current is measured when doing automatic modulation detection 81 Transmitting continuous 16 QAM PRBS all GPlOs and RAMDAC set to manual 2012 CML Microsystems Plc Page 111 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 AC Parameters Notes Min Typ Max Unit Modem Symbol Rate 2 000 20000 syms Modulation QAM Filter RRC Alpha 96 0 2 or 0 35 Tx Bit rate Accuracy 90 ppm Tx Output Level I Output Q Output 91 TBD Vp p Tx Adjacent Channel Power I Output Q Output 92 dB PRBS Rx Frequency Error Tolerated 95 1 0 kHz Rx Co channel Rejection 93 dB Rx Adjacent Channel Rejection 93 3 dB Notes 90 Determined by the accuracy of the Xtal oscillator provided 91 Transmitting continuous default preamble 92 See section 9 5 7164FI 4 x Typical Transmit Performance 93 Se
44. 64 33V i33V Multi Mode Modem 1 Brief Description The CMX7164 Multi Mode Modem is a half duplex device currently supporting GMSK GFSK QAM and 2 4 Level FSK modes in multiple channel spacings under host control Its Function Image Fl is loaded to initialise the device and determine modulation types The 7164FI 1 x supports GMSK GFSK modulation with BT 0 5 0 3 0 27 or 0 25 User programmable filters are also possible contact CML Technical Support for further information The 7164Fl 1 x supports up to 20kbps Flexible bit rates support a wide range of applications requiring a selectable bit rate and robustness The 7164Fl 1 x supports zero IF UO and two point modulation Mod1 2 transmit modes with zero IF receive mode The GMSK GFSK data is over air compatible with the FX MX909B and the CMX 7143FI 1 x The 7164Fl 2 x supports 2FSK and 4FSK modulations root raised cosine filtered with a 0 2 with optional sinc filtering User programmable filters are also possible contact CML Technical Support for further information The 7164Fl 2 x supports up to 20kbps in a 25kHz channel Flexible bit rates support a wide range of applications requiring a selectable bit rate and robustness The 7164Fl 2 x supports zero IF UO and two point modulation Mod1 2 transmit modes with zero IF receive mode The 4FSK data is over air compatible with the FX MX919B and the CMX 7143FI 2 x The 7164Fl 4 x supports 4 16 and 64 QAM modulations
45. A Dilnn 8ksymbols s FS found 61 9 2 mA Dilnn 9 6ksymbols s FS found 61 9 4 mA Alpp AVpp 3 3V 8 7 mA Tx Mode 60 Dlpp 8ksymbols s 4 9 mA Diop 9 6ksymbols s 5 0 mA Alpp AVpp 3 3V 7 7 mA Notes 60 Transmitting in I Q mode continuous GMSK GFSK PRBS all GPIOs and RAMDAC set to manual 61 8ksymbols s 12 5kHz channel BT 0 3 9 6ksymbols s 25kHz channel BT 0 5 2012 CML Microsystems Plc Page 107 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 AC Parameters Notes Min Typ Max Unit Modem Symbol Rate 2 000 20000 syms Modulation GMSK GFSK Filter BT 0 25 0 27 0 3 or 0 5 Tx Bit rate Accuracy 62 ppm Tx Output Level I Output Q Output 63 TBD Vp p Tx Adjacent Channel Power Output Q Output 64 dB PRBS Rx Frequency Error Tolerated 66 1 0 kHz Rx Co channel Rejection 65 dB Rx Adjacent Channel Rejection TBD 5 dB Notes 62 Determined by the accuracy of the Xtal oscillator provided 63 Transmitting continuous default preamble 64 See section 7 4 65 See section 7 5 66 Optimum performance is achieved with OHz frequency error The figure quoted is for a symbol rate of 9 6ksymbols s The frequency error tolerated is proportional to the symbol rate 10 1 5 7164Fl 2 x Parametric Performance Details in this section represent design target values and are not currently guaranteed For the following conditions unless otherwise
46. ACR performance of the modem is normally made in terms of BER or PER for a given ratio between the wanted signal on channel and larger interferer on the adjacent channel Detailed measurement methods vary depending on the standards in use in particular whether the wanted signal is raised above the sensitivity limit and where the reference is taken The figures quoted here are based on the measurement method from EN 300 113 which tends to give lower figures than 2012 CML Microsystems Plc Page 95 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 some other methods In these tests the adjacent channel signal is close to the maximum input signal amplitude allowed by the 7164Fl 4 x The figures quoted in Table 6 are based on the difference between the interferer 400Hz FM modulation 3kHz deviation and the mean power of the wanted signal for less than 2096 PER 182 byte packets for 18ksymbols s It has been observed that adjacent channel rejection is limited by the headroom offered by the UO Inputs above the sensitivity level of the input signal This means that when the adjacent channel interferer reaches the maximum allowed input level of the UO Inputs a rapid transition from almost zero BER to a large BER is observed Given the relative sensitivity levels of the 4 QAM 16 QAM and 64 QAM signals the result is a measured adjacent channel rejection of Table 6 ACR Rejection Performance 4 QAM 16 QA
47. BS conforming to ITU T 0 153 Paragraph 2 1 is used to generate the PRBS The output created by transmitting a PRBS using 7164FI 4 x in 16 QAM mode is shown in Figure 20 The 16 constellation points are just visible on the plot Likewise the transmitted eye diagram when using 7164FI 2 x in two point modulation 4FSK mode is shown in Figure 21 and the transmitted eye diagram when using 7164F1 1 x in two point modulation GMSK GFSK mode is shown in Figure 22 Figure 20 Transmit Constellation Figure 21 Transmit Eye Diagram 7164F1 2 x 7164F1 4 x ea bs puce Figure 22 Transmit Eye Diagram 7164F1 1 x Rx Constellation 7164 FI 4 x only A test mode to examine the Rx constellation diagram is also provided this utilises the IOUTPUTP N and QOUTPUTP N pins to produce a diagnostic signal where the RRC filtered UO signals are output This produces a two dimensional constellation diagram which may be displayed on an oscilloscope in X Y mode Note that best results are often obtained with an analogue oscilloscope 2012 CML Microsystems Plc Page 40 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 N Figure 23 Constellation Figure 24 Constella
48. C System Clock Div 2 SYSCLK2 GPIOD FI Configured UO d System XTAL Clock PLL H ec AUXDAC1 Ramp profile RAM mE Ba CLOCK Clock PLL XTALN AUXDAC2 VE System Clocks AUXDAC3 AUXDAC4 Le Power Auxiliary DACs control MOSI AGG CLK Controller MISO SPI Thru amp Flash Boot Port SSOUTO SSOUT1 Host Thru Commands Boot Control SSOUT2 C BUS SPI Thru Control AVDD AvsS gt RESETN VBIAS ADCREF DVDD3V3 DVCORE DVSS DACREF BOOTEN1 BOOTEN2 Figure 1 Overall Block Diagram Figure 1 illustrates the overall functionality of the CMX7164 detailing the auxiliary functions The following figures expand upon the transmit and receive functions 2012 CML Microsystems Plc Page 11 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 Auto Frame Sync Detect
49. CML Microcircuits COMMUNICATION SEMICONDUCTORS D 7164_Fl 1 x Fl 2 x Fl 4 x 9 May 2012 DATASHEET CMX7164 Multi Mode Modem Advance Information 7164FI 1 x 7164F1 2 x and 7164Fl 4 x Multi Mode Modem Features Half duplex modem supports multiple modulations and channel spacings 7164Fl 1 x O O Oo oO GMSK GFSK with BT 0 5 0 3 0 27 or 0 25 S Over air compatible with FX MX909B and CMX7143FI 1 x Two frame sync detectors Automatic frame sync detect Rx carrier frequency correction Receive signal quality measurement 7164Fl 2 x O O oo0o0o 0 2 4FSK up to 20kbps in 25kHz Compatible FEC for CMX7143 and FX MX919B 4FSK not 2FSK S Two frame sync detectors Automatic frame sync detect Rx carrier frequency correction Receive signal quality measurement 7164Fl 4 x e Q Q OO OQ O10 4 16 64 QAM up to 96kbps in 25kHz e Different rate robust FEC choices Channel estimation and equalisation Two frame sync detectors Automatic frame sync detect Rx carrier frequency and phase correction A Receive signal quality measurement High Performance UO Radio Analogue Interface O o Oo O Oo Tx and Rx direct connect to zero IF transceiver Simple external RC filters Digital IF filter reconfigures for multiple RF e channel spacings Rx Deviation control without manual trim Tx UO trims C BUS host Serial Interface SPI like with register addressing Read Write 128 byte FIFOs and data buffers streamlin
50. CMX7164 4 3 UO Output Reconstruction Filter The CMX7164 WO Outputs provide internal reconstruction filtering with four selectable bandwidths 3dB point shown in section 11 1 22 The bandwidth of the internal reconstruction filter may be selected using the HO Output Configuration B3 write or Signal Control 61 write registers To complete the UO output reconstruction filter one of the following external RC networks should be used for each of the differential outputs The external RC network should have a bandwidth that matches the bandwidth of the selected internal reconstruction filter IOUTPUTP 17 IOUTPUTN 18 QOUTPUTP 19 QOUTPUTN 20 Bandwidth kHz R3 R6 kKOhms C9 C10 pF 100 22 33 50 20 75 25 22 150 12 5 22 270 Figure 8 Recommended External Components I Q Output Reconstruction Filter When transmitting an UO signal each UO output will produce a signal with bandwidth half the channel bandwidth A reconstruction filter with a 3dB point close to half the channel bandwidth will therefore have significant roll off within the channel bandwidth which is undesirable An appropriate choice for channels occupying up to a 25kHz bandwidth channel bandwidth 2 12 5kHz would be a reconstruction filter of 25kHz bandwidth 4 4 VQ Input Antialias Filter The device has a programmable antialias filter in the UO input path which is controlled using the 1 Q Input Configuration BO write
51. CMX7164 Multi Mode Modem CMX7164 6 7 C BUS Register Summary Table 2 C BUS Registers ADDR Word User E Read REGISTER Size Manual Section hex Write bits Page Ls w osscar o we ame 848 Ww Modem Command FIFO Data Byte 8 123 1113 44 T Modem Command FIFO Control Bye Is 123 1113 4B R ModemCommandFiFOLevel 8 14 11125 4C R Receive FIFODataByte 8 141 11126 4D_ R Receive FIFOWord 16 14 11126 4E R Receive FIFO ControlByte 8 141 11126 4F R Receive FIFO Level L 143 1127 A ER 59to 5C_ W AuxDAC1 4Control 16 128 114 7110 74 D AuxADC1 4Read 16 143 11129 SD WN Output Control 16 128 114 SE W Q Output Control 3 16 128 1 St w p IilpuCotr e 129 1 6 Ww QlnputControi O0 16 19 1119 68 Ww fp SinaConr LA 16 130 11110 6 WL AGC Control 16 134 11144 6 w Rxracng 16 135 14115 70 R Internal Buffer Dog 16 143 11128 755 Oaet 0 S 16 144 LC 11130 70 R QOfet 3J b di6 14 1130 87 R AGCGainandRSSI 16 144 11131 7A R RxError Magnitude 16 145 11134 7B R FrequencyEr
52. DC Offset Diagnostic Mode with frequency error 42 Figure 30 Normalised Constellation even with a frequency or phase error 43 Figure 31 Normalised Constellation noisy received signal sees eee eee 43 2012 CML Microsystems Plc Page 6 D 7164 FI 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 Figure 61 Figure 62 Figure 63 Figure 64 Figure 65 Figure 66 Figure 67 Figure 68 Figure 69 Figure 70 Figure 71 Figure 72 Figure 73 Figure 74 Figure 75 Figure 76 Figure 77 Figure 78 Figure 79 Channel Filtered UO Signals sese eee 43 Channel Filtered UO Signals with UO DC Offset Estimate eee eee eee enee 43 Command and Rx Data FIFOS sese eee eee 45 AGC using SPI Ru Wel 48 AGC Behaviour During Burst Reception 49 Main Clock Generation see eee 50 Digital System Clock Generation Schemes eee ee eee ee ee ee eee 51 Outline Radio Design UO in out for GMSK GFSK sse eee 55 Outline Radio Design GMSK GFSK WO in two point mod out 56 Formatted Data Over Air Signal Format sese eee eee eee eee eee 57 Tx Spectrum and Modulation Measurement Configuration for UO Operation 58 Tx M
53. FIFO Level 4B hA Write up to 128 FIFO fill level words to CmdFIFO Word 49 ad End of Block Yes Y Read and verify 32 bit checksum words from RxFIFO Word 4D Y N N 1 SE Is the next block the Activation Block No Yes T Write Start Block N Length ACTIVATE_len to CmdFIFO Word 49 Y Write Start Block N Address ACTIVATE ptr to CmdFIFO Word 49 Y Poll Status 7E until Reg Done b14 1 PRG Flag is unmasked in Reg Done Select register 69 by default and indicates when the FI is loaded Y Read the Product ID Code and the FI version code from the RxFIFO Word 4D L CMX7164 is now ready for use No load next block Von BOOTEN1 BOOTEN2 Figure 13 FI Loading from Host 2012 CML Microsystems Plc Page 26 D 7164 FI 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 6 3 2 Fl Loading from Serial Memory The Fl must be converted into a format for the serial memory programmer normally Intel Hex and loaded into the serial memory either by the host or an external programmer The serial memory should contain the same data stream as written to the Command FIFO shown in Figure 13 The most significant byte of each 16 bit word should be stored first in serial memory The serial memory should be interfaced to the CMX7164 SPI Thru Port using SSOUTO as the chip s
54. FO updating both control and data registers In summary Operation Effect write Modem Command Cmd FIFO control word updated nothing added to Cmd FIFO FIFO Control Byte register write Modem Command Cmd FIFO control word data byte written are added to Cmd FIFO FIFO Data Byte register write Modem Command data word control and data bytes is added to Cmd FIFO FIFO Word register Cmd FIFO control word updated for future writes read Receive FIFO Rx FIFO control word is returned no effect on Rx FIFO contents Control Byte register read Receive FIFO Data Oldest Rx FIFO data byte is removed from FIFO and returned Rx FIFO Word Byte register updated read Receive FIFO Data Oldest Rx FIFO data word control and data bytes is removed from FIFO and Word register returned Rx FIFO control word updated 2012 CML Microsystems Plc Page 44 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 C BUS interface Rx Level CMD FIFO LEVEL CMD FIFO CTRL 128x16 CMD FIFO 128x16 RX FIFO ld LI Figure 34 Command and Rx Data FIFOs Raw or formatted data may be transmitted with the CMX7164 adding preamble frame sync and tail bits Raw or formatted transmission reception is selected using the Modem Mode and Control 6B write register each whole transmission reception must continue in the selected mode Relevant registers are 11 1 18 Modem Mode and Control 6B
55. Local Oscillator PA Gain Control RAMDAC 000000 Aux DACO 2x DAC m OS 1 90 Directional Power Coupler Amplifier L Output n aj 7 Q Output A ot OX ei Tag I Local Oscillator ae Se CMX998 Figure 66 Outline Radio Design UO in out for QAM Use of UO receive mode brings with it the problem of I Q dc offsets There are dc offsets caused by the radio receiver resulting in the signal into the CMX7164 having a dc offset other than Voss The offset needs to be removed prior to demodulation Offsets typically remain constant for a particular radio frequency selected but will vary if that frequency is changed Gain within the radio receiver may also affect the dc offset seen by the CMX7164 UO dc offset effects are a radio issue which is beyond the control of the CMX7164 However the CMX7164 does provide dc offset calculation and removal These are described in detail in the application note section 13 3 DC Offsets in UO Receivers 9 2 1 Control interfaces As can be seen in Figure 66 the CMX7164 provides control interfaces to assist with controlling the radio transmitter and receiver These include e A SPI Thru Port port which may be used to control radio ICs with C BUS SPI interfaces e ARAMDAC which can be used to control PA ramp up and ramp down e Four GPIO pins which may be used for Tx Rx switching LNA off and general device control 7 CMX992 i
56. M 64 QAM Raw Data 62dB less than 1e 3 55dB less than 1e 3 48dB less than 1e 3 BER BER BER Formatted Block Type 0 65dB for 6 PER 62dB 0 PER 58dB 19 PER Formatted Block Type 6 65dB for 0 PER 62dB 0 PER 58dB 0 PER Formatted Block Type 7 65dB for 0 PER 62dB 0 PER 58dB 0 PER The figures in Table 6 are typical of what may be achieved with 7164Fl 4 x and a typical WO radio receiver with no adjacent channel selectivity in the radio circuits In a more normal RF architecture some adjacent channel selectivity will be provided making system results better than the measured values for the 7164Fl 4 x alone Furthermore the results observed are not necessarily the maximum that the CMX7164 can achieve but are limited by the practical dynamic range of the CMX7164 combined with the system gain and noise figure of the receiver used in these tests 9 6 3 Receiver Dynamic Range The adjacent channel rejection results in section 9 6 2 also indicate that a wanted signal can be successfully received over the dynamic range stated in Table 6 without any need for an AGC Note that this is limited at the top end by the maximum allowed signal amplitude into the CMX7164 but performance at the bottom end is affected by noise added by the test receiver so these figures are not the absolute limit of CMX7164 FI 1 x 2 x 4 x performance 9 6 4 Receiver Response Equaliser Performance The performance of the 7164Fl 4 x when receiving a signal th
57. MSB Read data LSB Data value unimportant Repeated cycles Either logic level valid but must not change from low to high 2012 CML Microsystems Plc Figure 11 Basic C BUS Transactions Page 23 D 7164 FI 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 To increase the data bandwidth between the uC and the CMX7164 certain of the C BUS read and write registers are capable of data streaming operation This allows a single address byte to be followed by the transfer of multiple read or write data words all within the same C BUS transaction This can significantly increase the transfer rate of large data blocks as shown in Figure 12 Example of C BUS data streaming 8 bit write register CSN SCLK CDATA 7 6 5 4 3 2 1 0 7 6 5 4 3 2 110 7 6 5 4 38 2 1 6 5 4 3 2 1 0 Address First byte Second byte Jes Last byte RDATA Hi Z Example of C BUS data streaming 8 bit read register CSN SCLK c CDATA 7 e s5 4 3 2 1 o Address RDATA Z 7le s a s 2 t o v e s a s a2 ts o vle s 4 S 2
58. MX994 and other serially controllable devices e In build calibration routine to support CMX998 Cartesian loop transmitter IC e Four auxiliary DACs one with built in programmable RAMDAC Interface e Optimised C BUS 4 wire high speed synchronous serial command data bus interface to host for control and data transfer including streaming C BUS for efficient data transfer e Open drain IRQ to host e Four GPIO pins e Tx trigger input Provided by GPIOA The frame sync detection algorithm of the CMX7164 is capable of detecting a frame sync without having bit synchronisation so preamble is not required for obtaining bit sync Some preamble is still needed to ensure that the beginning of the frame sync is transmitted and received without distortion Preamble may also be used to provide a known signal on which to acquire UO dc offset corrections 2012 CML Microsystems Plc Page 19 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 e Serial memory or C BUS host boot mode Both transmit and receive data can be raw or coded data blocks Fl 4 x provides a variety of coding rates for flexibility and very large block sizes having the potential to improve performance in fading conditions considerably Fl 2 x provides coding compatible with CMX7143F1 2 x Fl 1 x provides coding compatible with CMX7143FI 1 x 5 2 Signal Interfaces I Q Tx and Rx Fl 4 x produces QAM modulation The transmitted signal is provided as an UO baseb
59. Operation Some typical results are shown in the following figures The internal PRBS generator was used to generate the data in all the results shown Two baud rates are demonstrated 18ksymbols s which is typical of a 25kHz channel and 9ksymbols s which is typical of a 12 5kHz channel In all cases the transmit filter selected had a 0 2 Depending on transmitter requirements e g applicable standards faster baud rates may be possible 2012 CML Microsystems Plc Page 86 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 500 Hz 2 kHz 1 35 s 19 44 d m 30 00615p30 MHz Wi 6 42 dB RBW RF Att VBW Marker 1 T1 13 44 dBm 450 00615030 MHz Unit Span 66 kHz 4 QAM Modulation spectrum with 18ksymbols s Adjacent Channel measurement for 25kHz channel ACP 76dB Integration window 16kHz 450 MW Mean Signs 16 b Veoto Dexod or e Bet lvl 35 ana 74 1666667 91 dB Offset BURST NOT FOUND cr 450 MHs Meas Signal sn 18 kHs Constellation Demod Qp3R PEAL 3 166666 rer 450 MHz Bet ivl Sp 15 kHz Syabol Errors 25 ana pas sd H 21 aD Offset Symbol Table o 00101010 11001111 11010100 01100111 10000101 ao 10100101 11111100 00000001 00111111 10111011 n 5o 01101011 10161100 00100111 00111010 11111000 Error Summary Constellation Diagram Receiver filtered Error Vector Mag Magnitude Error Phase Error Freq Erro
60. S __ gt HEAD 0 to 32 FRAME Figure 41 Formatted Data Over Air Signal Format The Frame head may be used to contain addressing and control flag information The Data block s contain user data and an optional checksum The CMX7164 performs all of the block formatting and de formatting the binary data transferred between the modem and its uC being that enclosed by the thick dashed rectangles near the top of Figure 41 When receiving data blocks with CRCs the CMX7164 will indicate CRC success or failure and will provide the data regardless 2012 CML Microsystems Plc Page 57 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem In Figure 41 the size of data block illustrated is 20 bytes when user bytes and CRC bytes are counted together The CMX7164 adds further flexibility by supporting block sizes of 4 6 12 or 18 user bytes with an optional 2 byte CRC The resulting data content is Table 3 Formatted Block Types and Sizes Fl 1 x Block type User bytes CRC bytes Frame Head With bit frame sync 2 0 Frame Head User data CRC only 6 0 4 byte data block with CRC 4 0 6 byte data block without CRC 6 0 12 byte data block without CRC 12 0 18 byte data block without CRC 18 0 4 byte data block with CRC 4 2 6 byte data block with CRC 6 2 12 byte data block with CRC 12 2 18 byte data block with CRC 18 2 7 4 T164Fl 1 x Typical Transmit Perform
61. Selects blocks of data bytes to be transmitted Command FIFO Control Byte blocks 8 bytes in each after which the CMX7164 will see Modem Command request more data from the host FIFO Data Control 48 49 and 4A write Write 8 data bytes to the Pre load the This provides a buffer of 8 data bytes before Modem Command FIFO Data Byte see Modem Command FIFO Data Control 48 49 and 4A write Command FIFO with data to transmit transmission starts so that the host does not need to write data as promptly for the rest of the burst Write 0042 to Modem Mode and Control 6B write Start transmission Initiates a transmission with preamble Frame Sync 1 and then the pre loaded data Poll the IRQ Status 7E read register for bit 8 Cmd Done 1 Wait until the data block has been read from the FIFO When this is complete a further 8 data bytes may be written to the Modem Command FIFO Data Byte see Modem Command FIFO Data Control 48 49 and 4A write and the IRQ Status 7E read register polled again This step may be repeated as many times as needed Write F000 to the Modem Command FIFO Word see Modem Command FIFO Data Control 48 49 and 4A write Indicate burst end is intended Indicate that no more data is to follow so when the data loaded into the Command FIFO is modulated the CMX7164 will terminate the burst with tail bits Poll the IRQ Status 7E
62. a read operation Commands can be called 0 1 or 2 byte reads or writes with a 0 byte write typically being a reset command As the word format is known then for convenience only the desired read data is returned to the host 2012 CML Microsystems Plc Page 47 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 SPI mode is a little more flexible No assumption is made about the SPI word format nor any assumption that the length is a whole number of bytes See e 11 1 11 SPI Thru Port Control 62 write e 11 1 12 SPI Thru Port Write 63 write e 11 1 32 SPI Thru Port Read 78 read e 11 2 8 Program Block 6 SPI Thru Port Configuration 6 4 22 SPI C BUS AGC Using the SPI Thru Port the CMX7164 provides a method of controlling an external C BUS device capable of implementing variable gain steps When using UO receive modes this allows for a fast response to large signals causing clipping and an increase in gain when the signal becomes too small Controlling the external device requires the host to program a table of eight C BUS commands that the CMX7164 stores and outputs when a specific gain step is required The commands may be produced by the AGC function or the CMX7164 can be commanded to output them manually if required Commands are programmed using Program Block 7 AGC Configuration AGC is controlled by sensing clipping in the received signal in which case the gain is backed off While searching for
63. alised curve flattens off 64 QAM is unusable without equalisation producing a residual bit error rate of greater than 1e 2 regardless of signal to noise ratio This is not plotted in Figure 85 The 4 QAM curves show that 4 QAM is less affected by the receiver response therefore the improvement made by equalisation is less Once equalisation is present the measured figures compare well to the results with no crystal filter in the receive path in section 9 6 1 Signal to Noise and Co channel Performance The response of crystal filters varies with temperature This will affect the ability of an equaliser which is trained at room temperature to compensate effectively for filter distortions at a different temperature Measurements showing the degradation in signal to noise performance over temperature when the equaliser was trained at room temperature are shown in Figure 86 2012 CML Microsystems Plc Page 98 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 1 00E 01 4 1 00E 02 1 00E 03 1 00E 04 BER 1 00E 05 1 00E 06 4 No Equalizer 1 00E 07 4 www VVith Equalizer 1 00E 08 4 T T T T 40 15 10 35 60 85 Temperature deg C Figure 86 Performance of 16 QAM equalised signals with temperature variation Tests were carried out using 16 QAM modulation with a signal level of 103dBm Figure 86 and a signal level of 95dBm for 64 QAM Figure 87 in both cases using the EV9910B BER performa
64. ame sync search searching for Frame Sync 1 Once it is detected then Rx data will be made available Apply input signal The input signal should contain preamble Frame Sync 1 and then raw data The frame sync should be detected and Rx data made available Poll the IRQ Status 7E read register for bit 8 Cmd Done 1 Wait for data This indicates that the 4 data bytes requested have been received and are available Read the Receive FIFO Data Byte see Receive FIFO Data Control 4C 4D 4E read 4 times Retrieve the received data Data is read from the Receive Data FIFO Once 4 data bytes are read the IRQ Status register may be polled again to check if more data is available if required and then those data bytes read This step may be repeated as many times as needed End of reception Once enough data has been received a mode change using the Modem Mode and Control 6B write register will stop reception or start searching for another frame sync The procedure described above can be adapted making reception of different numbers of bytes bits or coded blocks possible The registers used for basic transmission and reception are 11 1 18 Modem Mode and Control 6B write e e 11 1 37 IRQ Status 7E read e e e 11 1 4 FIFO Control 50 write e 11 1 15 Rx Tracking 66 write 6 4 3 Features that can be configured include Full details of how to configure these asp
65. ance Using the test system shown in Figure 42 the 7164F1 1 x internal PRBS generator was used to modulate the RF vector signal generator Some typical results are shown in the following figures The desired deviation was achieved by adjusting the CMX7164 peak deviation using register 61 CMX7164 Output j UO Q Output RF Vector Spectrum Analyser Signal Vector Signal Analyser Generator Lebe Figure 42 Tx Spectrum and Modulation Measurement Configuration for UO Operation 2012 CML Microsystems Plc Inputs O Buffer Amplifiers if required to drive RF signal generator modulation inputs Page 58 D 7164 FI 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 Marker 1 T1 RBW 500 Hz RF Att 30 dB Ref Lvl 21 71 dBm VBW 2 kHz O dBm 448 00072745 MHz SWT 1 35 8 Unit dBm Modulation Spectrum EN 300 113 Adjacent Channel measurement for 25kHz channel ACP 81dB limit is 60dB Integration window 16kHz Peak deviation 1 symbol 2 4kHz Center 448 MHz 6 6 kHz Span 66 kHz Cp 448 MHz Meas Signal Ref Lvl SR 9 6 kHz Eye I 0 dBm Demod 2FSK REAL Eye Diagram mi Deviation for 1 i symbol 2 4 kHz 100m 0 SYMBOLS 4 Figure 43 Tx Modulation Spectra GMSK 9 6kbps BT 0 5 I Q Modulatio
66. and for mixing up onto an RF carrier with amplification For reception an UO baseband signal should be interfaced into the 7164FlI 4 x 7164FI 2 x produces 2FSK and 4FSK modulation and can be configured to produce WO modulation in which case the signal interfaces are the same as for Fl 4 x 7164Fl 1 x produces GMSK GFSK modulation and can also be configured to produce UO modulation in which case the signal interfaces are the same as for Fl 4 x In receive the UO interface provides amplitude information so the RSSI signal is calculated internally It is averaged in order to produce the RSSI measurement and to support the carrier sense decision whether to transmit ea CMX7164 INPUT T R Radio Receiver Receive Processing QINPUT E Transmit Processing IOUTPUT QOUTPUT Mix onto RF carrier and linearise if required Figure 9 CMX7164 UO Tx I Q Rx 2012 CML Microsystems Plc Page 20 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 5 3 Signal Interfaces Two point Tx and UO Rx Fl 2 x produces 4FSK modulation and can be configured to produce two point modulation Fl 1 x produces GMSK GFSK modulation and can also be configured to produce two point modulation This option is not applicable for Fl 4 x The I Q interface is the only option available for receive ONG CMX7164 IINPUT
67. and the host uC this interface is compatible with Microwire SPI and other similar interfaces Interrupt signals notify the host UC when a change in status has occurred the uC should read the IRQ Status register across the C BUS and respond accordingly Interrupts only occur if the appropriate mask bit has been set see Interrupt Operation 6 2 1 C BUS Operation This block provides for the transfer of data and control or status information between the CMX7164 internal registers and the host uC over the C BUS serial bus Single register transactions consist of a single register address byte sent from the uC which may be followed by a data word sent from the uC to be written into one of the CMX7164 s write only registers or a data word read out from one of the CMX7164 s read only registers Streaming C BUS transactions consist of a single register address byte followed by many data bytes being written to or read from the CMX7164 All C BUS data words are a multiple of 8 bits wide the width depending on the source or destination register Note that certain C BUS transactions require only an address byte to be sent from the uC no data transfer being required The operation of the C BUS is illustrated in Figure 11 Data sent from the uC on the CDATA command data line is clocked into the CMX7164 on the rising edge of the SCLK input Data sent from the CMX7164 to the uC on the RDATA reply data line is valid when SCLK is high The CSN line must be
68. and therefore being able to output the signal level measured at the symbol timing instant with the frequency error removed and amplitude corrected So long as the CMX7164 remains locked to a suitable signal the normalised constellation output will remain static regardless of frequency error and amplitude of the input signal within limits see section 10 1 5 7164Fl 2 x Parametric Performance If the signal becomes noisy or its amplitude small then the constellation points will spread as shown in Figure 30 and Figure 31 2012 CML Microsystems Plc Page 42 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 g 1 ETT SEITE TPR TT at e lt AN es e ie D D A sl x 3 L EL EE Ae Ze Ke E H lad Figure 30 Normalised Figure 31 Normalised Constellation even with a Constellation noisy received frequency or phase error signal Rx Diagnostics 7164 Fl 1 x and Fl 2 x only A diagnostic mode is provided that produces channel filtered UO signals and an optional dc offset correction indication This aids in diagnosing reception issues that may be related to UO dc offsets in the CMX7164 input signal As shown in Figure 32 and Figure 33 the estimated UO dc offset correction is an extra dot in the centre of the constellation
69. ation of gain and dc offset does not cause the signal to clip at any point in the signal processing chain which is Fine gain followed by dc offset addition followed by coarse gain See e 11 1 8 UO Output Control 5D 5E write e 11 1 23 l Q Output Coarse Gain B4 B5 write 6 6 2 Receive Path Levels The Coarse Input has a variable gain of up to 22 4dB and no attenuation With the lowest gain setting 0dB the maximum allowable input signal level at the Input or Q Input pins is specified in section 10 1 3 Operating Characteristics A Fine Input level adjustment is provided although the CMX7164 should operate correctly with the default level selected The primary purpose of the Fine Input level adjustment is to allow independent inversion of the UO Input signals Inversion is achieved by selecting a negative value for the linear Fine Input gain adjustment When receiving UO format signals inverting one of the UO pair has a similar effect to swapping with Q DC offsets can be removed by the CMX7164 the offset to remove can be selected by the host or calculated automatically by the CMX7164 It should be noted that if the maximum allowable signal input level is exceeded signal distortion will occur regardless of the internal dc offset removal or attenuation See e 11 1 9 1 Q Input Control 5F 60 write e 11 1 20 I Q Input Configuration BO write 2012 CML Microsystems Plc Page 52 D 7164 FI 1 x Fl 2 x Fl 4 x 9
70. b9 in section 11 1 14 s Remove FI Load Activation Block references and describe default states in section11 1 2 and Table 5 e Clarify bit names in section 11 1 20 to avoid duplication e Add missing action 20 in section 11 2 1 1 e Original document prepared for first alpha release of FI 24 2 11 2012 CML Microsystems Plc Page 10 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 2 Block Diagrams Transmit Functions IOUTPUTP 1 x 2 x Q or Channel Coder c 2 point modulation Fl 4 x UO output E P QOUTPUTN Receive Functions IINPUTP Channel IINPUTN Filter 1 S Data Channel Decoder Demodulator QINPUTP Channel QINPUTN Filter Auxiliary Functions Thresholds k ADC 1 Averaging gt Thresholds S IRON Averaging Command FIFO RDATA gt Thresholds AUXADC1 0 Averaging Rx Data FIFO ON AUXADC2 Thresholds CDAT AUXADC3 L4 ADC 4 AUXADC4 Averaging Registers lt SCLK Auxiliary Multiplexed ADCs C BUS Interface GPIOA GPIOB GPIO with O P i Sequencer System Clock Div 1 SYSCLK1 GPIO
71. blem of UO dc offsets There are dc offsets caused by the radio receiver resulting in the signal into the CMX7164 having a dc offset other than BIAS The offset needs to be removed prior to demodulation Offsets typically remain constant for a particular radio frequency selected but will vary if that frequency is changed Gain within the radio receiver may also affect the dc offset seen by the CMX7164 UO dc offset effects are a radio issue which is beyond the control of the CMX7164 However the CMX7164 does provide dc offset calculation and removal These are described in detail in the application note Section 13 3 DC Offsets in UO Receivers 7 2 2 Two point Modulation Transmit with UO Receive Interface An overview of how the CMX7164 might integrate with an l Q receiver and two point modulation transmitter is shown in Figure 52 The internal functions of the CMX7164 when operating in this mode are shown in Figure 4 2012 CML Microsystems Plc Page 55 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 HOST Y Ase ecd e Ro a ike aM P AP Seg EE GPIOn uP I XO ac T Ney xus LNA Enable X CMX7164 l NNAS P SE 1 NEN GPIO Tx Rx RR NG GQ K Q2 IINPUT LNA Lo 2x ADC BUS Q QINPUT CMX992 Local O
72. blocks and last blocks the CMX7164 will indicate CRC success or failure and will provide the data regardless The size of the data block can be varied as can the coding rate applied A lower coding rate more FEC bits will improve performance in noisy or faded conditions but will reduce the user data rate available Small data blocks provide the ability to produce a short burst or granularity in burst size However to cope with fading conditions longer coded blocks are necessary The 7164Fl 4 x provides blocks with the following formatted block sizes rates Table 5 Formatted Block Types Sizes and Rates FI 4 x User CRC bytes for a Block Block Size Coding Rate Coding Rate Header Inter Last Type 4 16 QAM 64 QAM Block Block Block 0 15 bytes 0 75 0 83 13 2 15 11 4 1 60 bytes 0 75 0 83 58 2 60 56 4 2 33 bytes 0 55 0 61 31 2 33 29 4 3 37 bytes 0 62 0 69 35 2 37 33 4 4 44 bytes 0 55 0 61 42 2 44 40 4 5 176 bytes 0 55 0 61 174 2 176 172 4 6 73 bytes 0 52 0 58 71 2 73 69 4 7 292 bytes 0 52 0 58 290 2 292 288 4 8 88 bytes 0 55 0 61 86 2 88 84 4 9 352 bytes 0 55 0 61 350 2 352 348 4 10 104 bytes 0 65 0 72 102 2 104 100 4 11 416 bytes 0 65 0 72 414 2 416 412 4 2012 CML Microsystems Plc Page 83 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 9 4 7164Fl 4 x Receiver Response Equaliser When receiving s
73. e 82 Figure 83 Figure 84 Figure 85 Figure 86 Figure 87 Figure 88 Figure 89 Figure 90 Comparison of BER and PER for 4 QAM Modulation eee eee 94 Comparison of BER and PER for 16 QAM Modulatton sese 95 Comparison of BER and PER for 64 QAM Modulatton sese see eee eee 95 4 QAM Signal to Noise Performance Equalised and Non Equalised 97 16 QAM Signal to Noise Performance Equalised and Non Equalised 97 64 QAM Signal to Noise Performance Equalised and Non Equalised 98 Performance of 16 QAM equalised signals with temperature variation 99 Performance of 64 QAM equalised signals with temperature variation 100 G BUS Times ds etie tutt atate cnt 113 Mechanical Outline of 64 pin VOEN OT 114 Mechanical Outline of 64 pin LQFP LO sss sese 114 Information in this datasheet should not be relied upon for final product design It is always recommended that you check for the latest product datasheet version from the CML website www cmlmicro com 2012 CML Microsystems Plc Page 8 D 7164 FI 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 1 1 History Version Changes Date D M Y 9 e Add GMSK GFSK operation in Fl 1 x 30 4 12 8 e Added details of FLA Equaliser operation and control Mode register 9 1 12 programming block e Added details of programming block read mechanism Available for selected p
74. e section 9 6 7164FI 4 x Typical Receive Performance 95 Optimum performance is achieved with OHz frequency error The figure quoted is for a symbol rate of 18kHz The frequency error tolerated is proportional to the symbol rate 96 A user programmable filter option is also provided allowing for compensation for external hardware and different a values than those provided 2012 CML Microsystems Plc Page 112 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 10 2 C BUS Timing CSN SCLK CDATA RDATA 70 Vdd 30 Vdd 4 5 If 1 byte of data If 2 bytes of data t 4 gt tose A E tcc gt Leer sen tcsorr t tes Leer cht tuxr T 7186151413120 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 T tLoz 5 e taz gt K taz gt lt Hi Z 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Level not important or undefined ton tex SCLK thos troy toon RDATA Figure 88 C BUS Timing C BUS Timing Notes Min Typ Max Unit tcse CSN Enable to SCLK high time 100 ns lcsu Last SCLK high to CSN high time 100 ns tioz SCLK low to RDATA output enable Time 0 0 ns tuiz CSN high to RDATA high impedance 1 0 US lcsorr CSN high time be
75. e transfers and relax host service latency 2012 CML Microsystems Plc Auxiliary Functions Four 10 bit DACs Autonomous RAMDAC sequencer Automatic support for dc calibration of CMX998 Four 10 bit ADCs ADC averaging and trip on high low watch modes o Four GPIO o Sequence GPIO on Tx or Rx trigger o Start Tx on digital trigger input Master C BUS SPI Serial Interface o Forexternal slave devices e g RF transceiver and synthesiser o Pass through mode expands host C BUS SPI capacity Two Synthesised Clock Generators Low Power 3 3V Operation with Powersave Functions Small 64 pin VQFN and LQFP Packages OO OO Applications High Performance Narrowband Data Radio Telemetry SCADA data modems 6 25kHz to 25kHz RF channel spacing Compatible worldwide e g ETSI FCC ARIB etc FCC Part 90 per new spectral efficiency requirements Digital Software Defined Radio SDR High speed Wireless Data Mobile Data over Fading Channels O 00 O CMX7164 Multi Mode Modem CMX7164 ct weg AEN Seen 3 3V H 4x GPIO 4x ADC 4x DAC H m H Synth LJ _y i Digital iuis pm ADCS TE Filters FIFO g i Modem Sai Hes i Digital TE P iCBUS H RF Tx DACs X Fil onfiguration A Tais This document contains Modulate Sacre Ge External Serial i C BUS SPI Devices d gt master FEC Image Datasheet CMX71
76. e used to track the signal level UO dc offset and symbol timing of the input signal as required Use of the automatic tracking modes is recommended Data may be in variable size blocks and or bee note may be processed irregularly by the host Rx_Process Y Load Command FIFO with Rx data command s Set Modem Control to Rx and receive either framesync The Modem will start to look for If enabled 1 0 000000 p note ener frame sync The host should IRQ FrameSync will note ta ensure that any external occur before hardware is also set into Rx IRQ DataRdy No mode if not automatically m controlled by the GPIO pins IRQ mdDone or Rx FIFO yes Load Command FIFO Load data from Rx FIFO with further Rx data command s An S more data to Further data is requested the device Ee No receive will buffer data internally Therefore G atthis nee es eer l note an internal data overflow can occur if el 9 the Command FIFO is not written p yes promptly Transmission das required No Y Se Mu Set Modem Control to Idle Yes Y Goto Tx Process The Modem will drop into Idle mode The host should ensure that any external hardware is also set into Idle mode if not automatically controlled by the GPIO pins note Ss A See Tx Process Flow re Diagram v ere B Got
77. ects of device operation are given in section 11 2 in the User Manual 2012 CML Microsystems Plc Page 30 11 1 3 Modem Command FIFO Data Control 48 49 and 4A write 11 1 26 Receive FIFO Data Control 4C 4D 4E read Device Configuration Using the Programming Register While in Idle mode the Programming register becomes active The Programming register provides access to the Program Blocks Program Blocks allow configuration of the CMX7164 during major mode change Flexible selection of Baud rates from 2k to 20k baud Pre amble and frame syncs to be using in transmit and receive Selection of Automatic control of 4 x GPIO and the RAMDAC during transmission Configuration of RAMDAC profile Configuration of RSSI averaging Configuration of the carrier sense window and thresholds Configuration of System Clock outputs Configuration of SPI Thru Port rate and word format Configuration of AGC commands using the SPI Thru Port D 7164 FI 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 6 4 4 Device Configuration Using dedicated registers Some device features may be configured using dedicated registers This allows for configuration outside of Idle mode Configuration of the following features is possible Auxiliary ADC detect thresholds Auxiliary ADC input selection and averaging mode Output gain Output de offsets Selection of AGC mode or manual control of the gain level The registers that allow configuratio
78. ed in Bandwidth Symbols s Filter KHz Tx ACP Bandwidth kHz Figures KHz dBc 25 9600 Gaussian 24 81 16 Figure 47 BT 0 5 12 5 8000 Gaussian 2 0 73 8 Figure 47 BT 0 3 Figure 48 Figure 49 2012 CML Microsystems Plc Page 63 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 1 0E 02 8kbps Bt 0 3 9 6kbps Bt 0 5 1 0E 03 D N E Lon ta N 1 0E 06 6 0 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0 16 0 SNR dB Figure 47 Modem Sensitivity Performance 2012 CML Microsystems Plc Page 64 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 Data transfer may have channel coding applied to it wnen GMSK GFSK modulation is selected The graph in Figure 48 shows the improvement due to channel coding in the 12 5kHz channel case 8ksymbols s with Gaussian pulse shaping filter with BT 0 3 1 0E 02 8kbps Bt 0 3 Raw 8kbps Bt 0 3 code 2 1 0E 03 D G LOE 04 ta 1 0E 05 1 0E 06 8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0 16 0 17 0 SNR dB Figure 48 Sensitivity 12 5kHz Channel 8ksymbols s With and Without Coding 2012 CML Microsystems Plc Page 65 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 The co channel rejection ratio Figure 63 is measured with an interferer modulated with 400Hz FM and having a deviation of 1 5kHz which is 12 of the nominal 12 5kHz channel bandwidth This particular interfering
79. ed to both ADC channels the comparison is applied after averaging if this is enabled and an IRQ generated when an input exceeds the high or low threshold or on every sample as required The thresholds are programmed via the AuxADC1 4 Threshold 55 to 58 write register Auxiliary ADC data is read back in the AuxADC1 4 Read 71 to 74 read registers and includes the threshold status as well as the actual conversion data subject to averaging if enabled The AuxADC sample rate is selected using Program Block 1 Clock Control See 11 1 5 AuxADC1 4 Control 51 to 54 write 11 1 6 AuxADC1 4 Threshold 55 to 58 write 11 1 29 AuxADC1 4 Read 71 to 74 read 11 2 3 Program Block 1 Clock Control 11 1 24 Vgias Control B7 write 6 4 20 Auxiliary DAC RAMDAC Operation The four auxiliary DACs are programmed via the AuxDAC1 4 Control 59 to 5C write registers AuxDAC1 may also be programmed to operate as a RAMDAC which will autonomously output a pre programmed profile at a programmed rate The RAMDAC may be configured as automatic or manual using Program Block 5 Burst Tx Sequence The AuxDAC1 4 Control 59 to 5C write register with b12 set controls the RAMDAC mode of operation when configured as a manually triggered RAMDAC The RAMDAC ramp rate is controlled by the Internal system clock rate which changes between active CS Tx Rx modes and Idle mode Therefore it is inadvisable to return to Idle mode prior to RAMDAC ramp c
80. ee 10 1 2 Operating Limits C1 22pF Typical C2 22pF Typical Figure 6 Recommended External Components Xtal Interface Notes The clock circuit can operate with either a Xtal or external clock generator If using an external clock generator it should be connected to the XTAL CLOCK pin and the xtal and other components are not required For external clock generator frequency range see 10 1 2 Operating Limits When using an external clock generator the Xtal oscillator circuit may be disabled to save power see 11 2 3 Program Block 1 Clock Control for details Also refer to section 6 1 Xtal Frequency The tracks between the Xtal and the device pins should be as short as possible to achieve maximum stability and best start up performance It is also important to achieve a low impedance connection between the Xtal capacitors and the ground plane The DVgg to the Xtal oscillator capacitors C1 and C2 should be of low impedance and preferably be part of the DVss ground plane to ensure reliable start up For correct values of capacitors C1 and C2 refer to the documentation of the Xtal used 4 2 C BUS Interface DVpp 57 56 55 54 53 R2 10k 100kQ Figure 7 Recommended External Components C BUS Interface Note If the IRQN line is connected to other compatible pull down devices only one pull up resistor is required on the IRQN node 2012 CML Microsystems Plc Page 17 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem
81. eive interfaces are identical to those used for QAM modulation in Figure 66 facilitating multi mode modem operation However no linearisation is required when transmitting GMSK GFSK 3 CMX992 is an RF Quadrature IF Receiver CMX998 is a Cartesian Feedback Loop Transmitter which is designed primarily for non constant envelope modulations such as QAM although it will also support GMSK 4 FSK Conventional UO vector modulators such as the CMX993 would be more typical of solutions for GMSK 4 FSK modulation 2012 CML Microsystems Plc Page 54 D 7164 FI 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 HOST Y BE coe acne eR ARN once Saad ce tsa tn and AR eae tat tans nod GPIOn ___ DE l i i l l X ac t NS feien LNA Enable_____ X CMX7164 Bee l Soe a ERE GPIO Tx Rx et C9 Input 4 LNA Lo 2x ADC C BUS Q0 Q Input j CMX992 Thru C BUS Local Oscillator PA Gain Control RAMDAC geleist edel 1 Aux DACO 2x DAC x 90 Directional Power Coupler Amplifier L 1 Output A 3i r E Q Output X mE 2 3 1 9 Ton Local Oscillator S CMX998 Figure 39 Outline Radio Design UO in out for GMSK GFSK Use of UO receive mode introduces the pro
82. eiver 8 5 1 Signal to Noise and Co channel Performance The performance of the 7164Fl 2 x when receiving is shown in the following graphs It should be noted that error rate performance depends on the modulation rate and deviation results have been taken for typical channel bandwidths The 7164Fl 2 x supports multiple combinations of these factors but it is beyond the scope of this document to provide data for every combination Data is provided showing a selection of representative cases ranging from best case performance maximum coding to worst case where no coding is used raw mode plus the effect of using the two supported types of data pulse shaping plain Root Raised Cosine RRC filtering or RRC plus sinc filter In the following graphs the modulation is 4FSK and the data rate is dependant on channel bandwidth The 25kHz channel data rate is 9 6ksymbols s the 12 5kHz channel data rate is 4 8ksymbols s and the 6 25kHz channel data rate is 2 4ksymbols s which is typical of the rate that may be achieved in each RF channel The signal to noise ratio is calculated as SNR Mean signal power 174 NF 10 logi RXBW Where NF receiver noise figure in dB RxBW receiver noise bandwidth Mean signal power is in dBm SNR Signal to Noise Ratio in dB The graph in Figure 60 compares the raw sensitivity performance of data transfer using a 6 25kHz a 12 5kHz and a 25kHz channel in each case the deviation of the transmitted modulation
83. elect The CMX7164 needs to have the BOOTEN pins set to Serial Memory Load and then on power on following the RESETN pin becoming high or following a C BUS General Reset the CMX7164 will automatically load the data from the serial memory without intervention from the host controller BOOTEN2 0 BOOTEN1 1 i Power up or write General Reset to CMX7164 y Poll Status 7E until Reg Done b14 1 PRG Flag is unmasked in Reg Done Select register 69 by default and indicates when the FI is loaded BOOTEN1 and BOOTEN2 may be changed from this point on if required Y Read and discard 3 device check words from the RxFIFO Word 4D i Voo Read and verify the 32 bit checksum word of i each block loaded found in the RXFIFO Word 4D A Jumper for Y l BOOTEN1 b programming Read the Product ID code and the FI version i serial memory code from the RxFIFO Word 4D i BOOTEN2 4 if required T CMX7164 is now ready for use Figure 14 FI Loading from Serial Memory The CMX7164 has been designed to function with the AT25F512 serial flash device however other manufacturers parts may also be suitable The time taken to load the FI should be less than 500ms even when loading the largest possible Function Image 2012 CML Microsystems Plc Page 27 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 6 4 Device Control Once
84. er filters which may for example be used to compensate for two different crystal filters in a radio designed to receive in two channel bandwidths Although trained using a 4 QAM signal the resulting filter is suitable to compensate for the receiver response whilst receiving 4 16 or 64 QAM signals A suitable training signal may either be produced using another CMX7164 or the training sequence described in section 13 9 Fl 4 x Receiver Response Equaliser Training Sequence The Receiver Response Equaliser has two modes single mode produces better results when correcting for receivers with a simple baseband roll off for example in a direct conversion architecture Dual mode produces better results when compensating for a radio receiver which includes a crystal filter Program Block 11 Receiver Response Equaliser Fl 4 x only provides equaliser mode selection allows adjustment of the gain used in the feedback path when training the equaliser and allows the training time to be altered The same program block allows the filter resulting from training to be read for storage and to be be programmed back in to the CMX7164 later for use when receiving An example of the effect of the receiver crystal filter on a 4 and 16 QAM signals is shown in Figure 68 Once the equaliser has been trained the resulting received signal was as shown in Figure 69 Each plot is gathered by using the Rx diagnostics mode of the 7164FI 4 x see section 6 4 12 Other Modem Modes
85. ernal COM sis ree EENS 17 4 1 Aal Interface eee he te ette ente eh 17 4 2 EE Ee 17 4 3 UO Output Reconstruction Eiter 18 4 4 UO Input Antialias Eiter 18 4 5 G PIO DIE 18 5 General Description scvcsecacecteessccteceene ccantesaceesenctecteneacetedscctencuctesuutyect ROET OER 19 5 1 CMX71064 Featutes sec ten deve erede he eee eei e sete een deine 19 5 2 Signal Interfaces UO Tx and HX seene 20 5 3 Signal Interfaces Two point Tx and UO Rx sese eee eee 21 6 Detailed DeSCriptions cccsseeeeesseeeeeeesseeeeeesseneesesseneesesseneesesseeeesesseneesesseeeeeesseneeeesseneees 22 6 1 Xtal Frequericy EE 22 6 2 Host mern TEE 22 62A C BUS ele e aote ee Avnet reels eene reste evi A 22 6 3 Function Image Loading BETEN 25 6 3 1 Fl Loading from Host Controller 25 6 3 2 Fl Loading from Serial Memonm sss eee eee eee eee eee eee 27 6 4 Device GOnltrol o t tmb tte fate tct meet tette E 28 6 4 4 Normal Operation OvervieW nennen enne 28 6 4 2 Basic Tx and Rx Operation 29 6 4 3 Device Configuration Using the Programming Register 30 6 4 4 Device Configuration Using dedicated reglsiers sss 31 6 4 5 Interrupt Operation 31 6 4 6 Signal Gontrol 2 c aeta eee eaa eere nu 31 E Da ge die unire eR Meade rere c RU UE eR s 32 p 4 8 PFoxMOdG i obedece te enu 34 6 4 9 Carrier Sense Mode A 35 6 4 10 The Transmit Geouence nennen nennen enne nnns 37 6 4 11 CMX998 DC Offset Calibration
86. ernal Components Xtal Interface 17 Figure 7 Recommended External Components C BUS Intertace sees ee eee eee ee 17 Figure 8 Recommended External Components UO Output Reconstruction Filter 18 Figure 9 CMX7164 VQ Tx VQ PHS a Ge aaia Hea enne nnnm n nnne nnns nennen nnne nnns 20 Figure 10 CMX7164 Two point Tx l Q Rx nennen nnne 21 Figure 11 Basic C BUS Transactions nennen nnne 23 Figure 12 C BUS Data Streaming Operation 24 Figure 13 Fl Loading from Host EE 26 Figure 14 Fl Loading from Serial Memory nennen enne 27 Figure 15 Host Tx Data Flow No Tx Sequence Carrier Sense eee eee eee 33 Figure 16 Host Rx Data Flow ANEREN 34 Figure 17 Carrier Genee Au 36 Figure 18 Transmit Geouence nnne nennen entren rennen enne 37 Figure 19 CMX998 DC Calibration Interfaces nee 38 Figure 20 Transmit Constellation Z1GAELA xl 40 Figure 21 Transmit Eye Diagram 7164F1 2 x sese 40 Figure 22 Transmit Eye Diagram 71GAELTI le 40 Figure 23 Constellation Diagram no frequency or phase error sese eee ee eee ee ee 41 Figure 24 Constellation Diagram phase error eee eee eee eee eee 41 Figure 25 Constellation Diagram frequency error eee eee eee 41 Figure 26 Received Eye Diagram7164 Fl 2 x asses e resse neee 41 Figure 27 Received Eye Diagram7164 Fl 1 x asses sees ee eee eenn 42 Figure 28 Sample at Symbol Timing with UO DC Offset Diagnostic Mode no frequency error 42 Figure 29 Sample at Symbol Timing with UO
87. f the transmit sequence Figure 19 CMX998 DC Calibration Interfaces During calibration the CMX998 is controlled by the CMX7164 using the SPI Thru Port The CMX998 is assumed to be device 1 to select one of the following to be output to the CMX998 DCMEAS output Reference The CMX998 dc reference for the in phase signal path Q Reference The CMX998 dc reference for the quadrature signal path Error Low high gain The CMX998 measure of the dc produced by the input signal on the in phase signal path Q Error Low high gain The CMX998 measure of the dc produced by the input signal on the quadrature signal path The low and high gain states are created by adjusting the gain of the error amplifiers in the CMX998 see the CMX998 datasheet for more information 2012 CML Microsystems Plc Page 38 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 During calibration the CMX7164 uses AuxADC2 to measure Reference and Reference Q It then puts outputs a dc level on the Output Q Output signals AuxADC2 is used to measure the DCMEAS and Q Error and Output Q Output are adjusted to make the DCMEAS and Q errors equal to the DCMEAS Reference and Q Reference measurements There are three complications to this process 1 The total gain of the feedback loop Output to CMX998 DCMEAS Error signal to AuxADC is unknown so the adjustment to the Output signal may not be calculated completely accurately from a s
88. figure in dB RxBW receiver noise bandwidth which in Figure 75 Figure 82 is 18kHz Mean signal power is in dBm SNR Signal to Noise Ratio in dB 1 0E 02 1 es AQAM Raw 16QAM Raw 64QAM Raw 1 0E 03 BER 1 0E 04 1 0E 05 4 E nD annA 10 12 14 16 18 20 22 24 26 28 30 32 Signal to Noise Ratio dB Figure 75 Modem Sensitivity Performance The co channel rejection ratio Figure 76 is measured with an interferer modulated with 400Hz FM and having a deviation of 3kHz which is 12 of the nominal 25kHz channel bandwidth This particular interfering signal is used as it is specified in ETSI standard EN 300 113 for co channel tests The measurement is taken at approximately 20dB above sensitivity and although this is not in line with 2012 CML Microsystems Plc Page 91 D 7164 Fl 1 x FI 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 EN 300 113 it means that the data presented here gives a true representation of the performance of the 7164Fl 4 x modem rather than being partially influenced by the thermal noise level The methodology is in line with standards for 6 25kHz channel spaced systems EN 301 166 1 0E 02 rrr 4QAM Raw 16QAM Raw 64QAM Raw 1 0E 03 BER 1 0E 04 7 10 13 16 19 22 25 28 Co channel Rejection Ratio dB Figure 76 Modem Co channel Rejection with FM Interferer as EN
89. gain threshold is met and signal gt high selection or a false threshold then backoff detect so continue running AGC normally Figure 36 AGC Behaviour During Burst Reception A general issue with I Q receivers is that of dc offsets Offsets are generated by the receiver hardware and typically vary with channel selection but depending on receiver architecture can also change with gain The CMX7164 is capable of calculating WO dc offset corrections but if the gain steps suddenly and therefore the dc offset changes suddenly errors may occur Once again this may only be an issue for longer bursts when it is necessary to change gain during reception To overcome the dc offset issue the CMX7164 allows an WO dc offset correction to be latched in for each AGC gain step When a gain step other than maximum gain is selected the tabulated dc offset correction will become active and tracking will be suspended Additionally in receivers with large dc offsets present a gain change may result in a sufficiently large step in dc offset that the signal will look small large to the AGC algorithm resulting in unwanted gain changes The CMX7164 is able to use the WO dc offset information to correct for this effect AGC thresholds and parameters may be changed during reception for ease of setup and are controlled using the Signal Control 61 write register All times are measured in units of 6 5 of a symbol period All levels or thresholds are compared to the ma
90. gnitude of signed 16 bit samples with max range therefore being 32767 to 32768 See 11 2 8 Program Block 6 SPI Thru Port Configuration 11 2 9 Program Block 7 AGC Configuration 11 1 14 AGC Control 65 write 11 1 10 Signal Control 61 write 13 3 1 Effect of AGC on DC Offsets 2012 CML Microsystems Plc Page 49 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 6 5 Digital System Clock Generators The CMX7164 includes a two pin Xtal Oscillator circuit This can either be configured as an oscillator as shown in section 3 or the XTAL CLK input can be driven by an externally generated clock The crystal Xtal source frequency is typically 9 6MHz and if an external oscillator is used the input frequency is typically 9 6 or 19 2 MHz For both cases reference frequencies in the range specified in 10 1 2 Operating Limits may be used 6 5 1 Main Clock Operation A digital PLL is used to create the main clock for the internal sections of the CMX7164 The configuration of the main clock and the internal clocks derived from it is controlled using Program Block 1 Clock Control The CMX7164 defaults to settings appropriate for a 19 2MHz externally generated clock with a baud rate of 9 6ksymbols s however if a different reference frequency is to be used or a different baud rate required then Program Block entries P1 1 to P1 6 will need to be programmed appropriately at power on A table of preferred values is
91. gure 48 and Figure 49 It should be noted that error rate performance depends on the modulation rate deviation and BT results have been taken for typical channel bandwidths The 7164Fl 1 x supports multiple combinations of these factors but it is beyond the scope of this document to provide data for every combination Data is provided showing a selection of representative cases ranging from best case performance with coding to worst case where no coding is used raw mode plus the effect of using different BT values In the following graphs the modulation is GMSK and the data rate is dependent on channel bandwidth The 25kHz channel data rate is 9 6ksymbols s the 12 5kHz channel data rate is 8ksymbols s which is typical of the rate that may be achieved in each RF channel The signal to noise ratio is calculated as SNR Mean signal power 174 NF 10 logi RXBW Where NF receiver noise figure in dB RxBW receiver noise bandwidth Mean signal power is in dBm SNR Signal to Noise Ratio in dB The graph in Figure 47 compares the raw sensitivity performance of data transfer using a 12 5kHz and a 25kHz channel Pulse shaping was achieved using a Gaussian filter with BT 0 5 in the 25kHz channel and BT 0 3 in the 12 5kHz channel The modulation parameters used in all of the figures that follow in this section are summarised below Channel Baud Rate Pulse Shaping Deviation Measured Receiver Noise Us
92. has been adjusted to give a realistic Tx ACP in the 6 25kHz and 12 5kHz case the Tx ACP was 63dBc and in the 25kHz case the Tx ACP was 73dBc The pulse shaping filter used was an RRC with no sinc filter in place The modulation parameters used in all of the figures that follow in this section are summarised below Channel Baud Rate Pulse Shaping Deviation Measured Receiver Noise Used in Bandwidth Symbols s Filter KHz Tx ACP Bandwidth kHz Figures KHz dBc 25 9600 RRC Only 2 85 72 18 Figure 60 12 5 4800 RRC Sinc 2 45 63 9 Figure 61 12 5 4800 RRC Only 1 9 63 9 Figure 60 Figure 61 Figure 62 Figure 63 Figure 64 6 25 2400 RRC Only 0 95 63 4 5 Figure 60 2012 CML Microsystems Plc Page 76 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 1 00E 02 N v 6 25k Channel Ki 12 5k Channel N _ ZB Channel 1 00E 03 tc ul 1 00E 04 a 1 00E 05 1 00E 06 t t t i t t t t d 10 0 11 0 12 0 13 0 14 0 15 0 16 0 17 0 18 0 19 0 20 0 Signal to Noise Ratio dB Figure 60 Modem Sensitivity Performance Root Raised Cosine Pulse Shaping The 7164Fl 2 x supports pulse shaping filters using an alternative RRC plus sinc filter option Simply switching from a RRC Only filter to this filter reduces the bandwidth of the modulated signal so an increased deviation was used to return the Tx ACP to 63dBc The graph in Fig
93. hecksum calculation should be reset as required using the Reset CRC block type so that any transmitted CRC2 contains the CRC of only the desired blocks In receive it must be reset to match the expected input data block sequence A variety of different frame formats are possible some examples are illustrated in Figure 54 A A SYMBOL FRAME l ae ig ERAMI HEADER BLOCKS B B SYMBOL FRAME LAST Merval Kee INTERMEDIATE BLOCKS dui svveoL FRAME INTERMEDIATE BLOCKS EE SYNC SYNC Figure 54 Suggested Frame Structures The CMX7164 performs all of the block formatting and de formatting the binary data transferred between the modem and its uC being that enclosed by the thick dashed rectangles near the top of Figure 53 When receiving header blocks and last blocks the CMX7164 will indicate CRC success or failure and will provide the data regardless In Figure 53 the size of data block illustrated is always 12 bytes when user bytes and CRC bytes are counted together The CMX7164 adds further flexibility by supporting block sizes of 6 or 9 bytes total the resulting data content being Table 4 Formatted Block Types Sizes and Rates FI 2 x User CRC bytes for a Block Type Block Size Coding Rate 4 FSK only Header Block Inter Block Last Block 0 6 bytes 0 75 Excluding pad tri bit 4 2 6 2 4 1 9 bytes 0 75 Excluding pad tri bit 7 2 9 5 4 2 12 bytes 0 75 Excluding pad tri bit
94. ignals using a radio receiver the signal provided to the CMX7164 is likely to be distorted Considering the architecture of Figure 66 as typical the distortion will largely be caused by the crystal filter shown as a bandpass filter in the diagram The crystal filter operates on the received signal at an intermediate frequency its purpose is to attenuate unwanted signals such as those on adjacent channels before they get to the CMX7164 9 Typically the pass band of the crystal filter is not flat or perfectly linear phase resulting in the wanted QAM signal being distorted due to the amplitude phase response of the filter The result is usually a significantly degraded receive signal and therefore poor receive performance Other radio architectures may provide baseband filtering in order to help reject unwanted adjacent channel signals Such filtering may also have a pass band that is not flat and therefore will degrade reception The CMX7164 provides a Receiver Response Equaliser that will compensate for the group delay and variation in gain of the crystal filter or any other distortions present in the received signal The equaliser must be trained with a clean high level 4 QAM signal in order to establish the receiver response and produce a filter which compensates for it Once this filter is calculated it may be read from the CMX7164 and stored for later use The CMX7164 can be configured with up to two previously stored Receiver Response Equalis
95. in a 12 5kHz channel bandwidth A rate of 9 6kbps with BT 0 5 is typical in 25kHz bandwidth channels while meeting the transmit and receive requirements of international standards such as EN 300 113 Channel bandwidth is dependent on the deviation that the modulating signal causes the carrier to deviate by as well as the data rate and the BT As a result the user can choose to configure the device to suitable settings for a particular application 7 2 7164Fl 1 x Radio Interface The transmit radio interface of the 7164Fl 1 x can be set to two point modulation or UO When the 7164FI 1 x is in two point modulation mode the Output is used as Mod 1 and the Q Output is used as Mod 2 The receive signal must come from an UO radio receiver 7 2 1 VQ Transmit and UO Receive Interfaces The 7164FI 1 x can produce an WO modulated signal taking a baseband modulating signal and using it to frequency modulate an UO baseband signal with a user programmable deviation In receive the 7164FI 1 x will accept an UO input signal and provide significant channel filtering digitally It will then frequency demodulate the resulting signal which is treated as a limiter discriminator output signal would be internally An overview of how the CMX7164 might use the CMX992 for reception and the CMX998 for transmission is shown in Figure 39 The internal functions of the CMX7164 when operating in this mode are shown in Figure 3 Note that the transmit and rec
96. ing these maximum ratings can result in damage to the device Min Max Units Power Supplies DVpp DVss 0 3 4 0 V DVcore M DV as 0 3 2 16 V AVpp AVss 0 3 4 0 V Voltage on any pin to Vss 0 3 IOVpp O 3 V L9 Package 64 pin LQFP Min Max Units Total Allowable Power Dissipation at Tamg 25 C 1690 mW Derating 16 9 mW C Storage Temperature 55 125 C Operating Temperature 40 85 g Q1 Package 64 pin VQFN Min Max Units Total Allowable Power Dissipation at Tamg 25 C 3500 mW Derating 35 0 mW C Storage Temperature 55 125 2 Operating Temperature 40 85 C 10 1 2 Operating Limits Correct operation of the device outside these limits is not implied Min Typ Max Units DVpp DV ss 3 0 3 3 3 6 V DV coge D Vas 1 7 1 8 1 9 V AVpp AVss 3 0 3 3 3 6 V Operating Temperature 40 85 C Xtal Frequency 3 0 12 288 MHz External Clock Frequency 3 0 24 576 MHz 2012 CML Microsystems Plc Page 101 D 7164 FI 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 10 1 3 Operating Characteristics Details in this section represent design target values and are not currently guaranteed For the following conditions unless otherwise specified External components as recommended in Section 4 External Components Maximum load on digital outputs 30pF Xtal Frequency 9 6MHz 0 002 20ppm Tame 40 C to 85 C AVpp DVpp 3 0V to 3 6V Current consumption figures quoted in this section apply to the device
97. ingle measurement Therefore the gain applied to the calculated adjustment may be programmed and a number of iterations selected resulting in a damped feedback loop 2 The dc error to be corrected is usually large enough that if measured with the CMX998 in high gain mode the DCMEAS output would saturate This makes calculation of the magnitude of error impossible Therefore low gain mode should be used initially 3 When changing from low to high gain modes the circuit changes see dc calibration Application Note CMX998 Cartesian Feedback Loop DC Calibration therefore the correction needed changes However the low gain correction should at least be close to bringing the high gain measurement out of saturation The relationship between correction computed using low gain and high gain is consistent so may be noted and applied as an offset The calibration sequence implemented in the CMX7164 has the following stages Setup Initialise the SSP port AuxADC and select Refl as DCMEAS output from the CMX998 Refl Read Refl select DCMEAS RefQ RefQ Read RefQ select DCMEAS Errorl ErrorlLo Read Errorl assuming Low gain and adjust the Output accordingly ErrorQLo Read ErrorQ assuming Low gain and adjust the Q Output accordingly Iterate go to ErrorlLo after a delay for corrected signals to settle HighGain Select High gain mode of the CMX998 apply Low to High gain mode correction ErrorQHi Read ErrorQ assuming High gain and adjust the Q
98. it rate Accuracy 70 ppm Tx Output Level I Output Q Output 71 TBD Vp p Tx Adjacent Channel Power Output Q Output 72 dB PRBS Rx Frequency Error Tolerated 75 1 0 kHz Rx Co channel Rejection 73 dB Rx Adjacent Channel Rejection 73 S dB Notes 70 Determined by the accuracy of the Xtal oscillator provided 71 Transmitting continuous default preamble 72 See section 8 4 7164F1 2 x Typical Transmit Performance 73 See section 8 5 7164Fl 2 x Typical Receive Performance 75 Optimum performance is achieved with OHz frequency error The figure quoted is for a symbol rate of 9 6kHz The frequency error tolerated is proportional to the symbol rate 2012 CML Microsystems Plc Page 110 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 10 1 6 7164Fl 4 x Parametric Performance Details in this section represent design target values and are not currently guaranteed For the following conditions unless otherwise specified External components as recommended in section 4 Maximum load on digital outputs 30pF Clock source 19 2MHz 0 002 20ppm clock input Tame 40 C to 85 C AVpp DVpp 3 0V to 3 6V Reference signal level 308mV rms at 1kHz with AVpp 3 3V Signal levels track with supply voltage so scale accordingly Signal to Noise Ratio SNR in bit rate bandwidth Input stage gain OdB Output stage attenuation OdB All figures quoted in this section apply to the device when loaded with FI
99. n 2012 CML Microsystems Plc Page 59 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 Marker 1 T1 RBW 200 Hz RF Att 30 dB Ref Lvl 24 60 dBm VBW 1 kHz O dBm 447 99923948 MHz SWT 4 2 s Unit dBm Modulation Spectrum H EN 300 113 x d w d Adjacent Channel measurement for 25kHz channel 40 ACP lt 73dB E limit is 60dB Integration window 8kHz 60 70 Peak deviation 1 symbol 2 0kHz 80 90e 100 Center 448 MHz 3 3 KHz Span 33 kHz cr 448 MHz Meas Signal Ref Lvl SR 8 kHz Eye I D dBm Demod 2FSK 100m ES REAL mi Eye Diagram EXT BURST NOT FOUND 100m 0 SYMBOLS 4 Figure 44 Tx Modulation Spectra GMSK 8kbps BT 0 3 I Q Modulation 2012 CML Microsystems Plc Page 60 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 Spectrum Analyser Vector Signal Analyser IC 1 IOUTPUT Mod1 or QOUTPUT Mod2 i CMX7164 E ME RF Signal Generator DC FM Modulation Input Buffer Amplifier if required to drive RF signal generator modulation input Figure 45 Tx Spectrum and Modulation Measurement Configuration for Two point Modulation Using the test system shown in Figure 45 the 7164FI 1 x internal PRBS generator was used to modulate
100. n of these features are 11 1 8 UO Output Control 5D 5E write 11 1 9 UO Input Control 5F 60 write 11 1 21 I Q Input Coarse Gain B1 B2 write 11 1 23 UO Output Coarse Gain B4 B5 write 11 1 22 UO Output Configuration B3 write 11 1 20 UO Input Configuration BO write 11 1 5 AuxADC1 4 Control 51 to 54 write 11 1 6 AuxADC1 4 Threshold 55 to 58 write 11 1 10 Signal Control 61 write 11 1 14 AGC Control 65 write 6 4 5 Interrupt Operation The CMX7164 can produce an interrupt output when various events occur Examples of such events include detection of a frame sync an overflow of the internal data buffering in receive or completion of transmission whilst in transmit Each event has an associated IRQ Status register bit and an IRQ Mask register bit The IRQ Mask register is used to select which status events will trigger an interrupt on the IRQN line All events can be masked using the IRQ mask bit bit 15 or individually masked using the IRQ Mask register Enabling an interrupt by setting a mask bit 0 1 after the corresponding IRQ Status register bit has already been set to 1 will also cause an interrupt on the IRQN line The IRQ bit bit 15 of the IRQ Status register reflects the IRQN line state All interrupt flag bits in the IRQ Status register are cleared and the interrupt request is cleared following the command address phase of a C BUS read of the IRQ Status register See e 11 1 37 IRQ Status 7E
101. nage the data flow Likewise in receive the host can request continual data reception and the resulting bytes will be placed in the Rx Data FIFO FIFO levels and level IRQs may be used to manage the data flow This mode provides the ability to simply stream using streaming C BUS if desired multiple bytes into or out of the CMX7164 as FIFO content allows 6 4 16 Formatted Data Transfer When the transfer of formatted data is selected by the Modem Mode and Control 6B write register the FIFO Control byte indicates the block type to use in either sending or decoding the data The block type dictates the format or quantity of data transferred including how error detection and correction bits are added to the over air data stream 6 4 17 Pre loading Commands It is advisable to pre load data into the Command FIFO before transmission begins or to pre load receive data commands into the Command FIFO prior to frame sync reception 6 4 18 GPIO Pin Operation The CMX7164 provides four GPIO pins each pin can be configured independently as automatic manual input output and rising falling with the exception of the combination automatic input function which is only allowed for GPIOA Pins that are automatic outputs become part of a transmit sequence and will automatically switch along with the RAMDAC AuxDACH if it is configured as automatic during the course of a burst Pins that are manual are under direct user control When automatic a rising
102. nce was measured with and without equalisation being applied then the temperature was varied and the equalised and non equalised bit error rate measurements repeated The results are shown in Figure 86 and Figure 87 The results show that equalisation is most effective at the temperature at which calibration was carried out and that performance degrades outside of this temperature For all results a frequency error between transmitter and receiver of less than 100Hz magnitude was observed As the crystal filler was that used in EV9910B EV9920B we should note that its specified range of operation is 20 to 55 deg C It was also observed that a re calibration at a given temperature would result in equalisation coefficients capable of producing a much improved BER at that temperature 11 Evaluation card for CMX991 CMX992 RF Quadrature Transceiver Receiver ICs 2012 CML Microsystems Plc Page 99 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 1 00E 01 4 1 00E 02 1 00E 03 L BER 4 1 00E 04 No Equalizer 1 00E 05 4 ws With Equalizer 1 00E 06 40 15 10 35 60 85 Temperature deg C Figure 87 Performance of 64 QAM equalised signals with temperature variation 2012 CML Microsystems Plc Page 100 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 10 Performance Specification 10 1 Electrical Performance 10 1 1 Absolute Maximum Ratings Exceed
103. nnel bandwidth is dependent on the peak deviation that the modulating signal causes the carrier to deviate by as well as the data rate The bit to symbol mapping that this Function Image uses for 2FSK and 4FSK is 2FSK bit to symbol mapping 4FSK bit to symbol mapping Input Bit Relative Input Bit Relative Symbol Symbol Level Pair Level 0 3 00 1 01 3 1 3 10 1 11 3 RRC filters are implemented at both Tx and Rx with a filter alpha of 0 2 Marker 1 T1 55 5000 sym CF 450 MHz Meas Signal Ref Lvl FreqDev 4 923 kHz ep 9 6 kHz Frequency 0 dBm Demod 4FSK 1 5h T FREQ Tl w E URST NOT FOUND 0 SYMBOLS 99 9375 Figure 50 4 FSK PRBS Waveform Two point modulation 8 2 7164Fl 2 x Radio Interface The transmit radio interface of the 7164Fl 2 x can be set to two point modulation or UO When the 7164FI 2 x is in two point modulation mode the Output is used as Mod 1 and the Q Output is used as Mod 2 The receive signal must come from an WO radio receiver 2012 CML Microsystems Plc Page 67 D 7164 FI 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 8 2 1 IQ Tra
104. no adjacent channel selectivity in the radio circuits In a more normal RF architecture some adjacent channel selectivity will be provided making system results better than the measured values for the 7164Fl 2 x alone Furthermore the results observed are not necessarily the maximum that the CMX7164 can achieve but are limited by the practical dynamic range of the CMX7164 combined with the System gain and noise figure of the receiver used in these tests 8 5 3 Receiver Dynamic Range The adjacent channel rejection results in section 8 5 2 also indicate that a wanted signal can be successfully received over the dynamic range shown in Figure 64 without any need for an AGC Note that this is limited at the top end by the maximum allowed signal amplitude into the CMX7164 but performance at the bottom end is affected by noise added by the test receiver so these figures are not the absolute limit of CMX7164 FI 1 x 2 x 4 x performance 2012 CML Microsystems Plc Page 80 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 9 7164FI 4 x Features The 7164FI 4 x uses a QAM modulation scheme switchable between 4 16 and 64 QAM on a burst by burst basis The symbol rate is configurable up to 20ksymbols s resulting in 106 000 user bits per second maximum Raw data can be transferred in addition to formatted data blocks Formatted data blocks may be of variable length from 15 to 416 bytes and support a combination of 16 bit or 32 bit
105. nsmit and I Q Receive Interfaces The 7164F1 2 x can produce an WO modulated signal taking a baseband modulating signal and using it to frequency modulate an UO baseband signal with a user programmable deviation In receive the 7164F1 2 x will accept an UO input signal and provide significant channel filtering digitally It will then frequency demodulate the resulting signal which is treated as a limiter discriminator output signal would be internally An overview of how the CMX7164 might use the CMX992 for reception and the CMX9988 for transmission is shown in Figure 51 The internal functions of the CMX7164 when operating in this mode are shown in Figure 3 Note that the transmit and receive interfaces are identical to those used for QAM modulation in Figure 66 facilitating multi mode modem operation However no linearisation is required when transmitting 2 4FSK HOST Y A SEY te TEE SERERE Bea AA GPIOn ___ HP i 1 i 1 l E ac E l PE ana LNA Enable E z X CMX7164 I I U l Ar EEA Bis l e GPIO Tx Rx CN j Gi Input st LNA Lo 2x ADC C BUS Q Q Input j CMX992 A Thru C BUS Local Oscillator PA Gain Control RAMDAC n yet EE Aux DACO 2x DAC m Ld X 90 Directi
106. o Idle Process Figure 16 Host Rx Data Flow 2012 CML Microsystems Plc Page 34 D 7164 Fl 1 X FI 2 x FI 4 x 9 CMX7164 Multi Mode Modem CMX7164 6 4 9 Carrier Sense Mode Carrier sense mode is a receive mode pending a transmission A carrier sense period averaging window length and threshold must be defined in the Program Blocks prior to entering this mode The signal strength is calculated internally as the UO signal contains amplitude information On entry to Carrier Sense mode reception will begin or continue if the previous mode was receive with an attempt to search for a frame sync During the defined carrier sense period average RSSI will be computed over a moving window Three outcomes are possible 1 If during the carrier sense period the average RSSI is above the carrier sense threshold then transmission will be aborted and search for frame sync will continue The device reverts to receive 2 There is a possibility that a valid frame sync will be detected during the carrier sense period If this is the case the transmission will be aborted immediately and the device will revert to receive 3 Ifthe RSSI average remains below the carrier sense threshold then transmission will proceed In each of the three possible cases status bits will be used to indicate the result of the carrier sense period If the carrier sense mechanism is used in conjunction with GPIOA as a Tx trigger operation is as follows the de
107. odulation Spectra GMSK 9 6kbps BT 0 5 WO Modulation 59 Tx Modulation Spectra GMSK 8kbps BT 0 3 HO Modulation 60 Tx Spectrum and Modulation Measurement Configuration for Two point Modulation 61 Tx Modulation Spectra GMSK 8kbps BT 0 3 Two point Modulation 62 Modem Sensitivity Performance ener 64 Sensitivity 12 5kHz Channel 8ksymbols s With and Without Coding 65 Modem Co channel Rejection with FM Interferer as EN 300 113 66 4 FSK PRBS Waveform Two point modulatton sss sese eee eee eee eee eee 67 Outline Radio Design UO in out for 2 or AFGR sss sees eee 68 Outline Radio Design 2 or 4FSK HO in two point mod out 69 Formatted Data Over Air Signal Format sese eee eee eee eee eee 70 Suggested Frame Structures see eee eee 71 Tx Spectrum and Modulation Measurement Configuration for UO Operation 71 Tx Modulation Spectra 4FSK 19 2kbps 9 6ksymbols s UO Modulation 72 Tx Modulation Spectra 2FSK 19 2kbps UO Modulsaton sss sese 73 Tx Spectrum and Modulation Measurement Configuration for Two point Modulation 74 Tx Modulation Spectra 4FSK 19 2kbps Two point Modulation 75 Modem Sensitivity Performance Root Raised Cosine Pulse Shaping 77 12 5kHz Channel Sensitivity With and Without Sinc Filter Com
108. ompletion The default profile is a Raised Cosine see Table 11 in the user manual but this may be over written with a user defined profile by writing to Program Block 0 The AuxDAC outputs hold the user programmed level during a powersave operation if left enabled otherwise they will return to zero See e 11 1 7 AuxDAC1 4 Control 59 to 5C write e 11 2 2 Program Block 0 RAMDAC e 11 2 3 Program Block 1 Clock Control e 11 2 7 Program Block 5 Burst Tx Sequence 6 4 24 SPI Thru Port The CMX7164 offers an SPI Thru Port which allows the host using the main C BUS interface to command the CMX7164 to read or write up to three external SPI C BUS devices attached to the CMX7164 The CMX7164 acts as a SPI C BUS master in this mode controlling three chip selects clock and data out MOSI and receiving data in MISO Each individual SPI C BUS device can be independently configured using Program Block 6 SPI Thru Port Configuration to have clock speed inter frame guard period and clock phase polarity to match the specification of the slave SPI C BUS device attached In order to offer a simpler more convenient interface a device can be designated C BUS rather than SPI This means that data read written is assumed to be in the format Address byte data byte1 optional data byte 2 optional In each case the CMX7164 as the master drives the address and data for a write operation or drives the address and receives the data for
109. onal Power Q Coupler Amplifier L lt Output at Q Output Ze L S 90 lt Local Oscillator L CMX998 Figure 51 Outline Radio Design I Q in out for 2 or 4FSK Use of UO receive mode brings with it the problem of UO dc offsets There are dc offsets caused by the radio receiver resulting in the signal into the CMX7164 having a dc offset other than BIAS The offset needs to be removed prior to demodulation Offsets typically remain constant for a particular radio frequency selected but will vary if that frequency is changed Gain within the radio receiver may also affect the dc offset seen by the CMX7164 UO dc offset effects are a radio issue which is beyond the control of the CMX7164 However the CMX7164 does provide dc offset calculation and removal These are described in detail in the application note section 13 3 DC Offsets in UO Receivers 5 CMX992 is an RF Quadrature IF Receiver 6 CMX998 is a Cartesian Feedback Loop Transmitter which is designed primarily for non constant envelope modulations such as QAM although it will also support GMSK 4 FSK conventional UO vector modulators such as the CMX993 would be more typical of solutions for GMSK 4 FSK modulation 2012 CML Microsystems Plc Page 68 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 8 2 2 Two point Modulation Transmit with UO Receive Interface An overview of how the CMX7164 might integrate with an l Q receiver and two
110. or a falling event at the start or end of transmission will cause the specified GPIO to be switched high or low accordingly GPIOA may be configured as an automatic input This means that any attempted transmission will wait until GPIOA input is high if rising is selected or low if falling is selected See e 11 2 7 Program Block 5 Burst Tx Sequence e 11 1 13 GPIO Control 64 write e 11 1 33 GPIO Input 79 read 6 4 19 Auxiliary ADC Operation The inputs to the four Auxiliary ADCs can be independently routed from any of four dedicated AuxADC input pins or the two main inputs AuxADCs can be disabled to save power BIAS in the VBIAS Control B7 write register must be enabled for Auxiliary ADC operation Averaging can be applied to the ADC readings by selecting the relevant bits in the AuxADC1 4 Control 51 to 54 write registers This is a rolling average system such that a proportion of the current data will be added to the last value The proportion is determined by the value of the average counter in the AuxADC1 2012 CML Microsystems Plc Page 46 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 4 Control 51 to 54 write registers Setting the average counter to zero will disable the averager for an average value of 1 50 of the current value will be applied for a value of 2 25 3 12 5 continuing up to the maximum useful value of 11 0 0488 High and low thresholds may be independently appli
111. ost when a specified data block has been transferred or on FIFO fill level The CMX7164 offers internal buffering of data in addition to the Command and Rx FIFOs in both receive and transmit directions The amount of buffering offered is dependant on the mode in which the device is operating In the process of burst transmission or reception the most significant registers are 11 1 18 Modem Mode and Control 6B write 11 1 37 IRQ Status 7E read 11 1 19 IRQ Mask 6C write 11 1 3 Modem Command FIFO Data Control 48 49 and 4A write 11 1 26 Receive FIFO Data Control 4C 4D 4E read 11 1 25 Modem Command FIFO Level 4B read 11 1 27 Receive FIFO Level 4F read 2012 CML Microsystems Plc Page 28 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 6 4 2 Basic Tx and Rx Operation The CMX7164 has many features that provide a great deal of flexibility but basic data transmission and reception can be carried out fairly easily by understanding the operation of just a few registers There are other ways of controlling signal transmission and reception but basic examples are given below Basic Transmit Operation Transmission of raw data bytes uses the following procedure C BUS Operation Action Description Write 0080 to FIFO Control 50 write Flush the Command FIFO To ensure that no data is remaining from previous transmissions Write 18 to the Modem Select 8 byte data
112. parison 78 Sensitivity 12 5kHz Channel 4 8ksymbols s With and Without Coding 79 Modem Co channel Rejection with FM Interferer as EN 300 113 79 ACR Rejection Performance 80 QAM Mapplrigs 2 iste Me ee t tees ana tiiv Ree e 81 Outline Radio Design UO in out for OAMI 82 Suggested Frame Structures eene 83 Received 4 and 16 QAM signals no equalisation see eee eee eee eee eee 85 Received 4 and 16 QAM signals with equalisation see eee eee eee eee eee 85 Tx Spectrum and Modulation Measurement Configuration for UO Operation 86 Tx Modulation Spectra 4 QAM 18ksymbols s UO Modulation into CMX998 87 Tx Modulation Spectra 16 QAM 18ksymbols s UO Modulation into CMX998 88 Tx Modulation Spectra 64 QAM 18ksymbols s UO Modulation into CMX998 89 Tx Modulation Spectra 16 QAM 9ksymbols s UO Modulation into CMX998 90 Modem Sensitivity Performance sese eee eee eee eee eee eee eee 91 Modem Co channel Rejection with FM Interferer as EN 300 113 92 4 QAM Performance with Different Coding Schemes sss eee eee eee 92 16 QAM Performance with Different Coding Schemes sees eee eee eee 93 64 QAM Performance with Different Coding Gchemes sss sees ee eee eee 93 2012 CML Microsystems Plc Page 7 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 Figure 80 Figure 81 Figur
113. part no CMX7164L9 2012 CML Microsystems Plc Page 114 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 As package dimensions may change after publication of this datasheet it is recommended that you check for the latest Packaging Information from the Design Support Package Information page of the CML website www cmlmicro com finite Capabilities Firm ASI C About FirmASIC Maximum Flexibill CML s proprietary FirmASIC component technology reduces cost time to market and development risk with increased flexibility for the designer and end application FirmASIC combines Analogue Digital Firmware and Memory technologies in a single silicon platform that can be focused to deliver the right feature mix performance and price for a target application family Specific functions of a FirmASIC device are determined by uploading its Function Image during device initialization New Function Images IV may be later provided to supplement and enhance device functions expanding or modifying end product features without the need for expensive and time consuming design changes FirmASIC devices provide significant time to market and commercial benefits over Custom ASIC Structured ASIC FPGA and DSP solutions They may also be exclusively customised where security or intellectual property issues prevent the use of Application Specific Standard Products ASSP s Handling precautions This product includes in
114. point modulation transmitter is shown in Figure 52 The internal functions of the CMX7164 when operating in this mode are shown in Figure 4 Ss X ae Tx Rx Bus Q QINPUT CMX992 Local Oscillator Aoo ooo Thru C BUS PA Gain Control Power Amplifier PEL e o8 VCO HOST uP CMX7164 GPIO 2x ADC ___ RAMDAC Aux DAC1 2x DAC Reference IOUTPUT QOUTPUT e g VCTCXO MOD1 MOD2 Control Voltage Input Figure 52 Outline Radio Design 2 or 4FSK UO in two 2012 CML Microsystems Plc Page 69 point mod out D 7164 FI 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 8 3 7164Fl 2 x Formatted Data 4 FSK Only When transmitting receiving 4FSK the 7164Fl 2 x supports formatted data which provides the ability to channel code blocks of data using trellis coding and CRCs Formatted data is not available when 2FSK is selected The frame structure as used in a formatted data system is illustrated in Figure 53 It typically consists of a 24 symbol frame sync pattern followed by a Header Block one or more Intermediate Blocks and a Last Block Header Block Intermediate Blocks Last Block 7 6 5 4 3 2 1 0 7 6 5 4 32 140
115. provided in Table 13 along with details of how to calculate settings for other baud rates and crystal frequencies Prog Reg P1 2 PLL Cikin XTAL MAIN PLL PLL ClkOut Main PLL Tx Rx Active Prog Reg P1 5 out DIVIDER Clock 1 to 256 Prog Reg P1 1 Idle P1 4 Active Internal Prog Reg P1 0 System Clk Aux ADC 3 to 1024 COs Figure 37 Main Clock Generation See e 11 2 3 Program Block 1 Clock Control 2012 CML Microsystems Plc Page 50 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 6 5 2 System Clock Operation Two System Clock outputs SYSCLK1 and SYSCLK2 are available to drive additional circuits as required The System Clock circuitry is shown in Figure 38 Digital System Clock Generation Schemes Having chosen the input frequency source system clock generation may be by simply dividing the input frequency source or via its own phase locked loop The system clock PLL does not affect any other internal operation of the CMX7164 so if a frequency that is not a simple fraction of the Xtal is required it can be used with no side effects There is one phase locked loop with independent output dividers to provide phase locked output signals SYSPLLCONO SYSPLLCON1 SYSPLLCON2 1 to 4096 Local Clk VCO Clk SYSCLK PLL PLL ClkOut PLL ClkIn SysClkIn XTAL 0 0 SYSCLKCON b1 0 SYSCLKDIV1 b15 13 5
116. put protection however precautions should be taken to prevent device damage from electro static discharge CML does not assume any responsibility for the use of any circuitry described No IPR or circuit patent licences are implied CML reserves the right at any time without notice to change the said circuitry and this product specification CML has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification Specific testing of all circuit parameters is not necessarily performed ICML Microcircuits UK Ltd COMMUNICATION SEMICONDUCTORS CML Microcircuits E USA Inc COMMUNICATION SEMICONDUCTORS CML Microcircuits Singapore Pte Ltd COMMUNICATION SEMICONDUCTORS Tel 44 0 1621 875500 Fax 44 0 1621 875600 Sales sales cmimicro com Tech Support techsupport cmlmicro com Tel 1 336 744 5050 800 638 5577 Fax 1 336 744 5054 Sales us sales cmlimicro com Tech Support us techsupport cmimicro com Tel 65 62 888129 Fax 65 62 888230 Sales sg sales cmimicro com Tech Support sg techsupport cmimicro com www cmlmicro com 2012 CML Microsystems Plc Page 115 D 7164 Fl 1 X FI 2 x Fl 4 x 9
117. r Amplitude IQ Offset Proop 2 62 4 tms 5 60 1 Pk ac syn 4 1 67 1 rms 4 70 Pk et sym 116 1 16 deg rna 3 20 deg Pk at syn 64 128 75 ans 128 75 mHz Pk 0 40 dD sym Rho Factor 0 9994 0 28 1 IQ Imbalance 18 4 Error Vector Figure 71 Tx Modulation Spectra 4 QAM 18ksymbols s I Q Modulation into CMX998 2012 CML Microsystems Plc Page 87 D 7164 Fl 1 X FI 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 Marker 1 T1 RBW 500 Hz RF Att 20 dB Ref Lvl 16 00 dBm VBW 2 kHz 30 dBm 450 00284369 MHz SWT 1 35 3 Unit dBm 16 QAM Modulation spectrum with 18ksymbols s Adjacent Channel measurement for 25kHz channel ACP 75dB Integration window 16kHz L ap mu mud Wu l L al Center 450 MHz 6 6 kHz Span 66 kHz Aad cr 35D n s Meas Signal Es er 450 HH Heas Signal P A in L bie Pediat QD pat ivi EI 15 MRS Constellation 35 ap Deacd regas 39 080 nas vd L6 QAN SL dB Offset a 4 1666667 PEAL 4 160066 exr cr 450 miz Bet ivl sa 16 kHz Prabei ifsrerz 25 ana Desod 160A 31 aD Offre Symbol Tabie o 00111100 00000111 11110200 10000000 10001011 40 01100011 61110101 00011110 10111100 00000000 ER 560010000 00201116 01110011 o 0190619060 61169619 Error Sunmary BURST WOT FOUND Exror Veetor May 2 00 4 ens 4 32 4 Pk ac syn 125 Magnitude Error 1 25 ms 2 40 Pk et syn 106 Phaze Beror 1 49 deg rna 5 06 deg Pk at sym zo Freq Error
118. r Modem status Underflow yes mode if not automatically controlled by the GPIO pins note more data to send yes gt Load data to Command FIFO Lo ad TxEnd Command IRQ TxDone Yes x Execute RAMDAC rampdown See Rx Process flow diagram Due to internal processing delays in the filters etc the host should wait for IRQ TxDone or implement its own delay to ensure all data has been transmitted Mode Idle nete Goto Rx Process Set Modem Control to Idle The host should ensure that any external hardware is also set into Idle mode if not automatically controlled by the GPIO pins note Goto Idle Mode S Figure 15 Host Tx Data Flow No Tx Sequence Carrier Sense 2012 CML Microsystems Plc Page 33 D 7164 Fl 1 x FI 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 6 4 8 Rx Mode In Rx mode a frame sync must be detected then data is supplied to the host through the Rx Data FIFO Data should be read in response to a Cmd Done Rx Data FIFO IRQ or status indication The CMX7164 will continue decoding the input waveform until the host sets the mode bits to either Tx or Idle as required Once initial timing is established timing corrections can be derived from the data to track the received signal The Rx Tracking register allows selection of the tracking mod
119. r transmitting just waiting for a trigger on GPIOA to begin transmission In general Figure 15 describes operation when a transmit sequence is defined by the host by e Removing the need for the host to provide a ramp up instead the configured Tx sequence will deal with this e Inserting GPIO on off events before ramp up and after ramp down as specified by the transmit sequence 2012 CML Microsystems Plc Page 32 D 7164 FI 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 internal processi delays may occur at this point if enabled Ensure that RAMDAC speed is fast enough to allow for hardware and note Tx_Process I Y Load data to Command FIFO v Set Modem Control toTxPreamble Frame sync and required data mode Mode Tx This assumes that The transmit control sequence and frame syncs have been configured using the programming register Here the device is waiting for a GPIO trigger to start the transmission attempt As no carrier sense is P Tx BST lt triggered on GPIO lt YESH Wait for Tx Trigger selected it is not note receiving and is Execute RAMDAC rampup ng committed to transmit EDS GPIO Tx Trigger The Modem will transmit the preamble frame sync and data The host should ensure that any external hardware is also set into Tx IRQ CmdDone or Cmd FIFO IRQ Erro
120. re 26 Received Eye Diagram7164 F1 2 x 2012 CML Microsystems Plc Page 41 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 Figure 27 Received Eye Diagram7164 Fl 1 x Rx Diagnostics 7164FI 4 x only A diagnostic mode is provided that produces channel filtered UO signals and an optional dc offset correction indication This aids in diagnosing reception issues that may be related to UO dc offsets in the CMX7164 input signal This diagnostic mode can still be of use when there is a frequency error present in the received signal As shown in Figure 28 and Figure 29 the estimated UO dc offset correction is an extra dot in the centre of the constellation TTT TTT Ler TTP HR RE 4 d BHH Ts d UN s e Ze a T e 7 E lakea o la l RS Ig H 3 z n 3 MEE t4 B La rer tr A i s al j li rm 1 L L gt L 1 38 L 4 amp e E T i M a K a Te cole Ae kader e mitt iii i tel i iti te LR Figure 28 Sample at Symbol Figure 29 Sample at Symbol Timing with UO DC Offset Timing with UO DC Offset Diagnostic Mode no frequency Diagnostic Mode with error frequency error A normalised received constellation diagnostic output is provided It relies on having detected a frame sync
121. read e 11 1 19 IRQ Mask 6C write 6 4 6 Signal Control The CMX7164 offers two signal inputs I Input Q Input and two modulator outputs I Output Q Output The analogue gain attenuation of each input and output can be set individually During UO modulation transmit Output and Q Output will output in phase and quadrature output signals They may be independently inverted and their gains changed During UO modulation receive Input and Q Input will accept in phase and quadrature modulated signals They may be independently inverted and their gains changed During two point modulation transmit the 7164Fl 2 x or 7164FI 1 x will output two signals that may be used to drive VCOs in order to create FM modulation The two signals are provided on the and Q Outputs they may be independently inverted and their gains changed Note When transmitting or receiving in UO mode it may be necessary to swap the and Q signals This effect can be achieved by negating either the I or Q signals 2012 CML Microsystems Plc Page 31 D 7164 FI 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 See 11 1 8 UO Output Control 5D 5E write 11 1 9 UO Input Control 5F 60 write 11 1 21 UO Input Coarse Gain B1 B2 write 11 1 23 UO Output Coarse Gain B4 B5 write 11 1 22 UO Output Configuration B3 write 11 1 20 UO Input Configuration BO write 6 4 7 Tx Mode In typical Tx operation the preamble and FS1 or FS2 are transmi
122. rogramming registers only e Updated receive performance curves for Fl 4 e Added description of soft decision output bits for Fl 2 only e Added details of bus hold function for unused inputs e Added details of Core regulator select e Corrected conditions under which current measurements were made e Changed reference to input impedance of I Q INPUTs e Typos clarifications 7 e Remove constraint on use of document with Fl 2 x as the latter is now updated 21 09 11 6 e Advice in section 5 5 greyed out as not implemented in current FI 22 08 11 5 e Added advice about terminating unconnected GPIO pins in section 5 5 17 8 11 4 e Added details of default and inverting gains to the description of the UO Output 3 8 11 Control 5D 5E registers e Pointed out correct use of handshaking when using signal control Register 61 to select and Q offset measurements Registers 75 and 76 e Clarified behaviour of the and Q offset registers Rx dc offset correction when using automatic Rx IQ dc mode e Clarified behaviour and scaling of RSSI measurements e Documented further AGC controls added in Fl 4 0 5 4 and described AGC operation in detail e Documented the PII On bit added to the mode register in Fl 4 0 5 4 which provides a fast idle mode for programming register modifications without powersave but with improved speed e Added parameters in Program Block 1 to reduce delay when transitioning from Idle to Tx or Rx modes
123. roportional to this voltage This pin should be decoupled to AVss by capacitors mounted close to the device pins Negative supply rail ground for the analogue on chip circuits Auxiliary DAC output 1 Optionally the RAMDAC output Auxiliary DAC output 2 Auxiliary DAC output 3 Auxiliary DAC output 4 Negative supply rail ground for the digital on chip circuits Internally generated digital core voltage of approximately 1 8V This pin should be decoupled to DVss by capacitors mounted close to the device pins 3 3V positive supply rail for the digital on chip circuits This pin should be decoupled to DVss by capacitors mounted close to the supply pins Do not connect Negative supply rail ground for the digital on chip circuits Negative supply rail ground for the digital on chip circuits Output of the on chip Xtal oscillator inverter Page 14 D 7164 FI 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 58 59 60 61 62 63 64 EXPOSED METAL PAD XTAL CLOCK SYSCLK1 SYSCLK2 SCLK RDATA CDATA CSN IRQN DVCORE MOSI SSOUT1 MISO SSOUTO CLK GPIOA SUBSTRATE Description Input to the oscillator inverter from the Xtal circuit or external clock source Synthesised digital clock output 1 Synthesised digital clock output 2 C BUS serial clock input from the uC 3 state C BUS serial data output to the uC This output is high impedance when not sending data to the uC C BUS serial data
124. ror 16 147 11135 864 w GPIOControl J4 3J 3 16 133 11143 78 R SPIThru PortRead 16 145 11132 879 R GPOlpt 16 145 11133 68 W Modem Mode and Control 416 137 11118 7D R _ Programming Register Read 16 147 11136 BE IBO gene 1 16 148 11137 7F R ModemModeandControReadback 16 149 11138 80 W lQlnputConfiguraion 16 139 11120 B1 w llnputCoarse Gain JL 16 140 1121 All other C BUS addresses are reserved and must not be accessed 2012 CML Microsystems Plc Page 53 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 7 7164FiI 1 x Features The 7164Fl 1 x uses a GMSK GFSK modulation scheme with a configurable over air bit rate up to 20kbps The modulating signal is Gaussian filtered with a filter BT selectable from 0 5 0 3 0 27 or 0 25 Raw data can be transferred in addition to formatted data blocks Formatted data blocks may be of variable length up to 18 bytes and support 16 bit CRC for error detection plus hamming coding for error correction The modulation scheme and coding are designed to produce a signal that is over air compatible with the CML FX MX909B and CMX7143 7143Fl 1 x modems 7 1 7164Fl 1 x Modulation The GMSK GFSK modulation running at 8kbps with BT of 0 3 or less can be accommodated with
125. rough a typical IF crystal filter as used in EV9910B EV9920B is shown in the following graphs The nominal bandwidth of the filter is 15kHz however its response within that bandwidth is not flat both amplitude and group delay distortion is introduced into the signal The following tests were carried out using a 16ksymbols s 4 QAM 16 QAM or 64 QAM signal Where the results are quoted as using no equalisation the Receiver Response Equaliser was disabled Where the results are quoted as Equalised the Receiver Response Equaliser was provided a 4 QAM training sequence with level 70dBm which produced 400mvV differential on the and Q inputs Equaliser gain was set to 3000 and training lasted for 800 symbol periods While training the received signal had less than 100Hz frequency error Once trained the resulting equaliser coefficients were used for the remaining tests Firstly the signal to noise performance of equalised and non equalised received signals are compared The test is similar to that described in 9 6 1 Signal to Noise and Co channel Performance except that as the baud rate is 16ksymbols s the RxBW parameter is 16000 Applying this factor also means that the results in section 9 6 1 may be directly compared to those below in Figure 83 10 Evaluation card for CMX991 CMX992 RF Quadrature Transceiver Receiver ICs 2012 CML Microsystems Plc Page 96 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164
126. rovided in transmit or retrieved in receive This process is carried out by selecting the mode Tx Rx or Carrier Sense selecting the frame sync to use Frame Sync 1 or 2 and selecting formatted or raw data Such a selection is required at the beginning of transmission or reception of a burst In transmit or following a carrier sense period where no signal is detected on channel the CMX7164 will begin by switching GPIO signals as configured by the transmit sequence The RAMDAC can also be configured to ramp up at this point Transmission then begins with preamble and the selected frame sync The main payload of user data comes next ending with selectable tail bits The burst ends with the transmission sequence ramping the RAMDAC down and or switching GPIO signals In receive or following a carrier sense period where signal is detected on channel the CMX7164 will begin by searching for either or both of the configured frame sync patterns On detection of a frame sync reception and delivery of Rx data will begin Reception continues until the CMX7164 is switched into a different mode determined by the host During the burst data must be transferred into or out of the CMX7164 Transfers use the Command FIFO to transfer data and commands about data type into the CMX7164 and the Rx FIFO to transfer data out of the CMX7164 The IRQ Status register is used to indicate that the data has been dealt with The CMX7164 can be configured to interrupt the h
127. s SYSPLL Operating Frequency 38 250 MHz SYSCLK1 2 Output Frequency 20 MHz Rise Time 13 5 ns Fall Time 6 ns Veas Start up Time from powersave 30 ms Differential and Q Inputs Input Impedance Enabled 31 10 140 kQ Input Impedance Muted or Powersaved 200 kQ Maximum Input Voltage Excursion 32 20t080 AVpp Programmable Input Gain Stage Gain at OdB 33 0 5 0 40 5 dB Cumulative Gain Error w r t attenuation at OdB J 33 1 0 0 41 0 dB Notes 30 Timing for an external input to the XTAL CLOCK pin 31 With no external components connected 32 For each input pin and for AVpp 3 3V the maximum allowed signal swing is 3 3 x 0 8 3 3 x 0 2 2 0V 33 Design Value Overall attenuation input to output has a design tolerance of OdB 1 0dB 2012 CML Microsystems Plc Page 104 D 7164 FI 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 AC Parameters Notes Min Typ Max Unit Modulator UO Outputs I Output Q Output Power up to Output Stable 40 50 100 US UO Output Coarse Gain Attenuators Attenuation at OdB 42 0 2 0 0 2 dB Cumulative Attenuation Error 42 w r t attenuation at OdB J 0 6 0 40 6 dB Output Impedance Enabled 41 600 Q Disabled 41 2 TBD kQ Output Voltage Range 43 44 0 3 AVpp 0 3 V Load Resistance 20 kQ Notes 40 Power up refers to issuing a C BUS command to turn on an output These limits 41 43 44 apply only if Vgias is on and
128. s an RF Quadrature IF Receiver 8 CMX998 is a Cartesian Feedback Loop Transmitter 2012 CML Microsystems Plc Page 82 D 7164 FI 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 9 3 7164Fl 4 x Formatted Data The 7164Fl 4 x supports formatted data which provides the ability to channel code blocks of data using a variety of coding rates and CRCs A frame structure would typically consist of a 24 symbol frame sync pattern followed by a Header Block one or more Intermediate Blocks and a Last Block The Header block is self contained in that it includes its own checksum CRC1 and would normally carry information such as the address of the calling and called parties the number of following blocks in the frame if any and miscellaneous control information The Intermediate block s contain only data the checksum at the end of the Last block CRC2 also checks the data in any preceding Intermediate blocks This checksum calculation should be reset as required using the Reset CRC2 block type so that any transmitted CRC2 contains the CRC of only the desired blocks In receive it must be reset to match the expected input data block sequence A variety of different frame formats are possible some examples are illustrated in Figure 67 E A HEADER BLOCKS s INTERMEDIATE BLOCKS Figure 67 Suggested Frame Structures The CMX7164 performs all of the block formatting and de formatting When receiving header
129. s high or following a C BUS General Reset and must remain stable throughout the FI loading process Once the FI load has completed the BOOTEN1 2 pins are ignored by the CMX7164 until the next power up or Reset The BOOTEN 1 2 pins are both fitted with internal low current pull up devices For serial memory load operation BOOTEN should be pulled low by connecting it to DN lt lt either directly or via a 47k resistor see Table 1 Whilst booting the boot loader will return the checksum of each block loaded in the C BUS Rx Data FIFO The checksums can be verified against the values provided with the FI to ensure that the Fl has loaded correctly Once the FI has been loaded the CMX7164 performs these actions 1 The product identification code 7164 is reported in the C BUS Rx Data FIFO 2 The FI version code is reported in C BUS Rx Data FIFO Table 1 BOOTEN Pin States BOOTEN2 BOOTEN1 C BUS host load 1 1 reserved 1 0 Serial Memory load 0 1 reserved 0 0 6 3 1 Fl Loading from Host Controller The FI can be included into the host controller software build and downloaded into the CMX7164 at power up over the C BUS interface using the Command FIFO For Function Image load the FIFO accepts raw 16 bit Function Image data using the Modem Command FIFO Word 49 write register there is no need for distinction between control and data fields The BOOTEN1 2 pins must be set to the C BUS load config
130. scillator A gt 7 Thru C BUS PA Gain Control RAMDAC r IE cA C S ME cC CCP E EE anyone e Aux DAC1 2x DAC H H H H Reference IOUTPUT QOUTPUT e g VCTCXO MOD1 MOD2 S A PLL Q 4 Control vco Voltage Power Amplifier Input Figure 40 Outline Radio Design GMSK GFSK UO in two point mod out 2012 CML Microsystems Plc Page 56 D 7164 FI 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 7 3 T164Fl 1 x Formatted Data The 7164FI 1 x supports formatted data which provides the ability to channel code blocks of data using hamming coding and CRCs The frame structure as used in a formatted data system is illustrated in Figure 41 Typically it comprises a frame head consisting of a 16 bit sync word followed by a 16 symbol frame sync pattern control and data bytes and then one or more data blocks Frame Head Data Block MSB LSB MSB LSB 7 6 5 4 3 2 1 0 gi tag E Poesia Byte 0 Bit sync 1 ByteO T bw hl Byte 1 Bit sync 2 Byte 1 L D Byte 2 Frame sync1 Byte 2 Byte 3 Frame sync 2 Byte3 t Byte 4 l Control byte 1 Byte 4 G L Byte5 Control byte 2 Byte5 V Byte 6 rect Le Byte 6 T A Byte 7 Byte 8 F Data T 7 Byte 9 L 18 bytes FEC Byte 10 Byte 11 r T Nu Byte 12 L u Byte 13 E Byte 141 T _ Byte Bi L Byte 16 A Byte 171 T DATA BLOCKS Over Air signal BIT CTRL SYNC BYTES FEC 16 24 FRAME pq dDATABLOCK
131. ser Performance see eee eee eee eee eee 96 Performance Specification cccsecceseesseeeeeeeeeeseeeeeneeenseeensaeeeeseeseseaeeseeeeasaeseeseesesneeeeneneas 101 10 1 Electrical Performarico iei ero anter eed ib ci 101 10 1 1 Absolute Maximum Ratings seen 101 AO se 25 Operating Tl es tib teet RP tete obe edo eel te tallo rales eee Ne 101 10 1 3 Operating Characteristics 102 2012 CML Microsystems Plc Page 5 D 7164 FI 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 10 1 4 7164FI 1 x Parametric Performance sese essere essere sees reer enserre 107 10 1 5 7164FI 2 x Parametric Performance sees essere eser e eser ereer ener ennenen 108 10 1 6 7164FI 4 x Parametric Performance sese essere essere essere reer ener ennenen 111 10 2 Oro Local Bla ue DEE 113 UE WEN lee nt DEET 114 Table Page Table 1 BOOTEN Pin Giates A 25 Table 2 C BUS Register 53 Table 3 Formatted Block Types and Sizes FL si 58 Table 4 Formatted Block Types Sizes and Rates L 71 Table 5 Formatted Block Types Sizes and Rates LAN 83 Table 6 ACR Rejection Performance eee eee eee eee 96 Figure Page Figure 1 Overall Block Diagram sss sees eee eee eee eee 11 Figure 2 Fl 4 x Block Diagram UO Tx and RX sees eee 12 Figure 3 FI 1 x Fl 2 x Block Diagram UO Tx and Bn 12 Figure 4 FI 1 x Fl 2 x Block Diagram two point Tx with UO Hax 12 Figure 5 CMX7164 Power Supply and De coupling eee 16 Figure 6 Recommended Ext
132. specified External components as recommended in section 4 Maximum load on digital outputs 30pF Clock source 19 2MHz 0 002 20ppm clock input Tame 40 C to 85 C AVpp DVpp 3 0V to 3 6V Reference signal level 308mV rms at 1kHz with AVpp 3 3V Signal levels track with supply voltage so scale accordingly Signal to Noise Ratio SNR in bit rate bandwidth Input stage gain OdB Output stage attenuation OdB All figures quoted in this section apply to the device when loaded with Fl 2 x only The use of other valid Function Images can modify the parametric performance of the device DC Parameters Notes Min Typ Max Supply Current Rx Mode Dinn 4 8ksymbols s search for FS 12 9 Dilnn 9 6ksymbols s search for FS 20 2 Dipp 4 8ksymbols s FS found 8 7 Dipp 9 6ksymbols s FS found 11 6 Alpp AVpp 3 3V 7 7 Tx Mode 69 Dlpp 4 8ksymbols s 6 4 Diop 9 6ksymbols s 9 2 Alpp AVpp 3 3V 8 0 Unit 2012 CML Microsystems Plc Page 108 D 7164 FI 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 Notes 69 Transmitting in UO mode continuous 4FSK PRBS all GPIOs and RAMDAC set to manual 2012 CML Microsystems Plc Page 109 D 7164 FI 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 AC Parameters Notes Min Typ Max Unit Modem Symbol Rate 2 000 10000 syms Modulation 2 FSK or 4 FSK Filter RRC Alpha 0 2 Tx B
133. st I O resources Two synthesised system clock generators develop clock signals for off chip use The C BUS SPI master interface expands host C BUS SPI ports to control external devices Function Image The device utilises CML s proprietary FirmASIC component technology On chip sub systems are configured by a Function Image data file that is uploaded during device initialisation and defines the device s function and feature set The Function Image can be loaded automatically from a host uC over the C BUS serial interface or from an external memory device The device s functions and features can be enhanced by subsequent Function Image releases facilitating in the field upgrades The CMX7164 operates from a 3 3V supply and includes selectable powersaving modes It is available in 64 VQFN and 64 LQFP packages Note that text shown in pale grey indicates features that will be supported in future versions of the device This Data Sheet is the first part of a two part document 2012 CML Microsystems Plc Page 3 D 7164 FI 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 CONTENTS Section Page US Brief D ecrptgoft seriernes knne ranae eK e E AVAE NE EA 2 1 1 else 9 2 Block DiaQraim ries ccsccicecccctet ceectecesecentctzesnctcevceacecececacecesesundeeedduacten cuvadetedepetteedsevaderedevaueredevedees 11 SIQMali MES GE 13 3 PCB Layout Guidelines and Power Supply Decoupling eene 16 4 Ext
134. stable At power supply switch on the default state is for all blocks except the XTAL and C BUS interface to be in placed in powersave mode Small signal impedance at AVpp 3 3V and Taye 25 C Figures relate to attenuator block only Design Value Overall attenuation input to output has a design tolerance of OdB 1 0dB For each output pin With respect to the output driving a 20kQ load to AVpp 2 The levels of UO Output Fine Gain and Offset registers 5D and 5E should be adjusted so that the output voltage remains between 20 and 80 of AVpp on each output pin when OdB of coarse output gain is used This will produce the best performance when the device operates with AVpp 3 3V 2012 CML Microsystems Plc Page 105 D 7164 FI 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 AC Parameters cont Notes Min Typ Max Unit Auxiliary Signal Inputs AuxADC1 4 Source Output Impedance 50 24 kO Auxiliary 10 Bit ADCs Resolution 10 Bits Conversion Time 51 225 us Sample Rate 1 512 Hz Input Impedance Resistance TBD MQ Capacitance 5 pF Offset Error 54 55 18 mV Integral Non linearity 54 55 2 LSBs Differential Non linearity 52 54 1 LSBs Auxiliary 10 Bit DACs Resolution 10 Bits Conversion Time 51 60 US Settling Time to 0 5 LSB 10 US Offset Error 54 55 20 mV Resistive Load 5 E kQ Integral Non linearity 54 55 4 LSBs Differential Non linearity 52 54 1 LSBs
135. t o First byte Second byte oof Last byte Data value unimportant Either logic level valid but must not change from low to high Figure 12 C BUS Data Streaming Operation 1 For Command byte transfers only the first 8 bits are transferred 01 Reset 2 For single byte data transfers only the first 8 bits of the data are transferred 3 The CDATA and RDATA lines are never active at the same time The address byte determines the data direction for each C BUS transfer 4 The SCLK can be high or low at the start and end of each C BUS transaction 5 The gaps shown between each byte on the CDATA and RDATA lines in the above diagram are optional the host may insert gaps or concatenate the data as required 2012 CML Microsystems Plc Page 24 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 6 3 Function Image Loading The Function Image FI which defines the operational capabilities of the device may be obtained from the CML Technical Portal following registration and authorisation This is in the form of a C header file which can be included into the host controller software or programmed into an external serial memory The Function Image H size can never exceed 128 kbytes although a typical FI will be considerably less than this Note that the BOOTEN1 2 pins are only read at power on when the RESETN pin goe
136. the RF FM signal generator Some typical results are shown in the following figures The desired deviation was achieved by adjusting the deviation control in the RF signal generator 2012 CML Microsystems Plc Page 61 D 7164 FI 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 Marker 1 T1 RBW 200 Hz RF Att 20 dB Ref Lvl 22 95 dBm VBW 1 kHz Mixer 20 diBm O dBm 448 00095892 MHz SWT 4 2 S Unit diam odulation Spectrum N 300 113 Adjacent Channel easurement for 12 5kHz annel 50 Integration window 8kHz Peak deviation 1 symbol P OkHz Center 448 MHz 3 3 kHz Span 33 kHz cr 448 MHz Meas Signal Ref Lvl SR 8 kHz Eye I D dBm Demod 2FSK Eye Diagram BURST NOT 0 SYMBOLS 4 Figure 46 Tx Modulation Spectra GMSK 8kbps BT 0 3 Two point Modulation 2012 CML Microsystems Plc Page 62 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 7 5 7164FI 1 x Typical Receive Performance The performance of the receiver will be different for any combination of bit rate and deviation To aid the designer some typical performance data has been measured using a realistic UO receiver 7 5 4 Signal to Noise and Co channel Performance The performance of the 7164Fl 1 x when receiving is illustrated by the graphs shown in Figure 47 Fi
137. tion Figure 25 Constellation Diagram no frequency or Diagram phase error Diagram frequency error phase error As shown in the third plot if there is any frequency error between transmitting and receiving CMX7164 devices then the diagram will spin and be difficult to interpret Therefore other diagnostic modes are provided as described below Any of the GPIO signals can be configured to produce a pulse train at the nominal symbol rate of the receiving CMX7164 to aid triggering whilst viewing the constellation diagram I Output or Q Output alone vs time or other diagnostic modes in receive In some cases it is advisable to obtain a trigger pulse that is synchronised to the transmitting modem symbol rate for example if the transmitted signal comes from a signal generator Rx Eye 7164Fl 1 x and Fl 2 x only A test mode to examine the Rx eye diagram is provided this utilises the IOUTPUTP N and pins to produce a diagnostic signal showing an eye diagram The eye diagram is produced by channel filtering the UO input signals FM demodulating the result and applying a pulse shaping filter This produces a one dimensional eye diagram which may be displayed on an oscilloscope One of the CMX7164 GPIO pins may be used as a trigger locked to the symbol rate in order to display an eye diagram Note that best results are often obtained with an analogue oscilloscope Figu
138. tted automatically and then data from the Command FIFO is transmitted directly until a TxEnd command is processed or the mode is changed to Rx or Idle Data may be written to the Command FIFO prior to starting transmission enabling the host to create a buffer of data and therefore avoiding risk of the data running out during transmission Further buffering is provided to expand the amount of data that may be absorbed by the CMX7164 The host should write the initial data to the Command FIFO and then set modem control to the required transmit type with the Mode bits as Tx As soon as the data has been read from the C BUS TxData registers the Cmd Done IRQ and or Command FIFO IRQ will be asserted when configured correctly More data should be loaded into the Command FIFO at this stage before data buffered in the CMX7164 runs out otherwise an under run will occur To end the burst the host should send a TxEnd command signalling to the CMX7164 that the burst is to end and the imminent data under run is intentional It is possible to define a transmission sequence with defined RAMDAC ramp up down and GPIO on off events The transmission sequence is configured using Program Block 5 For precise control of the instant that transmission starts it is possible to trigger a transmission using GPIOA as an input Selecting a Tx mode with GPIOA configured as an automatic input places the device into a Tx pending state where it is neither receiving no
139. tween transactions 1 0 US txt Inter byte time 100 ns tek SCLK cycle time 100 ns Lou SCLK high time 50 ns teL SCLK low time 50 ns teps CDATA set up time 75 ns tcbH CDATA hold time 25 ns taps RDATA set up time 50 ns Innu RDATA hold time 0 ns Notes 1 Depending on the command 1 or 2 bytes of CDATA are transmitted to the peripheral MSB Bit 7 first LSB Bit 0 last RDATA is read from the peripheral MSB Bit 7 first LSB Bit 0 last Data is clocked into the peripheral on the rising SCLK edge Commands are acted upon between the last rising edge of SCLK of each command and the rising edge of the CSN signal To allow for differing uC serial interface formats C BUS compatible ICs are able to work with SCLK pulses starting and ending at either polarity Maximum 30pF load on IRQN pin and each C BUS interface line These timings are for the latest version of C BUS and allow faster transfers than the original C BUS timing specification The CMX7164 can be used in conjunction with devices that comply with the slower timings subject to system throughput constraints 2012 CML Microsystems Plc Page 113 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 10 3 Packaging Index Area 1 f A ese DIM MIN TYP MAX A 9 00 BSC 7 N B 9 00 BSC J P C 0 0 0 90 1 00 7 A F 7 00 7 80 B H G 7 00
140. uration the CMX7164 powered or Reset and then data can then be sent directly over the C BUS to the CMX7164 If the host detects a brownout the BOOTEN1 2 pins should be set to re load the Fl A General Reset should then be issued or the RESETN pin used to reset the CMX7164 and the appropriate FI load procedure followed Streaming C BUS may be used to load the Modem Command FIFO Word 49 write register with the Function Image and the Modem Command FIFO Level 4B read register used to ensure that the FIFO is not allowed to overflow during the load process The download time is limited by the clock frequency of the C BUS with a 5MHz SCLK it should take less than 250ms to complete even when loading the largest possible Function Image 2012 CML Microsystems Plc Page 25 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 BOOTEN2 1 BOOTEN1 1 Power up or write General Reset to CMX7164 Y Read the RxFIFO Level 4F until 3 device check words appear in RXFIFO Word 4D Read and discard them bd Block number N 71 4 BOOTEN and BOOTEN2 may be changed once it is clear that the CMX7164 has comitted to C BUS boot i e when a word has been read from the C BUS command FIFO Y Write Block 1 Length DBN len to CmdFIFO Word 49 Y Write Start Block N Address DBN ptr to CmdFIFO Word 49 p Y Check Cmd
141. ure 61 compares the performance of a 12 5kHz channel system with and without the sinc filtering included It can be seen that the sinc filter degrades the sensitivity by less than 0 5dB 2012 CML Microsystems Plc Page 77 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 1 00E 01 Pulse shaping RRC Only Pulse shaping RRC Sinc 1 00E 02 1 00E 03 BER 1 00E 04 1 00E 05 1 00E 06 10 0 11 0 12 0 13 0 14 0 15 0 16 0 17 0 Signal to Noise Ratio dB Figure 61 12 5kHz Channel Sensitivity With and Without Sinc Filter Comparison Data transfer may have channel coding applied to it when 4FSK modulation is selected The graph in Figure 62 shows the improvement due to channel coding in the 12 5kHz channel case 4 8ksymbols s with an RRC only pulse shaping filter 2012 CML Microsystems Plc Page 78 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 1 00E 02 4FSK Raw 4FSK Block Type 2 1 00E 03 i 1 00E 04 1 00E 05 1 00E 06 9 0 10 0 11 0 12 0 13 0 14 0 15 0 16 0 17 0 18 0 Signal to Noise Ratio dB Figure 62 Sensitivity 12 5kHz Channel 4 8ksymbols s With and Without Coding The co channel rejection ratio Figure 63 is measured with an interferer modulated with 400Hz FM and having a deviation of 1 5kHz which is 12 of the nominal 12 5kHz channel bandwidth This particular
142. user control and for control during latching in of UO dc corrections o Full Auto Gain can increase and decrease during the search for frame sync and during burst reception 2012 CML Microsystems Plc Page 48 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 o AGC lock on FS Gain can increase and decrease during the search for frame sync but once a frame sync is detected its level will be fixed o AGC down after FS Gain can increase and decrease during the search for frame sync but once a frame sync is detected its level will only decrease AGC changes during the frame sync can cause the frame sync to be corrupted and therefore not detected by the CMX7164 To avoid this problem the CMX7164 compares the incoming on channel signal to a Signal Detect Threshold the resulting AGC behaviour is as shown in Figure 36 Clip threshold High threshold No backoff even if signal gt high threshold Detect threshold SR Frame sync Data Payload ace c Normal AGC operation reacts to Ke Timer expires Either small signals by framesync detected So increasing gain AGC behaves based on clipping and large Timer starts to count S T Full Auto Lock on FS or signals result in down when detect If timer gt allow high time AGC Down After FS decreasing
143. vice is put in receive searching for a frame sync If frame sync is found during this period then it is indicated to the host via the status bits and normal reception resumes No carrier sense happens until GPIOA is used to start the transmit process at which point carrier sense begins and operation is as described above Note The Command FIFO and Command Buffer will automatically be flushed when a carrier sense attempt to transmit results in the CMX7164 reverting to receive mode This is to avoid accidentally processing transmit commands pre loaded by the host as receive commands This is the only situation in which the FIFOs or buffers will be flushed other than by direct host instruction 2012 CML Microsystems Plc Page 35 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 TET note his assumes that a carrier sense threshold and period Carrier sense process have been defined using the programming register GC NEM EDT Clear Command FIFO Set Modem Control toTxPreamble Frame sync and required data type Rx Frame sync and required data type Mode Carrier Sense Here the device is in d receive and searching Tx triggered on Yes for a frame sync as GPIO e A well as waiting for a GPIO trigger to start Wait for Tx Trigger note the transmission attempt GPIO Tx Trigger No
144. when loaded with FI 1 x 2 x 4 x only Current consumption may vary with other valid Function Images DC Parameters Notes Min Typ Max Unit Supply Current see also section 10 1 5 11 All Powersaved Alpp Dipp 10 15 1 0 UA Idle Mode 12 15 Dipp 13 550 UA Alpp 17 UA Additional Current for One Auxiliary 15 System Clock output running at 5MHz SYSCLKPLL active Diop DVpp 3 3V DVcore 1 8V 900 UA Additional Current for one Auxiliary 15 System Clock output running at 4 8MHz SYSCLKPLL not required Dlpp DVpp 3 3V DV GORE 1 8V 675 UA Additional Current for Each Auxiliary ADC 15 Dlpp DVpp 3 3V DVconE 1 8V ka 190 UA Additional Current for Each Auxiliary DAC 14 15 Alpp AVpp 3 3V 210 to 370 UA Notes 10 Idle mode with Vgias disabled 11 Tame 25 C not including any current drawn from the device pins by external circuitry 12 System Clocks Auxiliary circuits disabled but all other digital circuits including the Main Clock PLL enabled and Vpjas enabled 13 Using a 19 2MHz external clock input Xtal oscillator circuit powered down 14 A lower current is measured when outputting the smallest possible dc level from an AuxDAC a higher current is measured when outputting the largest possible dc value 15 Using a 19 2MHz external clock input 2012 CML Microsystems Plc Page 102 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 DC Parameters continued
145. wn in Figure 58 the 7164F1 2 x internal PRBS generator was used to modulate the RF FM signal generator Some typical results are shown in the following figures The desired deviation was achieved by adjusting the deviation control in the RF signal generator 2012 CML Microsystems Plc Page 74 D 7164 FI 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 Marker 1 T1 RBW 500 Hz RF Att 30 dB Ref Lvl 40 77 dBm VBW 5 kHz 0 dBm 450 00837836 MHz SWT 139 8 Unit dBm Modulation Spectrum EN 300 113 Adjacent Channel 20 measurement for 25kHz channel 20 ACP 75dB M mae Integration window 16kHz 50 UU Peak deviation 3 symbol li LI ES II 199 16999 HS Aula 1 1i Mike Center 450 MHz 6 7 kHz Span 67 kHz CF 450 MHz Meas Signal Ref Lvl SR 9 6 kHz Eye I 0 dBm Demod 4FSK 75m REAL Tl TS2 ITS1 75m 0 SYMBOLS 4 Eye Diagram Figure 59 Tx Modulation Spectra 4FSK 19 2kbps Two point Modulation 2012 CML Microsystems Plc Page 75 D 7164_Fl 1 x Fl 2 x Fl 4 x 9 CMX7164 Multi Mode Modem CMX7164 8 5 7164Fl 2 x Typical Receive Performance The performance of the receiver will be different for any combination of bit rate and deviation To aid the designer some typical performance data has been measured using a realistic UO rec

CMX7164 Multi Mode Modem

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