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MPC860 Family Hardware Specifications

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1. All Frequencies Num Characteristic Unit Min Max P61 DSCK cycle time 3 x TOLOCKOUT P62 DSCK clock pulse width 1 25 x TCLOCKOUT P63 DSCK rise and fall times 0 00 3 00 ns P64 DSDI input data setup time 8 00 ns P65 DSDI data hold time 5 00 ns P66 DSCK low to DSDO data valid 0 00 15 00 ns P67 DSCK low to DSDO invalid 0 00 2 00 ns Figure 29 provides the input timing for the debug port clock Figure 30 provides the timing for the debug port DSCK DSDO Figure 29 Debug Port Clock Input Timing DSCK DSDI Figure 30 Debug Port Timings MPC860 Family Hardware Specifications Rev 7 38 Freescale Semiconductor Table 12 shows the reset timing for the MPC860 Table 12 Reset Timing Bus Signal Timing 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max R69 CLKOUT to HRESET high 20 00 20 00 20 00 20 00 ns impedance R70 CLKOUT to SRESET high 20 00 20 00 20 00 20 00 ns impedance R71 RSTCONMF pulse width 515 1 425 0 340 0 2575 ns 5 0 0 8 R72 R73 Configuration data to HRESET rising 504 5 425 0 350 0 277 2 ns edge setup time 5 0 0 7 R74 Configuration data to RSTCONF 350 0 350 0 350 0 3
2. TDO Figure 35 JTAG Test Access Port Timing Diagram TCK f TRST Figure 36 JTAG TRST Timing Diagram TCK Output Signals Output Signals Output Signals Figure 37 Boundary Scan JTAG Timing Diagram MPC860 Family Hardware Specifications Rev 7 42 Freescale Semiconductor 11 CPM Electrical Characteristics This section provides the AC and DC electrical specifications for the communications processor module CPM of the MPC860 11 1 PIP PIO AC Electrical Specifications Table 14 provides the PIP PIO AC timings as shown in Figure 38 through Figure 42 Table 14 PIP PIO Timing CPM Electrical Characteristics All Frequencies Num Characteristic Unit Min Max 21 Data in setup time to STBI low 0 ns 22 Data in hold time to STBI high 25 13 CLK 23 STBI pulse width 1 5 CLK 24 STBO pulse width 1CLK 5 ns ns 25 Data out setup time to STBO low 2 CLK 26 Data out hold time from STBO high 5 CLK 27 STBllow to STBO low Rx interlock E 2 CLK 28 STBI low to STBO high Tx interlock 2 CLK 29 Data in setup time to clock high 15 ns 30 Data in hold time from clock high 7 5 ns 31 Clock low to data out valid CPU writes data control or direction 25 ns t3 Specification 23 DATA IN STBO Figure 38 PIP Rx Interlock Mode Timing Diagram MPC860 Family Hardware Specificati
3. RENA CD1 Input Figure 59 Ethernet Receive Timing Diagram MPC860 Family Hardware Specifications Rev 7 Freescale Semiconductor 59 CPM Electrical Characteristics TCLK1 TxD1 Output TENA RTS1 Input RENA CD1 Input NOTE 2 NOTES 1 Transmit clock invert TCI bit in GSMR is set 2 If RENA is deasserted before TENA or RENA is not asserted at all during transmit then the CSL bit is set in the buffer descriptor at the end of the frame transmission Figure 60 Ethernet Transmit Timing Diagram tatii A Vip ef AN VF UE RxD1 rou ___ cue EL a Start Frame De __ _ gt fse RSTRT Output Figure 61 CAM Interface Receive Start Timing Diagram REJECT 437 Figure 62 CAM Interface REJECT Timing Diagram MPC860 Family Hardware Specifications Rev 7 60 Freescale Semiconductor CPM Electrical Characteristics 11 9 SMC Transparent AC Electrical Specifications Table 23 provides the SMC transparent timings as shown in Figure 63 Table 23 SMC Transparent Timing All Frequencies Num Characteristic Unit Min Max 150 SMCLK clock period 100 ns 151 SMCLK width low 50 ns 151A SMCLK width high 50 ns 152 SMCLK rise fall time os 15 ns 153 SMTXD active delay from SMCLK falling edge 10 50 ns 154 SMRXD SMSYNC setup time 20 ns 155 RXD1 SMSYNC hold time 5 ns 1 SYNCC
4. o O O O o S O alO 9 9 z S is O A O O O BO O JO T fos oa z y z fse N gt z m ve 66 6 6 lo O O e e g z 3 30 gO Fe 3 3 Jo 8 303 403 Q Z D e Zz D o e e 6 lo O Va A lt iw s z a lt S 9 I 5 O gO p O alO 3 O w w E 3 n 4 O O O wo w w O w wo O O O e e e e e e e eo e e O 0 O BO O OO 0 O O O ORD O BBO O O O O O O O ORD O Bao o EMO O Os ome CN e e O O o O O O zZ O zZ fo o gt o gt N a gt W n gt O Q U 2 gt oO zZ O O n D O Ye N Q vu 2 gt a Q O O O SIO O O O O O N gt io S gt io R gt N 4 a N w m o O U pu Z O vU gt t O n NI O n e O O O O e O O O e O A8 O A9 O O O O O O O lo O O O O O w N gt Le gt N 3 gt N N a N O w a gt amp z O D v mi N OQ v 2 gt fo O oa O m gt Ww ZO 2 O O e 30O a ie N gt amp S gt o wb rd lt ZO O O O O N uN m w tj a Q RK O m N gt a o D a wo Figure 75 Pinout of the PBGA Package 14 2 Mechanical Dimensions of the PBGA Package F
5. All Frequencies Num Characteristic Unit Min Max 120 CLSN width high 40 ns 121 RCLK1 rise fall time 15 ns 122 RCLK1 width low 40 ns 123 RCLK1 clock period 80 120 ns 124 RXD1 setup time 20 ns 125 RXD1 hold time 5 ns 126 RENA active delay from RCLK1 rising edge of the last data bit 10 ns 127 RENA width low 100 ns 128 TCLK1 rise fall time 15 ns 129 TCLK1 width low 40 ns 130 TCLK1 clock period 99 101 ns 131 TXD1 active delay from TCLK1 rising edge 10 50 ns 132 TXD1 inactive delay from TCLK1 rising edge 10 50 ns 133 TENA active delay from TCLK1 rising edge 10 50 ns MPC860 Family Hardware Specifications Rev 7 58 Freescale Semiconductor CPM Electrical Characteristics Table 22 Ethernet Timing continued All Frequencies Num Characteristic Unit Min Max 134 TENA inactive delay from TCLK1 rising edge 10 50 ns 135 RSTRT active delay from TCLK1 falling edge 10 50 ns 136 RSTRT inactive delay from TCLK1 falling edge 10 50 ns 137 REJECT width low 1 CLK 138 CLKO1 low to SDACK asserted 20 ns 139 CLKO1 low to SDACK negated 20 ns a The ratios SYNCCLK RCLK1 and SYNCCLK TCLK1 must be greater than or equal to 2 1 2 SDACK is asserted whenever the SDMA writes the incoming frame DA into memory CLSN CTS1 Input la Figure 58 Ethernet Collision Timing Diagram
6. B31 CLKOUT falling edge to CS valid as requested by control bit CST4 in the corresponding word in UPM 1 50 6 00 1 50 6 00 ns B31a CLKOUT falling edge to CS valid as requested by control bit CST1 in the corresponding word in UPM 7 58 14 33 6 25 13 00 11 75 3 80 10 54 ns B31b CLKOUT rising edge to CS valid as requested by control bit CST2 in the corresponding word in UPM 1 50 1 50 8 00 1 50 8 00 ns B31c CLKOUT rising edge to CS valid as requested by control bit CST3 in the corresponding word in UPM 7 58 14 33 6 25 13 00 11 75 3 80 10 04 ns MPC860 Family Hardware Specifications Rev 7 Freescale Semiconductor 17 Bus Signal Timing Table 7 Bus Operation Timings continued 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max B31d CLKOUT falling edge to CS 13 26 17 99 11 28 16 00 9 40 14 13 7 58 12 31 ns valid as requested by control bit CST1 in the corresponding word in UPM EBDF 1 B32 CLKOUT falling edge to BS 1 50 6 00 1 50 6 00 1 50 6 00 1 50 6 00 ns valid as requested by control bit BST4 in the corresponding word in UPM B32a CLKOUT falling edge to BS 7 58 14 33 6 25 13 00 5 00 11 75 3 80 10 54 ns valid as requested by control bit BST1 in the corresponding word in
7. 3 00 3 00 3 00 Bih Frequency jitter on EXTCLK 0 50 0 50 0 50 0 50 B2 CLKOUT pulse width low 12 12 10 00 8 00 6 06 ns B3 CLKOUT width high 12 12 10 00 8 00 6 06 ns B4 CLKOUT rise time 4 00 4 00 4 00 4 00 ns B533 CLKOUT fall time 400 4 00 400 4 00 ns B7 CLKOUT to A 0 31 BADDR 28 30 7 58 6 25 5 00 3 80 ns RD WR BURST D 0 31 DP 0 3 invalid MPC860 Family Hardware Specifications Rev 7 12 Freescale Semiconductor Table 7 Bus Operation Timings continued Bus Signal Timing 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max B7a CLKOUT to TSIZ 0 1 REG RSV 758 625 500 380 ns AT 0 3 BDIP PTR invalid B7b CLKOUT to BR BG FRZ 758 625 500 380 ns VFLS 0 1 VF 0 2 IWP 0 2 LWP 0 1 STS invalid 4 B8 CLKOUT to A 0 31 BADDR 28 30 7 58 14 33 6 25 13 00 5 00 11 75 3 80 10 04 ns RD WR BURST D 0 31 DP 0 3 valid B8a CLKOUT to TSIZ 0 1 REG RSV 7 58 14 33 6 25 13 00 5 00 11 75 3 80 10 04 ns AT 0 3 BDIP PTR valid B8b CLKOUT to BR BG VFLS 0 1 7 58 14 33 6 25 13 00 5 00 11 75 3 8
8. CPM Electrical Characteristics indul HD nano Du indjno U P ISI1 indu axy ndino ax yndu ONASULI ndu y8 4 Figure 54 IDL Timing MPC860 Family Hardware Specifications Rev 7 55 Freescale Semiconductor CPM Electrical Characteristics 11 7 SCC in NMSI Mode Electrical Specifications Table 20 provides the NMSI external clock timing Table 20 NMSI External Clock Timing All Frequencies Num Characteristic Unit Min Max 100 RCLK1 and TCLK1 width high 1 SYNCCLK ns 101 RCLK1 and TCLK1 width low 1 SYNCCLK 5 ns 102 RCLK1 and TCLK1 rise fall time 15 00 ns 103 TXD1 active delay from TCLK1 falling edge 0 00 50 00 ns 104 RTS1 active inactive delay from TCLK1 falling edge 0 00 50 00 ns 105 CTS1 setup time to TCLK1 rising edge 5 00 ns 106 RXD1 setup time to RCLK1 rising edge 5 00 ns 107 RXD1 hold time from RCLK1 rising edge 5 00 ns 108 CD1 setup Time to RCLK1 rising edge 5 00 ns 1 The ratios SYNCCLK RCLK1 and SYNCCLK TCLK1 must be greater than or equal to 2 25 1 2 Also applies to CD and CTS hold time when they are used as external sync signals Table 21 provides the NMSI internal clock timing Table 21 NMSI Internal Clock Timing All Frequencies Num Characteristic Unit Min Max 100 RCLK1 and TCLK1 frequency 0 00 SYNCCLK 3 MHz 102 R
9. 2 00 8 00 2 00 8 00 2 00 8 00 2 00 8 00 ns GPCM read access GPCM write access ACS 00 TRLX 0 and CSNT 0 B24 A 0 31 and BADDR 28 30 to CS 558 425 300 1 79 ns asserted GPCM ACS 10 TRLX 0 B24a A 0 31 and BADDR 28 30 toCS 13 15 10 50 800 558 ns asserted GPCM ACS 11 TRLX 0 B25 CLKOUT rising edge to OE WE 0 3 9 00 9 00 9 00 9 00 ns asserted B26 CLKOUT rising edge to OE negated 2 00 9 00 2 00 9 00 2 00 9 00 2 00 9 00 ns B27 A 0 31 and BADDR 28 30 to CS 35 88 29 25 23 00 1694 ns asserted GPCM ACS 10 TRLX 1 B27a A 0 31 and BADDR 28 30 to CS 43 45 35 50 28 00 20 73 ns asserted GPCM ACS 11 TRLX 1 B28 CLKOUT rising edge to WE 0 3 9 00 9 00 9 00 9 00 ns negated GPCM write access CSNT 0 B28a CLKOUT falling edge to WE 0 3 7 58 14 33 6 25 13 00 5 00 11 75 3 80 10 54 ns negated GPCM write access TRLX 0 1 CSNT 1 EBDF 0 MPC860 Family Hardware Specifications Rev 7 14 Freescale Semiconductor Table 7 Bus Operation Timings continued Bus Signal Timing 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic U
10. Figure 19 Synchronous External Master Access Timing GPCM Handled ACS 00 Figure 20 provides the timing for the asynchronous external master memory access controlled by the GPCM CLKOUT a SI ee O a a 3 AS A 0 31 6 TSIZI0 1 RW CSx Figure 20 Asynchronous External Master Memory Access Timing GPCM Controlled ACS 00 Figure 21 provides the timing for the asynchronous external master control signals negation AS 643 CSx WE 0 3 SS OE GPLx BS 0 3 Figure 21 Asynchronous External Master Control Signals Negation Timing MPC860 Family Hardware Specifications Rev 7 32 Freescale Semiconductor Bus Signal Timing Table 8 provides interrupt timing for the MPC860 Table 8 Interrupt Timing All Frequencies Num Characteristic Unit Min Max 139 IRQx valid to CLKOUT rising edge setup time 6 00 ns 140 IRQx hold time after CLKOUT 2 00 ns 141 IRQX pulse width low 3 00 ns 142 IRQX pulse width high 3 00 ns 143 IRQx edge to edge time 4 x TCLOCKOUT 1 The timings 139 and 140 describe the testing conditions under which the IRQ lines are tested when being defined as level sensitive The IRQ lines are synchronized internally and do not have to be asserted or negated with reference to the CLKOUT The timings 141 142 and 143 are specified to allow the correct function of the IRQ lines detection circuitry and have no direct relation
11. SCL clock frequency master 1 5 100 kHz 202 Bus free time between transmissions 4 7 us 203 Low period of SCL 4 7 us 204 High period of SCL 4 0 us 205 Start condition setup time 4 7 us 206 Start condition hold time 4 0 us 207 Data hold time 0 us 208 Data setup time 250 ns 209 SDL SCL rise time 1 us MPC860 Family Hardware Specifications Rev 7 Freescale Semiconductor 65 CPM Electrical Characteristics Table 26 I2C Timing SCL lt 100 kHz continued All Frequencies Num Characteristic Unit Min Max 210 SDL SCL fall time 300 ns 211 Stop condition setup time 4 7 us 1 SCL frequency is given by SCL BRGCLK_frequency BRG register 3 x pre_scaler x 2 The ratio SYNCCLK BRGCLK pre_scaler must be greater than or equal to 4 1 Table 27 provides the PC SCL gt 100 kHz timings Table 27 I2C Timing SCL gt 100 kHz All Frequencies Num Characteristic Expression Unit Min Max 200 SCL clock frequency slave fSCL 0 BRGCLK 48 Hz 200 SCL clock frequency master fSCL BRGCLK 16512 BRGCLK 48 Hz 202 Bus free time between transmissions 1 2 2 fSCL s 203 Low period of SCL 1 2 2 fSCL s 204 High period of SCL 1 2 2 fSCL s 205 Start condition setup time 1 2 2 fSCL s 206 Start condition hold time 1 2 2 fSCL s 207 Data hold time 0
12. 2 3 CS 2 3 UPWAITA GPL_A4 UPWAITB GPL_B4 GPL_A5 ALE_A CE1_A CE2_A ALE_B DSCK AT1 OP 0 1 OP2 MODCK1 STS OP3 MODCK2 DSDO BADDR 28 30 ES 7 Thermal Calculation and Measurement For the following discussions Pp Vpp X Ipp PI O where PI O is the power dissipation of the I O drivers 7 1 Estimation with Junction to Ambient Thermal Resistance An estimation of the chip junction temperature Ty in C can be obtained from the equation Ty TA Roya X Pp where TA ambient temperature C Reza package junction to ambient thermal resistance C W Pp power dissipation in package The junction to ambient thermal resistance is an industry standard value which provides a quick and easy estimation of thermal performance However the answer is only an estimate test cases have demonstrated that errors of a factor of two in the quantity T TA are possible 7 2 Estimation with Junction to Case Thermal Resistance Historically the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance Rosa Rosc Roca where Resa junction to ambient thermal resistance C W Rgyc junction to case thermal resistance C W Reca case to ambient thermal resistance C W Rgjc is device related and cannot be influenced by the user The user adjusts the the
13. 50 BRGO rise and fall time 10 ns 51 BRGO duty cycle 40 60 52 BRGOcycle 40 ns BRGOX Figure 48 Baud Rate Generator Timing Diagram MPC860 Family Hardware Specifications Rev 7 48 Freescale Semiconductor CPM Electrical Characteristics 11 5 Timer AC Electrical Specifications Table 18 provides the general purpose timer timings as shown in Figure 49 Table 18 Timer Timing All Frequencies Num Characteristic Unit Min Max 61 TIN TGATE rise and fall time 10 ns 62 TIN TGATE low time 1 CLK 63 TIN TGATE high time 2 CLK 64 TIN TGATE cycle time 3 CLK 65 CLKO low to TOUT valid 3 25 ns CLKO TIN TGATE Input TOUT Output Figure 49 CPM General Purpose Timers Timing Diagram 11 6 Serial Interface AC Electrical Specifications Table 19 provides the serial interface timings as shown in Figure 50 through Figure 54 Table 19 SI Timing All Frequencies Num Characteristic Unit Min Max 70 L1RCLK L1TCLK frequency DSC 0 2 SYNCCLK 2 5 MHz 71 L1RCLK L1TCLK width low DSC 0 2 P 10 ns 71a L1RCLK LITCLK width high DSC 0 3 P 10 ns 72 L1TXD L1ST 1 4 L1RQ L1CLKO rise fall time 15 00 ns 73 LIRSYNC L1TSYNC valid to L1CLK edge SYNC setup time 20 00 ns 74 L1CLK edge to L1RSYNC L1TSYNC invalid SYNC hold time 35 00 ns
14. 7 Freescale Semiconductor DC Characteristics 6 DC Characteristics Table 6 provides the DC electrical characteristics for the MPC860 Table 6 DC Electrical Specifications Characteristic Symbol Min Max Unit Operating voltage at 40 MHz or less Vppuy Yoo VDDSYN 3 0 3 6 V KAPWR 2 0 3 6 V power down mode KAPWR VppH 0 4 VDDH V all other operating modes Operating voltage greater than 40 MHz Vpor Voi KAPWR 3 135 3 465 V VDDSYN KAPWR 2 0 3 6 V power down mode KAPWR VppH 0 4 VDDH V all other operating modes Input high voltage all inputs except EXTAL and Vin 2 0 5 5 V EXTCLK Input low voltage Vit GND 0 8 EXTAL EXTCLK input high voltage Vine 0 7 x VppH VDDH 0 3 Input leakage current Vin 5 5 V except TMS lin 100 uA TRST DSCK and DSDI pins Input leakage current Vin 3 6 V except TMS lin 10 uA TRST DSCK and DSDI pins Input leakage current Vin 0 V except TMS lin E 10 HA TRST DSCK and DSDI pins Input capacitance Cin 20 pF Output high voltage lop 2 0 MA Vpou 3 0 V Vou 2 4 V except XTAL XFC and open drain pins Output low voltage VoL 0 5 V IOL 2 0 mA CLKOUT IOL 3 2 mA 3 IOL 5 3 mA 4 IOL 7 0 mA TXD1 PA14 TXD2 PA12 IOL 8 9 mA TS TA TEA BI BB HRESET SRESET 1 2 Input capacitance is periodically sampled Vi max for the I C interface is 0 8 V rather than t
15. EBDF 0 B29f WE 0 3 negated to D 0 31 DP 0 3 8 86 6 88 5 00 3 18 ns High Z GPCM write access TRLX 0 CSNT 1 EBDF 1 B29g CS negated to D 0 31 DP 0 3 8 86 6 88 5 00 3 18 ns High Z GPCM write access TRLX 0 CSNT 1 ACS 10 or ACS 11 EBDF 1 B29h WE 0 3 negated to D 0 31 DP 0 3 38 67 31 38 2450 17 83 ns High Z GPCM write access TRLX 1 CSNT 1 EBDF 1 MPC860 Family Hardware Specifications Rev 7 Freescale Semiconductor 15 Table 7 Bus Operation Timings continued Haw to Re dhi Ms 1 Home Page ACS 11 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max B29i CS negated to D 0 31 DP 0 3 38 67 31 38 24 50 17 83 ns High Z GPCM write access CSNT 1 ACS 10 or EBDF 1 www freescale com email support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 800 521 6274 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale
16. MPC860 Family Hardware Specifications Rev 7 50 Freescale Semiconductor CPM Electrical Characteristics L1RCLK FE 0 CE 0 Input L1RCLK FE 1 CE 1 Input L1RSYNC Input L1RXD Input L1ST 4 1 Output Figure 50 SI Receive Timing Diagram with Normal Clocking DSC 0 MPC860 Family Hardware Specifications Rev 7 Freescale Semiconductor 51 CPM Electrical Characteristics L1RCLK FE 1 CE 1 Input L1RCLK FE 0 CE 0 Input BO L1RSYNC Input lt tipu KXXXX P pae L1ST 4 1 Output he L1CLKO Output Figure 51 SI Receive Timing with Double Speed Clocking DSC 1 MPC860 Family Hardware Specifications Rev 7 52 Freescale Semiconductor CPM Electrical Characteristics L1TCLK FE 0 CE 0 Input y LITCLK Input LITSYNC Input L1TXD Output L1ST 4 1 Output Figure 52 SI Transmit Timing Diagram DSC 0 MPC860 Family Hardware Specifications Rev 7 Freescale Semiconductor 53 CPM Electrical Characteristics L1RCLK FE 0 CE 0 Input S L1RCLK Input ge L1RSYNC Input L1TXD Output L1ST 4 1 Output L1CLKO Output Figure 53 SI Transmit Timing with Double Speed Clocking DSC 1 MPC860 Family Hardware Specifications Rev 7 54 Freescale Semiconductor
17. MPC860 Family Hardware Specifications Rev 7 Freescale Semiconductor 49 CPM Electrical Characteristics Table 19 SI Timing continued All Frequencies Num Characteristic Unit Min Max 75 LIRSYNC LITSYNC rise fall time 15 00 ns 76 L1RXD valid to L1CLK edge L1RXD setup time 17 00 ns 77 L1CLK edge to L1RXD invalid L1RXD hold time 13 00 ns 78 L1CLK edge to L1ST 1 4 valid 4 10 00 45 00 ns 78A L1SYNC valid to L1ST 1 4 valid 10 00 45 00 ns 79 L1CLK edge to L1ST 1 4 invalid 10 00 45 00 ns 80 L1CLK edge to L1TXD valid 10 00 55 00 ns 80A L1TSYNC valid to L1TXD valid 4 10 00 55 00 ns 81 L1CLK edge to L1TXD high impedance 0 00 42 00 ns 82 L1RCLK L1TCLK frequency DSC 1 16 00 or MHz SYNCCLK 2 83 LIRCLK L1TCLK width low DSC 1 P 10 ns 83a L1RCLK L1TCLK width high DSC 1 5 P 10 ns 84 L1CLK edge to L1CLKO valid DSC 1 E 30 00 ns 85 LIRQvalid before falling edge of L1TSYNC 1 00 ae 86 L1GR setup time 42 00 ns 87 L1GR hold time 42 00 ns 88 Maat edge to L1SYNC valid FSD 00 CNT 0000 BYT 0 0 00 ns DSC 0 The ratio SYNCCLK L1RCLK must be greater than 2 5 1 These specs are valid for IDL mode only Where P 1 CLKOUT Thus for a 25 MHz CLKO1 rate P 40 ns These strobes and TxD on the first bit of the frame become valid after LI CLK edge or L1SYNC whichever comes later A U N gt
18. Semiconductor Japan Ltd Technical Information Center 3 20 1 Minami Azabu Minato ku Tokyo 106 0047 Japan 0120 191014 81 3 3440 3569 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 800 441 2447 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com MPC860EC Rev 7 09 2004 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provid
19. UPM EBDF 0 B32b CLKOUT rising edge to BS valid as 1 50 8 00 1 50 8 00 1 50 8 00 1 50 8 00 ns requested by control bit BST2 in the corresponding word in UPM B32c CLKOUT rising edge to BS valid as 7 58 14 33 6 25 13 00 5 00 11 75 3 80 10 54 ns requested by control bit BST3 in the corresponding word in UPM B32d CLKOUT falling edge to BS 13 26 17 99 11 28 16 00 9 40 14 13 7 58 12 31 ns valid as requested by control bit BST1 in the corresponding word in UPM EBDF 1 B33 CLKOUT falling edge to GPL 1 50 6 00 1 50 6 00 1 50 6 00 1 50 6 00 ns valid as requested by control bit GxT4 in the corresponding word in UPM B33a CLKOUT rising edge to GPL 7 58 14 33 6 25 13 00 5 00 11 75 3 80 10 54 ns valid as requested by control bit GxT3 in the corresponding word in UPM B34 A 0 31 BADDR 28 30 and D 0 31 5 58 4 25 3 00 1 79 ns to CS valid as requested by control bit CST4 in the corresponding word in UPM B34a A 0 31 BADDR 28 30 and D 0 31 13 15 10 50 8 00 5 58 ns to CS valid as requested by control bit CST1 in the corresponding word in UPM B34b A 0 31 BADDR 28 30 andD 0 31 20 73 16 75 13 00 9 36 ns to CS valid as requested by control bit CST2 in the corresponding word in UPM MPC860 Famil
20. and tolerance per ASME Y14 5M 1994 3 Maximum Solder Ball Diameter measured parallel to Datum A Figure 77 Mechanical Dimensions and Bottom Surface Nomenclature of the ZQ PBGA Package MPC860 Family Hardware Specifications Rev 7 76 Freescale Semiconductor Document Revision History 15 Document Revision History Table 35 lists significant changes between revisions of this hardware specification Table 35 Document Revision History Revision Date Changes 5 1 11 2001 Revised template format removed references to MAC functionality changed Table 7 B23 max value Q 66 MHz from 2ns to 8ns added this revision history table 10 2002 Added the MPC855T Corrected Figure 25 on page 36 6 1 11 2002 Corrected UTOPIA RXenb and TXenb timing values Changed incorrect usage of Vcc to Vdd Corrected dual port RAM to 8 Kbytes 6 2 8 2003 Changed B28a through B28d and B29d to show that TRLX can be 0 or 1 Changed reference documentation to reflect the Rev 2 MPC860 PowerQUICC Family Users Manual Nontechnical reformatting 6 3 9 2003 Added Section 11 2 on the Port C interrupt pins Nontechnical reformatting 7 0 9 2004 Added a tablefootnote to Table 6 DC Electrical Specifications about meeting the VIL Max of the I2C Standard Replaced the thermal characteristics in Table 4 by the ZQ package Add the new parts to the Ordering and Availablity Chart in Table 34 Added the
21. applied to its inputs 3 Minimum temperatures are guaranteed as ambient temperature TA Maximum temperatures are guaranteed as junction temperature Tj 4 Thermal Characteristics Table 3 Package Description Package Designator Package Code Case No Package Description ZP 5050 1103 01 PBGA 357 25 25 0 9P1 27 ZQ VR 5058 1103D 02 PBGA 357 25 25 1 2P1 27 Table 4 shows the thermal characteristics for the MPC860 MPC860 Family Hardware Specifications Rev 7 Freescale Semiconductor Power Dissipation Table 4 MPC860 Thermal Resistance Data Rating Environment Symbol eae oe Unit Mold Compound Thickness 0 85 1 15 mm Junction to ambient Natural convection Single layer board 1s Roya 34 34 C W Four layer board 2s2p Roma 3 22 22 Airflow 200 ft min Single layer board 1s Rouma 27 27 Four layer board 2s2p Reyma3 18 18 Junction to board 4 Rous 14 13 Junction to case Rosc 6 8 Junction to package top 6 Natural convection Lot 2 2 1 Junction temperature is a function of on chip power dissipation package thermal resistance mounting site board temperature ambient temperature air flow power dissipation of other components on the board and board thermal resistance 2 Per SEMI G38 87 and JEDEC JESD51 2 with the single layer board horizontal Per JEDEC JESD51 6 with the board horizontal 4 Thermal resi
22. bank Glueless interface to DRAM SIMMS SRAM EPROM Flash EPROM and other memory devices DRAM controller programmable to support most size and speed memory interfaces Four CAS lines four WE lines and one OE line Boot chip select available at reset options for 8 16 or 32 bit memory Variable block sizes 32 Kbyte to 256 Mbyte Selectable write protection On chip bus arbitration logic e General purpose timers Four 16 bit timers or two 32 bit timers Gate mode can enable disable counting Interrupt can be masked on reference match and event capture e System integration unit SIU Bus monitor Software watchdog Periodic interrupt timer PIT Low power stop mode Clock synthesizer Decrementer time base and real time clock RTC from the PowerPC architecture Reset controller IEEE 1149 1 test access port JTAG e Interrupts Seven external interrupt request IRQ lines 12 port pins with interrupt capability 23 internal interrupt sources Programmable priority between SCCs Programmable highest priority request e 10 100 Mbps Ethernet support fully compliant with the IEEE 802 3u Standard not available when using ATM over UTOPIA interface e ATM support compliant with ATM forum UNI 4 0 specification Cell processing up to 50 70 Mbps at 50 MHz system clock Cell multiplexing demultiplexing Support of AALS and AALO protocols on a per VC basis AALO support enables OAM and software implementation of other protoc
23. edge of CLKOUT MPC860 Family Hardware Specifications Rev 7 Freescale Semiconductor 19 Bus Signal Timing 3 The timing B30 refers to CS when ACS 00 and to WE 0 3 when CSNT 0 9 The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally The timings specified in B37 and B38 are specified to enable the freeze of the UPM output signals as described in Figure 17 10 The AS signal is considered asynchronous to the CLKOUT The timing B39 is specified in order to allow the behavior specified in Figure 20 Figure 2 is the control timing diagram CLKOUT Outputs Outputs Maximum output delay specification Minimum output hold time Minimum input setup time specification Minimum input hold time specification Inputs A 2 Figure 2 Control Timing Figure 3 provides the timing for the external clock MPC860 Family Hardware Specifications Rev 7 20 Freescale Semiconductor Bus Signal Timing CLKOUT Figure 3 External Clock Timing Figure 4 provides the timing for the synchronous output signals CLKOUT A E O eo o A Output C Signals Output C Signals Output 7 Signals A Figure 4 Synchronous Output Signals Timing MPC860 Family Hardware Specifications Rev 7 Freescale Semiconductor 21 Bus Signal Timing Figure 5 provides the timing for the synchronous active pull up and open drain output sig
24. mechanical spec of the ZQ package in Figure 77 Removed all of the old revisions from Table 5 MPC860 Family Hardware Specifications Rev 7 Freescale Semiconductor 77 Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC860 Family Hardware Specifications Rev 7 78 Freescale Semiconductor Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC860 Family Hardware Specifications Rev 7 Freescale Semiconductor 79 How to Reach Us Home Page www freescale com email support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 800 521 6274 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Technical Information Center 3 20 1 Minami Azabu Minato ku Tokyo 106 0047 Japan 0120 191014 81 3 3440 3569 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only F
25. option e Four serial communications controllers SCCs Ethernet IEEE 802 3 optional on SCC1 4 supporting full 10 Mbps operation available only on specially programmed devices HDLC SDLC all channels supported at 2 Mbps HDLC bus implements an HDLC based local area network LAN Asynchronous HDLC to support point to point protocol PPP AppleTalk Universal asynchronous receiver transmitter UART Synchronous UART Serial infrared IrDA Binary synchronous communication BISYNC Totally transparent bit streams Totally transparent frame based with optional cyclic redundancy check CRC e Two SMCs serial management channels UART Transparent General circuit interface GCI controller Can be connected to the time division multiplexed TDM channels e One SPI serial peripheral interface Supports master and slave modes Supports multimaster operation on the same bus One C inter integrated circuit port Supports master and slave modes MPC860 Family Hardware Specifications Rev 7 4 Freescale Semiconductor Maximum Tolerated Ratings Multiple master environment support e Time slot assigner TSA Allows SCCs and SMCs to run in multiplexed and or non multiplexed operation Supports T1 CEPT PCM highway ISDN basic rate ISDN primary rate user defined 1 or 8 bit resolution Allows independent transmit and receive rout
26. pia anna id taia 2 Maximum Tolerated Ratings 5 Thermal Characteristics 0000 6 Power Dissipation 0 0 0 0 eee ee ee ee 7 IDC Characteristics stoso ta on era seca ack gins totes 8 Thermal Calculation and Measurement 9 lt Layout Practices yuh see tree ac a thew yd dace 11 Bus Signal Timing 000005 12 IEEE 1149 1 Electrical Specifications 41 CPM Electrical Characteristics 43 UTOPIA AC Electrical Specifications 67 FEC Electrical Characteristics 68 Mechanical Data and Ordering Information 71 Document Revision History 77 ey Z freescale semiconductor Features Table 1 MPC860 Family Functionality Cache Kbytes Ethernet Part Instruction oua Cache pe 5 ies ATM SCC _ Reference Cache MPC860DE 4 4 Up to 2 2 1 MPC860DT 4 4 Up to 2 1 Yes 2 1 MPC860DP 16 8 Up to 2 1 Yes 2 1 MPC860EN 4 4 Up to 4 4 1 MPC860SR 4 4 Up to 4 Yes 4 1 MPC860T 4 4 Up to 4 1 Yes 4 1 MPC860P 16 8 Up to 4 1 Yes 4 1 MPC855T 4 4 1 1 Yes 1 2 1 Supporting documentation for these devices refers to the following 1 MPC860 PowerQUICC Family User s Manual MPC860UM Rev 3 2 MPC855T User s Manual MPC855TUM D Rev 1 2 Features The following list summarizes the key MPC860 features Embe
27. s 208 Data setup time 1 40 fSCL s 209 SDL SCL rise time 1 10 fSCL s 210 SDL SCL fall time 1 33 fSCL s 211 Stop condition setup time 1 2 2 2 fSCL s The ratio SYNCCLK BRGCLK pre_scaler must be greater than or equal to 4 1 Figure 68 shows the PC bus timing Figure 68 I2C Bus Timing Diagram MPC860 Family Hardware Specifications Rev 7 SCL frequency is given by SCL BRGCLK_frequency BRG register 3 x pre_scaler x 2 66 Freescale Semiconductor UTOPIA AC Electrical Specifications 12 UTOPIA AC Electrical Specifications Table 28 shows the AC electrical specifications for the UTOPIA interface Table 28 UTOPIA AC Electrical Specifications Num Signal Characteristic Direction Min Max Unit U1 UtpClk rise fall time Internal clock option Output 3 5 ns Duty cycle 50 50 Frequency 50 MHz Uta UtpClk rise fall time external clock option Input 3 5 ns Duty cycle 40 60 Frequency 50 MHz U2 RxEnb and TxEnb active delay Output 2 16 ns U3 UTPB SOC Rxclav and Txclav setup time Input 8 ns U4 UTPB SOC Rxclav and Txclav hold time Input 1 E ns U5 UTPB SOC active delay and PHREQ and PHSEL active delay Output 2 16 ns in MPHY mode Figure 69 shows signal timings during UTOPIA receive operations UtpClk PHREQn RxClav RxEnb UT
28. with the total system interrupt latency that the MPC860 is able to support Figure 22 provides the interrupt detection timing for the external level sensitive lines CLKOUT IRQx Figure 22 Interrupt Detection Timing for External Level Sensitive Lines Figure 23 provides the interrupt detection timing for the external edge sensitive lines CLKOUT ee o a y a o a 43 gt Figure 23 Interrupt Detection Timing for External Edge Sensitive Lines MPC860 Family Hardware Specifications Rev 7 Freescale Semiconductor 33 Bus Signal Timing Table 9 shows the PCMCIA timing for the MPC860 Table 9 PCMCIA Timing 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max P44 A 0 31 REG valid to PCMCIA 20 73 16 75 13 00 9 36 ns Strobe asserted P45 A 0 31 REG valid to ALE negation 28 30 23 00 18 00 13 15 ns P46 CLKOUT to REG valid 7 58 15 58 6 25 14 25 5 00 13 00 3 79 11 84 ns P47 CLKOUT to REG invalid 8 58 7 25 6 00 4 84 ns P48 CLKOUT to CE1 CE2 asserted 7 58 15 58 6 25 14 25 5 00 13 00 3 79 11 84 ns P49 CLKOUT to CE1 CE2 negated 7 58 15 58 6 25 14 25 5 00 13 00 3 79 11 84 ns P50 CLKOUT to PCOE IORD PCWE 11 00 11 00 11 00 11 00 ns IOWR assert time P51 CLK
29. 0 10 04 ns VF 0 2 IWP 0 2 FRZ LWP 0 1 STS valid B9 CLKOUT to A 0 31 BADDR 28 30 7 58 14 33 6 25 13 00 5 00 11 75 3 80 10 04 ns RD WR BURST D 0 31 DP 0 3 TSIZ 0 1 REG RSV AT 0 3 PTR High Z B11 CLKOUT to TS BB assertion 7 58 13 58 6 25 12 25 5 00 11 00 3 80 11 29 ns B11a CLKOUT to TA Bl assertion when 2 50 9 25 2 50 9 25 2 50 9 25 2 50 9 75 ns driven by the memory controller or PCMCIA interface B12 CLKOUT to TS BB negation 7 58 14 33 6 25 13 00 5 00 11 75 3 80 8 54 ns B12a CLKOUT to TA BI negation when 2 50 11 00 2 50 11 00 2 50 11 00 2 50 9 00 ns driven by the memory controller or PCMCIA interface B13 CLKOUT to TS BB High Z 7 58 21 58 6 25 20 25 5 00 19 00 3 80 14 04 ns B13a CLKOUT to TA BI High Z when 2 50 15 00 2 50 15 00 2 50 15 00 2 50 15 00 ns driven by the memory controller or PCMCIA interface B14 CLKOUT to TEA assertion 2 50 10 00 2 50 10 00 2 50 10 00 2 50 9 00 ns B15 CLKOUT to TEA High Z 2 50 15 00 2 50 15 00 2 50 15 00 2 50 15 00 ns B16 TA BI valid to CLKOUT setup time 9 75 9 75 9 75 600 ns Bi6a TEA KR RETRY CR valid to 10 00 10 00 10 00 450 ns CLKOUT setup time B16b BB BG BR valid to CLKOUT setup 8 50 8 50 8 50 400 ns time 5 B17 C
30. 3 AS negation to memory controller TBD TBD TBD TBD ns signals negation Phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed value If the rate of change of the frequency of EXTAL is slow that is it does not jump between the minimum and maximum values in one cycle or the frequency of the jitter is fast that is it does not stay at an extreme value for a long time then the maximum allowed jitter on EXTAL can be up to 2 The timings specified in B4 and B5 are based on full strength clock The timing for BR output is relevant when the MPC860 is selected to work with external bus arbiter The timing for BG output is relevant when the MPC860 is selected to work with internal bus arbiter The timing required for BR input is relevant when the MPC860 is selected to work with internal bus arbiter The timing for BG input is relevant when the MPC860 is selected to work with external bus arbiter 8 The D 0 31 and DP 0 3 input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input signal is asserted 7 The D 0 31 and DP 0 3 input timings B20 and B21 refer to the falling edge of the CLKOUT This timing is valid only for read accesses controlled by chip selects under control of the UPM in the memory controller for data beats where DLT3 1 in the UPM RAM words This is only the case where data is latched on the falling
31. 50 0 ns rising edge setup time 0 0 0 0 R75 Configuration data hold time after 0 00 0 00 0 00 0 00 ns RSTCONF negation R76 Configuration data hold time after 0 00 0 00 0 00 0 00 ns HRESET negation R77 HRESET and RSTCONF assertedto 25 00 25 00 25 00 25 00 ns data out drive R78 RSTCONF negated to data out high 25 00 25 00 25 00 25 00 ns impedance R79 CLKOUT of last rising edge before 25 00 25 00 25 00 25 00 ns chip three state HRESET to data out high impedance R80 DSDI DSCK setup 90 91 75 00 160 00 45 45 ns R81 DSDI DSCK hold time 0 00 0 00 0 00 0 00 ns R82 SRESET negated to CLKOUT rising 242 4 200 0 160 0 121 2 ns edge for DSDI and DSCK sample 2 0 0 1 Figure 31 shows the reset timing for the data bus configuration MPC860 Family Hardware Specifications Rev 7 Freescale Semiconductor 39 Bus Signal Timing HRESET fe RSTCONF lt R73 gt lt fe 8 sean a Figure 31 Reset Timing Configuration from Data Bus Figure 32 provides the reset timing for the data bus weak drive during configuration cuKouT of ef HRESET RSTCONF er fre D 0 31 OUT Weak a ne Figure 32 Reset Timing Data Bus Weak Drive During Configuration Figure 33 provides the
32. 50D4R2 Sample KMPC855TZQ50D4 KMPC860DEZQ50D4 KMPC860DTZQ50D4 KMPC860TZQ50D4 KMPC860SRZQ50D4 66 ZP ZQ MPC855TZQ66D4 0 to 95 C MPC860DEZQ66D4 MPC860DTZQ66D4 MPC860ENZQ66D4 MPC860SRZQ66D4 MPC860TZQ66D4 MPC860DPZQ66D4 MPC860PZQ66D4 Tape and Reel MPC860SRZQ66D4R2 MPC860PZQ66D4R2 MPC860 Family Hardware Specifications Rev 7 72 Freescale Semiconductor Mechanical Data and Ordering Information Table 34 MPC860 Family Package Frequency Availability continued Package Type Freq MHz Temp Tj Package Sample Order Number KMPC855TZQ66D4 KMPC860SRZQ66D4 KMPC860TZQ66D4 KMPC860ENZQ66D4 KMPC860PZQ66D4 80 0 to 95 C ZP ZQ Tape and Reel Sample MPC855TZQ80D4 MPC860DEZQ80D4 MPC860DTZQ80D4 MPC860ENZQ80D4 MPC860SRZQ80D4 MPC860TZQ80D4 MPC860DPZQ80D4 MPC860PZQ80D4 MPC860PZQ80D4R2 KMPC855TZQ80D4 KMPC860DEZQ80D4 KMPC860DTZQ80D4 KMPC860ENZQ80D4 KMPC860SRZQ80D4 KMPC860TZQ80D4 KMPC860DPZQ80D4 KMPC860PZQ80D4 Ball grid array CZP suffix CZP suffix Leaded CZQ suffix Leaded CVR suffix Lead Free are available as needed 50 40 to 95 C ZP ZQ Tape and Reel MPC855TCZQ50D4 MPC860DECZQ50D4 MPC860DTCZQ50D4 MPC860ENCZQ50D4 MPC860SRCZQ50D4 MPC860TCZQ50D4 MPC860DPCZQ50D4 MPC860PCZQ50D4 MPC855TCZQ50D4R2 66 40 to 95 C ZP ZQ MPC855TCZQ66D4 MPC860ENCZQ66D4 MPC860SRCZQ66D4 MPC860TCZQ66D4 MPC860DPCZQ6
33. 6D4 MPC860PCZQ66D4 1 MPC860 Family Hardware Specifications Rev 7 The ZP package is no longer recommended for use The ZQ package replaces the ZP package Freescale Semiconductor 73 Mechanical Data and Ordering Information 14 1 Pin Assignments Figure 75 shows the top view pinout of the PBGA package For additional information see the MPCS60 PowerQUICC User s Manual or the MPC855T User s Manual NOTE This is the top view of the device O O PD10 PD8 O O PD14 PD13 D9 Gi O O PAO PB14 O O PA1 PC5 C4 Or Os 40 PC6 PA2 O PA4 PB17 PA3 O O O PB19 PAS Oo OO PA7 PC8 PA6 O O O PB22 PC9 PA8 O O O PC10 PAQ PB23 O ss 10 PC11 PB24 PA10 Oe I O VDDL M_MDIO TDI O O TRST TMS TDO O O O PB26 PC12 PA12 Cr Oe O PB27 PC13 PA13 O O 0 PB28 PC14 PA14 O O PB30 PA15 PB31 O Or A AO Al A4 O O A2 A5 18 17 30 o g P gO O gO O20 O RO O80 O80 O 80 O80 O lo v Ce ap O z x mm Zz a O 5 2 o N g D g A 2 g pici S is N A O O e O O U Og 191 3 a O gO iw 8 g g O g lt o iw Y D 8 gO O O O O O D x o I 7 N N a iw nm N g N a is d IPA6 IPAQ e VDDH O O lt D is O zO gO 0 80 O O O glo O z0 9 Zz o 3 O x gt O O 5 iw Q R S O O 8 9 9 O e
34. CLK1 and TCLK1 rise fall time ns 103 TXD1 active delay from TCLK1 falling edge 0 00 30 00 ns 104 RTS1 active inactive delay from TCLK1 falling edge 0 00 30 00 ns 105 CTS1 setup time to TCLK1 rising edge 40 00 ns 106 RXD1 setup time to RCLK1 rising edge 40 00 ns 107 RXD1 hold time from RCLK1 rising edge 0 00 ns 108 CD1 setup time to RCLK1 rising edge 40 00 ns Pf Figure 55 through Figure 57 show the NMSI timings The ratios SYNCCLK RCLK1 and SYNCCLK TCLK1 must be greater than or equal to 3 1 Also applies to CD and CTS hold time when they are used as external sync signals MPC860 Family Hardware Specifications Rev 7 56 Freescale Semiconductor RCLK1 RxD1 Input CD1 Input CD1 SYNC Input TCLK1 TxD1 Output RTS1 Output CTS1 Input CTS1 SYNC Input Figure 55 SCC NMSI Receive Timing Diagram Figure 56 SCC NMSI Transmit Timing Diagram MPC860 Family Hardware Specifications Rev 7 CPM Electrical Characteristics Freescale Semiconductor 57 CPM Electrical Characteristics TCLK1 TxD1 Output RTS1 Output CTS1 Echo Input Figure 57 HDLC Bus Timing Diagram 11 8 Ethernet Electrical Specifications Table 22 provides the Ethernet timings as shown in Figure 58 through Figure 62 Table 22 Ethernet Timing
35. Freescale Semiconductor Technical Data MPC860 Family Hardware Specifications This hardware specification contains detailed information on power considerations DC AC electrical characteristics and AC timing specifications for the MPC860 family 1 Overview The MPC860 Power Quad Integrated Communications Controller PowerQUICC is a versatile one chip integrated microprocessor and peripheral combination designed for a variety of controller applications It particularly excels in communications and networking systems The PowerQUICC unit is referred to as the MPC860 in this hardware specification The MPC860 implements the PowerPC architecture and contains a superset of Freescale s MC68360 Quad Integrated Communications Controller QUICC referred to here as the QUICC RISC Communications Proccessor Module CPM The CPM from the MC68360 QUICC has been enhanced by the addition of the inter integrated controller C channel The memory controller has been enhanced enabling the MPC860 to support any type of memory including high performance memories and new types of DRAMs A PCMCIA socket controller supports up to two sockets A real time clock has also been integrated Table 1 shows the functionality supported by the members of the MPC860 family Freescale Semiconductor Inc 2004 All rights reserved MPC860EC Rev 7 09 2004 Contents a VET VOW pn rs e auda alama aia 8 ar trai a magn ta 1 i Peate snoeren aan
36. Hardware Specifications Rev 7 24 Freescale Semiconductor Bus Signal Timing CLKOUT ff Nee ge E E S A 0 31 CSx OE he D 0 31 DP 0 3 Figure 10 External Bus Read Timing GPCM Controlled TRLX 0 ACS 10 agree 8 B22b gt CSx D 0 31 DP 0 3 Figure 11 External Bus Read Timing GPCM Controlled TRLX 0 ACS 11 MPC860 Family Hardware Specifications Rev 7 Freescale Semiconductor 25 Bus Signal Timing CLKOUT 6 ZI CSx 2 2 OE a 27a gt faa o fis ane si pa Figure 12 External Bus Read Timing GPCM Controlled TRLX 0 or 1 ACS 10 ACS 11 Figure 13 through Figure 15 provide the timing for the external bus write controlled by various GPCM factors MPC860 Family Hardware Specifications Rev 7 26 Freescale Semiconductor A 0 31 Bus Signal Timing CSx N WE 0 3 D 0 31 DP 0 3 Figure 13 External Bus Write Timing GPCM Controlled TRLX 0 or 1 CSNT 0 MPC860 Family Hardware Specifications Rev 7 Freescale Semiconductor 27 Bus Signal Timing CLKOUT NE IE E IE E fF IE D 0 31 DP 0 3 mg Figure 14 External Bus Write Timing GPCM Controlled TRLX 0 or 1 CSNT 1 MPC860 Family Hardware Specifications Rev 7 28 Freescale Semiconductor Bu
37. LK must be at least twice as fast as SMCLK SMCLK SMTXD Output SMSYNC SMRXD Input NOTE 1 This delay is equal to an integer number of character length clocks Figure 63 SMC Transparent Timing Diagram 11 10SPI Master AC Electrical Specifications Table 24 provides the SPI master timings as shown in Figure 64 and Figure 65 MPC860 Family Hardware Specifications Rev 7 Freescale Semiconductor 61 CPM Electrical Characteristics Table 24 SPI Master Timing All Frequencies Num Characteristic Unit Min Max 160 MASTER cycle time 4 1024 teyc 161 MASTER clock SCK high or low time 2 512 teyc 162 MASTER data setup time inputs 50 ns 163 Master data hold time inputs 0 ns 164 Master data valid after SCK edge 20 ns 165 Master data hold time outputs 0 ns 166 Rise time output 15 ns 167 Fall time output 15 ns SPICLK Cl 0 Output SPICLK Cl 1 Output SPIMISO Input SPIMOSI Output Figure 64 SPI Master CP 0 Timing Diagram MPC860 Family Hardware Specifications Rev 7 62 Freescale Semiconductor SPICLK Cl 0 Output SPICLK Cl 1 Output SPIMISO Input SPIMOSI Output Figure 65 SPI Master CP 1 Timing Diagram 11 11SPI Slave AC Electrical Specifications Table 25 provides the SPI slave timings as sho
38. LKOUT to TA TEA BI BB BG BR 1 00 1 00 1 00 200 ns valid hold time B17a CLKOUT to KR RETRY CR valid 2 00 200 200 200 ns hold time MPC860 Family Hardware Specifications Rev 7 Freescale Semiconductor 13 Bus Signal Timing Table 7 Bus Operation Timings continued 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max B18 D 0 31 DP 0 3 valid to CLKOUT 6 00 6 00 6 00 6 00 ns rising edge setup time B19 CLKOUT rising edge to D 0 31 1 00 1 00 1 00 2 00 ns DP 0 3 valid hold time B20 D 0 31 DP 0 3 valid to CLKOUT 4 00 4 00 4 00 400 ns falling edge setup time 7 B21 CLKOUT falling edge to D 0 31 200 200 200 200 Ins DP 0 3 valid hold time 7 B22 CLKOUT rising edge to CS asserted 7 58 14 33 6 25 13 00 5 00 11 75 3 80 10 04 ns GPCM ACS 00 B22a CLKOUT falling edge to CS asserted 8 00 8 00 8 00 8 00 ns GPCM ACS 10 TRLX 0 B22b CLKOUT falling edge to CS asserted 7 58 14 33 6 25 13 00 5 00 11 75 3 80 10 54 ns GPCM ACS 11 TRLX 0 EBDF 0 B22c CLKOUT falling edge to CS asserted 10 86 17 99 8 88 16 00 7 00 14 13 5 18 12 31 ns GPCM ACS 11 TRLX 0 EBDF 1 B23 CLKOUT rising edge to CS negated
39. Num Characteristic Unit Min Max 40 DREQ setup time to clock high 7 ns 41 DREQ hold time from clock high 3 ns 42 SDACK assertion delay from clock high 12 ns 43 SDACK negation delay from clock low 12 ns 44 SDACK negation delay from TA low 20 ns 45 SDACK negation delay from clock high 15 ns 46 TA assertion to falling edge of the clock setup time applies to A ns external TA CLKO Output DREQ Input Figure 44 IDMA External Requests Timing Diagram MPC860 Family Hardware Specifications Rev 7 46 Freescale Semiconductor CPM Electrical Characteristics CLKO Output TS Output RW Output TA Input SDACK Figure 45 SDACK Timing Diagram Peripheral Write Externally Generated TA CLKO Output TS Output R W Output TA L Output SDACK N Figure 46 SDACK Timing Diagram Peripheral Write Internally Generated TA MPC860 Family Hardware Specifications Rev 7 Freescale Semiconductor 47 CPM Electrical Characteristics CLKO Output TS Output RW Output TA Output SDACK _ en Figure 47 SDACK Timing Diagram Peripheral Read Internally Generated TA 11 4 Baud Rate Generator AC Electrical Specifications Table 17 provides the baud rate generator timings as shown in Figure 48 Table 17 Baud Rate Generator Timing All Frequencies Num Characteristic Unit Min Max
40. OUT to PCOE IORD PCWE 2 00 11 00 2 00 11 00 2 00 11 00 2 00 11 00 ns IOWR negate time P52 CLKOUT to ALE assert time 7 58 15 58 6 25 14 25 5 00 13 00 3 79 10 04 ns P53 CLKOUT to ALE negate time 15 58 14 25 13 00 11 84 ns P54 PCWE IOWR negated to D 0 31 5 58 4 25 3 00 1 79 ns invalid 1 P55 WAITA and WAITB valid to CLKOUT 8 00 8 00 8 00 8 00 ns rising edge P56 CLKOUT rising edge to WAITA and 2 00 i 2 00 2 00 2 00 ns WAITB invalid 1 PSST 1 Otherwise add PSST times cycle time PSHT 0 Otherwise add PSHT times cycle time These synchronous timings define when the WAITx signals are detected in order to freeze or relieve the PCMCIA current cycle The WAITx assertion will be effective only if it is detected 2 cycles before the PSL timer expiration See Chapter 16 PCMCIA Interface in the MPC860 PowerQUICC User s Manual Figure 24 provides the PCMCIA access cycle timing for the external bus read MPC860 Family Hardware Specifications Rev 7 34 Freescale Semiconductor Bus Signal Timing CLKOUT NANA N PCOE IORD D 0 31 Figure 24 PCMCIA Access Cycle Timing External Bus Read Figure 25 provides the PCMCIA access cycle timing for the external bus write MPC860 Family Hardware Specifications Rev 7 Freescale Semiconductor 35 Bus Signal Timin
41. PB SOC Figure 69 UTOPIA Receive Timing Figure 70 shows signal timings during UTOPIA transmit operations MPC860 Family Hardware Specifications Rev 7 Freescale Semiconductor 67 FEC Electrical Characteristics UtpClk PHSELn TxClav Figure 70 UTOPIA Transmit Timing 13 FEC Electrical Characteristics This section provides the AC electrical specifications for the Fast Ethernet controller FEC Note that the timing specifications for the MII signals are independent of system clock frequency part speed designation Also MII signals use TTL signal levels compatible with devices operating at either 5 0 V or 3 3 V 13 1 MII Receive Signal Timing MIl_RXD 3 0 MIl_ RX_DV Mil_ RX_ER MIL RX_CLK The receiver functions correctly up to a MIT_RX_CLK maximum frequency of 25 MHz 1 There is no minimum frequency requirement In addition the processor clock frequency must exceed the MIT_RX_CLK frequency 1 Table 29 provides information on the MII receive signal timing Table 29 MII Receive Signal Timing Num Characteristic Min Max Unit M1 MIL_RXD 3 0 MII_RX_DV MII_RX_ER to MIl_RX_CLK setup 5 ns M2 MIL_RX_CLK to MII RXD 3 0 MIl_RX_DV MII _RX_ER hold 5 ns M3 MII_RX CLK pulse width high 35 65 MIL_RX_CL K period M4 MIL_RX_CLK pulse width low 35 65 MIIL_RX_CL K period Figure 71 shows MII receive signal timing MPC860 Family Har
42. ble 31 MII Async Inputs Signal Timing Num Characteristic Min Max Unit M9 MIL_CRS MII_COL minimum pulse width 1 5 MII_TX_CLK period Figure 73 shows the MII asynchronous inputs signal timing diagram MII_CRS MII_COL z M9 Figure 73 MII Async Inputs Timing Diagram 13 4 MII Serial Management Channel Timing MII_MDIO MII_MDC Table 32 provides information on the MII serial management channel signal timing The FEC functions correctly with a maximum MDC frequency in excess of 2 5 MHz The exact upper bound is under investigation Table 32 MII Serial Management Channel Timing MII_MDC falling edge to MII_MDIO output invalid minimum propagation delay Mat mi MDC falling edge to MII_MDIO output valid max prop delay POEET input to MII_MDC rising edge setup EIEII MPC860 Family Hardware Specifications Rev 7 70 Freescale Semiconductor Mechanical Data and Ordering Information Table 32 MII Serial Management Channel Timing MII_MDIO input to MII_MDC rising edge hold IRON ie Ss SEA M14 MII_MDC pulse width high 40 60 MII_MDC period M15 MII_MDC pulse width low 40 60 MII_MDC period Figure 74 shows the MII serial management channel timing diagram M14 PP MM15 MII_MDC Output To a M10 MII_MDIO Output M11 MII_MDIO Input YX W aa M12 M13 Figure 74 MII Serial Management Channel Timing Diagram 14 Mechanical Data an
43. care should be taken to minimize the noise levels on the PLL supply pins 9 Bus Signal Timing Table 7 provides the bus operation timing for the MPC860 at 33 40 50 and 66 MHz The maximum bus speed supported by the MPC860 is 66 MHz Higher speed parts must be operated in half speed bus mode for example an MPC860 used at 80 MHz must be configured for a 40 MHz bus The timing for the MPC860 bus shown assumes a 50 pF load for maximum delays and a 0 pF load for minimum delays Table 7 Bus Operation Timings 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max B1 CLKOUT period 30 30 30 30 25 00 30 30 20 00 30 30 15 15 30 30 ns Bla EXTCLK to CLKOUT phase skew 0 90 0 90 0 90 0 90 0 90 0 90 0 90 0 90 ns EXTCLK gt 15 MHz and MF lt 2 Bib EXTCLK to CLKOUT phase skew 2 30 2 30 2 30 2 30 2 30 2 30 2 30 2 30 ns EXTCLK gt 10 MHz and MF lt 10 Bic CLKOUT phase jitter EXTCLK gt 0 60 0 60 0 60 0 60 0 60 0 60 0 60 0 60 ns 15 MHz and MF lt 2 Bid CLKOUT phase jitter 2 00 2 00 2 00 2 00 2 00 2 00 2 00 2 00 ns Bte CLKOUT frequency jitter MF lt 10 0 50 0 50 0 50 0 50 B1f CLKOUT frequency jitter 10 lt MF 2 00 2 00 2 00 2 00 lt 500 Big CEKOUT frequency jitter MF gt 500 3 00
44. cense All other product or service names are the property of their respective owners Freescale Semiconductor Inc 2004 Po Psd 2 freescale semiconductor Table 7 Bus Operation Timings continued Bus Signal Timing Num Characteristic 33 MHz 40 MHz 50 MHz 66 MHz Min Max Min Max Min Max Min Max Unit B30 CS WE 0 3 negated to A 0 31 BADDR 28 30 invalid GPCM write access 8 5 58 4 25 3 00 1 79 ns B30a WE 0 3 negated to A 0 31 BADDR 28 30 invalid GPCM write access TRLX 0 CSNT 1 CS negated to A 0 31 invalid GPCM write access TRLX 0 CSNT 1 ACS 10 or ACS 11 EBDF 0 13 15 10 50 5 58 ns B30b WE 0 3 negated to A 0 31 invalid GPCM BADDR 28 30 invalid GPCM write access TRLX 1 CSNT 1 CS negated to A 0 31 Invalid GPCM write access TRLX 1 CSNT 1 ACS 10 or ACS 11 EBDF 0 43 45 35 50 28 00 20 73 ns B30c WE 0 3 negated to A 0 31 BADDR 28 30 invalid GPCM write access TRLX 0 CSNT 1 CS negated to A 0 31 invalid GPCM write access TRLX 0 CSNT 1 ACS 10 ACS 11 EBDF 1 6 38 4 50 2 68 ns B30d WE 0 3 negated to A 0 31 BADDR 28 30 invalid GPCM write access TRLX 1 CSNT 1 CS negated to A 0 31 invalid GPCM write access TRLX 1 CSNT 1 ACS 10 or ACS 11 EBDF 1 38 67 31 38 24 50 17 83 ns
45. cts are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc The PowerPC name is a trademark of IBM Corp and is used under license All other product or service names are the property of their respective owners Freescale Semiconductor Inc 2004 Po Psd 2 freescale semiconductor
46. d Ordering Information Table 33 provides information on the MPC860 Revision D 4 derivative devices Table 33 MPC860 Family Revision D 4 Derivatives Bevite Number of Ethernet Support 2 Multichannel ATM SCCs Mbps HDLC Support Support MPC855T 1 10 100 Yes Yes MPC860DE 2 10 N A N A MPC860DT 10 100 Yes Yes MPC860DP 10 100 Yes Yes MPC860 Family Hardware Specifications Rev 7 Freescale Semiconductor 71 Mechanical Data and Ordering Information Table 33 MPC860 Family Revision D 4 Derivatives continued pavice Number of Ethernet Support 2 Multichannel ATM SCCs Mbps HDLC Support Support MPC860EN 4 10 N A N A MPC860SR 10 Yes Yes MPC860T 10 100 Yes Yes MPC860P 10 100 Yes Yes 1 Serial communications controller SCC 2 Up to 4 channels at 40 MHz or 2 channels at 25 MHz Table 34 identifies the packages and operating frequencies available for the MPC860 Table 34 MPC860 Family Package Frequency Availability Freq MHz Package Type Temp Tj Package Order Number Ball grid array 50 ZP ZQ MPC855TZQ50D4 ZP suffix Leaded 0 to 95 C MPC860DEZQ50D4 ZQ suffix Leaded MPC860DTZQ50D4 VR suffix Lead Free are available as needed MPC860ENZQ50D4 MPC860SRZQ50D4 MPC860TZQ50D4 MPC860DPZQ50D4 MPC860PZQ50D4 Tape and Reel MPC855TZQ50D4R2 MPC860DEZQ50D4R2 MPC860ENZQ50D4R2 MPC860SRZQ50D4R2 MPC860TZQ50D4R2 MPC860DPZQ
47. dded single issue 32 bit PowerPC core implementing the PowerPC architecture with thirty two 32 bit general purpose registers GPRs The core performs branch prediction with conditional prefetch without conditional execution 4 or 8 Kbyte data cache and 4 or 16 Kbyte instruction cache see Table 1 16 Kbyte instruction caches are four way set associative with 256 sets 4 Kbyte instruction caches are two way set associative with 128 sets 8 Kbyte data caches are two way set associative with 256 sets 4 Kbyte data caches are two way set associative with 128 sets Cache coherency for both instruction and data caches is maintained on 128 bit 4 word cache blocks Caches are physically addressed implement a least recently used LRU replacement algorithm and are lockable on a cache block basis MMUs with 32 entry TLB fully associative instruction and data TLBs MMUs support multiple page sizes of 4 16 and 512 Kbytes and 8 Mbytes 16 virtual address spaces and 16 protection groups Advanced on chip emulation debug mode Up to 32 bit data bus dynamic bus sizing for 8 16 and 32 bits 32 address lines Operates at up to 80 MHz Memory controller eight banks Contains complete dynamic RAM DRAM controller MPC860 Family Hardware Specifications Rev 7 Freescale Semiconductor Features Each bank can be a chip select or RAS to support a DRAM bank Up to 15 wait states programmable per memory
48. dware Specifications Rev 7 68 Freescale Semiconductor M3 lt ______ MIl_RX_CLK Input a y M4 MII_RXD 3 0 Inputs MII_RX_DV MII_RX_ER F IERI M1 M2 Figure 71 MII Receive Signal Timing Diagram 13 2 MII Transmit Signal Timing MII_TXD 3 0 MII_TX_EN MII_TX_ER MII_TX_CLK The transmitter functions correctly up to a MII_TX_CLK maximum frequency of 25 MHz 1 There is no minimum frequency requirement In addition the processor clock frequency must exceed the MII_TX_CLK frequency 1 Table 30 provides information on the MII transmit signal timing Table 30 MII Transmit Signal Timing Num Characteristic Min Max Unit M5 MIL_TX_CLK to MII_TXD 3 0 MIl_TX_EN MIIL_TX_ER invalid 5 ns M6 MIL_TX_CLK to MII_TXD 3 0 MIl_TX_EN MII_TX_ER valid 25 M7 MIIL_TX CLK pulse width high 35 65 MIL_TX_CLK period M8 MII_TX CLK pulse width low 35 65 MIL_TX_CLK period Figure 72 shows the MII transmit signal timing diagram MPC860 Family Hardware Specifications Rev 7 FEC Electrical Characteristics Freescale Semiconductor 69 FEC Electrical Characteristics M7 MII_TX_CLK Input vs MII_TXD 3 0 Outputs MIIL_TX_EN MIIL_TX_ER gt M6 Figure 72 MII Transmit Signal Timing Diagram 13 3 MII Async Inputs Signal Timing MII_CRS MIl_COL Table 31 provides information on the MII async inputs signal timing Ta
49. easurement of the temperature at the top center of the package case using the following equation Ty Tr yr x Pp where yr thermal characterization parameter T thermocouple temperature on top of package Pp power dissipation in package The thermal characterization parameter is measured per JEDEC JESD51 2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case The thermocouple should be positioned so that the thermocouple junction rests on the package A small amount of epoxy is placed over the thermocouple junction and over mm of wire extending from the junction The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire 7 6 References Semiconductor Equipment and Materials International 415 964 5111 805 East Middlefield Rd Mountain View CA 94043 MIL SPEC and EIA JESD JEDEC Specifications 800 854 7179 or Available from Global Engineering Documents 303 397 7956 JEDEC Specifications http www jedec org 1 C E Triplett and B Joiner An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module Proceedings of SemiTherm San Diego 1998 pp 47 54 2 B Joiner and V Adams Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling Proceedings of SemiTherm San Diego 1999 pp 212 220 8 Layout P
50. ed in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc The PowerPC name is a trademark of IBM Corp and is used under li
51. g CLKOUT A 0 31 PCWE IOWR ALE D 0 31 Figure 25 PCMCIA Access Cycle Timing External Bus Write Figure 26 provides the PCMCIA WAIT signal detection timing CLKOUT WAITx Figure 26 PCMCIA WAIT Signal Detection Timing Table 10 shows the PCMCIA port timing for the MPC860 MPC860 Family Hardware Specifications Rev 7 36 Freescale Semiconductor Bus Signal Timing Table 10 PCMCIA Port Timing 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max P57 CLKOUT to OPx valid 19 00 19 00 19 00 19 00 ns P58 HRESET negated to OPx drive f 25 73 21 75 18 00 14 36 ns P59 IP_Xx valid to CLKOUT rising edge 5 00 5 00 5 00 5 00 ns P60 CLKOUT rising edge to IP_Xx 1 00 1 00 1 00 1 00 ns invalid 1 OP2 and OP3 only Figure 27 provides the PCMCIA output port timing for the MPC860 CLKOUT ms Output Signals HRESET eee OP2 OP3 4 Figure 27 PCMCIA Output Port Timing Figure 28 provides the PCMCIA output port timing for the MPC860 CLKOUT Input Signals Figure 28 PCMCIA Input Port Timing Table 11 shows the debug port timing for the MPC860 MPC860 Family Hardware Specifications Rev 7 Freescale Semiconductor 37 Bus Signal Timing Table 11 Debug Port Timing
52. he 1 5 V as specified in the I C standard MPC860 Family Hardware Specifications Rev 7 Freescale Semiconductor Thermal Calculation and Measurement 3 A 0 31 TSIZO REG TSIZ1 D 0 31 DP 0 3 1RQ 3 6 RD WR BURST RSV IRQ2 IP_B 0 1 IWP 0 1 VFLS 0 1 IP_B2 IOIS16_B AT2 IP_B3 IWP2 VF2 IP_B4 LWPO VFO IP_B5 LWP1 VF1 IP_B6 DSDI ATO IP_B7 PTR AT3 RXD1 PA15 RXD2 PA13 L1TXDB PA11 L1RXDB PA10 L1TXDA PAQ L1RXDA PAS8 TIN1 L1 RCLKA BRGO1 CLK1 PA7 BRGCLK1 TOUT1 CLK2 PA6 TIN2 L1TCLKA BRGO2 CLK3 PAS TOUT2 CLK4 PA4 TIN3 BRGO3 CLK5 PA3 BRGCLK2 L1RCLKB TOUT3 CLK6 PA2 TIN4 BRGO4 CLK7 PA1 L1TCLKB TOUT4 CLK8 PAO REJCT1 SPISEL PB31 SPICLK PB30 SPIMOSI PB29 BRGO4 SPIMISO PB28 BRGO1 I2CSDA PB27 BRGO2 I2CSCL PB26 SMTXD1 PB25 SMRXD1 PB24 SMSYN1 SDACK1 PB23 SMSYN2 SDACK2 PB22 SMTXD2 L1CLKOB PB21 SMRXD2 L1CLKOA PB20 L1ST1 RTS1 PB19 L1ST2 RTS2 PB18 L1ST3 L1RQB PB17 L1ST4 L1RQA PB16 BRGO3 PB15 RSTRT1 PB14 L1ST1 RTS1 DREQO PC15 L1ST2 RTS2 DREQ1 PC14 L1ST3 L1RQB PC13 L1ST4 L1RQA PC12 CTS1 PC11 TGATE1 CD1 PC10 CTS2 PC9 TGATE2 CD2 PC8 SDACK2 L1TSYNCB PC7 L1RSYNCB PC6 SDACK1 L1TSYNCA PC5 L1RSYNCA PC4 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD5 PD6 PD7 PD4 PD3 MII_MDC MIl_TX_ER MII_EN MII_MDIO MIl_TXD 0 3 BDIP GPL_B 5 BR BG FRZ IRQ6 CS 0 5 CS 6 CE 1 _B CS 7 CE 2 _B WE0 BS_BO IORD WE1 BS_B1 IOWR WE2 BS_B2 PCOE WE3 BS_B3 PCWE BS_A 0 3 GPL_AO GPL_BO OE GPL_AT GPL B1 GPL_A 2 3 GPL_B
53. igure 76 shows the mechanical dimensions of the ZP PBGA package MPC860 Family Hardware Specifications Rev 7 74 Freescale Semiconductor Mechanical Data and Ordering Information TOP VIEW A2 A3 Al A 18X e SIDE VIEW WI V U T R P N M K E1 J H G MILLIMETERS 5 DIM MIN MAX 5 A 2 05 A1 0 50 0 70 357X b A2 0 95 1 35 A3 0 70 0 90 BOTTOM VIEW O H 0 3 Wiciale b 0 60 0 90 D 25 00 BSC S 0 150 Ic pi 22 86 BSC D2 22 40 22 60 e 1 27 BSC E 25 00 BSC NOTE E1 22 86 BSC 1 Dimensions and tolerance per ASME Y14 5M 1994 E2 22 40 22 60 Dimensions in millimeters 3 Dimension b is the maximum solder ball diameter Figure 76 Mechanical Dimensions and Bottom Surface Nomenclature of the ZP PBGA Package Figure 77 shows the mechanical dimensions of the ZQ PBGA package MPC860 Family Hardware Specifications Rev 7 Freescale Semiconductor 75 Mechanical Data and Ordering Information AL INDEX SEATING PLANE A zanamanz Nrcaan ccf i ha ha Ca mn a a D H BA 0 5 1 2 14 adu ee dTant ia ARTA 357 op gn prenna SIDE VIEW 20 1504 A BOTTOM VIEW ENTE NOTE All Dimensions in millimeters Dimensions
54. ing frame synchronization and clocking Allows dynamic changes Can be internally connected to six serial channels four SCCs and two SMCs e Parallel interface port PIP Centronics interface support Supports fast connection between compatible ports on the MPC860 or the MC68360 e PCMCIA interface Master socket interface release 2 1 compliant Supports two independent PCMCIA sockets Supports eight memory or I O windows e Low power support Full on all units fully powered Doze core functional units disabled except time base decrementer PLL memory controller RTC and CPM in low power standby Sleep all units disabled except RTC and PIT PLL active for fast wake up Deep sleep all units disabled including PLL except RTC and PIT Power down mode all units powered down except PLL RTC PIT time base and decrementer e Debug interface Eight comparators four operate on instruction address two operate on data address and two operate on data Supports conditions lt gt Each watchpoint can generate a break point internally e 3 3 V operation with 5 V TTL compatibility except EXTAL and EXTCLK e 357 pin ball grid array BGA package 3 Maximum Tolerated Ratings This section provides the maximum tolerated voltage and temperature ranges for the MPC860 Table 2 provides the maximum ratings This device contains circuitry protecting against damage due to high static vo
55. ltage or electrical fields however it is advised that normal precautions be taken to avoid application of any voltages higher than maximum rated voltages to this high impedance circuit Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level for example either GND or V qq MPC860 Family Hardware Specifications Rev 7 Freescale Semiconductor 5 Thermal Characteristics Table 2 Maximum Tolerated Ratings GND 0V Rating Symbol Value Unit Supply voltage VDDu 0 3 to 4 0 V VDDL 0 3 to 4 0 V KAPWR 0 3 to 4 0 V VDDSYN 0 3 to 4 0 V Input voltage Vin GND 0 3 to V VDDH Temperature standard TA min 0 C Ti max 95 C Temperature 3 extended TA min 40 C Ti max 95 C Storage temperature range Tstg 55 to 150 C 1 The power supply of the device must start its ramp from 0 0 V 2 Functional operating conditions are provided with the DC electrical specifications in Table 6 Absolute maximum ratings are stress ratings only functional operation at the maxima is not guaranteed Stress beyond those listed may affect device reliability or cause permanent damage to the device Caution All inputs that tolerate 5 V cannot be more than 2 5 V greater than the supply voltage This restriction applies to power up and normal operation that is if the MPC860 is unpowered voltage greater than 2 5 V must not be
56. mperature Rise Above Ambient Divided by Package Power Figure 1 Effect of Board Temperature Rise on Thermal Behavior If the board temperature is known an estimate of the junction temperature in the environment can be made using the following equation Ty Tg Rozp X Pp where Rgyp junction to board thermal resistance C W Tp board temperature C Pp power dissipation in package If the board temperature is known and the heat loss from the package case to the air can be ignored acceptable predictions of junction temperature can be made For this method to work the board and board mounting must be similar to the test board used to determine the junction to board thermal resistance namely a 2s2p board with a power and a ground plane and by attaching the thermal balls to the ground plane MPC860 Family Hardware Specifications Rev 7 10 Freescale Semiconductor Layout Practices 7 4 Estimation Using Simulation When the board temperature is not known a thermal simulation of the application is needed The simple two resistor model can be used with the thermal simulation of the application 2 or a more accurate and complex model of the package can be used in the thermal simulation 7 5 Experimental Determination To determine the junction temperature of the device in the application after prototypes are available the thermal characterization parameter Y yy can be used to determine the junction temperature with a m
57. nals CLKOUT p 6134 gt TEA Figure 5 Synchronous Active Pull Up Resistor and Open Drain Outputs Signals Timing Figure 6 provides the timing for the synchronous input signals CLKOUT PE ee eee O ee S TEA KR RETRY CR E DN 0 0 Ge 4 0 CI Figure 6 Synchronous Input Signals Timing e DD a EI wo Figure 7 provides normal case timing for input data It also applies to normal read accesses under the control of the UPM in the memory controller MPC860 Family Hardware Specifications Rev 7 22 Freescale Semiconductor Bus Signal Timing CLKOUT O O A SE DE O o 3 o III 7 7 618 T woi NNO OOA o DP 0 3 Figure 7 Input Data Timing in Normal Case Figure 8 provides the timing for the input data controlled by the UPM for data beats where DLT3 1 in the UPM RAM words This is only the case where data is latched on the falling edge of CLKOUT CLKOUT ee Se eee ee re D 0 31 DP 0 3 Figure 8 Input Data Timing when Controlled by UPM in the Memory Controller and DLT3 1 Figure 9 through Figure 12 provide the timing for the external bus read controlled by various GPCM factors MPC860 Family Hardware Specifications Rev 7 Freescale Semiconductor 23 Bus Signal Timing SR 3 CSx WE 0 3 D 0 31 DP 0 3 Figure 9 External Bus Read Timing GPCM Controlled ACS 00 MPC860 Family
58. nit Min Max Min Max Min Max Min Max B28b CLKOUT falling edge to CS negated 14 33 13 00 11 75 10 54 ns GPCM write access TRLX 0 1 CSNT 1 ACS 10 or ACS 11 EBDF 0 B28c CLKOUT falling edge to WE 0 3 10 86 17 99 8 88 16 00 7 00 14 13 5 18 12 31 ns negated GPCM write access TRLX 0 1 CSNT 1 write access TRLX 0 CSNT 1 EBDF 1 B28d CLKOUT falling edge to CS negated 17 99 16 00 14 13 12 31 ns GPCM write access TRLX 0 1 CSNT 1 ACS 10 or ACS 11 EBDF 1 B29 WE 0 3 negated to D 0 31 DP 0 3 5 58 4 25 3 00 1 79 ns High Z GPCM write access CSNT 0 EBDF 0 B29a WE 0 3 negated to D 0 31 DP 0 3 13 15 10 5 8 00 5 58 ns High Z GPCM write access TRLX 0 CSNT 1 EBDF 0 B29b CS negated to D 0 31 DP 0 3 5 58 4 25 3 00 1 79 ns High Z GPCM write access ACS 00 TRLX 0 1 and CSNT 0 B29c CS negated to D 0 31 DP 0 3 13 15 10 5 8 00 5 58 ns High Z GPCM write access TRLX 0 CSNT 1 ACS 10 or ACS 11 EBDF 0 B29d WE 0 3 negated to D 0 31 DP 0 3 43 45 35 5 28 00 20 73 ns High Z GPCM write access TRLX 1 CSNT 1 EBDF 0 B29e CS negated to D 0 31 DP 0 3 43 45 35 5 28 00 29 73 ns High Z GPCM write access TRLX 1 CSNT 1 ACS 10 or ACS 11
59. ols ATM pace control APC scheduler providing direct support for constant bit rate CBR and unspecified bit rate UBR and providing control mechanisms enabling software support of available bit rate ABR Physical interface support for UTOPIA 10 100 Mbps is not supported with this interface and byte aligned serial for example T1 E1 ADSL MPC860 Family Hardware Specifications Rev 7 Freescale Semiconductor 3 Features UTOPIA mode ATM supports level 1 master with cell level handshake multi PHY up to four physical layer devices connection to 25 51 or 155 Mbps framers and UTOPIA system clock ratios of 1 2 or 1 3 Serial mode ATM connection supports transmission convergence TC function for T1 E1 ADSL lines cell delineation cell payload scrambling descrambling automatic idle unassigned cell insertion stripping header error control HEC generation checking and statistics e Communications processor module CPM RISC communications processor CP Communication specific commands for example GRACEFUL STOP TRANSMIT ENTER HUNT MODE and RESTART TRANSMIT Supports continuous mode transmission and reception on all serial channels Upto 8 Kbytes of dual port RAM 16serial DMA SDMA channels Three parallel I O registers with open drain capability e Four baud rate generators BRGs Independent can be tied to any SCC or SMC Allows changes during operation Autobaud support
60. ons Rev 7 Freescale Semiconductor 43 CPM Electrical Characteristics DATA OUT STBO Output STBI Input Figure 39 PIP Tx Interlock Mode Timing Diagram DATA IN pa as STBI Input STBO Output DATA OUT STBO Output STBI Input Figure 41 PIP TX Pulse Mode Timing Diagram MPC860 Family Hardware Specifications Rev 7 44 Freescale Semiconductor CPM Electrical Characteristics CLKO DATA IN DATA OUT Figure 42 Parallel I O Data In Data Out Timing Diagram 11 2 Port C Interrupt AC Electrical Specifications Table 15 provides the timings for port C interrupts Table 15 Port C Interrupt Timing gt 33 34 MHz Num Characteristic Unit Min Max 35 Port C interrupt pulse width low edge triggered mode 55 ns 36 Port C interrupt minimum time between active edges 55 ns 1 External bus frequency of greater than or equal to 33 34 MHz Figure 43 shows the port C interrupt detection timing 6 gt PortC Input Figure 43 Port C Interrupt Detection Timing 11 3 IDMA Controller AC Electrical Specifications Table 16 provides the IDMA controller timings as shown in Figure 44 through Figure 47 MPC860 Family Hardware Specifications Rev 7 Freescale Semiconductor 45 CPM Electrical Characteristics Table 16 IDMA Controller Timing All Frequencies
61. ractices Each Vpp pin on the MPC860 should be provided with a low impedance path to the board s supply Each GND pin should likewise be provided with a low impedance path to ground The power supply pins drive distinct groups of logic on the chip The Vpp power supply should be bypassed to ground using at least four 0 1 uF bypass capacitors located as close as possible to the four sides of the package The capacitor leads and associated printed circuit traces connecting to chip Vpp and GND should be kept to less than half an inch per capacitor lead A four layer board employing two inner layers as Vcc and GND planes is recommended MPC860 Family Hardware Specifications Rev 7 Freescale Semiconductor 11 Bus Signal Timing All output pins on the MPC860 have fast rise and fall times Printed circuit PC trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times This recommendation particularly applies to the address and data buses Maximum PC trace lengths of 6 inches are recommended Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PC traces Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the Vcc and GND circuits Pull up all unused inputs or signals that will be inputs during reset Special
62. reescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 800 441 2447 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com MPC860EC Rev 7 09 2004 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor produ
63. reset timing for the debug port configuration MPC860 Family Hardware Specifications Rev 7 40 Freescale Semiconductor IEEE 1149 1 Electrical Specifications SRESET SETS feo gt Sy DSCK DSDI Figure 33 Reset Timing Debug Port Configuration 10 IEEE 1149 1 Electrical Specifications Table 13 provides the JTAG timings for the MPC860 shown in Figure 34 through Figure 37 Table 13 JTAG Timing All Frequencies Num Characteristic Unit Min Max J82 TCK cycle time 100 00 ns J83 TCK clock pulse width measured at 1 5 V 40 00 ns J84 TCK rise and fall times 0 00 10 00 ns J85 TMS TDI data setup time 5 00 ns J86 TMS TDI data hold time 25 00 ns J87 TCK low to TDO data valid 27 00 ns J88 TCK low to TDO data invalid 0 00 ns J89 TCK low to TDO high impedance 20 00 ns J90 TRST assert time 100 00 ns J91 TRST setup time to TCK low 40 00 ns J92 TCK falling edge to output valid 50 00 ns J93 TCK falling edge to output valid out of high impedance 50 00 ns J94 TCK falling edge to output high impedance 50 00 ns J95 Boundary scan input valid to TCK rising edge 50 00 ns J96 TCK rising edge to boundary scan input invalid 50 00 ns MPC860 Family Hardware Specifications Rev 7 Freescale Semiconductor 41 IEEE 1149 1 Electrical Specifications TCK TMS TDI
64. rmal environment to affect the case to ambient thermal resistance Rgca For instance the user can change the air flow around the device add a heat sink change the mounting arrangement on the printed circuit board or change the thermal dissipation on the MPC860 Family Hardware Specifications Rev 7 Freescale Semiconductor 9 Thermal Calculation and Measurement printed circuit board surrounding the device This thermal model is most useful for ceramic packages with heat sinks where some 90 of the heat flows through the case and the heat sink to the ambient environment For most packages a better model is required 7 3 Estimation with Junction to Board Thermal Resistance A simple package thermal model which has demonstrated reasonable accuracy about 20 is a two resistor model consisting of a junction to board and a junction to case thermal resistance The junction to case thermal resistance covers the situation where a heat sink is used or where a substantial amount of heat is dissipated from the top of the package The junction to board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board It has been observed that the thermal performance of most plastic packages especially PBGA packages is strongly dependent on the board temperature see Figure 1 100 30 o D a6 PI 2 a 2 8 70 CC x og 60 3a Ea 50 9 Fs 5p 30 3 o CO 20 3 amp 10 0 0 20 40 60 80 Board Te
65. s Signal Timing Gia E A 0 31 625 a B2ooea gt B29d B29h D 0 31 DP 0 3 Figure 15 External Bus Write Timing GPCM Controlled TRLX 0 or 1 CSNT 1 Figure 16 provides the timing for the external bus controlled by the UPM MPC860 Family Hardware Specifications Rev 7 Freescale Semiconductor 29 Bus Signal Timing CLKOUT A 0 31 CSx BS_AJ0 3 BS _B 0 3 GPL_A0 5 GPL_B 0 5 Ga ee a Le N NI ae Figure 16 External Bus Timing UPM Controlled Signals Figure 17 provides the timing for the asynchronous asserted UPWAIT signal controlled by the UPM MPC860 Family Hardware Specifications Rev 7 30 Freescale Semiconductor Bus Signal Timing CLKOUT UPWAIT BS_AJ0 3 BS_B 0 3 GPL_A 0 5 GPL_B 0 5 Figure 17 Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing Figure 18 provides the timing for the asynchronous negated UPWAIT signal controlled by the UPM CLKOUT UPWAIT BS_AJ0 3 BS_B 0 3 Figure 18 Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing Figure 19 provides the timing for the synchronous external master access controlled by the GPCM MPC860 Family Hardware Specifications Rev 7 Freescale Semiconductor 31 Bus Signal Timing CLKOUT A 0 31 _TSIZ0 1 R W BURST CSx
66. stance between the die and the printed circuit board per JEDEC JESD51 8 Board temperature is measured on the top surface of the board near the package 5 Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method MIL SPEC 883 Method 1012 1 with the cold plate temperature used for the case temperature For exposed pad packages where the pad would be expected to be soldered junction to case thermal resistance is a simulated value from the junction to the exposed pad without contact resistance 8 Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51 2 5 Power Dissipation Table 5 provides power dissipation information The modes are 1 1 where CPU and bus speeds are equal and 2 1 where CPU frequency is twice the bus speed Table 5 Power Dissipation Pp Die Revision Frequency MHz Typical 1 Maximum 2 Unit D 4 50 656 735 mW 1 1 mode 66 TBD TBD mW D 4 66 722 762 mW 2 1 mode 80 851 909 mW 1 Typical power dissipation is measured at 3 3 V 2 Maximum power dissipation is measured at 3 5 V NOTE Values in Table 5 represent Vpp based power dissipation and do not include I O power dissipation over Vppx I O power dissipation varies widely by application due to buffer current depending on external circuitry MPC860 Family Hardware Specifications Rev
67. wn in Figure 66 and Figure 67 Table 25 SPI Slave Timing All Frequencies Num Characteristic Unit Min Max 170 Slave cycle time 2 toye 171 Slave enable lead time 15 ns 172 Slave enable lag time 15 ns 173 Slave clock SPICLK high or low time 1 toye 174 Slave sequential transfer delay does not require deselect 1 toye 175 Slave data setup time inputs 20 ns 176 Slave data hold time inputs 20 ns 177 Slave access time 50 ns MPC860 Family Hardware Specifications Rev 7 CPM Electrical Characteristics Freescale Semiconductor 63 CPM Electrical Characteristics SPISEL Input SPICLK Cl 0 Input SPICLK Cl 1 Input SPIMISO Output SPIMOSI Input Figure 66 SPI Slave CP 0 Timing Diagram MPC860 Family Hardware Specifications Rev 7 64 Freescale Semiconductor CPM Electrical Characteristics SPISEL Input SPICLK Cl 0 Input SPICLK Cl 1 Input SPIMISO Output SPIMOSI Input Figure 67 SPI Slave CP 1 Timing Diagram 11 12I C AC Electrical Specifications Table 26 provides the PC SCL lt 100 kHz timings Table 26 I2C Timing SCL lt 100 kHz All Frequencies Num Characteristic Unit Min Max 200 SCL clock frequency slave 0 100 kHz 200
68. y Hardware Specifications Rev 7 18 Freescale Semiconductor Bus Signal Timing Table 7 Bus Operation Timings continued 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max B35 A 0 31 BADDR 28 30 to CS 5 58 4 25 3 00 1 79 ns valid as requested by control bit BST4 in the corresponding word in UPM B35a A 0 31 BADDR 28 30 andD 0 31 13 15 1050 8 00 5 58 ns to BS valid as requested by control bit BST1 in the corresponding word in UPM B35b A 0 31 BADDR 28 30 andD 0 31 20 73 16 75 13 00 9 36 ns to BS valid as requested by control bit BST2 in the corresponding word in UPM B36 A 0 31 BADDR 28 30 and D 0 31 5 58 4 25 3 00 1 79 ns to GPL valid as requested by control bit GxT4 in the corresponding word in UPM B37 UPWAIT valid to CLKOUT falling 6 00 6 00 6 00 6 00 ns edge 9 B38 CLKOUT falling edge to UPWAIT 1 00 1 00 1 00 1 00 ns valid 9 B39 AS valid to CLKOUT rising edge 1 7 00 7 00 7 00 7 00 ns B40 A 0 31 TSIZ 0 1 RD WR BURST 7 00 7 00 7 00 7 00 ns valid to CLKOUT rising edge B41 TS valid to CLKOUT rising edge 7 00 7 00 7 00 7 00 ns setup time B42 CLKOUT rising edge to TS valid 2 00 2 00 2 00 2 00 ns hold time B4

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