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1 PRODUCT OVERVIEW

1. 4 Doc 500 10b 1 Trpz3 5 MT Figure 19 23 DRAM EDO Page Hit Miss READ Timing Trcdz2 Tcasz2 Tcp ELECTRONICS 19 18 53 44 RISC MICROPROCESSOR ELECTRICAL DATA xeak _ Figure 19 24 DRAM Self Refresh Timing Teas Figure 19 25 DRAM FP EDO Single Write Timing 3 Tcas 2 Tcp 1 4 5 MT 01 10b ELECTRENICS 19 19 ELECTRICAL DATA 53 44 RISC MICROPROCESSOR 000 Tred Q a gt Figure 19 26 DRAM FP EDO Page Hit Miss Write Timing 2 Tcas 2 1 Trp 3 5 MT 01 10b 19 20 ELECTRONICS 53 44 RISC MICROPROCESSOR ELECTRICAL DATA 1905 Figure 19 27 Masked ROM Single READ Timing Tacs 2 Tcosz2 Taccz8 PMC 01 10 11b EXTCLK Tpac NI T 1808 05 05 RDS DATA CERCA Ae gt MEE Ac Figure 19 28 Masked ROM Consecutive READ Timing Tacs 0 Tcos 0 Tacc 3 Tpac 2 PMC 01 10 11b ELECTRONICS 19 21 ELECTRICAL DATA 53 44 RISC MICROPROCESSOR lt a c a a Figure 19 29 SDRAM Single Burst READ Timing Trpz2 Trcdz2 Tcl 2 DW 16bit 19 22 ELECTRONICS 53 44 RISC MICROPROCESSOR ELECTRICAL DATA A10 AP x
2. Rm Single Data Swap Branch and Exchange Rn 1 5 1 Halfword Data Transfer register offset U 1 WIL Offset Offset Halfword Data Transfer immendiate offset aa Tant Undefined m l o o __ Block Data Transfer Offset Branch Opc 1 Ignored by processor Software Interrupt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1211109876543210 Figure 3 1 ARM Instruction Set Format ELECTRONICS 3 1 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR NOTE Some instruction codes are not defined but do not cause the Undefined instruction trap to be taken for instance a Multiply instruction with bit 6 changed to a 1 These instructions should not be used as their action may change in future ARM implementations INSTRUCTION SUMMARY Table 3 1 The ARM Instruction Set Add with carry Rd Rn Op2 Carry R15 address Branch with Link R14 R15 R15 address 20 CPSR flags Rn Exclusive OR Rd Rn AND NOT Op2 OR Op2 AND NOT Rn Load coprocessor from memory Coprocessor load Load multiple registers Stack manipulation Pop Load register from memory Rd address Move CPU register to coprocessor cRn rRn lt op gt cRm register Multiply Accumulate Rd Rm x Rs Rn Move register or constant Rd Op2 3 2 ELECTRONICS 53
3. 00 1 01 29 10 34 11 4 00 1 01 29 10 35 11 44 00 1 01 29 10 34 9 11 47 00 1 01 29 10 34 11 47 NOTE Theitems in PMST must be configured with different priorities even if the corresponding interrupt source is not used 11 18 ELECTRONICS 53 44 RISC MICROPROCESSOR INTERRUPT CONTROLLER CURRENT IRQ PRIORITY OF SLAVE REGISTER CSLV CSLV indicates the current priority status among the sources in each slave group The CSLV may differ from PSLV if the round robin mode is enabled cstv 0 01 00018 Current IRQ priorities of slave register 0x1b1b1b1b sGA EINTO 31 30 00 151 01 2 10 3rd 11 4th sGB EINT1 29 28 00 151 01 2 10 3rd 11 4th 01 sGC EINT2 27 26 00 151 01 2 10 3rd 11 4th sGD EINT3 25 24 00 1st 01 2 10 3rd 11 4th mv at 00 15 01 24 10 39 11 4 00 15 01 2 10 34 11 4 00 1 01 29 10 34 11 4 sGD BDMA1 17 16 00 1 01 29 10 39 11 4 00 15 01 29 10 39 11 4 00 15 01 29 10 34 11 4 00 1 01 24 10 35 11 4 00 15 01 35 _ 40 38 1124 00 15 01 29 10 39 11 4 20000 00 44 01229 4090 114 00 15 01 24 10 3 11 4 00 15 01 29 10 34 11 4 ELECTRONICS 11 19 INTERRUPT CONTROLLER 53 44 RISC MICROPROCESSOR CURRENT IRQ PRIORITY OF MASTER REGISTER CMST CMST indicates the current priority status among the slave groups C
4. om ojo 2 25 26 k phbsu50ct12sm 1 12 ELECTRONICS 53 44 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 1 160 Pin LQFP Pin Assignment Concluded Default State State State TYPE Function BUS REQ STOP lnitial Hi z Hi z 2 phbsu50ct12sm ADDR15 ADDR15 z 2 ADDR14 ADDR14 ADDR13 ADDR13 ADDR12 ADDR12 VSSIO 880 vss3op ELECTRONICS 1 13 PRODUCT OVERVIEW 53 44 RISC MICROPROCESSOR Table 1 2 160 Pin FBGA Pin Assignment s s s ne no 11 T 85 mom I mms 5 1 14 ELECTRONICS 53 44 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 2 160 Pin FBGA Pin Assignment Continued 2 2 2 2 ELECTRONICS 1 15 PRODUCT OVERVIEW 53 44 RISC MICROPROCESSOR Table 1 2 160 Pin FBGA Pin Assignment Continued esr joe 3 TCK 5 2 1 Sonoman NOTES 1 ON 3 0 and ENDIAN value are latched only at the rising edge of nRESET Therefore when nRESET is L the pins of OM 3 0 ENDIAN are in input state After nRESET becomes the pin of ENDIAN will be in output state 2 The QBUS REQ shows
5. 5 18 _ 0 Service available INT URXDO 0 Service available INT URXD1 B 0 Service available INT 0 Service available INT SIO 0 Service available INT UTXDO 0 Service available INT UTXD1 0 Service available INT RTC 0 Service available INT ADC 0 Service available ELECTRONICS 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 1 1 1 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 1 Masked 11 14 53 44 RISC MICROPROCESSOR INTERRUPT CONTROLLER IRQ VECTORED MODE REGISTERS The priority generating block consists of five units 1 master unit and 4 slave units Each slave priority generating unit manages six interrupt sources The master priority generating unit manages 4 slave units and 2 interrupt sources Each slave unit has 4 programmable priority source sGn and 2 fixed priority sources kn The priority among the 4 sources in each slave unit is determined the PSLV register The other 2 fixed priorities have the lowest priority among the 6 sources The master priority generating unit determines the priority between 4 slave units and 2 interrupt sources using the register 2 interrupt sources INT and have the lowest priority among the 26 interrupt sources If several interrupts a
6. 2 ADD 3 SUB Figure 3 32 Format 3 OPERATIONS The instructions in this group perform operations between a Lo register and an 8 bit immediate value The THUMB assembler syntax is shown in Table 3 10 NOTE All instructions in this group set the CPSR condition codes Table 3 10 Summary of Format 3 Instructions 00 MOV Rd fOffset8 MOVS sOffset8 Move 8 bit immediate value into Rd 01 CMP Rd Offset8 CMP Offset8 Compare contents of Rd with 8 bit immediate value 10 ADD Offset8 ADDS Rd Offset8 Add 8 bit immediate value to contents of Rd and place the result in Rd 11 SUB Rad Offset8 SUBS Rd Offset8 Subtract 8 bit immediate value from contents of Rd and place the result in Rd 3 72 ELECTRONICS 53 44 RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES ARM INSTRUCTION SET All instructions in this format have an equivalent ARM instruction as shown in Table 3 10 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES MOV CMP ADD SUB ELECTRONICS RO 128 R2 62 R1 255 R6 145 RO 128 and set condition codes Set condition codes on R2 62 R1 R1 255 and set condition codes R6 R6 145 and set condition codes 3 73 ARM INSTRUCTION SET S3C44B0X RISC MICROPROCESSOR FORMAT 4 ALU OPERATIONS 15 11 10 9 6 5 3 2 0 14 13 12 2
7. 0 Disable 1 Enable Second alarm enable 0 Disable 1 Enable ELECTRONICS 14 5 REAL TIME CLOCK 53 44 RISC MICROPROCESSOR ALARM SECOND DATA REGISTER ALMSEC ALMSEC 0x01D70054 L R W Alarm second data Register 0x00 0x01D70057 B by byte SECDATA 6 4 BCD value for alarm second 0105 ALARM MIN DATA REGISTER ALMMIN ALMMIN 0x01D70058 L R W minute data Register 0x00 0x01D7005B B by byte 4 6 4 BCD value for alarm minute from 0 to 5 a ao ALARM HOUR DATA REGISTER ALMHOUR ALMHOUR 0x01D7005C L R W Alarm hour data Register 0x00 0x01D7005F B by byte 74 HOURDATA 5 4 sa value for alarm hour from 0 to 2 ao 14 6 53 44 RISC MICROPROCESSOR REAL TIME CLOCK ALARM DAY DATA REGISTER ALMDAY ALMDAY 0x01D70060 L R W Alarm day data Register 0x01 0x01D70063 B by byte 2212 1727 DAYDATA 5 4 BCD value for alarm day from 0 to 28 29 30 31 from 0 to 3 ar mmoms ALARM MON DATA REGISTER ALMMON ALMMON 0x01D70064 L R W Alarm month data Register 0x01 0x01D70067 B by byte rs MONDATA n value for alarm month from 0 to 1 a ALARM YEAR DATA REGISTER ALMYEAR ALMYEAR 0x01D70068 L R W Alarm year data Register 0x00 0x01D7006B B by byte YEARDATA 7 0 BCD value for year 0x00 from 00 to 99 ELECTRONICS 14 7 REAL TIME CL
8. LCD CONTROL UNIT ora o cowme 02 wemwe 0 of the row and col volage _ 002 TIMER PWM meo 7 eean INTERRUPT CONTROL UNIT EINT 7 0 External Interrupt request nXDREQ 1 0 External DMA request 0 External DMA acknowledge UART RxD 1 0 E UART receives data input 1 UART aar o sonansa 2 UART request sera ouput signal y IIC BUS IISLRCK o 115 channel select clock IISDO lo IIS bus serial data output 150 EN 15 serial data input IISCLK IIS bus serial clock CODECLK CODEC system clock SIORXD SIOTXD SIOCK SIORDY SIO receives data input SIO transmits data output SIO clock SIO handshake signal when DMA completes the SIO operation d ELECTRENICE 1 19 PRODUCT OVERVIEW 53 44 RISC MICROPROCESSOR Table 1 3 53 44 Signal Descriptions Continued swa v ADC GENERAL PORT P 70 0 o General input output ports some ports are output mode only RESET amp CLOCK nRESET ST nRESET suspends any operation in progress and places S3C44BOX into a known reset state For a reset nRESET must be held to L level for at least 4 MCLK after the processor power has been stabilized 3 2 3 2 determines how the clock is made 00 Crystal XTALO
9. 000000 lt destination address gt lt vector address gt 0x8 gt gt 2 For example if Timer 0 interrupt to be processed in vector interrupt mode the branch instruction which jumps to the ISR is located at 0 00000060 The ISR start address is 0x10000 The following 32bit machine code is written at 0x00000060 machine code 20x00000060 0 000000 0 10000 0 60 0 8 gt gt 2 0xea000000 0x3fe6 003 The machine code is usually generated automatically by the assembler and therefore the machine code does not have to be calculated as above ELECTRONICS 11 5 INTERRUPT CONTROLLER 53 44 RISC MICROPROCESSOR 11 6 ELECTRONICS 53 44 RISC MICROPROCESSOR INTERRUPT CONTROLLER EXAMPLE OF VECTORED INTERRUPT MODE In the vectored interrupt mode CPU will branch to each interrupt address when an interrupt request is generated So there must be the branch instruction to jump each corresponding ISR on it s own address as follows ENTRY b ResetHandler 0x00 b HandlerUndef 0x04 b HandlerSWI 0x08 b HandlerPabort 0 0 b HandlerDabort 0x10 b 0x14 b HandlerlRQ 0x18 b HandlerFIQ Oxic Idr pc HandlerEINTO 0x20 pc HandlerEINT1 pc HandlerEINT2 pc HandlerEINT3 Idr pc HandlerEINT4567 Idr pc HandlerTICK 0x34 b b Idr pc HandlerZDMAO 0x40 Idr pc HandlerZDMA1 Idr pc HandlerBDMAO Idr pc HandlerBDMA1 Idr pc HandlerWDT Idr pc Handle
10. 2bit 1pixel x 80Hz x 1byte 861 512Kbyte Transmission cycle per 1 Transmission clock per 4word 16 Transmission clock 4word Trp 2clk 2 C L 2clk Burst cycle 8clk 14clk System load system bus occupation 448KHz 66MHz 0 68 NOTE The higher the system load is the lower the CPU performance is Example 2 Virtual screen register 4 level gray 4 bit single scan display Vertual screen size 1024 x 1024 LCD size 320 x 240 LCDBASEU 0x64 1 half word 8 pixels 4 level gray Virtual screen 1 line 128 half word 1024 pixels LCD 1 line 320 pixels 40 half word OFFSIZE 128 40 88 0x58 PAGEWIDTH 40 0x28 LCDBASEL LCDBASEU PAGEWIDTH OFFSIZE x LINEVAL 1 100 40 88 x 240 64 12 26 ELECTRONICS 53 44 RISC MICROPROCESSOR LCD CONTROLLER Gray Level Selection Guide S3C44BOX LCD controller can generate 16 gray level using FRC frame rate control The FRC characteristics cause unexpected patterns in gray level These unwanted erronous patterns may be shown in fast response LCD or at lower frame rates Because the quality of LCD gray levels depends on LCD s own characteristics the user may have to select the good gray levels after viewing all gray levels on user s own LCD Please select the gray level quality through the following procedures 1 Get the latest dithering pattern register value from SAMSUNG
11. HZD HZD HZD c HZD HZ XnBROS amp XnBRQH XnBREQ Y XnBACK tXnBACKD Figure 19 30 External Bus Request SDRAM Timing 2 Trcd 2 Tcl 2 079 ELECTRENICS 19 23 ELECTRICAL DATA 53 44 RISC MICROPROCESSOR ADDR BA A10 AP Figure 19 31 SDRAM MRS Timing 19 24 ELECTRONICS 53 44 RISC MICROPROCESSOR ELECTRICAL DATA ISAD ADDR BA A10 AP tSCSD Figure 19 32 SDRAM Single READ Trpz2 Trcdz2 Tcl 2 ELECTRENICS 19 25 ELECTRICAL DATA 53 44 RISC MICROPROCESSOR ADDR BA A10 AP lt 1505 tSDH 4 Figure 19 33 SDRAM Single READ Timing Il Trp 2 Trcdz2 Tcl 3 19 26 ELECTRONICS 53 44 RISC MICROPROCESSOR ELECTRICAL DATA ADDR BA A10 AP Before executing auto self refresh command all banks must be idle state Figure 19 34 SDRAM Auto Refresh Timing Trp 2 Trc 4 ELECTRONICS 19 27 53 44 RISC MICROPROCESSOR ELECTRICAL DATA c Has 5051 0 dV OLV 8705 1195 2 Figure 19 35 SDRAM Page Hit Miss READ Timing Trp 2 Trcd 2 Tcl ELECTRONICS 19 28 53 44 RISC MICROPROCESSOR ELECTRICAL DATA iCKED ES SAD gt i ADDRIBA TEE A10 AP tSCSD tscsb gt gt gt gt
12. Note that the THUMB opcode will contain 26asthe Word7 value and S 1 ELECTRONICS 3 93 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR FORMAT 14 PUSH POP REGISTERS 11 7 0 Register List 8 PC LR Bit 0 Do not store LR Load PC 1 Store LR Load PC 11 Load Store Bit 0 Store to memory 1 Load from memory Figure 3 43 Format 14 OPERATION The instructions in this group allow registers 0 7 and optionally LR to be pushed onto the stack and registers 0 7 and optionally PC to be popped off the stack The THUMB assembler syntax is shown in Table 3 21 NOTE The stack is always assumed to be Full Descending Table 3 21 PUSH and POP Instructions B THUMB assembler ARM equivalent PUSH Rlist STMDB R13 Rlist the registers specified by Rlist onto the stack Update the stack pointer PUSH Rlist LR STMDB R13 Push the Link Register and the registers Rlist R14 specified by Rlist if any onto the stack Update the stack pointer 1 POP RIist LDMIA R13 Rlist Pop values off the stack into the registers specified by Rlist Update the stack pointer 1 1 POP Rlist PC LDMIA R13 Rlist R15 Pop values off the stack and load into the registers specified by Rlist Pop the PC off the stack Update the stack pointer 3 94 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET INSTRUCTION CYCLE TIMES All instruction
13. 53 44 has five power down modes The following section describes each power managing mode The transition between the modes is not allowed freely For available transitions among the modes please refer to Figure 5 11 Normal Mode In normal mode all peripherals UART DMA Timer and so and the basic blocks CPU core bus controller memory controller interrupt controller and power management block may operate fully But the clock to each peripheral except the basic blocks can be stopped selectively by S W to reduce power consumption NOTE The basic blocks consist of the CPU core bus controller memory controller interrupt controller and power management IDLE Mode In IDLE mode the clock to CPU core is stopped except bus controller memory controller interrupt controller and power management block To exit IDLE mode EINT 7 0 or RTC alarm interrupt or the other interrupts should be activated If users are willing to use EINT 7 0 GPIO block has to be turned on before the activation STOP Mode In STOP mode all clocks are stopped for minimum power consumption Therefore the PLL and oscillator circuit are also stopped Just after exiting the STOP mode only THAW mode is available In other words the user can not return to NORMAL mode from STOP mode as shown in Fig 5 11 directly To exit from STOP mode EINT 7 0 or RTC alarm interrupt has to be activated Just after entering into the STOP mode the Clock Con
14. Divide result in Rc remainder Ra 3 to 6 cycles 1 cycle and a register 3 to 6 cycles 1 cycle and a register 3 Overflow in unsigned multiply accumulate with a 32 bit result UMLAL TEQ BNE Rd Rt Rm Rn Rt 0 overflow 4 to 7 cycles 1 cycle and a register 4 Overflow in signed multiply accumulate with a 32 bit result SMLAL TEQ BNE 3 60 Rd Rt Rm Rn Rt Rd ASR 31 overflow 4 to 7 cycles 1 cycle and a register ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET 5 Overflow in unsigned multiply accumulate with a 64 bit result UMULL RI Rh Rm Rn 3to6 cycles ADDS RI RI Ra1 Lower accumulate ADC Rh Rh Ra2 Upper accumulate BCS overflow 1 cycle and 2 registers 6 Overflow in signed multiply accumulate with a 64 bit result SMULL RI Rh Rm Rn 3106 cycles ADDS RI RI Ra1 Lower accumulate ADC Rh Rh Ra2 Upper accumulate BVS overflow 1 cycle and 2 registers NOTE Overflow checking is not applicable to unsigned and signed multiplies with a 64 bit result since overflow does not occur in such calculations PSEUDO RANDOM BINARY SEQUENCE GENERATOR It is often necessary to generate pseudo random numbers and the most efficient algorithms are based on shift generators with exclusive OR feedback rather like a cyclic redundancy check generator Unfortunately the sequence of a 32 bit generator needs more than one feedback tap to be maximal length i e 2 32 1 cycles before repetiti
15. EOR with 1 OxFFFFFFFF if negative SUB 83 RO R2 and ADD 1 SUB 1 to get abs value SUB always sets flag so go amp report division by 0 if necessary BEQ divide by zero abs value of R1 by xoring with OxFFFFFFFF and adding 1 if negative ASR RO R1 31 Get 0 or 1 in R3 depending on sign of R1 EOR R1 RO EOR with 1 OxFFFFFFFF if negative SUB R1 RO and ADD 1 SUB 1 to get abs value signs 0 or 1 in RO R2 for later use in determining sign of quotient amp remainder PUSH RO R2 Justification shift 1 bit at a time until divisor RO value is just lt than dividend R1 value To do this shift dividend right by 1 and stop as soon as shifted value becomes LSR RO R1 1 MOV R2 R3 B FTO just_l LSL R2 1 0 CMP R2 RO BLS just_l MOV RO 0 Set accumulator to 0 B FTO Branch into division loop 1 LSR R2 1 0 CMP R1 R2 Test subtract BCC FTO SUB R1 R2 successful do a real subtract 0 ADC RO RO Shift result and add 1 if subtract succeeded CMP R2 R3 Terminate when R2 R3 ie we have just BNE div_ tested subtracting the value 3 104 ELECTRONICS 53 44 RISC MICROPROCESSOR Now fix up the signs of the quotient RO POP EOR EOR SUB EOR SUB MOV ARM Code signed_divide ANDS RSBMI EORS bit 31 sign of result bit 30 sign of a2 RSBCS R2 R3 R3 R2 RO RO R3 R1 R2 R1 R2 Ir a4 a1
16. Figure 2 6 Program Status Register Format ELECTRONICS 2 7 PROGRAMMER S MODEL 53 44 RISC MICROPROCESSOR The Condition Code Flags The N Z C and V bits are the condition code flags These may be changed as a result of arithmetic and logical operations and may be tested to determine whether an instruction should be executed In ARM state all instructions may be executed conditionally see Table 3 2 for details In THUMB state only the Branch instruction is capable of conditional execution see Figure 3 46 for details The Control Bits The bottom 8 bits of a PSR incorporating F T and M 4 0 are known collectively as the control bits These will be changed when an exception arises If the processor is operating in a privileged mode they can also be manipulated by software The T bit This reflects the operating state When this bit is set the processor is executing in THUMB state otherwise it is executing in ARM state This is reflected on the TBIT external signal Note that the software must never change the state of the TBIT in the CPSR If this happens the processor will enter an unpredictable state Interrupt disable bits The and F bits are the interrupt disable bits When set these disable the IRQ and interrupts respectively The mode bits The M3 M2 M1 and bits M 4 0 are the mode bits These determine the processor s operating mode as shown in Table 2 1 Not all combinations of the mode
17. Figure 5 9 The Case that Exit_from_Slow_Mode Command is Issued after Lock Time is End 5 10 53 44 RISC MICROPROCESSOR CLOCK amp POWER MANAGEMENT If users exit from SLOW mode to Normal mode by disabling SLOW mode bit and PLL off bit simultaneously in CLKSLOW register the frequency is changed just after the PLL lock time The timing diagram is as follow H W lock time PLL_CLK Slow bit Slow mode enable Slow mode disable PLL off PLL off on FOUT Divided It changes to PLL clock OSC clock after lock time automatically Figure 5 10 The Case that Exit from Slow Mode Command is Issued the Instant PLL on Command is Issued Wake Up amp THAW State When the S3C44B0X is woken up from power down mode STOP mode by an EINT 7 0 or a RTC alarm interrupt the processor state will be changed into THAW state as shown in Figure 5 11 In thaw state the configuration of the CLKCON should be ignored because the CLKCON value which had been set before the entrance to stop mode can not reflect the actual processor state After the wake up from STOP mode the processor is in THAW mode as explained above The new value which reflects the new state has to be re written into the CLKCON register Eventually the processor state will be changed from THAW state to Normal or SLOW or even STOP mode Just after writing the valid configuration value into the CLKCON the mode return
18. ISRD 4580 Aer Trp n E icu NOTE Before executing auto self refresh command all banks must be idle state Figure 19 36 SDRAM Self Refresh Timing Trpz2 Trcz4 ELECTRENICS 19 29 ELECTRICAL DATA 53 44 RISC MICROPROCESSOR ADDR BA A10 AP Figure 19 37 SDRAM Single Write Timing Trp 2 Trcd 2 19 30 ELECTRONICS ELECTRICAL DATA 53 44 RISC MICROPROCESSOR vga rdaav 2 2 Figure 19 38 SDRAM Page Hit Miss Write Timing Trpz2 Trcd 19 31 ELECTRENICS ELECTRICAL DATA 53 44 RISC MICROPROCESSOR XnDREQ XnDACK XnDREQ XnDACK Figure 19 40 External DMA Timing Handshake Unit transfer Block mode XnDREQ XnDACK Figure 19 41 External DMA Timing Handshake On The Fly mode 19 32 ELECTRONICS 53 44 RISC MICROPROCESSOR ELECTRICAL DATA XnDREQ XnDACK Figure 19 42 External DMA Timing Single Step Unit Block On the fly mode 1 XnDREQ XnDACK Figure 19 43 External DMA Timing Single Step Unit Block On the fly mode II XnDREQ XnDACK Figure 19 44 External DMA Timing Single Step Unit Block On the fly mode 111 ELECTRENICS 19 33 ELECTRICAL DATA 53 44 RISC MICROPROCESSOR XnDREQ XnDACK 1WAD tACCR AACCW Figure 19 45 External DMA Timing Demand On The Fly mode XnDREQ XnDACK IACCR AACCW tWADIACCRAACCW Figure 19 46 Ex
19. The minimum non cacheable area is 4Kbytes SA1 Start address 4K ELECTRENICS 6 9 CPU WRAPPER amp BUS PRIORITIES 53 44 RISC MICROPROCESSOR BUS PRIORITY SPECIAL REGISTER SYSTEM BUS PRIORITY CONTROLLER SBUSCON SBUSCON 0x01C40000 Determines the bus priorities among the bus masters 0x80001B1B 31 0 round robin priorities 1 fixed priorities S LCD DMA 15 14 Indicates the LCD bus priority read only 00 1st 01 2nd 10 3rd 11 4th S_ZDMA 13 12 Indicates the ZDMA bus priority read only 00 1st 01 2nd 10 3rd 11 4th S_BDMA 11 10 Indicates the BDMA bus priority read only 00 1st 01 2 10 3rd 11 4th S nBREQ Indicates the nBREQ bus priority read only 11 00 1st 01 2nd 10 11 4th LCD_DMA 7 6 Determines the LCD_DMA bus priority 00 1st 01 2nd 10 3rd 11 4th ZDMA 5 4 Determines the ZDMA bus priority 01 00 1st 01 2nd 10 3rd 11 4th BDMA 3 2 Determines the BDMA bus priority 00 1st 01 2nd 10 3rd 11 4th nBREQ 1 0 Determines the nBREQ bus priority 00 1st 01 2 10 3rd 11 4th NOTE The priorities are only valid in the fixed priority mode 6 10 ELECTRONICS 53 44 RISC MICROPROCESSOR DMA DMA OVERVIEW The S3CA4BOX has 4 channel DMA Controllers The two DMAs we call it ZDMA General DMA are attached to SSB Samsung System Bus and the other two DMAs we call it as BDMA Bridge DMA are inside the bridge which is an interface layer between SSB a
20. 0 0102004 Special Pull up register 2 0 0 4 Table 8 9 D 15 0 Pull up Control Register SPUCR HZ STOP 0 Previous state of PAD 1 HZ stop SPUCR1 1 0 DATA 15 8 port pull up resistor is enabled 1 DATA 15 8 port pull up resistor is disabled SPUCRO 0 7 0 port pull up resistor is enabled 1 DATA 7 0 port pull up resistor is disabled 8 14 ELECTRENICS 53 44 RISC MICROPROCESSOR PORTS EXTINT EXTERNAL INTERRUPT CONTROL REGISTER The 8 external interrupts can be requested by various signaling methods The EXTINT register configures the signaling method between the level trigger and edge trigger for the external interrupt request and also configures the signal polarity EXTINT 0x01D20050 External Interrupt control Register 0x000000 Table 8 10 External Interrupt Control Register EXTINT EINT7 28 Setting the signaling method of the EINT7 000 Low level interrupt 001 High level interrupt 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered EINT6 26 24 Setting the signaling method of the EINT6 000 Low level interrupt 001 High level interrupt 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered EINT5 22 20 Setting the signaling method of the EINT5 000 Low level interrupt 001 High level interrupt 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered EINT4 18 16 Setti
21. 31 28 Condition Field Figure 3 27 Coprocessor Register Transfer Instructions THE COPROCESSOR FIELDS The CP field is used as for all coprocessor instructions to specify which coprocessor is being called upon The CP Opc CRn CP and CRm fields are used only by the coprocessor and the interpretation presented here is derived from convention only Other interpretations are allowed where the coprocessor functionality is incompatible with this one The conventional interpretation is that the CP Opc and CP fields specify the operation the coprocessor is required to perform CRn is the coprocessor register which is the source or destination of the transferred information and CRm is a second coprocessor register which may be involved in some way which depends on the particular operation specified 3 56 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET TRANSFERS TO R15 When a coprocessor register transfer to ARM7TDMI has R15 as the destination bits 31 30 29 and 28 of the transferred word are copied into the N Z C and V flags respectively The other bits of the transferred word are ignored and the PC and other CPSR bits are unaffected by the transfer TRANSFERS FROM R15 A coprocessor register transfer from ARM7TDMI with R15 as the source register will store the PC 12 INSTRUCTION CYCLE TIMES MRC instructions take 15 6 1 1 1C incremental cycles to execute where S and are defined as sequential S cycle
22. 4 SUBS PC R14 irq 4 SUBS PC R14_abt 4 SUBS PC R14_abt 8 NA A A NOTES 1 Where is the address of the BL SWI Undefined Instruction fetch which had the prefetch abort 2 Where is the address of the instruction which did not get executed since the or IRQ took priority 3 Where PC is the address of the Load or Store instruction which generated the data abort 4 The value saved in R14_svc upon reset is unpredictable FIQ The FIQ Fast Interrupt Request exception is designed to support a data transfer or channel process and in state has sufficient private registers to remove the need for register saving thus minimising the overhead of context switching FIQ is externally generated by taking the nFIQ input LOW This input can except either synchronous or asynchronous transitions depending on the state of the ISYNC input signal When ISYNC is LOW nFIQ and nIRQ are considered asynchronous and a cycle delay for synchronization is incurred before the interrupt can affect the processor flow Irrespective of whether the exception was entered from ARM or Thumb state a FIQ handler should leave the interrupt by executing SUBS PC R14_fiq 4 FIQ may be disabled by setting the CPSR s F flag but note that this is not possible from User mode If the F flag is clear ARM7TDMI checks for a LOW level on the output of the FIQ synchroniser at the end of each instruction ELECTRONICS 2
23. 44 RISC MICROPROCESSOR ARM INSTRUCTION SET Table 3 1 The ARM Instruction Set Continued Move from coprocessor register to Rn cRn lt op gt cRm CPU register Joa _____________ 00000 RSB SBC STC STM Stack manipulation Push STR SWP TEQ ELECTRONICS 3 3 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR THE CONDITION FIELD In ARM state all instructions are conditionally executed according to the state of the CPSR condition codes and the instruction s condition field This field bits 31 28 determines the circumstances under which an instruction is to be executed If the state of the C N Z and V flags fulfils the conditions encoded by the field the instruction is executed otherwise it is ignored There are sixteen possible conditions each represented by a two character suffix that can be appended to the instruction s mnemonic For example a Branch B in assembly language becomes BEQ for Branch if Equal which means the Branch will only be taken if the Z flag is set In practice fifteen different conditions may be used these are listed in Table 3 2 The sixteenth 1111 is reserved and must not be used In the absence of a suffix the condition field of most instructions is set to Always suffix AL This means the instruction will always be executed regardless of the CPSR condition codes Table 3 2 Condition Code Summary Fas ig
24. 53 44 RISC MICROPROCESSOR PORTS Table 8 1 53 44 Port Configuration Overview Continued Selectable Pin functions Input output DATA18 IISDI Input output DATA17 IISDO Input output DATA16 IISLRCK Selectable Pin functions me muepa 1 1 2 m mue ELECTRENICS 8 3 PORTS 3C44B0X RISC MICROPROCESSOR Table 8 1 53 44 Port Configuration Overview Continued Selectable Pin functions Selectable Pin functions eee ee ee Selectable Pin Functions input NOTES P 8 4 ELECTRONICS 53 44 RISC MICROPROCESSOR PORTS 1 The underlined function name is selected just after a reset ENDIAN PE8 is used only when nRESET is L 2 IICSDA and pins are open drain pin So this pin needs pull up resistors when used as output port PF 1 0 PORT CONTROL DESCRIPTIONS PORT CONFIGURATION REGISTER PCONA G In S3C44BOX most pins are multiplexed pins Therefore the functions for each pin should be selected The PCONn port control register determines which function is used for each pin If PGO PG7 are used for the wakeup signal in power down mode these ports must be configured in interrupt mode PORT DATA REGISTER PDATA G If these ports are configured as output ports data can be written to the corresponding bit of PDATn If Ports are configured as input ports the data can be r
25. Bit Description Initial state state DP3 4 15 0 Recommended pattern value Ox7dbe 0111 1101 1011 1110 Ox7dbe ELECTRONICS 12 23 LCD CONTROLLER 53 44 RISC MICROPROCESSOR Dithering Pattern DP4_5 Register DP4_5 0x01F00038 R W Dithering pattern duty 4 5 register Ox7ebdf Please refer to a sample program source for the latest value of this register 5 Bit Description Initial state state 5 19 0 Recommended pattern value Ox7ebdf 0111 1110 1011 1101 1111 Ox7ebdf Dithering Pattern DP6 7 Register DP6 7 0 01 0003 R W Dithering pattern duty 6 7 register Ox7fdfbfe Please refer to a sample program source for the latest value of this register 0267 7 Description initial state state DP6 7 0 Recommended pattern value Ox7fdfbfe 0111 1111 1101 1111 1011 1111 1110 Ox7fdfbfe Mode Register E 0x01F00044 Dithering Mode Register 0x00000 This register reset value is 0 00000 But users will have to change this value to 0x12210 Please refer to a sample program source for the latest value of this register DP8 9 Bit Description initial state DITHMODE 18 0 Use one of following value for your LCD 0x00000 0x12210 or 0 0 12 24 ELECTRONICS 53 44 RISC MICROPROCESSOR LCD CONTROLLER Register Setting Guide The maximum VCLK frequency of the LCD controller is 16 5MHz whenever system clock frequency is 66 MHz therefore the LCD controller sup
26. CODE16 Into_THUMB ADR R5 Back to ARM BX R5 ALIGN CODE32 Back to 53 44 RISC MICROPROCESSOR Generate branch target address and set bit 0 high hence arrive in THUMB state Branch and change to THUMB state Assemble subsequent code as THUMB instructions Generate branch target to word aligned address hence bit 0 is low and so change back to ARM state Branch and change back to ARM state Word align Assemble subsequent code as ARM instructions ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET BRANCH AND BRANCH WITH LINK B BL The instruction is only executed if the condition is true The various conditions are defined Table 3 2 The instruction encoding is shown in Figure 3 3 below 31 28 27 252423 0 e 24 Link bit 0 Branch 1 Branch with link 31 28 Condition Field Figure 3 3 Branch Instructions Branch instructions contain a signed 2 s complement 24 bit offset This is shifted left two bits sign extended to 32 bits and added to the PC The instruction can therefore specify a branch of 32Mbytes The branch offset must take account of the prefetch operation which causes the PC to be 2 words 8 bytes ahead of the current instruction Branches beyond 32Mbytes must use an offset or absolute destination which has been previously loaded into a register In this case the PC should be manually saved in R14 if a Branch
27. HALFWORD AND SIGNED DATA TRANSFER LDRH STRH LDRSB LDRSH The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 16 These instructions are used to load or store half words of data and also load sign extended bytes or half words of data The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register The result of this calculation may be written back into the base register if auto indexing is required 28 27 25 24 23 22 21 20 19 16 15 12 11 876543 Des Dom Do 3 0 Offset Register 6 5 S H 0 0 SWP instruction 0 1 Unsigned halfword 1 1 byte 1 1 Signed halfword 15 12 Source Destination Register 19 16 Base Register 20 Load Store 0 Store to memory 1 Load from memory 21 Write back 0 No write back 1 Write address into base 23 Up Down 0 Down subtract offset from base 1 Up add offset to base 24 Pre Post Indexing 0 Post add subtract offset after transfer 1 Pre add subtract offset bofore transfer 31 28 Condition Field Figure 3 16 Halfword and Signed Data Transfer with Register Offset 3 34 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET 28 27 25 24 23 22 21 20 19 16 15 12 11 8 7 6 5 4 3 Lu Dom Dee DIPL 3 0 Immediate Offset Low Nibble 6
28. IISCON ISCON 0x01D18000 Li HW Bi W R W 15 control register 0x100 0x01D18002 Bi HW Left Right channel 0 Left channel 1 index read only 1 Right channel Transmit FIFO ready 7 0 FIFO is not ready empty flag read only 1 FIFO is ready not empty Receive FIFO ready 0 FIFO is not ready full flag read only 1 FIFO is ready not full Transmit DMA service 0 Request disable request enable 1 Request enable Receive DMA service request enable 0 Request disable 1 Request enable In Idle state the IISLRCK is inactive pause Rx This bit is only effective if the IIS is a master 0 IISLRCK is generated 1 IISLRCK is not generated IIS prescaler enable 0 Prescaler disable 1 Prescaler enable IIS interface enable 0 IIS disable stop start 1 15 enable start NOTES 1 ThellSCON register can be accessed by halfword and word unit using STRH STR and LDRH LDR instructions or char short int int type pointer in Little Big endian mode 2 Li HW W Access by halfword word unit when the endian mode is Little Bi HW W Access by halfword word unit when the endian mode is Big Receive channel idle command 5 1 NE Transmit channel idle 3 In Idle state the IISLRCK is inactive pause Tx This bit is only command effective if the IIS is a master 0 IISLRCK is generated 1 IISLRCK is not generated mE ELECTRENICE 17 5 IIS BUS INTERFACE 53 44 RISC MIC
29. Move R14 LR into R15 PC but don t set the condition codes eg return from subroutine Switch from THUMB to ARM state Load address of outof THUMB into R1 Transfer the contents of R11 into the PC Bit 0 of R11 determines whether ARM or THUMB state is entered ie ARM state here Now processing ARM instructions If R15 is used as an operand the value will be the address of the instruction 4 with bit 0 cleared Executing a BX PC in THUMB state from a non word aligned address will result in unpredictable execution 3 78 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET FORMAT 6 PC RELATIVE LOAD 15 14 13 7 0 12 11 10 8 2 7 0 Immediate Value 10 8 Destination Register Figure 3 35 Format 6 OPERATION This instruction loads a word from an address specified as a 10 bit immediate offset from the PC The THUMB assembler syntax is shown below Table 3 13 Summary of PC Relative Load Instruction THUMB assembler ARM equivalent LDR Rd PC lmm LDR Rd R15 Add unsigned offset 255 words 1020 bytes in Imm to the current value of the PC Load the word from the resulting address into Rd NOTE The value specified by lmm is a full 10 bit address but must always be word aligned ie with bits 1 0 set to 0 since the assembler places 1 gt gt 2 in field Word 8 The value of the PC will be 4 bytes greater than the address of thi
30. RISC MICROPROCESSOR BCD MONTH REGISTER BCDMON BCDMON 0x01D70084 L R W BCD month Register Undef 0x01D70087 B by byte _ MONDATA BCD value for month 0 10 1 rom oo 9 BCD YEAR REGISTER BCDYEAR BCDYEAR 0x01D70088 L R W BCD year Register Undef 0x01D7008B B by byte YEARDATA 7 0 BCD value for year from 00 to 99 TICK TIME COUNT REGISTER TICNT TICNT 0x01D7008C L R W Tick time count Register 0x00000000 0x01D7008F B by byte TICK INT ENABLE 7 Tick time interrupt enable 0 disable 1 enable TICK TIME COUNT Tick time count value 1 127 000000 This counter value decreases internally and users can not read this real counter value in working 14 10 53 44 RISC MICROPROCESSOR WATCHDOG TIMER WATCHDOG TIMER OVERVIEW The 53 44 watchdog timer is used to resume the controller operation when it had been disturbed by malfunctions such as noise and system errors It can be used as a normal 16 bit interval timer to request interrupt service The watchdog timer generates the reset signal for 128 MCLK cycles FEATURES Normal interval timer mode with interrupt request Internal reset signal is activated for 128 MCLK cycles when the timer count value reaches 0 time out ELECTRONICS 15 1 WATCHDOG TIMER S3C44BOX RISC MICROPROCESSOR WATCHDOG TIMER OPERATION The functional block diagram of the watchdog timer is shown in Figu
31. THUMB assembler ARM equivalent Action 1001 BLS label BLS label Branch if C clear or Z set unsigned lower or same 1010 BGE label BGE label Branch if N set and V set or N clear and V clear greater or equal 1011 BLT label BLT label Branch if N set and V clear or N clear and V set less than 1100 BGT label BGT label Branch if Z clear and either N set and V set or N clear and V clear greater than 1101 BLE label BLE label Branch if Z set or N set and V clear or N clear and V set less than or equal NOTES 1 While label specifies a full 9 bit two s complement address this must always be halfword aligned ie with bit 0 set to 0 since the assembler actually places label gt gt 1 in field SOffset8 2 Cond 1110 is undefined and should not be used Cond 1111 creates the SWI instruction see INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 23 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES CMP 45 Branch to over if RO gt 45 BGT over Note that the THUMB opcode will contain the number of halfwords to offset over Must be halfword aligned 3 98 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET FORMAT 17 SOFTWARE INTERRUPT 15 14 13 11 10 7 0 12 9 8 vaes y 7 0 Comment Field Figure 3
32. These bits define the rate at which the VM signal will toggle if 0x00 the MMODE bit is set to logic 1 LCDBASEL 20 0 These bits indicate A 21 1 of the start address of the lower 0x0000 address counter which is used for the lower frame memory of dual scan LCD LCDBASEL LCDBASEU PAGEWIDTH OFFSIZE x LINEVAL 1 NOTE Users can change the LCDBASEU and LCDBASEL values for scrolling while LCD controller is turned on But users must not change the LCDBASEU and LCDBASEL registers at the end of FRAME by referring to the LINECNT field in LCDCON 1 register Because of the LCD FIFO fetches the next frame data prior to the change the frame So if you change the frame the pre fetched FIFO data will be obsolete and LCD controller will display the incorrect screen To check the LINECNT interrutpt should be masked If any interrupt is executed just after reading LINECNT the read LINECNT value may be obsolete because of the execution time of ISR interrupt service routine ELECTRONICS 12 19 LCD CONTROLLER 53 44 RISC MICROPROCESSOR FRAME Buffer Start Address 3 Register LCDSADDR3 0x01F00010 Virtual screen address set 0x000000 OFFSIZE 19 9 Virtual screen offset size the number of half words 0x0000 This value defines the difference between the address of the last half word displayed on the previous LCD line and the address of the first half word to be displayed in the new LCD line PAGEWIDTH Virtual screen pa
33. internal I cycle and coprocessor register transfer C cycle respectively MCR instructions take 15 bl 1C incremental cycles to execute where b is the number of cycles spent in the coprocessor busy wait loop ASSEMBLER SYNTAX lt MCR MRC gt cond p lt expression1 gt Rd cn cm lt expression2 gt MRC Move from coprocessor to ARM7TDMI register L 1 MCR Move from ARM7TDMI register to coprocessor L 0 cond Two character condition mnemonic See Table 3 2 p The unique number of the required coprocessor lt expression1 gt Evaluated to a constant and placed in the CP field Rd An expression evaluating to a valid ARM7TDMI register number cn and cm Expressions evaluating to the valid coprocessor register numbers CRn and CRm respectively lt expression2 gt Where present is evaluated to a constant and placed in the CP field EXAMPLES MRC p2 5 R3 c5 c6 Request coproc 2 to perform operation 5 c5 and and transfer the single 32 bit word result back to R3 MCR p6 0 R4 c5 c6 Request coproc 6 to perform operation 0 on R4 and place the result in MRCEQ p3 9 R3 c5 c6 2 Conditionally request coproc 3 to perform operation 9 type 2 on c5 and c6 and transfer the result back to ELECTRONICS 3 57 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR UNDEFINED INSTRUCTION The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instructi
34. 01 Output fe IISDI 11 EINT5 9 8 Input 01 Output IISCLK 11 EINT4 7 6 Input 01 Output nRTSO 11 5 4 Input 01 Output nCTSO 11 EINT2 3 2 Input 01 Output 07 VD5 11 EINT1 1 0 Input 01 Output VD4 11 EINTO PG 7 0 7 0 When the port is configured as an input port the corresponding bit is the pin state When the port is configured as an output port the pin state is the same as the corresponding bit When the port is configured as a functional pin the undefined value will be read ma m eon O PG 7 0 7 0 0 the pull up resistor attached to the corresponding port pin is enabled 1 the pull up resistor is disabled ELECTRENICS 8 13 1 0 PORTS 3C44B0X RISC MICROPROCESSOR SPECIAL PULL UP RESISTOR CONTROL REGISTER SPUCR D 15 0 pin pull up resistor can be controlled by the SPUCR register In STOP SL_IDLE mode the data bus D 31 0 or D 15 0 is in Hi Z state But because of the characteristics of pad the data bus pull up resistors have to be turned on to reduce the power consumption in STOP SL_IDLE mode D 31 16 pin pull up resistors can be controlled by PUPC register D 15 0 pin pull up resistors can be controlled by the SPUCR register In STOP mode memory control signals can be selected as Hi z state or previous state in order to protect against memory mal functions by setting the HZ STOP field in SPUCR register SPUCR
35. 11 LCD CONTROLLER 53 44 RISC MICROPROCESSOR 4 bit Dual Scan Display 4 bit Single Scan Display 8 bit Single Scan Display Figure 12 4 Monochrome Display Types 12 12 ELECTRONICS 53 44 RISC MICROPROCESSOR LCD CONTROLLER VD2 VD1 VDO VD3 VD2 VDO R1 G1 B1 R2 G2 B2 G3 1 Pixel VD7 VD6 VD5 VD4 VD7 VD6 VD5 VD4 H1 G1 Bi R2 22 B2 G3 4 bit Dual Scan Display VD2 VD1 VDO VD3 VD2 VD1 VDO H1 G1 1 R2 2 B2 G3 1 Pixel 4 bit Single Scan Display VD7 06 VD5 VD4 VD3 VD2 VD1 VDO R1 G1 R2 22 2 R3 G3 1 Pixel 8 bit Single Scan Display Figure 12 5 Color Display Types ELECTRONICS 12 13 LCD CONTROLLER 53 44 RISC MICROPROCESSOR MEMORY DATA FORMAT BSWPz0 Mono 4 bit Dual Scan Display LCD Panel 31 A 30 Video Buffer Memory Address Data 0000H A 31 0 0004H B 31 0 L 31 L 30 1000H 31 0 1004 M 31 0 LCD Panel A 31 A 30 A 29 CIO Mono 4 bit Single Scan Display amp 8 bit Single Scan Display Video Buffer Memory Address Data 0000H A 31 0 0004H B 31 0 0008H C 31 0 In 4 level gray mode 2 bits of video data correspond to 1 pixel In 16 level gray mode 4 bits of video data correspond to 1 pixel In color mode 8 bits 3 bits of red 3 bits of green 2 bits of blue of video data correspond to 1 pixel The color data format i
36. 19 16 Destination Register 20 Set Condition Code 0 Do not after condition codes 1 Set condition codes 21 Accumulate 0 Multiply only 1 Multiply and accumulate 31 28 Condition Field Figure 3 12 Multiply Instructions The multiply form of the instruction gives Rd Rm Rs Rn is ignored and should be set to zero for compatibility with possible future upgrades to the instruction set The multiply accumulate form gives Rd Rm Rs Rn which can save an explicit ADD instruction in some circumstances Both forms of the instruction work on operands which may be considered as signed 2 s complement or unsigned integers The results of a signed multiply and of an unsigned multiply of 32 bit operands differ only in the upper 32 bits the low 32 bits of the signed and unsigned results are identical As these instructions only produce the low 32 bits of a multiply they can be used for both signed and unsigned multiplies For example consider the multiplication of the operands Operand A Operand B Result OxFFFFFFF6 0 0000001 OxFFFFFF38 3 22 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET If the Operands Are Interpreted as Signed Operand A has the value 10 operand B has the value 20 and the result is 200 which is correctly represented as OxFFFFFF38 If the Operands Are Interpreted as Unsigned Operand A has the value 4294967286 operand B has the value 20 and the result is 85899345720 which is repres
37. 32 32 x8 x8 32 16MB 32 x8 x8 64Mb 8M x 4 x 2B x2 x8 4M x 4x 48 x2 A 23 22 28 2 2M x 8x 4B 2 23 22 m I6 x28 x2 32 x2 x8 32 32 32 8 d ELECTRENICS 4 5 MEMORY CONTROLLER 53 44 RISC MICROPROCESSOR ROM Memory Interface Example Figure 4 2 Memory Interface with 8bit ROM Figure 4 3 Memory Interface with 8bit ROM x 2 4 6 ELECTRONICS 53 44 RISC MICROPROCESSOR MEMORY CONTROLLER 0 DQO Al 001 1 2 002 A2 AS 003 AS 003 A4 004 A4 004 5 DQ5 A5 DQ5 A6 DQ6 6 DQ6 A7 DQ7 007 A8 A8 A9 nWE A9 nWE A10 nOE A10 nOE A11 11 A12 A12 A13 A13 A14 A14 A15 A15 Figure 4 4 Memory Interface with 8bit ROM x 4 Figure 4 5 Memory Interface with 16bit ROM ELECTRENICS 4 7 MEMORY CONTROLLER 53 44 RISC MICROPROCESSOR SRAM Memory Interface Example Figure 4 6 Memory Interface with 16bit SRAM 4 8 ELECTRONICS 53 44 RISC MICROPROCESSOR MEMORY CONTROLLER Figure 4 7 Memory Interface with 16bit SRAM x 2 ELECTRONICS 4 9 MEMORY CONTROLLER 53 44 RISC MICROPROCESSOR DRAM Memory Interface Example Figure 4 8 Memory Interface with 16bit DRAM Figure 4 9 Memory Interface with 16bit DRAM x 2 4 10 ELECTRONICS 53 44 RISC MICROPROCESSOR MEMORY CONTROLLER SDRAM Memory Interface Example Figure 4 10 Memory Interface with 16bit SDRAM 4Mx16 4b
38. 5 ADDCS Rc Rc Ra ADDHI Combining Discrete and Range Tests TEQ 127 CMPNE Rc 1 MOVLS ELECTRONICS If Rn p OR Rm q THEN GOTO Label If condition not satisfied try other test Test sign and 2 s complement if necessary Multiply by 4 Test value Complete multiply by 5 Complete multiply by 6 Discrete test Range test IF lt OR Rc ASCII 127 THEN Rc 3 59 ARM INSTRUCTION SET Division and Remainder 53 44 RISC MICROPROCESSOR A number of divide routines for specific applications are provided in source form as part of the ANSI C library provided with the ARM Cross Development Toolkit available from your supplier A short general purpose divide routine follows MOV CMP CMPCC MOVCC MOVCC BCC MOV CMP SUBCS ADDCS MOVS MOVNE BNE Div1 Div2 Rent 1 Rb 0x80000000 Rb Ra Rb Rb ASL 1 Rent Rent ASL 1 Div1 0 Ra Rb Ra Ra Rb Re Re Rent Rent Rent _LSR 1 Rb Rb LSR 1 Div2 Overflow Detection in the ARM7TDMI 1 Overflow in unsigned multiply with a 32 bit result UMULL TEQ BNE Rd Rt Rm Rn Rt 0 overflow 2 Overflow in signed multiply with a 32 bit result SMULL TEQ BNE Rd Rt Rm Rn Rt Rd ASR 31 overflow Enter with numbers in Ra and Rb Bit to control the division Move Rb until greater than Ra Test for possible subtraction Subtract if ok Put relevant bit into result Shift control bit Halve unless finished
39. 53 44 cache provides the entire cache enable disable mode You can enable cache by setting the value of CM in SYSCFG to 01 or 11 and disable it by clearing SYSCFG 2 1 to 00 When the cache disable mode is specified instructions and data are always fetched from external memory The 53 44 can also provide non cacheable areas in cache enable mode for some particular memory access operations such as the DMA operation The two non cacheable areas are specified by four special registers to be introduced later Data coherency is important when the cache memory is re enabled because the cache memory does not have auto flush mode You also have to be cautious whether or not DMA changes memory data The DMA accessible memory area should be non cacheable to keep data coherency To keep data coherency between cache and external memory S3C44BOX uses the write through method Cache Flushing A cache flushing can re enable the cache operation When the cache is disabled the LRU RAM can be manipulated exactly like normal memory The cache can be flushed by writing 0 to the LRU RAM and making all cache data invalid The memory location of the LRU memory is as follows NOTE Cache flushing must be executed only in the cache disable mode Non Cacheable Area The S3C44BOX provides two non cacheable areas Each of them requires two cache control fields which indicate the start and end address of each non cacheable area In a non cacheable area th
40. 7 0 General Chip Select are activated when the address of a memory is within the address region of each bank The number of access cycles and the bank size can be programmed nWE nWE Write Enable indicates that the current bus cycle is a write cycle nWBE 3 0 Ed Write Byte Enable nBE 3 0 Upper Byte Lower Byte Enable In case of SRAM pes 122 nOE Output Enable indicates that the current bus cycle is a read cycle nXBREQ nXBREQ Bus Hold Request allows another bus master to request control of the local bus BACK active indicates that bus control has been granted nXBACK nXBACK Bus Hold Acknowledge indicates that the S3C44BOX has surrendered control of ram local bus to another bus master nWAIT nWAIT requests to prolong a current bus cycle As long as nWAIT is L the current bus cycle cannot be completed ENDIAN It determines whether or not the data type is little endian or big endian The logic level is determined by the pull up down resistor during the RESET cycle O little endian 1 big endian DRAM SDRAM SRAM nRAS 1 0 Row Address Strobe nCAS 3 0 Column Address strobe nSRAS SDRAM Row Address Strobe nSCAS SDRAM Column Address Strobe nSCS 1 0 O SDRAM Chip Select DOMI3 0 O SDRAM Data Mask SCLK SDRAM Clock SCKE EX SDRAM Clock Enable 1 18 ELECTRONICS 53 44 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 3 53 44 Signal Descriptions Continued uo
41. 7 2 ELECTRDNICS 53 44 RISC MICROPROCESSOR DMA BDMA BRIDGE DMA Figure 7 2 shows the internal diagram of a BDMA block The BDMA is in the Bridge which is the interface layer between SSB and SPB The main role of BDMA is to transfer the data between external memory and internal peripherals like UART IIS and SIO which are attached to SPB The timer can also request a DMA operation anytime it is useful for operating the ADC block automatically Usually the CPU or other master devices should access the external memory through memory controller which is attached to SPB Please be reminded that the BDMA is also a type of master device To transfer the data from memory peripheral devices to peripheral devices memory attached to SPB SSB the memory controller attached to SSB should be used Because the BDMA is in the Bridge which is an interface layer between SSB and SPB it can transfer the data between two devices which are attached to SSB as well as SPB The BDMA cannot support a 4 word burst transfer the block transfer mode because BDMA does not have a temporary buffer and because the peripheral devices attached to SPB is slow Specifically the BDMA can support the data transfer from external memory to external memory a slightly ineffective way of data transfer if you look at the block diagram Even if BDMA can support the data transfer between external memories ZDMA is recommended for use instead of to transfer data between exte
42. 8 REDLUT 7 4 REDLUT 3 0 are assigned to each red level The possible combination of 4 bits each field is 16 and each red level should be assigned to one level among possible 16 cases In other words the user can select the suitable red level by using this type of lookup table For green color the GREENVAL 31 0 of the GREENLUT register is assigned as the lookup table as was done in the case of red color Similarly the BLUEVAL 15 0 of the BLUELUT register is also assigned as a lookup table For blue color we need 16bit for a lookup table because 2 bits are allocated for 4 blue levels different from the 8 red or green levels 12 6 ELECTRONICS 53 44 RISC MICROPROCESSOR LCD CONTROLLER DITHERING AND FRC FRAME RATE CONTROL The DITHFRC block has two functions such as a Time based Dithering Algorithm for reducing flicker and FRC Frame Rate Control for displaying gray level on the STN panel The main principle of gray level display on the STN panel based on FRC is described For example to display the third gray 3 16 level from a total of 16 levels the 3 times pixel should be on and 13 times pixel off In other words 3 frames should be selected among the 16 frames of which 3 frames should have a pixel on on a specific pixel while the remaining 13 frames should have a pixel off on a specific pixel These 16 frames should be displayed periodically This is basic principle on how to display the gray level on the screen so ca
43. A clock_prescaler_A MCLK lt division factor Prescaler value B 3 0 prescaler division factor for the prescaler B clock_prescaler_B MCLK lt division factor gt ww 6 1 0 2 s wm wm s wm ww w ww ww t we NOTES 1 If the prescaler value is 3 5 7 the duty is not 50 In this case the H duration is 0 5 2 ThellSPSR register can be accessed by byte halfword and word unit using STRB STRH STR and LDRB LDRH LDR instructions or char short int int type pointer in Little Big endian mode 3 Li B HW W Access by byte halfword word unit when the endian mode is Little Bi B HW W Access by byte halfword word unit when the endian mode is Big ELECTRENICE 17 7 IIS BUS INTERFACE 53 44 RISC MICROPROCESSOR IIS FIFO CONTROL REGISTER IISFCON To start IIS operation the following procedure is needed 1 Enable the FIFO in IISFCON register 2 Enable DMA request in IISCON register 3 Enable IIS interface start in IISCON register To end IIS operation the following procedure is needed 1 Disable the FIFO If you want to transmit the data remained in FIFO you must not disable the FIFO and skip this stop 1 2 Disable DMA request in IISCON register 3 Disable IIS interface start in IISCON register IISFCON 0x01D1800C Li HW Li W Bi W R W 1 FIFO interface register 0 0 0x01 D1800E Bi HW Transmit FIFO 11 0 Normal access m
44. CPU the other DMA and the external bus master may have bus mastership This feature in the whole service mode can provide the optimal bus sharing preventing the monopoly of bus mastership by DMA If the other master intercepts the bus mastership as shown in Figure 7 7 the remainder of DMA operation can be executed after servicing the impinged bus mastership without the re activation of nXDREQ 1 nXDACK 1 A DMA DMA DMA Service Service Service Figure 7 6 Whole Service Mode nXDREQ 1 nXDACK 1 DMA DMA DMA Service Service Service Service Service The other service Figure 7 7 Whole Service Mode When Another Bus Master Acquires Bus Mastership 7 6 ELECTRONICS 53 44 RISC MICROPROCESSOR DMA Demand Mode Demand mode implies continuous DMA transfer cycles as long as DMA request signal is activated as shown in figure 7 8 Unlike the whole service mode this mode does not permit the bus hand over bus mastership to higher priority bus master which make this request to bus controller during DMA operations In other words no other bus master can have bus mastership during the demand mode The sole monopoly of the bus mastership in demand mode prevents the demand mode from exceeding the specified maximum time such as the DRAM refresh period nXDREQ 1 nXDACK 1 DMA DMA DMA Service Service Service Figure 7 8 Demand Mode NOTE The bus controlle
45. EXTALO PLL on 01 EXTCLK PLL on 10 11 Chip test mode EXTCLK External clock source when OM 3 2 01b If it isn t used it has to be H 3 3V XTALO Al Crystal Input for internal osc circuit for system clock If it isn t used XTALO has to be H 3 3V EXTALO AO Crystal Output for internal osc circuit for system clock It is the inverted output of XTALO If it isn t used it has to be a floating pin ou JTAG TEST LOGIC nTRST nTRST TAP Controller Reset resets the TAP controller at start If debugger is used A 10K pull up resistor has to be connected If debugger black ICE is not used nTRST pin must be at L or low active pulse TAP Controller Mode Select controls the sequence the TAP controller s A 10K pull up resistor has to be connected to TMS pin TCK TAP Controller Clock provides the clock input for the JTAG logic A pull up resistor must be connected to TCK pin TDI TAP Controller Data Input is the serial input for test instructions and data A K pull up resistor must be connected to TDI pin 10 TDO TAP Controller Data Output is the serial output for test instructions and data 1 20 ELECTRONICS 53 44 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 3 S3C44B0X Signal Descriptions Concluded sewaxewwgewongSY RTC VDD 2 5 V 3 0 V Not support 3 3V This pin must be conne
46. External clock Data direction This bit controls whether MSB is transmitted first or LSB is transmitted first 0 MSB mode 1 2 LSB mode Tx Rx selection This bit decides whether to enable the transmit operation enabled If you want to only transmit the received data in SIODAT will be ignored If users want to transmit and receive SIO supports data transmission and reception simultaneously Users write the data transmitted in the SIODAT register and then SIO will transmit the data serially At the same time SIO will receive the data from an external SIO device After the SIO transmission is completed the contents of SIODAT will have the received data 0 Receive only mode 1 Transmit Receive mode receive operation 0 falling edge clock 1 rising edge clock SIO start This bit determines whether the SIO functions is running or has stopped When BDMA Tx is used this bit should be 0 0 No action 1 Clear 3 bit counter and start shift This bit is cleared just after writing this bit as 1 Shift operation Determines SIO shift operation 0 Non hand shaking mode Auto run mode 1 Reserved SIO mode select Determines how and by what SIODATA is read written 00 no operations 01 SIO interrupt mode 10 BDMAO mode 11 BDMA1 mode Clock edge select This bit determines the clock to be used for serial transmit or ELECTRONICS 18 7 SIO 53 44 RISC MICROPROCESSOR SIO DATA REGISTER SIODAT Before
47. GENERATOR amp POWER MANAGEMENT SPECIAL REGISTER PLL CONTROL REGISTER PLLCON m p 2 m MDIV 8 p PDIV 2 s SDIV NOTE Fpllo must greater than 20Mhz and less than 66Mhz Example If Fin 14 318Mhz and Fout 60Mhz the calculated value is as follows MDIV 59 PDIV 6 and SDIV 1 This value may be calculated using PLLSET EXE utility provided by SAMSUNG PLL VALUE SELECTION GUIDE 1 Fpllo 2 has to be less than 170 MHz 2 Sshould be as great as possible 3 Fin p is recommended to be 1Mhz or above But Fin p lt 2Mhz PLLCON 0x01D80000 PLL configuration Register 0x38080 MDIV 19 12 Main divider control PDIV 9 4 Pre divider control SDIV 1 0 Post divider control 5 14 ELECTRONICS S3C44B0X RISC MICROPROCESSOR CLOCK amp POWER MANAGEMENT CLOCK CONTROL REGISTER CLKCON CLKCON 0x01D80004 Clock generator control Register 0 7 8 1 13 Controls MCLK into IIC block 0 Disable 1 Enable 12 Controls MCLK into ADC block 0 Disable 1 Enable 11 Controls MCLK into RTC control block Even if this bit is cleared to 0 RTC timer is alive 0 Disable 1 Enable 10 Controls MCLK into GPIO block Set to 1 to use interrupt requests by EINT 4 7 0 Disable 1 Enable Controls MCLK into UART1 block 0 Disable 1 Enable Controls MCLK into UARTO block 0 Disable 1 Enable Controls MCLK into BDMA block 0 Disable 1 Enable 14 Con
48. Hour and O Minute because of the one second deviation that was mentioned In this case user should re read from BCDYEAR to BCDSEC if BCDSEC is zero BACKUP BATTERY OPERATION The RTC logic can be driven by the backup battery which supplies the power through the RTCVDD pin into RTC block even if the system power is off When the system off the interfaces of the CPU and RTC logic should be blocked and the backup battery only drives the oscillation circuit and the BCD counters to minimize power dissipation 14 2 ELECTR NICS 53 44 RISC MICROPROCESSOR REAL TIME CLOCK ALARM FUNCTION The RTC generates an alarm signal at a specified time in the power down mode or normal operation mode In normal operation mode the alarm interrupt ALMINT is activated In the power down mode the power management wakeup PMWKUP signal is activated as well as the ALMINT The RTC alarm register RTCALM determines the alarm enable disable and the condition of the alarm time setting TICK TIME INTERRUPT The RTC tick time is used for interrupt request The TICNT register has an interrupt enable bit and the count value for the interrupt The count value reaches 0 when the tick time interrupt occurs Then the period of interrupt is as follow Period n 1 128 second Tick time count value 1 127 This RTC time tick may be used for RTOS real time operating system kernel time tick If time tick is generated by RTC time tick the time rel
49. If READ_START is enabled this value is not valid 0 No operation 1 A D conversion starts and this bit is cleared after the start up NOTES 1 The ADCCON register can be accessed by halfword word unit using STRB STRH STR and LDRB LDRH LDR instructions or char short int int type pointer in the Little Big endian mode 2 Li B HW W Access by char halfword word unit when the endian mode is Little Bi B HW W Access by char halfword word unit when the endian mode is Big ELECTRENICS 13 5 A D CONVERTER 53 44 RISC MICROPROCESSOR A D CONVERTER PRESCALER REGISTER ADCPSR ADCPSR 0x01D40004 Li W Li HW R W A D Converter prescaler Register Li B Bi W 0x01D40006 Bi HW 0x01D40007 Bi B ADCPSR Bit Description Initial State PRESCALER 7 0 Prescaler value 0 255 Division factor 2 prescaler_value 1 Total clocks for ADC converstion 2 Prescalser_value 1 16 NOTES 1 The ADCPSR register can be accessed by halfword and word unit using STRB STRH STR and LDRB LDRH LDR instructions or char short int int type pointer in Little Big endian mode 2 Li HW W Access by char halfword word unit when the endian mode is Little Bi HW W Access by char halfword word unit when the endian mode is Big A D CONVERTER DATA REGISTER ADCDAT After A D conversion is completed the ADCDAT reads the converted data ADCDAT has to be read after the conversion has been completed ADCDAT 0x01D40008 Li W L HW B
50. KB the other 4KB internal memory can be used as a 2 way set associative cache The memory access cycle of the internal SRAM is 1 MCLK cycle Cache Size 8KB 4way 4KB 2way None 4KB 2 way set associative SRAM uses the area allocated for sets 2 and 3 of 8KB cache 4 way set associative 8KB Addresses in a set memory is increased sequentially and addresses in TAG LRU increases of 16byte Don t access the interval addresses between 0x10003004 and 0x1000300f Area Set Cache cache set 0 cache set 1 cache set 2 cache set 3 cache tag 0 2 98 7 0x10002000 0 10002710 512bytes note cache tag 1 0x10004000 0x10004710 The cache tag3 0 amp LRU must be read written by word access 32bit The address bit 3 0 of tag amp LRU must be 0 For example if you want to read the 2nd item among 128 cache tag 0 items you should not read the address 0x10002004 but 0x10002010 Therefore the tagO addresses are 0x10002000 0 10002010 0x10002020 0 10002710 cache tag 2 0x10001800 0x10001fff cache tag 3 LRU NOTE 0 1000 0000 Valid data 1 word 0x1000 0010 valid 0x1000 2010 Valid data 0x1000_0020 0x1000_2020 3 word invalid 0 Size 5128 2KB Valid data 0 1000 270 i 0x1000_07f0 Valid data 0x1000_0800 0x1000_2800 ELECTRENICS 6 5 CPU WRAPPER amp BUS PRIORITIES 53 44 RISC MICROPROCESSOR Figu
51. MICROPROCESSOR PWM TIMER PWM PULSE WIDTH MODULATION Write Write TCMPBn 60 TCMPBn 40 TCMPBn 30 Write Write Write TOMES SQ TCMPBn Next PWM Value Figure 9 5 Example of PWM PWM feature can be implemented by using the TCMPBn PWM frequency is determined by TCNTBn A PWM value is determined by in figure 9 5 For a lower PWM output value decrease the TCMPBn value For a higher PWM output value increase the TCMPBn value If an output inverter is enabled the increment decrement may be reversed Because of the double buffering feature TCMPBn for a next PWM cycle can be written at any point in the current PWM cycle by ISR or something else ELECTRENICS 9 7 PWM TIMER 53 44 RISC MICROPROCESSOR OUTPUT LEVEL CONTROL Inverter off ___ bL b i Inverter on Initial State Period 1 Period 2 Timer Stop Figure 9 6 Inverter On Off The following methods can be used to maintain TOUT as high or low assume the inverter is off 1 Turn off the auto reload bit And then TOUTn goes to high level and the timer is stopped after TCNTn reaches to 0 This method is recommended 2 Stop the timer by clearing the timer start stop bit to 0 If TCNTn lt TCMPn the output level is high If TCNTn the output level 15 low 3 Write the TCMPBn which is bigger than TCNTBn This inhibits the TOUTn from going to high because TCMPBn can not have the same val
52. Master receive mode 11 Master transmit mode Busy signal status 1 busy signal status bit START STOP 0 read IIC bus not busy when read condition write IIC bus STOP signal generation 1 read busy when read write IIC bus START signal generation The data in IICDS will be transferred automatically just after the start signal Serial output enable 4 data output enable disable bit 0 Rx Tx 1 Rx Tx Arbitration 3 IIC bus arbitration procedure status flag bit status flag 0 Bus arbitration successful 1 Bus arbitration failed during serial I O Address as slave 2 IIC bus address as slave status flag bit status flag 0 cleared when START STOP condition was detected 1 Received slave address matches the address value in the IICADD Address zero IIC bus address zero status flag bit status flag 0 cleared when START STOP condition was detected 1 Received slave address is 000000000 Last received bit last received bit status flag bit status flag 0 Last received bit is 0 ACK was received 1 Last receive bit is 1 ACK was not received 16 12 ELECTRONICS 53 44 RISC MICROPROCESSOR IIC BUS INTERFACE MULTI MASTER IIC BUS ADDRESS REGISTER IICADD IICADD 0x01D60008 address register X000 itial State Slave address 7 0 7 bit slave address latched from the IIC bus XXXX When serial output ena
53. Move a value from a register in the range 8 15 to a register in the range 0 7 10 1 MOV Hd Rs MOV Hd Rs Move a value from a register in the range 0 7 to a register in the range 8 15 10 MOV Hd Hs MOV Hd Hs Move a value between two registers in the range 8 15 11 BX Rs BX Rs Perform branch plus optional state change to address in a register in the range 0 7 BX Hs BX Hs Perform branch plus optional state change to address in a register in the range 8 15 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 12 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction THE BX INSTRUCTION BX performs a Branch to a routine whose start address is specified in a Lo or Hi register Bit 0 of the address determines the processor state on entry to the routine BitO 0 Causes the processor to enter ARM state Bit 0 1 Causes the processor to enter THUMB state NOTE The action of H1 1 for this instruction is undefined and should not be used ELECTRONICS 3 77 ARM INSTRUCTION SET EXAMPLES Hi Register Operations ADD PC R5 CMP R4 R12 MOV R15 R14 Branch and Exchange ADR R1 0utof THUMB MOV R11 R1 BX R11 ALIGN CODE32 outof THUMB USING R15 AS AN OPERAND 53 44 RISC MICROPROCESSOR PC PC R5 but don t set the condition codes Set the condition codes on the result of R12
54. PC as a base and a corrected immediate offset to address the location given by evaluating the expression This will be a PC relative pre indexed address If the address is out of range an error will be generated A pre indexed addressing specification Rn offset of zero Rn lt expression gt Rn Rm lt shift gt offset of lt expression gt bytes offset of contents of index register shifted by lt shift gt A post indexed addressing specification Rn lt expression gt Rnj Rm lt shift gt offset of lt expression gt bytes offset of contents of index register shifted as by lt shift gt General shift operation see data processing instructions but you cannot specify the shift amount by a register Writes back the base register set the W bit if is present ELECTRONICS ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR EXAMPLES STR STR LDR LDR LDREQB STR PLACE ELECTRONICS R1 R2 R4 R1 R2 R4 R1 R2 16 R1 R2 R3 LSL 2 R1 R6 5 R1 PLACE Store R1 at R2 R4 both of which are registers and write back address to R2 Store R1 at R2 and write back R2 R4 to R2 Load R1 from contents of R2 16 but don t write back Load R1 from contents of R2 R3 4 Conditionally load byte at R6 5 into R1 bits O to 7 filling bits 8 to 31 with zeros Generate PC relative offset to address PLACE 3 33 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR
55. Receive Buffer URXH1 0x01d04027 0x01d04024 UART 1 Receive Buffer UBRDIVO 0x01d00028 W R W UART 0 Baud Rate Divisor UBRDIV1 0x01d04028 UART 1 Baud Rate Divisor SS LS Baud Rate Prescaler Interval Counter DCNTZ 0x01d14010 510 Count DMA Count Zero ELECTRONICS 1 23 PRODUCT OVERVIEW 53 44 RISC MICROPROCESSOR Table 1 4 S3C44B0X Special Registers Continued Register Address Address Read Name B Endian L Endian Write PORT R W Port A Control Pull up Control Pull up Control D Pull up Control E Pull up Control F Pull up Control G WATCHDOG TIMER 1 24 Special Pull up External Interrupt Control External Interrupt Pending R W Timer Mode Timer Data Watchdog Timer Count Timer Count ELECTRONICS 53 44 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 4 S3C44B0X Special Registers Continued mpm 9500 Endian L Endian Write A D CONVERTER IW ADC ox0ra40008 0a Dioizea 10 ot Daa 00000 PWM TIMER W R W Timer Configuration Timer Configuration Timer Count Buffer 0 Timer Compare Buffer 0 Count Observation 0 R W Timer Count Buffer 1 Timer Compare Buffer 1 Timer Count Observations Rw Timer Count Timer Count Observations RW meCortObsenalni TmercemO
56. To support the Auto reload mdoe the DMA should have two registers sets The registers Z B DISRCn Z B DIDESn and Z B DICNTn have the initial configuration for DMA operation as above mentioned and registers Z B DCSRCn Z B DCDESn and Z B DCCNTn have the configuraion reflecting the current DMA operation For example these register should have dynamic values of source address destination address and the remained transfer count or TC Terminal Count during DMA operation The register contents of Z B DISRCn Z B DIDESn Z B DICNTn can be reloaded into the registers Z B DCSROn Z B DCDESn and Z B DCCNTn under one of the four cases case 1 Auto Reload AR is equal to 1 and DMA Count reaches to 0 which are normal auto reload mode of DMA operation case 2 Writes new configuration into the Z B DISRCO Z B DIDESO and Z B DICNTO If DMA is in Auto reload mode these new contests of the register will be re loaded automatically as same as above case If DMA is not active these new configuration will be written into registers Z B DISRCO Z B DIDESO and Z B DICNTO immediately case 3 When DMA is enable i e EN bit in Z B DICNT register changes from 0 to 1 The register contents of Z B DISRCO Z B DIDESO and Z B DICNTO will be loaded into the registers of Z B DCSRCO Z BJDCDESO and Z B DCCNTO immediately to start of DMA operation regardless of whether DMA is in Auto reload mode or not case 4 S W command is Cancel When user wri
57. When a cache fill occurs the value of CS is changed to 0110 at the specified line which signifies that only set 0 is valid When the subsequent cache fill occurs the value of CS will be 0011 at the specified line which represents that contents of both set 0 and set 2 are valid When the subsequent cache fill occurs the value of CS will be 0101 at the specified line which represents that contents of set 0 set 1 and set 2 are valid And succesive cache fill make CS 1000 at the specified line which represents that all caches are valid The value of CS 1xxx represents that all of the sets are valid Then the next cache miss occurs the least significant 3 bits of CS select set are replaced First bit selects a group of sets 0 selects group 0 which contains 5610 and seti otherwise group1 which contains set2 and set3 Second bit selects the set of group 0 selects 6610 otherwise set1 Third bit selects the set of group 1 0 selects 5612 otherwise set 3 For example if LS 3bit is 000 the victim is 5610 If LS 3bit is 101 the victim is 6613 Cache Line Replacement All 4 Lines in the set valid Replace Invalid Line LO or L1 least 80 09 L2 or L3 least resently used resently used Replace Replace Replace Replace Line LO Line L1 Line L2 Line L3 Figure 6 2 Cache Replace Configuration ELECTRENICS 6 3 CPU WRAPPER amp BUS PRIORITIES 53 44 RISC MICROPROCESSOR Cache Disable Operation The
58. a Enable interrupt b Define SCL period 3 Set IICSTAT to enable Serial Output START Master Tx mode has been configured Write slave address to IICDS Write OxFO M T Start to IICSTAT The data of the IICDS is transmitted ACK period and then interrupt is pending Write new data Write OxDO M T Stop to transmitted to IICDS IICSTAT Clear pending bit to Clear pending bit resume The data of the IICDS is Wait until the stop shifted to SDA condition takes effect Figure 16 6 Operations for Master Transmitter Mode i ad E E E aee ELECTRONICS 16 7 IIC BUS INTERFACE 53 44 RISC MICROPROCESSOR START Master Rx mode has been configured Write slave address to ICDS Write OxFO M R Start to IICSTAT The data of the IICDS slave address is transmitted ACK period and then interrupt is pending Read new data from Write 0x90 M R Stop to IICDS IICSTAT Clear pending bit to Clear pending bit resume SDA is shifted to IICDS Wait une stop condition takes effect E E pep E ud ES Figure 16 7 Operations for Master Receiver Mode 16 8 ELECTRONICS 53 44 RISC MICROPROCESSOR IIC BUS INTERFACE START Slave Tx mode has been configured detects start signal and IICDS receives data compares IICADD and IICDS the received slave address The IIC address match interrupt is generated Write data to IICDS Clear pending bit to resume The data of the IICD
59. a serial clock line SCL carry information between bus masters and peripheral devices which are connected to the The SDA and SCL lines are bi directional In multi master mode multiple 53 44 RISC microprocessors can receive or transmit serial data to or from slave devices The master S3C44BOX which can initiate a data transfer over the IIC bus is responsible for terminating the transfer Standard bus arbitration procedure is used in this in 53 44 To control multi master operations values must be written to the following registers Multi master IIC bus control register Multi master control status register IICSTAT Multi master Tx Rx data shift register IICDS Multi master address register IICADD When the is free the SDA and SCL lines should be both at High level A High to Low transition of SDA can initiate a Start condition A Low to High transition of SDA can initiate a Stop condition while SCL remains steady at High Level The Start and Stop conditions can always be generated by the master devices A 7 bit address value in the first data byte which is put onto the bus after the Start condition has been initiated can determine the slave device which the bus master device has selected The 8 bit determines the direction of the transfer read or write Every data byte put onto the SDA line shoul
60. a2 10 0 MOV Ir ARM Code udiv10 Take argument in a1 returns quotient in a1 remainder in a2 SUB a2 a1 10 SUB a1 al a1 Isr 2 ADD a1 a1 a1 Isr 4 ADD a1 a1 a1 Isr 48 ADD al a1 al Isr 16 MOV a1 a1 Isr 43 ADD a3 a1 a1 asl 42 SUBS a2 a2 a3 asl 1 ADDPL al 1 ADDMI a2 a2 10 MOV Ir 3 106 ELECTRONICS 53 44 RISC MICROPROCESSOR MEMORY CONTROLLER MEMORY CONTROLLER OVERVIEW The 53 44 0 memory controller provides the necessary memory control signals for external memory access 53 44 has the following features Little Big endian selectable by an external pin Address space 32Mbytes per each bank total 256MB 8 banks Programmable access size 8 16 32 bit for all banks Total 8 memory banks 6 memory banks for ROM SRAM etc 2 memory banks for ROM SRAM FP EDO SDRAM etc 7 fixed memory bank start address and programmble bank size 1 flexible memory bank start address and programmable bank size Programmable access cycles for all memory banks External wait to extend the bus cycles Supports self refresh mode in DRAM SDRAM for power down Supports asymmetrically or symmetrically addressable DRAM ELECTRONICS 4 1 MEMORY CONTROLLER 53 44 RISC MICROPROCESSOR Table 4 1 Bs Bs 0 0 00 0000 Lom 16655 0x0a00_0000 Lom 1854 0 0800 0000 256MB SA 27 0 1853 0 0600 0000 2 4 8 16 32MB 0x1000
61. again In the receive mode after a data is received the IIC bus interface will wait until IICDS register is read Until the new data is read out the SCL line will be held low After the new data is read out from IICDS register the SCL line will be released The S3C44BOX should hold the interrupt to identify the completion of the new data reception After the CPU receives the interrupt request it should read the data from IICDS BUS ARBITRATION PROCEDURES Arbitration takes place on the SDA line to prevent the contention on the bus between two masters If a master with a SDA High level detects another master with a SDA active Low level it will not initiate a data transfer because the current level on the bus does not correspond to its own The arbitration procedure will be extended until the SDA line turns High However when the masters simultaneously lower the SDA line each master should evaluate whether or not the mastership is allocated to itself For the purpose of evaluation each master should detect the address bits While each master generates the slaver address it should also detect the address bit on the SDA line because the lowering of SDA line is stronger than maintaining High on the line For example one master generates a Low as first address bit while the other master is maintaining High In this case both masters will detect Low on the bus because Low is stronger than High even if first master is trying to maintain High on the
62. amp 80000000 a1 a1 0 ip a4 a2 ASR 32 a2 a2 0 and remainder INSTRUCTION SET R1 Get dividend divisor signs back Result sign Negate if result sign 1 Negate remainder if dividend sign 1 Effectively zero a4 as top bit will be shifted out later Central part is identical code to udiv without MOV a4 0 which comes for free as part of signed entry sequence MOVS BEQ just MOVLS BLO div_ CMP ADC SUBCS TEQ MOVNE BNE MOV 5 RSBCS RSBMI MOV ELECTRONICS a3 a1 divide by zero a3 a2 LSR 1 a3 a3 LSL 1 s loop a2 a3 a4 a4 a4 a2 a2 a3 a3 al a3 a3 LSR 1 S loop2 al a4 ip ip ASL 1 a1 a1 0 a2 a2 0 Ir Justification stage shifts 1 bit at time NB LSL 1 is always OK if LS succeeds 3 105 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR DIVISION BY A CONSTANT Division by a constant can often be performed by a short fixed sequence of shifts adds and subtracts Here is an example of a divide by 10 routine based on the algorithm in the ARM Cookbook in both Thumb and ARM code Thumb Code udiv10 Take argument in a1 returns quotient in a1 remainder a2 MOV a2 al LSR a3 a1 2 SUB a1 a3 LSR a3 al 4 ADD al a3 LSR a3 a1 8 ADD al a3 LSR 16 ADD al LSR al 3 ASL a3 a1 2 ADD a3 a1 ASL a3 1 SUB a2 a3 CMP a2 10 BLT FTO ADD al 1 SUB
63. and Write cycle It means that the bus controller can allocate the bus usage to other higher bus master between Read and Write cycle The DMA request by nXDREQ causes one byte one half word or one word to be transmitted The handshake mode requires the DMA request for every data transfer The nXDREQ can be released after active nXDACK and request again after inactive nXDACK as shown in Figure 7 3 nXDREQ 1 nXDACK 1 aS Service Figure 7 3 Handshake Mode Diagram 7 4 ELECTRDNICS 53 44 RISC MICROPROCESSOR DMA Single Step Mode The single step mode means that there are two DMA acknowledge cycles indicating DMA read and write cycle The single step mode is usually used for test or debugging because the bus mastership can be handed over to other bus master between Read and Write During the inactive period nXDACK i e between Read and Write cycle the bus controller re evaluates the bus priority to determine the new bus mastership Therefore data transfer slower than that of the hand shake mode is expected When the DMA request signal goes low the bus controller indicates the bus allocation for the DMA operation by lowering the DMA acknowledge signal if there is no higher priority bus request During the first low level period of the DMA acknowledge signal there will be a DMA read cycle After the DMA read cycle there will be a rising of the DMA acknowledge signal to indicate the end of the DMA read cycle Simultaneo
64. and write operations to signal to the external memory manager that they are locked together and should be allowed to complete without interruption This is important in multi processor systems where the swap instruction is the only indivisible instruction which may be used to implement semaphores control of the memory must not be removed from a processor while it is performing a locked operation BYTES AND WORDS This instruction class may be used to swap a byte B 1 or a word B 0 between an ARM7TDMI register and memory The SWP instruction is implemented as a LDR followed by a STR and the action of these is as described in the section on single data transfers In particular the description of Big and Little Endian configuration applies to the SWP instruction ELECTRONICS 3 47 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR USE OF R15 Do not use R15 as an operand Rd Rn or Rs in a SWP instruction DATA ABORTS If the address used for the swap is unacceptable to a memory management system the memory manager can flag the problem by driving ABORT HIGH This can happen on either the read or the write cycle or both and in either case the Data Abort trap will be taken It is up to the system software to resolve the cause of the problem then the instruction can be restarted and the original program continued INSTRUCTION CYCLE TIMES Swap instructions take 1S 2N 11 incremental cycles to execute where S N are defin
65. bits in the external interrupt request is generated EXTINTPNDn will be set as 1 The interrupt service routine must clear the interrupt pending condition INTPND after clearing the external pending condition EXTINTPND EXTINTPND is cleared by writing 1 EXTINTPND 0x01D20054 External interrupt pending Register Table 8 11 D 15 0 Pull Up Control Register PUPS Bt Desrpin O EXTINTPND3 If EINT7 is activated EXINTPNDS bit is set to 1 and also INTPND 21 is set to 1 EXTINTPND2 If EINT6 is activated EXINTPND bit is set to 1 and also INTPND 21 is set to 1 EXTINTPND1 1 If EINTS is activated EXINTPND1 bit is set to 1 and also INTPND 21 is set to 1 EXTINTPNDO 0 If EINT4 is activated EXINTPNDO bit is set to 1 and also 21 is set to 1 8 16 ELECTRONICS 53 44 RISC MICROPROCESSOR PWM TIMER PWM TIMER OVERVIEW The 53 44 has six 16 bit timers each timer can operate interrupt based or DMA based mode The timers 0 1 2 3 and 4 have the PWM function Pulse Width Modulation Timer 5 has an internal timer only with no output pins Timer 0 has a dead zone generator which is used with a large current device Timer 0 and timer 1 share an 8 bit prescaler timers 2 amp 3 share another 8 bit prescaler and timers 4 amp 5 share the other 8 bit prescaler Each timer except timers 4 and 5 has a clock divider which has 5 different divided signals 1 2 1 4 1 8 1 16 1 32 Timer
66. byte FIFOs and data shifters Data which is to be transmitted is written to FIFO and then copied to the transmit shifter It is then shifted out by the transmit data pin TxDn The received data is shifted from the receive data pin RxDn and then copied to FIFO from the shifter FEATURES RxDO TxDO RxD1 TxD1 with DMA based or interrupt based operation UART Ch 0 with IrDA 1 0 amp 16 byte FIFO UART Ch 1 with IrDA 1 0 amp 16 byte FIFO Supports handshake transmit receive ELECTRENICE 10 1 UART 53 44 RISC MICROPROCESSOR BLOCK DIAGRAM Peripheral BUS Transmitter Transmit Shifter Control m Buad rate Unit Generator Receive Shifter Receive FIFO 16 Byte Receiver Figure 10 1 UART Block Diagram with FIFO 10 2 ELECTRONICS 53 44 RISC MICROPROCESSOR UART UART OPERATION The following sections describe the UART operations that include data transmission data reception interrupt generation baud rate generation loopback mode infra red mode and auto flow control Data Transmission The data frame for transmission is programmable It consists of a start bit 5 to 8 data bits an optional parity bit and 1 to 2 stop bits which can be specified by the line control register UCONn The transmitter can also produce the break condition The break condition forces the serial output to logic 0 state for a duration longer than one frame transmission time This block transmit break sig
67. consecutive writings is shortened the write buffer 0 Disable write buffer operation 1 Enable write buffer operation These two bits determine cache mode 00 Disable cache 8KB internal SRAM 01 Half cache enable 4KB cache 4KB internal SRAM 10 Reserved 11 Full Cache enable 8KB cache Enable stall option This bit is recommended to be 0 O stall disable 1 stall enable Stall option Insert one internal wait cycle when a non sequential address is generated for caching 6 8 ELECTRONICS 53 44 RISC MICROPROCESSOR CPU WRAPPER amp BUS PRIORITIES NON CACHEABLE AREA CONTROL REGISTER NCACHBEn NCACHBEO 0x01C00004 Start address amp end address of non cacheable area 0 0x00000000 NCACHBE1 0x01C00008 Start address amp end address of non cacheable area 1 0x00000000 SEO 31 16 End address of non cacheable area 0 0x0000 These 16 bits provide the end address of non cacheable area 0 The minimum non cacheable area is 4 Kbytes SEO End address 1 4K SAO 15 0 Start address of non cacheable area 0 0x0000 These 16 bits provide the start address of non cacheable area 0 SAO Start address 4K SE1 31 16 End address of non cacheable area 1 0x0000 These 16 bits provide the end address of non cacheable area 1 The minimum non cacheable area is 4Kbytes SE1 End address 1 4K SA1 15 0 Start address of non cacheable area 1 0x0000 These 16 bits provide the start address of non cacheable area 1
68. control registers are shown in Table 8 3 21 0x01D20008 R W Configures the pins of port B PDATB 0x01D2000C The data register for port B Table 8 3 Port of Group B Control Registers PCONB PDATB Row m 0010 B 20 B 0 Output 1 nGCS2 PBe 6 0 Output 1 16651 0 Output 1 nWBE3 nBE3 DQM3 0 Output 1 nWBE2 nBE2 DQM2 0 Output 1 nSRAS nCAS3 0 Output 1 nSCAS nCAS2 0 Output 1 SCLK 0 0 Output 1 SCKE PB 10 0 10 0 When the port is configured as an output port the pin state is the same as the corresponding bit When the port is configured as a functional pin an undefined value will be read ELECTRENICS 8 7 PORTS 3C44B0X RISC MICROPROCESSOR PORT C CONTROL REGISTERS PCONC PDATC PUPC Port C control registers are shown in Table 8 4 0x01D20010 Configures the pins of port C PDATC 0x01D20014 The data register for port C PUPC 0x01D20018 pull up disable register for port C 0x0 Table 8 4 Port of Group C Control Registers PCONC PDATC PUPC PC15 31 30 00 Input 01 Output 10 DATA31 11 5 14 29 28 00 Input 01 Output 10 DATA30 11 2 nRTSO PC13 27 26 00 Input 01 Output 10 DATA29 11 RxD1 PC12 25 24 00 Input 01 Output 10 DATA28 11 TxD1 PC11 23 22 00 Input 01 Output 10 DATA27 11 nCTS1 PC10 21 20 00 Input 01 Output 10 DA
69. cycle from having 4 times pixel on and times pixel off Using the same methodology the 5 2 3 DP5_7 DP3_4 DP4_5 and DP6_7 are made to correspond to 9 10 11 12 13 and 14 gray level respectively For the gray level from 1 to 6 the reverse sequence of DP6 7 DP4 5 4 DP2 3 5 and 7 should be used this way new tables for gray level of 1 to 6 are not needed The Table 12 7 shows that the same pixel value can not have the same FRC sequence For example if the Pi pixel has half gray level frame and if adjacent pixel of Pi 1 also has half gray level in frame and if adjacent pixel of Pi 2 also has half gray level in frame and if adjacent pixel of Pi 3 also has half gray level in N frame the Pi Pi 1 Pi 2 and Pi 3 pixel should be 1 0 1 and 0 in frame In N 1 frame the Pi Pi 1 Pi 2 and Pi 3 pixel should be 0 1 0 and 1 as shown in Table 12 3 In case of arbitrary pixel values on arbitrary position the H W will select a suitable display value by referring to the corresponding frame number and pixel position This type of display methodology can randomize the pixel display to reduce the Flicker Noise The value of table 12 3 is just only reference and users can specify their own value suitable for the LCD display Table 12 2 Dither Duty Cycle Examples Pixel Duty Rate 53 44 has eight programmable registers such as DP6 7 4 5 DP5 7 4 DP
70. data bus inputs 31 through to 24 if the supplied address is a word boundary on data bus inputs 23 through to 16 if itis a word address plus one byte and so on The selected byte is placed in the bottom 8 bit of the destination register and the remaining bits of the register are filled with the sign bit bit 7 of the byte Please see Figure 2 1 A halfword load LDRSH or LDRH expects data on data bus inputs 31 through to 16 if the supplied address is on a word boundary and on data bus inputs 15 through to 0 if it is a halfword boundary A 1 1 The supplied address should always be on a halfword boundary If bit O of the supplied address is HIGH then the ARM7TDMI will load an unpredictable value The selected halfword is placed in the bottom 16 bits of the destination register For unsigned half words LDRH the top 16 bits of the register are filled with zeros and for signed half words LDRSH the top 16 bits are filled with the sign bit bit 15 of the halfword A halfword store STRH repeats the bottom 16 bits of the source register twice across the data bus outputs 31 through to 0 The external memory system should activate the appropriate halfword subsystem to store the data Note that the address must be halfword aligned if bit O of the address is HIGH this will cause unpredictable behaviour USE OF R15 Write back should not be specified if R15 is specified as the base register Rn When using R15 as the base register you must remem
71. data using the DMA controller SIO can wait until the transmitted data is read by the external destination device Not using hand shaking the SIO must wait for a fixed interval between every 8 bit data The interval is determined by the IVTCNT register In the auto run mode the SIO inserts this interval after transmitting every 8 bit data Steps for Transmit by DMA Refer to Fig 18 2 1 N a DCNTZ n is cleared to 0 which allows the SIO to request DMA service The SIO is configured properly but the value of SIOCON 1 0 has to be 000 DMA is configured properly The SIO is configured as DMA transmit mode SIOCON 3 SIO start bit will be ignored The SIO automatically requests DMA service without SIO start The SIO transmits the data Go to step 4 until DMA count is O DCNTZ n is set to 1 which stops the SIO from requesting further DMA service DCNTZ n 0 Setting SIOCON SIOCON 1xxx00b BDMA Setting SIOCON 10b xxxxxx 116 auto start DMAcount 0 P Y DCNTZ n 1 Figure 18 2 SIO Transmit by DMA ELECTRENICS 18 3 SIO 53 44 RISC MICROPROCESSOR Steps for Receive by DMA Refer to Fig 18 3 1 DONTZ n is cleared to 0 which allows the SIO to request the DMA service The SIO is configured properly But the value of SIOCON 1 0 has to be 006 DMA is configured properly The SIO is configured in DMA receive only mode Set SIOCON 3
72. for bank 1 0 Not using UB LB Pin 14 11 is dedicated nWBE 3 0 1 Using UB LB Pin 14 11 is dedicated nBE 3 0 bit determines WAIT status for bank 1 WAIT disable 1 WAIT enable 5 4 These two bits determine data bus width for bank 1 00 8 bit 01 16 bit 10 32 bit DWO 2 1 Indicates data bus width for bank 0 read only 00 8 bit 01 16 bit 10 32 bit The states are selected by OM 1 0 pins ENDIAN Indicates endian mode read only 0 Little endian 1 endian The states are selected by ENDIAN pins NOTES 1 Alltypes of master clock in this memory controller correspond to the bus clock For example MCLK in DRAM and SRAM is same as the bus clock and SCLK in SDRAM is also the same as the bus clock In this chapter Memory Controller one clock means one bus clock 2 nBE 3 0 is the AND signal nWBE 3 0 and nOE ELECTRENICS 4 13 MEMORY CONTROLLER 53 44 RISC MICROPROCESSOR BANK CONTROL REGISTER nGCS0 nGCS5 14 13 Tacs Address set up before nGCSn 00 0 clock 01 1 clock 10 2 clocks 11 4 clocks Tcos 12 11 Chip selection set up nOE 00 0 clock 01 1 clock 10 2 clocks 11 4 clocks Tacc 10 8 Access cycle 111 000 1 clock 001 2 clocks 010 3 clocks 011 4 clocks 100 6 clocks 101 8 clocks 110 10 clocks 111 14 clocks Toch 7 6 Chip selection hold on nOE 00 0 clock 1 clock 10 2 clocks 4 clocks 5 4 Address
73. holding time after nGCSn 00 0 clock 01 1 clock 10 2 clocks 11 4 clocks Tpac 3 2 Page mode access cycle Page mode 00 2 clocks 01 3 clocks 10 4 clocks 11 6 clocks PMC 1 0 Page mode configuration 00 normal 1 data 01 4 data 10 8 data 11 16 data 4 14 ELECTRENICS 53 44 RISC MICROPROCESSOR MEMORY CONTROLLER BANK CONTROL REGISTER BANKCONn nGCS6 nGCS7 BANKCON6 0x01C8001C Bank 6 control register 0x18008 BANKCON7 0x01C80020 Bank 7 control register 0x18008 MT 16 15 These two bits determine the memory type for bank6 and bank7 00 ROM or SRAM 01 FP DRAM 10 EDO DRAM 11 Sync DRAM Memory Type ROM or SRAM MT 00 15 bit 14 13 Address set up before nGCS 00 0 clock 01 1clock 10 2clocks clocks Tacs 12 11 Chip selection set up nOE 00 0 clock 01 1 clock 10 2 clocks clocks 10 8 Access cycle 000 1 clock 001 2 clocks 010 3 clocks 011 4 clocks 100 6 clocks 101 8 clocks 110 10 clocks 111 14 clocks 7 6 Chip selection hold on nOE 00 0 clock 01 1 clock 10 2 clocks 11 4 clocks 5 4 Address hold time on nGCSn 00 Oclock 01 1 10 2clocks 11 4 clocks 3 2 Page mode access cycle Page mode 00 2 clocks 01 3 clocks 10 4 clocks 11 6 clocks 1 0 Page mode configuration 00 normal 1 data 01 4 consecutive accesses 10 8 consecutive accesses 11 16 consecutive accesses Memory Type FP DRAM MT 01 or EDO D
74. in Rb and the value in Ro Store the contents of Rd at the address STRB Rb Ro STRB Rb Ro Pre indexed byte store Calculate the target address by adding together the value in Rb and the value in Ro Store the byte value in Rd at the resulting address LDR Rd Rb Ro LDR Rd Rb Ro Pre indexed word load Calculate the source address by adding together the value in Rb and the value in Ro Load the contents of the address into Rd LDRB Rd Rb Ro LDRB Rd Rb Ro Pre indexed byte load Calculate the source address by adding together the value in Rb and the value in Ro Load the byte value at the resulting address INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 14 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES STR R2 R6 Store word in R3 at the address formed by adding R6 to R2 LDRB R2 RO R7 Load into R2 the byte found at the address formed by adding R7 to RO 3 82 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET FORMAT 8 LOAD STORE SIGN EXTENDED BYTE HALFWORD 15 14 13 12 11 10 9 8 6 5 3 2 0 mw rm 2 0 Destination Register 5 3 Base Register 8 6 Offset Register 10 Sign Extended Flag 0 Operand not sing extended 1 Operand sing extended 11 H Flag Figure 3 37 Form
75. in a PSR a value can be written directly to the flag bits without disturbing the control bits The following instruction sets the N Z C and V flags MSR CPSR flg 40xF0000000 Setall the flags regardless of their previous state does not affect any control bits No attempt should be made to write an 8 bit immediate value into the whole PSR since such an operation cannot preserve the reserved bits INSTRUCTION CYCLE TIMES PSR transfers take 1S incremental cycles where S is defined as Sequential S cycle 3 20 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLY SYNTAX e MRS transfer PSR contents to a register MRS cond Rd lt psr gt e MSR transfer register contents to PSR MSR cond lt psr gt Rm e MSR transfer register contents to PSR flag bits only MSR cond lt psrf gt Rm The most significant four bits of the register contents are written to the N Z C amp V flags respectively e MSR transfer immediate value to PSR flag bits only expression The expression should symbolise a 32 bit value of which the most significant four bits are written to the N Z C and V flags respectively Key cond Two character condition mnemonic See Table 3 2 Rd and Rm Expressions evaluating to a register number other than R15 lt psr gt CPSR all SPSR SPSR all CPSR CPSR are synonyms as SPSR and SPSR all lt psrf gt CPSR flg or SPSR_
76. input for PWM 5 0000 1 2 0001 1 4 0010 1 8 0011 1 16 EXTCLK MUX 4 19 16 Select MUX input for PWM Timer4 0000 1 2 0001 1 4 0010 1 8 0011 1 16 01xx TCLK MUX 3 15 12 Select MUX input for PWM Timers 0000 1 2 0001 1 4 0010 1 8 0011 1 16 01xx 1 32 MUX 2 11 8 Select MUX input for PWM 0000 1 2 0001 1 4 0010 1 8 0011 1 16 01xx 1 32 MUX 1 7 4 Select MUX input for PWM Timer1 0000 1 2 0001 1 4 0010 1 8 0011 1 16 01xx 1 32 MUX 0 3 0 Select MUX input for PWM 0000 1 2 0001 1 4 0010 1 8 0011 1 16 01xx 1 32 9 12 ELECTRONICS 53 44 RISC MICROPROCESSOR PWM TIMER TIMER CONTROL REGISTER TCON Timer 5 auto reload 26 This bit determines auto reload on off for Timer 5 on off 0 One shot 1 Interval mode auto reload Timer 5 manual 25 This bit determines the manual update for Timer 5 update note 0 No operation 1 Update 5 Timer 5 start stop 24 This bit determines start stop for Timer 5 0 Stop 1 Start for Timer 5 Timer 4 auto reload 23 This bit determines auto reload on off for Timer 4 on off 0 One shot 1 Interval mode auto reload Timer 4 output 22 e bit determines output inverter on off for Timer4 inverter on off Inverter off 1 Inverter on for TOUTA Timer 4 manual 21 This bit determines the manual update for Timer 4 update note 0 No operation 1 Update TCNTB4 TCMPB4 Time
77. input frequency should not exceed 100Hz for accurate conversion although the maximum conversion rate is 100KSPS 13 2 ELECTRENICE 53 44 RISC MICROPROCESSOR A D CONVERTER Sleep Mode The ADC sleep mode is activated by setting the SLEEP bit ADCCONJ 5 to 1 In this mode the conversion clock is disabled and A D conversion operation is halted The A D converter data register contains the previous data in sleep mode NOTE After the ADC exits the sleep mode ADCCON 5 1 0 there is 10ms wait for the ADC reference voltage stabilization before the first AD conversion ADC reference pin configuration Users must configure 3 44 s reference pins 83 84 85 as shown Fig 13 2 AVCOM AREFT AREFB L 10nF 10nF 10nF i Figure 13 2 External reference pin configuration Workaround For the ADC Data Reading Problem The ADC converter state flag ADCCON 6 FLAG bit is not correct The FLAG operates incorrectly in the following cases a The FLAG will be 1 for one ADC clock time just after the ADC conversion is started This is not correct b The FLAG will be 1 one ADC clock time ago than the ADC conversion is completed This is not correct This problem will be shown conspicuously only if the ADCPSR is large To read ADC converted data correctly please refer to the following codes 0 1 0 0 lt lt 2 Start A D conversion while rADCCON amp 0x1 To avoid The first FLAG erro
78. isolating faults in the communication link In this mode the transmitted data is immediately received This feature allows the processor to verify the internal transmit and to receive the data path of each SIO channel This mode can be selected by setting the loopback bit in the UART control register UCONn Break Condition The break is defined as a continuous low level signal for more than one frame transmission time on the transmit data output ELECTRONICS 10 7 UART 53 44 RISC MICROPROCESSOR IR Infrared Mode The S3C44BOX UART block supports Infrared IR transmission and reception which be selected by setting the Infrared mode bit in the UART control register ULCONn The implementation of the mode is shown in Figure 10 3 In IR transmit mode the transmit period is pulsed at a rate of 3 16 the normal serial transmit rate when the transmit data bit is zero In IR receive mode the receiver must detect the 3 16 pulsed period to recognize a zero value refer to the frame timing diagrams shown in Figures 10 5 and 10 6 Note The received pulse is recognized by 53 44 which sampling frequency is 1 16 bit frame time so when it communicates in low speed the Rx pulse must be longer than 1 16 bit frame time In case of 9600 baud rate the Rx pulse width must be longer than 6 51us Bit frame width 104 1us sampling frequency 6 51us IrDA Tx IrDA Rx Encoder Decoder Figure 10 4 IrDA Function Block Diagr
79. reduce the number of required DMA cycles different from the general DMA cycles which has separate Read and Write cycles To operate the on the fly mode the bus size of the source should be the same as that of the destination ELECTRONICS 7 1 DMA 53 44 RISC MICROPROCESSOR ZDMA BDMA OPERATION ZDMA GENERAL DMA Figure 7 1 shows the internal diagram of a ZDMA block The ZDMA is interfaced to SSB and can transfer data from external memory to external memory Unlikely the BDMA Bridge DMA this DMA can be used to transfer data between memory mapped device or memories In other words data transfer between fixed source and external memory external memory and external memory and external memory and fixed destination can be done by using this DMA The DMA operation can be started by S W or an external DMA request signal which will be explained later In the ZDMA there is a temporary buffer which allows multiple transfers to enhance bus utilization as well as transfer speed In other words the S3C44BOX has a 4 word FIFO type buffer to support the 4 word burst transfer during DMA operation For example during the DMA operation between memories a 4 word burst write happens after a 4 word burst read nXDREQ 0 nXACK 0 nXDREQ 1 nXACK 1 ZDMA 0 lt gt ZDMA 1 Channel FIFO ZDMA 4 WORD Control 1009128 0 e 5 B o 1 Figure 7 1 ZDMA Controller Block Diagram
80. redundant as the assembler inserts it automatically SUB R4 R5 R7 LSR R2 Logical right shift R7 by the number in the bottom byte of R2 subtract result from 5 and put the answer into MOV PC R14 Return from subroutine MOVS PC R14 Return from exception and restore CPSR from SPSR_mode ELECTRONICS 3 17 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR PSR TRANSFER MRS MSR The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The MRS and MSR instructions are formed from a subset of the Data Processing operations and are implemented using the TEQ TST CMN and CMP instructions without the S flag set The encoding is shown in Figure 3 11 These instructions allow access to the CPSR and SPSR registers The MRS instruction allows the contents of the or SPSR_ lt mode gt to be moved to a general register The MSR instruction allows the contents of a general register to be moved to the CPSR or SPSR mode register The MSR instruction also allows an immediate value or register contents to be transferred to the condition code flags N Z C and V of CPSR or SPSR mode without affecting the control bits In this case the top four bits of the specified register contents or 32 bit immediate value are written to the top four bits of the relevant PSR OPERAND RESTRICTIONS n user mode the control bits of the CPSR are protected from change so only the c
81. register is empty 0 Not empty 1 Transmit holding amp shifter register empty Transmit buffer This bit is automatically set to 1 when the transmit buffer empty register does not contain valid data 0 The buffer register is not empty 1 Empty If the UART uses the FIFO users should check Tx FIFO Count bits and Tx FIFO Full bit in the UFSTAT register instead of this bit Receive buffer This bit is automatically set to 1 whenever the receive buffer data ready register contains valid data received over the RXDn port 0 Completely empty 1 The buffer register has a received data If the UART uses the FIFO users should check Rx FIFO Count bits in the UFSTAT register instead of this bit ELECTRENICS 10 13 UART 53 44 RISC MICROPROCESSOR UART ERROR STATUS REGISTER There are two UART Rx error status registers UERSTATO and UERSTAT1 in the UART block UERSTATO 0x01D00014 oR UART channel 0 Rx error status register UERSTAT1 0x01D04014 oR UART channel 1 Rx error status register Break Detect 3 This bit is automatically set to 1 to indicate that a break signal has been received 0 No break receive 1 Break receive Frame Error 2 This bit is automatically set to 1 whenever a frame error occurs during receive operation 0 No frame error during receive 1 Frame error Parity Error 1 This bit is automatically set to 1 whenever a parity error occurs during receive operation 0 No parity error during rec
82. return to the next instruction regardless of whether the SWI was executed in ARM or THUMB state Copies the CPSR into the appropriate SPSR Forces the CPSR mode bits to a value which depends on the exception Forces the PC to fetch the next instruction from the relevant exception vector It may also set the interrupt disable flags to prevent otherwise unmanageable nestings of exceptions If the processor is in THUMB state when an exception occurs it will automatically switch into ARM state when the PC is loaded with the exception vector address Action on Leaving an Exception On completion the exception handler 1 Moves the Link Register minus an offset where appropriate to the PC The offset will vary depending on the type of exception Copies the SPSR back to the CPSR Clears the interrupt disable flags if they were set on entry NOTE An explicit switch back to THUMB state is never needed since restoring the CPSR from the SPSR automatically sets the T bit to the value it held immediately prior to the exception 2 10 ELECTRONICS 53 44 RISC MICROPROCESSOR PROGRAMMER S MODEL Exception Entry Exit Summary Table 2 2 summarises the PC value preserved in the relevant R14 on exception entry and the recommended instruction for exiting the exception handler Table 2 2 Exception Entry Exit Return Instruction Previous State ARM R14 x THUMB R14 x MOV PC R14 MOVS 14 MOVS PC R14 und SUBS PC R14 fiq
83. the C flag will be set to the carry out from the barrel shifter or preserved when the shift operation is LSL 0 the Z flag will be set if and only if the result is all zeros and the N flag will be set to the logical value of bit 31 of the result Table 3 3 ARM Data Processing Instructions Assembler Mnemonic OP Cos AND EOR WUB RSB ADD ADC RSC TST CMP CMN 10 Operandi ORoperand2 O i O MOV Operand2 operand1 is ignored BIC Operand1 AND NOT operand2 Bit clear MVN operand2 operandi is ignored The arithmetic operations SUB RSB ADD ADC SBC RSC CMP CMN treat each operand as a 32 bit integer either unsigned or 2 s complement signed the two are equivalent If the S bit is set and Rd is not R15 the V flag in the CPSR will be set if an overflow occurs into bit 31 of the result this may be ignored if the operands were considered unsigned but warns of a possible error if the operands were 2 s complement signed The C flag will be set to the carry out of bit 31 of the ALU the Z flag will be set if and only if the result was zero and the N flag will be set to the value of bit 31 of the result indicating a negative result if the operands are considered to be 2 s complement signed ELECTRONICS 3 11 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR SHIFTS When the second operand is specified to be a shifted register the operation of the barrel shifter is controlled by the Shi
84. the VM signal is configured to toggle on the every number of VLINE signal by the MVAL 7 0 value Figure 12 3 shows an example for MMODE 0 and for MMODE 1 with the value of MVAL 7 0 0x2 When MMODE 1 the VM rate is related to MVAL 7 0 as shown below VM Rate VLINE Rate 2 MVAL The VFRAME and VLINE pulse generation is controlled by the configurations of the HOZVAL field and the LINEVAL field in the LCDCON2 register Each field is related to the LCD size and display mode In other words the HOZVAL and LINEVAL can be determined by the size of the LCD panel and the display mode according to the following equation HOZVAL Horizontal display size Number of the valid VD data line 1 In color mode Horizontal display size 3 Number of Horizontal Pixel In case of 4 bit dual scan display the number of valid VD data line should be 4 and in case of 8 bit signal scan display mode the number of valid VD data lines should be 8 LINEVAL Vertical display size 1 In case of single scan display type LINEVAL Vertical display size 2 1 In case of dual scan display type The rate of VCLK signal can be controlled by the CLKVAL field in the LCDCON1 register The Table 12 1 defines the relationship of VCLK and CLKVAL The minimum value of CLKVAL is 2 VCLK Hz MCLK CLKVAL x 2 The frame rate is the VFRAM signal frequency The frame rate is closely related to the field of WLH VLINE pulse width WHLY the delay width of aft
85. the modified value will always overwrite the updated base if the base is in the list DATA ABORTS Some legal addresses may be unacceptable to a memory management system and the memory manager can indicate a problem with an address by taking the ABORT signal HIGH This can happen on any transfer during a multiple register load or store and must be recoverable if ARM7TDMI is to be used in a virtual memory system Abort during STM Instructions If the abort occurs during a store multiple instruction ARM7TDMI takes little action until the instruction completes whereupon it enters the data abort trap The memory manager is responsible for preventing erroneous writes to the memory The only change to the internal state of the processor will be the modification of the base register if write back was specified and this must be reversed by software and the cause of the abort resolved before the instruction may be retried Aborts during LDM Instructions When ARM7TDMI detects a data abort during a load multiple instruction it modifies the operation of the instruction to ensure that recovery is possible e Overwriting of registers stops when the abort happens The aborting load will not take place but earlier ones may have overwritten registers The PC is always the last register to be written and so will always be preserved base register is restored to its modified value if write back was requested This ensures recoverabil
86. to another state after PLL stabilization PUPS register and STOP SL_IDLE mode In STOP SL_IDLE mode the data bus D 31 0 or D 15 0 is Hi z state But because of the characteristics of I O pad the data bus pull up resistors have to be turned on to reduce the power consumption in STOP SL_IDLE mode D 31 16 pin pull up resistors can be controlled by PUPC and PUPD registers D 15 0 pin pull up resistors can be controlled by the PUPS register OUTPUT PORT State and STOP SL_IDLE mode If output is L the current will be consumed through the internal parasitic resistance if the output is H the current will not be consumed If a port is configured as an output port the current consumption can be reduced if the output state is H The output ports are recommended to be in H state to reduce STOP mode current consumption ADC Power Down The ADC has an additional power down bit in ADCCON If 53 44 enters the STOP mode the ADC should enter it s own power down mode 5 12 ELECTRONICS 53 44 RISC MICROPROCESSOR CLOCK amp POWER MANAGEMENT POWER MANAGEMENT STATE MACHINE SL_IDLE_BIT 1 EINT 7 0 RTC alarm IDLE_BIT 1 Interrupts EINT 7 0 RTC alarm NORMAL SLOW 0 IDLE BIT 0 amp STOP BIT 0 SLOW SLOW_BIT 1 EINT 7 0 RTC alarm STOP_BIT 1 STOP BIT 1 Figure 5 11 Power Management State Machine ELECTRONICS 5 13 CLOCK amp POWER MANAGEMENT 53 44 RISC MICROPROCESSOR CLOCK
87. transmitting the SIO data register SIODAT contains an 8 bit data value to be transmitted After transmitting is completed the SIODAT has the received data or dummy data SIODAT 0 01014004 SIO data register 0x00 SIODAT Description Initial State SIO DATA 7 0 This field contains the data to be transmitted or received over the 0x00 SIO channel SIO BAUD RATE PRESCALER REGISTER SBRDR The baud rate prescaler register SBRDR determines SIO clock rate baud rate as follows Baud rate MCLK 2 Prescaler value 1 R W SIO baud rate prescaler register 0x00 SBRDR 11 0 This field contains the prescaler value for the baud rate 0x00 SIO INTERVAL COUNT REGISTER IVTCNT Register Address SBRDR 0x01D14008 In the auto run mode the SIO inserts this interval after transmitting every 8 bit data Intervals between 8 bit data MCLK 4 IVTCNT 1 IVTCNT 0x01D1400C SIO interval counter register 0x00 7 0 SIO interval counter register 0x00 8 8 ELECTRONICS 53 44 RISC MICROPROCESSOR 510 SIO DMA COUNT ZERO REGISTER DCNTZ When SIO operates in DMA mode the corresponding DCNTZ bit has to be 0 initially When DMA terminal count is reached the corresponding DCNTZ bit has to be set to 1 DCNTZ 0x01D14010 SIO dma count zero register DCNTZ1 0 Enables BDMA1 service request When this bit is 0 the SIO can request the DMA service Disables BDMA1 service request DCNTZO Ena
88. unique number of the required coprocessor cd An expression evaluating to a valid coprocessor register number that is placed in the field lt Address gt can be 1 An expression which generates an address The assembler will attempt to generate an instruction using the PC as a base anda corrected immediate offset to address the location given by evaluating the expression This will be a PC relative pre indexed address If the address is out of range an error will be generated 2 A pre indexed addressing specification Rn offset of zero Rn expression offset of expression bytes 3 A post indexed addressing specification Rn lt expression offset of lt expression gt bytes write back the base register set the W bit if is present Hn is an expression evaluating to a valid register number NOTE If Rn is R15 the assembler will subtract 8 from the offset value to allow for ARM7TDMI pipelining EXAMPLES LDC p1 c2 table Load c2 of coproc 1 from address table using a PC relative address STCEQL p2 c3 R5 24 Conditionally store c3 of coproc 2 into an address 24 bytes up from R5 write this address back to R5 and use long transfer option probably to store multiple words NOTE Although the address offset is expressed in bytes the instruction offset field is in words The assembler will adjust the offset appropriately ELECTRONICS 3 55 ARM INSTRUCTION SET 53 44
89. user should write the same value into PLLCON register by S W The PLL begins the lockup sequence again toward the new frequency only after the S W configures the PLL with a new frequency Fout can be configured to be PLL output Fpllo immediately after lock time AM 2 PLL can operate after OM 3 2 is latched nRESET Y PLL is configured by S W first time Clock Disable lock time VCO is adapted to new clock frequency A The logic operates by OSC AA Pouvishewtiaquoncy clcok Figure 5 4 Power On Reset Sequence ELECTRONICS 5 5 CLOCK amp POWER MANAGEMENT 53 44 RISC MICROPROCESSOR Change PLL Settings In Normal Operation Mode During the operation of S3CA4BOX in Normal mode if the user wants to change the frequency by writing the PMS value the PLL lock time is automatically inserted During the lock time the clock is not supplied to the internal blocks 53 440 The timing diagram is as follow PLL_CLK PMS setting PLL Lock time FOUT It changes to new PLL clock after lock time automatically Figure 5 5 The Case that Changes Slow Clock by Setting PMS Value 5 6 ELECTRONICS 53 44 RISC MICROPROCESSOR CLOCK amp POWER MANAGEMENT POWER MANAGEMENT The power management block controls the system clocks by software for reduction of power consumption in 53 44 These schemes are related to PLL clock control logic peripheral clock control and wake up signal
90. video data and to generate the necessary control signals such as VFRAME VLINE and VM As well as the control signals S3C44BOX has the data ports of video data which are VD 7 0 as shown in Fig 12 1 The LCD controller consists of a REGBANK LCDCDMA VIDPRCS and TIMEGEN See Figure 12 1 LCD Controller Block Diagram The REGBANK has 18 programmable register sets which are used to configure the LCD controller The LCDCDMA is a dedicated DMA which it can transfer the video data in frame memory to LCD driver automatically By using this special DMA the video data can be displayed on the screen without CPU intervention The VIDPRCS receives the video data from LCDCDMA and sends the video data through the VD 7 0 data ports to the LCD driver after changing them into a suitable data format for example 4 8 bit single scan or 4 bit dual scan display mode The TIMEGEN consists of programmable logic to support the variable requirement of interface timing and rates commonly found in different LCD drivers The TIMEGEN block generates VFRAME VLINE VCLK VM and so on The description of data flow is as follows FIFO memory is present in the LCDCDMA When FIFO is empty or partially empty LCDCDMA requests data fetching from the frame memory based on the burst memory transfer mode Consecutive memory fetching of 4 words 16 bytes per one burst request without allowing the bus mastership to another bus master during the bus transfer When this kind o
91. with Link type operation is required THE LINK BIT Branch with Link BL writes the old PC into the link register R14 of the current bank The PC value written into R14 is adjusted to allow for the prefetch and contains the address of the instruction following the branch and link instruction Note that the CPSR is not saved with the PC and R14 1 0 are always cleared To return from a routine called by Branch with Link use MOV PC R14 if the link register is still valid or LDM Rn PC if the link register has been saved onto a stack pointed to by Rn INSTRUCTION CYCLE TIMES Branch and Branch with Link instructions take 2S 1N incremental cycles where S and N are defined as sequential S cycle and internal ELECTRONICS 3 7 ARM INSTRUCTION SET ASSEMBLER SYNTAX Items 1 are optional Items in lt gt must be present B L cond lt expression gt L cond lt expression gt EXAMPLES here BAL CMP BEQ ADDS BLCC 3 8 53 44 RISC MICROPROCESSOR Used to request the Branch with Link form of the instruction If absent R14 will not be affected by the instruction two character mnemonic as shown in Table 3 2 absent then AL ALways will be used The destination The assembler calculates the offset here there R1 0 fred sub ROM R1 1 sub Assembles to OxEAFFFFFE note effect of PC offset Always condition used as default Compare R1 with zero and branch
92. 0 Source Destination Register 5 3 Source Register 2 9 6 Opcode Figure 3 33 Format 4 OPERATION The following instructions perform ALU operations on a Lo register pair NOTE All instructions in this group set the CPSR condition codes Table 3 11 Summary of Format 4 Instructions THUMB Assembler ARM Equipment __________ Set condition codes on Rd AND Rs 1001 NEG Rs RSBS Rs 0 Rs 07 3 74 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 11 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES EOR R3 R4 EOR R4 and set condition codes ROR R1 RO Rotate Right R1 by the value in RO store the result in R1 and set condition codes NEG R5 R3 Subtract the contents of R3 from zero Store the result in R5 Set condition codes ie R5 CMP R2 R6 Setthe condition codes on the result of R2 R6 MUL RO R7 RO R7 RO and set condition codes ELECTRONICS 3 75 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR FORMAT 5 HI REGISTER OPERATIONS BRANCH EXCHANGE 14 11 11111 T oe 2 0 Destination Register 5 3 Source Register 6 Hi Operand Flag 2 7 Hi Operand Flag 1 9 8 Opcode Figure 3 34 Format 5 OPERATION T
93. 01 Output 010 TxD1 100 IISDO Others Reserved 001 Output 010 nRTS1 PF4 9 8 00 Input 10 nXBREQ PF3 7 6 00 Input 10 PF2 5 4 00 Input 10 nWAIT PF1 3 2 00 Input 10 01 Output 11 nXDREQO 01 Output 11 nXDACKO 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved PFO 1 0 00 Input 10 IICSCL PF 8 0 8 0 When the port is configured as an input port the corresponding bit is the pin state When the port is configured as an output port the pin state is the same as the corresponding bit When the port is configured as a functional pin the undefined value will be read wu m 0 PF 8 0 8 0 0 the pull up resistor attached to the corresponding port pin is enabled 1 the pull up resistor is disabled 8 12 ELECTRONICS 53 44 RISC MICROPROCESSOR PORTS PORT G CONTROL REGISTERS PCONG PDATG PUPG Port G control registers are shown in Table 8 8 If PGO PG7 are to be used for wake up signals in power down mode the ports will be set in the interrupt mode PCONG 0x01D20040 Configures the pins of port G PDATG 0x01D20044 The data register for port G PUPG 0x01D20048 Pull up disable register for port G Table 8 8 Port of Group G Control Registers PCONG PDATG PUPG 15 14 Input 01 Output IISLRCK 11 13 12 Input 01 Output oe IISDO 11 EINT6 11 10 Input
94. 1 Output TOUT2 11 TCLK in 9 8 Input 01 Output rn TOUT1 11 TCLK in 7 6 Input 01 Output i TOUTO 11 Reserved 5 4 Input 01 Output RxDO 11 Reserved 3 2 Input 01 Output TxDO 11 Reserved 1 0 Input 01 Output 105 Fpllo out 11 Fout out NOTE Please refer to Fig 5 1 when selecting or Fout PE 8 0 8 0 When the port is configured as an output port the pin state is the same as the corresponding bit When the port is configured as a functional pin the undefined value will be read mme 88122222 7 0 7 0 0 the pull up resistor attached to the corresponding port pin is enabled 1 the pull up resistor is disabled PE8 do not have programmable pull up resistor ELECTRONICS 8 11 PORTS 3C44B0X RISC MICROPROCESSOR PORT F CONTROL REGISTERS PCONF PDATF PUPF Port F control registers are shown in Table 8 7 below PCONF 0x01D20034 Configures the pins of port F 0x0000 PDATF 0x01D20038 The data register for port F PUPF 0x01D2003C pull up disable register for port F 0x000 Table 8 7 Port of Group F Control Registers PCONF PDATF PUPF PF8 21 19 000 Input 001 Output 010 nCTS1 011 SIOCLK 100 IISCLK Others Reserved PF7 18 16 000 Input 001 Output 010 RxD1 011 SIORxD 100 IISDI Others Reserved PF6 15 13 000 Input 011 SIORDY PF5 12 10 000 Input 011 SIOTxD 100 IISLRCK Others Reserved 0
95. 11 PROGRAMMER S MODEL 53 44 RISC MICROPROCESSOR IRQ The IRQ Interrupt Request exception is a normal interrupt caused by a LOW level on the nIRQ input IRQ has a lower priority than FIQ and is masked out when a FIQ sequence is entered It may be disabled at any time by setting the bit in the CPSR though this can only be done from a privileged non User mode Irrespective of whether the exception was entered from ARM or Thumb state an IRQ handler should return from the interrupt by executing SUBS PC R14 4 Abort An abort indicates that the current memory access cannot be completed It can be signalled by the external ABORT input ARM7TDMI checks for the abort exception during memory access cycles There are two types of abort Prefetch abort occurs during an instruction prefetch Data abort occurs during data access If a prefetch abort occurs the prefetched instruction is marked as invalid but the exception will not be taken until the instruction reaches the head of the pipeline If the instruction is not executed for example because a branch occurs while it is in the pipeline the abort does not take place If a data abort occurs the action taken depends on the instruction type Single data transfer instructions LDR STR write back modified base registers the Abort handler must aware of this swap instruction SWP is aborted as though it had not been executed
96. 2 Display 16gray bar in LCD 3 Change the frame rate into an optimal value 4 Change the VM alternating period to get the best quality 5 some gray level quality is not good select the good gray levels which is displayed well on your LCD ELECTRONICS 12 27 LCD CONTROLLER 53 44 RISC MICROPROCESSOR NOTES 12 28 ELECTRONICS 53 44 RISC MICROPROCESSOR A D CONVERTER OVERVIEW A D CONVERTER 10 bit CMOS ADC Analog to Digital Converter of 53 44 consists of a 8 channel analog input multiplexer auto zeroing comparator clock generator 10 bit successive approximation register SAR and output register This ADC provides software selection power down sleep mode FEATURES Resolution 10 bit Differential Linearity Error 1 LSB Integral Linearity Error 2 LSB Max 3 LSB Maximum Conversion Rate 100 KSPS Input voltage range 0 2 5V Input bandwidth 0 100 Hz without S H sample amp hold circuit Low Power Consumption ELECTRICS A D CONVERTER 53 44 RISC MICROPROCESSOR A D CONVERTER OPERATION BLOCK DIAGRAM Figure 13 1 shows the functional block diagram of 53 440 A D converter Note that the reference positive voltage REFT and reference negative voltage RETB are applied internally by A D converter power supply and ground so no power is applied to REFT and REFB pins Also REFT REFB and analog common voltage VCOM should be connected
97. 2 This bit determines WAIT status for bank 5 0 WAIT disable 1 WAIT enable DW5 21 20 These two bits determine data bus width for bank 5 00 8 bit 01 16 bit 10 32 bit ST4 19 This bit determines SRAM for using UB LB for bank 4 0 Not using UB LB Pin 14 11 is dedicated nWBE 3 0 1 Using UB LB Pin 14 11 is dedicated nBE 3 0 WS4 18 This bit determines WAIT status for bank 4 0 WAIT disable 1 WAIT enable DW4 17 16 These two bits determine data bus width for bank 4 00 8 bit 01 16 bit 10 32 bit 4 12 ELECTRENICS 53 44 RISC MICROPROCESSOR MEMORY CONTROLLER BUS WIDTH amp WAIT CONTROL REGISTER BWSCON Continued 00000000 ST3 15 This bit determines SRAM for using UB LB for bank 3 0 Not using UB LB Pin 14 11 is dedicated nWBE 3 0 1 Using UB LB Pin 14 11 is dedicated nBE 3 0 WS3 14 This bit determines WAIT status for bank 3 0 WAIT disable 1 WAIT enable DW3 13 12 These two bits determine data bus width for bank 3 00 8 bit 01 16 bit 10 32 bit 512 11 This bit determines SRAM for using UB LB for bank 2 0 Not using UB LB Pin 14 11 is dedicated nWBE 3 0 1 Using UB LB Pin 14 11 is dedicated nBE 3 0 10 This bit determines WAIT status for bank 2 0 WAIT disable 1 WAIT enable psum two bits determine data bus width for bank 2 8 bit 01 16 bit 10 32 bit This bit determines SRAM for using UB LB
98. 2 3 5 DPA 7 and 12 7 LCD CONTROLLER 53 44 RISC MICROPROCESSOR DP1_2 The pre dithered data 1111b has a dithering data 1 because the duty rate is 1 pre dithered data 00000 has a dithering data 0 because the duty rate is 0 The pre dithered data from 0001b to 1110b refer to DP6_7 DP4_5 DP5_7 DP3_4 DP2_3 DP3_5 DP4_7 and DP1_2 registers for dithering data The dithering data are used to do FRC The DP6_7 DP4_5 5 7 4 DP2_3 DP3_5 DP4_7 and DP1 2 registers can also determine the duty rates such as 6 7 4 5 5 7 3 4 2 3 3 5 and 4 7 respectively For examples 1 7 can be made by inverting 6 7 Table 12 3 Recommended Dithering Pattern Pattern Number of Recommened Pattern Name Bits 1010 0101 1010 0101 5 1011 1010 0101 1101 1010 0110 0101 65 1010 0101 1010 0101 1111 1101 0110 1011 OxD6B 1110 1011 0111 1011 0101 1110 1101 0111 1101 1011 1110 OX7DBE 0111 1110 1011 1101 1111 0x7EBDF 0111 1111 1101 1111 1011 1111 1110 7 5th FRAME 10th FRAME 4th FRAME 9th FRAME 3rd FRAME 8th FRAME 2nd FRAME 7th FRAME 1st FRAME eth FRAME 11th FRAME NOTE This figure is only explanation The real operation is some different Figure 12 2 The example of DP3 5 pattern 12 8 ELECTRONICS 53 44 RISC MICROPROCESSOR LCD CONTROLLER LCD Self Refresh M
99. 46 Format 17 OPERATION The SWI instruction performs a software interrupt On taking the SWI the processor switches into ARM state and enters Supervisor SVC mode The THUMB assembler syntax for this instruction is shown below Table 3 24 The SWI Instruction THUMB assembler ARM equivalent Action SWI Value 8 SWI Value 8 Perform Software Interrupt Move the address of the next instruction into LR move CPSR to SPSR load the SWI vector address 0x8 into the PC Switch to ARM state and enter SVC mode NOTE Value8 is used solely by the SWI handler it is ignored by the processor INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 24 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES SWI 18 Take the software interrupt exception Enter Supervisor mode with 18 as the requested SWI number ELECTRONICS 3 99 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR FORMAT 18 UNCONDITIONAL BRANCH 15 14 13 10 i 12 11 ce 10 0 Immediate Value Figure 3 47 Format 18 OPERATION This instruction performs a PC relative Branch The THUMB assembler syntax is shown below The branch offset must take account of the prefetch operation which causes the PC to be 1 word 4 bytes ahead of the current instruction Table 3 25 Summary of Branch Instruction THUMB
100. 5 S H 0 SWP instruction 1 Unsigned halfword 1 1 Signed byte Signed halfword 11 8 Immediate Offset High Nibble 15 12 Source Destination Register 19 16 Base Register 20 Load Store 0 Store to memory 1 Load from memory 21 Write back 0 No write back 1 Write address into base 23 Up Down 0 Down subtract offset from base 1 Up add offset to base 24 Pre Post Indexing 0 Post add subtract offset after transfer 1 Pre add subtract offset bofore transfer 31 28 Condition Field Figure 3 17 Halfword and Signed Data Transfer with Immediate Offset and Auto Indexing OFFSETS AND AUTO INDEXING The offset from the base may be either a 8 bit unsigned binary immediate value in the instruction or a second register The 8 bit offset is formed by concatenating bits 11 to 8 and bits 3 to 0 of the instruction word such that bit 11 becomes the MSB and bit 0 becomes the LSB The offset may be added to U 1 or subtracted from U 0 the base register Rn The offset modification may be performed either before pre indexed P 1 or after post indexed P 0 the base register is used as the transfer address The W bit gives optional auto increment and decrement addressing modes The modified base value may be written back into the base W 1 or the old base may be kept W 0 In the case of post indexed addressing the write back bit is redundant and is always set to zero since the old base value can be reta
101. 5 0 Setting count observation value for Timer 2 0x00000000 observation register ELECTRENICE 9 17 PWM TIMER 53 44 RISC MICROPROCESSOR TIMER 3 COUNT BUFFER REGISTER amp COMPARE BUFFER REGISTER TCNTB3 TCMPB3 TCNTB3 0 01050030 Timer 3 count buffer register 0x00000000 TCMPB3 0x01D50034 Timer 3 campare buffer register 0x00000000 Timer 3 compare Setting compare buffer value for Timer 3 0x00000000 buffer register NOTE This value must be smaller than TCNTB3 Timer 3 count buffer 15 0 Setting count buffer value for Timer 3 0x00000000 register TIMER 3 COUNT OBSERVATION REGISTER TCNTO3 0 01050038 __ ___ Timer count observation register 0x00000000 Timer 3 15 0 Setting count observation value for Timer 3 0x00000000 observation register 9 18 ELECTRONICS 53 44 RISC MICROPROCESSOR PWM TIMER TIMER 4 COUNT BUFFER REGISTER amp COMPARE BUFFER REGISTER TCNTB4 TCMPB4 TCNTB4 0 0105003 Timer 4 count buffer register 0x00000000 TCMPB4 0x01D50040 Timer 4 campare buffer register 0x00000000 Timer 4 compare Setting compare buffer value for Timer 4 0x00000000 buffer register NOTE This value must be smaller than TCNTB4 Timer 4 count buffer 15 0 Setting count buffer value for Timer 4 0x00000000 register TIMER 4 COUNT OBSERVATION REGISTER TCNTO4 TCNTO4 0x01D50044 oR Timer 4 count observation register 0x00000000 Timer 4 15 0 Setting count ob
102. 53 44 RISC MICROPROCESSOR UART BAUD RATE DIVISION REGISTER The value stored in the baud rate divisor register UBRDIV is used to determine the serial Tx Rx clock rate baud rate as follows UBRDIVn round_off MCLK bps x 16 1 where the divisor should be from 1 to 25 1 For example if the baud rate is 115200 bps and MCLK is 40 MHz UBRDIVn is UBRDIVn int 40000000 115200 x 16 0 5 1 int 21 7 0 5 1 22 1 21 27 UBRDIVO 0x01D00028 R W Baud rate divisior register 0 UBRDIVi 0 01004028 R W Baud rate divisior register 1 UBRDIV 15 0 Baud rate division value UBRDIVn gt 0 10 18 ELECTRONICS 53 44 RISC MICROPROCESSOR INTERRUPT CONTROLLER 1 1 INTERRUPT CONTROLLER OVERVIEW The interrupt controller in 53 44 receives the request from 30 interrupt sources These interrupt sources are provided by internal peripherals such as the DMA controller UARTand SIO etc In these interrupt sources the four external interrupts EINT4 5 6 7 are OR ed to the interrupt controller The UARTO and 1 Error interrupt are OR ed as well The role of the interrupt controller is to ask for the FIQ or IRQ interrupt request to the ARM7TDMI core after making the arbitration process when there are multiple interrupt requests from internal peripherals and external interrupt request pins Originally ARM7TDMI core only permits the FIQ or IRQ interrupt which is the arbitration proces
103. 53 44 RISC MICROPROCESSOR PRODUCT OVERVIEW PRODUCT OVERVIEW INTRODUCTION SAMSUNG s 53 44 16 32 bit RISC microprocessor is designed to provide a cost effective and high performance micro controller solution for hand held devices and general applications To reduce total system cost S3C44BOX also provides the following 8KB cache optional internal SRAM LCD controller 2 channel UART with handshake 4 channel DMA System manager chip select logic FP EDO SDRAM controller 5 channel timers with PWM ports 8 channel 10 bit ADC IIC BUS interface IIS BUS interface Sync SIO interface and PLL for clock The 53 44 was developed using a ARM7TDMI core 0 25 um CMOS standard cells a memory compiler Its low power simple elegant and fully static design is particularly suitable for cost sensitive and power sensitive applications Also S3C44BOX adopts a new bus architecture SAMBA II SAMSUNG ARM CPU embedded Microcontroller Bus Architecture An outstanding feature of the S3C44BOX is its CPU core 16 32 bit ARM7TDMI RISC processor 66 2 designed by Advanced RISC Machines Ltd The architectural enhancements of ARM7TDMI include the Thumb de compressor an on chip ICE breaker debug support and a 32 bit hardware multiplier By providing a complete set of common system peripherals the S3C44BOX minimizes overall system costs and eliminates the need to configure additional components The integrated on c
104. 6cycle NOTE The status of nWait is checked at Tacc 1 cycle Figure 19 16 External nWAIT READ Timing Tacs 0 Tcos 0 Tacc 6 Toch 0 Tcah 0 PMC 0 ST 0 1800 Figure 19 17 External nWAIT WRITE Timing Tacs 0 Tcos 0 Tacc 4 Toch 0 Tcah 0 PMC 0 ST 0 19 14 ELECTRONICS ELECTRICAL DATA 53 44 RISC MICROPROCESSOR HOH HHH 5001 gt 991 seo 91 seo 491 441 vivd Figure 19 18 DRAM EDO Burst READ Timing 10b DW 16bit 2 Tcas 1 Tcp 1 Trp 3 5 MT Tred 19 15 ELECTRONICS ELECTRICAL DATA 53 44 RISC MICROPROCESSOR 19 16 E tHZD Burg 4 tHZD k tHZD HZ amp XnBRQS IXnBRQH i XnBREQ 1 TXnBRQL 7 IXnBACKD 1 10 txnBackD XnBACK Figure 19 19 External Bus Request in DRAM Cycle Trcd 3 Tcas 2 Tcp 1 Trp 4 5 IDRCD Tcas 3 gt e 00 Figure 19 20 DRAM FP Single READ Timing Trcd 3 Tcas 2 Tcp 1 Trp 4 5 MT 01b ELECTRONICS 53 44 RISC MICROPROCESSOR ELECTRICAL DATA 24 Figure 19 21 DRAM EDO Single READ Timing Trcd 3 Tcas 2 Tcp 1 Trp 4 5 MT 10b ADDR 2 pop qp od tDRD nOE nWE Figure 19 22 DRAM CBR Refresh Timing Tchr 4 ELECTRONICS 19 17 53 44 RISC MICROPROCESSOR ELECTRICAL DATA Saas 4 aoa
105. 9 LOCK TIME COUNT REGISTER LOCKTIME LOCKTIME 0x01D8000C PLL lock time count register Oxfff LTIME CNT 11 0 PLL lock time count value Oxfff q o 53 44 RISC MICROPROCESSOR CLOCK amp POWER MANAGEMENT NOTES ELECTRONICS 5 17 53 44 RISC MICROPROCESSOR CPU WRAPPER amp BUS PRIORITIES CPU WRAPPER amp BUS PRIORITIES OVERVIEW The CPU wrapper consists of a cache write buffer and CPU core The bus arbitration logic determines the priority of each bus master The CPU wrapper has an 8 Kbyte internal memory The internal memory can be used in three ways First the 8 Kbyte memory can be used as an 8KB unified instruction data cache Second the internal memory can be used as a 4 Kbyte unified cache and a 4 Kbyte internal SRAM Third the internal memory can be used wholly as an 8 Kbyte internal SRAM The internal unified instruction data cache adopts four way set associative architecture with a four word 16 bytes line size It has a write through policy to keep data coherency When a cache miss occurs four words of memory are fetched sequentially from external memory It has an LRU Least Recently Used algorithm to raise the hit ratio The unified cache deals with instruction and data by distinguishing them The internal SRAM mainly will be used to reduce ISR interrupt service routine execution time ISR execution time will be reduced because the internal SRAM has the fa
106. AL 15 0 in BLUELUT Blue Lookup Table register as same as blue lookup table in color mode The gray level 0 will be denoted by 3 0 value If BLUEVAL 3 0 is 9 level 0 will be represented by gray level 9 among 16 gray levels If 3 0 is 15 level 0 will be represented by gray level 15 among 16 gray levels and so on As same as in the case of level 0 level 1 will also be denoted by BLUEVAL 7 4 the level 2 by BLUEVAL 11 8 and the level by BLUEVAL 15 12 These four groups among BLUEVAL 15 0 will represent level 0 level 1 level 2 and level 3 In 16 gray levels of course there is no selection as in the 4 gray levels ELECTRIDNICS 12 5 LCD CONTROLLER 53 44 RISC MICROPROCESSOR Color Mode Operation LCD controller in 53 44 can support an 8 bit per pixel 256 color display mode The color display mode can generate 256 levels of color using the dithering algorithm and FRC The 8 bit per pixel are encoded into 3 bits for red 3 bits for green and 2 bits for blue The color display mode uses separate lookup tables for red green and blue Each lookup table uses the REDVAL 31 0 REDLUT register GREENVAL 31 0 of GREENLUT register and 15 0 of BLUELUT register as the programmable lookup table entries Similarly with the gray level display 8 group or field of 4 bits in the REDLUR register i e REDVAL 31 28 REDLUT 27 24 REDLUT 23 20 REDLUT 19 16 REDLUT 15 12 REDLUT 11
107. Block data transfer instructions LDM STM complete If write back is set the base is updated If the instruction would have overwritten the base with data ie it has the base in the transfer list the overwriting is prevented All register overwriting is prevented after an abort is indicated which means in particular that R15 always the last register to be transferred is preserved in an aborted LDM instruction The abort mechanism allows the implementation of a demand paged virtual memory system In such a system the processor is allowed to generate arbitrary addresses When the data at an address is unavailable the Memory Management Unit MMU signals an abort The abort handler must then work out the cause of the abort make the requested data available and retry the aborted instruction The application program needs no knowledge of the amount of memory available to it nor is its state in any way affected by the abort After fixing the reason for the abort the handler should execute the following irrespective of the state ARM or Thumb SUBS PC R14_abt 4 prefetch abort or SUBS PC R14_abt 8 for a data abort This restores both the PC and the CPSR and retries the aborted instruction 2 12 ELECTRONICS 53 44 RISC MICROPROCESSOR PROGRAMMER S MODEL Software Interrupt The software interrupt instruction SWI is used for entering Supervisor mode usually to request a particular supervisor function A SWI handler
108. C MICROPROCESSOR Multiply by 3 and then by 2 Multiply by 5 Multiply by 2 and add in next digit This is not quite optimal but close An example of its non optimality is multiply by 45 which is done by RSB Rb Ra Ra LSL 2 RSB Rb Ra Rb LSL 2 ADD Rb Ra Rb LSL 2 rather than by ADD ADD 3 62 Rb Ra Ra LSL 3 Rb Rb Rb LSL 2 Multiply by 3 Multiply by 4 3 1 11 Multiply by 4 11 1 45 Multiply by 9 Multiply by 5 9 45 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET LOADING A WORD FROM AN UNKNOWN ALIGNMENT BIC LDMIA AND MOVS MOVNE RSBNE ORRNE ELECTRONICS Rb Ra 3 Rb Rd Rc Rb Ra 3 Rb Rb LSL 3 Rd Rd LSR Rb Rb Rb 32 Rd Rd Rc LSL Rb Enter with address in Ra 32 bits uses Rb result in Rd Note must be less than e g 0 1 Get word aligned address Get 64 bits containing answer Correction factor in bytes how in bits and test if aligned Produce bottom of result word if not aligned Get other shift amount Combine two halves to get result 3 63 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR NOTES 3 64 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET THUMB INSTRUCTION SET FORMAT The thumb instruction sets are 16 bit versions of ARM instruction sets 32 bit format The ARM instructions are reduced to 16 bit versions Thumb instructions at the cost of versatile functions of the ARM instruction sets The thumb instructions are d
109. CMPn TCNTBn and TCMPBn are loaded into TCNTn and TCMPn when the timer reaches 0 When TCNTn reaches 0 the interrupt request will occur if the interrupt is enabled TCNTn and TCMPn are the names of the internal registers The TCNTn register can be read from the TCNTOn register ELECTRENICS 9 3 PWM TIMER 53 44 RISC MICROPROCESSOR AUTO RELOAD amp DOUBLE BUFFERING 53 44 PWM Timers have a double buffering feature which can change the reload value for the next timer operation without stopping the current timer operation So although the new timer value is set a current timer operation is completed successfully The timer value can be written into TCNTBn timer counter buffer register and the current counter value of the timer can be read from TCNTOn timer count observation register If TCNTBn is read the read value is not the current state of the counter but the reload value for the next timer duration The auto reload is the operation which copies the TCNTBn into TCNTn when TCNTn reaches 0 The value written into TCNTBn is loaded to TCNTn only when the TCNTn reaches to 0 and auto reload is enabled If the TCNTn is 0 and the auto reload bit is 0 the TCNTn does not operate any further Write Write TONTBn 100 TCNTBn 200 Start TCNTBn 150 Auto reload 4 4 Mo tM 150 100 100 Interrupt Figure 9 3 Example of Double Bufferin
110. CON RTCALM PMWKUP PWDN ALMINT Figure 14 1 Real Time Clock Block Diagram LEAP YEAR GENERATOR This block can determine whether the last date of each month is 28 29 30 or 31 based on data from BCDDAY BCDMON and BCDYEAR This block considers the leap year in deciding on the last date An 8 bit counter can only represent 2 BCD digits so it cannot decide whether 00 year is a leap year or not For example it can not discriminate between 1900 and 2000 To solve this problem the RTC block in S3C44BOX has hard wired logic to support the leap year in 2000 Please note 1900 is not leap year while 2000 is leap year Therefore two digits of 00 53 44 denote 2000 not 1900 READ WRITE REGISTERS Bit 0 of the RTCCON register must be set in order to read and write the register in RTC block To display the sec min hour date month and year the CPU should read the data in BCDSEC BCDMIN BCDHOUR BCDDAY BCDDATE BCDMON and BCDYEAR registers respectively in the RTC block However a one second deviation may exist because multiple registers are read For example when the user reads the registers from BCDYEAR to BCDMIN the result is assumed to be 1959 Year 12 Month 31 Date 23 Hour and 59 Minute When the user read the BCDSEC register and the result is a value from 1 to 59 5 there is no problem but if the result is 0 sec the year month date hour and minute may be changed to 1960 Year 1 Month 1 Date O
111. D PDATD PUPD 15 14 Input 01 Output o VFRAME 11 Reserved 13 12 Input 01 Output a VM 11 Reserved 11 10 Input 01 Output va VLINE 11 Reserved 9 8 Input 01 Output ee VCLK 11 Reserved 7 6 Input 01 Output VD3 11 Reserved 5 4 Input 01 Output mis VD2 11 Reserved 3 2 Input 01 Output a VD1 11 Reserved 1 0 Input 01 Output VDO 11 Reserved PD 7 0 7 0 When the port is configured as an input port the corresponding bit is the pin state When the port is configured as an output port the pin state is the same as the corresponding bit When the port is configured as a functional pin an undefined value will be read Pub m PD 7 0 7 0 0 the pull up resistor attached to the corresponding port pin is enabled 1 the pull up resistor is disabled 8 10 ELECTRENICE 53 44 RISC MICROPROCESSOR PORTS PORT E CONTROL REGISTERS PCONE PDATE Port E control registers are shown in Table 8 6 PCONE 0x01D20028 Configures the pins of port E PDATE 0x01D2002C The data register for port E PUPE 0x01D20030 pull up disable register for port E Table 8 6 Port of Group E Control Registers PCONE PDATE PE8 17 16 00 Reserved ENDIAN 01 Output 10 CODECLK 11 Reserved PE8 can be used as ENDIAN only during the reset cycle 15 14 Input 01 Output nis TOUT4 11 VD7 13 12 Input 01 Output TOUT3 11 11 10 Input 0
112. DA line should be eight bits in length The number of bytes which can be transmitted per transfer is unlimited The first byte following a Start condition should have the address field The address field can be transmitted by the master when the is operating in master mode Each byte should be followed by an acknowledgement ACK bit The MSB bit of the serial data and addresses are always sent first Write Mode Format with 7 bit Addresses Slave Address 7bits DATA 1Byte 0 Write Data Transferred Data Acknowledge Write Mode Format with 10 bit Addresses Slave Address Slave Address Write Data Transferred Data Acknowledge Read Mode Format with 7 bit Addresses Slave Address 7 bits DATA 1 Read Data Transferred Data Acknowledge Read Mode Format with 10 bit Addresses Slave Address Slave Address Slave Address Read Read Data Transferred Data Acknowledge NOTES 1 58 Start rS Repeat Start Stop A Acknowledge 2 From Master to Slave Slave to Master Figure 16 3 IIC Bus Interface Data Format 16 4 ELECTRONICS 53 44 RISC MICROPROCESSOR IIC BUS INTERFACE Acknowledgement Acknowledgement Signal from Receiver Signal from Receiv 8 9 1 ACK Byte Complete Interrupt Clock Line Held Low While within Receiver Interrupts are Serviced Figure 16 4 Data Transfer on the ACK SIGNAL TRANSMISSION To finish a one byte trans
113. DATA ie 5081 HOH x 508 Figure 19 10 ROM SRAM Burst READ Timing Il DW 16bit 1 0 Tacc 2 Toch 0 Tcah 0 PMC 10b ST Tacs 0 Tcos ELECTRONICS 19 10 53 44 RISC MICROPROCESSOR ELECTRICAL DATA EXTCLK E J JUWU tHZD T 004113 gt tHZD Doc AZ tHZD aie J Ww 4 tXnBACKD XnBREQ 1 1 XnBACKD gt Figure 19 11 External Bus Request in ROM SRAM Cycle Tacs 0 Tcos 0 Tacc 8 Toch 0 Tcah 0 PMC 0 ST 0 ELECTRONICS 19 11 ELECTRICAL DATA 53 44 RISC MICROPROCESSOR RDS gt IRDH Figure 19 12 ROM SRAM READ Timing 1 Tacs 2 Tcos 2 Tacc 4 Tochz2 Tcahz2 PMC 0 ST 0 Figure 19 13 ROM SRAM READ Timing 1 Tacs 2 Tcos 2 Tacc 4 Toch 2 Tcah 2cycle PMC 0 ST 1 19 12 ELECTRONICS 53 44 RISC MICROPROCESSOR ELECTRICAL DATA Toch IRWBED RWBED Figure 19 14 ROM SRAM WRITE Timing 1 Tacs 2 Tcos 2 Tacc 4 Toch 2 Tcah 2 PMC 0 ST 0 Figure 19 15 ROM SRAM WRITE Timing 11 Tacs 2 Tcos 2 Tacc 4 Toch 2 Tcah 2 PMC 0 ST 1 ELECTRENICS 19 13 ELECTRICAL DATA 53 44 RISC MICROPROCESSOR EXTCLK delayed 4 9 Tacc
114. DMA ZDMA BDMA and an external bus master can be programmed by the SBUSCON register The CPU wrapper always has the lowest priority regardless of the SBUSCON register The round robin priority mode or fixed priority mode can be selected In the round robin priority mode the bus master which had once served will have the lowest priority In this way all the bus masters have equal priorities In the fixed priority mode each bus master s priority is written onto SBUSCON SBUSCON determines which is 1st Ath priority bus master ELECTRENICS 6 7 CPU WRAPPER amp BUS PRIORITIES 53 44 RISC MICROPROCESSOR CPU WRAPPER SPECIAL REGISTERS There are 3 control registers for the CPU wrapper block cache write buffer and ARM7TDMI SYSCFG register controls the general system operation registers provide non cacheable areas SYSTEM CONFIGURATION REGISTER SYSCFG SYSCFG 0x01C00000 System Cofiguration Register DA reserved DATA ABORT controls This bit is recommended to be 0 0 Enable data abort 1 Disable data abort RSE reserved Enable read stall option This bit is recommended to be 0 0 read stall disable 1 read stall enable Read stall option Insert one internal wait cycle when reading data for cache amp CPU core This bit determines write buffer enable disable Some external devices which require the minimum writing cycle time do not operate normally because the period between
115. DP 3 3V VDDI 2 5V Ta 25 C PLCAP 70pf max min typ 30 Table 19 11 DMA Controller Module Signal Timing Constants VDDP 3 3V VDDI 2 5V Ta 25 C PLCAP 70pf max min typ 30 eXternal Request Setup 3 eXternal Acknowledge Setup 3 aCcess to Ack Delay when Low transition U aCcess to Ack Delay when High transition 9 eXternal Acknowledge Delay tx 2 MCLK Width Acknowledge when Handshake mode 0 MCLK Width of Acknowledge high when Whole mode 2 MCLK Width of Acknowledge high when Whole and OTF twawo MCLK mode Width of Acknowledge when Demand mode twa 0 MCLK 19 42 ELECTRONICS 53 44 RISC MICROPROCESSOR ELECTRICAL DATA Table 19 12 LCD Controller Module Signal Timing Constants VDDP 3 3V VDDI 2 5V Ta 25 C PLCAP 70pf 4 P wakovoderme tm 3 wm 4 wmwEwvakcem me l Table 19 13 IIS Controller Module Signal Timing Constants VDDP 3 3V VDDI 2 5V Ta 25 C PLCAP 70pf 05 9 9 25 w 1 spm w 75 1 w I ooEceektemeny 3 hme Table 19 14 BUS Controller Module S
116. Default State State I O State TYPE Function BUS REQ STOP lnitial 36 ExINT2 nCTSO GPG2 GPG2 phbsu50ct8sm 37 ExINT3 nRTSO GPG3 GPG3 40 ExINT6 IISDO GPG6 GPG6 41 ExINT7 IISLRCK GPG7 GPG7 42 nTRST nTRST phis 49 CLKout GPEO GPEO lO phbsub ctBsm 50 nRESET nRESET EENN phis woe ow phbsu50ct8sm phbsu50cd4sm m 5 56 5 5 phsoscm16 1 lol 64 XTALO XTALO AK 5 65 EXTALO EXTALO PLLCAP PLLCAP phnc50 option 1 10 ELECTRONICS 53 44 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 1 160 Pin LQFP Pin Assignment Continued oem mm mew 9 Function BUS REQ STOP lnitial 2 om 2 T 5 lt 2 67 70 71 72 73 74 75 76 77 78 79 81 82 83 84 85 7 8 8 8 lt 50 9 d ELECTRENICE 1 11 PRODUCT OVERVIEW 53 44 RISC MICROPROCESSOR Table 1 1 160 Pin LQFP Pin Assignment Continued Function BUS REQ STOP lnitial eee 101 2 2 phbsu50ct12sm 05 DATA27 nCTS1 GPC11 06 DATA26 nRTS1 GPC10 DATA26 107 DATA25 nXDREQ1 GPC9 DATA25 6 9 0 108 DATA24 nXDACK1 GPC8 DATA24 _ 5 111 Hi z IO phbsu50ct12sm 5 oaTaeivosercs patazovorercs z owwe 2 x
117. GB EINT1 29 28 00 14 01 29 10 37 01 sGC EINT2 27 26 00 1 01 29 10 39 11 4 sGD EINT3 25 24 00 1 01 24 10 34 11 4 00 1 01 29 10 39 11 44 00000 00 1 01 29 10 39 11 4 00 15 01 2 10 34 11 4 00 17 01 24 11 16 ELECTRONICS 53 44 RISC MICROPROCESSOR INTERRUPT CONTROLLER 00 15 01 24 10 38 11 4 00 15 01 29 10 39 11 4 00 15 0 24 10 39 11 4 00 1 01 24 10 39 11 4 rari 00 15 01 29 10 35 11 4 o O 00 1 01 28 10 24 11 4 00 1 01 2 10 39 11 4 00 15 01 24 10 34 11 4 NOTE The items in I_PSLAVE must be configured with different priorities even if the corresponding interrupt source is not used ELECTRONICS 11 17 INTERRUPT CONTROLLER 53 44 RISC MICROPROCESSOR IRQ PRIORITY OF MASTER REGISTER 5 PMST determines the interrupt priorities among the 4 slave groups PMST 0 01 0014 IRQ priority of master register 0x00001f1b PMST Bit Description Initial State sss 12 Master operating mode 0 round robin 1 fix mode FxSLV A D 11 8 Slave operating mode 0 round robin 1 fix mode PMASTER 7 0 Fx mGA 11 Determines the operating mode of slave unit Fx mGB 10 Determines the operating mode of slave unit mGB Fx mGC Determines the operating mode of slave unit 9mGC 1 Fx mGD B Determines the operating mode of slave unit mGD
118. Interrupt DMA Request Generation Each UART of 53 44 has seven status Tx Rx Error signals Overrun error Parity error Frame error Break Receive FlFO buffer data ready Transmit FIFO buffer empty and Transmit shifter empty all of which are indicated by the corresponding UART status register UTRSTATn UERSTATn The overrun error parity error frame error and break condition are referred to as the receive error status each of which can cause the receive error status interrupt request if the receive error status interrupt enable bit is set to one in the control register UCONn When a receive error status interrupt request is detected the signal causing the request can be identified by reading UERSTSTn When the receiver transfers the data of the receive shifter to the receive FIFO it activates the receive FIFO full status signal which will cause the receive interrupt if the receive mode in control register is selected as the interrupt mode When the transmitter transfers data from its transmit FIFO to its transmit shifter the transmit FIFO empty status signal is activated The signal causes the transmit interrupt if the transmit mode in control register is selected as that interrupt mode The receive FIFO full and transmit FIFO empty status signals can also be connected to generate the DMA request signals if the receive transmit mode is selected as the DMA mode Table 10 1 Interrupts In Connection with FIFO FIFO Mode Non FIFO Mo
119. LCDBASEL is data of line 1 of virtual screen is the data of tye 1 of virtual screen data of line 2 of virtual screen is tha data of line 3 of virtual screen is the of line 4 of virtual 64 ELECTRONICS is the data of line 5 of virtual screen is the data of 6 of virtual screen is the data of line 7 d virtuaf screen is the data of line 8 of virttg is the data of line 9 of virtual screen is the data of line 10 of virtual screen is the data of line 11 of virtual screen Figure 12 6 Example of Scrolling in Virtual Display single scan is the data of line 5 of virtual 64 is the data of line 6 of virtual sqreen is the data of line 7 of virtual 64 This is the data of line 8 of virtual 64 This is the data of line 9 of virtual screen This is the data of line 10 of virtual screen This is the data of line 11 of virtual screen After Scrolling 12 15 LCD CONTROLLER 53 44 RISC MICROPROCESSOR LCD CONTROLLER SPECIAL REGISTERS LCD Control 1 Register LCDCON1 0x01F00000 LCD control 1 register 0x00000000 LINECNT read 31 22 These bits provide the status of the line counter 0000000000 only Down count from LINEVAL to 0 CLKVAL 21 12 These bits determine the rate of VCLK If this value can be 0000000000 changed when ENVID 1 the new value will be used next frame MCLK CLKVAL x 2 CLKVAL 2 2 WLH 11 10 These bits determine
120. Load Store Instructions THUMB assembler ARMequivalent Action STR lmm STR Rd R13 lmm Add unsigned offset 255 words 1020 bytes in Imm to the current value of the SP R7 Store the contents of Rd at the resulting address LDR LDR Rd R13 Imm Add unsigned offset 255 words 1020 bytes in Imm to the current value of the SP R7 Load the word from the resulting address into Rd NOTE The offset supplied in 1 is a full 10 bit address but must always be word aligned ie bits 1 0 set to 0 since the assembler places gt gt 2 in the Word8 field ELECTRONICS 3 89 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 18 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES STR R4 SP 492 Store the contents of R4 at the address formed by adding 492 to SP R13 Note that the THUMB opcode will contain 123 as the Word8 value 3 90 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET FORMAT 12 LOAD ADDRESS 0 14 GIDBISISD 51112 7 0 8 bit Unsigned Constant 10 8 Destination Register 11 Source 0 PC 1 SP Figure 3 41 Format 12 OPERATION These instructions calculate an address by adding an 10 bit constant to either the PC or the SP and load th
121. MB assembler syntax is shown in Table 3 8 NOTE All instructions in this group set the CPSR condition codes Table 3 8 Summary of Format 1 Instructions LSL Rd Rs Offset5 MOVS Rs LSL Offset5 Shift Rs left by a 5 bit immediate value and store the result in Rd 01 LSR Rad Rs Offset5 MOVS Rs LSR Offset5 Perform logical shift right on Rs by a 5 bit immediate value and store the result in Rd 10 ASR Rad Rs Offset5 MOVS Rd Rs ASR Perform arithmetic shift right on Rs Offset5 by a 5 bit immediate value and store the result in Rd 3 68 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 8 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES LSR R2 R5 27 Logical shift right the contents of R5 by 27 and store the result in R2 Set condition codes on the result ELECTRONICS 3 69 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR FORMAT 2 ADD SUBTRACT 15 14 13 11 10 12 9 8 6 5 3 2 0 _ Ra 2 0 Destination Register 5 3 Source Register 8 6 Register Immediate Vale 9 Opcode 10 Immediate Flag 0 Register operand 1 Immediate oerand Figure 3 31 Format 2 OPERATION These instructions allow the contents of a Lo
122. MSK bit was set To clear this problem clear the corresponding pending bit INTPND after changing INTMSK The 26 interrupt sources and global mask bit are summarized as follows INTMSK 0x01E0000C R W Determines which interrupt source is masked The masked interrupt source will not be serviced 0 Interrupt service is available 1 Interrupt service is masked IMPORTANT NOTES 1 INTMSK register can be masked only when it is sure that the corresponding interrupt does not be requested If your application should mask any interrupt mask bit INTMSK just when the corresponding interrupt is issued please contact our FAE field application engineer 2 f you need that all interrupt is masked we recommend that I F bits in CPSR are set using MRS MSR instructions The F bit in CPSR can be masked even when any interrupt is issued ELECTRONICS 11 13 53 44 RISC MICROPROCESSOR INTERRUPT CONTROLLER Global 0 Service available EINTO 0 Service available EINT1 0 Service available EINT2 0 Service available EINT3 0 Service available 17 0 Service available INT BDMA1 16 0 Service available INT WDT 15 0 Service available INT UERRO 1 14 0 Service available INT TIMERO 13 0 Service available INT 12 0 Service available INT TIMER2 11 0 Service available INT 10 0 Service available INT 4 9 0 Seice available INT
123. MST 0x01E0001C oR Current IRQ priority of master register 0x0000xx1b VECTOR The lower 6 bits of corresponding branch machine code C se 00 1 Ot 2nd 10 39 11 4th 00 18 Ot 2nd 10 39 11 4th 00 18 Ot 2nd 10 30 11 4th 00 18 01 204 10 39 11 4th 11 20 ELECTRONICS 53 44 RISC MICROPROCESSOR INTERRUPT CONTROLLER IRQ INTERRUPT SERVICE PENDING REGISTER ISPR _ISPR indicates the interrupt being currently serviced Although the several interrupt pending bits are all turned on only one bit will be turned on ISPR 0 01 00020 IRQ interrupt service pending register 0x00000000 EINTO 10 0 not serviced 1 serviced now 0 INT_TIMER4 METER 18 n 13 0 1 o rotseced 0 m te wane m o notserced 5 i B INTURXDO 7 ELECTRONICS 11 21 INTERRUPT CONTROLLER 53 44 RISC MICROPROCESSOR IRQ FIQ INTERRUPT SERVICE PENDING CLEAR REGISTER I ISPC F ISPC ISPC F_ISPC clears the interrupt pending bit INTPND _ISPC F_ISPC also informs the interrupt controller of the end of corresponding ISR interrupt service routine At the end of ISR interrupt service routine the corresponding pending bit must be cleared The bit of INTPND bit is cleared to z
124. O fq RIO fq D R11 fg D R12 D R13 RIA ARM State Program Status Registers PXSPSR svc P SPSR_abt XSPSR ira und b banked register Figure 2 3 Register Organization in ARM State 2 4 ELECTRONICS 53 44 RISC MICROPROCESSOR PROGRAMMER S MODEL The THUMB State Register Set The THUMB state register set is a subset of the ARM state set The programmer has direct access to eight general registers RO R7 as well as the Program Counter PC a stack pointer register SP a link register LR and the CPSR There are banked Stack Pointers Link Registers and Saved Process Status Registers SPSRs for each privileged mode This is shown in Figure 2 4 THUMB State General Registers and Program Counter System amp User FIQ Supervisor Abort IRQ Undefined THUMB State Program Status Registers banked register Figure 2 4 Register Organization in THUMB State ELECTRONICS 2 5 PROGRAMMER S MODEL 53 44 RISC MICROPROCESSOR The relationship between ARM and THUMB state registers The THUMB state registers relate to the ARM state registers in the following way THUMB state RO R7 and ARM state RO R7 are identical THUMB state CPSR and SPSRs and ARM state CPSR SPSRs are identical THUMB state SP maps onto ARM state R13 e THUMB state LR maps onto ARM state R14 The THUMB state Program Counter maps onto the ARM state Program Counter R15 This relati
125. O interrupt request is activated if a programmer enables an interrupt source Transmitting always occurs with reception If you want only to transmit you may treat the received data as dummy The transmission frequency is controlled by making the appropriate bit settings to the SIOCON and SBRDR registers The serial interface can be operated by an internal or external clock source If the internal clock signal is used you can modify its frequency to adjust the baud rate data register value Programming Procedure When a byte data is written into the SIODAT register SIO starts to transmit if the SIO run bit is set and the transmit mode bit is enabled To program the SIO modules follow these basic steps 1 Configure the I O pins at port SIOTXD SIOCLK SIORXD Set SIOCON register to properly configure the serial module For interrupt generation set the serial I O interrupt enable bit and refer the interrupt controller to 1 If you want to transmit data to the serial buffer write data to SIODAT For receiving transmitting set SIOCON 3 to 1 to start the shift operation Oak oD When the shift operation transmit receive is completed the SIO interrupt is requested and SIODAT has the received data or dummy data 7 goto step 4 18 2 ELECTRONICS 53 44 RISC MICROPROCESSOR 510 SIO DMA OPERATION Auto Run Mode non hand shaking mode If the SIO is in the auto run mode non hand shaking mode and the SIO transmits
126. OCK 53 44 RISC MICROPROCESSOR RTC ROUND RESET REGISTER RTCRST RTCRST 0x01D7006C L R W RTC round reset Register 0x0 0x01D7006F B by byte SRSTEN 3 Round second reset enable 0 Disable 1 Enable SECCR 2 0 Round boundary for second carry generation note 011 over than 30 sec 100 over than 40 sec 101 over than 50 sec NOTE Otherwise no second carry is generated BCD SECOND REGISTER BCDSEC BCDSEC 0x01D70070 L R W BCD second Register Undef 0x01D70073 B by byte 4 SECDATA 6 4 BCD value for second from 0 to 5 at roms SSCS BCD MINUTE REGISTER BCDMIN BCDMIN 0x01D70074 L R W BCD minute Register Undef 0x01D70077 B by byte 4 MINDATA 6 4 BCD value for minute 0105 89 mmoms 14 8 ELECTRONICS 53 44 RISC MICROPROCESSOR REAL TIME CLOCK BCD HOUR REGISTER BCDHOUR BCDHOUR 0x01D70078 L R W BCD hour Register Undef 0x01D7007B B by byte p 2 5 4 BCD value for hour from 0 to 2 BCD DAY REGISTER BCDDAY BCDDAY 0x01D7007C L R W BCD day Register Undef 0x01D7007F B by byte gp DAYDATA 5 4 BCD value for day from 0 to 3 BCD DATE REGISTER BCDDATE 0x01D70080 L R W BCD date Register Undef 0x01D70083 B by byte Ss DATEDATA 2 0 BCD value for date from 1 to 7 ELECTRONICS 14 9 REAL TIME CLOCK 53 44
127. OD QUO T IO X TX X OAA OOO X O01 QD E UT O00 1 X 0002 QUOD T HO O00 Q QUO OQ QUUD QUO OO OO 1 13 OOG WO AD XU 580 14 PRODUCT OVERVIEW Bottom View Figure 1 3 53 44 Pin Assignments 160 FBGA PRODUCT OVERVIEW 53 44 RISC MICROPROCESSOR Table 1 1 160 Pin LQFP Pin Assignment Default State 2 State 2 State 6 Function BUS REQ STOP lnitial ADDR3 ADDR3 ADDR2 ADDR2 ADDR1 ADDR1 H Hi z ADDRO GPAO ADDRO Hi z O nCASO nCASO H Low E _ 3 H Hi z nCAS2 nSCAS GPB2 nCAS3 nSRAS GPB3 VDDIO 10 vssio 11 nBEO nWBEO DQMO DOMO 12 nBE1 nWBE1 DQM1 7 High Low O 3 nBE2 nWBE2 DQM2 GPB4 DQM2 nBE3 nWBE3 DQM3 GPB5 A 5 5 m gt nGCS1 GPB6 Hi z O Hi z O 19 nGCS2 GPB7 20 nGCS3 GPB8 nGCs3 23 nGCS4 GPB9 nGCS4 Hi z O 24 nGCS5 GPB10 nGCS5 25 nGCS6 nSCSO nRASO nSCS0 H High High Low nGCS7 nSCS1 nRAS1 nSCS1 2 m 26 27 SCKE GPBO SCKE Hi z O Low O 28 SCLK GPB1 SCLK High O 29 nWAIT GPF2 nXDREQO nXBREQ GPF4 nXDACKO nXBACK GPF3 ExINTO VDA GPGO 30 ExINT1 VD5 GPG1 GPG1 2 2 3 2 2 31 32 33 53 44 RISC MICROPROCESSOR ELECTRONICS PRODUCT OVERVIEW 1 9 PRODUCT OVERVIEW 53 44 RISC MICROPROCESSOR Table 1 1 160 Pin LQFP Pin Assignment Continued
128. PD6 VLINE GPD5 VCLK GPD4 VD3 GPD3 VD2 GPD2 VD1 GPD1 VDO GPDO RxDO GPE2 TxDO GPE1 DATA31 nCTSO GPC15 DATASO nRTSO GPC14 DATA29 RxD1 GPC13 DATA28 TxD1 GPC12 DATA27 nCTS1 GPC1 1 DATA26 nRTS1 GPC10 DATA25 nXDREQ1 GPC9 DATA24 nXDACK1 GPC8 VDD VSS DATA23 VD4 GPC7 DATA22 VD5 GPC6 DATA21 VD6 GPC5 DATA20 VD7 GPC4 DATA19 IISCLK GPC3 DATA18 IISD GPC2 DATA17 IISDO GPC1 DATA16 IISLRCK GPCO DATA15 88 5685 8 96968655906 53 44 0 ExINT6 IISDO GPG6 ExINTS IISDI GPG5 ExINT4 IISCLK GPG4 ExINT3 nRTSO GPG3 ExINT2 nCTSO GPG2 VSS VDD ExINT1 VD5 GPG1 ExINTO VD4 GPGO nXDACKO nXBACK GPF3 nXDREQO nXBREQ GPF4 nWAIT GPF2 SCLK GPB1 SCKE GPBO nGCS7 nSCS1 nRAS1 nGCS6 nSCS0 nRASO nGCS5 GPB10 nGCS4 GPB9 VSS VDD nGCS3 GPB8 nGCS2 GPB7 nGCS1 GPB6 nGCS0 nWE nOE nBE3 nWBE3 DQM3 GPB5 nBE2 nWBE2 DQM2 GPB4 nBE1 nWBE1 DQM1 nBEO nWBEO DQMO VSSIO VDDIO nCAS3 nSRAS GPB3 nCAS2 nSCAS GPB2 nCAS1 nCASO ADDRO GPAO ADDR1 ADDR2 ts 160 LQFP ignmen S3C44BOX Pin Ass 2 Figure 1 PRODUCT OVERVIEW PIN ASSIGNMENTS M C DATA14 ADDR3 VSSIO 126 GPA6 5 4 IGPA2 ADDR24 GPAQ ADDR23 GPA8 ADDR22 GPA7 ADDR21 ADDR20 ADDR19 ADDRI8 ADDRI7 1 6 53 44 RISC MICROPROCESSOR ELECTRONICS O O O 6 Ball Pad A1 x Corner Indicator O XO 22905655 OQ OX OO OO
129. Parity forced checked as 0 Number of stop bit The number of stop bits specifies how many stop bits are to be used to signal end of frame 0 One stop bit per frame 1 Two stop bit per frame Word length 1 0 The word length indicates the number of data bits to be transmitted or received per frame 00 5 bits 01 6 bits 10 7 bits 11 8 bits 10 10 ELECTRONICS 53 44 RISC MICROPROCESSOR UART CONTROL REGISTER There are two UART control registers UCONO in the UART block UCONO 0 01000004 UART channel 0 control register UCON1 0x01D04004 UART channel 1 control register Tx interrupt type Rx interrupt type Rx time out enable Rx error status interrupt enable Loop back Mode Send Break Signal Transmit Mode Receive Mode ELECTRONICS Interrupt request type 0 Pulse Interrupt is requested the instant Tx buffer becomes empty 1 Level Interrupt is requested while Tx buffer is empty Interrupt request type 0 Pulse Interrupt is requested the instant Rx buffer receives the data 1 Level Interrupt is requested while Rx buffer is receiving data Enable Disable Rx time out interrupt when UART FIFO is enabled The interrupt is a receive interrupt 0 Disable 1 Enable This bit enables the UART to generate an interrupt if an exception such as a break frame error parity error or overrun error occurs during a receive operation 0 Do not generate receive error st
130. R INTERRUPT CONTROLLER INTERRUPT CONTROLLER SPECIAL REGISTERS INTERRUPT CONTROL REGISTER INTCON INTCON 0x01E00000 Interrupt control Register 0 7 a This bit disables enables vector mode for IRQ 0 Vectored interrupt mode 1 Non vectored interrupt mode ur bit enables IRQ interrupt request line to CPU IRQ interrupt enable Reserved Note Before using the IRQ interrupt this bit must be cleared This bit enables FIQ interrupt request line to CPU 0 interrupt enable Not allowed vectored interrupt mode 1 Reserved Note Before using the FIQ interrupt this bit must be cleared NOTE FIQ interrupt mode does not support vectored interrupt mode ELECTRENICE 11 9 INTERRUPT CONTROLLER 53 44 RISC MICROPROCESSOR INTERRUPT PENDING REGISTER INTPND Each of the 26 bits in the interrupt pending register INTPND corresponds to an interrupt source When an interrupt request is generated it will be set to 1 The interrupt service routine must then clear the pending condition by writing 1 to the corresponding bit of ISPC F_ISPC Although several interrupt sources generate requests simultaneously the INTPND will indicate all interrupt sources that generate an interrupt request Even if the interrupt source is masked by INTMSK the corresponding pending bit can be set to 1 INTPND 0x01E00004 Indicates the interrupt request status 0x0000000 0 The interrupt has not been requested 1 The i
131. RAM MT 10 6 bit 5 4 RAS to CAS delay 00 1 clock 01 2 clocks 10 3 clocks 11 4 clocks 3 CAS pulse width 0 1 clock 1 2 clocks 2 CAS pre charge 0 1 clock 1 2 clocks 1 0 Column address number 00 8 bit 01 9 bit 10 10 bit 11 11 bit d ELECTRENICS 4 15 MEMORY CONTROLLER 53 44 RISC MICROPROCESSOR BANK CONTROL REGISTER nGCS6 nGCS7 Continued Memory Type SDRAM MT 11 4 bit Tred 3 2 RAS to CAS delay 10 00 2 clocks 01 3 clocks 10 4 clocks SCAN 1 0 Column address number 00 8 bit 01 9 bit 10 10 bit SUPPORTED BANK 6 7 MEMORY CONFIGURATION SROM DRAM SDRAM SROM SDRAM DRAM DRAM SROM SROM SDRAM DRAM SDRAM NOTE SROM means ROM or SRAM type memory REFRESH CONTROL REGISTER REFRESH 0x01C80024 DRAM SDRAM refresh control register 0 0000 REFEN 23 DRAM SDRAM Refresh Enable 0 Disable 1 Enable self or CBR auto refresh TREFMD 22 DRAM SDRAM Refresh Mode 0 CBR Auto Refresh 1 Self Refresh In self refresh time the DRAM SDRAM control signals are driven to the appropriate level Trp 21 20 DRAM SDRAM RAS pre charge Time DRAM 00 1 5 clocks 01 2 5clocks 10 3 5 clocks 11 4 5 clocks SDRAM 00 2 clocks 01 3 clocks 10 4 clocks 11 support 19 18 SDRAM RC minimum Time 11 00 4 clocks 01 5clocks 10 6clocks 11 7 clocks Tchr 17 16 CAS Hold Time DRAM 00 1 clock 01 2 clocks 10 clocks 11 4 clocks
132. RISC MICROPROCESSOR COPROCESSOR REGISTER TRANSFERS MRC MCR The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 27 This class of instruction is used to communicate information directly between ARM7TDMI and a coprocessor An example of a coprocessor to ARM7TDMI register transfer MRC instruction would be a FIX of a floating point value held in a coprocessor where the floating point number is converted into a 32 bit integer within the coprocessor and the result is then transferred to ARM7TDMI register A FLOAT of a 32 bit value in ARM7TDMI register into a floating point value within the coprocessor illustrates the use of ARM7TDMI register to coprocessor transfer MCR An important use of this instruction is to communicate control information directly from the coprocessor into the ARM7TDMI CPSR flags As an example the result of a comparison of two floating point values within a coprocessor can be moved to the CPSR to control the subsequent flow of execution 28 27 2423 212019 16 15 12 11 7 5 4 3 Lu uw om om 3 0 Coprocessor Register 7 5 Coprocessor Information 11 8 Coprocessor Number 15 12 ARM Source Destination Register 19 16 Coprocessor Source Destination Register 20 Load Store Bit 0 Store to coprocessor 1 Load from coprocessor 21 Coprocessor Operation Mode
133. ROCESSOR LOL 1 25 Figure 20 3 160 FBGA 12 0x12 0 Package Dimensions 2 NOTE get more specific information for testing the FBGA TQFP package using JTAG Please contact us ELECTRONICS MECHANICAL DATA 53 44 RISC MICROPROCESSOR NOTES 20 4 ELECTRONICS
134. ROPROCESSOR IIS MODE REGISTER IISMOD IISMOD 0x01D18004 Li W Li HW Bi W 15 mode register 0x01D18006 Bi HW Master slave mode select 8 0 Master mode IISLRCK and IISCLK are output mode 1 Slave mode IISLRCK and IISCLK are input mode Transmit receive mode 7 6 00 No transfer 01 Receive mode select 10 Transmit mode 11 Transmit and receive mode Active level of left right Low for left channel high for right channel channel High for left channel low for right channel Serial interface format IIS compatible format Serial data bit per channel 0 8 bit 1 16 bit Master 0 25615 38415 frequency select fs sampling Serial bit clock frequency 00 16fs 01 32fs select 10 48fs 11 fs sampling frequency MSB Left justified format NOTES 1 The IISMOD register can be accessed by halfword and word unit using STRH STR and LDRH LDR instructions or short int int type pointer in Little Big endian mode 2 Li HW W Access by halfword word unit when the endian mode is Little Bi HW W Access by halfword word unit when the endian mode is Big 17 6 ELECTRONICS 53 44 RISC MICROPROCESSOR IIS BUS INTERFACE 15 PRESCALER REGISTER IISPSR IISPSR 0x01D18008 Li B Li HW Li W Bi W IIS prescaler register 0x01D1800A Bi HW 0x01D1800B Bi B Description Initial State State EET value A ECN 4 prescaler division factor for the prescaler
135. RUCTION SET 53 44 RISC MICROPROCESSOR SINGLE DATA TRANSFER LDR STR The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 14 The single data transfer instructions are used to load or store single bytes or words of data The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register The result of this calculation may be written back into the base register if auto indexing is required 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0 Lem m Do 15 12 Source Destination Registers 19 16 Base Register 20 Load Store Bit 0 Store to memory 1 Load from memory 21 Write back Bit 0 No write back 1 Write address into base 22 Byte Word Bit 0 Transfer word quantity 1 Transfer byte quantity 23 Up Down Bit 0 Down subtract offset from base 1 Up add offset to base 24 Pre Post Indexing Bit 0 Post add offset after transfer 1 Pre add offset before transfer 25 Immediate Offset Offset is an immediate value 11 0 Offset 11 0 11 0 Unsigned 12 bit immediate offset 11 4 3 0 3 0 Offset register 11 4 Shift applied to Rm 31 28 Condition Field Figure 3 14 Single Data Transfer Instructions 3 28 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET OFFSETS AND AUTO INDEXING The offset fro
136. S is shifted to SDA Interrupt is pending Figure 16 8 Operations for Slave Transmitter Mode ELECTRONICS 16 9 IIC BUS INTERFACE S3C44BOX RISC MICROPROCESSOR START Slave Rx mode has been configured detects start signal and IICDS receives data compares IICADD and IICDS the received slave address The IIC address match interrupt is generated Read IICDS Clear pending bit to resume SDA is shifted to IICDS Interrupt is pending Figure 16 9 Operations for Slave Receiver Mode 16 10 ELECTRONICS 53 44 RISC MICROPROCESSOR IIC BUS INTERFACE IIC BUS INTERFACE SPECIAL REGISTERS MULTI MASTER IIC BUS CONTROL REGISTER IICCON IICCON 0x01D60000 control register Acknowledge enable 1 Tx clock source selection Tx Rx Interrupt 5 enable Interrupt pending flag 2 3 Transmit clock value 4 NOTES 0000_XXXX acknowledge enable bit 0 Disable ACK generation 1 Enable ACK generation In Tx mode the IICSDA is free in the ack time In Rx mode the IICSDA is L in the ack time Source clock of transmit clock prescaler selection bit 0 IICCLK 16 1 fyucik 512 Tx Rx interrupt enable disable bit 0 Disable interrupt 1 Enable interrupt Tx Rx interrupt pending flag Writing 1 is impossible When this bit is read as 1 the IICSCL is tied to L and the IIC is stopped To resume the
137. SIO start bit to start the receiving operation The SIO requests the DMA service after 8 bit data has been received Go to step 5 until DMA count is 0 QO DCNTZ n is set to 1 which stops the SIO from requesting further DMA service DCNTZ n 0 Setting SIOCON SIOCON xxxxxx 00b BDMA Setting SIOCON 110 xxxxx 111 manual start DMAcount 0 Y DCNTZ n 1 Figure 18 3 SIO Receive by 18 4 ELECTRONICS 53 44 RISC MICROPROCESSOR 510 SIOCLK o 51 o 00000060005 gt Xem m om e enm SIOCON Transmit Start Bit Complete Figure 18 4 SIO Transmit Receive Mode Timing diagram Tx at Falling SIOCLK A e OCC Ye Xe X gt e em em SIOCON Transmit Start Bit Complete Figure 18 5 SIO Transmit Receive Mode Timing diagram Tx at Rising ELECTRENICS 18 5 SIO 53 44 RISC MICROPROCESSOR Interval Time 2 SIOCLK 2 SIOTXD SIORXD SIOCON Transmit Start Bit Complete DMA Condition Setting NOTE SIO Tx is auto start regardless of the SIOCON start bit Figure 18 6 SIO in Non Hand shaking Mode Timing diagram Auto Run Mode 18 6 ELECTRONICS 53 44 RISC MICROPROCESSOR SIO SYNCHRONOUS I O INTERFACE SPECIAL REGISTERS SIO CONTROL REGISTER SIOCON SIOCON 0x01D14000 SIO control register Clock source select 7 SIO shift clock source select bit 0 Internal clock 1
138. TA26 11 nRTS1 PC9 19 18 00 Input 01 Output 10 DATA25 11 nXDREQ1 PC8 17 16 00 Input 01 Output 10 DATA24 11 nXDACK1 PC7 15 14 00 Input 01 Output 10 DATA23 11 4 PC6 13 12 00 Input 01 Output 10 DATA22 11 VD5 PC5 11 10 00 Input 01 Output 10 DATA21 11 VD6 4 9 8 00 01 Output 10 DATA20 11 VD7 7 6 00 Input 01 Output 10 DATA19 11 IISCLK PC2 5 4 00 Input 01 Output 10 DATA18 11 IISDI PC1 3 2 00 Input 01 Output 10 DATA17 11 IISDO PCO 1 0 00 Input 01 Output 10 DATA16 11 IISLRCK 8 8 ELECTRONICS 53 44 RISC MICROPROCESSOR PORTS PC 15 0 15 0 When the port is configured as an input port the corresponding bit is the pin state When the port is configured as an output port the pin state is the same as the corresponding bit When the port is configured as a functional pin an undefined value will be read PC 15 0 15 0 0 the pull up resistor attached to the corresponding port pin is enabled 1 the pull up resistor is disabled ELECTRENICS 8 9 PORTS 3C44B0X RISC MICROPROCESSOR PORT D CONTROL REGISTERS PCOND PDATD PUPD Port D control registers are shown in Table 8 5 PCOND 0x01D2001C Configures the pins of port D 0x0000 PDATD 0x01D20020 The data register for port D PUPD 0x01D20024 Pull up disable register for port D Table 8 5 Port of Group D Control Registers PCON
139. TIAL CURRENT DESTINATION ADDRESS REGISTERS ZDIDES ZDCDE OPT 31 30 DMA internal options OPT 10 is recommended bit 31 Indicates how nXDREQ is sampled in the single step mode 1 is recommended bit 30 If the DST is half word or word and if the DMA mode is not the block transfer mode this bit takes a role DMA does word swap or half word swap Before transfer BO B1 B2 B3 B4 B5 B6 B7 word swapped data B3 B2 B1 B0 B7 B6 B5 B4 half word swapped data B1 B0 B3 B2 B5 B4 B7 B6 normal DAS 29 28 Direction of address for store 00 N A 01 Increment 10 Decrement 11 Fixed IDADDR CDADDR 27 0 Initial current destination address for ZDMAn 0x0000000 7 14 ELECTRONICS 53 44 RISC MICROPROCESSOR DMA ZDMAn INITIAL CURRENT COUNT REGISTERS ZDICNT ZDCCNT 31 30 DREQ DMA request source selection 00 nXDREQ O0 01 nXDREQ 1 10 11 N A 29 28 DREQ protocol 00 Handshake 01 Single step 10 Whole Service 11 Demand 27 26 Transfer mode 00 Not used 01 Unit transfer mode 10 Block 4 word transfer mode 11 On the fly If block transfer mode is selected the ADDR 3 0 should be 0 to meet 16 byte align condition 25 24 On the fly mode 00 N A 01 10 Read time on the fly 11 Write time on the fly INTS 23 22 Interrupt mode set 00 Polling mode 01 N A 10 Int whenever transferred 11 Int whenever terminated count 21 Auto reload and Auto start
140. TO Tx buffer the UARTO Tx buffer address will be used 7 18 ELECTRONICS 53 44 RISC MICROPROCESSOR DMA BDMAO INITIAL CURRENT COUNT REGISTERS BDICNTO BDCCNTO QSC 31 30 DMA request source selection 00 N A 01 IIS 10 UARTO 11 SIO 27 26 01 unit transfer mode 25 24 00 on the fly mode is not supported in BDMAn INTS 23 22 Interrupt mode set 00 Polling mode 01 N A 10 Int whenever transferred 11 Int whenever terminated count 21 Auto reload and Auto start after DMA count are 0 0 Disable 1 Enable Even after DMA count is 0 the DMA H W enable bit EN bit is still 1 But DMA will start to operate only if the start command or DMA request is activated B EN 20 DMA H W enable disable 0 Disable DMA 1 Enable DMA If the QDS bit is 000 DMA request can be serviced Also if the S W command is started the DMA operation will occur If the EN bit is 0 DMA will not operate even though S W command is started If the S W command is canceled the DMA operation will be canceled and EN bit will be cleared to 0 At the terminal count the EN bit will be cleared to 0 NOTE Do not set the EN bit and the other bits of BDICNT register at the same time User have to set EN bit after setting the other bits of BDICNT register as following steps 1 Set BDICNT register with disabled En bit 2 Set EN bit enable 19 0 Transfer count for BDMAO transfer count must be r
141. The PC is saved in R14_svc upon entering the software interrupt trap with the PC adjusted to point to the word after the SWI instruction MOVS PC R14_svc will return to the calling program and restore the CPSR Note that the link mechanism is not re entrant so if the supervisor code wishes to use software interrupts within itself it must first save a copy of the return address and SPSR COMMENT FIELD The bottom 24 bits of the instruction are ignored by the processor and may be used to communicate information to the supervisor code For instance the supervisor may look at this field and use it to index into an array of entry points for routines which perform the various supervisor functions INSTRUCTION CYCLE TIMES Software interrupt instructions take 2S 1N incremental cycles to execute where S and N are defined as sequential S cycle and non sequential ELECTRONICS 3 49 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR ASSEMBLER SYNTAX SWI cond lt expression gt cond Two character condition mnemonic Table 3 2 lt expression gt Evaluated and placed in the comment field which is ignored by ARM7TDMI EXAMPLES SWI ReadC Get next character from read stream SWI Writel k Output a k to the write stream SWINE 0 Conditionally call supervisor with 0 in comment field Supervisor code The previous examples assume that suitable supervisor code exists for instance 0x08 B Supervisor SWI en
142. The master priority generating unit determines the priority between the 4 slave units and 2 interrupt sources The 2 interrupt sources INT RTC and INT ADC have the lowest priority among 26 interrupt sources sGA B C D EINTO 1 2 3 mGA B C D sGKA B EINT4 5 6 7 ARM IRQ mGKA sGA B C D 20 ZD BRDMAO BRDMA1 WDT calico UERRO 1 sGA B D 1 2 3 sGKA B 5 RXDO 1 SIO sGKA TXDO 1 RTC ADC Figure 11 1 Priority Generating Block 11 4 ELECTRONICS 53 44 RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT PRIORITY If source A is configured to FIQ and source B is configured to IRQ source A has higher priority than source B because a FIQ interrupt has higher priority than an IRQ interrupt in all cases If source A and source B are in different master groups and the master group priority of source A is higher than the master group priority of source B the priority of source A is higher than source B If source A and source B are in the same master group and source A has higher priority than source B source A has the higher priority The priorities of SGA sGB sGC and sGD are always higher than those of sGKA and sGKB The priorities among sGA sGB sGC and sGD are programmable are determined by the round robin method Between sGKA and sGKB sGKA has always the higher priority The group priority of mGA mGB mGC a
143. The power consumption due to PLL itself is excluded The Idle mode disconnects the clock only to CPU core while it supplies the clock to all peripherals By using this Idle mode power consumption due to CPU core can be reduced Any interrupt request to CPU can wake up from Idle mode The Stop mode freezes all clocks to the CPU as well as peripherals by disabling PLL The power consumption is only due to the leakage current in S3C44BOX which is less than 10 uA The wake up from Stop mode can be done by external interrupt to CPU The SL Idle mode causes the LCD controller to work In this case the clock to CPU and all peripherals except LCD controller should be stopped therefore the power consumption in the SL Idle mode is less than that in the Idle mode ELECTRONICS 5 1 CLOCK amp POWER MANAGEMENT 53 44 RISC MICROPROCESSOR FUNCTION DESCRIPTION CLOCK GENERATION Figure 5 1 shows a block diagram of the clock generator The main clock source comes from an external crystal or external clock The clock generator has an oscillator Oscillation Amplifier which should be connected to an external crystal and also has a PLL Phase Locked Loop which takes the low frequency oscillator output as its input and generates the high frequency clock required by 53 44 The clock generator block has the logic to generate stable clock frequency after a reset or a stop mode External XTALO 00 EXTALO lt i CLKout 01 CLOCK
144. Tm 22 Refresh 10 0 DRAM SDRAM refresh count value Please refer to chap 6 DRAM Counter refresh controller bus priority section Refresh period 2 refresh_count 1 MCLK Ex If refresh period is 15 6 us and MCLK is 60 MHz the refresh count is as follows refresh count 2 1 60x15 6 1113 d 4 16 ELECTRONICS 53 44 RISC MICROPROCESSOR MEMORY CONTROLLER ELECTRONICS 4 17 MEMORY CONTROLLER 53 44 RISC MICROPROCESSOR BANKSIZE REGISTER BANKSIZE 0x01C80028 Flexible bank size register SCLKEN 4 SCLK will be generated only during SDRAM access cycle This feature will reduce the power consumption 1 is recommended 0 normal SCLK 1 SCLK for reducing power consumption 9 BK76MAP 2 0 BANK6 7 memory map 000 32M 32M 100 2M 2M 101 4M 4M 110 8M 8M 111 16M 16M SDRAM MODE REGISTER SET REGISTER MRSR MRSRB6 0x01C8002C Mode register set register bank6 MRSRB7 0x01C80030 Mode register set register bank7 MRSR Description Initial State 11 10 Not use WBL Write burst length 0 is the recommended value CAS latency 000 1 clock 010 2 clocks 01123 clocks CL the others reserved BT 3 Burst type 0 Sequential recommended 1 N A BL Burst length 000 1 the others N A NOTE MRSR register must not be reconfigured while the code is running on SDRAM 8 7 Test mode 00 mode register set 01 10 11 reserved 6 4 IMPORTANT NOTES 1 Al
145. Two character condition mnemonic See Table 3 2 S Set condition codes if S present Rd Rm Rs and Rn Expressions evaluating to a register number other than R15 EXAMPLES MUL R1 R2 R3 1 2 MLAEQS R1 R2 R3 R4 Conditionally R1 R2 R3 R4 Setting condition codes 3 24 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET MULTIPLY LONG AND MULTIPLY ACCUMULATE LONG MULL MLAL The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 13 The multiply long instructions perform integer multiplication on two 32 bit operands and produce 64 bit results Signed and unsigned multiplication each with optional accumulate give rise to four variations 28 27 23 22 21 20 19 16 15 12 11 Tow oes faje mer sas m 160 11 8 3 0 Operand Registers 19 16 15 12 Source Destination Registers 20 Set Condition Code 0 Do not alter condition codes 1 Set condition codes 21 Accumulate 0 Multiply only 1 Multiply and accumulate 22 Unsigned 0 Unsigned 1 Signed 31 28 Condition Field Figure 3 13 Multiply Long Instructions The multiply forms UMULL and SMULL take two 32 bit numbers and multiply them to produce a 64 bit result of the form RdHi RdLo Rm Rs The lower 32 bits of the 64 bit result are written to RdLo the upper 32 bits of the result are written to RdHi The multiply ac
146. _0000 SROM DRAM SDRAM nGCS7 2 4 8 16 32 0 0 00 0000 Refer to om nGCS2 0x0400_0000 om 16651 0 0200_0000 0 01 0 0000 Special function Registers 4M bytes 0x0000_0000 NOTE SROM means ROM or SRAM type memory Figure 4 1 S3C44BOX Memory Map after Reset Table 4 1 Bank 6 7 Address mw e ws 8 0000 00 0000 0000 00 0000 00 0000 End address Oxc1f Oxc3t_ffff Oxc7f Oxcff_ffff fff 0 20_ 0000 0 40 0000 80 0000 0000 00 0000 End address Oxc3t_fiff Oxc7t Oxctf_fff fff NOTE Bank 6 and 7 must have the same memory size 4 2 ELECTRONICS 53 44 RISC MICROPROCESSOR MEMORY CONTROLLER FUNCTION DESCRIPTION LITTLE ENDIAN BIG ENDIAN While nRESET is L the ENDIAN pin defines which endian mode should be selected If the ENDIAN pin is connected to Vss with a pull down resistor the little endian mode is selected If the pin is connected to Vdd with a pull up resistor the big endian mode is selected ENDIAN Input Reset ENDIAN Mode BANKO BUS WIDTH The data bus width of BANKO nGCSO should be configured as one of 8 bit 16 bit and 32 bit Because the BANKO is the booting ROM bank map to 0x0000_0000 the bus width of BANKO should be determined before the first ROM access which will be determined by the logic level of OM 1 0 at Reset OM1 Operating Mod
147. able The 53044 can support the palette table for various selection of color or gray level mapping This kind of selection gives users flexibility The lookup table is the palette which allows the selection on the level of color or gray Selection on 4 gray levels among 16 gray levels in case of gray mode selection on 8 red levels among 16 levels 8 green levels among 16 levels and 4 blue levels among 16 levels in case of color mode In other words users can select 4 gray levels among 16 gray levels by using the lookup table in the 4 gray level mode The gray levels cannot be selected in the 16 gray level mode all 16 gray levels must be chosen among the possible 16 gray levels In case of 256 color mode 3 bits are allocated for red 3 bits for green and 2 bits for blue The 256 colors mean that the colors are formed from the combination of 8 red 8 green and 4 blue levels 8x8x4 256 In the color mode the lookup table can be used for suitable selections Eight red levels can be selected among 16 possible red levels 8 green levels among 16 green levels and 4 blue levels among 16 blue levels Gray Mode Operation Two gray modes are supported by the LCD controller within the 53 44 2 bit per pixel gray 4 level gray scale or 4 bit per pixel gray 16 level gray scale The 2 bit per pixel gray mode uses a lookup table which allows selection on 4 gray levels among 16 possible gray levels The 2 bit per pixel gray lookup table uses the BULEV
148. accept the FIQ fast interrupt request from the interrupt controller If 1 68 of PSR program status register in ARM7TDMI CPU is set 0 1 the CPU does not accept the IRQ interrupt request from the interrupt controller So to enable the interrupt reception the F bit or I bit of PSR has to be cleared to 0 and also the corresponding bit of INTMSK has to be cleared to 0 Interrupt Mode has 2 types of interrupt mode or IRQ All the interrupt sources determine the mode of interrupt to be used at interrupt request Interrupt Pending Register Indicates whether or not an interrupt request is pending When a pending bit is set the interrupt service routine starts whenever the or F flag is cleared to 0 Interrupt Pending Register is a read only register so the service routine must clear the pending condition by writing a 1 to ISPC F ISPC Interrupt Mask Register Indicates that an interrupt has been disabled if the corresponding mask bit is 1 If an interrupt mask bit of INTMSK is 0 the interrupt will be serviced normally If the corresponding mask bit is 1 and the interrupt is generated the pending bit will be set If the global mask bit is set to 1 the interrupt pending bit will be set but all interrupts will not be serviced 11 2 ELECTRONICS 53 44 RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT SOURCES Among 30 interrupt sources 26 sources are provided for the interrupt controller Four ex
149. after DMA count are 0 0 Disable 1 Enable Even after DMA count is 0 the DMA H W enable bit EN bit is still 1 But DMA will start to operate only if the start command or is activated 20 DMA H W enable disable 0 Disable DMA 1 Enable DMA If the QDS bit is 00b DMA request can be serviced Also if the S W command is started the DMA operation will occur If the EN bit is 0 DMA will not operate even though S W command is started If the S W command is canceled the DMA operation will be canceled and EN bit will be cleared to 0 At the terminal count the EN bit will be cleared to 0 NOTE Do not set the EN bit and the other bits of ZDICNT register at the same time User have to set EN bit after setting the other bits of ZDICNT register as following steps 1 Set ZDICNT register with disabled En bit 2 Set EN bit enable 19 0 Initial current transfer count for ZDMAn 0x00000 If 1 byte is transferred the ICNT will be decreased by 1 If 1 half word is transferred the ICNT will be decreased by 2 If 1 word is transferred the ICNT will be decreased by 4 For example if the data size of a transfer is word and the count is 4n 3 the last 3 bytes will not be transferred ELECTRONICS 7 15 DMA 53 44 RISC MICROPROCESSOR BDMAn CONTROL REGISTER BDCON BDCONO 0 01 80000 Bridge DMA 0 Control Register BDCON1 0x01F80020 Bridge DMA 1 Control Register 76 STE 5 4 Sta
150. al The UART s transmitter transfers the data in FIFO only when nCTS signal active In AFC nCTS means that the other UART s FIFO is ready to receive data Before the UART receives data nRTS has to be activated when its receive FIFO has a spare more than 2 byte and has to be inactivated when its receive FIFO has a spare under 1 byte In AFC nRTS means that its own receive FIFO is ready to receive data Transmission case in Reception case in UART A UART A Figure 10 2 UART AFC interface ELECTRENICS 10 3 UART 53 44 RISC MICROPROCESSOR Non Auto Flow control Controlling nRTS and nCTS by S W Rx operation 1 Select receive mode Interrupt mode 2 Check the value of Rx FIFO count in UFSTATn register If the value is less than 15 users have to set the value of 0 to 1 activate nRTS and if it is equal or larger than 15 users have to set the value to O inactivate nRTS 3 Repeat item 2 Tx operation 1 Select transmit mode Interrupt or mode 2 Check the value of UMSTATn O If the value is 1 nCTS is activated users write the data to Tx buffer or Tx FIFO register RS 232C interface If users connect to modem interface not equal null modem nRTS nCTS nDSR nDTR DCD and nRI signals are need In this case users control these signals with general I O ports by S W because the AFC does not support the RS 232C interface 10 4 ELECTRONICS 53 44 RISC MICROPROCESSOR UART
151. al source address Register 0x00000000 ZDIDESO 0x01E80008 ZDMA 0 initial destination address Register 0x00000000 ZDICNTO 0 01 8000 ZDMA 0 initial count register 0x00000000 ZDMAO CURRENT SRC DST ADDRESS AND COUNT REGISTERS ZDCSRCO ZDCDESO ZDCCNTO zocsncs ZMA 0 caren source access _ destination adress Reger or00000000 zov 0 curent countregsier NOTE These registers read only ZDMAt1 INITIAL SOURCE DESTINATION ADDRESS AND COUNT REGISTERS ZDISRC1 ZDIDES1 ZDICNT1 ZDMA1 CURRENT SRC DST ADDRESS AND COUNT REGISTERS ZDCSRC1 ZDCDES1 ZDCCNT1 ZDCSRCi 0x01E80030 ZDMA 1 current source address Register 0x00000000 ZDCDES1 0x01E80034 oR ZDMA 1 current destination address Register 0x00000000 ZDCCNT1 0 01 80038 R 20 1 current count register 0x00000000 NOTE These registers are read only ELECTRONICS 7 13 DMA 53 44 RISC MICROPROCESSOR ZDMAn INITIAL CURRENT SOURCE ADDRESS REGISTERS ZDISRC ZDCSRC DST 31 30 Data size for transfer 00 Byte 01 Half word 10 Word 11 used If the block transfer mode is used the DST must be 10 DAL 29 28 Direction of address for load 00 N A 01 Increment 10 Decrement 11 Fixed ISADDR CSADDR 27 0 Initial current source address for ZDMAn 0x0000000 ZDMAn INI
152. am 10 8 ELECTRONICS 53 44 RISC MICROPROCESSOR UART 4 SIO Frame 9 Start Data Bits _ Stop Figure 10 5 Serial I O Frame Timing Diagram Normal UART amp IR Transmit Frame Start Datta _ Stop Pulse Width 3 16 Bit Frame Figure 10 6 Infra Red Transmit Mode Frame Timing Diagram Receive Frame 9 Stat 4 Datta Bits Stop Figure 10 7 Infra Red Receive Mode Frame Timing Diagram ELECTRENICS 10 9 UART 53 44 RISC MICROPROCESSOR UART SPECIAL REGISTERS UART LINE CONTROL REGISTER There are two UART line control registers ULCONO and ULCON1 in the UART block ULCONO 0x01D00000 UART channel 0 line control register ULCON1 0x01D04000 UART channel 1 line control register mm Infra Red Mode The Infra Red mode determines whether or not to use the Infra Red mode 0 Normal mode operation 1 Infra Red Tx Rx mode Parity Mode 5 3 The parity mode specifies how parity generation and checking are to be performed during UART transmit and receive operation Oxx No parity 100 Odd parity 101 Even parity 110 Parity forced checked as 1 111
153. and 2 is an immediate value 11 0 Operand 2 type selection 11 3 4 0 3 0 2nd operand register 11 4 Shift applied to Rm 11 8 7 7 0 Unsigned 8 bit immediate value 11 8 Shift applied to Imm 31 28 Condition field Figure 3 4 Data Processing Instructions ELECTRONICS 3 9 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR The instruction produces a result by performing a specified arithmetic or logical operation on one or two operands The first operand is always a register Rn The second operand may be a shifted register Rm or a rotated 8 bit immediate value Imm according to the value of the bit in the instruction The condition codes in the CPSR may be preserved or updated as a result of this instruction according to the value of the S bit in the instruction Certain operations TST TEQ CMP CMN do not write the result to Rd They are used only to perform tests and to set the condition codes on the result and always have the S bit set The instructions and their effects are listed in Table 3 3 3 10 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET CPSR FLAGS The data processing operations may be classified as logical or arithmetic The logical operations AND EOR TST TEQ ORR MOV BIC MVN perform the logical action on all corresponding bits of the operand or operands to produce the result If the S bit is set and Rd is not R15 see below the V flag in the CPSR will be unaffected
154. and N 1 could select the transfer of all the registers for context switching ELECTRONICS 3 53 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR ADDRESSING MODES is responsible for providing the address used by the memory system for the transfer and the addressing modes available are a subset of those used in single data transfer instructions Note however that the immediate offsets are 8 bits wide and specify word offsets for coprocessor data transfers whereas they are 12 bits wide and specify byte offsets for single data transfers The 8 bit unsigned immediate offset is shifted left 2 bits and either added to U 1 or subtracted from U 0 the base register Rn this calculation may be performed either before P 1 or after 0 the base is used as the transfer address The modified base value may be overwritten back into the base register if W 1 or the old value of the base may be preserved W 0 Note that post indexed addressing modes require explicit setting of the W bit unlike LDR and STR which always write back when post indexed The value of the base register modified by the offset in a pre indexed instruction is used as the address for the transfer of the first word The second word if more than one is transferred will go to or come from an address one word 4 bytes higher than the first transfer and the address will be incremented by one word for each subsequent transfer ADDRESS ALIGNMENT Th
155. and R14 for returning This nested call will overwrite R14 Restore workspace and return ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET SINGLE DATA SWAP SWP 28 27 23 22 21 20 19 16 15 12 11 w D w o D 3 0 Source Register 15 12 Destination Register 19 16 Base Register 22 Byte Word Bit 0 Swap word quantity 1 Swap word quantity 31 28 Condition Field Figure 3 23 Swap Instruction The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 23 The data swap instruction is used to swap a byte or word quantity between a register and external memory This instruction is implemented as a memory read followed by a memory write which are locked together the processor cannot be interrupted until both operations have completed and the memory manager is warned to treat them as inseparable This class of instruction is particularly useful for implementing software semaphores The swap address is determined by the contents of the base register Rn The processor first reads the contents of the swap address Then it writes the contents of the source register Rm to the swap address and stores the old memory contents in the destination register Rd The same register may be specified as both the source and destination The LOCK output goes HIGH for the duration of the read
156. ank Figure 4 11 Memory Interface with 16bit SDRAM 4Mx16 2ea 4bank NOTE Please refer to Table 4 2 the Bank Address configurations of SDRAM ELECTRONICS 4 11 MEMORY CONTROLLER 53 44 RISC MICROPROCESSOR MEMORY CONTROLLER SPECIAL REGISGERS BUS WIDTH amp WAIT CONTROL REGISTER BWSCON BWSCON 0x01C80000 Bus Width amp Wait Status Control Register 0x000000 BWSCON Bit Description Initial state ST7 31 This bit determines SRAM for using UB LB for bank 7 0 Not using UB LB Pin 14 11 is dedicated nWBE 3 0 1 Using UB LB Pin 14 11 is dedicated nBE 3 0 WS7 30 This bit determines WAIT status for bank 7 If bank7 has DRAM or SDRAM WAIT function is not supported 0 WAIT disable 1 WAIT enable DW7 29 28 These two bits determine data bus width for bank 7 00 8 bit 01 16 bit 10 32 bit ST6 27 This bit determines SRAM for using UB LB for bank 6 0 Not using UB LB Pin 14 11 is dedicated nWBE 3 0 1 Using UB LB Pin 14 11 is dedicated nBE 3 0 WS6 26 This bit determines WAIT status for bank 6 If bank6 has DRAM or SDRAM WAIT function is not supported 0 WAIT disable 1 WAIT enable DW6 25 24 These two bits determine data bus width for bank 6 00 8 bit 01 16 bit 10 32 bit ST5 23 This bit determines SRAM for using UB LB for bank 5 0 Not using UB LB Pin 14 11 is dedicated nWBE 3 0 1 Using UB LB Pin 14 11 is dedicated nBE 3 0 WS5 2
157. are register in the timer control logic Therefore the compare register determines the turn on time or turn off time of an PWM output FEATURES Six 16 bit timers with DMA based or interrupt based operation Three 8 bit prescalers amp Two 5 bit dividers amp One 4 bit divider Programmable duty control of output waveform PWM Auto reload mode or one shot pulse mode Dead zone generator ELECTRENICS 9 1 PWM TIMER 53 44 RISC MICROPROCESSOR Dead Zone Generator 8 Bit Prescaler TOME Clock Divider 8 Bit Prescaler Clock Divider 8 Bit Prescaler Clock 1 TOUTS No Pin Divider ogic Figure 9 1 16 bit PWM Timer Block Diagram 9 2 ELECTRENICE 53 44 RISC MICROPROCESSOR PWM TIMER PWM TIMER OPERATION PRESCALER amp DIVIDER An 8 bit prescaler and an independent 4 bit divider make the following output frequencies 4 bit divider settings minimum resolution maximum resolution maximum interval prescaler 1 prescaler 255 TCNTBn 65535 1 2 MCLK 66 MHz 0 030 us 33 0 MHz 7 75 us 58 6 KHz 1 4 MCLK 66 MHz 0 060 us 16 5 MHz 0 485 us 2 06 MHz 125 us 7 32 KHz BASIC TIMER OPERATION dob Oa TCNTBn 3 TCNTBn 2 TCMPBn 1 0 Manual Update 1 Manual Update 0 Auto reload 1 Auto reload 1 Command C Status Figure 9 2 Timer operations A timer except the timer ch 5 has TCNTBn TCNTn TCMPBn and T
158. ared to the Fref To avoid overloading the VCO a low pass filter samples and filters the high frequency components out of the control signal The filter is typically a single pole RC filter consisting of a resistor and capacitor A recommended capacitance in the external loop filter Capacitance as shown in Figure 5 2 is 700pF Voltage Controlled Oscillator VCO The output voltage from the loop filter drives the VCO causing its oscillation frequency to increase or decrease linearly as a function of variations in average voltage When the Fvco output matches Fref in terms of frequency as well as phase the PFD stops sending a control signal to the charge pump which in turn stabilizes the input voltage to the loop filter The VCO frequency then remains constant and the PLL remains locked onto the system clock Usual Condition for PLL amp Clock Generator The following conditions are generally used Loop filter capacitance 700 820 pF External feedback resistance External X tal frequency 6 20 Mhz External capacitance used for X tal 15 22 pF ELECTRONICS 5 3 CLOCK amp POWER MANAGEMENT 53 44 RISC MICROPROCESSOR 5 0 PLLCAP 700pF Fret Loop Filter T Internal External Divider M vo Divider S Figure 5 2 PLL Phase Locked Loop Block Diagram VDD or External EXTCLK ial EXTCLK Clock for OSC 5 EXTALO EXTALO a X TAL oscillation b External clock source Figu
159. as CONTROL t Port E control MUX5 Fout for Timer5 Test Mode MCLK only 10 11 3 2 Figure 5 1 Clock Generator Block Diagram CLOCK SOURCE SELECTION Table 5 1 shows the relationship between the combination of mode control pins OM3 and 2 and the selection of source clock for S3C44BOX The OM 3 2 status is latched internally by referring the and OM pins at the rising edge of nRESET Table 5 1 Clock source selection at boot up Mode 3 2 Clock Source Crystal Driver PLL starting state Ext Clock enable 1 PLL Output 1 Others 10 11 Test mode Although the PLL starts just after a reset the PLL output can not be used as Fout until the S W writes valid settings to the PLLCON register Before this valid setting the clock from crystal oscillator or Ext clock source will be used as Fout directly Even if the user wants to maintain the default value of PLLCON register the user should write the same value into PLLCON register If the 53044 operates by PLL output from XTALO EXTALO the EXTCLK can be dedicated as TCLK for Timer 5 5 2 53 44 RISC MICROPROCESSOR CLOCK amp POWER MANAGEMENT PLL PHASE LOCKED LOOP The PLL within the clock generator is the circuit which synchronizes an output signal with a reference input signal in frequency and phase In this application it includes the following basic blocks Figure 5 2 shows the clock generator b
160. assembler ARMequivalent Action O B label BAL label halfword offset Branch PC relative Offset11 lt lt 1 where label is PC 2048 bytes NOTE The address specified by label is a full 12 bit two s complement address but must always be halfword aligned ie bit 0 set to 0 since the assembler places label gt gt 1 in the Offset11 field EXAMPLES here B here Branch onto itself Assembles to OxE7FE Note effect of PC offset B jimmy Branch to jimmy Note that the THUMB opcode will contain the number of halfwords to offset jimmy Must be halfword aligned 3 100 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET FORMAT 19 LONG BRANCH WITH LINK 15 14 13 10 0 1 12 11 ptt 10 0 Long Branch and Link Offset High Low 11 Low High Offset Bit 0 Offset high 1 Offset low Figure 3 48 Format 19 OPERATION This format specifies a long branch with link The assembler splits the 23 bit two s complement half word offset specified by the label into two 11 bit halves ignoring bit 0 which must be 0 and creates two THUMB instructions Instruction 1 H 0 In the first instruction the Offset field contains the upper 11 bits of the target address This is shifted left by 12 bits and added to the current PC address The resulting address is placed in LR Instruction 2 H 1 In the second instruction the Offset field contains an 11 bit represent
161. at 8 OPERATION These instructions load optionally sign extended bytes or halfwords and store halfwords The THUMB assembler syntax is shown below Table 3 15 Summary of format 8 instructions STRH Rd Rb Ro STRH Rd Rb Ro Store halfword Add Ro to base address in Rb Store bits 0 15 of Rd at the resulting address LDRH Rd Rb Ro LDRH Rd Rb Ro Load halfword Add Ro to base address in Rb Load bits 0 15 of Rd from the resulting address and set bits 16 31 of Rd to 0 LDSB Rd Rb Ro LDRSB Rd Rb Ro Load sign extended byte Add Ro to base address in Rb Load bits 0 7 of Rd from the resulting address and set bits 8 31 of Rd to bit 7 LDSH Rd Rb Ro LDRSH Rd Rb Ro Load sign extended halfword Add Ro to base address in Rb Load bits 0 15 of Rd from the resulting address and set bits 16 31 of Rd to bit 15 ELECTRONICS 3 83 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 15 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES STRH R3 RO Store the lower 16 bits of R4 at the address formed by adding RO to R3 LDSB R2 R7 R1 Load into R2 the sign extended byte found at the address formed by adding R1 to R7 LDSH R3 R4 R2 Loadinto R3 the sign extended halfword found the address form
162. at R14 14 but don t write back Load R8 with the sign extended contents of the byte address contained in R2 and write back R2 223 to R2 Conditionally load R11 with the sign extended contents of the halfword address contained in RO Generate PC relative offset to address FRED Store the halfword in R5 at address FRED 3 39 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR BLOCK DATA TRANSFER LDM STM The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 18 Block data transfer instructions are used to load or store STM any subset of the currently visible registers They support all possible stacking modes maintaining full or empty stacks which can grow up or down memory and are very efficient instructions for saving or restoring context or for moving large blocks of data around main memory THE REGISTER LIST The instruction can cause the transfer of any registers in the current bank and non user mode programs can also transfer to and from the user bank see below The register list is a 16 bit field in the instruction with each bit corresponding to a register A 1 in bit 0 of the register field will cause RO to be transferred a 0 will cause it not to be transferred similarly bit 1 controls the transfer of R1 and so on Any subset of the registers or all the registers may be specified The only restriction is that
163. ata on data bus inputs 7 through to 0 if the supplied address is on a word boundary on data bus inputs 15 through to 8 if it is a word address plus one byte and so on The selected byte is placed in the bottom 8 bit of the destination register and the remaining bits of the register are filled with the sign bit bit 7 of the byte Please see Figure 2 2 A halfword load LDRSH or LDRH expects data on data bus inputs 15 through to 0 if the supplied address is on a word boundary and on data bus inputs 31 through to 16 if it is a halfword boundary A 1 1 The supplied address should always be on a halfword boundary If bit O of the supplied address is HIGH then the ARM7TDMI will load an unpredictable value The selected halfword is placed in the bottom 16 bits of the destination register For unsigned half words LDRH the top 16 bits of the register are filled with zeros and for signed half words LDRSH the top 16 bits are filled with the sign bit bit 15 of the halfword A halfword store STRH repeats the bottom 16 bits of the source register twice across the data bus outputs 31 through to 0 The external memory system should activate the appropriate halfword subsystem to store the data Note that the address must be halfword aligned if bit 0 of the address is HIGH this will cause unpredictable behaviour 3 36 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET Big Endian Configuration A signed byte load LDRSB expects data on
164. ated function of RTOS will always synchronized with real time ROUND RESET FUNCTION The round reset function can be performed by the RTC round reset register RTCRST The round boundary 30 40 or 50 sec of the second carry generation can be selected and the second value is rounded to zero in the round reset For example when the current time is 23 37 47 and the round boundary is selected to 40 sec the round reset changes the current time to 23 38 00 NOTE All RTC registers have to be accessed by the byte unit using the STRB LDRB instructions or char type pointer 32 768KHZ X TAL CONNECTION EXAMPLE The Figure 14 2 is an example circuit of the RTC unit oscillation at 32 768Khz 15 22 pF 32 768 Hz EXTAL1 Figure 14 2 Main Oscillator Circuit Examples ELECTRONICS 14 3 REAL TIME CLOCK 53 44 RISC MICROPROCESSOR REAL TIME CLOCK SPECIAL REGISTERS REAL TIME CLOCK CONTROL REGISTER RTCCON The RTCCON register consists of 4 bits such as the RTCEN which controls the read write enable of the BCD registers CLKSEL CNTSEL and CLKRST for testing RTCEN bit can control all interfaces between the CPU and the RTC so it should be set to 1 in an RTC control routine to enable data read write after a system reset Also before power off the RTCEN bit should be cleared to 0 to prevent inadvertent writing into RTC registers RTCCON 0x01D70040 L R W RTC control Register 0x0 0x01D70043 B by byte CLKRST 3 RTC cloc
165. ation address Register 0x00000000 BDCCNT1 0 01 80038 BDMA 1 current count register 0x00000000 NOTE These registers are read only ELECTRONICS 7 17 DMA 53 44 RISC MICROPROCESSOR BDMAn INITIAL CURRENT SOURCE ADDRESS REGISTERS BDISRC BDCSRC DST 31 30 Data size for transfer 00 Byte 01 Half word 10 Word 11 Not used DAL 29 28 Direction of address for load 00 N A 01 Increment 10 Decrement 11 Internal peripheral fixed address ISADDR CSADDR 27 0 Initial current source address for BDMAn 0x0000000 If the destination is the internal peripherals the SFR address has to be used For example if the source is the UARTO Rx buffer the UARTO Rx buffer address will be used BDMAn INITIAL CURRENT DESTINATION ADDRESS REGISTERS BDIDES BDCDES 30 Transfer direction mode 00 Reserved 01 2 from external memory to internal peripheral 10 102M from internal peripheral to external memory 11 10210 from internal peripheral to internal peripheral NOTE The initial value is 00 but you must change value as another though the BDMA channel is unused 29 28 Direction of address for store 00 N A 01 Increment 10 Decrement 11 Internal peripheral fixed address IDADDR CDADDR 27 0 Initial current destination address for BDMAn 0x0000000 If the destination is the internal peripherals the SFR address has to be used For example if the destination is UAR
166. ation lower half of the target address This is shifted left by 1 bit and added to LR LR which now contains the full 23 bit address is placed in PC the address of the instruction following the BL is placed in LR and bit 0 of LR is set The branch offset must take account of the prefetch operation which causes the PC to be 1 word 4 bytes ahead of the current instruction ELECTRONICS 3 101 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES This instruction format does not have an equivalent ARM instruction Table 3 26 The BL Instruction THUMB assembler ARMequivalent Action BL label none LR PC OffsetHigh lt lt 12 1 temp next instruction address PC LR OffsetLow lt lt 1 LR temp 1 EXAMPLES BL faraway Unconditionally Branch to faraway next and place following instruction address ie next in R14 the Link register and set bit 0 of LR high Note that the THUMB opcodes will contain the number of halfwords to offset faraway Must be Half word aligned 3 102 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET INSTRUCTION SET EXAMPLES The following examples show ways in which the THUMB instructions may be used to generate small and efficient code Each example also shows the ARM equivalent so these may be compared MULTIPLICATION BY A CONSTANT USING SHIFTS AND ADDS The following shows code to multiply by various constants us
167. atus interrupt 1 Generate receive error status interrupt Setting loop back bit to 1 causes the UART to enter the loop back mode This mode is provided for test purposes only 0 Normal operation 1 Loop back mode Setting this bit causes the UART to send a break during 1 frame time This bit is auto cleared after sending the break signal 0 Normal transmit 1 Send break signal These two bits determine which function is currently able to write Tx data to the UART transmit holding register 00 Disable 01 Interrupt request or polling mode 10 BDMAO request Only for UARTO 11 1 request Only for UART1 These two bits determine which function is currently able to read data from UART receive buffer register 00 Disable 01 Interrupt request or polling mode 10 request Only UARTO 11 1 request Only for UART1 UART 10 11 UART 53 44 RISC MICROPROCESSOR UART FIFO CONTROL REGISTER There are two UART FIFO control registers UFCONO and UFCON1 in the UART block UFCONO 0x01D00008 UART channel 0 FIFO control register UFCON1 0x01D04008 UART channel 1 FIFO control register Tx FIFO Trigger These two bits determine the trigger level of transmit FIFO Level 00 Empty 01 4 byte 10 8 byte 11 12 byte Rx FIFO Trigger These two bits determine the trigger level of receive FIFO Level 00 4 byte 01 8 byte 10 12 byte 11 16 byte feed B Tx FIFO Re
168. ave an external coprocessor interface It does not have a on chip coprocessor also So then all coprocessor instructions will cause the undefined instruction trap to be taken on the 53 44 These coprocessor instructions can be emulated by the undefined trap handler Even though external coprocessor not be connected to the 53 44 the coprocessor instructions are still described here in for completeness Remember that any external coprocessor described in this section is a software emulation 28 27 24 23 20 19 16 15 12 11 7 5 4 3 Dee om ow 3 0 Coprocessor operand register 7 5 Coprocessor information 11 8 Coprocessor number 15 12 Coprocessor destination register 19 16 Coprocessor operand register 23 20 Coprocessor operation code 31 28 Condition Field Figure 3 25 Coprocessor Data Operation Instruction Only bit 4 and bits 24 to 31 The coprocessor fields are significant to ARM7TDMI The remaining bits are used by coprocessors The above field names are used by convention and particular coprocessors may redefine the use of all fields except CP as appropriate The CP field is used to contain an identifying number in the range 0 to 15 for each coprocessor and a coprocessor will ignore any instruction which does not contain its number in the CP field The conventional interpretation of the instruction is that the coprocessor should perform an operation s
169. be word aligned ie with bits 1 0 set to 0 since the assembler places gt gt 2 in the Offset5 field INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 16 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES LDR R2 R5 116 Load into R2 the word found at the address formed by adding 116 to R5 Note that the THUMB opcode will contain 29 as the Offset5 value STRB R1 0 13 Store the lower 8 bits of R1 at the address formed by adding 13 to RO Note that the THUMB opcode will contain 13 as the Offset5 value 3 86 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET FORMAT 10 LOAD STORE HALFWORD 15 14 13 10 6 5 3 2 0 12 11 _ rm _ 2 0 Source Destination Register 5 3 Base Register 10 6 Immediate Value 11 Load Store Flag 0 Store to memory 1 Load from memory Figure 3 39 Format 10 OPERATION These instructions transfer halfword values between a Lo register and memory Addresses are pre indexed using a 6 bit immediate value The THUMB assembler syntax is shown in Table 3 17 Table 3 17 Halfword Data Transfer Instructions THUMB assembler ARMequivalent Acton ______ STRH Rd STRH Rd Add to base address Rb and store bits 0 15 of Rd at the resultin
170. ber it contains an address 8 bytes on from the address of the current instruction R15 should not be specified as the register offset Rm When R15 is the source register Rd of a Half word store STRH instruction the stored address will be address of the instruction plus 12 DATA ABORTS A transfer to or from a legal address may cause problems for a memory management system For instance system which uses virtual memory the required data may be absent from the main memory The memory manager can signal a problem by taking the processor ABORT input HIGH whereupon the Data Abort trap will be taken It is up to the system software to resolve the cause of the problem then the instruction can be restarted and the original program continued INSTRUCTION CYCLE TIMES Normal LDR H SH SB instructions take 15 1N 11 LDR H SH SB PC take 2S 2 1l incremental cycles S N and are defined as sequential S cycle non sequential N cycle and internal respectively instructions take 2N incremental cycles to execute ELECTRONICS 3 37 ARM INSTRUCTION SET ASSEMBLER SYNTAX 53 44 RISC MICROPROCESSOR lt LDR STR gt cond lt H SH SB gt Rd lt address gt LDR STR cond H SB SH Rd lt address gt can be 1 1 3 38 Load from memory into a register Store from a register into memory Two character condition mnemonic See Table 3 2 Transfer halfword quantity Load sign extend
171. bewainS RW lCCoto ELECTRONICS 1 25 PRODUCT OVERVIEW 53 44 RISC MICROPROCESSOR Table 1 4 S3C44B0X Special Registers Continued Register Address Address Read Name Endian L Endian Write CLOCK amp POWER MANAGEMENT _______________ amp POWER MANAGEMENT PLLCON 0x01d80000 PLL 065 0 01480004 o H Control CLKSLOW 0x01d80008 clock Control LOCKTIME 0x01d8000c PLL lock time Counter time Counter 1 26 ELECTRONICS 53 44 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 4 S3C44B0X Special Registers Continued L Endian Write INTERRUPT CONTROLLER INTCON W R W INTPND Interrupt Request Status INTMOD R W Interrupt Mode Control INTMSK Interrupt Mask Control PSLV IRQ Interrupt Previous Slave PMST IRQ Interrupt Priority Master CSLV IRQ Interrupt Current Slave ISPC w F_ISPC W LCD CONTROLLER LCDCON1 LCD Control 1 LCDCON2 LCD Control 2 LCDCON3 LCD Control 3 LCDSADDR 1 0x01f00008 Frame Upper Buffer Start Address 1 LCDSADDR2 0x01f0000c Frame Lower Buffer Start Address 2 LCDSADDR3 Virtual Screen Address REDLUT RED Lookup Table GREENLUT GREEN Lookup Table BLUELUT BLUE Lookup Table DP1 2 Dithering Pattern duty 1 2 DP4 7 Dithering Pattern duty 4 7 DP3_5 Dithering Pattern duty 3 5 DP2_3 Dithering Pattern duty 2 3 DP5_7 Dithering Pattern duty 5 7 DP3_4 Dithering Pattern duty 3 4 DP4_5 Dith
172. bits define a valid processor mode Only those explicitly described shall be used The user should be aware that if any illegal value is programmed into the mode bits M 4 0 then the processor will enter an unrecoverable state If this occurs reset should be applied Reserved bits The remaining bits in the PSRs are reserved When changing a PSR s flag or control bits you must ensure that these unused bits are not altered Also your program should not rely on them containing specific values since in future processors they may read as one or zero 2 8 ELECTRONICS 53 44 RISC MICROPROCESSOR PROGRAMMER S MODEL Table 2 1 PSR Mode Bit Values M40 Visible THUMB state registers Visible ARM state registers User R7 RO LR SP PC CPSR FIQ 87 80 LR_fiq SP fiq PC CPSR SPSR fiq aJ LR CPSR SPSR irq Supervisor 7 LR svc PC CPSR SPSR svc Abort R7 RO LR_abt SP_abt PC CPSR SPSR_abt Undefined R7 RO LR_und SP_und PC CPSR SPSR_und R7 RO R14 fiq R8 fiq PC CPSR SPSR fiq 12 R14 PC CPSR SPSR irq R12 R0 R14 svc sve PC CPSR SPSHR 12 R14 abt R13 abt PC CPSR SPSR abt 12 R14_und R13_und PC CPSR 14 0 CPSR Reserved bits The remaining bits in the PSR s are reserved When changing PSR s flag or control bits you must ensure tha
173. ble 0 in the IICSTAT IICADD is write enabled The IICADD value can be read any time regardless of the current serial output enable bit IICSTAT setting Slave address 7 1 Not mapped 0 MULTI MASTER IIC BUS TRANSMIT RECEIVE DATA SHIFT REGISTER IICDS IICDS 0x01D6000C transmit receive data shift register X000 Data shift 7 0 8 bit data shift register for IIC bus Tx Rx operation When serial output enable 1 in the IICSTAT IICDS is write enabled The IICDS value can be read any time regardless of the current serial output enable bit IICSTAT setting ELECTRONICS 16 13 IIC BUS INTERFACE S3C44BOX RISC MICROPROCESSOR NOTES 16 14 ELECTRONICS 53 44 RISC MICROPROCESSOR IIS BUS INTERFACE IIS BUS INTERFACE OVERVIEW Many digital audio systems are introduced into the consumer audio market including compact disc digital audio tapes digital sound processors and digital TV sound The S3C44BOX IIS Inter IC Sound bus interface can be used to implement a CODEC interface to an external 8 16 bit stereo audio CODEC IC for mini disc and portable applications It supports the IIS bus data format and MSB justified data format IIS bus interface provides DMA transfer mode for FIFO access instead of an interrupt It can transmit or receive data simultaneously as well as transmit or receive only FEATURES 15 MSB justified format compatible 8 16 bit data per channel 16 32 48fs sam
174. ble 8 16 32 bit data bus width for each bank e Fixed bank start address and programmable bank size for 7 banks e Programmable bank start address and bank size for one bank 8memory banks 6 memory banks for ROM SRAM etc 2 memory banks for ROM SRAM DRAM Fast Page EDO and Synchronous DRAM Fully Programmable access cycles for all memory banks e Supports external wait signal to expend the bus cycle e Supports self refresh mode DRAM SDRAM for power down Supports asymmetric symmetric address of DRAM FEATURES Continued 53 44 RISC MICROPROCESSOR Cache Memory amp internal SRAM 4 set associative ID Unified cache with 8Kbyte e 0 4 8 Kbytes internal SRAM using unused cache memory Pseudo LRU Least Recently Used Replace Algorithm e Write through policy to maintain the coherence between main memory and cache content e Write buffer with four depth e Request data first fill technique when cache miss occurs Clock amp Power Manager e Low power The on chip PLL makes the clock for operating MCU at maximum 66MHz e Clock can be fed selectively to each function block by software e Power mode Normal Slow Idle and Stop mode Normal mode Normal operating mode Slow mode Low frequency clock without PLL Idle mode Stop the clock for only CPU Stop mode All clocks are stopped Wake up by EINT 7 0 or RTC alarm interrupt from Stop mod
175. bles service request When this bit is 0 the SIO can request the DMA service Disables BDMAO service request ELECTRENICS 18 9 SIO 53 44 RISC MICROPROCESSOR NOTES 18 10 ELECTRONICS 53 44 RISC MICROPROCESSOR ELECTRICAL DATA 1 9 ELECTRICAL DATA ABSOLUTE MAXIMUM RATINGS Table 19 1 Absolute Maximum Rating DC Input Voltage 3 3 V Input buffer DC Input Voltage 3 3 V buffer Storage Temperature 40 to 125 _ RECOMMENDED OPERATING CONDITIONS Table 19 2 Recommended Operating Conditions Parameter ____ Commercial temperature range 0 to 70 ELECTRONICS 19 1 ELECTRICAL DATA 53 44 RISC MICROPROCESSOR D C ELECTRICAL CHARACTERISTICS Table 19 3 Normal I O PAD DC Electrical Characteristics Vppp 3 3 V 0 3 V 0 to 70 C Schmitt trigger positive going threshold LVCMOS Schmitt trigger negative going threshold LVCMOS High level input current Input buffer Input buffer with pull up Low level input current Low level output voltage note Stop current Vin Vss OF VT Vu lia VoL lbs Operating current NOTE Type B4 means 4mA output driver cell and Type B8 means 8mA output driver cells 19 2 ELECTRONICS 53 44 RISC MICROPROCESSOR ELECTRICAL DATA Table 19 4 DC Electrical Characteristics TA 0 to 70 C LL um Normal N
176. ceiving B and the parity error occurs while receiving D Although the UART error occurred the error interrupt will not be generated because the character which was received with an error has not been read yet The error interrupt will occur when the character is read out After A is read out The frame error in B interrupt occurs The B has to be read out e 0 1 2 3 4 5 After C is read out The parity error in D interrupt occurs The D has to be read out AterEisreadout o RX FIFO ee break error parity error frame error Figure 10 3 A Case showing UART Receiving 5 Characters with 2 Errors 10 6 ELECTRONICS 53 44 RISC MICROPROCESSOR UART Baud Rate Generation Each UART s baud rate generator provides the serial clock for transmitter and receiver The source clock for the baud rate generator can be selected with the 53 44 0 internal system clock The baud rate clock is generated by dividing the source clock by 16 and a 16 bit divisor specified in the UART baud rate divisor register UBRDIVn The UBRDIVn can be determined as follows UBRDIVn round_off MCLK bps x 16 1 where the divisor should be from 1 to 216 1 For example if the baud rate is 115200 bps and MCLK is 40 MHz UBRDIVn is UBRDIVn int 40000000 115200 x 16 0 5 1 int 21 7 0 5 1 22 1 21 Loop back Mode The S3C44BOX UART provides a test mode referred to as the loopback mode to aid in
177. code will contain 53 as the Word 8 value 3 92 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET FORMAT 13 ADD OFFSET TO STACK POINTER 1514 13 12 11 10 6 0 1 9 8 7 pt 6 0 7 bit Immediate Value 7 Sign Flag 0 Offset is positive 1 Offset is negative Figure 3 42 Format 13 OPERATION This instruction adds a 9 bit signed constant to the stack pointer The following table shows the THUMB assembler syntax Table 3 20 The ADD SP Instruction THUMB assembler ARM equivalent Action O ADD SP ADD R13 R13 Add Imm to the stack pointer SP ADD SP Imm SUB R13 R13 Add Imm to the stack pointer SP NOTE The offset specified by lmm can be up to 508 but must be word aligned ie with bits 1 0 set to 0 since the assembler converts lmm to an 8 bit sign magnitude number before placing it in field SWord7 The condition codes are not set by this instruction INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 20 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES ADD SP 268 SP R13 SP 268 but don t set the condition codes Note that the THUMB opcode will contain 67 as the value 5 0 ADD SP 44 104 SP R13 SP 104 but don t set the condition codes
178. correspond to particular non overlapping decodings of the current instruction If a data abort occurs at the same time as a and FlQs are enabled ie the CPSR s F flag is clear enters the data abort handler and then immediately proceeds to the FIQ vector A normal return from FIQ will cause the data abort handler to resume execution Placing data abort at a higher priority than FIQ is necessary to ensure that the transfer error does not escape detection The time for this exception entry should be added to worst case FIQ latency calculations 2 14 ELECTRONICS 53 44 RISC MICROPROCESSOR PROGRAMMER S MODEL INTERRUPT LATENCIES The worst case latency for FIQ assuming that it is enabled consists of the longest time the request can take to pass through the synchroniser Tsyncmax if asynchronous plus the time for the longest instruction to complete the longest instruction is an LDM which loads all the registers including the PC plus the time for the data abort entry Texc plus the time for entry Tfig At the end of this time ARM7TDMI will be executing the instruction at Ox1C Tsyncmax is processor cycles is 20 cycles Texc is cycles and Tfiq is 2 cycles The total time is therefore 28 processor cycles This is just over 1 4 microseconds in a system which uses a continuous 20 MHz processor clock The maximum IRQ latency calculation is similar but must allow for the fact that FIQ has h
179. cquires the bus mastership DMA operations will continue after the service of higher priority bus master The DMA operations can also be initiated by nXDREQ External DMA request signal as well as S W if the DMA is configured for the external trigger mode i e enable External DMA request by writing QDS bit as 1 in the ZDCONO 1 register In BDMA there are six hardware request sources UARTO UART1 SIO Timer and IIS The BDMA can be initiated by software as the ZDMA These sources can be selected by writing the QSC field in the BDICNT register AUTO RELOAD MODE In the auto reload mode the register content of Z B DCSRCn Z B DCDSTn and Z B DCCNTn are reloaded from the registers of Z B DISRCn Z B DIDESn and Z B DICNTn when the DMA count decreases to 0 The configuration parameters relating to DMA operation are contained in the registers of Z B DISRCn Z B DIDESn and Z B DICNTn for example soure destination address and source destination transfer count This kind of Auto reloading can preschedule DMA operation automatically In other words to change the configuration the configuration in the registers of Z B DISRCn Z B DIDESn and Z B DICNTn should be changed before the end of DMA operation based on current configuration But this kind of parameter auto reloading can not guarantee the DMA re run automatically after the current DMA operation The DMA will re run if CMD field is written newly or external DMA request is issued
180. cted to power properly if RTC isn t used IW S ELECTRONICS 1 21 PRODUCT OVERVIEW 53 44 RISC MICROPROCESSOR S3C44BOX SPECIAL REGISTERS Table 1 4 S3C44BOX Special Registers Register Address Address Read Name B Endian L Endian Write CPU WRAPPER SYSCFG 0 01 00000 Oo Configuration NCACHBEO 0 01 00004 rr Cacheable Area 0 NCACHBE1 0x01c00008 Cacheable Area 1 SBUSCON 0 01 40000 EE Bus Control MEMORYCONTROLLER ees CONTROLLER MRSRB6 0 01 8002 MRSRB7 0x01c80030 Mode set for SDRAM Mode Mode register set for SDRAM set for SDRAM EHE Width amp Wait Status Control Boot ROM Control ROM Control BANK2 Control BANK4 ET Control o Control BANK7 ER Refresh Control ee Bank Size 1 22 ELECTRONICS 53 44 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 4 S3C44B0X Special Registers Continued _ Endian L Endian Write R W UART 0 Line Control UART 1 Line Control UART 1 Control UART 0 FIFO Control UART 1 FIFO Control UART 0 Modem Control UART 1 Modem Control UART 0 Tx Rx Status UART 1 Tx Rx Status UART 1 Rx Error Status UART 0 FIFO Status UART 1 FIFO Status UART 0 Modem Status UART 1 Modem Status B UART 0 Transmission Hold UTXH1 0x01d04023 0x01d04020 UART 1 Transmission Hold URXHO 0x01d00027 0x01d00024 UART 0
181. cumulate forms UMLAL and SMLAL take two 32 bit numbers multiply them and add a 64 bit number to produce 64 bit result of the form RdHi RdLo Rm Rs RdHi RdLo The lower 32 bits of the 64 bit number to add is read from RdLo The upper 32 bits of the 64 bit number to add is read from RdHi The lower 32 bits of the 64 bit result are written to RdLo The upper 32 bits of the 64 bit result are written to RdHi The UMULL and UMLAL instructions treat all of their operands as unsigned binary numbers and write an unsigned 64 bit result The SMULL and SMLAL instructions treat all of their operands as two s complement signed numbers and write a two s complement signed 64 bit result ELECTRONICS 3 25 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR OPERAND RESTRICTIONS e R15 must be used as an operand or as a destination register RdLo and Rm must all specify different registers CPSR FLAGS Setting the CPSR flags is optional and is controlled by the S bit in the instruction The N and Z flags are set correctly on the result N is equal to bit 63 of the result Z is set if and only if all 64 bits of the result are zero Both the C and V flags are set to meaningless values INSTRUCTION CYCLE TIMES MULL takes 15 m 1 l MLAL 15 m 2 I cycles to execute where m is the number of 8 bit multiplier array cycles required to complete the multiply which is controlled by the value of the multiplier operand speci
182. d total eight bits The number of bytes which can be sent or received during the bus transfer operation is unlimited Data is always sent from most significant bit MSB first and every byte should be immediately followed by an acknowledge ACK bit ELECTRONICS 16 1 IIC BUS INTERFACE S3C44BOX RISC MICROPROCESSOR Address Register Comparator IIC Bus Control Logic IICSTAT 4 bit Prescaler Shift Register lt SDA Shift Register IICDS f Data Bus Figure 16 1 Block Diagram Note The IIC data hold time tSDAH is minimum Ons Refer to figure 19 52 1 The IIC data hold time tSDAH is minimum Ons Please check the data hold time of your IIC device IIC data hold time is minimum Ons for standard fast bus mode in IIC specification v2 1 2 The IIC controller supports only IIC bus device standard fast bus mode not C bus device 16 2 ELECTRONICS 53 44 RISC MICROPROCESSOR IIC BUS INTERFACE THE IIC BUS INTERFACE The 53 44 IIC bus interface has four operation modes Master transmitter mode Master receive mode Slave transmitter mode Slave receive mode Functional relationships among these operating modes are described below START AND STOP CONDITIONS When the interface is inactive it is usually in slave mode In other words the interface should be in slave mode before detecting a Start condition on the SDA line A Start condition can be
183. de Rx interrupt Each time receive data reaches the trigger Each time receive data becomes full the level of receive FIFO the Rx interrupt will be receive shift register generates an interrupt generated When the FIFO is not empty and does not receive data during 3 word time the Rx interrupt will be generated receive time out Tx interrupt Each time transmit data reaches the trigger Each time transmit data become empty level of transmit FIFO the Tx interrupt will be the transmit holding register generates an generated interrupt Error interrupt Frame error parity error and break signal are All errors generate an error interrupt detected and received in bytes and will immediately However if another error generate an error interrupt occurs at the same time only one interrupt When it gets to the top of the receive FIFO is generated the error interrupt will be generated overrun error ELECTRENICS 10 5 UART 53 44 RISC MICROPROCESSOR UART Error Status FIFO UART has the status FIFO besides the Rx FIFO register The status FIFO indicates which data among FIFO registers is received with an error The error interrupt will be issued only when the data which has an error is ready to read out To clear the status of FIFO the URXHn with an error and UERSTATn must be read out For example It is assumed that the UART FIFO receives A B C D E characters sequentially and the frame error occurrs while re
184. e Interrupt Controller e 30 Interrupt sources Watch dog timer 6 Timer 6 UART 8 External interrupts 4 DMA 2 RTC 1 ADC 1 IIC 1 SIO e Vectored IRQ interrupt mode to reduce interrupt latency Level edge mode on the external interrupt sources Programmable polarity of edge and level e Supports Fast Interrupt request for very urgent interrupt request ELECTRONICS 53 44 RISC MICROPROCESSOR Timer with PWM Pulse Width Modulation e 5 16 bit Timer with PWM 1 ch 16 bit internal timer with DMA based or interrupt based operation e Programmable duty cycle frequency and polarity e Dead zone generation Supports external clock source RTC Real Time Clock e Full clock feature msec sec min hour day week month year e 32 768 KHz operation e Alarm interrupt for CPU wake up e Time tick interrupt General purpose input output ports e 8 external interrupt ports 71 multiplexed input output ports UART e 2 UART with DMA based or interrupt based operation Supports 5 bit 6 bit 7 bit or 8 bit serial data transmit receive Supports H W handshaking during transmit receive e Programmable baud rate Supports IrDA 1 0 115 2kbps back mode for testing e Each channel have two internal 32 byte FIFO for Rx and Tx 1 3 PRODUCT OVERVIEW DMA Controller e 2 channel general purpose Direct Memory Access controller w
185. e resulting address into a register The THUMB assembler syntax is shown in the following table Table 3 19 Load Address THUMB assembler ARMequivalent Action ADD Rd PC ADD R15 lmm Add 1 to the current value of the program counter PC and load the result into Rd ADD SP lmm ADD R13 Imm Add stlmm to the current value of the stack pointer SP and load the result into Rd NOTE The value specified by is a full 10 bit value but this must be word aligned ie with bits 1 0 set to 0 since the assembler places gt gt 2 in field Word 8 Where the PC is used as the source register SP 0 bit 1 of the PC is always read as 0 The value of the PC will be 4 bytes greater than the address of the instruction before bit 1 is forced to O The CPSR condition codes are unaffected by these instructions ELECTRONICS 3 91 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 19 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES ADD R2 PC 572 R2 572 but don t set the condition codes bit 1 of PC is forced to zero Note that the THUMB opcode will contain 143 as the Word8 value ADD R6 SP 212 R6 SP R13 212 but don t set the condition codes Note that the THUMB op
186. e 1 Operating Mode 0 Booting ROM Data width Programming Memory Controller All thirteen memory control registers have to be written using the STMIA instruction as shown in the following example Idr r0 SMRDATA Idmia r1 r13 Idr rO 0 01 80000 BWSCON Address stmia r1 r13 SMRDATA DATA DCD 0x22221210 BWSCON DCD 0x00000600 GCSO DCD 0x00000700 GCS1 DCD 0x00000700 GCS2 DCD 0x00000700 GCS3 DCD 0x00000700 GCS4 DCD 0x00000700 GCS5 DCD 0x0001002a GCS6 EDO DRAM Trcd 3 2 Tcp 1 CAN 10bit DCD 0x0001002a GCS7 EDO DRAM DCD 0x00960000 953 Refresh REFEN 1 TREFMD O Trp 3 Trc 5 Tchr 3 DCD 0x0 Bank Size 32MB 32MB DCD 0x20 MRSR 6 CL 2 DCD 0x20 MRSR 7 CL 2 ELECTRENICS 4 3 MEMORY CONTROLLER 53 44 RISC MICROPROCESSOR MEMORY SROM DRAM SDRAM ADDRESS PIN CONNECTIONS MEMORY ADDR PIN S3C44BOX ADDR S3C44BOX ADDR S3C44B0X ADDR 8 bit DATA BUS 16 bit DATA BUS 32 bit DATA BUS 4 4 ELECTRONICS 53 44 RISC MICROPROCESSOR MEMORY CONTROLLER SDRAM BANK ADDRESS PIN CONNECTION Table 4 2 SDRAM Bank Address configuration Bank Size Width Base Component Memory Configuration Bank Address x8 16Mbit 1M x 8 x 2Bank x 1 512K x 16 x 2B 1 1 1 16 1M x 16 x 4B 1 22 21 ow Ce EE e TES c 8 8
187. e base address should normally be a word aligned quantity The bottom 2 bits of the address will appear on 1 0 and might be interpreted by the memory system USE OF R15 If Rn is R15 the value used will be the address of the instruction plus 8 bytes Base write back to R15 must not be specified DATA ABORTS If the address is legal but the memory manager generates an abort the data trap will be taken The write back of the modified base will take place but all other processor state will be preserved The coprocessor is partly responsible for ensuring that the data transfer can be restarted after the cause of the abort has been resolved and must ensure that any subsequent actions it undertakes can be repeated when the instruction is retried INSTRUCTION CYCLE TIMES Coprocessor data transfer instructions take n 1 S 2N bl incremental cycles to execute where The number of words transferred The number of cycles spent in the coprocessor busy wait loop 5 are defined as sequential S cycle non sequential N cycle and internal respectively 3 54 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLER SYNTAX lt LDC STC gt cond L p cd lt Address gt LDC Load from memory to coprocessor STC Store from coprocessor to memory L When present perform long transfer N 1 otherwise perform short transfer N 0 cond Two character condition mnemonic See Table 3 2 p The
188. e cache is not updated when cache misses a read Usually a cache stores any data in the whole system memory area but sometimes it needs a non cacheable area because the cache cannot keep track of the external memory device whose contents are changed without read write operation The size of a non cacheable area can be increased decreased by 4KB units The end address has to point the next 4KB block For example if non cacheable area is 0x10000 0x22fff the start address value of NCACHBEn is 0x10 and the end address value of NCACHBEn is 0x23 To Speed Up a Program Execution by Considering Cache Usage 1 Locates the ISRs which is executed most frequently on the internal SRAM 2 Let ISR not be cached Most ISR codes cause a cache miss and the codes in the cache memory are not re used because the code is erased by main codes executed after exiting the ISR 3 Locates the functions which are related to each other together and executes them concurrently This function aggregation reduce cache misses 4 Somtimes if the data area is assigned as non cachable area the program execution speed will be higher because most variables are not re used Refreshing the 16 byte cache memory is wasteful for un reused variables 6 4 ELECTRONICS 53 44 RISC MICROPROCESSOR CPU WRAPPER amp BUS PRIORITIES INTERNAL SRAM INTERNAL MEMORY MAP 53044 has a maximum 8 KB 4way set associative cache or internal SRAM If the internal SRAM is 4
189. e endian mode is Little Bi HW Access by halfword unit when the endian mode is Big ELECTRONICS 17 9 IIS BUS INTERFACE 53 44 RISC MICROPROCESSOR NOTES 17 10 ELECTRONICS 53 44 RISC MICROPROCESSOR 510 SIO SYNCHRONOUS 10 OVERVIEW The 53 44 SIO synchronous IO can interface with various types of external devices that requires serial data transfer The SIO module can transmit or receive 8bit serial data at a frequency determined by its corresponding control register settings To ensure flexible data transmission rates you can select an internal or external clock source FEATURES 8 bit Data Buffer SIODAT 12 bit Prescaler SBRDR 8 bit Interval Counter ITVCNT Clock Selection Logic Serial data pins SIORXD and SIOTXD External clock input output pin SIOCK run mode auto run flag run SIORDY SIORDY SIO Control Logic 8 bit SIO Shift Buffer gt gt SIOTXD MCLK 12 bit Prescaler MUX SIORXD Data Bus Figure 18 1 SIO Interface Block Diagram ELECTRONICS 18 1 SIO 53 44 RISC MICROPROCESSOR SIO NORMAL OPERATION Transmit and Receive by Serial Line Synchronously Using the serial I O interface 8 bit data can be exchanged by serial line The serial output data comes through a serial input pin SIORXD and goes out through a serial output pin synchronously by serial clock pin SIOCK After transmitting or receiving data the SI
190. e not been required W 0 Rn would have retained its initial value of 0x1000 unless it was also in the transfer list of a load multiple register instruction when it would have been overwritten with the loaded value ADDRESS ALIGNMENT The address should normally be a word aligned quantity and non word aligned addresses do not affect the instruction However the bottom 2 bits of the address will appear A 1 0 and might be interpreted by the memory system 0 100 0 100 0 1000 0 1000 OxOFF4 1 100 0 1000 OxOFF4 Figure 3 19 Post Increment Addressing ELECTRONICS 3 41 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR 0 100 0000 O 0 1000 0x1000 OxOFFA 2 0x100C 0x1000 OxOFF4 5 _ L m 8 3 Figure 3 21 Post Decrement Addressing 3 42 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET 0 100 0 100 0 1000 0 1000 OxOFF4 1 _________ 100 0 1000 OxOFF4 Figure 3 22 Pre Decrement Addressing USE OF THE S BIT When the 5 bit is set in a LDM STM instruction its meaning depends on whether or not R15 is in the transfer list and on the type of instruction The S bit should only be set if the instruction is to execute in a privileged mode LDM with R15 in Transfer List and S Bit Set Mode Changes If the instruction is then SPSR mode is transferred to CPSR a
191. ead from the corresponding bit of PDATn PORT PULL UP REGISTER PUPC G The port pull up resistor controls the pull up resistor enable disable of each port group When the corresponding bit is 0 the pull up resistor of the pin is enabled When 1 the pull up resistor is disabled EXTERNAL INTERRUPT CONTROL REGISTER The 8 external interrupts are requested by various signaling methods The EXTINT register configures the signaling method among the low level trigger high level trigger falling edge trigger rising edge trigger and both edge triggers for the external interrupt request Because each external interrupt pin has a digital filter the interrupt controller can recognize the request signal longer than 3 clocks ELECTRENICS 8 5 PORTS 3C44B0X RISC MICROPROCESSOR PORT CONTROL REGISTER PORT A CONTROL REGISTERS PCONA PDATA PUPA Port A control registers are shown in Table 8 2 0 01020000 Configures the pins of port A PDATA 0x01D20004 The data register for port A Table 8 2 Port of Group A Control Registers PCONA PDATA Pag 8 0 1 ADDR24 7 0 Output 1 ADDR22 PA 9 0 9 0 When the port is configured as an output port the pin state is the same as the corresponding bit When the port is configured as a functional pin an undefined value will be read 8 6 ELECTRENICE 53 44 RISC MICROPROCESSOR PORTS PORT B CONTROL REGISTERS PCONB PDATB Port B
192. ecompressed to the ARM instructions by the Thumb decompressor inside the ARM7TDMI core As the Thumb instructions are compressed ARM instructions the Thumb instructions have the 16 bit format instructions and have some restrictions The restrictions by 16 bit format is fully notified for using the Thumb instructions FORMAT SUMMARY The THUMB instruction set formats are shown in the following figure 15 14 13 12 11 Offset8 Word8 s o je m Toe C COE 11011131 Ris vaes Offset 15 14 13 12 11 10 9 8 7 6 Move Shifted register Add subtract Move compare add subtract immediate ALU operations Hi register operations branch exchange PC relative load Load store with register offset Load store sign extended byte halfword Load store with immediate offset Load store halfword SP relative load store Load address Add offset to stack pointer Push pop register Multiple load store Conditional branch Software interrupt Unconditional branch Long branch with link Figure 3 29 THUMB Instruction Set Formats ELECTRONICS 3 65 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR OPCODE SUMMARY The following table summarizes the THUMB instruction set For further information about a particular instruction p
193. ed as sequential S cycle non sequential and internal I cycle respectively ASSEMBLER SYNTAX lt SWP gt cond B Rd Rm Rn cond Two character condition mnemonic See Table 3 2 B If B is present then byte transfer otherwise word transfer Rd Rm Rn Expressions evaluating to valid register numbers EXAMPLES SWP RO R1 R2 Load with the word addressed by R2 and Store R1 at R2 SWPB R2 R3 R4 Load R2 with the byte addressed by R4 and Store bits 0 to 7 of R3 at R4 SWPEQ RO RO R 1 Conditionally swap the contents of the word addressed by R1 with RO 3 48 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET SOFTWARE INTERRUPT SWI The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 24 below 31 28 27 24 23 0 1111 Comment Field Ignored by Processor 31 28 Condition Field Figure 3 24 Software Interrupt Instruction The software interrupt instruction is used to enter Supervisor mode in a controlled manner The instruction causes the software interrupt trap to be taken which effects the mode change The PC is then forced to a fixed value 0x08 and the CPSR is saved in SPSR_sve If the SWI vector address is suitably protected by external memory management hardware from modification by the user a fully protected operating system may be constructed RETURN FROM THE SUPERVISOR
194. ed by adding R2 to 3 84 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET FORMAT 9 LOAD STORE WITH IMMEDIATE OFFSET 15 14 13 12 11 10 6 5 3 2 0 ra 2 0 Source Destination Register 5 3 Base Register 10 6 Offset Register 11 Load Store Flag 0 Store to memory 1 Load from memory 12 Byte Word Flad 0 Transfer word quantity 1 Transfer byte quantity Figure 3 38 Format 9 ELECTRONICS 3 85 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR OPERATION These instructions transfer byte or word values between registers and memory using an immediate 5 or 7 bit offset The THUMB assembler syntax is shown in Table 3 16 Table 3 16 Summary of Format 9 Instructions STR Rd Rb lmm STR Rd Rb lmm Calculate the target address by adding together the value in Rb and Imm Store the contents of Rd at the address LDR Rd Rb LDR Rd Rb Calculate the source address by adding together the value in Rb and Imm Load Rd from the address STRB Rd Rb lmm STRB Rd Rb Imm Calculate the target address by adding together the value in Rb and Imm Store the byte value in Rd at the address LDRB Rd Rb lmm LDRB Rd Rb Calculate source address by adding together the value in Rb and Imm Load the byte value at the address into Rd NOTE For word accesses 0 the value specified by lmm is a full 7 bit address but must
195. ed byte Only valid for LDR Load sign extended halfword Only valid for LDR An expression evaluating to a valid register number An expression which generates an address The assembler will attempt to generate an instruction using the PC as a base anda corrected immediate offset to address the location given by evaluating the expression This will be a PC relative pre indexed address If the address is out of range an error will be generated A pre indexed addressing specification Rn offset of zero Rn lt expression gt offset of lt expression gt bytes Rn Rm offset of contents of index register A post indexed addressing specification Rn lt expression gt Rn Rm offset of expression bytes offset of contents of index register Rn and Rm are expressions evaluating to a register number If Rn is R15 then the assembler will subtract 8 from the offset value to allow for ARM7TDMI pipelining this case base write back should not be specified Writes back the base register set the W bit if is present ELECTRONICS 53 44 RISC MICROPROCESSOR EXAMPLES LDRH STRH LDRSB LDRNESH HERE STRH FRED ELECTRONICS R1 R2 R3 R3 R4 4H 4 R8 R2 4 223 R11 RO R5 PC FRED HERE 8 ARM INSTRUCTION SET Load R1 from the contents of the halfword address contained in R2 R3 both of which are registers and write back address to R2 Store the halfword in
196. egister 54 65 Please refer to a sample program source for the latest value of this register 7 Description Initial state state DP4 7 EM 0 Recommended pattern value Oxba5da65 1011 1010 0101 1101 1010 0110 0101 5 5 Dithering Pattern DP3 5 Register DP3 5 0x01F00028 R W Dithering pattern duty 3 5 register 5 Please refer to a sample program source for the latest value of this register Description Initial state state DP3_5 19 0 Recommended pattern value 5 1010 0101 1010 0101 1111 Oxa5a5f 12 22 ELECTRONICS 53 44 RISC MICROPROCESSOR LCD CONTROLLER Dithering Pattern DP2_3 Register DP2_3 0x01F0002C R W Dithering pattern duty 2 3 register Please refer to a sample program source for the latest value of this register DP23 Bi Description Initial state state DP2 3 11 0 Recommended pattern value Oxd6b 1101 0110 1011 Oxd6b Dithering Pattern DP5_7 Register 5 7 0x01F00030 R W Dithering pattern duty 5 7 register Oxeb7b5ed Please refer to a sample program source for the latest value of this register Description Initial state Recommended pattern value Oxeb7b5ed 1110 1011 0111 1011 0101 1110 1101 Oxeb7b5ed Dithering Pattern DP3_4 Register 4 0x01F00034 R W Dithering pattern duty 3 4 register Ox7dbe Please refer to a sample program source for the latest value of this register DP3_4
197. eive 1 Parity error Overrun Error This bit is automatically set to 1 whenever an overrun error occurs during receive operation 0 No overrun error during receive 1 Overrun error NOTE These bits UERSATn 3 0 are automatically cleared to 0 when the UART error status register is read 10 14 ELECTRONICS 53 44 RISC MICROPROCESSOR UART UART FIFO STATUS REGISTER Only the UARTn has a 16 byte transmit FIFO amp a 16 byte receive FIFO There two UART FIFO status registers UFSTATO and UFSTAT1 in the UART block UFSTATO 0x01D00018 oR UART channel 0 FIFO status register UFSTAT1 0x01D04018 UART channel 1 FIFO status register Rx FIFO Full 0 0 byte lt Rx FIFO data lt 15 byte 1 Full Tx FIFO Count 7 4 Number of data in Tx FIFO Rx FIFO Count 3 0 Number of data in Rx FIFO Tx FIFO Full This bit is automatically set to 1 whenever transmit FIFO is full during transmit operation 0 0 byte lt Tx FIFO data lt 15 byte 1 Full This bit is automatically set to 1 whenever receive FIFO is full during receive operation ELECTRENICS 10 15 UART 53 44 RISC MICROPROCESSOR UART MODEM STATUS REGISTER There are two UART modem status register UMSTATO and UMSTAT1 in the UART block UMSTATO 0x01D0001C oR UART channel 0 Modem status register UMSTAT1 0x01D0401C oR UART channel 1 Modem status register Delta CTS 4 This bit indicates that the nCTS input to S3C44BOX has changed s
198. ens before the successive 4 word DMA write cycle as shown in Figure 7 10 Figure 7 10 shows an example of the block transfer mode with single step mode If the block transfer mode is used the total data size to be transferred should be a multiple of 16 bytes In other words the minimum transfer size is 16 bytes i e 4 words Because the DMA count is defined in byte unit 16 should be the DMA transfer count in the case of 4 words transfer If the transfer size or DMA count is not a multiple of 16 for example 16 32 48 64 and so on the DMA can not transfer the data completely If assume 100 bytes transfer DMA count is 100 6x16 96 bytes can be transferred But the remaining 4 bytes can not be transferred because DMA operation will be stopped after 96 bytes transfer The users should be aware of this characteristics when they select the block transfer mode of DMA NOTE The ADDR 3 0 should be 0 to meet 16 byte align condition in Block Transfer Mode nXDREQ 1 nXDACK 1 Read Burst Ready Write Burst Figure 7 10 Block Transfer Mode With Single Step Mode ELECTRONICS 7 9 DMA 53 44 RISC MICROPROCESSOR On the fly Transfer Mode The on the fly transfer mode means that when DMA reads writes data a fixed addressed external device writes reads the data by DMA acknowledge signals nXDACKO 1 In the other modes the DMA reads data before writing the data In on the fly transfer mode the read and write opera
199. ented as 0x13FFFFFF38 so the least significant 32 bits are OxFFFFFF38 Operand Restrictions The destination register Rd must not be the same as the operand register Rm R15 must not be used as an operand or as the destination register All other register combinations will give correct results and Rd Rn and Rs may use the same register when required ELECTRONICS 3 23 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR CPSR FLAGS Setting the CPSR flags is optional and is controlled by the S bit in the instruction The N Negative and Z Zero flags are set correctly on the result N is made equal to bit 31 of the result and Z is set if and only if the result is zero The C Carry flag is set to a meaningless value and the V oVerflow flag is unaffected INSTRUCTION CYCLE TIMES MUL takes 15 and MLA 15 m 1 I cycles to execute where S and are defined as sequential S cycle and internal respectively m The number of 8 bit multiplier array cycles is required to complete the multiply which is controlled by the value of the multiplier operand specified by Rs Its possible values are as follows If bits 32 8 of the multiplier operand are all zero or all one If bits 32 16 of the multiplier operand are all zero or all one If bits 32 24 of the multiplier operand are all zero or all one N In all other cases ASSEMBLER SYNTAX MUL cond S Rd Rm Rs MLA cond S Rd Rm Rs Rn cond
200. er VLINE pulse HOZVAL VLINEBLANK and LINEVAL in LCDCON1 and LCDCONe registers as well as VCLK and MCLK Most LCD drivers need their own adequate frame rate The frame rate is calculated as follows frame rate Hz 1 1 VCLK x HOZVAL 1 1 MCLK WLH WDLY LINEBLANK x LINEVAL 1 VCLK Hz HOZVAL 1 1 frame rate x LINEVAL 1 WLH WDLY LINEBLANK MCLK 12 4 ELECTRONICS 53 44 RISC MICROPROCESSOR LCD CONTROLLER Table 12 1 Relation between and CLKVAL MCLK 60MHz CLKVAL 60MHz X VCLK 60 MHz 4 15 0 MHz 60 MHz 6 10 0 MHz 1023 60 MHz 2046 29 3 kHz VIDEO OPERATION The LCD controller within S3C44BOX supports 8 bit color mode 256 color mode 4 level gray scale mode 16 level gray scale mode as well as the monochrome mode When the gray or color mode is needed the time based dithering algorithm and FRC Frame Rate Control method can be used to implement the shades of gray or color from which selection can be made by using a programmable lockup table which will be explained later The monochrome mode bypasses these modules FRC and lookup table and basically serializes the data in FIFOH and FIFOL if a dual scan display type is used into 4 bit or 8 bit if a 4 bit dual scan or 8 bit single scan display type is used streams by shifting the video data to the LCD driver The following sections describe the operation on gray mode and color mode in terms of the lookup table and FRC Lookup T
201. er is working to maintain the LCD screen Less power is consumed in the SL_ILDE mode than in the IDLE mode Before entering into SL_IDLE mode SLOW mode has to be entered and PLL has to be turned off After SLOW mode entrance and PLL off 0x46 LCDC enable IDLE enable and SL_IDLE enable should be written into the CLKCON register to enter into SL_IDLE mode To exit SL_IDLE mode EINT 7 0 or RTC alarm interrupt has to be activated In this case the processor mode will change into Slow Mode automatically as shown in Fig 5 11 To return to Normal mode users have to wait until the end of lock time then disable the SLOW mode and clear the SL_IDLE bit In the PLL lock time the SLOW clock is supplied DRAM has to be in self refresh mode during SL_IDLE mode to retain the valid data in DRAM y S WLocktine y PLL_CLK Slow mode enable Slow mode disable Wake_Up is accured by after lock time Wake_Up Alarm or EINT 7 0 PLL off PLL off SL_IDLE SL_IDLE enable IDLE modes end FOUT A Devided OSC It changes to PLL clock after _4 clock slow mode is disabled Figure 5 7 Entering SL_IDLE Mode and Exiting SL_IDLE Mode Wake up ELECTRONICS 5 9 CLOCK amp POWER MANAGEMENT 53 44 RISC MICROPROCESSOR SLOW Mode non PLL Mode Power consumption can be reduced in the SLOW mode by applying a slow clock and excluding the power consumption from the PLL itself The Fout is the frequency of divide_by_n of Fin
202. ering Pattern duty 4 5 DP6_7 Dithering Pattern duty 6 7 DITHMODE Dithering Mode Interrupt Control IRQ Interrupt Current Master IRQ Interrupt Pending Status IRQ Interrupt Pending Clear FIQ Interrupt Pending FIQ Interrupt Pending Clear d ELECTRENICE 1 27 PRODUCT OVERVIEW 53 44 RISC MICROPROCESSOR Table 1 4 53 44 Special Registers Concluded Register Address Address Read W Name m a 77 Endian L Endian rite Control ZDMA 0 2 0 Initial Source Address 5 ZDMA 0 Initial Transfer Count ZDMA 0 ZDMA 0 Current Destination Address Destination Address 2 0 Current Transfer Count 0 2 0 Current Transfer Count Transfer Count RW ZDMA 1 E Source Address ZDMA 1 E Destination Address ZDMA 1 ZDMA 1 Initial Transfer Count Transfer Count ZDMA 1 Current Destination Address ZDMA 1 ZDMA 1 Current Transfer Count Transfer Count BDMA 0 Control 0 Initial Source Address 0 Initial Source Address Source Address BDMA me 0 Initial Destination Address Destination Address BDMA 0 0 Initial Transfer Count Transfer Count BDMA 0 Current Destination Address Destination Address BDMA 0 0 Current Transfer Count Transfer Count 1 Initial Source Address 1 1 Initial Source Address Source Address BDMA 1 Ini
203. ero by writing 1 on ISPC F ISPC This feature reduces the code size to clear the INTPND The corresponding INTPND bit is cleared automatically by ISPC INTPND register not be cleared directly NOTE To clear the ISPC F ISPC the following two rules has to be obeyed 1 The ISPC F ISPC registers are accessed only once in ISR interrupt service routine 2 The pending bit in ISPR INTPND register should be cleared by writing ISPC register If these two rules are not followed ISPR and INTPND register may be 0 although the interrupt has been requested ISPC 0x01E00024 IRQ interrupt service pending clear register F ISPC 0x01E0003C FIQ interrupt service pending clear register 11 22 ELECTRONICS 53 44 RISC MICROPROCESSOR INTERRUPT CONTROLLER NWOT e ELECTRONICS 11 23 53 44 RISC MICROPROCESSOR LCD CONTROLLER LCD CONTROLLER OVERVIEW LCD controller within S3C44BOX consists of logic for transferring LCD image data from a video buffer located in system memory to an external LCD driver The LCD controller supports monochrome 2 bit per pixel 4 level gray scale or 4 bit per pixel 16 level gray scale mode on a monochrome LCD using a time based dithering algorithm and FRC Frame Rate Control method It can support 8 bit per pixel 256 level color for interfacing with a color LCD panel also The LCD controller can be pr
204. es of the bits in the instruction are shown in the following table 3 6 Table 3 6 Addressing Mode Names Pre Increment Load Post Increment Load Pre Decrement Load Post Decrement Load Pre Increment Store Post Increment Store Pre Decrement Store Post Decrement Store O O FD ED FA EA define pre post indexing and the up down bit by reference to the form of stack required The F and E refer to a full or empty stack i e whether a pre index has to be done full before storing to the stack The A and D refer to whether the stack is ascending or descending If ascending a STM will go up and LDM down if descending vice versa IA IB DA DB allow control when LDM STM are not being used for stacks and simply mean Increment After Increment Before Decrement After Decrement Before ELECTRONICS 3 45 ARM INSTRUCTION SET EXAMPLES LDMFD SPL RO RI R2 STMIA RO RO R15 LDMFD SPI R15 LDMFD _ 15 STMFD 3 814 53 44 RISC MICROPROCESSOR Unstack 3 registers Save all registers R15 SP CPSR unchanged R15 SP CPSR SPSR mode allowed only in privileged modes Save user mode regs on stack allowed only in privileged modes These instructions may be used to save state on subroutine entry and restore it efficiently on return to the calling routine STMED SP RO R3 R14 BL somewhere LDMED SP RO R3 R15 3 46 Save RO to R3 to use as workspace
205. f 1 Inverter on for TOUT1 Timer 1 manual This bit determines the manual update for Timer 1 update note 0 operation 1 Update TCNTB1 TCMPB1 Timer 1 start stop This bit determines start stop for Timer 1 0 Stop 1 Start for Timer 1 Dead zone enable 4 This bit determines the dead zone operation 0 Disable 1 Enable Timer 0 auto reload 3 This bit determines auto reload on off for Timer 0 on off 0 One shot 1 Interval mode auto reload Timer 0 output bit determines the output inverter on off for Timer 0 inverter on off Inverter off 1 Inverter on for TOUTO Timer 0 manual This bit determines the manual update for Timer 0 update note 0 No operation 1 Update TCNTBO TCMPBO Timer 0 start stop This bit determines start stop for Timer 0 0 Stop 1 Start for Timer 0 NOTE This bit has to be cleared at next writing ELECTRONICS 53 44 RISC MICROPROCESSOR PWM TIMER TIMER 0 COUNT BUFFER REGISTER amp COMPARE BUFFER REGISTER TCNTBO TCNTBO 0 0105000 Timer 0 count buffer register 0x00000000 TCMPBO 0x01D50010 Timer 0 compare buffer register 0x00000000 Timer 0 compare Setting compare buffer value for Timer 0 0x00000000 buffer register NOTE This value must be smaller than TCNTBO Timer 0 count buffer 15 0 Setting count buffer value for Timer 0 0x00000000 register TIMER 0 COUNT OBSERVATION REGISTER TCNTOO TCNTOO 0x01D50014 oR Timer 0 count observation reg
206. f the VLINE finely The unit of LINEBLANK is MCLK Ex If the value of LINEBLANK is 10 the blank time is inserted to VCLK during 10 system clocks HOZVAL 20 10 These bits determine the horizontal size of the LCD panel 0 000 HOZVAL has to be determined to meet the condition that total bytes of 1 line be 2n bytes If the x size of LCD is 120 dots in mono mode x 120 can not be supported because 1 line consists of 15 bytes Instead x 128 in mono mode can be supported because 1 line consists of 16 bytes 2n The additional 8 dot will be discarded by LCD panel driver LINEVAL 9 0 These bits determine the vertical size of LCD panel 0x000 LCD Control 3 Register LCDCON3 0x01F00040 Test Mode Enable Register 2 1 reserved for test SELFREF LCD self refresh mode enable bit 0 LCD self refresh mode disable 1 LCD self refresh mode enable ELECTRINICS 12 17 LCD CONTROLLER 53 44 RISC MICROPROCESSOR FRAME Buffer Start Address 1 Register LCDSADDR 1 0x01F00008 Frame buffer start address 1 register 0x000000 MODESEL 28 27 These bits select the monochrome gray or color mode 00 monochrome mode 01 4 level gray mode 10 16 level gray mode 11 color mode LCDBANK 26 21 These bits indicate A 27 22 of the bank location for the video buffer in the system memory LCDBANK value can not be changed even when moving the view port LCD frame buffer should be inside aligned 4MB region which ensures that LCDBANK va
207. f transfer request is accepted by bus arbitrator in the memory controller there will be four successive word data transfers from system memory to internal FIFO The total size of FIFO is 24 words which consists of FIFOL and FIFOH of 12 words The 53 44 has two FIFOs because it needs to support the dual scan display mode In case of single scan mode one of them can only be used ELECTRIDNICS 12 3 LCD CONTROLLER 53 44 RISC MICROPROCESSOR LCD CONTROLLER OPERATION TIMING GENERATOR The TIMEGEN generates the control signals for LCD driver such as VFRAME VLINE VCLK and VM These control signals are closely related to the configuration on the LCDCON1 2 register in the REGBANK Based on these programmable configurations on the LCD control registers in REGBANK the TIMEGEN can generate the programmable control signals suitable to support many different types of LCD drivers The VFRAME pulse is asserted for a duration of the entire first line at a frequency of once per frame The VFRAME signal is asserted to bring the LCD s line pointer to the top of the display to start over The VM signal is used by the LCD driver to alternate the polarity of the row and column voltage used to turn the pixel on and off The toggle rate of VM signal can be controlled by using the MMODE bit of LCDCON 1 register and MVAL 7 0 field of LCDSADDR 2 register If the MMODE bit is 0 the VM signal is configured to toggle on every frame If the MMODE bit is 1
208. fer operation completely the receiver should send an ACK bit to the transmitter The ACK pulse should occur at the ninth clock of the SCL line Eight clocks are required for the one byte data transfer The master should generate the clock pulse required to transmit the ACK bit The transmitter should release the SDA line by making the SDA line High when the ACK clock pulse is received The receiver should also drive the SDA line Low during the ACK clock pulse so that the SDA is Low during the High period of the ninth SCL pulse The ACK bit transmit function can be enabled or disabled by software IICSTAT However the ACK pulse on the ninth clock of SCL is required to complete a one byte data transfer operation Clock to Output Data Output by Transmitter Data Output by Receiver SCL from Master Condition Clock Pulse for Acknowledgment Figure 16 5 Acknowledge on the IIC Bus ELECTRONICS 16 5 IIC BUS INTERFACE S3C44BOX RISC MICROPROCESSOR READ WRITE OPERATION In the transmitter mode after the data is transferred the IIC bus interface will wait until IICDS IIC bus Data Shift Register is written by a new data Until the new data is written the SCL line will be held low After the new data is written to IICDS register the SCL line will be released The S3C44BOX should hold the interrupt to identify the completion of current data transfer After the CPU receives the interrupt request it should write a new data into IICDS
209. fied by Rs Its possible values are as follows For Signed INSTRUCTIONS SMULL SMLAL e 1 bits 31 8 of the multiplier operand are all zero or all one e 1 bits 31 16 of the multiplier operand are all zero or all one If bits 31 24 of the multiplier operand are all zero or all one e other cases For Unsigned Instructions UMULL UMLAL e If bits 31 8 of the multiplier operand are all zero 1 bits 31 16 of the multiplier operand are all zero e 1 bits 31 24 of the multiplier operand are all zero e other cases 5 and are defined as sequential S cycle and internal respectively 3 26 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLER SYNTAX Table 3 5 Assembler Syntax Descriptions 1 Bespio UMULL cond S RdLo RaHi Rm Rs Unsigned Multiply Long 32 x 32 64 UMLAL cond S RdLo RdHi Rm Rs Unsigned Multiply amp Accumulate Long 32 x 32 64 64 SMULL cond S RdLo RdHi Rm Rs Signed Multiply Long 32 x 32 64 SMLAL cond S RdLo RdHi Rm Rs Signed Multiply amp Accumulate Long 32 x 32 64 64 where cond Two character condition mnemonic See Table 3 2 S Set condition codes if S present RdLo Rm Rs Expressions evaluating to a register number other than R15 EXAMPLES UMULL R1 R4 R2 R3 UMLALS R1 R5 R2 R3 R4 R1 R2 R3 R5 R1 R2 R3 R5 R1 also setting condition codes ELECTRONICS 3 27 ARM INST
210. flag is set to 1 if transmit FIFO is not empty If transmit FIFO is empty FIFO ready flag is set to 0 When receive FIFO is not full the FIFO ready flag for receive FIFO is set to 1 it indicates that FIFO is ready to receive data If receive FIFO is full FIFO ready flag is set to 0 These flags can determine the time that CPU is to write or read FIFOs Serial data can be transmitted or received while CPU is accessing transmit and receive FIFOs in this way 17 2 ELECTRONICS 53 44 RISC MICROPROCESSOR IIS BUS INTERFACE DMA transfer In this mode transmit or receive FIFO access is made by the DMA controller DMA service request in transmit or receive mode is made by the FIFO ready flag automatically TRANSMIT AND RECEIVE MODE In this mode IIS bus interface can transmit and receive data simultaneously Because one DMA source is assigned normal FIFO write is done in the transmit channel and DMA receive FIFO read is done in the receive channel and vice versa AUDIO SERIAL INTERFACE FORMAT IIS BUS FORMAT The IIS bus has four lines serial data input IISDI serial data output IISDO left right channel select IISLRCK and serial bit clock IISCLK the device generating IISLRCK and IISCLK is the master Serial data is transmitted in 2 s complement with the MSB first The MSB is transmitted first because the transmitter and receiver may have different word lengths It is not necessary for the transmitter to know how many bi
211. flg lt gt Where this is used the assembler will attempt to generate shifted immediate 8 bit field to match the expression If this is impossible it will give an error EXAMPLES In User mode the instructions behave as follows MSR CPSR_all Rm CPSR 81 28 lt Rm 31 28 MSR CPSR flg Rm CPSR 81 28 lt Rm 31 28 MSR CPSR_flg 0xA0000000 CPSR 81 28 lt set clear Z V MRS Rd CPSR Rd 81 0 lt CPSR 81 0 In privileged modes the instructions behave as follows MSR CPSR all Rm CPSR 31 0 lt Rm 31 0 MSR CPSR flg Rm CPSR 31 28 lt Rm 81 28 MSR CPSR flg 40x50000000 CPSR 31 28 lt 0x5 set Z V clear N C MSR SPSR all Rm SPSR mode 31 0 Rm 31 0 MSR SPSR flg Rm SPSR 31 28 lt Rm 31 28 MSR SPSR flg 0xC0000000 SPSR mode 31 28 lt OxC set N Z clear MRS SPSR Rd 81 0 lt SPSR_ lt mode gt 31 0 ELECTRONICS 3 21 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR MULTIPLY AND MULTIPLY ACCUMULATE MUL MLA The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 12 The multiply and multiply accumulate instructions use an 8 bit Booth s algorithm to perform integer multiplication 28 27 22 21 20 19 16 15 12 11 86 15 12 11 8 3 0 Operand Registers
212. ft field in the instruction This field indicates the type of shift to be performed logical left or right arithmetic right or rotate right The amount by which the register should be shifted may be contained in an immediate field in the instruction or in the bottom byte of another register other than R15 The encoding for the different shift types is shown in Figure 3 5 11 T I 6 5 Shift type 6 5 Shift type 00 logical left 01 logical right 00 logical left 01 logical right 10 arithmetic right 11 rotate right 10 arithmetic right 11 rotate right 11 7 Shift amount 11 8 Shift register 5 bit unsigned integer Shift amount specified in bottom byte of Rs Figure 3 5 ARM Shift Operations Instruction specified shift amount When the shift amount is specified in the instruction it is contained in a 5 bit field which may take any value from 0 to 31 A logical shift left 151 takes the contents of Rm and moves each bit by the specified amount to a more significant position The least significant bits of the result are filled with zeros and the high bits of Rm which do not map into the result are discarded except that the least significant discarded bit becomes the shifter carry output which may be latched into the C bit of the CPSR when the ALU operation is in the logical class see above For example the effect of LSL 5 is shown in Figure 3 6 Contents of Rm Value of Operand 2 00000 Figure 3 6 Logica
213. g Feature 9 4 ELECTRONICS 53 44 RISC MICROPROCESSOR PWM TIMER TIMER INITIALIZATION USING MANUAL UPDATE BIT AND INVERTER BIT Because an auto reload operation of the timer occurs when the down counter reaches to 0 a starting value of the is not defined at first In this case the starting value has to be loaded by the manual update bit The sequence of starting a timer is as follows 1 Write the initial value into TONTBn and TCMPBn 2 Set the manual update bit of the corresponding timer It is recommended to configure the inverter on off bit 3 Set the start bit of the corresponding timer to start the timer At the same time clear the manual update bit Also if the timer is stopped by force the TCNTn retains the counter value and is not reloaded from TCNTBn If new value has to be set manual update has to be done NOTE Whenever TOUT inverter on off bit is changed the TOUTn logic value will be changed whether or not the timer runs Therefore it is desirable that the inverter on off bit is configured with the manual update bit ELECTRENICS 9 5 PWM TIMER 53 44 RISC MICROPROCESSOR EXAMPLE OF A TIMER OPERATION __ 4th 501 110 14014020 60 Figure 9 4 Example of a Timer Operation The result of the following procedure is shown in Figure 9 4 1 Enable the auto reload feature Set the TCNTBn as 160 50 110 and the TCMPBn as 110 Set the manual update bit and configure the inverter b
214. g address 0 15 from the resulting address into Rd and set bits 16 31 to zero LDRH Rd Rb LDRH Rd Rb Add 1 to base address in Rb Load bits NOTE is a full 6 bit address but must be halfword aligned ie with bit 0 set to 0 since the assembler places gt gt 1 in the 5 field ELECTRONICS 3 87 ARM INSTRUCTION SET INSTRUCTION CYCLE TIMES 53 44 RISC MICROPROCESSOR All instructions in this format have an equivalent ARM instruction as shown in Table 3 17 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES STRH 86 R1 56 LDRH R4 R7 4 3 88 Store the lower 16 bits of R4 at the address formed by adding 56 R1 Note that the THUMB opcode will contain 28 as the Offset5 value Load into R4 the halfword found at the address formed by adding 4 to R7 Note that the THUMB opcode will contain 2 as the Offset5 value ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET FORMAT 11 SP RELATIVE LOAD STORE 15 14 13 7 0 1 12 11 10 8 7 0 Immediate Value 10 8 Destination Register 11 Load Store Bit 0 Store to memory 1 Load from memory Figure 3 40 Format 11 OPERATION The instructions in this group perform an SP relative load or store The THUMB assembler syntax is shown in the following table Table 3 18 SP Relative
215. ge width the number of half words This value defines the width of the view port in the frame NOTE The values of PAGEWIDTH and OFFSIZE must be changed when ENVID bit is 0 Example 1 LCD panel 320 240 16gray single scan frame start address 0xc500000 offset dot number 2048 dots 512 half words LINEVAL 240 1 Oxef PAGEWIDTH 320 4 16 0x50 OFFSIZE 512 0x200 LCDBANK 0xc500000 gt gt 22 0x31 LCDBASEU 0x100000 gt gt 1 0x80000 LCDBASEL 0 80000 0x50 0x200 Oxef 1 Oxa2b00 Example 2 LCD panel 320 240 16gray dual scan frame start address 0xc500000 offset dot number 2048 dots 512 half words LINEVAL 120 1 0x77 PAGEWIDTH 320 4 16 0x50 OFFSIZE 512 0x200 LCDBANK 0xc500000 gt gt 22 0x31 LCDBASEU 0x100000 gt gt 1 0x80000 LCDBASEL 0 80000 0x50 0x200 0x77 1 0x91580 Example 3 LCD panel 320 240 color single scan frame start address 0xc500000 offset dot number 1024 dots 512 half words LINEVAL 240 1 Oxef PAGEWIDTH 320 8 16 0 OFFSIZE 512 0x200 LCDBANK 0xc500000 gt gt 22 0x31 LCDBASEU 0x100000 gt gt 1 0x80000 LCDBASEL 0x80000 0 0x200 Oxef 1 7600 12 20 ELECTRONICS 53 44 RISC MICROPROCESSOR LCD CONTROLLER RED Lookup Table Register REDLUT 0x01F00014 Red lookup table register 0x00000000 REDVAL 31 0 These bits define which of the 16 shade
216. he 4 bits of data in the 8 parallel data lines are shifted to the upper half and 4 bits of data is shifted to the lower half as shown in figure 12 4 The end of frame is reached when each half of the display has been shifted and transferred The 8 pins VD 7 0 for the LCD output from the LCD controller can be directly connected to the LCD driver 4 bit single scan display type A 4 bit single scan display uses 4 parallel data lines to shift data to successive single horizontal lines of the display at a time until the entire frame has been shifted and transferred The 4 pins VD 3 0 for the LCD output from the LCD controller can be directly connected to the LCD driver and the 4 pins VD 7 4 for the LCD output are not used 8 bit single scan display type An 8 bit single scan display uses 8 parallel data lines to shift data to successive single horizontal lines of the display at a time until the entire frame has been shifted and transferred The 8 pins VD 7 0 for the LCD output from the LCD controller can be directly connected to the LCD driver Color displays Color displays require 3 bits Red Green Blue of image data per pixel resulting in a horizontal shift register of length 3 times the number of pixels per horizontal line This RGB is shifted to the LCD driver as consecutive bits via the parallel data lines Figure 12 5 shows the RGB and order of the pixels in the parallel data lines for the 3 types of color displays ELECTRONICS 12
217. he value of bit 31 of Rm ELECTRONICS 3 13 ARM INSTRUCTION SET S3C44BOX RISC MICROPROCESSOR Rotate right ROR operations reuse the bits which overshoot in a logical shift right operation by reintroducing them at the high end of the result in place of the zeros used to fill the high end in logical right operations For example ROR 5 is shown in Figure 3 9 31 5 4 0 Contents of Rm carry out Value of Operand 2 Figure 3 9 Rotate Right The form of the shift field which might be expected to give ROR 0 is used to encode a special function of the barrel shifter rotate right extended RRX This is a rotate right by one bit position of the 33 bit quantity formed by appending the CPSR C flag to the most significant end of the contents of Rm as shown in Figure 3 10 Contents of Rm in l Value of Operand 2 Figure 3 10 Rotate Right Extended 3 14 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET Register specified shift amount Only the least significant byte of the contents of Rs is used to determine the shift amount Rs can be any general register other than R15 If this byte is zero the unchanged contents of Rm will be used as the second operand and the old value of the CPSR C flag will be passed on as the shifter carry output If the byte has a value between 1 and 31 the shifted result will exactly match that of an instruction specified shift with the same value and shift operation If the va
218. here are four sets of instructions in this group The first three allow ADD CMP and MOV operations to be performed between Lo and Hi registers or a pair of Hi registers The fourth BX allows a Branch to be performed which may also be used to switch processor state The THUMB assembler syntax is shown in Table 3 12 NOTE In this group only CMP Op 01 sets the CPSR condition codes The action of H1 0 H2 0 for Op 00 ADD Op 01 CMP and Op 10 MOV is undefined and should not be used Table 3 12 Summary of Format 5 Instructions ELE m THUMB assembler ARM equivalent ADD Rd Hs ADD Rd Rd Hs EM C E a register in the range 8 15 to a register in the range 0 7 ADD Hd Rs ADD Hd Hd Rs Add a register in the range 0 7 to a register in the range 8 15 1 1 ADD Hd Hd Hs Add two registers in the range 8 15 01 1 CMP Rd Hs CMP Rd Hs Compare a register in the range 0 7 with a register in the range 8 15 Set the condition code flags on the result 01 1 CMP Hd Rs CMP Hd Rs Compare a register in the range 8 15 with a register in the range 0 7 Set the condition code flags on the result 3 76 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET Table 3 12 Summary of Format 5 Instructions Continued THUMB assembler equivalent Action CMP Hd Hs CMP Hd Hs Compare two registers in the range 8 15 Set the condition code flags on the result MOV Rd Hs MOV Rd Hs
219. hip functions that are described in this document are as follows e 2 5V Static ARM7TDMI CPU core with 8KB cache SAMBA II bus architecture up to 66 2 e External memory controller FP EDO SDRAM Control Chip Select logic LCD controller up to 256 color DSTN with 1 ch LCD dedicated DMA e 2 general DMAs 2 ch peripheral DMAs with external request pins e 2 UART with handshake IrDA1 0 16 byte FIFO 1 ch SIO 1 multi master IIC BUS controller e 1 IIS BUS controller e 5 ch PWM timers amp 1 ch internal timer Watch Dog Timer e 71 general purpose ports 8 ch external interrupt source e Power control Normal Slow Idle and Stop mode e 8 10 bit ADC e RTC with calendar function e On chip clock generator with PLL 1 1 ELECTRONICS PRODUCT OVERVIEW FEATURES Architecture Integrated system for hand held devices and general embedded applications e 16 32 RISC architecture and powerful instruction set with ARM7TDMI CPU core e Thumb de compressor maximizes code density while maintaining performance e On chip ICEbreaker debug support with JTAG based debugging solution e 32x8 bit hardware multiplier bus architecture to implement Low Power SAMBA II SAMSUNG s ARM CPU embedded Micro controller Bus Architecture System Manager e Little Big endian support Address space 32Mbytes per each bank Total 256Mbyte e Supports programma
220. i W A D converter data register 0x01D4000A Bi HW ADCDAT 9 0 A D converter output data value NOTES 1 The ADCDAT register can be accessed by halfword and word unit using STRH STR and LDRH LDR instructions or short X int int type pointer in Little Big endian mode 2 L HW W Access by halfword word unit when the endian mode is Little Bi HW W Access by halfword word unit when the endian mode is Big 13 6 ELECTRENICE 53 44 RISC MICROPROCESSOR REAL TIME CLOCK RTC REAL TIME CLOCK OVERVIEW The RTC Real Time Clock unit can be operated by the backup battery while the system power is off The RTC can transmit 8 bit data to CPU as BCD Binary Coded Decimal values using the STRB LDRB ARM operation The data include second minute hour date day month and year The RTC unit works with an external 32 768 KHz crystal and also can perform the alarm function FEATURES BCD number second minute hour date day month year Leap year generator Alarm function alarm interrupt or wake up from power down mode Year 2000 problem is removed Independent power pin VDDRTC Supports millisecond tick time interrupt for RTOS kernel time tick Round reset function ELECTRONICS 14 1 REAL TIME CLOCK 53 44 RISC MICROPROCESSOR REAL TIME CLOCK OPERATION TIME TICK Time Tick Generator Leap Year Generator HOUR DATE DAY MON Control Register Alarm Generator RTC
221. igher priority and could delay entry into the IRQ handling routine for an arbitrary length of time The minimum latency for FIQ or IRQ consists of the shortest time the request can take through the synchroniser Tsyncmin plus Tfiq This is 4 processor cycles RESET When the nRESET signal goes LOW ARM7TDMI abandons the executing instruction and then continues to fetch instructions from incrementing word addresses When nRESET goes HIGH again ARM7TDMI 1 Overwrites R14 svc and SPSR svc by copying the current values of the PC and CPSR into them The value of the saved PC and SPSR is not defined Forces M 4 0 to 10011 Supervisor mode sets the and F bits in the CPSR and clears the CPSR s T bit Forces the PC to fetch the next instruction from address 0 00 Execution resumes in ARM state ELECTRONICS 2 15 PROGRAMMER S MODEL NOTES 53 44 RISC MICROPROCESSOR ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET INSTRUCTION SET INSTRUCTION SET SUMMAY This chapter describes the ARM instruction set and the THUMB instruction set in the ARM7TDMI core FORMAT SUMMARY The ARM instruction set formats are shown below 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1211109876543210 Opcode S Rn Operand2 Data Processing PSR Transfer 88 Rn ms Rm 000011 Roto Long
222. ight 0x00000 value For example if DST is word ICNT must be 4n If 1 byte is transferred the ICNT will be decreased by 1 If 1 half word is transferred the ICNT will be decreased by 2 If 1 word is transferred the ICNT will be decreased by 4 ELECTRONICS 7 19 DMA 53 44 RISC MICROPROCESSOR 1 INITIAL CURRENT COUNT REGISTERS BDICNT1 BDCCNT1 QSC 31 30 DMA request source selection 00 N A 01 Timer 10 UART1 11 510 27 26 01 unit transfer mode 25 24 00 on the fly mode is not supported in BDMAn INTS 23 22 Interrupt mode set 00 Polling mode 01 10 Int whenever transferred 11 Int whenever terminated count 21 Auto reload and Auto start after DMA count are 0 0 Disable 1 Enable Even after DMA count is 0 the DMA H W enable bit EN bit is still 1 But DMA will start to operate only if the start command or DMA request is activated EN 20 DMA H W enable disable 0 Disable DMA 1 Enable DMA If the QDS bit is 000 DMA request can be serviced Also if the S W command is started the DMA operation will occur If the EN bit is 0 DMA will not operate even though S W command is started If the S W command is canceled the DMA operation will be canceled and EN bit will be cleared to 0 At the terminal count the EN bit will be cleared to 0 NOTE Do not set the EN bit and the other bits of BDICNT register at the same time User have to set EN bit after setting the other bi
223. ignal Timing VDDP 3 3V VDDI 2 5V Ta 25 C PLCAP 70pf SCL clock frequency fec std 100 KHz fast 400 SCL high level pulse width tecLHIGH std 4 0 uS fast 0 6 SCL low level pulse width tecLLOW std 4 7 us fast 1 3 fast 1 3 START hold time tsTARTS std 4 0 us fast 0 6 SDA hold time 510 0 std fast us fast 0 0 9 SDA setup time tspas std 250 ns fast 100 STOP setup time Std 4 0 us fast 0 6 NOTE Std means Standard Mode and fast means Fast Mode ELECTRENICS 19 43 ELECTRICAL DATA 53 44 RISC MICROPROCESSOR NOTES 19 44 ELECTRENICS MECHANICAL DATA 53 44 RISC MICROPROCESSOR MECHANICAL DATA 0 PACKAGE DIMENSIONS 2 3 H 0 073 0 127 0 037 0 05 0 15 1 40 0 05 1 60 24 00 0 10 io 160 LQFP 2424 NOTE Dimensions are in millimeters 02 0 00 92 Figure 20 1 160 LQFP 2424 Package Dimensions 20 1 ELECTRONICS MECHANICAL DATA 3C44B0X RISC MICROPROCESSOR DEEP BALL PAD INDICATOR 910 x 001010 Figure 20 2 160 FBGA 12 0x12 0 Package Dimensions 1 20 2 ELECTRONICS MECHANICAL DATA KOL TWIS MHA 4 0000 0000 0000 0000 0000 0000 00000000000000 9 00000000000000 00000000000000 4 0000000000096 x 1 20 3 53 44 RISC MICROP
224. ined if necessary by setting the offset to zero Therefore post indexed data transfers always write back the modified base The Write back bit should not be set high W 1 when post indexed addressing is selected ELECTRONICS 3 35 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR HALFWORD LOAD AND STORES Setting 5 0 and H 1 may be used to transfer unsigned Half words between an ARM7TDMI register and memory The action of LDRH instructions is influenced by the BIGEND control signal The two possible configurations are described in the section below SIGNED BYTE AND HALFWORD LOADS The S bit controls the loading of sign extended data When S 1 the H bit selects between Bytes H 0 and Half words H 1 The L bit should not be set low Store when Signed 5 1 operations have been selected The LDRSB instruction loads the selected Byte into bits 7 to O of the destination register and bits 31 to 8 of the destination register are set to the value of bit 7 the sign bit The LDRSH instruction loads the selected Half word into bits 15 to 0 of the destination register and bits 31 to 16 of the destination register are set to the value of bit 15 the sign bit The action of the LDRSB and LDRSH instructions is influenced by the BIGEND control signal The two possible configurations are described in the following section ENDIANNESS AND BYTE HALFWORD SELECTION Little Endian Configuration A signed byte load LDRSB expects d
225. ing 1 2 or 3 Thumb instructions alongside the ARM equivalents For other constants it is generally better to use the built in MUL instruction rather than using a sequence of 4 or more instructions Thumb ARM 1 Multiplication by 24n 1 2 4 8 LSL Ra Rb LSL n MOV Ra Rb LSL n 2 Multiplication by 2 1 3 5 9 17 LSL Rt Rb n ADD Ra Rb Rb LSL n ADD Ra Rt Rb 3 Multiplication by 2 n 1 3 7 15 LSL Rt Rb n RSB Rb Rb LSL zin SUB Ra Rt Rb 4 Multiplication by 27 2 4 8 LSL Ra Rb n MOV Ra Rb LSL n MVN Ra Ra RSB Ra 0 5 Multiplication by 2 n 1 3 7 15 LSL Rt Rb n SUB Ra Rb Rb LSL n SUB Ra Rb Rt Multiplication by any C 2 1 2 n 1 2 n or 2 1 2 n Effectively this is any of the multiplications in 2 to 5 followed by a final shift This allows the following additional constants to be multiplied 6 10 12 14 18 20 24 28 30 34 36 40 48 56 60 62 2 5 2 5 LSL Ra Ra n MOV Ra Ra LSL zin ELECTRONICS 3 103 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR GENERAL PURPOSE SIGNED DIVIDE This example shows a general purpose signed divide and remainder routine in both Thumb and ARM code Thumb code signed_divide Signed divide of R1 by RO returns quotient in RO remainder in R1 Get abs value of RO into R3 ASR R2 RO 31 Get 0 or 1 in R2 depending on sign of RO EOR RO R2
226. initiated with a High to Low transition of the SDA line while the clock signal of SCL is High When the interface state is changed to the master mode a data transfer on the SDA line can be initiated and SCL signal generated A Start condition can transfer a one byte serial data over the SDA line and a stop condition can terminate the data transfer A stop condition is a Low to High transition of the SDA line while SCL is High Start and Stop conditions are always generated by the master The is busy when a Start condition is generated A few clocks after a Stop condition the IIC bus will be free again When a master initiates a Start condition it should send a slave address to notify the slave device The one byte of address field consist of a 7 bit address and a 1 bit transfer direction indicator that is write or read If bit 8 is 0 it indicates a write operation transmit operation if bit 8 is 1 it indicates a request for data read receive operation The master will finish the transfer operation by transmitting a Stop condition If the master wants to continue the data transmission to the bus it should generate another Start condition as well as a slave address In this way the read write operation can be performed in various formats Condition Condition Figure 16 2 Start and Stop Condition ELECTRONICS 16 3 IIC BUS INTERFACE 53 44 RISC MICROPROCESSOR DATA TRANSFER FORMAT Every byte placed on the S
227. ission Furthermore it enables the receiver to store the previous word and clear the input for the next word MSB LEFT JUSTIFIED MSB left justified bus has the same lines as the IIS format It is only different with the IIS bus that transmitter always sends the MSB of the next word when the IISLRCK change ELECTRENICE 17 3 IIS BUS INTERFACE 53 44 RISC MICROPROCESSOR MSB V 2nd V MSBV ist Bt MSB JUSTIFIED FORMAT N 8 or 16 Figure 17 2 IIS Bus and MSB Left justified Data Interface Formats SAMPLING FREQUENCY AND MASTER CLOCK Master clock frequency MCLK can be selected by sampling frequency as shown in Table 17 1 Because MCLK is made by IIS prescaler the prescaler value and MCLK type 256 or 384fs should be determined properly Serial bit clock frequency type 16 32 48fs can be selected by the serial bit per channel and MCLK as shown in Table 17 2 Table 17 1 CODEC clock CODECLK 256 or 384fs 8 000 11 025 16 000 22 050 32 000 44 100 48 000 64 000 88 200 96 000 fs KHz KHz KHz KHz KHz KHz KHz KHz KHz KHz 256fs MHz 384fs Table 17 2 Usable serial bit clock frequency IISCLK 16 or 32 or 48fs Serial clock frequency IISCLK CODECLK 256fs 16fs 32fs 32fs CODECLK 384fs 16fs 32fs 48fs 32fs 48fs 17 4 ELECTRONICS 53 44 RISC MICROPROCESSOR IIS BUS INTERFACE IIS BUS INTERFACE SPECIAL REGISTERS IIS CONTROL REGISTER
228. ister 0x00000000 observation register Timer 0 15 0 Setting count observation value for Timer 0 0x00000000 ELECTRENICS 9 15 PWM TIMER 53 44 RISC MICROPROCESSOR TIMER 1 COUNT BUFFER REGISTER amp COMPARE BUFFER REGISTER TCNTB1 TCMPB1 TCNTB1 0x01D50018 Timer 1 count buffer register 0x00000000 TCMPB1 0x01D5001C Timer 1 campare buffer register 0x00000000 Timer 1 compare Setting compare buffer value for Timer 1 0x00000000 buffer register NOTE This value must be smaller than TCNTB1 Timer 1 count buffer 15 0 Setting count buffer value for Timer 1 0x00000000 register TIMER 1 COUNT OBSERVATION REGISTER TCNTO1 TCNTO1 0x01D50020 oR Timer 1 count observation register 0x00000000 Timer 1 15 0 Setting count observation value for Timer 1 0x00000000 observation register 9 16 ELECTRONICS 53 44 RISC MICROPROCESSOR PWM TIMER TIMER 2 COUNT BUFFER REGISTER amp COMPARE BUFFER REGISTER TCNTB2 TCMPB2 TCNTB2 0 01050024 Timer 2 count buffer register 0x00000000 TCMPB2 0x01D50028 Timer 2 campare buffer register 0x00000000 Timer 2 compare Setting compare buffer value for Timer 2 0x00000000 buffer register NOTE This value must be smaller than 2 Timer 2 count buffer 15 0 Setting count buffer value for Timer 2 0x00000000 register TIMER 2 COUNT OBSERVATION REGISTER TCNTO2 TCNTO2 0x01D5002C oR Timer 2 count observation register 0x00000000 Timer 2 1
229. it on off The manual update bit sets TCNTn and TCMPn to the values of TCNTBn and TCMPBn respectively And then set TCNTBn and TCMPBn as 80 40 40 and 40 respectively to determine the next reload value 2 Set the start bit provided that manual update is 0 and inverter is off and auto reload is on The timer starts counting down after latency time within the timer resolution When TCNTn has the same value with TCMPn the logic level of TOUTn is changed from low to high When TCNTn reaches 0 the interrupt request is generated and TCNTBn value is loaded into a temporary register At the next timer tick TCNTn is reloaded with the temporary register value TCNTBn 5 Inthe ISR interrupt service routine the TCNTBn and TCMPBn set as 80 20 60 and 60 respectively which is used for the next duration 6 When TCNTn has the same value as TCMPn the logic level of TOUTn is changed from low to high 7 When reaches 0 TCNTn is reloaded automatically with TCNTBn At the same time the interrupt request is generated 8 In the ISR interrupt service routine auto reload and interrupt request are disabled to stop the timer When the value of TCNTn is same as TCMPn the logic level of TOUTn is changed from low to high 10 Even when TCNTn reaches to 0 TCNTn is not any more reloaded and the timer is stopped because auto reload has been disabled 11 No interrupt request is generated 9 6 ELECTRENICE 53 44 RISC
230. ithout CPU intervention e 2 channel Bridge DMA peripheral DMA controller e Support IO to memory memory to IO IO to IO with the Bridge DMA which has 6 type s DMA requestor Software 4 internal function blocks UART SIO Timer IIS and External pins e Programmable priority order between DMAs fixed or round robin mode e Burst transfer mode to enhance the transfer rate on the EDODRAM and SDRAM e Supports fly by mode on the memory to external device and external device to memory transfer mode A D Converter e 8 multiplexed ADC e Max 100KSPS 10 bit LCD Controller e Supports color monochrome gray LCD panel Supports single scan and dual scan displays e Supports virtual screen function e System memory is used as display memory e Dedicated DMA for fetching image data from system memory e Programmable screen size Gray level 16 gray levels e 256 Color levels ELECTRONICS PRODUCT OVERVIEW FEATURES Continued Watchdog Timer e 16 bit Watchdog Timer e Interrupt request or system reset at time out IIC BUS Interface e 1 Multi Master IIC Bus with interrupt based operation e Serial 8 bit oriented bi directional data transfers can be made at up to 100 Kbit s in the standard mode or up to 400 Kbit s in the fast mode 115 805 Interface e 1 IIS bus for audio interface with DMA based operation e Serial 8 16bit per channel data transfers Supports MSB j
231. ity in the case where the base register is also in the transfer list and may have been overwritten before the abort occurred The data abort trap is taken when the load multiple has completed and the system software must undo any base modification and resolve the cause of the abort before restarting the instruction INSTRUCTION CYCLE TIMES Normal LDM instructions take nS 1N 11 and LDM PC takes 1 5 2N 11 incremental cycles where 5 and are defined as sequential S cycle non sequential N cycle and internal I cycle respectively STM instructions take n 1 S 2N incremental cycles to execute where nis the number of words transferred 3 44 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLER SYNTAX lt LDM STM gt cond lt FD ED FA EAIIA IB DA DB gt Rn lt Rlist gt where cond Two character condition mnemonic See Table 3 2 Rn An expression evaluating to a valid register number lt Rlist gt A list of registers and register ranges enclosed in e g RO R2 R7 R10 If present requests write back W 1 otherwise W 0 If present set S bit to load the CPSR along with the PC or force transfer of user bank when in privileged mode Addressing Mode Names There are different assembler mnemonics for each of the addressing modes depending on whether the instruction is being used to support stacks or for other purposes The equivalence between the names and the valu
232. k count reset 0 No reset 1 Reset CNTSEL 2 0 Merge BCD counters 1 Reserved Separate BCD counters CLKSEL 1 BCD clock select 0 XTAL 1 2 divided clock 1 Reserved XTAL clock only for test BCD count select RTC read write enable 0 Disable 1 Enable If RTC read write feature is enabled The STOP current will be consumed excessively To reduce STOP current this bit should be 0 while not accessing RTC Although this bit is 0 the RTC clock is still alive RTCEN NOTES 1 All RTC registers have to be accessed by byte unit using STRB and LDRB instructions or char type pointer 2 1 When the endian mode is little endian B When the endian mode is Big endian 14 4 53 44 RISC MICROPROCESSOR REAL TIME CLOCK RTC ALARM CONTROL REGISTER RTCALM RTCALM register determines the alarm enable and the alarm time Note that the RTCALM register generates the alarm signal through both ALMINT and PMWKUP in power down mode but only through ALMINT in the normal operation mode RTCALM 0x01D70050 L R W RTC alarm control Register 0x00 0x01D70053 B by byte Alarm global enable 0 Disable 1 Enable RTCALM ALMEN YEAREN Year alarm enable 0 Disable 1 Enable NER ERES MONREN 4 Month alarm enable 0 Disable 1 Enable DAYEN 3 Day alarm enable 0 Disable 1 Enable HOUREN 2 Hour alarm enable 0 Disable 1 Enable MINEN Minute alarm enable
233. l 13 memory control registers have to be written using the STMIA instruction 2 In STOP mode SL IDLE mode DRAM SDRAM has to enter the DRAM SDRAM self refresh mode 4 18 ELECTRONICS 53 44 RISC MICROPROCESSOR MEMORY CONTROLLER NOTES ELECTRONICS 4 19 S3C44B0X RISC MICROPROCESSOR CLOCK amp POWER MANAGEMENT CLOCK amp POWER MANAGEMENT OVERVIEW The Clock Generator 53 44 can generate the required clock signals for the CPU as well as peripherals The Clock Generator can be controlled to supply or disconnect the clock to each peripheral block by S W which will reduce the power As well as this kind of S W controllability S3C44BOX has various power management schemes to keep optimal power consumption for a given task The power management in S3C44BOX consists of five modes Normal mode Slow mode Idle mode Stop mode and SL Idle mode for LCD The Normal mode is used to supply clocks to CPU as well as all peripherals in S3C44BOX In this case the power consumption will be maximized when all peripherals are turned on The user can control the operation of peripherals by S W For example if a timer and DMA are not needed the user can disconnect the clock to the timer and DMA to reduce power The Slow mode is non PLL mode Unlike the Normal mode the Slow mode uses an external clock directly as master clock in 53044 without PLL In this case the power consumption depends on the frequency of the external clock only
234. l ADC error or an external S H circuit is used the higher frequency signal can be converted If the ADC channel is changed the channel setup time min 15us is needed So If the ADC channel is changed you must wait for 15us and then start AD conversion After the ADC exits the sleep mode the initial state is the sleep mode there is 10ms wait for the ADC reference voltage stabilization before the first AD conversion Our ADC has ADC start by read feature This feature can be used for DMA to move the ADC data to memory If you read the ADCDAT by polling method you must apply the work around for ADC data reading problem ELECTRONICS 53 44 RISC MICROPROCESSOR A D CONVERTER A D CONVERTER SPECIAL REGISTERS A D CONVERTER CONTROL REGISTER ADCCON ADCCON 0x01D40000 Li W Li HW A D Converter control Register Li B Bi W 0x01D40002 Bi HW 0x01D40003 Bi B ADCCON Bit Description Initial State FLAG 6 A D converter state flag Read Only 0 A D conversion in process 1 End of A D conversion If check this bit please refer to workaround in page13 3 SLEEP 5 System power down 1 0 Normal operation 1 Sleep mode INPUT 4 2 Clock source select SELECT 000 AINO 001 AINT 010 AIN2 011 100 101 5 110 111 7 READ START 1 A D conversion start by read 0 Disable start by read operation 1 Enable start by read operation ENABLE_START A D conversion start by enable
235. l Shift Left NOTE LSL 0 is a special case where the shifter carry out is the old value of the CPSR C flag The contents of Rm are used directly as the second operand A logical shift right LSR is similar but the contents of Rm are moved to less significant positions in the result LSR 5 has the effect shown in Figure 3 7 3 12 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET 31 5 4 0 Contents carry out 00000 Value of Operand 2 Figure 3 7 Logical Shift Right The form of the shift field which might be expected to correspond to LSR 0 is used to encode LSR 32 which has a zero result with bit 31 of Rm as the carry output Logical shift right zero is redundant as it is the same as logical shift left zero so the assembler will convert LSR 0 and ASR 0 and ROR 0 into LSL 0 and allow LSR 82 to be specified An arithmetic shift right ASR is similar to logical shift right except that the high bits are filled with bit 31 of Rm instead of zeros This preserves the sign in 2 s complement notation For example ASR 5 is shown in Figure 3 8 5 4 0 Contents of Rm carry out Value of Operand 2 Figure 3 8 Arithmetic Shift Right The form of the shift field which might be expected to give ASR 0 is used to encode ASR 32 Bit 31 of Rm is again used as the carry output and each bit of operand 2 is also equal to bit 31 of Rm The result is therefore all ones or all zeros according to t
236. lease refer to the sections listed in the right most column Table 3 7 THUMB Instruction Set Opcodes Operand Operand Codes Set eon 2 oz 5 E ADC ADD AND ASR de o LDR ____ tst DSB LDSH 3 66 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET Table 3 7 THUMB Instruction Set Opcodes Continued Lo Register Hi Register Condition pM Set Negate 00 5 PUSH Pushregister ROR RotateRight 580 Y _ lt lt lt lt STMA FP 7 0 STRO STRH __ swi Software interrupt SUB 17 lt lt lt lt NOTES 1 condition codes are unaffected by the format 5 12 and 13 versions of this instruction 2 The condition codes are unaffected by the format 5 version of this instruction ELECTRONICS 3 67 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR FORMAT 1 MOVE SHIFTED REGISTER 15 14 13 12 11 10 6 5 3 2 0 2 0 Destination Register 5 3 Source Register 10 6 Immediate Vale 12 11 Opcode 0 LSL 1 LSR 2 ASR Figure 3 30 Format 1 OPERATION These instructions move a shifted value between Lo registers The THU
237. line When this happens Low as the first bit of address generating master will get the mastership and High as the first bit of address generating master should withdraw the mastership If both masters generate Low as the first bit of address there should be an arbitration for second address bit again This arbitration will continue to the end of last address bit ABORT CONDITIONS If a slave receiver can not acknowledge the confirmation of the slave address it should hold the level of the SDA line High In this case the master should generate a Stop condition and to abort the transfer If a master receiver is involved in the aborted transfer it should signal the end of the slave transmit operation by canceling the generation of an ACK after the last data byte received from the slave The slave transmitter should then release the SDA to allow a master to generate a Stop condition CONFIGURING THE IIC BUS To control the frequency of the serial clock SCL the 4 bit prescaler value can be programmed in the IICCON register The interface address is stored in the IIC bus address register IICADD By default the interface address is an unknown value 16 6 ELECTRONICS 53 44 RISC MICROPROCESSOR IIC BUS INTERFACE FLOWCHARTS OF THE OPERATIONS IN EACH MODE The following steps must be executed before any IIC tx rx operations 1 Write own slave address on IICADD register if needed 2 Set IICCON Register
238. lled gray level display by FRC Frame Rate Control The actual example is shown in Table 12 2 To represent the 14 gray level in the table we should have a 6 7 duty cycle which mean that there are 6 times pixel on and one time pixel off The other cases for all gray levels are also shown in Table 12 2 In the STN LCD display we should be reminded of one item i e Flicker Noise due to the simultaneous pixel on and off on adjacent frames For example if all pixels on first frame are turned on and all pixels on next frame are turned off the Flicker Noise will be maximized To reduce the Flicker Noise on the screen the average probability of pixel on and off between frames should be as same as possible In order to realize this the Time based Dithering Algorithm which varies the pattern of adjacent pixels on every frame should be used This is explained in detail For the 16 gray level FRC should have the following relationship between gray level and FRC The 15 gray level should always have pixel on and the 14 gray level should have 6 times pixel on and one times pixel off and the 13 gray level should have 4 times pixel on and one times pixel off and the 0 gray level should always have pixel off as shown in Table 12 2 In Table 12 3 the DP1_2 corresponds to the 7 gray level because it has half the duty cycle from having 2 times pixel on and 2 times pixel off Also the DP4_7 corresponds to 8 gray level because it has 4 7 duty
239. lock diagram the VCO Voltage Controlled Oscillator to generate the output frequency proportional to input DC voltage the divider P to divide the input frequency Fin by p the divider M to divide the VCO output frequency by m which is input to PFD Phase Frequency Detector the divider S to divide the VCO output frequency by s which is Fpllo the output frequency from PLL block the phase difference detector charge pump and loop filter The output clock frequency Fpllo is related to the reference input clock frequency Fin by the following equation Fpllo m Fin p Z m M the value for divider M 8 P the value for divider P 2 The following sections describe the operation of the PLL that includes the phase difference detector charge pump VCO Voltage controlled oscillator and loop filter If the PLL is on Fpllo is same as Fout as shown in Figure 5 1 Phase Difference Detector PFD The PFD monitors the phase difference between the Fref the reference frequency as shown in Fig 5 2 and Fvco the output frequency from VCO and Divider M block and generates a control signal tracking signal when it detects a difference Charge Pump PUMP The charge pump converts the PFD control signal into a proportional charge in voltage across the external filter that drives the VCO Loop Filter The control signal that the PFD generates for the charge pump may generate large excursions ripples each time the Fvco output is comp
240. lock to CKOUT External clock to SCLK SCLK to CKOUT Crystal clock input frequency Crystal clock input cycle time External clock input frequency fext External clock input cycle time AL Mode reset hold time 3 0 Reset assert time after clock stabilization 4 MCLK Power on oscillation setting time 4096 MCLK STOP mode return oscillation setting time lop 4096 MCLK the interval before CPU runs after nRESET is trsTORUN 132 MCLK released ELECTRENICS 19 39 ELECTRICAL DATA 53 44 RISC MICROPROCESSOR Table 19 7 ROM SRAM Bus Timing Constants VDDP 3 3V VDDI 2 5V Ta 25 C PLCAP 70pf max min typ 30 ROM SRAM Chip select Delay ROM SRAM Output enable Delay ROM SRAM read Data Setup time ROM SRAM read Data Hold time ROM SRAM Byte Enable Delay ROM SRAM Write Byte Enable Delay ROM SRAM output Data Delay ROM SRAM external Wait Setup time ROM SRAM external Wait Hold time ROM SRAM Write enable Delay 19 40 ELECTRONICS 53 44 RISC MICROPROCESSOR ELECTRICAL DATA Table 19 8 Clock Timing Constants VDDP 3 3V VDDI 2 5V Ta 25 C PLCAP 70pf max min typ 30 Table 19 9 Memory Interface Timing Constants VDDP 3 3V VDDI 2 5V 25 C PLCAP 70pf max min typ 30 ELECTRONICS 19 41 ELECTRICAL DATA 53 44 RISC MICROPROCESSOR Table 19 10 External Bus Request Timing Constants VD
241. lue in the byte is 32 or more the result will be a logical extension of the shift described above LSL by 32 has result zero carry out equal to bit 0 of Rm LSL by more than 32 has result zero carry out zero LSR by 32 has result zero carry out equal to bit 31 of Rm LSR by more than 32 has result zero carry out zero ASR by 32 or more has result filled with and carry out equal to bit 31 of Rm ROR by 32 has result equal to Rm carry out equal to bit 31 of Rm NO a O P gt ROR by n where n is greater than 32 will give the same result and carry out as ROR by n 32 therefore repeatedly subtract 32 from n until the amount is in the range 1 to 32 and see above NOTE The zero in bit 7 of an instruction with a register controlled shift is compulsory a one in this bit will cause the instruction to be a multiply or undefined instruction ELECTRONICS 3 15 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR IMMEDIATE OPERAND ROTATES The immediate operand rotate field is a 4 bit unsigned integer which specifies a shift operation on the 8 bit immediate value This value is zero extended to 32 bits and then subject to a rotate right by twice the value in the rotate field This enables many common constants to be generated for example all powers of 2 WRITING TO R15 When Rad is a register other than R15 the condition code flags in the CPSR may be updated from the ALU flags as described above When Rad is R15 and the S flag in
242. lue should not be changed when moving the view port So using the malloc function the care should be taken LCDBASEU 20 0 These bits indicate A 21 1 of the start address of the upper 0x000000 address counter which is for the upper frame memory of dual scan LCD or the frame memory of single scan LCD NOTES 1 LCDBANK can t be changed while ENVID 1 2 If LCDBASEU LCDBASEL is changed during ENVID 1 the new value will be used next frame If you use serveral frame buffer for better display quality and if you write the previous frame memory just after changing LCDBASEU LCDBASEL the items drawn on the previous frame memory may be shown To avoid this undesirable phenomen you may have to check LINECNT 12 18 ELECTRONICS 53 44 RISC MICROPROCESSOR LCD CONTROLLER FRAME Buffer Start Address 2 Register LCDSADDR2 0 01 0000 Frame buffer start address 2 register 0x000000 BSWP 29 Byte swap control bit 1 Swap Enable 0 Swap Disable LCD DMA fetches the frame memory data by 4 word burst access In little endian mode and BSWP is 0 the frame memory data are displayed in the sequence 4n 3th 4n 2th 4n 1th 4n th data If BSWP is 1 the sequence will be 4n th 4n 1th 4n 2th 4n 3th If the CPU is little endian mode the frame buffer may be accessed by only byte access mode Because BSWP is 1 the byte accessed data will be shown correctly also in the little endian mode In the other case BSWP has to be 0 MVAL 28 21
243. m the base may be either a 12 bit unsigned binary immediate value in the instruction or a second register possibly shifted in some way The offset may be added to U 1 or subtracted from U 0 the base register Rn The offset modification may be performed either before pre indexed P 1 or after post indexed 0 the base is used as the transfer address The W bit gives optional auto increment and decrement addressing modes The modified base value may be written back into the base W 1 or the old base value may be kept W 0 In the case of post indexed addressing the write back bit is redundant and is always set to zero since the old base value can be retained by setting the offset to zero Therefore post indexed data transfers always write back the modified base The only use of the W bit in a post indexed data transfer is in privileged mode code where setting the W bit forces non privileged mode for the transfer allowing the operating system to generate a user address in a system where the memory management hardware makes suitable use of this hardware SHIFTED REGISTER OFFSET The 8 shift control bits are described in the data processing instructions section However the register specified shift amounts are not available in this instruction class See Figure 3 5 BYTES AND WORDS This instruction class may be used to transfer a byte B 1 or a word B 0 between an ARM7TDMI register and memory The action of LDR B and STR B ins
244. ments Image data should be transferred from the memory to the LCD driver using the VD 7 0 signal VCLK signal is used to clock the data into the LCD driver s shift register After each horizontal line of data has been shifted into the LCD driver s shift register the VLINE signal is asserted to display the line on the panel The VM signal provides an AC signal for the display It is used by the LCD to alternate the polarity of the row and column voltages used to turn the pixels on and off because the LCD plasma tends to deteriorate whenever subjected to a DC voltage It can be configured to toggle on every frame or to toggle every programmable number of VLINE signals Figure 12 3 shows the timing requirements for the LCD driver interface ELECTRINICS 12 9 LCD CONTROLLER 53 44 RISC MICROPROCESSOR Full Frame Timing MMODE 0 LINECNT VCLK 7 0 Figure 12 3 8 bit Single Scan Display Type LCD Timing 12 10 ELECTRONICS 53 44 RISC MICROPROCESSOR LCD CONTROLLER Display Types The LCD controller supports 3 types of LCD drivers 4 bit dual scan 4 bit single scan and 8 bit single scan display mode Figure 12 4 shows these 3 different display types for monochrome displays and figure 12 5 shows these 3 different display types for color displays 4 bit dual scan display type A 4 bit dual scan display uses 8 parallel data lines to shift data to both the upper and lower halves of the display at the same time T
245. n Big Endian format the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte Byte 0 of the memory system is therefore connected to data lines 31 through 24 Higher Address Word Address Lower Address Most significant byte is at lowest address Word is addressed by byte address of most significant byte Figure 2 1 Big Endian Addresses of Bytes within Words LITTLE ENDIAN FORMAT In Little Endian format the lowest numbered byte in a word is considered the word s least significant byte and the highest numbered byte the most significant Byte 0 of the memory system is therefore connected to data lines 7 through O Higher Address Word Address Lower Address Least significant byte is at lowest address Word is addressed by byte address of least significant byte Figure 2 2 Little Endian Addresses of Bytes whthin Words INSTRUCTION LENGTH Instructions are either 32 bits long in ARM state or 16 bits long in THUMB state Data Types ARMTTDMI supports byte 8 bit halfword 16 bit and word 32 bit data types Words must be aligned to four byte boundaries and half words to two byte boundaries 2 2 ELECTRONICS 53 44 RISC MICROPROCESSOR PROGRAMMER S MODEL OPERATING MODES supports seven modes of operation e User usr The normal ARM program execution state Designed to support a data transfer o
246. n a byte is as follows Bit 7 5 Bit 4 2 Oe 12 14 ELECTRONICS 53 44 RISC MICROPROCESSOR LCD CONTROLLER VIRTUAL DISPLAY The 53 44 supports hardware horizontal or vertical scrolling If the screen is scrolled the fields of LCDBASEU and LCDBASEL LCDSADDR 1 2 registers need to be changed refer to Fig 12 6 but not the values of PAGEWIDTH and OFFSIZE The size of video buffer in which the image is stored should be larger than LCD panel screen size PAGEWIDTH is the data of line 1 of virtual screen is of line 2 of virtual screen 4 of line 2 of virtual screen is the data of line 3 of virtual screen 4 of line 3 of virtual screen isthe of line 4 of virtual 4 of line 4 of virtual screen LINEVAL 1 s the of line 5 of virtual scXeen 4 of line 5 of virtual screen is the qata of line 6 of virtual scr amp en 4 of line 6 of virtual screen is of line 7 of virtual scre amp n screen is the data of line 8 of virtual This is the data of line 8 of virtual screen View Port The same size of LCD panel is the data of line 9 of virtual screen This is the data of line 9 of virtual screen s the data of line 10 of virtual screen This is the data of line 10 of virtual screen is the data of line 11 of virtual screen This is the data of line 11 of virtual screen LCDBASEU Before Scrolling
247. n immediate value 11 8 7 0 mm 7 0 Unsigned 8 bit immediate value 11 8 Shift applied to Imm 31 28 Condition Field Figure 3 11 PSR Transfer ELECTRONICS 3 19 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR RESERVED BITS Only twelve bits of the PSR are defined in ARM7TDMI N Z C V I F T M 4 0 the remaining bits are reserved for use in future versions of the processor Refer to Figure 2 6 for a full description of the PSR bits To ensure the maximum compatibility between ARM7TDMI programs and future processors the following rules should be observed reserved bits should be preserved when changing the value in a PSR Programs should not rely on specific values from the reserved bits when checking the PSR status since they may read as one or zero in future processors A read modify write strategy should therefore be used when altering the control bits of any PSR register this involves transferring the appropriate PSR register to a general register using the MRS instruction changing only the relevant bits and then transferring the modified value back to the PSR register using the MSR instruction EXAMPLES The following sequence performs a mode change MRS RO CPSR Take of the CPSR BIC RO RO 0x1F Clear the mode bits ORR RO RO Znew mode Select new mode MSR CPSR RO Write back the modified CPSR When the aim is simply to change the condition code flags
248. nal after the present transmission word transmits perfectly After the break signal transmit continously transmit data into the Tx FIFO Tx holding register in the case of Non FIFO mode Data Reception Like the transmission the data frame for reception is also programmable It consists of a start bit 5 to 8 data bits an optional parity bit and 1 to 2 stop bits in the line control register UCONn The receiver can detect overrun error parity error frame error and break condition each of which can set an error flag The overrun error indicates that new data has overwritten the old data before the old data has been read The parity error indicates that the receiver has detected an unexpected parity condition The frame error indicates that the received data does not have a valid stop bit The break condition indicates that the RxDn input is held in the logic 0 state for a duration longer than one frame transmission time Receive time out condition occurs when it does not receive data during the 3 word time and the Rx FIFO is not empty in the FIFO mode Auto Flow Control AFC S3C44BOX s UART supports auto flow control with nRTS and nCTS signals in case it would have to connect UART to UART If users connect UART to a Modem disable auto flow control bit in UMCONn register and control the signal of nRTS by software In AFC nRTS is controlled by condition of the receiver and operation of transmitter is controlled by the nCTS sign
249. nd SPB Samsung Peripheral Bus The two ZDMA controllers attached to SSB are to transfer data from memory to memory from memory to I O memory Fixed destination and from I O devices and devices to memory The other two BDMA controllers transfer data from memory to I O devices and devices to memory In this case I O devices means the peripherals attached to SPB like SIO IIS and UART The main advantage of DMA is that it can transfer the data without CPU intervention The operation of ZDMA and BDMA can be initiated by S W the request from internal peripherals or the external request pins NXDREQO 1 The most important feature in ZDMA is the on the fly mode which reduces the number of cycles during DMA operation between external memory and a fixed external peripheral Fixed source or destination addressed device Usually the DMA transfer consists of two separate cycles one is Read from the source memory or I O device and the other is Write to memory or destination I O device To perform these operations the memory controller reads the data on data bus and writes this data to data bus again The on the fly mode has inseparable Read Write cycle In other words the memory controller generates the acknowledge signal for the source or destination device to read or write data on the data bus At the same time the memory controller also generates the Read or Write related control signals for memory access This kind of on the fly mode can
250. nd mGD are always higher than that of mGKA mGKB So the priorities of mGKA and mGKB are the lowest among the other interrupt sources The group priority among mGA mGB mGC and mGD is programmable is determined by the round robin method Between mGKA and mGKB mGKA always has the higher priority VECTORED INTERRUPT MODE ONLY FOR IRQ 53 44 has a new feature the vectored interrupt mode to reduce the interrupt latency time If ARM7TDMI receives the IRQ interrupt request from the interrupt controller ARM7TDMI executes an instruction at 0x00000018 In vectored interrupt mode the interrupt controller will load branch instructions on the data bus when fetches the instructions at 0x00000018 The branch instructions let the program counter be a unique address corresponding to each interrupt source The interrupt controller generates the machine code for branching to the vector address of each interrupt source For example If EINTO is IRQ the interrupt controller must generate the branch instruction which branches from 0x18 to 0x20 So the interrupt controller generates the machine code 000000 The user program code must locate the branch instruction which branches to the corresponding ISR interrupt service routine at each vector address The machine code branch instruction at the corresponding vector address is calculated as follows Branch Instruction machine code for vectored interrupt mode
251. ng the signaling method of the EINT4 000 Low level interrupt 001 High level interrupt 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered EINT3 14 12 Setting the signaling method of the EINTS 000 Low level interrupt 001 High level interrupt 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered EINT2 10 8 Setting the signaling method of the EINT2 000 Low level interrupt 001 High level interrupt 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered EINT1 6 4 Setting the signaling method of the EINT1 000 Low level interrupt 001 High level interrupt 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered EINTO 2 0 Setting the signaling method of the EINTO 000 Low level interrupt 001 High level interrupt 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered NOTE Because each external interrupt pin has a digital filter the interrupt controller can recognize a request signal that is longer than 3 clocks 079 ELECTRENICS 8 15 PORTS 3C44B0X RISC MICROPROCESSOR EXTINTPND EXTERNAL INTERRUPT PENDING REGISTER The external interrupt requests 4 5 6 and 7 are OR ed to provide a single interrupt source to interrupt controller EINT4 EINT5 EINT6 and EINT7 share the same interrupt request line EINT4 5 6 7 in interrupt controller If each of the 4
252. nored 3 4 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET BRANCH AND EXCHANGE BX This instruction is only executed if the condition is true The various conditions are defined in Table 3 2 This instruction performs a branch by copying the contents of a general register Rn into the program counter PC The branch causes a pipeline flush and refill from the address specified by Rn This instruction also permits the instruction set to be exchanged When the instruction is executed the value of Rn 0 determines whether the instruction stream will be decoded as ARM or THUMB instructions 28 27 24 23 20 19 16 15 12 11 1694 11 3 0 Operand Register of Rn 1 subsequent instructions decoded as THUMB instructions of Rn 0 subsequent instructions decoded as ARM instructions 31 28 Condition Field Figure 3 2 Branch and Exchange Instructions INSTRUCTION CYCLE TIMES The BX instruction takes 2S 1N cycles to execute where S and N are defined as sequential S cycle and non sequential N cycle respectively ASSEMBLER SYNTAX BX branch and exchange BX cond Rn cond Two character condition mnemonic See Table 3 2 Rn is an expression evaluating to a valid register number USING R15 AS AN OPERAND If R15 is used as an operand the behavior is undefined ELECTRONICS 3 5 ARM INSTRUCTION SET Examples 3 6 ADR RO Into_THUMB 1 BX RO
253. not generate an interrupt request The others can generate interrupt normally DMA mode configuration and DMA interrupt operation DMA mode DMA 0 INT Timer1 INT Timer2 Timer3 INT Timer4 Timer5 INT request MCLK Timer4_Int_tmp DMA mode 101 nDMA_ACK nDMA_REQ Timer4_Int Figure 9 8 The Timer4 DMA mode operation 9 10 ELECTRONICS 53 44 RISC MICROPROCESSOR PWM TIMER PWM TIMER CONTROL REGISTERS TIMER CONFIGURATION REGISTERO Timer input clock Frequency MCLK prescaler value 1 divider value prescaler value 0 255 divider value 2 4 8 16 32 TCFGO 0x01D50000 Configures the three 8 bit prescalers 0x00000000 Dead zone length 31 24 These 8 bits determine the dead zone length The 1 unit time of 0x00 the dead zone length is equal to the 1 unit time of timer 0 23 16 These 8 bits determine prescaler value for Timer 4 amp 5 15 8 These 8 bits determine prescaler value for Timer 2 amp 3 7 0 These 8 bits determine prescaler value for Timer 0 amp 1 ELECTRONICS 9 11 PWM TIMER S3C44BOX RISC MICROPROCESSOR TIMER CONFIGURATION REGISTER1 TCFG1 TCFG1 0 01050004 6 MUX amp DMA mode selecton register 0x00000000 DMA mode 27 24 Select DMA request channel 0000 No select all interrupt 0001 0010 Timer1 0011 Timer2 0100 Timer3 0101 Timer4 0110 5 0111 Reserved MUX 5 23 20 Select MUX
254. nt ARM instruction as shown in Table 3 22 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES STMIA RO R3 R7 Store the contents of registers R3 R7 starting at the address specified in RO incrementing the addresses for each word Write back the updated value of RO 3 96 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET FORMAT 16 CONDITIONAL BRANCH 15 14 13 1 8 7 1 12 ptt 7 0 8 bit Signed Immediate 11 8 Condition Figure 3 45 Format 16 OPERATION The instructions in this group all perform a conditional Branch depending on the state of the CPSR condition codes The branch offset must take account of the prefetch operation which causes the PC to be 1 word 4 bytes ahead of the current instruction The THUMB assembler syntax is shown in the following table Table 2 23 The Conditional Branch Instructions THUMB assembler ARMequvaem acon Branch if Z set equal Branch if Z clear not equal Branch if C set unsigned higher or same Branch if C clear unsigned lower Branch if N set negative Branch if N clear positive or zero Branch if V set overflow Branch if V clear no overflow Branch if C set and Z clear unsigned higher ELECTRONICS 3 97 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR Table 2 23 The Conditional Branch Instructions Continued
255. nterrupt source has asserted the interrupt request 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested E NI o ET EE 9 0 Notrequested 1 Requesed O Not requested 1 Requesed o Noremesed 1 Requesed 0 Not requested 1 Requested 0 requested 1 Requested 0 requested 1 Requested a ND EE p __ __ __ NN EE NE INT 0 Not requested 1 Requested al xm Wrumx 0 i Remesed 0 0 Not requested 1 Requested 0 Not requested 1 Requested INT RTC 0 Not requested 1 Requested 11 10 ELECTRONICS 53 44 RISC MICROPROCESSOR INTERRUPT CONTROLLER INT_ADC fo 0 Not requested 1 Requested ELECTRENICE 11 11 INTERRUPT CONTROLLER 53 44 RISC MICROPROCESSOR INTERRUPT MODE REGISTER INTMOD Each of the 26 bits in the interrupt mode register INTMOD corresponds to an interrupt source When the interrupt mode bit for each source is set to 1 the interrupt is processed by the ARM7TDMI core in the FIQ fast interrupt mode Otherwise it is processed in the IRQ mode n
256. ode The LCD controller within SSC44BOX can support the self refresh mode to reduce power comsumption The self refresh mode can only be applied to only the LCD which has the special LCD driver for example LCD panel of SED1580D from Seiko Epson Corporation The SED1580D has the built in display memory which can display the previous stored image in the built in display memory without image data fetch when the self refresh mode has been invoked The kind of self refresh mode can be made by writing the control bit of SELFREF in the LCDCONS register If the SELFREF bit is set to 1 the LCD controller enters into the self refresh mode from the next line When the LCD controller enters into the self refresh mode the signal of VCLK and VD should be fixed as Low and last VD value but the signal of VM VFRAME and VLINE will be generated continuously To exit the self refresh mode the user should execute the following path 1 disable the ENVID bit in LCDCON 1 register 2 disable SELFREF bit in LODCON 3 register and 3 enable ENVID bit again in LCDCON 1 register SL IDLE Mode LCD dedicated Idle Mode SL mode in the power management scheme should be used to enter into the LCD driver s self refresh mode In SL IDLE mode all function blocks except the LCD controller within SSC44BOX should be stopped to reduce the power comsumption because the power management block inserts divide by n input clock only to the LCD controller Timing Require
257. ode access mode select 1 DMA access mode Receive FIFO 10 0 Normal access mode access mode select 1 DMA access mode Transmit FFO 0 disable 1 FIFO enable enable Receive FIFO 0 disable 1 FIFO enable enable Transmit FIFO data 7 4 Data count value 0 8 count read only Receive FIFO data 3 0 Data count value 0 8 count read only NOTES 1 The IISFCON register can be accessed by halfword and word unit using STRH STR and LDRH LDR instructions or short int int type pointer in Little Big endian mode 2 Li HW W Access by halfword word unit when the endian mode is Little Bi HW W Access by halfword word unit when the endian mode is Big 17 8 ELECTRONICS 53 44 RISC MICROPROCESSOR IIS BUS INTERFACE IIS FIFO REGISTER IISFIF 15 bus interface contains two 16 byte FIFO for the transmit and receive mode Each FIFO has 16 width and 8 depth form which allows the FIFO to handles data by halfword unit regardless of valid data size Transmit and receive FIFO access is performed through FIFO entry the address of FENTRY is 0x01D18010 IISFIF 0x01D18010 Li HW R W 15 FIFO register 0x0 0x01D18012 Bi HW FENTRY 15 0 Transmit Receive data for IIS NOTES 1 The IISFIF register can be accessed by halfword and word unit using and LDRH instructions or short int type pointer in Little Big endian mode 2 Li HW Access by halfword unit when th
258. ogrammed to support the different requirements on the screen related to the number of horizontal and vertical pixels data line width for the data interface interface timing and refresh rate FEATURES Supports color gray monochrome LCD panels Supports 3 types of LCD panels 4 bit dual scan 4 bit single scan 8 bit single scan display type Supports Multiple Virtual Display Screen Supports Hardware Horizontal Vertical Scrolling system memory is used as the display memory Dedicated DMA supports to fetch the image data from video buffer located in system memory Supports multiple screen size Typical actual screen sizes 640x480 320x240 160x160 pixels Maximum virtual screen sizes color mode 4096x1024 2048x2048 1024x4096 etc Supports the monochrome 4 gray levels and 16 gray levels Supports 256 level colors for color STN LCD panel Supports the power saving mode SL_IDLE Mode ELECTRONICS 12 1 LCD CONTROLLER 53 44 RISC MICROPROCESSOR EXTERNAL INTERFACE SIGNAL VFRAME VLINE VCLK VM VD 3 0 4 bit VD 7 4 12 2 This is the frame synchronous signal between the LCD controller and LCD driver It signals the LCD panel of the start of a new frame The LCD controller asserts VFRAME after a full frame of display as shown in Fig 12 3 This is the line synchronous pulse signal between LCD controller and LCD driver and it is used by the LCD driver to t
259. on so this example uses a 33 bit register with taps at bits 33 and 20 The basic algorithm is newbit bit 33 eor bit 20 shift left the 33 bit number and put in newbit at the bottom this operation is performed for all the newbits needed i e 32 bits The entire operation can be done in 5 S cycles Enter with seed in Ra 32 bits Rb 1 bit in Rb Isb uses TST Rb Rb LSR 1 Top bit into carry MOVS Rc Ra RRX 33 bit rotate right ADC Rb Rb Rb Carry into Isb of Rb EOR 51412 involved EOR Ra Rc Rc _SR 20 similarly involved new seed in Ra Rb as before MULTIPLICATION BY CONSTANT USING THE BARREL SHIFTER Multiplication by 27 1 2 4 8 16 32 MOV Ra Rb LSL n Multiplication by 2 1 3 5 9 17 ADD Ra Ra Ra LSL n Multiplication by 2 n 1 3 7 15 RSB Ra Ra Ra LSL n ELECTRONICS 3 61 ARM INSTRUCTION SET Multiplication by 6 ADD Ra Ra Ra LSL 1 MOV Ra Ra LSL 1 Multiply by 10 and add in extra number ADD Ra Ra Ra LSL 2 ADD Ra Rc Ra LSLiH General recursive method for Rb Ra C C a constant 1 If C even say C 2 n D D odd D 1 MOV Rb Ra LSL n 0 lt gt 1 Rb Ra D MOV Rb Rb LSL n 2 If C MOD 4 1 say 24n D 1 D odd gt 1 D 1 ADD Rb Ra Ra LSL 0 lt gt 1 Rb Ra D ADD Rb Ra Rb LSL n 3 If C MOD 4 3 say 2 n D 1 D odd gt 1 D 1 RSB Rb Ra Ra LSL 0 lt gt 1 Rb Ra D RSB Rb Ra Rb LSL n 53 44 RIS
260. on format is shown in Figure 3 28 31 2827 2524 cone en om Figure 3 28 Undefined Instruction If the condition is true the undefined instruction trap will be taken Note that the undefined instruction mechanism involves offering this instruction to any coprocessors which may be present and all coprocessors must refuse to accept it by driving CPA and CPB HIGH INSTRUCTION CYCLE TIMES This instruction takes 25 11 1N cycles where S are defined as sequential S cycle non sequential N cycle and internal I cycle ASSEMBLER SYNTAX The assembler has no mnemonics for generating this instruction If it is adopted in the future for some specified use suitable mnemonics will be added to the assembler Until such time this instruction must not be used 3 58 ELECTRONICS 53 44 RISC MICROPROCESSOR INSTRUCTION SET EXAMPLES ARM INSTRUCTION SET The following examples show ways in which the basic ARM7TDMI instructions can combine to give efficient code None of these methods saves a great deal of execution time although they may save some they just save code USING THE CONDITIONAL INSTRUCTIONS Using Conditionals for Logical OR CMP Rn p BEQ Label CMP Rm q BEQ Label This can be replaced by CMP Rn p CMPNE Rm q BEQ Label Absolute Value TEQ Rn 0 RSBMI Rn Rn 0 Multiplication by 4 5 or 6 Run Time MOV Rc Ra LSL 2 CMP Rb
261. ondition code flags of the CPSR can be changed In other privileged modes the entire CPSR can be changed e Note that the software must never change the state of the T bit in the CPSR If this happens the processor will enter an unpredictable state e The SPSR register which is accessed depends on the mode at the time of execution For example only SPSR fiq is accessible when the processor is in FIQ mode e You must not specify R15 as the source or destination register e Also do not attempt to access an SPSR in User mode since no such register exists 3 18 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET MRS transfer PSR contents to a register 28 27 23 22 21 16 15 12 11 0 4 15 21 Destination Register 19 16 Source PSR 0 CPSR 1 SPSR_ lt current mode gt 31 28 Condition Field MRS transfer register contents to PSR 28 27 23 22 21 12 11 4 0010 101001111 00000000 3 0 Source Register 22 Destination PSR 0 CPSR 1 SPSR_ lt current mode gt 31 28 Condition Field MRS transfer register contents or immediate value to PSR flag bits only 28 27 26 25 24 23 22 21 12 11 0 po iEn Fd 22 Destination PSR 0 CPSR 1 SPSR current mode 25 Immediate Operand 0 Source operand is a register 1 SPSR current mode 11 0 Source Operand 0 00000000 Rm 3 0 Source Register 11 4 Source operand is a
262. onship is shown in Figure 2 5 THUMB state ARM state Lo registers 2 Hi registers Figure 2 5 Mapping of THUMB State Registers onto ARM State Registers 2 6 ELECTRONICS 53 44 RISC MICROPROCESSOR PROGRAMMER S MODEL Accessing Hi Registers in THUMB State In THUMB state registers R8 R15 the Hi registers are not part of the standard register set However the assembly language programmer has limited access to them and can use them for fast temporary storage A value may be transferred from a register in the range RO R7 a Lo register to a Hi register and from a Hi register to a Lo register using special variants of the MOV instruction Hi register values can also be compared against or added to Lo register values with the CMP and ADD instructions For more information refer to Figure 3 34 THE PROGRAM STATUS REGISTERS The ARM7TDMI contains a Current Program Status Register CPSR plus five Saved Program Status Registers SPSRs for use by exception handlers These register s functions are information about the most recently performed ALU operation e Control the enabling and disabling of interrupts Set the processor operating mode The arrangement of bits is shown in Figure 2 6 Condition Code Flags Reserved Control Bits 7 6 5 4 3 2 1 0 0990500 1 30 22 28 27 26 25 24 23 Overflow Mode bits Carry Borrow Extend State bit Zero FIQ disable Negative Less Than IRQ disable
263. operation clear this bit as 0 0 1 No interrupt pending when read 2 Clear pending condition amp Resume the operation when write 1 1 Interrupt is pending when read 2 N A when write transmit clock prescaler transmit clock frequency is determined by this 4 bit prescaler value according to the following formula Tx clock IICCLK IICCON 3 0 1 1 Interfacing with EEPROM the ack generation may be disabled before reading the last data in order to generate the STOP condition in Rx mode 2 AllC bus interrupt occurs 1 when 1 byte transmit or receive operation is completed 2 when a general call or a slave address match occurs or 3 if bus arbitration fails 3 To time the setup time of IICSDA before IISSCL rising edge IICDS has to be written before clearing the interrupt pending bit 4 ICCLK is determined by IICCON 6 Tx clock can vary by SCL transition time When IICCON 6 0 3 01 0 0 or 0x1 is not available 5 Ifthe IICON 5 0 IICON 4 does not operate correctly So It is recommended to set IICCON 5 1 although you does not use the IIC interrupt ELECTRONICS 16 11 IIC BUS INTERFACE S3C44BOX RISC MICROPROCESSOR MULTI MASTER IIC BUS CONTROL STATUS REGISTER IICSTAT 0x01D60004 control status register 0000 0000 Mode selection master slave Tx Rx mode select bits 00 Slave receive mode 01 Slave transmit mode 10
264. ormal interrupt The 26 interrupt sources are summarized as follows INTMOD 0x01E00008 R W Interrupt mode Register 0x0000000 0 IRQ mode 1 FIQ mode EINT2 0 IRQ mode 1 FIQ mode EINT3 0 1 FIQ mode EINT4 5 6 7 0 IRQ mode 1 mode 1 1 INT BDMA1 16 IRQ mode FIQ mode INT WDT 15 0 IRQ mode FIQ mode INT UERRO 1 14 0 IRQ mode 1 FIQ mode INT TIMERO 13 0 IRQ mode 1 FIQ mode 12 0 IRQ mode 1 FIQ mode INT_SIO IRQ mode 1 FIQ mode INT_UTXDO IRQ mode 1 FIQ mode INT_UTXD1 0 IRQ mode 1 FIQ mode INT 0 mode 1 mode INT ADC 0 10 180 1 mode 7 5 4 0 lo 2 d 11 12 ELECTRONICS 53 44 RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT MASK REGISTER INTMSK Each of the 26 bits except the global mask bit in the interrupt mask register INTMSK corresponds to an interrupt source When a source interrupt mask bit is 1 and the corresponding interrupt event occurs the interrupt is not serviced by the CPU If the mask bit is 0 the interrupt is serviced upon a request If the global mask bit is set to 1 all interrupt requests are not serviced and the INTPND register is set to 1 If the INTMSK is changed ISR interrupt service routine and the vectored interrupt is used an INTMSK bit can not mask an interrupt event which had been latched in INTPND before the INT
265. ormal operation lopcpu 1 66MHz Lr mode Both oscillators running CPU sais LCD refresh active Slow mode 1MHz 7 Total current consumption SL Idle mode SL ldle mode 1MHz MHz mode Just running 32KHz oscillator for ea C RTC all other I O static late x tal 32 768KHz for RTC consumption Table 19 5 Typical current decrease percentage by register 66MHz 3 2 Unit NOTE This table includes each power consumption of each peripherals For example If you do not use IIS and you turned off IIS block by CLKCON register you can save the 1 3 portion from total power consumption ELECTRENICS 19 3 ELECTRICAL DATA 53 44 RISC MICROPROCESSOR MCLK MHz 80 75 70 66 60 50 40 Spec Guranteed Area 30 2 4 2 5 26 2 7 VDDCPU V Figure 19 1 Typical Operating Voltage Frequency Range VDDIO 3 3V Room temperature amp SMDK41100 board 19 4 ELECTRONICS 53 44 RISC MICROPROCESSOR ELECTRICAL DATA A C ELECTRICAL CHARACTERISTICS 1 2 1 2 The clock input from the EXTALO pin Figure 19 2 EXTALO Clock Timing tEXTCYC tEXTHIGH tEXTLOW 1 2 The clock input from the Figure 19 3 EXTCLK Clock Input Timing ELECTRENICS 19 5 ELECTRICAL DATA 53 44 RISC MICROPROCESSOR tEX2CK CLKo
266. ory register LDR from word aligned address memory register LDR from address offset by 2 Figure 3 15 Little Endian Offset Addressing Big Endian Configuration A byte load LDRB expects the data on data bus inputs 31 through 24 if the supplied address is on a word boundary on data bus inputs 23 through 16 if it is a word address plus one byte and so on The selected byte is placed in the bottom 8 bits of the destination register and the remaining bits of the register are filled with zeros Please see Figure 2 1 A byte store STRB repeats the bottom 8 bits of the source register four times across data bus outputs 31 through 0 The external memory system should activate the appropriate byte subsystem to store the data A word load LDR should generate a word aligned address An address offset of 0 or 2 from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 31 through 24 This means that half words accessed at these offsets will be correctly loaded into bits 16 through 31 of the register A shift operation is then required to move and optionally sign extend the data into the bottom 16 bits An address offset of 1 or 3 from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 15 through 8 A word store STR should generate a word aligned address The word presented to the data bus is not affected if the address is not wo
267. pecified in the CP Opc field and possibly in the CP field on the contents of CRn and CRm and place the result in CRd ELECTRONICS 3 51 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES Coprocessor data operations take 1S bl incremental cycles to execute where bis the number of cycles spent in the coprocessor busy wait loop 5 and are defined as sequential S cycle and internal ASSEMBLER SYNTAX CDP cond p lt expression1 gt cd cn cm lt expression2 gt cond Two character condition mnemonic See Table 3 2 p The unique number of the required coprocessor lt expression1 gt Evaluated to a constant and placed in the CP Opc field cd cn and cm Evaluate to the valid coprocessor register numbers CRd CRn and CRm respectively lt expression2 gt Where present is evaluated to a constant and placed in the CP field EXAMPLES CDP p1 10 c1 c2 c3 Request coproc 1 to do operation 10 on CR2 and CR3 and put the result in CR1 CDPEQ 2 5 1 2 3 2 If Z flag is set request coproc 2 to do operation 5 type 2 CR2 and CR3 put the result in 3 52 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET COPROCESSOR DATA TRANSFERS LDC STC The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 26 This class of instruction is used to load LDC o
268. pling frequency serial bit clock per channel 256 384fs master clock Programmable frequency divider for master clock and CODEC clock 32 bytes 2X16 FIFO for transmit and receive Normal and DMA transfer mode ELECTRONICS 17 1 IIS BUS INTERFACE 53 44 RISC MICROPROCESSOR BLOCK DIAGRAM 1 TxFIFO RxFIFO IISCLK IISLRCK CODECLK Figure 17 1 15 Block Diagram FUNCTIONAL DESCRIPTIONS Bus interface register bank and state machine BRFC Bus interface logic and FIFO access are controlled by the state machine 3 bit dual prescaler IPSR One prescaler is used as the master clock generator of the IIS bus interface and the other is used as the external CODEC clock generator 16 byte FIFOs TXFIFO RXFIFO In transmit data transfer data are written to TXFIFO and in the receive data transfer data are read from RXFIFO Master generaor SCLKG In master mode serial bit clock is generated from the master clock Channel generator and state machine CHNC and IISLRCK are generated and controlled by the channel state machine 16 bit shift register SFTR Parallel data is shifted to serial data output in the transmit mode and serial data input is shifted to parallel data in the receive mode TRANSMIT OR RECEIVE ONLY MODE Normal transfer 15 control register has FIFO ready flag bits for transmit and receive FIFO When FIFO is ready to transmit data the FIFO ready
269. ports all existing LCD drivers The LCD controller supports multiple screen sizes by special register setting The CLKVAL value determines the frequency of VCLK The data transmission rate for the VD port of the LCD controller should be calculated in order to determine the value of CLKVAL register The data transmission rate is given by the following equation CLKVAL has to be determined such that the VCLK value is greater than the data transmission rate Data transmission rate HS x VS x FR x MV HS Horizontal LCD size VS Vertical LCD size FR Frame rate MV Mode dependent value Table 12 4 MV Value for Each Display Mode ELECTRONICS 12 25 LCD CONTROLLER 53 44 RISC MICROPROCESSOR The LCDBASEU register value is the first address value of the frame buffer The lowest 4 bits must be eliminated for burst 4 word access The LCDBASEL register value is determined by LCD size and LCDBASEU The LCDBASEL value is given by the following equation LCDBASEL LCDBASEU LCDBASEL offset Example 1 160 x 160pixel 4 level gray 80 frame sec 4 bit single scan display system clock frequency 66 MHz WLH 1 WDLY 1 LCD frame buffer SDRAM Bus width 16bit System bus occupation LCD data transmission frequency System clock frequency LCD data transmission frequency Total LCD data during 1sec x Transmission cycle 1byte Total LCD data during 1sec Total LCD data x frame rate 160 160pixel
270. processing with register specified shift 15 11 Data processing with PC written 28 1 Data processing with register specified shift PC written 25 1N 11 NOTE 5 as defined sequential S cycle non sequential N cycle and internal respectively 07 3 16 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLER SYNTAX e MOV MVN single operand instructions lt opcode gt cond S Rd lt Op2 gt e CMP CMN TEQ TST instructions which do not produce a result lt opcode gt cond Rn lt Op2 gt AND EOR SUB RSB ADD ADC SBC RSC ORR BIC lt opcode gt cond S Rd Rn lt Op2 gt where lt Op2 gt Rm lt shift gt or lt expression gt cond A two character condition mnemonic See Table 3 2 S Set condition codes if S present implied for CMP CMN TEQ TST Rd Rn and Rm Expressions evaluating to a register number lt gt If this is used the assembler will attempt generate shifted immediate 8 bit field to match the expression If this is impossible it will give an error lt shift gt lt Shiftname gt lt register gt or lt shiftname gt expression or RRX rotate right one bit with extend lt shiftname gt s ASL LSL LSR ASR ROR ASL is a synonym for LSL they assemble to the same code EXAMPLES ADDEQ R2 R4 R5 If the 2 flag is set make R2 R4 R5 TEQS R4 3 Test R4 for equality with 3 The S is in fact
271. r 4 start stop 20 This bit determines start stop for Timer 4 0 Stop 1 Start for Timer 4 Timer 3 auto reload 19 This bit determines auto reload on off for Timer 3 on off 0 One shot 1 Interval mode auto reload Timer 3 output 18 bit determines output inverter on off for Timer 3 inverter on off Inverter off 1 Inverter on for TOUT3 Timer 3 manual 17 This bit determine manual update for Timer 3 update note 0 No operation 1 Update TCNTB3 TCMPB3 Timer 3 start stop 16 This bit determines start stop for Timer 3 0 Stop 1 Start for Timer 3 Timer 2 auto reload 15 This bit determines auto reload on off for Timer 2 on off 0 One shot 1 Interval mode auto reload Timer 2 output 14 1 bit determines output inverter on off for Timer 2 inverter on off Inverter off 1 Inverter on for TOUT2 Timer 2 manual 13 This bit determines the manual update for Timer 2 update note 0 No operation 1 Update TCNTB2 TCMPB2 Timer 2 start stop 12 This bit determines start stop for Timer 2 0 Stop 1 Start for Timer 2 NOTE This bit has to be cleared at next writing ELECTRENICS 9 13 PWM TIMER 53 44 RISC MICROPROCESSOR TIMER CONTROL REGISTER TCON Continued Timer 1 auto reload 11 This bit determines the auto reload on off for Timer1 on off 0 One shot 1 Interval mode auto reload Timer 1 output 10 bit determines the output inverter on off for Timer inverter on off Inverter of
272. r case The START bit is cleared in one ADC clock while rADCCON amp 0x40 for 1 0 1 lt rADCPSR i To avoid The second FLAG error case Uart_Printf A0 03xh rADCDAT ELECTRONICS 13 3 A D CONVERTER 53 44 RISC MICROPROCESSOR The 1 Programming Technique in ADC There is no sample amp hold circuit on the ADC input pin So The small current will flow in out from AINn input pins because of the ADC internal operation If the output impedance of source signal is high this current will change the signal voltage The current is about 7 6uA in the following condition 100KSPS 10K ohm resister Vsource 0 0V Induced Current 7 84 78mV 1 This ADC error will be decreased if the output impedance of the signal source is reduced For example If the output impedance of the signal source is 1Kohm the induced ADC error by the ADC input current is 3 1 10 2 The current will be also decreased if ADCPSR is large If the ADC conversion rate is 30KSPS the current will be about 1 2uA The ADCPSR value is higher the current is lower The ADC conversion error is decreased if the ADCPSR is large beside the above ADC conversion error If you want accurate ADC conversion you let the ADCPSR as large as possible Because our ADC have sample amp hold circuit the input frequency bandwidth is 0 100Hz This limitation is because there is no internal sample amp hold circuit But If you can ignore the smal
273. r channel process irq Used for general purpose interrupt handling Supervisor svc Protected mode the operating system Abort mode abt Entered after a data or instruction prefetch abort e System sys A privileged user mode for the operating system e Undefined und Entered when an undefined instruction is executed Mode changes may be made under software control or may be brought about by external interrupts or exception processing Most application programs will execute in User mode The non user modes known as privileged modes are entered in order to service interrupts or exceptions or to access protected resources REGISTERS ARMT7TDMI has a total of 37 registers 31 general purpose 32 bit registers and six status registers but these cannot all be seen at once The processor state and operating mode dictate which registers are available to the programmer The ARM State Register Set In ARM state 16 general registers and one or two status registers are visible at any one time In privileged non User modes mode specific banked registers are switched in Figure 2 3 shows which registers are available in each mode the banked registers are marked with a shaded triangle The ARM state register set contains 16 directly accessible registers RO to R15 All of these except R15 are general purpose and may be used to hold either data or address values In addition to these there is a seventeenth register u
274. r does not permit the hand over of bus mastership during the DMA operation using the demand mode In other words the DMA monopolizes bus usage right up to the completion of DMA operation Care is warranted when using the DMA operation in the demand mode because this kind of monopoly may cause an un expected malfunction on other masters by blocking optimal bus sharing ELECTRONICS 7 7 DMA 53 44 RISC MICROPROCESSOR DMA TRANSFER MODE There are three types of DMA transfer modes Unit transfer mode Block transfer mode and On the fly transfer mode Different from the external DMA request acknowledge protocol the DMA transfer mode defines the number of reads writes per unit transfer as shown in the following table DMA Transfer Mode Read Write Unit transfer 1 unit read then 1 unit write Block transfer 4 unit burst read then 4 unit burst write On the fly transfer 1 unit read or 1 unit write exclusively Unit Transfer Mode The unit transfer mode means that the paired DMA read write cycle happens corresponding each DMA request as shown below in Figure Figure 7 9 shows the example case of the unit transfer mode at the handshake mode nXDREQ 1 nXDACK 1 Read Write Read Write Byte Byte Byte Byte Figure 7 9 Unitary Transfer Mode with Handshake mode 7 8 ELECTHDNICS 53 44 RISC MICROPROCESSOR DMA Block 4 word Transfer Mode The block 4 word transfer mode means that the successive 4 word DMA read cycle happ
275. r store STC a subset of a coprocessors s registers directly to memory ARM7TDM is responsible for supplying the memory address and the coprocessor supplies or accepts the data and controls the number of words transferred 2827 2524 23 22 21 20 19 1615 12 11 0 Lus ID on 7 0 Unsigned 8 Bit Immediate Offset 11 8 Coprocessor Number 15 12 Coprocessor Source Destination Register 19 16 Base Register 20 Load Store Bit 0 Store to memory 1 Load from memory 21 Write back Bit 0 No write back 1 Write address into base 22 Transfer Length 23 Up Down Bit 0 Down subtract offset from base 1 Up add offset to base 24 Pre Post Indexing Bit 0 Post add offset after transfer 1 Pre add offset before transfer 31 28 Condition Field Figure 3 26 Coprocessor Data Transfer Instructions THE COPROCESSOR FIELDS The field is used to identify the coprocessor which is required to supply or accept the data anda coprocessor will only respond if its number matches the contents of this field The field and the bit contain information for the coprocessor which may be interpreted different ways by different coprocessors but by convention CRd is the register to be transferred or the first register where more than one is to be transferred and the N bit is used to choose one of two transfer length options For instance N 0 could select the transfer of a single register
276. rUERRO1 0x54 b b Idr pc HandlerTIMERO 0x60 Idr pc HandlerTIMER1 Idr pc HandlerTIMER2 Idr pc HandlerTIMER3 Idr pc HandlerTIMER4 Idr pc HandlerTIMER5 0x74 b b pc HandlerURXDO 0x80 pc HandlerURXD1 Idr pc HandlerlIC Idr pc HandlerSIO pc HandlerUTXDO Idr pc HandlerUTXD1 0x94 b b Idr pc HandlerRTC 0 0 b b b b b b pc HandlerADC Oxb4 ELECTRENICE 11 7 INTERRUPT CONTROLLER 53 44 RISC MICROPROCESSOR EXAMPLE FOR NON VECTORED INTERRUPT MODE USING LISPR In the non vectored interrupt mode the IRQ FIQ handler will move the PC to the corresponding ISR by analyzing _ISPR F_ISPR register HandleXXX addresses hold each corresponding ISR routine start addresses The source code for an IRQ interrupt is as follows ENTRY b ResetHandler for debug b HandlerUndef handlerUndef b HandlerSWI SWlinterrupt handler b HandlerPabort handlerPAbort b HandlerDabort handlerDAbort b handlerReserved b IsrlIRQ b HandlerFIQ IsrIRQ sub sp sp 4 reserved for PC stmfd sp r8 r9 Idr r9 I_ISPR Idr r9 r9 mov r8 0x0 0 movs r9 r9 lsr 1 bcs SF 1 add r8 r8 4 b BO 1 Idr r9 HandleADC add r9 r9 r8 Idr r9 r9 str r9 sp 8 Idmfd sp r8 r9 pc HandleADC 4 HandleRTC 4 HandleUTXD1 4 Handle UTXDO 4 HandleEINT3 4 HandleEINT2 4 HandleEINT1 4 HandleEINTO 4 Oxci c7 fffSa 11 8 ELECTRONICS 53 44 RISC MICROPROCESSO
277. ransfer the contents of it s horizontal line shift register to the LCD panel for display The LCD controller asserts VLINE after an entire horizontal line of data has been shifted into the LCD driver This pin is the pixel clock signal between the LCD controller and LCD driver and data is sent by the LCD controller on the rising edge of VCLK and sampled by LCD driver on the falling edge of VCLK This is the AC signal for the LCD driver The VM signal is used by the LCD driver to alternate the polarity of the row and column voltage used to turn the pixel on and off The VM signal can be toggled on every frame or toggled on the programmable number of the VLINE signal These are LCD pixel data output ports For a 4 bit or 8 bit single scan display these 4 bit data are used as the display data as shown in Fig 12 4 In case of 4 bit dual scan display these plays into its role of the upper display data as shown in Fig 12 4 These are LCD pixel data output ports For a 8 bit single scan display these data are used as upper dispaly data as shown in Fig 12 4 For a 4 bit dual scan display these data are used as lower display data as shown in Fig 12 4 ELECTRONICS 53 44 RISC MICROPROCESSOR LCD CONTROLLER BLOCK DIAGRAM System Bus VCLK VLINE REGBANK TIMEGEN VM VD 3 0 LCDCDMA VIDPRCS 32 3 VD 7 4 Figure 12 1 LCD Controller Block Diagram The LCD controller within 53 44 is used to transfer the
278. rd aligned That is bit 31 of the register being stored always appears on data bus output 31 3 30 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET USE OF R15 Write back must not be specified if R15 is specified as the base register Rn When using R15 as the base register you must remember it contains an address 8 bytes on from the address of the current instruction R15 must not be specified as the register offset Rm When R15 is the source register Rd of a register store STR instruction the stored value will be address of the instruction plus 12 RESTRICTION ON THE USE OF BASE REGISTER When configured for late aborts the following example code is difficult to unwind as the base register Rn gets updated before the abort handler starts Sometimes it may be impossible to calculate the initial value After an abort the following example code is difficult to unwind as the base register Rn gets updated before the abort handler starts Sometimes it may be impossible to calculate the initial value EXAMPLE LDR RO R1 R1 Therefore a post indexed LDR or STR where Rm is the same register as Rn should not be used DATA ABORTS A transfer to or from a legal address may cause problems for a memory management system For instance in a system which uses virtual memory the required data may be absent from main memory The memory manager can signal a problem by taking the processor ABORT input HIGH whereupon the Da
279. re 15 1 The watchdog timer uses MCLK as its only source clock To generate the corresponding watchdog timer clock the MCLK frequency is prescaled first and the resulting frequency is divided again Interrupt 8 bit Prescaler WONT Reset Signal Generator RESET Down Counter WTCON 15 8 WTCON 4 3 WTCON 2 WTCON O Figure 15 1 Watchdog Timer Block Diagram The prescaler value and the frequency division factor are specified in the watchdog timer control register WTCON The valid prescaler values range from 0 to 28 1 The frequency division factor can be selected as 16 32 64 or 128 Use the following equation to calculate the watchdog timer clock frequency and the duration of each timer clock cycle t watchdog 1 MCLK Prescaler value 1 Division factor WTDAT amp WTCNT When the watchdog timer is enabled first the value of watchdog timer data register cannot be automatically reloaded into the WTCNT timer counter For this reason an initial value must be written to the watchdog timer count register WTCNT before the watchdog timer starts CONSIDERATION OF DEBUGGING ENVIRONMENT When 53 44 is in debug mode using Embedded ICE the watchdog timer must not operate The watchdog timer can determine whether or not the current mode is the debug mode from the CPU core signal DBGACK signal Once the DBGACK signal is asserted the reset output of the watchdog timer is not activated
280. re 5 3 Main Oscillator Circuit Examples 5 4 ELECTRONICS 53 44 RISC MICROPROCESSOR CLOCK amp POWER MANAGEMENT CLOCK CONTROL LOGIC The clock control logic determines the clock source to be used i e the PLL clock or the direct OSC clock When PLL is configured to a new frequency value the clock control logic disables the FOUT until the PLL output is stabilized using the PLL locking time The clock control logic is also activated at power on reset and wake up from power down mode PLL Lock Time The lock time is the time required for PLL output stabilization The lock time should be bigger than 208us After reset and wake up from STOP and SL_IDLE mode respectively the lock time is inserted automatically by the internal logic with lock time count register The automatically inserted lock time is calculated as follows t_lock the PLL lock time by H W logic 1 Fin x n n LTIMECNT value Power On Reset Figure 5 4 shows the clock behavior during the power on reset sequence The crystal oscillator begins oscillation within several milliseconds When nRESET is released after the stabilization of OSC clock the PLL starts to operate according to the default PLL configuration However PLL is commonly known to be unstable after power on reset so Fin fed directly to Fout instead of the Fpllo PLL output before the S W newly configures the PLLCON Even if the user wants to use the default value of PLLCON register after Reset the
281. re 6 3 Cache Memory Mapping WRITE BUFFER OPERATION Write Buffer Operation 53 44 has four write buffer registers to enhance memory writing performance When the write buffer mode is enabled the CPU writes data into the write buffer registers instead of an external memory even when the external bus is already occupied by another bus master like DMA The write buffer block will write the data when the system bus is not occupied by higher priority bus masters Also CPU performance will be enhanced because the CPU does not have to wait the completion of the write operation The write buffer has 4 registers Each register includes a 32 bit data field a 28 bit address field and a 2 bit status field 27 0 31 0 31 0 Write Buffer Data Data to be written into external memory 1 0 MAS 00 8 bit data mode 01 16 bit data mode 10 32 bit data mode 11 Not used 27 0 Address Indicates the address of write data Figure 6 4 Write Buffer Configuration 6 6 ELECTRONICS 53 44 RISC MICROPROCESSOR CPU WRAPPER amp BUS PRIORITIES BUS PRIORITY MAP In 53 44 there are seven bus masters LCD_DMA BDMAO BDMA1 ZDMAO ZDMA1 nBREQ external bus masters and CPU wrapper The priorities among these bus masters after a reset are as follows 1 7 oN DRAM refresh controller LCD_DMA ZDMAO 1 1 External bus master Write buffer Cache amp CPU The bus priorities among LCD_
282. re requested at the same time the ISPR register shows only the requested interrupt source with the highest priority ics ooo R Curent i proriy of save Curent IRG priority or masier regse ISPR 0x01E00020 IRQ interrupt service pending register 0x00000000 Only one service bit can be set ISPC 0x01E00024 W IRQ interrupt service clear register Whatever to be set INTPND will be cleared automatically IMPORTANT NOTE In FIQ mode there is no service pending register like _ISPR users must check INTPND resister ELECTRONICS 11 15 INTERRUPT CONTROLLER 53 44 RISC MICROPROCESSOR IRQ PRIORITY OF SLAVE REGISTER PSLV PSLV determines the interrupt priorities among the 4 interrupt sources of each slave group LPSLV 0 01 00010 priority of slave register 0 10101516 PSLAVE mGA 31 24 Determine the priorities among sGA B D of mGA 0 10 Each sGn must have a different priority PSLAVE mGB 23 16 Determine the priorities among sGA B C D of mGB 0 10 Each sGn must have a different priority PSLAVE mGC 15 8 Determine the priorities among sGA B C D of mGC 0 10 Each sGn must have a different priority PSLAVE mGD 7 0 Determine the priorities among sGA B C D of mGD 0 10 Each sGn must have a different priority PSLAVE mGA 31 30 00 1 a 11 sGA EINTO 0 01 10 s
283. register or a 3 bit immediate value to be added to or subtracted from a Lo register The THUMB assembler syntax is shown in Table 3 9 NOTE All instructions in this group set the CPSR condition codes Table 3 9 Summary of Format 2 Instructions THUMB Assembler Equipment Action ADD Rs Rn ADDS Rs Rn Add contents of Rn to contents of Rs Place result in Rd 1 ADD Rs Offset3 ADDS Rd Rs Offset3 Add 3 bit immediate value to contents of Rs Place result in Rd ENSE eee SUB Rs Rn SUBS Rs Rn Subtract contents of Rn from contents of Rs Place result in Rd SUB Rd Rs Offset3 SUBS Rd Rs Offset3 Subtract 3 bit immediate value from contents of Rs Place result in Rd 07 3 70 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 9 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES ADD RO R3 R4 RO R4 and set condition codes on the result SUB R6 R2 6 22 6 and set condition codes ELECTRONICS 3 71 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR FORMAT 3 MOVE COMPARE ADD SUBTRACT IMMEDIATE 15 14 13 7 0 12 11 10 8 9 D 9 7 7 0 Immediate Vale 10 8 Source Destination Register 12 11 Opcode 0 MOV 1
284. rnal memories faster transfer and optional bus utilization are required But if more number of DMA channels for data transfer between external memories Maximum 2 channels using ZDMA is needed the BDMA can be used SSB Source Selector 5 5 Signals SBS_STATE 727 Source Selector SLAVE BDMA Peripheral Control SPB Sginals Figure 7 2 BDMA Controller Block Diagram ELECTRONICS 7 3 DMA 53 44 RISC MICROPROCESSOR EXTERNAL DMA REQ ACK PROTOCOL There are four types of external DMA request acknowledge protocols Each type defines how the signals like DMA request and acknowledge are related to these protocols Because ZDMA and BDMA can support external triggering these protocols correspond to ZMDA only not BDMA Handshake Mode In the handshake mode the DMA can generate a single DMA acknowledge corresponding to the single DMA request The Figure 7 3 shows the handshake mode of DMA operation In this figure the DMA service means a paired or an inseparable Read and Write cycle during DMA operation which is one DMA operation During one DMA operation Pared or inseparable Read and Write cycle the bus controller does not allocate bus usage right to other bus masters If the user wants to allocate the bus usage properly for the higher priority master during one DMA operation the user should use the single step mode which is explained in the next page The single step mode considers one DMA operation to consist of separable Read
285. s 4 5 have 4 divided signals 1 2 1 4 1 8 1 16 and one input TCLK EXTCLK Each timer block receives its own clock signals from the clock divider which receives the clock from the corresponding 8 bit prescaler The 8 bit prescaler is programmable and divides the MCLK signal according to the loading value which is stored in TCFGO and TCFG1 registers The timer count buffer register TCNTBn has an initial value which is loaded into the down counter when the timer is enabled The timer compare buffer register TCMPBn has an initial value which is loaded into the compare register to be compared with the down counter value This double buffering feature of TCNTBn and TCMPBn makes the timer generate a stable output when the frequency and duty ratio are changed Each timer has its own 16 bit down counter which is driven by the timer clock When the down counter reaches zero the timer interrupt request is generated to inform the CPU that the timer operation has been completed When the timer counter reaches zero the value of corresponding TCNTBn is automatically loaded into the down counter to continue the next operation However if the timer stops for example by clearing the timer enable bit of TCONn during the timer running mode the value of TCNTBn will not be reloaded into the counter The value of TCMPBn is used for PWM pulse width modulation The timer control logic changes the output level when the down counter value matches the value of the comp
286. s based on priority by software For example if you define all interrupt source as IRQ Interrupt Mode Setting and if there are 10 interrupt requests at the same time you can determine the interrupt service priority by reading the interrupt pending register which indicates the type of interrupt request that will occur This kind of interrupt process requires a long interrupt latency until to jump to the exact service routine The 53 44 may support this kind of interrupt processing To solve the above mentioned problem 53 44 supports a new interrupt processing called vectored interrupt mode which is a general feature of the CISC type micro controller to reduce the interrupt latency In other words the hardware inside the S3C44BOX interrupt controller provides the interrupt service vector directly When the multiple interrupt sources request interrupts the hardware priority logic determines which interrupt should be serviced At same time this hardware logic applies the jump instruction of the vector table to 0x18 or Ox1c which performs the jump to the corresponding service routine Compared with the previous software method it will reduce the interrupt latency dramatically ELECTRENICE 11 1 INTERRUPT CONTROLLER 53 44 RISC MICROPROCESSOR INTERRUPT CONTROLLER OPERATION F bit and I bit of PSR program status register If the F bit of PSR program status register in ARM7TDMI CPU is set to 1 the CPU does not
287. s each of the 8 possible 0x00000000 red combinations will choose 000 REDVAL 3 0 001 REDVAL 7 4 010 REDVAL 11 8 011 REDVAL 15 12 100 REDVAL 19 16 101 REDVAL 23 20 110 REDVAL 27 24 111 REDVAL 31 28 GREEN Lookup Table Register GREENLUT 0 01 00018 R W Green lookup table register 0x00000000 GREENVAL 31 0 These bits define which of the 16 shades each of the 8 possible 0x00000000 green combinations will choose 000 GREENVAL 3 0 001 GREENVAL 7 4 010 1 8 011 GREENVAL 15 12 100 GREENVAL 19 16 101 GREENVAL 23 20 110 GREENVAL 27 24 111 31 28 BLUE Lookup Table Register BLUELUT 0 01 0001 R W Blue lookup table register 0x0000 BLUEVAL 15 0 These bits define which of the 16 shades each of the 4 possible 0x0000 blue combinations will choose 00 01 7 4 10 11 8 11 15 12 ELECTRONICS 12 21 LCD CONTROLLER 53 44 RISC MICROPROCESSOR Dithering Pattern DP1_2 Register DP1_2 0x01F00020 R W Dithering pattern duty 1 2 register 5 Please refer to sample program source for the latest value of this register DP12 Description Initial state state DP1_2 15 0 Recommended pattern value 5 1010 0101 1010 0101 0 5 5 Dithering Pattern DPA 7 Register DP4 7 0 01 00024 R W Dithering pattern duty 4 7 r
288. s in this format have an equivalent ARM instruction as shown in Table 3 21 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES PUSH RO R4 LR Store RO R1 R2 R3 R4 and R14 LR at the stack pointed to by R13 SP and update R13 Useful at start of a sub routine to save workspace and return address POP R2 R6 PC Load R2 R6 and R15 PC from the stack pointed to by R13 SP and update R13 Useful to restore workspace and return from sub routine ELECTRONICS 3 95 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR FORMAT 15 MULTIPLE LOAD STORE 15 14 13 7 0 12 11 10 8 me 7 0 Register List 10 8 Base Register 11 Load Store Bit 0 Store to memory 1 Load from memory Figure 3 44 Format 15 OPERATION These instructions allow multiple loading and storing of Lo registers The THUMB assembler syntax is shown in the following table Table 3 22 The Multiple Load Store Instructions THUMB assembler ARM equivalent Action STMIA Rlist STMIA Rlist Store the registers specified by Rlist starting at the base address in Rb Write back the new base address LDMIA Rb Rlist LDMIA Rb Rlist Load the registers specified by Rlist starting at the base address in Rb Write back the new base address INSTRUCTION CYCLE TIMES All instructions in this format have an equivale
289. s instruction but bit 1 of the PC is forced to 0 to ensure it is word aligned ELECTRONICS 3 79 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES LDR R3 PC 844 Load into R3 the word found at the address formed by adding 844 to PC bit 1 of PC is forced to zero Note that the THUMB opcode will contain 211 as the Word8 value 3 80 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET FORMAT 7 LOAD STORE WITH REGISTER OFFSET 15 14 13 12 11 10 9 8 6 5 3 2 0 ro mw 2 0 Source Destination Register 5 3 Base Register 8 6 Offset Register 10 Byte Word Flag 0 Transfer word quantity 1 Transfer byte quantity 11 Load Store Flag 0 Store to memory 1 Load from memory Figure 3 36 Format 7 ELECTRONICS 3 81 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR OPERATION These instructions transfer byte or word values between registers and memory Memory addresses are pre indexed using an offset register in the range 0 7 The THUMB assembler syntax is shown in Table 3 14 Table 3 14 Summary of Format 7 Instructions STR Rb Ro STR Rb Ro Pre indexed word store Calculate the target address by adding together the value
290. s point of view the ARM7TDMI can be in one of two states e ARM state which executes 32 bit word aligned ARM instructions e THUMB state which can execute 16 bit halfword aligned THUMB instructions In this state the PC uses bit 1 to select between alternate halfwords NOTE Transition between these two states does not affect the processor mode or the contents of the registers SWITCHING STATE Entering THUMB State Entry into THUMB state can be achieved by executing a BX instruction with the state bit bit 0 set in the operand register Transition to THUMB state will also occur automatically on return from an exception IRQ FIQ UNDEF ABORT SWI etc if the exception was entered with the processor in THUMB state Entering ARM State Entry into ARM state happens e On execution of the BX instruction with the state bit clear in the operand register e On the processor taking an exception IRQ RESET UNDEF ABORT SWI etc In this case the PC is placed in the exception mode s link register and execution commences at the exception s vector address MEMORY FORMATS views memory as a linear collection of bytes numbered upwards from zero Bytes 0 to hold the first stored word bytes 4 to 7 the second and so on ARM7TDMI can treat words in memory as being stored either in Big Endian or Little Endian format ELECTRONICS 2 1 PROGRAMMER S MODEL 53 44 RISC MICROPROCESSOR BIG ENDIAN FORMAT I
291. s to normal mode slow mode or even STOP mode Table 5 2 The Status of PLL and Fout after Wake Up Mode before wake up PLL on off after wake up Fout after wake up and Fout after the lock time before the lock time by internal logic Signaling EINT 7 0 For Wake Up The S3C44BOX can be woken from SL IDLE mode or STOP mode only if the following conditions are met a Level signal H or L or edge signal rising or falling or both is asserted on EINTn input pin b EINTn pin has to be configured as EINT in PCONG register It is important to configure the EINTn in the PCONG register as an external interrupt pins For wake up we need H L level or rising falling edge or both edge signals on EINTn pin Just after wake up the corresponding EINTn pin will not be used for wake up This means that these pins can be ELECTRONICS 5 11 CLOCK amp POWER MANAGEMENT 53 44 RISC MICROPROCESSOR used as external interrupt request pins again Entering IDLE Mode If CLKCON 2 is set to 1 to enter the IDLE mode S3C44BOX will enter into IDLE mode after some delay until when the power control logic receives ACK signal from the CPU wrapper PLL On Off The PLL can only be turned off for power saving in slow mode If PLL is turned off in any other mode MCU operation is not guaranteed When the processor is in SLOW mode and tries to change its state into other state requiring that PLL be turned on then SLOW_BIT should be clear to move
292. sed to store status information Register 14 is used as the subroutine link register This receives a copy of R15 when a Branch and Link BL instruction is executed At all other times it may be treated as a general purpose register The corresponding banked registers R14 svc R14 R14 fiq R14 abt and R14 und are similarly used to hold the return values of R15 when interrupts and exceptions arise or when Branch and Link instructions are executed within interrupt or exception routines Register 15 holds the Program Counter PC In ARM state bits 1 0 of R15 are zero and bits 31 2 contain the PC In THUMB state bit 0 is zero and bits 31 1 contain the PC Register 16 is the CPSR Current Program Status Register This contains condition code flags and the current mode bits mode has seven banked registers mapped to R8 14 R8 fiq R14 fig In ARM state many handlers do not need to save any registers User IRQ Supervisor Abort and Undefined each have two banked registers mapped to R13 and R14 allowing each of these modes to have a private stack pointer and link registers ELECTRONICS 2 3 PROGRAMMER S MODEL 53 44 RISC MICROPROCESSOR ARM State General Registers and Program Counter System amp User FIQ Supervisor Abort Undefined 23 1 31 0 1 0 5 100 R1 R2 R3 R4 R5 R7 JJ R10 E E 15 PC ___815 PC RO __22 RS Ra RS Re R7 DXR8 R
293. servation value for Timer 4 0x00000000 observation register ELECTRENICS 9 19 PWM TIMER 53 44 RISC MICROPROCESSOR TIMER 5 COUNT BUFFER REGISTER 5 TCNTBS 0 01050048 Timer 5 count buffer register 0x00000000 TCNTB5 Description Initial State Timer 5 count buffer 15 0 Setting count buffer value for Timer 5 0x00000000 register TIMER 5 COUNT OBSERVATION REGISTER 5 5 Ox01D5004C Timer 5 count observation register 0x00000000 observation register Timer 5 15 0 Setting count observation value for Timer 5 0x00000000 9 20 ELECTRONICS 53 44 RISC MICROPROCESSOR UART UART OVERVIEW S3C44BOX UART Universal Asynchronous Receiver and Transmitter unit provides two independent asynchronous serial I O SIO ports each of which can operate in interrupt based or DMA based mode In other words UART can generate an interrupt or DMA request to transfer data between CPU and UART It can support bit rates of up to 115 2K bps Each UART channel contains two 16 byte FIFOs for receive and transmit The S3C44BOX UART includes programmable baud rates infra red IR transmit receive one or two stop bit insertion 5 bit 6 bit 7 bit or 8 bit data width and parity checking Each UART contains a baud rate generator transmitter receiver and control unit as shown in Figure10 1 The baud rate generator can be clocked by MCLK The transmitter and the receiver contain 16
294. set 2 This bit is auto cleared after resetting FIFO 0 Normal 12 Tx FIFO reset Rx FIFO Reset 1 This bit is auto cleared after resetting FIFO 0 Normal 1 Rx FIFO reset FIFO Enable 10 0 FIFO disable 1 FIFO mode NOTE When the UART does not reach the FIFO trigger level and does not receive data during 3 word time in DMA receive mode with FIFO the Rx interrupt will be generated receive time out and the users should check the FIFO status and read out the rest UART MODEM CONTROL REGISTER There are two UART MODEM control registers UMCONO UMCON1 in the UART block UMCONO 0x01D0000C UART channel 0 Modem control register UMCON1 0x01D0400C UART channel 1 Modem control register AFC Auto Flow 4 0 Disable 1 Enable Control Request to Send If AFC bit is enabled this value will be ignored In this case the 53 44 will control nRTS automatically If AFC bit is disabled nRTS must be controlled by S W 0 level Inactivate nRTS 1 level Activate nRTS 10 12 ELECTRONICS 53 44 RISC MICROPROCESSOR UART UART TX RX STATUS REGISTER There are two UART Tx Rx status registers UTRSTATO and UTRSTAT1 in the UART block UTRSTATO 0x01D00010 oR UART channel 0 Tx Rx status register UTRSTAT1 0 01004010 R UART channel 1 Tx Rx status register Transmit shifter This bit is automatically set to 1 when the transmit shift register empty has no valid data to transmit and the transmit shift
295. should return by executing the following irrespective of the state ARM or Thumb MOV PC R14 svc This restores the PC and CPSR and returns to the instruction following the SWI NOTE nFIQ nIRQ ISYNC LOCK BIGEND and ABORT pins exist only in the ARM7TDMI CPU core Undefined Instruction When ARM7TDMI comes across an instruction which it cannot handle it takes the undefined instruction trap This mechanism may be used to extend either the THUMB or ARM instruction set by software emulation After emulating the failed instruction the trap handler should execute the following irrespective of the state ARM or Thumb MOVS PC R14 und This restores the CPSR and returns to the instruction following the undefined instruction Exception Vectors The following table shows the exception vector addresses Table 2 3 Exception Vectors Exeon Abort prefetch Abort data _______ ELECTRONICS 2 13 PROGRAMMER S MODEL 53 44 RISC MICROPROCESSOR Exception Priorites When multiple exceptions arise at the same time a fixed priority system determines the order in which they are handled Highest priority Reset Data abort FIQ IRQ Prefetch abort Lowest priority 6 Undefined Instruction Software interrupt Not All Exceptions Can Occur at Once Undefined Instruction and Software Interrupt are mutually exclusive since they each
296. stest access time Also the ISR in SRAM is very efficient because most ISR codes may cause cache miss The bus arbitration logic can determine the priorities of bus masters The bus arbitration logic supports a round robin priority mode and a fixed priority mode Also The priorities among LCD_DMA BDMA ZDMA nBREQ external bus masters can be changed by S W ELECTRENICS 6 1 CPU WRAPPER amp BUS PRIORITIES 53 44 RISC MICROPROCESSOR 2 N i N 5 E 7 43210 Decoder Height 128 1110 o lt lt Figure 6 1 Cache Memory Configuration 6 2 ELECTRONICS 53 44 RISC MICROPROCESSOR CPU WRAPPER amp BUS PRIORITIES CACHE OPERATION Cache Organization 53 44 cache has 8KB or 4KB cache memory four Tag RAMs LRU memory The internal unified instructions data cache adopts a four way set associative architecture with 4 word 16 bytes line size It has a write through policy to keep data coherency It has an LRU Least Recently Used algorithm to raise the hit ratio Cache Replace Operation After a system is initialized the value of CS is set to 0000 signifying that the contents of set 0 set1 set2 and set 3 cache memories are invalid
297. t the same time as R15 is loaded STM with R15 in Transfer List and S Bit Set User Bank Transfer The registers transferred are taken from the User bank rather than the bank corresponding to the current mode This is useful for saving the user state on process switches Base write back should not be used when this mechanism is employed R15 not in List and S Bit Set User Bank Transfer For both LDM and STM instructions the User bank registers are transferred rather than the register bank corresponding to the current mode This is useful for saving the user state on process switches Base write back should not be used when this mechanism is employed When the instruction is LDM care must be taken not to read from a banked register during the following cycle inserting a dummy instruction such as MOV RO RO after the LDM will ensure safety USE OF R15 AS THE BASE R15 should not be used as the base register in any LDM or STM instruction ELECTRONICS 3 43 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR INCLUSION OF THE BASE IN THE REGISTER LIST When write back is specified the base is written back at the end of the second cycle the instruction During a STM the first register is written out at the start of the second cycle A STM which includes storing the base with the base as the first register to be stored will therefore store the unchanged value whereas with the base second or later in the transfer order will store
298. t these unused bits are not altered Also your program should not rely on them containing specific values since in future processors they may read as one or Zero ELECTRONICS 2 9 PROGRAMMER S MODEL 53 44 RISC MICROPROCESSOR EXCEPTIONS Exceptions arise whenever the normal flow of a program has to be halted temporarily for example to service an interrupt from a peripheral Before an exception can be handled the current processor state must be preserved so that the original program can resume when the handler routine has finished It is possible for several exceptions to arise at the same time If this happens they are dealt with in a fixed order See Exception Priorities on page 2 14 Action on Entering an Exception When handling an exception the ARM7TDMI 1 Preserves the address of the next instruction in the appropriate Link Register If the exception has been entered from ARM state then the address of the next instruction is copied into the Link Register that is current PC 4 or PC 8 depending on the exception See Table 2 2 on for details If the exception has been entered from THUMB state then the value written into the Link Register is the current PC offset by a value such that the program resumes from the correct place on return from the exception This means that the exception handler need not determine which state the exception was entered from For example in the case of SWI MOVS R14 svc will always
299. ta Abort trap will be taken It is up to the system software to resolve the cause of the problem then the instruction can be restarted and the original program continued INSTRUCTION CYCLE TIMES Normal LDR instructions take 1S 1N 11 and LDR PC take 2S 2N 11 incremental cycles where S N and are defined as sequential S cycle non sequential N cycle and internal I cycle respectively STR instructions take 2N incremental cycles to execute ELECTRONICS 3 31 ARM INSTRUCTION SET ASSEMBLER SYNTAX 53 44 RISC MICROPROCESSOR lt LDR STR gt cond B T Rd lt Address gt where LDR STR cond B T Rd Rn and Rm lt Address gt can be 1 lt shift gt 3 32 Load from memory into a register Store from a register into memory Two character condition mnemonic See Table 3 2 If B is present then byte transfer otherwise word transfer If T is present the W bit will be set in a post indexed instruction forcing non privileged mode for the transfer cycle T is not allowed when a pre indexed addressing mode is specified or implied An expression evaluating to a valid register number Expressions evaluating to a register number If Rn is R15 then the assembler will subtract 8 from the offset value to allow for ARM7TDMI pipelining In this case base write back should not be specified An expression which generates an address The assembler will attempt to generate an instruction using the
300. tate since the last time it was read by CPU Refer to Fig 10 7 0 Has not changed 1 Has changed Gu mew 1212 Clear to Send 0 CTS signal is not activated nCTS pin is high 1 CTS signal is activated nCTS pin is low Delta CTS Read UMSTATn Figure 10 8 nCTS and Delta CTS Timing diagram 10 16 ELECTRENICE 53 44 RISC MICROPROCESSOR UART UART TRANSMIT HOLDING BUFFER REGISTER amp FIFO REGISTER UTXHn has an 8 bit data for transmission data W W UTXHO 0x01D00020 L UART channel 0 transmit holding register 0x01D00023 B by byte UTXH1 0x01D04020 L UART channel 1 transmit holding register 0x01D04023 B by byte UTXHn Bit Description Initial State TXDATAn 7 0 Transmit data for UARTn NOTE L When the endian mode is Little endian B When the endian mode is Big endian UART RECEIVE HOLDING BUFFER REGISTER amp FIFO REGISTER URXHn has 8 bit data for received data Register Description Reset Value R 0x01D00024 L UART channel 0 receive buffer register 0x01D00027 B byte URXH1 0x01D04024 L R UART channel 1 receive buffer register 0x01D04027 B by byte ae Yi RXDATAn 7 0 Receive data for UARTn NOTE When an overrun error occurs the URXHn must be read If the next received data will also make overrun error even though the overrun bit of USTATn had been cleared ELECTRONICS 10 17 UART
301. ternal DMA Timing Demand On The Fly mode 11 19 34 ELECTRENICE 53 44 RISC MICROPROCESSOR ELECTRICAL DATA XnDREQ XnDACK Figure 19 47 External DMA Timing Demand Unit transfer Block mode 1 XnDREQ XnDACK Figure 19 48 External DMA Timing Demand Unit transfer Block mode Il ELECTRENICS 19 35 ELECTRICAL DATA 53 44 RISC MICROPROCESSOR XnDREQ XnDACK Figure 19 49 External DMA Timing Whole Unit transfer Block mode XnDREQ XnDACK tACCR Figure 19 50 External DMA Timing Whole On The Fly mode 19 36 ELECTRONICS 53 44 RISC MICROPROCESSOR ELECTRICAL DATA tF2CDLY VCLKCY tc2DDLY 4 Figure 19 51 LCD Controller Timing tSCLHIGH tSCLLOW IICSCL tSTOPH tSTARTS IICSDA Figure 19 52 Interface Timing ELECTRENICS 19 37 ELECTRICAL DATA 53 44 RISC MICROPROCESSOR EXTCLK tRDYIS tRDYIH gt lt lt nXWAIT tRDYIW SIOCKO gt tSIOTXD 4 SIOTXD Figure 19 53 SIO Interface Transmit Timing Rising edge clock CODECLK IISCLK IISLRCK gt LRCK yt gt gt tSDIS Figure 19 54 SIO Interface Transmit Timing Rising edge clock 19 38 ELECTRONICS 53 44 RISC MICROPROCESSOR ELECTRICAL DATA Table 19 6 Clock Timing Constants VDDP 3 3V 2 5V Ta 25 C PLCAP 70 max min typ 30 Parameter External c
302. ternal interrupt EINT4 5 6 7 requests are ORed to provide a single interrupt source to the interrupt controller and two UART error interrupts UERROR0O 1 are the same configuration Sources ____ ____ Waster Group rc arm ert wr ane NOTE EINT4 EINT5 EINT6 EINT7 share the same interrupt request line Therefore the ISR interrupt service routine will discriminate these four interrupt sources by reading the EXTINPND 3 0 register EXTINPND 3 0 must be cleared by writing a 1 in the ISR after the corresponding ISR has been completed ELECTRONICS 11 3 INTERRUPT CONTROLLER 53 44 RISC MICROPROCESSOR INTERRUPT PRIORITY GENERATING BLOCK There is the interrupt priority generating block only for IRQ interrupt request If the vectored mode is used and an interrupt source is configured as ISR in INTMOD register the interrupt will be processed by the interrupt priority generating block The priority generating block consists of five units 1 master unit and 4 slave units Each slave priority generating unit manages six interrupt sources The master priority generating unit manages 4 slave units and 2 interrupt sources Each slave unit has 4 programmable priority sources sGn and 2 fixed priotiry sources sGKn The priority among the 4 sources in each slave unit is programmable The other 2 fixed priorities have the lowest priority among the 6 sources
303. tes the CMD field as 11 in the register of ZDCONO 1 In this case the register content of Z B DISRCO Z B DIDESO and Z B DICNTO will be loaded into the registers ZIB DCSRCO Z B DCDESO and 2 8 immediately ELECTRONICS 7 11 DMA 53 44 RISC MICROPROCESSOR DMA SPECIAL REGISTERS ZDMA CONTROL REGISTER ZDCONn ZDCONO 0 01 80000 ZDMA 0 Control Register ZDCON1 0x01E80020 ZDMA 1 Control Register va STE 5 4 Status of DMA channel Read only 00 Ready 01 Not TC yet 10 Terminal Count 11 Before the DMA counter decreases from the initial counter value STE is still in the ready state QDS 3 2 Disable Enable External DMA request nXDREQ 00 Enable other Disable CMD 1 0 Software commands 00 No command After writing 01 10 11 CMD bit is cleared automatically is available 01 Starts DMA operation by S W without nXDREQ S W start function can be used only in the whole mode As DMA is in the whole mode the DMA will operate until the counter is 0 If nKDREQ is used this command must not be issued 10 Pauses DMA operation But nXDREQ is still available 11 Cancels DMA operation NOTE If users start the operation by CMD 01b the DREQ protocol must be whole service mode 7 12 ELECTRONICS 53 44 RISC MICROPROCESSOR DMA ZDMAO INITIAL SOURCE DESTINATION ADDRESS AND COUNT REGISTERS ZDISRCO ZDIDESO ZDICNTO ZDISRCO 0x01E80004 ZDMA 0 initi
304. the VLINE pulse s high level width by counting the number of the system clock 00 4 clock 01 8 clock 10 12 clock 11 16 clock WDLY These bits determine the delay between VLINE and VCLK by counting the number of the system clock 00 4clock 01 8 clock 10 12 clock 11 16 clock MMODE 7 This bit determines the toggle rate of the VM 0 Each Frame 1 The rate defined by the MVAL DISMODE 6 5 These bits select the display mode 00 4 bit dual scan display mode 01 4 bit single scan display mode 10 8 bit single scan display mode 11 Not used INVCLK 4 This bit controls the polarity of the VCLK active edge 0 The video data is fetched at VCLK falling edge 1 The video data is fetched at VCLK rising edge INVLINE 3 This bit indicates the line pulse polarity 0 normal 1 inverted INVFRAME 2 This bit indicates the frame pulse polarity 0 normal 1 inverted INVVD 1 This bit indicates the video data VD 7 0 polarity 0 Normal 1 VD 7 0 output is inverted ENVID LCD video output and the logic enable disable 0 Disable the video output and the logic The LCD FIFO is cleared 1 Enable the video output and the logic MEE 12 16 ELECTRONICS 53 44 RISC MICROPROCESSOR LCD CONTROLLER LCD Control 2 Register LCDCON2 0x01F00004 LCD control 2 register 0x00000000 LINEBLANK 31 21 These bits indicate the blank time in one horizontal line duration 0x000 time These bits adjust the rate o
305. the instruction is not set the result of the operation is placed in R15 and the CPSR is unaffected When Rad is R15 and the S flag is set the result of the operation is placed in R15 and the SPSR corresponding to the current mode is moved to the CPSR This allows state changes which atomically restore both PC and CPSR This form of instruction should not be used in User mode USING R15 AS AN OPERANDY If R15 the PC is used as an operand in a data processing instruction the register is used directly The PC value will be the address of the instruction plus 8 or 12 bytes due to instruction prefetching If the shift amount is specified in the instruction the PC will be 8 bytes ahead If a register is used to specify the shift amount the PC will be 12 bytes ahead TEQ TST CMP AND CMN OPCODES NOTE TEQ TST CMP and CMN do not write the result of their operation but do set flags in the CPSR An assembler should always set the S flag for these instructions even if this is not specified in the mnemonic The TEQP form of the TEQ instruction used in earlier ARM processors must not be used the PSR transfer operations should be used instead The action of TEQP in the ARM7TDMI is to move SPSR mode to the CPSR if the processor is in a privileged mode and to do nothing if in User mode INSTRUCTION CYCLE TIMES Data Processing instructions vary in the number of incremental cycles taken as follows Table 3 4 Incremental Cycle Times Data
306. the pin states at the external bus which is used by the other bus master The STOP shows the pin states when S3C44BOX is in STOP mode 3 mark indicates the unchanged pin state at STOP mode or Bus released mode IICSDA IICSCL pins are open drain type 5 means analog input output gt 1 16 ELECTRONICS 53 44 RISC MICROPROCESSOR PRODUCT OVERVIEW Oscillator cell with enable and feedback resistor phbsu50ct12sm bi directional pad CMOS schmitt trigger 50 pull up resistor with control tri state lo 12mA phbsu50ct8sm bi directional pad CMOS schmitt trigger 50 pull up resistor with control tri state lo 8mA phbsu50cd4sm bi directional pad CMOS schmitt trigger pull up resistor with control tri state lo 4mA 1 17 ELECTRONICS PRODUCT OVERVIEW 53 44 RISC MICROPROCESSOR SIGNAL DESCRIPTIONS Table 1 3 53 44 Signal Descriptions swa BUS CONTROLLER 1 0 ON 1 0 sets 53 44 in the TEST mode which is used only at fabrication Also it determines the bus width of nGCSO The logic level is determined by the pull up down resistor during the RESET cycle 00 8 bit 01 16 bit 10 32 bit 11 Test mode ADDR 24 0 ADDR 24 0 Address Bus outputs the memory address of the corresponding bank DATA 31 0 DATA 31 0 Data Bus inputs data during memory read and outputs data during memory write The bus width is programmable among 8 16 32 bit nGCS 7 0 nGCS
307. the register list should not be empty Whenever R15 is stored to memory the stored value is the address of the STM instruction plus 12 28 27 25 24 23 22 21 20 19 16 15 0 Lus ferme 19 16 Base Register 20 Load Store Bit 0 Store to memory 1 Load from memory 21 Write back Bit 0 No write back 1 Write address into base 22 PSR amp Force User Bit 0 Do not load PSR or user mode 1 Load PSR or force user mode 23 Up Down Bit 0 Down subtract offset from base 1 Up add offset to base 24 Pre Post Indexing Bit 0 Post add offset after transfer 1 Pre add offset bofore transfer 31 28 Condition Field Figure 3 18 Block Data Transfer Instructions 3 40 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET ADDRESSING MODES The transfer addresses are determined by the contents of the base register Rn the pre post bit P and the up down bit U The registers are transferred in the order lowest to highest so R15 if in the list will always be transferred last The lowest register also gets transferred to from the lowest memory address By way of illustration consider the transfer of R1 R5 and R7 in the case where Rn 0x1000 and write back of the modified base is required W 1 Figure 3 19 22 show the sequence of register transfers the addresses used and the value of Rn after the instruction has completed In all cases had write back of the modified bas
308. tial Destination Address 1 EU Destination Address BDMA 1 Transfer Count BDMA 1 1 Current Source Address Source Address BDMA 1 aa Destination Address BDMA 1 1 Current Transfer Count Transfer Count 1 28 ELECTRONICS 53 44 RISC MICROPROCESSOR PRODUCT OVERVIEW IMPORTANT NOTES ABOUT S3C44B0X SPECIAL REGISTERS 1 In the little endian mode L endian address must be used In the big endian mode endian address must be used The special registers have to be accessed by the recommended access unit All registers except ADC registers RTC registers and UART registers must be read written in word unit 32bit at little big endian 4 lt is very important that the ADC registers RTC registers and UART registers be read written by the specified access unit and the specified address Moreover one must carefully consider which endian mode is used 5 W 32 bit register which must be accessed by LDR STR or int type pointer int HW 16 bit register which must be accessed by LDRH STRH or short int type pointer short int B 8 bit register which must be accessed by LDRB STRB or char type pointer char ELECTRONICS 1 29 53 44 RISC MICROPROCESSOR PROGRAMMER S MODEL PROGRAMMER S MODEL OVERVIEW 3 44 has been developed using the advanced ARM7TDMI core which has been designed by Advanced RISC Machines Ltd PROCESSOR OPERATING STATES From the programmer
309. tion occur simultaneously The DMA acknowledge signal notifies the external device to read or write Simultaneously the memory controller should generate Read related or Write related control signals to the external memory If the external device can support the on the fly mode can read write the data by DMA acknowledge the data transfer rates will be doubled During the on the fly transfer cycle 53 44 data bus will be in Hi z state Figure 7 11 shows the example of the on the fly transfer mode with the whole service mode nXDREQ 1 nXDACK 1 Co i The other service Figure 7 11 On the fly Transfer Mode with Whole Transfer Mode 7 10 ELECTHDNICS 53 44 RISC MICROPROCESSOR DMA DMA REQUEST SOURCE SELECTION In ZDMA S W or H W produces the nXDREQ external DMA request signal which is the DMA request source The S W trigger can be done by writing the CMD field as 01 in ZDCONO 1 register i e the start of DMA Before the start of DMA the DMA related parameters such as source address destination address transfer count and so on should be configured Based on these configuration the DMA operation will start when the CMD field is written as 01 In S W trigger the DMA operations will continue as long as the burst mastership is allocated to the DMA master and as long as the DMA transfer count or TC Terminal Count reaches zero i e the completion of DMA operation If the higher bus master a
310. to bypass capacitors respectively because of voltage level stability AIN 7 0 MCLK ADCDAT Data Bus Figure 13 1 A D Converter Block Diagram FUNCTION DESCRIPTIONS SAR Successive Approximation Register A D Converter Operation A SAR type A D converter basically consists of the comparator D A converter and SAR logic At the beginning of the conversion the MSB is switched ON and the analog input signal is compared the reference signal of D A converter Because the A D converter was designed with differential architecture D A converter generates the differential reference signal internally and the two difference signals one signal is the difference between analog input and positive reference signal the other is between the analog common voltage VCOM and negative reference signal are delivered to comparator The comparator then compares the analog input with the reference signal differentially When the input signal is larger than the reference then MSB remains ON and the next bit is switched ON and a comparison will be performed A bit by bit operation is in this system bring the reference signal within 1 LSB of the time discrete input signal A D Conversion Time When the system clock frequency is 66MHz and the prescaler value is 20 total 10 bit conversion time is as follows 66 MHz 2 20 1 16 at least 16 cycle by 10 bit operation 98 2 KHz 10 2 us NOTE Because this A D converter has no sample and hold circuit analog
311. to fred if R1 was zero otherwise continue Continue to next instruction Call subroutine at computed address Add 1 to register 1 setting CPSR flags on the result then call subroutine if the C flag is clear which will be the case unless R1 held OxFFFFFFFF ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET DATA PROCESSING The data processing instruction is only executed if the condition is true The conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 4 28 27 26 25 24 21 20 19 16 15 12 11 0 H 15 12 Destination register 0 Branch 1 Branch with link 19 16 1st operand register 0 Branch 1 Branch with link 20 Set condition codes 0 Do not after condition codes 1 Set condition codes 24 21 Operation codes 0000 AND Rd 1 AND 0001 EOR Rd Op1 EOR Op2 0010 SUB Rd Op1 Op2 0011 RSB Rd Op2 Op1 0100 ADD Rd 0101 ADC Rd 1 2 0110 SBC Rd 1 2 1 0111 RSC Rd 2 1 1 1000 TST set condition codes on Op1 AND Op2 1001 TEO set condition codes on OP1 EOR Op2 1010 CMP set condition codes on Op1 Op2 1011 SMN set condition codes on 1 2 1100 ORR Rd Op1 OR Op2 1101 MOV Rd 1110 BIC Rd Op1 AND NOT Op2 1111 MVN Rd 25 Immediate operand 0 Operand 2 is a register 1 Oper
312. trol Logic output the Fin clock instead of the Fpllo clock from Fout during 16 Fin clocks After 16 Fin clocks the Fout is stopped and 53 44 enters into STOP mode completely The latency time from command issue of the power down by STOP mode to actual entrance into power down mode is calculated as follows Power down latency time Input clock period crystal oscillator clock or external clock 16 If 53 44 is in the SLOW mode the S3C44BOX enters into STOP mode immediately because the frequency of the clock in slow mode is lower than Fin The S3C44BOX can exit from STOP mode by external interrupts or RTC alarm interrupt During the wake up sequences the crystal oscillator and PLL may begin to operate The lock time is also needed to stabilize Fout The lock time is inserted automatically and guaranteed by power management logic During this lock time the clock is not supplied Just after wake up sequences wake up interrupt alarm or external interrupt is requested ELECTRONICS 5 7 CLOCK amp POWER MANAGEMENT 53 44 RISC MICROPROCESSOR Fin X tal Clock Disable VCO Output OSC clocks Taror mode is initiated Figure 5 6 Entering STOP Mode and Exiting STOP Mode Wake up IMPORTANT NOTES Before entering STOP mode the following 6 items must be obeyed 1 DRAM has to be in self refresh mode during STOP mode to retain valid memory data 2 LCD displa
313. trols MCLK into IIS block 0 Disable 1 Enable UART1 UARTO 1 If BDMA is turned off the peripherals in the peripheral bus may not be accessed Controls MCLK into LCDC block 0 Disable 1 Enable Controls MCLK into SIO block 0 Disable 1 Enable ZDMAO 1 Controls MCLK into ZDMA block 0 Disable 1 Enable Controls MCLK into PWMTIMER block 0 Disable 1 Enable Enters IDLE mode This bit can t be cleared automatically 0 Disable 1 Transition to IDLE SL IDLE mode SL IDLE mode option This bit can t be cleared automatically 0 Disable 1 SL_IDLE mode To enter SL IDLE mode CLKCON register has to be 0x46 Enters STOP mode This bit can t be cleared automatically 0 Disable 1 Transition to STOP mode PWMTIMER IDLE BIT SL IDLE STOP BIT V ELECTRONICS CLOCK amp POWER MANAGEMENT 53 44 RISC MICROPROCESSOR CLOCK SLOW CONTROL REGISTER CLKSLOW CLKSLOW 0x01D80008 Slow clock control register 0x9 000 0x0 PLL OFF 5 0 PLL is turned on PLL is turned on only when SLOW BIT is 1 After PLL stabilization time minimum 150uS SLOW BIT may be cleared to 0 1 PLL is turned off PLL is turned off only when SLOW BIT is 1 SLOW BIT 4 0 Fout Fpllo PLL output 1 Fout Fin 2 x SLOW VAL SLOW VAL gt 0 Fout Fin SLOW VAL 0 SLOW_VAL 3 0 The divider value for the slow clock when SLOW_BIT is on 0
314. tructions is influenced by the BIGEND control signal of ARM7TDMI core The two possible configurations are described below Little Endian Configuration A byte load LDRB expects the data on data bus inputs 7 through 0 if the supplied address is on a word boundary on data bus inputs 15 through 8 if it is a word address plus one byte and so on The selected byte is placed in the bottom 8 bits of the destination register and the remaining bits of the register are filled with zeros Please see Figure 2 2 A byte store STRB repeats the bottom 8 bits of the source register four times across data bus outputs 31 through 0 The external memory system should activate the appropriate byte subsystem to store the data A word load LDR will normally use a word aligned address However an address offset from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 0 to 7 This means that half words accessed at offsets 0 and 2 from the word boundary will be correctly loaded into bits 0 through 15 of the register Two shift operations are then required to clear or to sign extend the upper 16 bits store STR should generate word aligned address The word presented to the data bus is not affected if the address is not word aligned That is bit 31 of the register being stored always appears on data bus output 31 ELECTRONICS 3 29 ARM INSTRUCTION SET 53 44 RISC MICROPROCESSOR mem
315. try point EntryTable Addresses of supervisor routines DCD ZeroRin DCD ReadCRin DCD WritelRtn Zero EQU 0 ReadC EQU 256 Writel EQU 512 Supervisor SWI has routine required in bits 8 23 and data if any in bits 0 7 Assumes points to a suitable stack STMFD R13 RO R2 R14 Save work registers and return address LDR RO R14 4 Get SWI instruction BIC R0 R0 Z0xFF000000 Clear top 8 bits MOV R1 RO LSR 8 Get routine offset ADR R2 EntryTable Get start address of entry table LDR R15 R2 R1 LSL 2 Branch to appropriate routine WritelRtn Enter with character in RO bits 0 7 LDMFD R13 RO R2 R15 Restore workspace and return restoring processor mode and flags 3 50 ELECTRONICS 53 44 RISC MICROPROCESSOR ARM INSTRUCTION SET COPROCESSOR DATA OPERATIONS CDP The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 25 This class of instruction is used to tell a coprocessor to perform some internal operation No result is communicated back to ARM7TDMI and it will not wait for the operation to complete The coprocessor could contain a queue of such instructions awaiting execution and their execution can overlap other activity allowing the coprocessor and ARM7TDMI to perform independent tasks in parallel COPROCESSOR INSTRUCTIONS The 53 44 unlike some other ARM based processors does not h
316. ts of BDICNT register as following steps 1 Set BDICNT register with disabled En bit 2 Set EN bit enable 19 0 Transfer count for BDMA1 The transfer count must be right 0x00000 value For example if DST is word ICNT must be 4n If 1 byte is transferred the ICNT will be decreased by 1 If 1 half word is transferred the ICNT will be decreased by 2 If 1 word is transferred the ICNT will be decreased by 4 7 20 ELECTRDNICS 53 44 RISC MICROPROCESSOR PORTS I O PORTS OVERVIEW 53 44 has 71 multi functional input output port pins There are seven ports Two 9 bit input output ports Port E and F Two 8 bit input output ports Port D and G One 16 bit input output port Port C One 10 bit output port Port A One 11 bit output port Port B Each port can be easily configured by software to meet various system configuration and design requirements The function of each pin to be used must be defined before starting the main program If the multiplexed functions on a not used the can be configured as ports Before pin configurations the initial pin states are configured elegantly to avoid some problems ELECTRENICS 8 1 PORTS 3C44B0X RISC MICROPROCESSOR Table 8 1 53 44 Port Configuration Overview Selectable Pin functions Functions e 00 Lm p mee 8 2 ELECTRONICS
317. ts the receiver can handle nor does the receiver need to know how many bits are being transmitted When the system word length is greater than the transmitter word length the word is truncated least significant data bits are set to 0 for data transmission If the receiver is sent more bits than its word length the bits after the LSB are ignored On the other hand if the receiver is sent fewer bits than its word length the missing bits are set to zero internally And so the MSB has a fixed position whereas the position of the LSB depends on the word length The transmitter always sends the MSB of the next word at one clock period after the IISLRCK change Serial data sent by the transmitter may be synchronized with either the trailing HIGH to LOW or the leading LOW to HIGH edge of the clock signal However the serial data must be latched into the receiver on the leading edge of the serial clock signal and so there are some restrictions when transmitting data that is synchronized with the leading edge The LR channel select line indicates the channel being transmitted IISLRCK may change either on a trailing or leading edge of the serial clock but it does not need to be symmetrical In the slave this signal is latched on the leading edge of the clock signal The IISLRCK line changes one clock period before the MSB is transmitted This allows the slave transmitter to derive synchronous timing of the serial data that will be set up for transm
318. tus of DMA channel Read only 00 Ready 01 Not TC yet 10 Terminal Count 11 Before the DMA counter decreases from a initial counter value STE is still the ready state QDS 3 2 Disable Enable External Internal DMA request UARTn SIO IIS Timer 00 Enable Other Disable CMD 1 0 Software commands 00 No command After writing 01 10 11 CMD bits are cleared automatically 01 Reserved 10 Reserved 11 Cancels DMA operation 7 16 ELECTRDNICS S3C44B0X RISC MICROPROCESSOR DMA BDMAO INITIAL SRC DST ADDRESS AND COUNT REGISTERS BDISRCO BDIDESO BDICNTO BDISRCO 0x01F80004 BDMA O initial source address Register 0x00000000 BDIDESO 0x01F80008 BDMA O initial destination address Register 0x00000000 BDICNTO 0 01 8000 BDMA 0 initial count register 0x00000000 BDMAO CURRENT SRC DST ADDRESS AND COUNT REGISTERS BDCSRCO BDCDESO BDCCNTO BOMA O curent source address Register R BOMA curent destination address Regier oro0000000 R BOAO curent count regier NOTE These registers are read only BDMA1 INITIAL SRC DST ADDRESS AND COUNT REGISTERS BDISRC1 BDIDES1 BDICNT1 BDMA1 CURRENT SRC DST ADDRESS AND COUNT REGISTERS BDCSRC1 BDCDES1 BDCCNT1 BDCSRC1 0x01F80030 BDMA 1 current source address Register 0x00000000 BDCDES 1 0x01F80034 oR BDMA 1 current destin
319. ue as TCNTn 4 can be inverted by the inverter on off bit in TCON The inverter removes the additional circuit to adjust the output level 9 8 ELECTRENICE 53 44 RISC MICROPROCESSOR PWM TIMER DEAD ZONE GENERATOR The dead zone is for the PWM control in a power device This feature is used to insert the time gap between a turn off of a switching device and a turn on of another switching device This time gap prohibits the two switching devices turning on simultaneously even for a very short time TOUTO is the PWM output nTOUTO is the inversion of the TOUTO If the dead zone is enabled the output wave form TOUTO and nTOUTO will be TOUTO DZ and nTOUTO DZ respectively ATOUTO DZ is routed to the TOUT1 pin In the dead zone interval TOUTO DZ and nTOUTO DZ can never be turned on simultaneously Deadzone Interval TOUTO DZ Figure 9 7 The Wave Form When a Dead Zone Feature is Enabled gt lt ELECTRENICS 9 9 PWM TIMER 53 44 RISC MICROPROCESSOR DMA REQUEST MODE The PWM timer can generate a DMA request at every specific times The timer keeps DMA request signal low until the timer receives the ACK signal When the timer receives the ACK signal it makes the request signal inactive One of 6 timers can generate a DMA request The timer that generates the DMA request is determined by setting DMA mode bits in TCFG1 register If a timer is configured as DMA request mode the timer does
320. unction of the watchdog timer Reserved 1 Reserved This bit must be 0 in normal operation ELECTRENICS 15 3 WATCHDOG TIMER S3C44BOX RISC MICROPROCESSOR WATCHDOG TIMER DATA REGISTER WTDAT The watchdog timer data register WTDAT is used to specify the time out duration The content of WTDAT can not be automatically loaded into the timer counter at initial watchdog timer operation However the first time out occurs by using Ox8000 initial value after then the value WTDAT will be automatically reloaded into WTCNT WTDAT 0x01D30004 Watchdog timer data Register 0x8000 Count reload value 15 0 Watchdog timer count value for reload 0x8000 WATCHDOG TIMER COUNT REGISTER WTCNT The watchdog timer count register WTCNT contains the current count values for the watchdog timer during normal operation Note that the content of the watchdog timer data register cannot be automatically loaded into the timer count register when the watchdog timer is enabled initially so the watchdog timer count register must be set to an initial value before enabling it WTCNT 0x01D30008 R W Watchdog timer count Register 0x8000 Count value 15 0 The current count value of the watchdog timer 0x8000 5 4 ELECTRONICS 53 44 RISC MICROPROCESSOR IIC BUS INTERFACE IIC BUS INTERFACE OVERVIEW The 53 44 RISC microprocessor can support multi master serial interface A dedicated serial data line SDA and
321. usly the next DMA write cycle initiates if the DMA request signal is still low at the rising edge of DMA acknowledge But if the DMA request signal is already high at the rising edge of DMA acknowledge the next DMA write cycle will be delayed until anew DMA request signal is activated These two cases are shown in below Figure 7 4 and Figure 7 5 nXDREQ 1 nXDACK 1 DMA Read Cycle DMA Write Cycle Figure 7 4 Single Step Mode Case 1 nXDREQ 1 nXDACK 1 DMA Read Cycle DMA Write Cycle Figure 7 5 Single Step Mode Case 2 ELECTRONICS 7 5 DMA 53 44 RISC MICROPROCESSOR Whole Service Mode The whole service mode means that the specified number of DMA operations i e number of DMA operations based on transfer count will be initiated by a single activation of DMA Request and will be proceeded without further activations of DMA requests The figure below shows how the whole service mode proceeds The nXDACK signal will be active until the end of the whole DMA operations If the number of DMA transfer operation is too large the long bus occupation during the whole service mode of DMA operation may cause problem because the other bus services will not be provided To solve this kind of problem the DMA releases the bus mastership in the whole service mode every time one unit 1byte or 1 half word 1 word is transferred When the DMA releases the bus mastership the other bus masters such as the
322. ustified data format 53 44 RISC MICROPROCESSOR SIO Synchronous Serial I O e 1 SIO with DMA based or interrupt based operation e Programmable baud rates e Supports serial data transmit receive operations 8 bit in SIO Operating Voltage Range e Core 2 5V 3 0 V to 3 6 V Operating Frequency e Up to 66 MHz Package 160 LQFP 160 FBGA ELECTRONICS 53 44 RISC MICROPROCESSOR PRODUCT OVERVIEW BLOCK DIAGRAM Memory Bus Arbiter ROM SRAM Write Buffer DRAM SDRAM Boundary Scan ARM7TDMI LCD LCD ARM7TDMI TAP CPU Core CONT Controller Cache 8K byte Interrupt CONT Power Management ZDMA 2 Ch Clock Generator System Bus Bridge amp Arbitration BDMA 2 Ch GPIO Controller Bus Controller PS Bus Controller UART 0 1 Each B 16byte FIFO Synchronout I O Rear Time Real Time Clock PWM Timer 0 4 5 internal gt 7 5 32 768 Hz Figure 1 1 S3C44B0X Block Diagram ELECTRENICS 1 5 OUTO GPES ICSCL GPFO ICSDA GPF1 1 TOUTS VD6 GPE6 70 1 TOUT2 TCLK GPES 69 L 3 TOUTI TCLK GPE4 72 TOUT4 VD7 GPE7 59 SIOTxD nRTS1 IISLRCK GPF5 55 7 ENDIAN CODECLK GPE8 73 3 5510 6 220 EXTCLK 49 ClKout GPEO 6 ELECTRONICS 53 44 RISC MICROPROCESSOR AING AIN7 AREFT AREFB AVCOM VDDADC XTAL1 EXTAL1 VDDRTC VSSIO VFRAME GPD7 VM G
323. ut WES q LtEX2SCK tSCK2CK Figure 19 4 EXTCLK CLKout SCLK in the case that EXTCLK is used without the PLL ig tEX2CK CLKout NES q LtEX2SCK ig 4 tSCK2CK Figure 19 5 MCLK CLKout SCLK in the case that EXTCLK is used with the PLL nRESET gt lt 3 0 Figure 19 6 Manual Reset OM 3 0 Input Timing 19 6 ELECTRONICS 53 44 RISC MICROPROCESSOR ELECTRICAL DATA PLL can operate after OM 3 2 is latched nRESET Y PLL is configured by S W first time Clock Don Disable VCO is adapted to new clock frequency ML output Jn IL Fout operates by OSC A Fout is new frequency Figure 19 7 Power On Oscillation Setting Timing ELECTRONICS 19 7 ELECTRICAL DATA 53 44 RISC MICROPROCESSOR Clock Disable VCO Output Duc 16 OSC clocks 4 STOP mode is initiated Figure 19 8 STOP Mode Return Oscillation Setting Timing 19 8 ELECTRENICE ELECTRICAL DATA 53 44 RISC MICROPROCESSOR 508 SOH 508 4 Sd SOH 4 4 SOH 4 Sad Figure 19 9 ROM SRAM Burst READ Timing l DW 16bit 0 Tacc 2 Toch 0 Tcahz0 PMC 10b ST 0 Tacs 0 Tcos 19 9 ELECTRONICS 53 44 RISC MICROPROCESSOR ELECTRICAL
324. when the watchdog timer is expired 15 2 ELECTRONICS 53 44 RISC MICROPROCESSOR WATCHDOG TIMER WATCHDOG TIMER SPECIAL REGISTERS WATCHDOG TIMER CONTROL REGISTER WTCON Using the watchdog Timer Control register WTCON you can enable disable the watchdog timer select the clock signal from 4 different sources enable disable interrupts and enable disable the watchdog timer output The watchdog timer is used to resume the S3C44BOX restart on mal function after power on if controller restart is not desired the watchdog timer should be disabled If the user wants to use the normal timer provided by the watchdog timer please enable the interrupt and disable the watchdog timer WTCON 0x01D30000 watchdog timer control Register 0x8021 Prescaler value 15 8 the prescaler value The valid range is from 0 to 28 1 Reserved 7 6 Reserved These two bits must be 00 in normal operation watchdog timer 5 Enable or disable bit of watchdog timer enable disable 0 Disable watchdog timer 1 Enable watchdog timer Clock select 4 3 This two bits determines the clock division factor 00 1 16 01 1 32 10 1 64 11 1 128 Interrupt enable disable Enable or disable bit of the interrupt 0 Disable interrupt generation 1 Enable interrupt generation Reset enable disable Enable or disable bit of watchdog timer output for reset signal 1 asserts reset signal of the S3C44BOX at watchdog time out 0 disables the reset f
325. without PLL The divider ratio is determined by SLOW_VAL in the CLKSLOW control register Fout Fin 2 x SLOW VAL when SLOW VAL is bigger than 0 Fout Fin when SLOW_VAL is 0 In SLOW mode the PLL will be turned off to reduce the PLL power consumption When PLL is turned off in SLOW mode and users change power mode from SLOW mode to NORMAL mode the PLL needs clock stabilization time PLL lock time This PLL stabilization time is automatically inserted by the internal logic with lock time count register The PLL stability time will take 400us after PLL is turn on During PLL lock time the Fout is SLOW clock Users can change the frequency by enabling SLOW mode bit in CLKSLOW register in PLL on state The SLOW clock is generated during SLOW mode The timing diagram is as follow PLL_CLK Slow bit Slow mode enable Slow mode disable PLL off FOUT Divided OSC clock It changes to PLL clock after slow mode off Figure 5 8 The Case that Exit_from_Slow_Mode Command is Issued in PLL on State If users exit from SLOW mode to Normal mode by disabling the SLOW mode bit in the CLKSLOW register after PLL lock time the frequency is changed just after SLOW mode is disabled The timing diagram is as follow S W lock time PLL_CLK Slow bit Slow mode enable Slow mode disable PLL off PLLoff on FOUT Divided OSC clock It changes to PLL clock after slow mode off
326. y must be stopped before entering STOP mode because DRAM is in self refresh mode and LCD can t access DRAM during DRAM self refresh mode If LCD display is turned on SYSTEM will be hanged up 3 The ports of 53 44 0 must be configured properly according to your system to reduce power consumption 4 If STOP mode is issued CPU will enter into STOP mode after 16 X tal clocks If the wake up is asserted for the 14th clocking duration among 16 clocks S3C44BOX will never respond to any wake up signaling It is strongly recommended that any wake up signals should not be asserted until entering into STOP mode completely 5 When S3C44BOX enters STOP mode MCLK should be more than 2 5 times of Fin X tal frequency After wake up in NORMAL mode user can change MCLK to the frequency that user want For example if Fin is 20MHz and a user want MCLK 36MHz the MCLK before entering into STOP mode should be more than 50MHz After wake up and 53 44 returns to NORMAL mode from STOP mode MCLK can be changed from 50MHz to 36MHz by setting PLLCON register 6 When 53 44 enters STOP mode in the level triggered EINT mode the level EINT wake up should not be active If the level EINT wake up is active 53 44 0 should skip entering into STOP mode 5 8 ELECTRONICS 53 44 RISC MICROPROCESSOR CLOCK amp POWER MANAGEMENT SL_IDLE Mode S_LCD Mode In SL_IDLE mode the clock to the basic blocks is stopped Only the LCD controll

1 PRODUCT OVERVIEW

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