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V850E2/ML4 - Renesas Electronics

1. Figure 6 25 Initialization of UARTJO RO1AN1475EJ0100 Rev 1 00 Page 56 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 6 7 21 Initialization of UARTJO Ports Figure 6 26 shows the Initialization of UARTJO Ports uartjO_serial_port_init Peal variable uint32 t set_pdsc2 Setting value for PDSC2 register X PIBC2 amp PORT_BIT_P2_12 PORT_BIT_P2_13 Initialize ports PBDC2 amp PORT_BIT_P2_12 PORT_BIT_P2_13 PM2 PORT BIT P2 12 PORT BIT P2 13 PMC2 amp PORT BIT P2 12 PORT BIT P2 13 PIPC2 amp PORT BIT P2 12 PORT BIT P2 13 Repregram PDSC3 user set pdsc2 PDSC2 amp PORT BIT P2 13 for protection EAT PDSC2 lt set pdsc2 PDSC2 lt set pdsc2 PDSC2 lt set pdsc2 v PU2 amp PORT_BIT_P2_12 P2 12 does not connect internal pull up resistor Set pull up pull down resistors PD2 amp PORT_BIT_P2_12 P2_12 does not connect internal pull down resistor PIS2 PORT_BIT_P2_12 PISE2 amp PORT_BIT_P2_12 Set port functions PISA2 amp PORT_BIT_P2_12 PFC2 PORT_BIT_P2_12 PORT_BIT_P2_13 PFCE2 PORT_BIT_P2_12 PORT_BIT_P2_13 PMC2 PORT_BIT_P2_12 PORT_BIT_P2_13 PM2 PORT_BIT_P2_12 PM2 amp PORT_BIT_P2_13 PIBC2 PORT_BIT_P2_12 y v return Figure 6 26 Initialization of UARTJO Ports RO1AN1475EJ0100 R
2. Vv Initialize hardware hdwinit LL Initialize sbss section _zeroclrw Vv Initialize bss section _zeroclrw Clear program area in RAM _Zeroclrw Copy ROMized data Copy AA Execute main processing main E Figure 6 4 Startup Routine Processing R01AN1475EJ0100 Rev 1 00 Page 35 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 6 7 2 Main Processing Figure 6 5 shows the Main Processing int8_t g_flag_start_flash_reprog Start writing flash memory Global variable y Initialize global variable v Change exception handler address except_handler_addr_set v Initialize INTP1 interrupt intp1 init v Initialize UARTJO uartj0 serial init 7 Checksum judgment check_sum_check g_flag_start_flash_reprog lt false Checksum error Noy v Program in reprogram Program in spare area areaport led sample port led spare lt y Enable interrupts El v Transmit message Output message interrupt switch request uartj0_serial_tx_msg Generate INTP1 interrupt for transition to flash programming event 14 Repeat until switch interrupt is generated Start writing flash memory g_flag_start_flash_reprog false Transmit message Output
3. Execute program for reprogram area or spare area Yy Transmit message Start writing flash memory Start reprogramming after switch interrupt AA Transmit message Vv Erase flash Y Transmit message Generate INTP1 interrupt for transition to flash programming event C Serial communication host D Output message Repeat until switch interrupt is general A w user operation Push interrupt INTP1 switch SW4 Y Message processing gt l Output message gt INTP1 detected AA Message processing Output message Send subroutine code to update program in Intel expanded hex format lt Yy Receive data 7 Write flash memory Y Write checksum data AA Transmit message Infinite loop Message processing Vv Vv Transmit updating program file data Output message Successfully Finish Writing Program Data Please Reset for reset wait Le operation Reset Figure 6 3 Communication Control Sequence RO1AN1475EJ0100 Rev 1 00 Mar 18 2013 RENESAS gt Message processing y Page 22 of 63 V850E2 ML4 6 2 File Composition Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface
4. H FEDF FSL function Reprogram processing interrupt processing etc for functions allocated to RAM Instruction to sene reprogram using flash Exception handler library H FEDF Flash macro service use area H FEDF Figure 6 1 Overview of Reprogramming Flash Memory 1 After cancelling the reset the S romp ROMized section group is copied to the on chip RAM during the cstart asm processing before starting the main function 2 The Intel Extend Hex format data received via serial communication is stored to the on chip RAM with the state of binary data which executes writing 3 The operation for the flash macro service is executed by the flash library function which is assigned to the on chip RAM 4 The flash macro service executes the reprogram processing of on chip flash memory RO1AN1475EJ0100 Rev 1 00 Page 19 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 6 1 3 Process from Startup to Normal Operation After the system activation execute initializations in the main processing and transmit a message Generate INTP1 interrupt for transition to flash programming event to the host Then call the checksum judgment function to judge the program code in the reprogram area The checksum of this sample program uses Program code size and Checksum data that a program was added to one byte a
5. flash store serial data Store processing of receive data conversion hex2bin Text binary conversion processing taua0 led sample Initialization of TAUAO for LED blink with fixed cycle sample function in reprogram area taua0 led spare Initialization of TAUAO for LED blink with fixed cycle sample function in spare area taua0 iQ interval timer isr TAUAO interval timer interrupt processing uartjO_serial_init uartjO_serial_port_init Initialization of UARTJO Initialization of UARTJO ports uartjO_serial_tx_msg UARTJO message transmit processing uartjO_serial_rx_isr UARTJO receive interrupt processing uartjO_serial_status_isr UARTJO status interrupt processing Notes To set the store processing for received program data by serial communication above the LED flash processing the interrupt handler function taua0 chO interval timer isr enables multiple interrupts TAUAO interval timer interrupt is set to the lower priority than FCNO reception completion interrupt RO1AN1475EJ0100 Rev 1 00 Mar 18 2013 Page 27 of 63 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 6 6 Function Specifications The following tables list the sample code function specifications main Outline Main processing Header Declaration void main void Description After initializing the variables the exception handler
6. l URTJOSTC lt H 1E Clear status flag URTJOFSTC H E3 Processing for status I return Note This sample program does not provide the status handling processing The processing which corresponds to various statuses should be added according to the user system Refer to 4 2 6 Precautions for Interrupts Generated During Use of FSL when applying this function 14 y Figure 6 29 UARTJO Status Interrupt Processing R01AN1475EJ0100 Rev 1 00 Page 60 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 7 Operation Overview In this sample program the updating program is transmitted by using the serial communication host device This chapter describes an example of controlling the data transmission using the PC as a serial communication host device Figure 7 1 shows the Hardware Configuration Example for Sample Code Serial communication V850E2 ML4 CPU board Application software Type ROKOF4022C000BR P Serial cable ar Message Program data V850E2 ML4 This sample code Host PC Figure 7 1 Hardware Configuration Example for Sample Code JP1 for signal selection of the CPU board should be switched to 2 3 to use the INTP1 The CPU board serial port connector J5 and the hos
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8. Checksum unmatched RO1AN1475EJ0100 Rev 1 00 Page 28 of 63 Mar 18 2013 RENESAS V850E2 ML4 intp1_init Outline Header Declaration Description Arguments Return Value intp1 isr Outline Header Declaration Description Arguments Return Value flash reprogram Outline Header Declaration Description Arguments Return Value RO1AN1475EJ0100 Rev 1 00 Mar 18 2013 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ Initialization of INTP1 interrupt void intp1 init void Initializes INTP1 interrupt After setting P2 3 pin function to INTP1 input sets the interrupt request to be detected at the falling edge for input using interrupt controller Then sets INTP1 interrupt priority level None None INTP1 interrupt processing void intp1 isr void Sets the flag which indicates that INTP1 interrupt has been generated None None Flash reprogram processing flash h int32 t flash reprogram void Executes initialization of the flash environment start processing of the flash environment checking processing of FLMDO pin and reprogram block erase processing Then transmits the program transmit request message and enters into the loop for program receive wait and flash writing When the program has been received to the last executes the flash reprogram termination processing by writing the checksum data None 0 RET OK 1 RET ERR FLASH ACTIVATE 2 RET ERR
9. Hardware V850E2 ML4 User s Manual Hardware Rev 2 00 RO1UH0262EJ The latest version can be downloaded from the Renesas Electronics website Technical Update Technical News The latest information can be downloaded from the Renesas Electronics website User s Manual Development Tools CubeSuite V 1 03 00 Integrated Development Environment User s Manual Coding for CX compiler Rev 1 00 R20UT2139EJ CubeSuite V1 03 00 Integrated Development Environment User s Manual Build for CX compiler Rev 1 00 R20UT2142EJ V850E2 ML4 CPU Board ROKOF4022COO0BR User s Manual Rev 1 00 R20UT0778EJ The latest version can be downloaded from the Renesas Electronics website User s Manual Software V850E2 ML4 User s Manual Architecture Rev 1 00 RO1US0001EJ The latest version can be downloaded from the Renesas Electronics website Website and Support Renesas Electronics website http www renesas com Inquiries http www renesas com contact RO1AN1475EJ0100 Rev 1 00 Page 63 of 63 Mar 18 2013 RENESAS V850E2 ML4 Application Note Updating Program Code Using REVISION HISTORY Flash Self Programming with Asynchronous Serial Interface J UARTJ Rev G te Description Summary 1 00 Mar 18 2013 First edition issued All trademarks and registered trademarks are the property of their respective owners A 1 General Precautions in the Handling of MPU MCU Products The following usage notes are applicable to all MPU
10. INTUARTJOIRRAM text This sample program additionally assigns a section area to store a spare program as a solution when the flash memory reprogram processing failed to reprogram properly such as abort without any intention For the reprogram area and the spare area before receiving data initial state the programs which have the same processing are stored in respective area Table 6 2 lists the Functions and Sections Specifying Addresses on Flash Memory Table 6 2 Functions and Sections Specifying Addresses on Flash Memory Start Address block number ROM Section Name Reprogram area H 0000 8000 8 taua0 led sample MasterPRG text Spare area H 0000 6000 6 taua0 led spare SparePRG text RO1AN1475EJ0100 Rev 1 00 Page 18 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 6 1 2 Overview of Reprogramming Flash Memory Figure 6 1 shows the Overview of Reprogramming Flash Memory Flash memory H 0000 Exception handler H 0000 Constants Functions ROMized functions allocated to RAM Execute reprogram processing using flash macro service Spare area Reprogram area Checksum area reprogram area Transmit to on chip RAM area at startup On chip RAM HEEDE Variables Buffer 0 Binarize serial Buffer 1 communication receive data
11. to check Using link directive file Refer to CubeSuite V1 03 00 Integrated Development Environment User s manual Coding CX compiler for more details When creating the link directive file in this sample program the reprogram area section MasterPRG text the spare area section SparePRG text and the FSL area FSL CONST should be created in the flash memory other than the default area In addition the FSL use area and user program area sections FSL DATA bss FSL CODE text FSL CODE ROMRAM text FSL CODE RAM text FSL CODE RAM USRINT text FSL CODE RAM USR text and FSL CODE RAM EX PROT text and exception handler address sections INTPIRAM text INTTAUAOIORAM text INTFCNOIERRRAM text and INTFCNOIRECRAM text should be created in RAM In this sample program the start address of the MasterPRG text section is assumed to be H 0000 8000 Also the start address of the exception handler address section is assumed to be the address that adds the respective interrupt handler address to the transfer destination base address HFEDF E000 Figure 4 1 shows the Location of Link Directive File Figure 4 2 shows the Example of Creation and Section Setting for Link Directive File File Edit View Project Build Debug Tool Window Help Rt AM i x BBV e HRS SORES Project Tree 5 DQ g Aq CX Property v850e2ml4 flash update Debug Informabon fk uPD20F402 Microcontro E Input Eile ES GN CX Build Tool gt Using link dire
12. FLASH MODECHECK 3 RET ERR FLASH ERASE 4 RET ERR FLASH WRITE 5 RET ERR FLASH IVERIFY 6 7 8 9 Normal end Failure to start flash environment Failure to check FLMDO pin Failure of erase processing Failure of write processing Failure of internal verification Failure to terminate flash environment RET ERR FLASH FLMDO HIGH Failure to set FLMDO pin to High level RET ERR FLASH FLMDO LOW Failure to set FLMDO pin to Low level RET ERR FLASH HEX LINESIZE Abnormal numbers of hex file data 10 RET ERR FLASH HEX DATA Abnormal program data of hex file RET ERR FLASH DEACTIVATE Page 29 of 63 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ flash_init Outline Initialization of flash environment Header Declaration int32_t flash_init void Description After executing FLMDO pin level setting function and setting FLMDO pin to High level initializes the self library by executing the FSL Init function When the flash set flmdO function becomes an error the RET ERR FLASH FLMDO HIGH will be returned Arguments None Return Value 0 RET OK Normal end 7 RET ERR FLASH FLMDO HIGH Failure to set FLMDO pin to High level flash activate Outline Start processing of flash environment Header Declaration int32 tflash activate void Description Starts the flash environment by calling the FSL FlashEnv Act
13. MCU products from Renesas For detailed usage notes on the products covered by this document refer to the relevant sections of the document as well as any technical updates that have been issued for the products 1 Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual The input pins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of LSI an associated shoot through current flows internally and malfunctions occur due to the false recognition of the pin state as an input signal become possible Unused pins should be handled as described under Handling of Unused Pins in the manual Processing at Power on The state of the product is undefined at the moment when power is supplied The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied In a finished product where the reset signal is applied to the external reset pin the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting
14. ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 6 Software 6 1 Operation Overview This sample program receives a program file data for update with Intel expanded hex format using serial communication and reprograms the program in the flash memory area This section describes its operation overview 6 1 1 Setting for Section Assignment The access to the flash memory is prohibited while the flash memory is reprogrammed All programs that are used during the reprogram of flash memory should be transferred to the area except flash memory This sample program sets section assignment to transfer all the sections used during the reprogram to the on chip RAM Table 6 1 lists the Sections Used During Flash Memory Reprogram Table 6 1 Sections Used During Flash Memory Reprogram Section Name Program Details Function Name FSL CODE ROMRAM text FSL area Flash function FSL CODE RAM text FSL CODE RAM EX PROT text FSL CODE RAM USRINT text User program interrupt section for uartj0 serial rx isr RAM flash store serial data hex2bin intp1 isr taua0 chO interval timer isr FSL CODE RAM USR text User program section RAM uartjO serial tx msg flash reprogram flash init flash activate flash modecheck flash erase flash write flash iverify flash end flash set flmdO INTP1RAM text Jump instruction to interrupt INTTAUAOIORAM text handler function INTUARTJOISRAM text
15. Processing of FLMDO Pin Using FSL RO1AN1475EJ0100 Rev 1 00 Page 45 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 6 7 11 Erase Processing of Specified Block Figure 6 15 shows the Erase Processing of Specified Block uint32_t start_block Start block number of the range to be erased flash_erase Arguments uint32_t end_block End block number of the range to be erased Erase specified block FSL_Erase fsl status Return value of FSL_Erase start_block end block fsl status FSL BUSY Wait for erase completion Check previously specified fsl_status lt Return value of FSL StatusCheck statusFSL StatusCheck error fsl status lt fsl status Store error state g mo a en retum RET ERR FLASH ERASE Global variable C GE fsl status tg error fsl status Store FSL error Local variable fsl status tfsl status Return value of FSL function Figure 6 15 Erase Processing of Specified Block RO1AN1475EJ0100 Rev 1 00 Page 46 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 6 7 12 Write Processing from Specified Address Figure 6 16 shows the Write Processing from Specified Address Arguments N uint8_t src data addr Write source RAM address
16. address INTP1 interrupt and UARTJ executes the program allocated in the reprogram area or the spare area according to the checksum judgment Enables interrupts and outputs INTP1 interrupt request message then execute the flash reprogram processing when INTP1 interrupt is generated Outputs the reset request message for successful reprogram or the error message for failure Arguments None Return Value None except_handler_addr_set Outline Switching processing of exception handler base address Header Declaration int32 t except handler addr set uint32_t base_addr Description After setting the value specified by the argument to the SW BASE register sets 1 to SET bit of the SW CTL register Then transfers the contents of SW BASE register to the exception handler base address register EH BASE Arguments uint32 t base addr Exception handler base address setting value The lower 12 bit should be 0 Return Value 0 RET OK Normal end 1 RET ERR Argument error The lower 12 bit is not 0 check sum check Outline Checksum judgment of reprogram area Header Declaration int32 t check sum check void Description Based on the program code size or checksum data stored in the last 4 bytes H 0000 8FFO to H 0000 8FF3 of reprogram area calculates sum value from the start address H 0000 8000 of reprogram area to judge the consistency with the checksum data Arguments None Return Value O RET OK Checksum matched 1 RET ERR
17. can be written into flash memory Vv Write buffer 0 into flash memory ret flash write g buf write data0 Yes flash write write addr Write buffer 1 into flash memory ret flash write g buf write data1 AA SIZE WRITE 4 flash write write addr SIZE WRITE 4 AA g flag w data bufO full lt false flash 8 x aR S aaa write_addr SIZE_WRITE g flag w data bufo full lt false Update flash write address write addr SIZE WRITE No No data to be written Receive end record Figure 6 11 Flash Reprogram Processing 2 2 RO1AN1475EJ0100 Rev 1 00 Page 42 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 6 7 8 Initialization of Flash Environment Figure 6 12 shows the Initialization of Flash Environment flash init Global variable Z uint8_t g_flag_flash_status Flash environment status AA Set FLMDO pin to High level flash_set_flmd0O Return value of flash_set_flmd0 is 0 eumrr ERR FLASH FLMDO Hem g_flag_flash_status FLASH STATUS FLMDO HIGH Update flash environment status Vv Initialize self library FSL Init y C return RET OK Figure 6 12 Initialization of Flash Environment RO1AN1475EJ0100 Rev 1 00 Page 43 of 63 Mar 18 2013 RENESAS V850E2 M
18. ep register cannot be operated properly e Sections when accessing to the gp register as a base address The created global variables without section specification will be allocated to sdata or sbss data bss sdata sbss e Sections when accessing to the ep register as a base address sedata sebss sidata sibss tidata byte tibss byte tidata word tibss word This sample program does not use a section which accesses to the ep register as a base address and therefore the saving setting and restoring processes for the ep register are not executed in the interrupt processing The V850E2 ML4 does not require the saving setting and restoring of the gp register when using the FSL When changing the microcomputer or using the above sections the saving setting and restoring of the gp register or ep register may be necessary in the interrupt processing Cautions are required when applying RO1AN1475EJ0100 Rev 1 00 Page 16 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 5 Hardware 5 1 Pins Used Table 5 1 lists the Pins Used and Their Functions Table 5 1 Pins Used and Their Functions Pin Name Function P2 12 RXDOF Serial data input P2 13 TXDOF Serial data output P2_3 INTP1 INTP1 interrupt RO1AN1475EJ0100 Rev 1 00 Page 17 of 63 Mar 18 2013 RENESAS V850E2
19. for 1 byte of the record size The four characters from 4th to 8th green indicate the lower 2 bytes of the start data store address of the record e Regarding the 10th and later characters orange of the record each two characters indicates 1 byte In the data receive processing the 10th and later characters orange is converted into binary data every 2 characters call text binary conversion processing store the I byte data after the conversion into the write buffer in the order converted Add the one byte data for the checksum judgment checksum data and count the amounts of the data as a program code size When repeated these processing before the last two characters black of the record return to the wait state for receive data until the next entire record will be displayed e When the 8th and 9th red characters of the record data show 01 it means end record the bottom line in Figure 6 2 When the end record is shown terminate the data receive processing without storing receive data However if the data size in the write buffer is less than 16 bytes unit of flash write at this point add H FF to make the buffer size 16 bytes This sample program provides a double structured write buffer with 16 byte size Every time the store data in a write buffer becomes full at 16 bytes the store destination is switched to another write buffer during the data receive processing When the said buffer becomes full the buffer data is written
20. for LED blink with fixed cycle sample function in reprogram area void taua0 led sample void Sets the port connected to the LEDs to output to blink them Sets TAUAO to the interval timer which generates interrupts with fixed cycle None None Initialization of TAUAO for LED blink with fixed cycle sample function in spare area void taua0 led spare void Sets the port connected to the LEDs to output to blink them Sets TAUAO to the interval timer which generates interrupts with fixed cycle None None taua0 iQ interval timer isr Outline Header Declaration Description Arguments Return Value RO1AN1475EJ0100 Rev 1 00 Mar 18 2013 TAUAQO interval timer interrupt processing void taua0 iO interval timer isr void Inverts P1 4 output for LED blink None None Page 33 of 63 RENESAS V850E2 ML4 uartjO_serial_init Outline Header Declaration Description Arguments Return Value uartjO_serial_port_init Outline Header Declaration Description Arguments Return Value uartjO_serial_tx_msg Outline Header Declaration Description Arguments Return Value uartjO_serial_rx_isr Outline Header Declaration Description Arguments Return Value uartjO_serial_status_isr Outline Header Declaration Description Arguments Return Value RO1AN1475EJ0100 Rev 1 00 Mar 18 2013 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ Initializa
21. for reprogram area in ROM DATA LOAD RW VOxfedf0000 data PROGBITS AW data sdata PROGBITS AWG sdata sbss NOBITS AWG sbss FSL_DATA bss NOBITS AW FSL_DATA bss FSL use area Create section for FSL use area in RAM AW ss bss li SEDATA LOAD RW sedata PROGBITS AW sedata sebss NOBITS AW sebss SIDATA LOAD RW tidata byte PROGBITS AW tidata byte tibss byte NOBITS AW tibss byte tidata word PROGBITS AW tidata word tibss word NOBITS AW tibss word tidata PROGBITS AW tidata tibss NOBITS AW tibss sidata PROGBITS AW sidata sibss NOBITS AW sibss Program area allocated to RAM RAM PROG LOAD RX VOxfedfc000 Create segment and section for FSL area FSL_CODE text PROGBITS AX FSL_CODE text and user program area in RAM FSL_CODE_ROMRAM text PROGBITS AX FSL_CODE_ROMRAM text FSL CODE RAM text PROGBITS AX FSL_CODE_RAM text FSL CODE RAM USRINT text PROGBITS AX FSL CODE RAM USRINT text FSL CODE RAM USR text PROGBITS AX FSL CODE RAM USR text FSL CODE RAM EX PROT text PROGBITS AX FSL CODE RAM EX PROT text Exception handler area allocated to RAM INTRAM LOAD RX VOxfedfe000 L0x00001080 INTP1RAM text PROGBITS AX VOxfedfel70 HOx0000000a INTP1RAM text Create segment and section INTTAUAOIORAM text PROGBITS AX VOxfedfe3b0 HOx0000000a I
22. interrupt is generate the V850E2 ML4 enters into flash reprogram processing and erases the update area After the erasing is completed the V850E2 ML4 transmits a message Send subroutine code to update program in Intel expanded Hex format to the host and enters into wait state for data reception from the host In case of transmitting a file with Intel expanded hex format as a program data from the host the terminal emulator transmit function should be used When choosing and transmitting the said file such as v850e2ml4_sample_host_send hex in this sample program the received file is converted to program data and written to the flash memory After the writing is completed the V850E2 ML4 transmits a message Successfully Finish Writing Program Data Please Reset to the host it enters into wait state for reset Reset the board When restarting the LEDs on the board flash with the different period from previous one If the data reception flash reprogram update prior to restart was failed to execute properly the V850E2 ML4 finds a checksum error at the time of restarting by reset input The V850E2 ML4 executes the program in the spare area RO1AN1475EJ0100 Rev 1 00 Page 62 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 8 Sample Code Sample code can be downloaded from the Renesas Electronics website 9 Reference Documents User s Manual
23. set gp register offset tp gp set gp register 4 stack STACKSIZE sp set sp register ep DATA ep set ep register PROLOG TABLE r12 for prologue epilogue runtime r12 20 set CTBP CALLT base pointer _hdwinit lp initialize hardware __ssbss r6 clear sbss section f esbss r7 r __zeroclrw lp Clear the periphery of the area to be used as a program in RAM to zero before __ sbss r6 clear bss section 4 ebss r7 _ zeroclrw mov32 Oxfedfc000 Clear ram_prog section for e2core prefetch processing mov32 Oxfedfffff jarl __zeroclrw Continued Figure 4 8 Example of Startup Routine Preparation Excerpt from cstart asm RO1AN1475EJ0100 Rev 1 00 Page 15 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 4 2 6 Precautions for Interrupts Generated During Use of FSL When accessing to the data using the gp register or the ep register in the interrupt processing generated during the use of the FSL set appropriate values to the gp register or the ep register before accessing to the data The saving process for the gp register or the ep register is required before setting the appropriate values to the registers Furthermore the restoring process for the gp register or the ep register is required before returning from the interrupt processing If the said measures are not executed the data access using the gp register or the
24. to the flash memory during flash reprogram event processing Writing to the flash memory is executed by polling waiting for receive data not by an interrupt processing When switching the buffer at full set flag variables which indicate writability 6 1 6 Processing after Data Deception Reprogramming When the end record is determined during data receive processing and the write of flash memory for the receive data is terminated the V850E2 ML4 leaves from the wait state for data reception in the flash reprogram event processing and writes the data for checksum judgment calculated at the time of data reception program code size and checksum data 2 bytes for each the flash memory In this sample program the data for checksum judgment is stored the last 4 bytes of the reprogram area H 0000 8FFO to H 0000 8FF3 H 0000 8FFO to H 0000 8FF1 for the program code size and H 0000 8FF2 to H 0000 8FF3 for the checksum data After writing the data for checksum judgment a message is transmitted to the host and the V850E2 ML4 enters wait state for reset RO1AN1475EJ0100 Rev 1 00 Page 21 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 6 1 7 Communication Control Sequence Figure 6 3 shows the Communication Control Sequence d V850E2 ML4 D I Change exception handler address v Initializations I Checksum judgment
25. 0E2 E1 JTAG Deb Picgiem ak nen ha Generate load module file has rompsec section only No i neluded in ramp on Data sections included in rompsec section 0 I File PT ext sections included in rompsec section 10 FSL_CODE text FSL_CODE_ROMRAM text FSL_CODE_RAM text FSL_CODE_R amp M BE RAM EX PROT test Text sections included in roppst Specifies the text sectioraricluded in the rompsec section Figure 4 4 Setting for Romization of Section in RAM RO1AN1475EJ0100 Rev 1 00 Page 11 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 4 2 4 Setting for Far Jump Function In the V850E2 MLA the end address of the flash memory and the start address of the on chip RAM are separated more than 2MB In the CX compiler when jumping to the area more than 2MBs away at the time of function call the far jump option should be specified to the call destination function In this sample code the far jump option is specified to the functions called from the ones on the flash memory out of the functions allocated in the on chip RAM and all interrupt handlers to be used To specify the far jump option create the file which lists the functions to be specified far jump calling function list file and specify the file name in the compile option Xfar jump To set in the CubeSuite select CX Built Tool under the Pro
26. 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ e For the processing of each line determine if the 1st character of the data in the receive buffer shows If it shows judge the 8th and 9th characters red as Intel expanded hex format If the 1st character does not show the record data become invalid and returns to wait state for receive data When the 8th character does not show 0 the record data also become invalid and returns to wait state e The 8th and 9th characters red of the first line show 05 This 05 indicates the start linear address record which does not have a program data When received the start linear address record return to the wait state for receive data until the next entire record line data will be displayed e The 8th and 9th characters red of the second line show 04 This 04 indicates the extended linear address record which does not have a program data When received the extended linear address record return to the wait state for receive data until the next entire record will be displayed e When the entire 3rd line of the record is displayed the line is determined as a data record because the 8th and 9th characters red show 00 The type of the record can be determined by the numbers from the start to 9th of each record with Intel expanded hex format e The 2th and 3rd characters blue of the record indicate the hex
27. 2tEN ESAS APPLICATION NOTE V850E2 ML4 RO1AN1475EJ0100 Rev 1 00 Updating Program Code by Using Flash Self Programming Mar 18 2013 with Asynchronous Serial Interface J UARTJ Abstract This document describes an example to update program code by reprogramming on chip flash memory in V850E2 ML4 using flash self programming with serial communication The features of the example to update program code in this Application note are described below e Reprograms a program code in the flash memory area using update program file with Intel expanded hex format received through serial communication e For the procedure in case of reprogram failure such as reprogram processing is aborted without intention an error control register by checksum is included Products V850E2 ML4 When using this application note with other Renesas MCUs careful evaluation is recommended after making modifications to comply with the alternate MCU RO1AN1475EJ0100 Rev 1 00 Page 1 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ Contents T SPECMEANONS ua 4 2 Operation Confirmation Conditions uanrerannrnnnerrvnnnvrnnnnrnnenrnnrrrrennnrnnnennenrrrnesnnrnnennenrenarnnnrnssnnnenneneeenn 5 3 Reference Application Notes rrrurnrrnannrnnnnnvnnnrrnnnnrrnnrnnnnrerrennrnrnnnnenennenrnraesnnrnnennenrrnrresnnnnsennenennenenn 6 4 Peripheral Functions wssrrn
28. C flash write J uint32_t dst_write_addr Write destination flash address uint32_t length Write size y Write from specified address FSL_Write fsl_status lt Return value of FSL_Write src_data_addr dst_write_addr length 14 fsl status FSL BUSY Wait for write completion y Check previously specified fsl_status lt Return value of FSL_StatusCheck statusFSL_StatusCheck fsl_status FSL_OK v g error fsl status lt fsl status g addr write error lt dst write addr Store error state y feturn RET_ERR_FLASH_WRITE y Global variables C return RET_OK fsl status tg error fsl status Store FSL error 1uint32 tg addr write error Write error address Local variable fsl status tfsl status Return value of FSL function Figure 6 16 Write Processing from Specified Address RO1AN1475EJ0100 Rev 1 00 Page 47 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 6 7 13 Internal Verification of Specified Block Figure 6 17 shows the Internal Verification of Specified Block Arguments a uint32_t start_block Start block number of internal verification flash_iverify uint32_t end_block End block number of internal verification Write from specified address FSL IVerify fsl status Return value of FSL IVerify start block e
29. E_NUM g_buf_rx_data HEXDATA_POS_BYTE_NUM 1 y Obtain data by using binary conversion hex2bin bin data hex2bin g buf rx data HEXDATA POS CODE TOP 2 il 9 buf rx data HEXDATA POS CODE TOP 2 i 1 Write buffer is0 gt Repeat for binary data size Yes I g_status_data_bu Store in write data store buffer0 Store in write data store buffer 1 g_buf_write_dataO g_cnt_store_buf_w_dai g_cnt_store_buf_w_data0 y a0 lt bin data g_buf_write_data1 g_cnt_store_buf_w_da g_cnt_store_buf_w_data1 a1 lt bin data AA Buffer 0 is full p Buffer 1 is full saa Yes Ves y Change of write buffer 0 Change of write buffer 1 g cnt store buf w data0 lt 0 g flag w data bufO full true g status data buff 1 g ent store buf w datai 0 g flag w data buf1 full lt true g status data buff lt 0 4 AA g_chksm_data bin_data Checksum calculation y for loop End v A chksm size bin size Checksum size calculation g Write buffer is 0 Local variables uint8_t bin data Program data int8 t bin size Data size included in a line uint8 ti Loop counter Yes y v Pad the remaining of write data store Pad the remaining of write data store buffer 0 with H FF buffer with H FF v v Global variables uint8_t g_buf_rx_datal Chan
30. H STATUS FLMDO HIGH 0 set to High y Set FLMDO pin to Low level ret lt flash_set_fImd0 0 flash_set_fImd0 v NG Update flash environment status Set error to return value g_flag flash status amp FLASH STATUS FLMDO HIGH PE ERR FLASH FLMDO LOW Yy return ret Figure 6 18 Termination Processing of Flash Environment R01AN1475EJ0100 Rev 1 00 Page 49 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 6 7 15 Setting for FLMDO Pin Level Figure 6 19 shows the Setting for FLMDO Pin Level Argument C flash set flmdo _ uint8 t level FLMDO pin level y Enable writing FLMD protection FLMDPCMD lt H A5 command register y FLMDCNT lt level FLMDCNT lt level FLMDCNT lt level Write FLMD control register Succeed in writing 0x00 FLMDPS level FLMDCNT C return RET OK C return RET ERR Figure 6 19 Setting for FLMDO Pin Level RO1AN1475EJ0100 Rev 1 00 Page 50 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 6 7 16 Store Processing for Receive Data Figure 6 20 and Figure 6 21 show the Store Processing for Receive Data Global variables uint8_t g_buf_recv_data Receive data store buff
31. J UARTJ Table 6 3 lists the Files Used in the Sample Code Files generated by the integrated development environment are not included in this table Table 6 3 Files Used in the Sample Code File Name main c Outline Main processing Remarks intp1 c INTP1 interrupt processing flash c Processing related to flash reprogram uartjO_serial c Processing related to UARTJ taua0 led sample c Sample program for updating LED blink port processing flash h Common header for flash memory reprogram processing r typedefs h Fixed length integer type definition header FSL h FSL header file except handler ram asm Exception handler in RAM Jump to interrupt processing function from RAM cstart asm Startup routine Change stack size by standard startup routine and add initialization of program area in RAM libFSL T05 REC R32 lib FSL library 32 register mode v850e2ml4 flash update uartj dir Link directive setting file v850e2ml4 flash update uartj fjp Far jump calling functions file Note Defines the jump instruction from the interrupt handler address to the interrupt handler function to be allocated on the exception handler RO1AN1475EJ0100 Rev 1 00 Mar 18 2013 RENESAS Page 23 of 63 V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 6 3 Constants Table 6 4 and Tabl
32. L4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 6 7 9 Start Processing of Flash Environment Figure 6 13 shows the Start Processing of Flash Environment fide activate Global variables uint8_t g_flag_flash_status Flash environment status fsl status tg error fsl status Store FSL error y Start flash environment FSL_FlashEnv_Activate eturn value 0 FSL FlashEnv Activate is FSL OK b g error fsl status lt Return value of FSL FlashEnv Activate Store error state y eu MRET ERR FLASH ACTIVATE v Update flash environment status g_flag_flash_status FLASH_STATUS_FSL_ACTIVATE y C return RET OK Figure 6 13 Start Processing of Flash Environment RO1AN1475EJ0100 Rev 1 00 Page 44 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 6 7 10 Checking Processing of FLMDO Pin Using FSL Figure 6 14 shows the Checking Processing of FLMDO Pin Using FSL flash_modecheck Global variable fsl_status_t g_error_fsl_status Store FSL error I Check FLMDO pin FSL ModeCheck Return value 0 FSL ModeCheck is FSL OK g error fsl status lt Return value of FSL ModeCheck Store error state I 1oumrET ERR FLASH MODECHECX C return RET OK Figure 6 14 Checking
33. NTTAUAOIORAM text for exception handler in RAM INTUARTJOISRAM text PROGBITS AX VOxfedfea50 HOx0000000a INTUARTJOISRAM text INTUARTJOIRRAM text PROGBITS AX VOxfedfea60 HOx0000000a INTUARTJOIRRAM text J __tp_TEXT TP_SYMBOL __gp_DATA GP SYMBOL amp tp TEXT DATA __ep DATAQ EP_SYMBOL Figure 4 2 Example of Creation and Section Setting for Link Directive File RO1AN1475EJ0100 Rev 1 00 Page 9 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 4 2 2 Setting for Non use of Prologue Epilogue Library The CubeSuite executes setting for non use of the prologue epilogue library Select CX Build Tool under the Project Tree and click Compile Options tab in the Property Select No Xpro_epi_runtime off for Use prologue epilogue library in Optimization Details Figure 4 3 shows the Location of Setting Non Use of Prologue Epilogue Library File Edit View Project Build Debug Tool Window Help Rs ASP i Xx BBIVS MRSAA i Si SS EG Project Tree is E Property J main c Ay CX Property 850e2ml4 flash update Debug Informabon uPD70F4022 Microcontro 4 Optimization K CX Build Tool gt E et amp ort external variables E amp x V850E2 EI TAG Debug Perform inline expansion of strepy stremp memcpy memset gt Use prologue epilogue library g File Prohibit the operation that changes memory access size Perform
34. RR p Figure 6 7 Checksum Judgment of Reprogram Area RO1AN1475EJ0100 Rev 1 00 Page 38 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 6 7 5 Initialization of INTP1 Interrupt Figure 6 8 shows the Initialization of INTP1 Interrupt C intp1_init Initialize ports Port input mode and input buffer in disabled state y Set port filter Initialize FCLA15CTL2 register y Initialize PU2 register y Initialize PD2 register y Set ALT1 IN input of P2_3 to be used for INTP1 interrupt y Enable interrupt level setting set il y return Figure 6 8 Initialization of INTP1 Interrupt RO1AN1475EJ0100 Rev 1 00 Mar 18 2013 RENESAS PIBC2 amp H 0008 PBDC2 amp H 0008 PM2 H 0008 PMC2 amp H 0008 PIPC2 amp H 0008 FCLA15CTL2 lt H 02 PU2 amp H 0008 PD2 amp H 0008 PIS2 H 0008 PISE2 amp H 0008 PISA2 amp H 0008 PFC2 amp H 0008 PFCE2 amp H 0008 PMC2 H 0008 PIBC2 H 0008 __set_il 2 INTP1 set il 0 INTP1 Page 39 of 63 V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 6 7 6 INPT1 Interrupt Processing Figure 6 9 shows the INTP1 Interrupt Processing Tore Global variable pl int8_t g_flag_start_fla
35. a uint8 t g buf rx data SIZE BUF RX DATA Receive data store buffer flash store serial data int8_t g_status_store_error Error flag flash_reprogram flash store serial data uint8 _t g flag flash status Flash environment status flash init flash activate flash end g_msg_sendcode RO1AN1475EJ0100 Rev 1 00 Mar 18 2013 Program transmit request message RENESAS flash_reprogram Page 26 of 63 V850E2 ML4 6 5 Functions Table 6 7 lists the Functions Table 6 7 Functions Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ Function Name Outline main Main processing except_handler_addr_set Switching processing of exception handler base address check_sum_check Checksum judgment of reprogram area intp1_ init Initialization of INTP1 interrupt intp1 isr NTP1 interrupt processing flash reprogram Flash reprogram processing flash init Initialization of flash environment flash activate Start processing of flash environment flash modecheck Checking processing of FLMDO pin using FSL flash erase Erase processing for specified block flash write Write processing from specified address flash iverify Internal verification of specified block flash end Termination processing of flash environment flash set flmdO Setting for FLMDO pin level
36. a record converts the data in binary form and saves it until the buffer becomes full When the hex data for on line is the end record pads the remaining bytes with H FF and sets the flag which indicates the receiving has been completed Arguments uint8 trx data Receive hex data Return Value None RO1AN1475EJ0100 Rev 1 00 Page 32 of 63 Mar 18 2013 RENESAS V850E2 ML4 hex2bin Outline Header Declaration Description Arguments Return Value taua0 led sample Outline Header Declaration Description Arguments Return Value taua0 led spare Outline Header Declaration Description Arguments Return Value Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ Text binary conversion processing int32 t hex2bin uint8 t upper uint8 t lower Converts the text data 2 characters to the binary data with 1 byte When the data given to the argument is the text data with 0 to 9 or A to F it is considered as the valid data and will be converted to the binary data with H O to HF After shifting the conversion result of the first argument upper to left by 4 bits and implementing the OR with the conversion result of the second argument lower returns it as the binary data with 1 byte uint8 i upper Text data for the upper 4 bit uint8 t lower Text data for the lower 4 bit 0 to 255 Binary data with 1 byte 1 RET ERR Input data error Initialization of TAUAO
37. anavonnonrvrnnrrnannvonnnnonnnrrnannrnnannvnnnnrnnnnrnnnnnnnnnnnresnnrnnsnanennnnenennreentannrnenennenenn 6 4 1 Terms for Flash Self Programming arrvrnannvnnervvnnnvrvnnnrnnnnvvnrnrrrnnnnrnnenvenrrrrennnrnnennenrenrenennrnsennnnennn 6 4 2 Notes for Flash Self Programming arnvvnannvnnorvvnnnrrnnnnrnnnnnvnrnnrrnnnnrnnenrennsrresnnrnnsnnnenennresnrnssnnnernn 7 4 2 1 Setting for Link Directive File rnrnrnnrnnnnvrnannvnnnnnrvnnnrrnnnnvnnannnnnerrennnrnnnnnnnnnenrensnrnrannrnssnnnennnn 8 4 2 2 Setting for Non use of Prologue Epilogue Library rarsreronvvnrnrvvnnnrnnnnnvnnenrvnnnnrrnnnnnnnenreeenn 10 4 2 3 Setting for ROMization of Section in RAM rrnrnnrvnnnvnnnnnvnnenvvnrnrrennnnrnnenvenrnrrernnrrnsnnrnserreeenn 11 4 2 4 Setting for Far Jump Function senrrernrrnnnnrrnenvvnrerrvrnnrrvnnnvnnennenrnrrnnnnrnennnresenvenrrrresnsrnesennennn 12 4 2 5 Setting for Startup Routine xrrnanvrnnnrvvnnnrrnnnnvnnenvrnrnrrenennrnnennennnrrennnrnennnnenenrennnnrrnannnnnennennn 14 4 2 6 Precautions for Interrupts Generated During Use of FSL rnrunrnnnnnvnnannvnnenrvnnnrrnnnnnrnnenvenenn 16 me VE EEE EE EE 17 SA PNS USSA aaan gaea e Ea aE aE A a a a AAEE A ES 17 6 SONNIE oea aE EEA T T AO A 18 6 1 Operation Overview 0 ecececcc cece eeeneeeeeeee cea aeeeeaeeeeeeee seas eeeaaeeeeesaeeeceaeseeaaeeseeeesaesseeaeeseneeseeeee 18 6 1 1 Setting for Section Assignment cccceccee eet ee cece eeteeeeeaeeeeaeeeeneeeseaeeeseaeesee
38. ation in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information 2 Renesas Electronics has used reasonable care in preparing the information included in this document but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein 3 Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others 4 You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration modification copy or otherwise misappropriation of Renesas El
39. cannot occur unless the flash environment is ended e Flash function This refers to the individual functions comprising the self library They can be used with the C language e Internal verification This refers to the action of internally checking the signal level and verifying that the signal can be read normally following write to flash memory RO1AN1475EJ0100 Rev 1 00 Page 6 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 4 2 Notes for Flash Self Programming The V850E2 ML4 has the flash macro service which operates the flash memory This sample program describes how to reprogram a program code using the flash self programing library FSL which enables to use the flash macro service with C language The following notes are provided to use this library e The program allocation in RAM executed during the flash environment including runtime library Setting for a section to allocate the program in RAM Creation and setting for the link directive file is required to set a section Refer to 4 2 1 Setting for Link Directive File for more details Setting for non use or allocation in RAM for the functional prologue epilogue runtime library This sample program runs the non use setting of the prologue epilogue runtime library Refer to 4 2 2 Setting for Non use of Prologue Epilogue Library for more details Setting for the exception hand
40. cessing R01AN1475EJ0100 Rev 1 00 Page 59 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 6 7 24 UARTJO Status Interrupt Processing Figure 6 29 shows the UARTJO Status Interrupt Processing C uartjO_serial_status_isr Local variables og uint8_t reg_urtjOstr1 Read value of URTJOSTR1 uint8 treg urtjOfstri Read value of URTJOFSTR1 uint16 t dummy_read Variable to read URTJOFRX uint16 trx num The number of remaining receive data in receive FIFO uint16 il Loop counter y Read URTJOSTR1 register reg_urtjOstr1 URTJOSTR1 Yy Read URTJOFSTRI register I Read the number of remaining rx num URTJOFSTRO amp H 1F00 gt gt 8 receive data in receive FIFO I for loop i 0 i lt rx_num i Read URTJOFSTRI register I Read remaining receive data in receive FIFO reg urtjOfstri lt URTJOFSTR1 dummy read lt URTJOFRX for loop End Detect inconsistency of Yes reg_urtjOstr1 amp H 04 nsmit data and receive data Yy Clear transmit FIFO pointer DELETE salle reg_urtjOfstr1 amp H 20 Detect receive FIFO overrun Xes reg ur rhe number of remaining data Yes rx_num 0 in receive FIFO is 0 Vv Receive overrun error processing Receive overrun error processing with receive FIFO full with receive FIFO empty
41. chronous Serial Interface J UARTJ Contents Start flag for writing flash memory Function Used main intp1 isr fsl status i g error fsl status Store FSL error main flash activate flash modecheck flash erase flash write flash iverify uint32 g addr write error Write error address main flash write uint8 g flag w data bufO full Write buffer 0 full flag flash reprogram flash store serial data uint8 g flag w data buf1 full Write buffer 1 full flag flash reprogram flash store serial data uint8 t g status end record End record receive flag flash reprogram flash store serial data uint16 g chksm size Program code size for write data flash reprogram flash store serial data uint16 g chksm data Checksum data of write data flash reprogram flash store serial data uint8 t g buf write data0 SIZE WRITE Write data store buffer 0 flash reprogram flash store serial data uint32 g cnt store buf w data0 Data counts of write data store buffer 0 flash reprogram flash store serial data uint8 _t g buf write datal SIZE WRITE Write data store buffer 1 flash reprogram flash store serial data uint32 g cnt store buf w data1 Data counts of write data store buffer 1 flash reprogram flash store serial data uint32 t g index rx data Receive data storage location index flash reprogram flash store serial dat
42. cnt store buf w data uint32 tg index recv data g index recv data lt 0 write addr lt TOP ADDR MASTER PRG Write buffer 0 full flag Write buffer 1 full flag Write buffer status End record receive flag Program code size of write data Checksum data of write data Write data store buffer 0 Data counts of write data store buffer 0 Write data store buffer 1 Data counts of write data store buffer 1 Specify receive data storage location Local variable fsl u32 write addr Write address Yes Erase block in reprogram area flash erase Yes Transmit message uartj serial tx msg Erase block 8 ret lt flash erase BLOCK MASTER PRG BLOCK MASTER PRG Output message Send subroutine code to update program in Intel expanded hex format hd Failed to write program Succeed E D Cc B g buf write data0 0 g buf write data0 1 lt g buf write data0 2 g chksm size amp OxOOff g chksm size amp Oxff00 gt gt 8 g chksm data amp OxOOff g chksm data amp Oxff00 gt gt 8 Y Create checksum data I g buf write data0 3 lt Write checksum data ret lt flash write g buf write data0 TOP ADDR MASTER PRG CHKSUM SIZE WRITE 4 flash write Yes Internal verification of reprogram area flash iverify ret lt flash iverify BLOCK MASTER PRG BLOCK MASTER PRG Flash
43. e 6 5 list the Constants Used in the Sample Code Table 6 4 Constants Used in the Sample Code Constant Name RET_OK Setting Value Contents Normal end RET_ERR Error end RET_ERR_FLASH_ACTIVATE Failure to start flash environment RET_ERR_FLASH_MODECHECK Failure to check FLMDO pin RET_ERR_FLASH_ERASE Failure of erase processing RET_ERR_FLASH_WRITE Failure to write RET_ERR_FLASH_IVERIFY Failure of internal verification RET_ERR_FLASH_DEACTIVATE Failure to terminate flash environment RET ERR FLASH FLMDO HIGH Failure to set High level for FLMDO pin RET ERR FLASH FLMDO LOW Failure to set Low level for FLMDO pin RET ERR FLASH HEX LINESIZE Abnormal numbers of hex file line data RET ERR FLASH HEX DATA 10 Abnormal hex file program data BLOCK MASTER PRG 8 Block number of reprogram area TOP ADDR MASTER PRG H 00008000 Start address of reprogram area SIZE MASTER PRG H 1000 Reprogram area size 4KB SIZE WRITE 16 Write specification size TOP ADDR MASTER PRG CHKSUM TOP ADDR MASTER _PRG SIZE_MASTER_PRG SIZE_WRITE Start address of checksum area H 00008FFO TOP_ADDR_EXT_HANDLER RO1AN1475EJ0100 Rev 1 00 Mar 18 2013 H FEDF E000 RENESAS Start address of exception handler address for transfer destination Page 24 of 63 V850E2 ML4 Updating Program Code Using Flash Sel
44. e startup of switching procedure to the termination thereof must be free from exceptions or any problem in case that an exception was generated This sample program has a program that operates properly for any exception handler address of before after switching If the program cannot be located at the time of application settings such as interrupt disable will be required Figure 6 6 Switching Processing of Exception Handler Address RO1AN1475EJ0100 Rev 1 00 Page 37 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 6 7 4 Checksum Judgment of Reprogram Area Figure 6 7 shows the Checksum Judgment of Reprogram Area check_sum_check Read the following data calculated at the time of last activation when data received and stored in the last Read checksum judgment data 16 byte area of reprogram area Checksum data Write data program code size Ensure that the size does not excceed rite data size falls within 4080 bytes 4K bytes 16 bytes effective range AA Set start address of reprogram area gt A A Read data 1 byte in reprogram area for calculation Complete reading for write data size v Increment read address of reprogram area alculation result matches with checksum data AA return RET OK return RET_E
45. e2ml4_flash_update_uartj hex Operating mode Normal operating mode Will be changed to flash memory programming mode at the time of reprogram Sample code version 1 00 Board used ROKOF4022CO00BR Device used Serial communication host device RO1AN1475EJ0100 Rev 1 00 Page 5 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 3 Reference Application Notes For additional information associated with this document refer to the following application notes e V850 Microcontroller Flash Self Programming Library Type05 RO1ANO661EJ 4 Peripheral Functions This chapter provides supplementary information on the flash self programming library which is required to reprogram the flash memory using the software operated on the V850E2 ML4 Refer to the V850E2 ML4 User s Manual Hardware and the V850 Microcontroller Flash Self Programming Library Type05 for basic information 4 1 Terms for Flash Self Programming The terms for flash self programming used in this Application note are described as follows e Flash macro service This refers to functions for manipulating the flash memory in devices e Flash environment This refers to the state in which the code flash can be operated by using the flash macro service There are special restrictions different from execution of normal programs A transition to other environment
46. ectronics product 5 Renesas Electronics products are classified according to the following two quality grades Standard and High Quality The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots etc High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems and safety equipment etc Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury artificial life support devices or systems surgical implantations etc or may cause serious property damages nuclear reactor control systems military equipment etc You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application for which it is not intended Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics 6 You should use the Renesas Electronics prod
47. eeeteaeeesaeeseneeee 18 6 1 2 Overview of Reprogramming Flash Memory c ccccecceeseeeeeeeeeeeeeeesaeseeeeeseeeeetaeeeeeeeee 19 6 1 3 Process from Startup to Normal Operation srrernvrnnnnvrnannvnnrnrrnnnnrrnnnnvnnerrnrnrrrennnrnnennnnennne 20 6 1 4 Flash Reprogram Processing after INTP1 Interrupt Input oeesnronannrnnonvvnrnnrrnnnnrnnrnnnnrnnn 20 6 1 5 Data Receive Processing mrrrnannrrnnnnvnnrrrrvnnnrnnnnnnnnenrennnrrennnnnnennrenrnrnennnrnnennnererresnsrnesnnnneennn 20 6 1 6 Processing after Data Deception Reprogramming asrrrannvnnnnvvnnnr vanen nrnnrnnnnrnrrenrnrnnennnnnrnnn 21 6 1 7 Communication Control Sequence mrrrrrannrrnnnnvnnenvvnnnrrrnnnnnnnenrenrnrrennrnnennnnrrrrreennrnnsnnnennnn 22 62 File Composito Misese a unike kneet 23 ee EE Ee TAIE A EAEE E A 24 64 Vanabl S erona n a a a a a A E R E 26 65 FONCIONS ere E E EE AAE AO EOE 27 6 6 Function Specifications rrrrnrvnnnnvnnnn vnr vnr nvnnnn vennen nr nnannnnnenrennnr are nnnnnnnenennranennrenennennveenn 28 6 7 Floweharsuxaahaanasdlesada E T cabs 35 6 7 1 Startup Routine Processing Lunds medeedenidtdlnsurn additiv 35 GLZ Man Froes crn aske ke 36 6 7 3 Switching Processing of Exception Handler Address mrrmnsnrvrnrnrrnnnnrnnnnnvnrvrrennnnrnnrnnenennne 37 6 7 4 Checksum Judgment of Reprogram Area msrenannvnnenvvnnnvrnnnnnvnnenvvnnnrrennnrnnrnnnnrrrrnnnnnrnnennneennn 38 6 7 5 Initialization of INTP1 Interrupt sononnrnrrnnnn
48. er uint32 tg index rx data Receive data storage location index Local variable uint8_t i Loop counter Argument flash_store_serial_data uint8 trx data Serial receive data y i g_buf_rx_data g_index_rx_data lt rx_data Store receive data from the serial g_index_rx data Line feed Yes return h d No r addr_buf amp amp n addr_buf No Start of line data is Yes as No he upper digit of record is 07 gt Vv g_index_rx_data lt 0 Yes Restore buffer storage position to the initial position y return Type of records 0 Data record End record Extended address record Start address record Extended linear address record Start linear address record Termination Data conversion Processing store processing Unexpected data default Do Nothing g 14 y Restore buffer storage position g index rx data 0 to the initial position y C return Figure 6 20 Store Processing for Receive Data 1 2 RO1AN1475EJ0100 Rev 1 00 Page 51 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ Obtain data length by using binary conversion hex2bin AA for loop i 0 i lt bin_size i bin size lt hex2bin g_buf_rx_data HEXDATA_POS_BYT
49. erase by calling the FSL_Erase function according to the specified argument After executing the FSL_Erase function calls the FSL_StatusCheck function and waits until the erase processing has been completed When the FSL_Erase function or the FSL_StatusCheck function returns the error value the return value will be stored in the g_error_fsl_status of the global variable The RET_ERR_FLASH_ERASE is returned to terminate Arguments uint32_t start block Start block number of the range to be erased uint32 t end block End block number of the range to be erased Return Value 0 RET OK Normal end 3 RET ERR FLASH ERASE Failure to erase flash write Outline Write processing from specified address Header Declaration int32 tflash write uint8_t src data addr uint32 tdst write addr uint32_t length Description Executes writing to the flash memory by calling the FSL Write function according to the specified argument After executing the FSL Write function calls the FSL StatusCheck function and waits until the write processing has been completed When the FSL Write function or the FSL StatusCheck function returns the error value the value will be stored in the g error fsl status of the global variable The RET ERR FLASH WRITE is returned to terminate Arguments uint8 t src data addr Start address of write data outside the on chip RAM uint32 t dst write addr Destination address of write data 4 word boundary uint32 t length Write data
50. ev 1 00 Page 57 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 6 7 22 UARTJO Message Transmit Processing Figure 6 27 shows the UARTJO Message Transmit Processing 7 uartjO_serial_tx_msg Argument char msg The number of character strings in character string group Local variable uint8_t pt Processing position pointer Initialize processing position pt lt msg ermination character of character string No pt 0 Vv Serial output from UARTJO URTJOFTX lt pt Update processing position Transmission has been completed URTJOSTRO amp 0x01 0 Figure 6 27 UARTJO Message Transmit Processing RO1AN1475EJ0100 Rev 1 00 Mar 18 2013 RENESAS Page 58 of 63 V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 6 7 23 UARTJO Receive Interrupt Processing Figure 6 28 shows the UARTJO Receive Interrupt Processing Local variable uint8 trx data Receive data uartjo serial rx isr aad eee tata rx_data lt URTJOFRX Program data store processing flash_store_serial_data rx_data flash_store_serial_data return Note Refer to 4 2 6 Precautions for Interrupts Generated During Use of FSL for application Figure 6 28 UARTJO Receive Interrupt Pro
51. f Programming with Asynchronous Serial Interface J UARTJ Table 6 5 Constants Used in the Sample Code Constant Name FLASH STATUS FLMDO HIGH Contents FLMDO High setting completion status valid pull up FLASH STATUS FSL ACTIVE FSL start status HEXDATA POS RECMARK Record mark position of hex data HEXDATA POS BYTE NUM Position for the number of bytes of hex data HEXDATA POS RECTYPE UPPER The upper digit position of hex data record type HEXDATA POS RECTYPE LOWER The lower digit position of hex data record type HEXDATA POS CODE TOP Start position of hex data code SIZE BUF RX DATA PORT BIT P1 4 Receive data store buffer size total of the followings Record mark 1 character The number of bytes 2 characters Location address 4 characters Record type 2 characters Code 512 characters max Checksum 2 characters Return r New line In 2 characters Bit position of port function setting P1 4 PORT BIT P2 3 Bit position of port function setting P2 3 PORT BIT P2 12 Bit position of port function setting P2 12 PORT BIT P2 13 RO1AN1475EJ0100 Rev 1 00 Mar 18 2013 Bit position of port function setting P2 13 Page 25 of 63 RENESAS V850E2 ML4 6 4 Variables Table 6 6 lists the Global Variables Table 6 6 Global Variables Variable Name uint8_t g_flag_start_flash_reprog Updating Program Code Using Flash Self Programming with Asyn
52. ge of write buffer 0 Change of write buffer 1 Receive data store buffer uint8_t g_buf_write_dataO SIZE_WRITE Write data store buffer 0 uint8_t g_buf_write_data1 SIZE_WRITE uint8_t g_flag_w_data_buf0_full uint8 tg flag w data buf1 full uint32 tg cnt store buf w data0 uint32 tg cnt store buf w datal uint8 tg status data buff Write data store buffer 1 Write buffer 0 full flag Write buffer 1 full flag Data counts of buffer 0 Data counts of buffer 1 Write buffer status g cnt store buf w data0 lt 0 g flag w data bufO full lt true g status data buff lt 1 le g ent store buf w datat 0 g flag w data buf1 full true g status data buff lt 0 Figure 6 21 Store Processing for Receive Data 2 2 RO1AN1475EJ0100 Rev 1 00 Mar 18 2013 RENESAS Page 52 of 63 V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 6 7 17 Text Binary Conversion Processing Figure 6 22 shows the Text Binary Conversion Processing hex2bin Arguments uint8_t upper Text binary data for the upper 4 bit uint8_t lower Text binary data for the lower 4 bit No The upper is numeric data The upper indicates 0 to 9 or A to F Yes Convert the upper into binary data and store conversion result in the upper Shift upper to left by 4 bits upper lt lt 4 The lower is numeric da
53. has been specified Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited The reserved addresses are provided for the possible future expansion of functions Do not access these addresses the correct operation of LSI is not guaranteed if they are accessed Clock Signals After applying a reset only release the reset line after the operating clock signal has become stable When switching the clock signal during program execution wait until the target clock signal has stabilized When the clock signal is generated with an external resonator or from an external oscillator during a reset ensure that the reset line is only released after full stabilization of the clock signal Moreover when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress wait until the target clock signal is stable Differences between Products Before changing from one product to another i e to one with a different part number confirm that the change will not lead to problems The characteristics of MPU MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern When changing to products of different part numbers implement a system evaluation test for each of the products Notice 1 Descriptions of circuits software and other related inform
54. hen the FSL_FlashEnv_Deactivate returns the error value the RET ERR FLASH DEAGTIVATE will be returned When the flash set flmdO function returns the value other than 0 the RET ERR FLASH FLMDO LOW will be returned to terminate Arguments None Return Value 0 RET OK Normal end 6 RET ERR FLASH DEACTIVATE Failure to terminate flash environment 8 RET ERR FLASH FLMDO LOW Failure to set FLMDO pin to High level flash set flmdo Outline Setting for FLMDO pin level Header Declaration int32 tflash set flmdO uint8 t level Description Sets FLMD control register to switch FLMDO pull up pull down control According to the reprogram sequence for the protect register substitutes H A5 for FLMD protect command register and then substitutes the value specified by the argument for FLMD control register After substituting the invert value substitutes the value specified again by the argument Checks that the register value has been changed to terminate Arguments uint8_t level 0x00 Set FLMDO pin to Low level 0x01 Set FLMDO pin to High level Return Value 0 RET OK Normal end 1 RET ERR Error in writing operation to FLMDCNT register flash store serial data Outline Store processing of receive data conversion Header flash h Declaration void flash store serial data uint8 trx data Description Converts the hex data to binary data every line and stores the converted data in the buffer When the hex data for one line is the dat
55. ing No asm cstart asm Output code of switch statement Auto None dir v850e2ml4_flash_upde Label size of switch table 2 bytes None er except handler ra Size threshold of sdata sbss section allocation Bytes ej mene Size threshold of sconst section allocation Bytes ej flash c Floating point calculating type Auto None ej tada ledi tannie Generate div divu instructions No led samp Use 32 bit branch in Hat No intp1 c wl Far Jump file names Far Jump file names 1 fenO can c 0 v850e2ml4 flash update can fip Dutput File om T amp Program Analyzer Analyze a Far Jump file names Pa Specifies the Far Jump file name The Far Jump file outputs the code that uses the jmp insteucfion V850E ES core or jarl32 instruction and jr32 instructionfy850E2 core V 850E2V3 architecture for branch instructons of functions described in the file If the function itself is in a range 2Mbyte or more where branching is not possib with the jarl or jr instruction and the cx command outputs an error compile processing is done again using this option The extension is fp This option corresponds to the lt far_jump option of the cx command Path Edit X Common Options Compile Options Lir Path One path per one line Ga Output Fe50e2ml4_flash_update fip Browse cous Figure 4 5 Location of Far Jump Calling Function File uartj0_serial_tx sg Far jump option specification is required because the uartj0 serial tx m
56. inline expansion of library Merge string literals Preprocess CLanguage T CO Program Analyzer Analyze Use prologue epilogue ibrary Specifies whether to process the prologues and epilogues of functions through runtime library calls This option corresponds to the lt pro_epi_runtime option of the cx command Common Options Compile Options 4 Link Options ROMize Options Hex Output Options Output Figure 4 3 Location of Setting Non Use of Prologue Epilogue Library RO1AN1475EJ0100 Rev 1 00 Page 10 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 4 2 3 Setting for ROMization of Section in RAM The setting for CubeSuite is required for ROMization to expand the section in RAM Select CX Built Tool under the Project Tree and click ROMize Options tab in the Property From Text sections included rompsec section specify the section required for ROMization out of the sections to be assigned in RAM Write the section names one section per line in the Text Edit window shown by clicking the button on the right Figure 4 4 shows the Setting for Romization of Section in RAM File Edit View Project Build Debug Tool Window Help set ES XxX DSBIVO RSA SORE E t A CX Property v850e2ml4 flash update Dutput File uPD70E4022 Microcontro GE CX Build Tool S Start symbol of rompsec section 85
57. ivate function In case of normal end sets the bit which indicates that the flash environment has been started to the g flag flash status of the global variable and then the RET OK is returned to terminate When the FSL FlashEnv Activate function returns the value other than the FSL OK the return value will be stored in the g error fs status of the global variable The RET ERR FLASH ACTIVATE is returned to terminate Arguments None Return Value 0 RET OK Normal end 1 RET ERR FLASH ACTIVATE Failure to start flash environment flash modecheck Outline Checking processing of FLMDO pin using FSL Header Declaration int32 t flash modecheck void Description Executes checking of FLMDO pin by calling the FSL ModeCheck function In case of normal end the RET OK will be returned to terminate When the FSL ModeCheck function returns other than the FSL OK the return value will be stored in the g error fsl status of the global variable The RET ERR FLASH MODEGCHECK is returned to terminate Arguments None Return Value 0 RET OK Normal end 2 RET ERR FLASH MODECHECK Failure to check FLMDO pin RO1AN1475EJ0100 Rev 1 00 Page 30 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ flash_erase Outline Erase processing of specified block Header Declaration int32_t flash_erase uint32_t start_block uint32 t end block Description Executes the block
58. ject Tree and click Compile Options tab in the Property Click button shown on the right side of Far Jump file names in Output Code and write the path of the created far jump calling function list file Note that fjp is recommended for the extension of the far jump calling function list file In the far jump calling function list file write one function name per line The function name should have _ underscore at the beginning of the function name with C language Note that if all_interrupt is written all interrupt handler functions are subject for the far jump calling functions For creation of far jump calling function file refer to 3 3 3 far jump function in CubeSuite V1 03 00 Integrated Development Environment User s manual Coding CX compiler Figure 4 5 shows the Location of Far Jump Calling Function File Figure 4 6 shows the Example of Creation of Far Jump Calling Function File RO1AN1475EJ0100 Rev 1 00 Page 12 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ File Edit View Project Build Debug Tool Window Help Stat A nh oe a SOLER Project Tree a x qe Property f main c 298 Ay CX Property v850e2ml4 flash update Debug informabon PE uPD70F 4022 Microcontro J Optimization Me a K reprocess S 850E2 E1 JTAG Debug Language Character Encoding A ID File E Output Code S Startup Structure pack
59. length word unit 4 word boundary MAX on chip ROM size Return Value 0 RET OK Normal end 4 RET ERR FLASH WRITE Failure to write flash iverify Outline Internal verification of specified block Header Declaration int32 tflash iverify uint32 i start block uint32 tend block Description Calls the FSL IVerify function according to the argument to execute the internal verification of specified block After executing the FSL_IVerify function calls the FSL StatusCheck function and waits until the internal verification has been completed When the FSL IVerify function or the FSL StatusCheck function returns the error value the return value will be stored in the g error fsl status of global variable Returns the RET ERR FLASH IVERIFY to terminate Arguments uint32 t start block Start block number of the range for verify check uint32 t end block End block number of the range for verify check Return Value 0 RET OK Normal end 5 RET ERR FLASH IVERIFY Failure of internal verification RO1AN1475EJ0100 Rev 1 00 Page 31 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ flash_end Outline Termination processing of flash environment Header Declaration int32_t flash_end void Description After terminating the flash environment by calling the FSL_FlashEnv_Deactivate function sets FLMDO pin to Low level by calling the flash_set_flmd0 function W
60. ler address switching function when using interrupts The setting for the exception handler address switching function is executed by the software Refer to 6 7 3 Switching Processing of Exception Handler Address for more details Initialization of the program area in the RAM allocation destination When allocating a program to RAM on the V850E2 ML4 the 16 byte boundary area H xxxx_xxx0 to H xxxx_xxxF including the program area in the allocation destination is required to be initialized cleared to zero In this sample program the initialization is executed during the startup routine Refer to 4 2 5 Setting for Startup Routine for its change and 6 7 1 Startup Routine Processing for its details Setting for ROMization of the section to expand the program in RAM Regarding to the setting for ROMizaton on the CubeSuite refer to 4 2 3 Setting for ROMization of Section in RAM e The execution of the flash functions are disabled in the interrupt handler e The far jump specification for the CX compiler when calling function allocated to the address separated more than 2 MB In this sample program the far jump option is specified to the function allocated in RAM which is called from the flash memory Refer to 4 2 4 Setting for Far Jump Function for more details e Saving setting and restoring the gp register and the ep register when accessing to the global variables with C language in the interrupt handler The above mentioned operatio
61. message INTP1 interrupt detection uartjO_serial_tx_msg gt INTP1 detected 7 Flash reprogram processing flash_reprogram 4 Output message message corresponds to reprogram result Transmit message Messages according to reprogram result uartjO_serial_tx_msg Reset request for success Message corresponding to an error eturn value of flash Error When failed to reprogram output debug eprogram processing information Transmit message Error code uartjO_serial_tx_msg Write error address Infinite loop for reset wait Figure 6 5 Main Processing RO1AN1475EJ0100 Rev 1 00 Page 36 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 6 7 3 Switching Processing of Exception Handler Address Figure 6 6 shows the Switching Processing of Exception Handler Address except_handler_addr_set Argument S uint32 t base addr Setting value of exception handler base address Lower 12 bit of base addris 0 Yes Switch to EHSWO bank Idsr 31 H 00000010 Set register bank to H 10 C return RET ERR Vv Set transfer value for EH BASE register ldsr 3 base addr Set SW BASE register y Transfer Idsr 0 H 00000001 Write 1 into SW CTL SET y C return RET OK Note When switching the exception handler address the period from th
62. nd block fsl status FSL BUSY Wait for write completion Vv Check previously specified fsl_status lt Return value of statusFSL_StatusCheck FSL_StatusCheck AA St re Base st t g_error_fsl_status lt fsl_status y otuin RET_ERR_FLASH_VERIFY Global variable C return RET OK 7 fsl_status_t g_error_fsl_status Store FSL error Local variable fsl_status_t fsl_status Return value of FSL function Figure 6 17 Internal Verification of Specified Block R01AN1475EJ0100 Rev 1 00 Page 48 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 6 7 14 Termination Processing of Flash Environment Figure 6 18 shows the Termination Processing of Flash Environment flash_end Local variable int32_t ret Return value Vv ret RET OK Global variable Initialize return value uint8 tg flag flash status Flash environment status Flash environment Yes g flag flash status amp FLASH STATUS FSL ACTIVATE 0 has been started Vv Terminate flash environment FSL_FlashEnv_Deactivate y ne Update flash environment status Set error to return value g_flag flash status amp FLASH_STATUS_FSL_ACTIVATE k RET_ERR_FLASH_DEACTIVATE LMDO pin has been Yes g_flag_flash_status amp FLAS
63. ns might be required when accessing to the data section in the interrupt handler Refer to 4 2 6 Precautions for Interrupts Generated During Use of FSL for more details In regard to the function specification and the system configuration of the FSL refer to the reference application note V850 Microcontroller Flash Self Programming Library Type05 In regard to section specification to the CX compiler allocation address setting ROMization and far jump option specification on the CubeSuite refer to CubeSuite V1 03 00 Integrated Development Environment User s manual Build CX compiler In regard to switching the exception handler address refer to V850E2 User s Manual Architecture RO1AN1475EJ0100 Rev 1 00 Page 7 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 4 2 1 Setting for Link Directive File The link directive file creation and the CubeSuite setting are required to change the section assignment When creating the link directive file using text editor without the CubeSuite menu the Cube Suite setting is required Drag the link directive file from explore and drop it in blank area the bottom part of the Project Tree In the CubeSuite the file which has extension of dir or dr is considered as the link directive file Select CX Build Tool under the Project Tree and click Link Options tab in the Property Open Input File
64. ogram provides a double structured write buffer Regarding Storing write data during data receive processing and Writing to the flash memory each processing should be executed by switching the write buffer to be used 6 1 5 Data Receive Processing After entering in the wait state for data reception the UARTJO receive interrupt is generated every time the serial communication data is received from the host When the UARTJO interrupt is generated the received data will be stored into the serial receive data store buffer receive buffer in the order received When receiving the line feed code the data that has been stored in the receive buffer is considered as a record data for one line The following data receive processing is executed to extract write data necessary for updating The data receive processing is described as follows referring to Figure 6 2 that shows the Example of Data with Inter Expanded Hex Format The data shown in Figure 6 2 is color coded depending on its function 04000005000013C81C 020000040000FA 20800000E0570584CASEEFFF 605F0484E0670583CC6EEFFF 606F0483407640FF2E7F054609 20802000CF 86EFFF408E40FF71870546E0970580929E1000609F0480405681FF6A070082E5 208040002B06FAFF0000406681FF6C5F4082206EFF3F606F00C44076FFFFOE7F66608F86C8 1A8060000F00408EFFFF518766604096FFFFD2BF6660019A609FC4C57F00C0 0000000LFF Figure 6 2 Example of Data with Inter Expanded Hex Format RO1AN1475EJ0100 Rev 1 00 Page 20 of 63 Mar 18
65. onous Serial Interface J UARTJ 1 Specifications In this Application note a program code update is performed by reprogramming on chip flash memory using flash self programming Serial communication with an arbitrary device enables to receive a program file data for update with Intel expanded hex format type and reprogram a program code in the on chip flash memory area Table 1 1 lists the Peripheral Functions and Their Applications and Figure 1 1 shows the System Configuration Table 1 1 Peripheral Functions and Their Applications Flash memory on chip flash memory Program storage area Flash macro service Reprogramming flash memory Asynchronous serial interface J UARTJ Reprogramming data Message communication V850E2 ML4 CPU board Type ROKOF4022C000BR V850E2 ML4 Operate Flash macro service _ gt Flash memory Serial Readout communication Execute flash function Host device Serial FSL communication UARTJ Serial port RS 232C On chip RAM Program data g Se gt transceiver gt P2_12 RXDOF P2_13 TXDOF Reprogram flash Message Store receive data FSL Flash Self Programming Library Figure 1 1 System Configuration RO1AN1475EJ0100 Rev 1 00 Page 4 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Inte
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67. r created assembler source file in which the startup routine is written to register on the CubeSuite project Right click startup in file under the Project tree then the menu will appear to add the startup routine source file Figure 4 7 shows the Location of Startup Routine Figure 4 8 shows the Example of Startup Routine Preparation Excerpt from cstart asm File Edit View Project Build Debug Tool Window Help Q sn AJia OC BSA SORES Project Tree x 4 main c s Startup Property v850e2ml4 flash update E Category Information uPD70F 4022 Microcontro Category name Startup A CX Build Tool S 850E2 E1 JTAG Debug D Program Analyzer Analyze Category name I File This is the name of this category The category name can be between 1 and 200 characters EE Startup D Also the category name colored in gray is fixed a QD Ktddre Ed Remove from Project Shift Del Add New File tS Copy Ctrl C ia Add New Category 4 Paste Ctrl V ale Rename F2 Property Figure 4 7 Location of Startup Routine RO1AN1475EJ0100 Rev 1 00 Page 14 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ Excerpt from cstart asm Change the stack size to the one required for execution of FSL and user program STACKSIZE RESET cseg jr 4 __tp TEXT tp set tp register __gp_DATA gp
68. reprogram termination processing ret end lt flash end flash end Yes Change return value to error in Return without change when termination processing an error occurs before termination processing C Figure 6 10 Flash Reprogram Processing 1 2 ret lt ret end return ret RO1AN1475EJ0100 Rev 1 00 Mar 18 2013 Page 41 of 63 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ Global variables uint8 tg flag w data bufo full Write buffer 0 full flag uint8 tg flag w data buft full Write buffer 1 full flag uint8 tg status data buff Write buffer status uint8 tg status end record End record receive flag uint16 tg chksm size Program code size of write data uint16 tg chksm data Checksum data of write data uint8 tg buf write data0 SIZE WRITE Write data store buffer 0 uint32 tg cnt store buf w data0 Data counts of write data store buffer 0 uint8 tg buf write datai SIZE WRITE Write data store buffer 1 uint32 tg cnt store buf w data Data counts of write data store buffer 1 uint32 tg index recv data Specify receive data storage location Local variable E A ive data fsl u32 write_addr Write address rror in receive data Change return value to error in ret g status store error termination processing uffer 0 can be written into flash memory Yes uffer 1
69. rface J UARTJ 2 Operation Confirmation Conditions The sample code accompanying this application note has been run and confirmed under the conditions below Table 2 1 Operation Confirmation Conditions MCU used V850E2 ML4 Operating frequency Internal system clock foyk 200MHz P bus clock fect 66 667MHz Operating voltage Positive power supply for external pins EVpp 3 3V Positive power supply for internal units IVpp 1 2V Integrated development environment Renesas Electronics Corporation CubeSuite Ver 1 02 01 C compiler Renesas Electronics Corporation CX compiler package Ver 1 21 Compile option Cf4022 oDefaultBuildiv850e2ml4 flash update uartj imf Xobj path DefaultBuild g Xpro epi runtime off IC WorkSpacelv850e2ml4 flash update uartjlinc IC WorkSpacelv850e2ml4 flash update uartlF SL Xdef var Xfar jump v850e2ml4 flash update uartj fjp Xlink directive v850e2ml4 flash update uartj dir Xstartup DefaultBuild cstart obj Xide Xmap DefaultBuildiv850e2ml4 flash update uartj map IFSL T05 REC R32 LC WorkSpacelv850e2mi4 flash update uartilFSLVib Xrompsec text FSL CODE text Xrompsec text FSL CODE ROMRAM text Xrompsec text FSL CODE RAM text Xrompsec text FSL CODE RAM USRINT text Xrompsec text FSL CODE RAM USR text Xrompsec text FSL CODE RAM EX PROT text Xrompsec_text INTP1RAM text Xrompsec_text INT TAUAOIORAM text Xrompsec_text INTUARTJOIRRAM text Xhex DefaultBuild v850
70. rrnnnnvnnenrrvnnnrrnnnnnnnenrennnrrennnrnnennenennrnesnnrnnsnnneennn 39 6 7 6 INPT1 Interrupt Processing rrannvnnnnvvnrnr vnr nrnnnnnvnnrnrrennnr nen nnnnennennnrnennnrnnennnnnnnrneennrnssnnnennnn 40 6 7 7 Flash Reprogram Processing rsrvnanvvnrnrrvnnnrrnannnvnrnrrennnrnvennnnnennennrrnesnnrnnnennesnnrnesnnnnnennenenn 41 6 7 8 Initialization of Flash Environment eernronennvnnonnvnnenvvnnnnrrnnnnvnnenvnnnnrrennnrnnsnnnnrnrrreennrnnsnnnernnn 43 6 7 9 Start Processing of Flash Environment ussrnnannvnnonrnnnnvrvnnnvnnnonvnnnnrrennnrnnennnnrrrrenssrrnssnnnernnn 44 6 7 10 Checking Processing of FLMDO Pin Using FSL rrurnrrnannvnnnnnvnnnrrrnnnnvnnennrnrrrrnennrrnsnnnnernnn 45 6 7 11 Erase Processing of Specified Block rurnrrnannvnnonvvnnnr vnr nvnnnrnvennnrrennnrnnrnnnererrenrnrnensnnneennn 46 RO1AN1475EJ0100 Rev 1 00 Page 2 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 6 7 12 Write Processing from Specified Address cceccceceeeceseeeeeeeeeeceaeeeseaeeeeeeeseeeeetaeeeeeneeee 47 6 7 13 Internal Verification of Specified BlOCK cceeececeeeeeceeeeeeeeceeeeeeeaeeesaeeeeeeeeseaeeseaeeeeneeeaas 48 6 7 14 Termination Processing of Flash Environment 0 ccccccsccceeceeceeeeeeeeeeseeeeeseaeeseaeeeeeeeeaas 49 6 7 15 Setting for FLMDO Pin Level iriiritia aiaa 50 6 7 16 Store Processing for Receive Data rrrrn
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72. sg _flash_reprogram function allocated to RAM is also called by the main function in ROM fall interrupt aa IFar jump option specification is required because the flash reprogram Ifunction allocated to RAM is also called by the main function in ROM IAll interrupt handler functions are subject for far jump specification IThe interrupt handler is allocated to RAM but the far jump option specification is required because Figure 4 6 Example of Creation of Far Jump Calling Function File RO1AN1475EJ0100 Rev 1 00 Page 13 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 4 2 5 Setting for Startup Routine The stack used in this sample program requires larger area than the stack size 512 bytes which is set in the standard startup routine In the standard startup routine the function _rcopy ROMize processing is executed to develop the data with initial value and the program allocated in RAM However when executing the ROMize processing for the program area initialize clear to 0 the 16 byte boundary area of program destination before executing rcopy In this sample program the initialization processing for the stack size change and the 16 byte boundary area of program destination is added for the assembler source file cstart asm in which the standard startup routine is written When switching the standard startup routine create the use
73. sh_reprog Start reprogramming flash memory l Set flag to start reprogramming g_flag_start_flash_reprog lt 1 flash memory l return Note Refer to 4 2 6 Precautions for Interrupts Generated During Use of FSL for application Figure 6 9 INTP1 Interrupt Processing RO1AN1475EJ0100 Rev 1 00 Page 40 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 6 7 7 Flash Reprogram Processing Figure 6 10 and Figure 6 11 show the Flash Reprogram Processing flash_reprogram I Initialize variables Initialize flash environment flash_init Yes Start processing for flash environment flash_activate Ye Check FLMDO pinflash_modecheck g flag w data bufo full lt false g flag w data buf1 full lt false g status data buff 0 g status end record 0 ret lt flash init ret lt flash activate ret lt flash moecheck g chksm size lt 0 g chksm data lt 0 9 cnt store buf w data0 0 9 cnt store buf w datat 0 Global variables uint8 tg flag w data bufo full uint8 tg flag w data buf1 full uint8 tg status data buff uint8 tg status end record uint16 tg chksm size uint16 tg chksm data uint8 tg buf write data0 SIZE WRITE uint32 tg cnt store buf w data0 uint8 tg buf write data1 SIZE WRITE uint32 tg
74. t PC should be connected by the serial cable Refer to V850E2 ML4 CPU board ROKOF4022COO0BR User s Manual for more details about the CPU board jumper settings and connectors Table 7 1 Jumper List 1 2 default 2 3 used in this program P VBUS An operation procedure with the VT100 compatible terminal emulator is described as follows First of all activate the terminal emulator and set for serial port connection Select the number connected to the board for the serial port number of the terminal emulator The setting values for serial ports are listed in Table 7 2 RO1AN1475EJ0100 Rev 1 00 Page 61 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ Table 7 2 Serial Port Setting Item Setting Value Bit sec 9600bps Data bit 8bit Parity None Stop bit 1bit Flow control None After the above setting is completed turn on the through board and the board for this sample program When the board for this sample program is activated the V850E2 ML4 transmits a message Generate INTP1 interrupt for transition to flash programming event to the host Then the V850E2 ML4 executes the program stored in the reprogram area and flashes the LEDs on the board with the fixed period When the INTP1 switch SW4 on the board is pushed in this condition the V850E2 ML4 transmits a message gt INTP1 detected to the host When the INTPI
75. t a time The checksum judgment function adds a program one byte at a time with the start address H 0000 8000 in the reprogram area for the number of program data size The calculation result is compared with the checksum judgment data calculated when received a data Stored in the last 16 byte area of MasterPRG text Refer to 6 1 6 for the details The program in the reprogram area will be executed when the calculation result matches the said data and the one in the spare area will be executed if there is a difference 6 1 4 Flash Reprogram Processing after INTP1 Interrupt Input When the INTP1 interrupt rising edge detection INTP1 switch push down on the board is generated moves to flash reprogram processing In the flash reprogram processing the message gt INTP1 detected is transmitted to the host to erase the reprogram area Then the message Send subroutine code to update program in Intel expanded hex format is transmitted to the host to enter wait state for data reception from the host In the wait state for data reception flag variables are used by polling to detect if the flash write is enabled or disabled When receiving program file data for update with Intel expanded hex format from the host the data receive processing later described is executed and the data is stored into the write data store buffer write buffer When the write buffer becomes full the buffer data will be written to the flash memory This sample pr
76. ta The lower indicates 0 to 9 or A to F Convert the lower into binary data and store conversion result in the lower p C return upper lower C return RET_ERR Figure 6 22 Text Binary Conversion Processing RO1AN1475EJ0100 Rev 1 00 Page 53 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 6 7 18 TAUAO Initialization for LED Blink with Fixed Cycle Sample Function in Reprogram Area and Spare Area Figure 6 23 shows the TAUAO Initialization for LED blink with Fixed Cycle Sample Function in Reprogram Area and Spare Area a taua0 led sample ve taua0 led spare y Set port functions PMC1 amp PORT_BIT_P1_4 Output mode setting for LEDO port P1_4 PM1 amp PORT_BIT_P1_4 PDSC1 amp PORT_BIT_P1_4 P1 PORT_BIT_P1_4 y TAUAOCMORO lt H 0000 Set TAUAOGMORO register TAUAOCKS bit B 00 Select operation clock CKO TAUAOSTS bit B 000 Software trigger TAUAOMD bit B 0000 Interval timer mode Do not output INTTAUAOIM y TAUAOTPSO lt H FFF7 Set TAUAOTPS register TAUAOPRSO bit B 0111 Specify CKO clock division ratio PCLK 2 7 y Set TAUAOCDRO register TAUAOCDRO lt H FFFF Compare value setting y Enable interrupt level setting __set_il 16 INTTAUAOIO set il set il 0 INTTAUAOIO y re
77. tion of UARTJO flash h void uartjO_serial_init void After initializing the ports of UARTJO executes initial setting for UARTJO Then sets the interrupt level and enables the interrupts to enable UARTJO operation None None Initialization of UARTJO ports void uartjO_serial_port_init void Initializes the ports to use P2 12 pin for reception and P2 13 for transmission in serial communication None None UARTJO message transmit processing flash h void uartjO_serial_rx_isr void Provides serial output of the character string specified by the argument from UARTJO char msg None Transmit message character string UARTJO receive interrupt processing void uartj0 serial rx isr void Specifies the received data to the argument and executes program data store processing flash store serial data function None None UARTJO status interrupt processing void uartj0 serial status isr void Clears the status as UARTJO interrupt processing None None Page 34 of 63 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 6 7 Flowcharts 6 7 1 Startup Routine Processing Figure 6 4 shows the Startup Routine Processing Startup processing EE Initialize the following criterial pointer registers Initialize pointer registers when accessing to memories data and instructions tp register gp register sp register ep register CTBP register
78. turn t Figure 6 23 TAUAO Initialization for LED blink with Fixed Cycle Sample Function in Reprogram Area and Spare Area RO1AN1475EJ0100 Rev 1 00 Page 54 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 6 7 19 TAUAO Interval Timer Interrupt Processing Figure 6 24 shows the TAUAO Interval Timer Interrupt Processing C taua0 iO interval timer isr l LED port output inversion P1 PORT_BIT_P1_4 return Note Refer to 4 2 6 Precautions for Interrupts Generated During Use of FSL for application Figure 6 24 TAUAO Interval Timer Interrupt Processing RO1AN1475EJ0100 Rev 1 00 Page 55 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ 6 7 20 Initialization of UARTJO Figure 6 25 shows the Initialization of UARTJO uartjo serial init Ga af Y Initialize UARTJO port uartjO_serial_port_init Vv URTJOCTL2 lt H 0D90 Baud rate 9600bps se URTJOCTL1 lt H 5102 Data bit length 8 bits No parity bit The number of stop bits 1 bit LSB first transfer y Enable interrupt level setting __ set il 1 INTUARTJOIS setil set il 0 INTUARTJOIS _ setil _ setil Enable UARTJO operation ETO TASTED I return 0 2 INTUARTJOIR 0 INTUARTJOIR
79. ucts described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges 7 Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or systems manufactured by you 8 Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics
80. unnrnnannvnnenrvnnnrrrnnnnvnnenvennnrrennnrnnennnererrenennrnnennnernnn 51 6 7 17 Text Binary Conversion Processing ccsccceeceeeeeeeeeeeeeeeeeeeeeesaeeeseaeeseeeeeseaeeesaeeeeneeee 53 6 7 18 TAUAO Initialization for LED Blink with Fixed Cycle Sample Function in Reprogram Area and Spare Area Luinins nnigresseran kresne s2acqstestap saxdvaccead a a a aaa a 54 6 7 19 TAUAO Interval Timer Interrupt ProceSSing c ccccceeeeeeeeeeeeeeceeeeesaeseeeeeseaeeesaeeeeeeeeaas 55 6 7 20 Initialization Of UARTJO 000 ee ccecccceesneceececnneeececsaeeeeeesaeeecessaeeeeeesaeeeeesaeeeeeessaeeeeesseeeeeees 56 6 7 21 Initialization Of UARTJO Ports 0 cccsccccesseeeeeeeseeeeeeeeceeeeeesaeeeesseaeeeeesseeeeseseeeeeesseeeeeees 57 6 7 22 UARTJO Message Transmit Processing cc ccceeceeeeeeeeeeneeeeeeeecaeeeseaeeeeaeeseeeesaeeeeaeeeee 58 6 7 23 UARTJO Receive Interrupt ProceSSing ccccccceecceceeeeeeneeceeeeecaeeesaaeseeeeeseeessaaeeeeneeeaas 59 6 7 24 UARTJO Status Interrupt Processing ccccecececeeeeececeeeeeeeeeeeeceaeeeseaeseeeeeseeeeeaeeeeaaeeee 60 2 Operation Ovenview sin 4 c h waitin sgis hein detente ei herniated ada 61 8 Sample Gode nude baner india de 63 9 Reference DOCumentS mannnnnnnrnnnnronannrnnnnnennnnrrnannnnnnnnennrnrennnrnnenannnnnnennr a aaia adadad iiie 63 R01AN1475EJ0100 Rev 1 00 Page 3 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchr
81. vBSDe2mld flash update 8 gm dir gt Pts M AX VE50E2 TUTAG Debug EN p Program Analyzer Analyze Library Link Map 3 Fie Symbol Information Others l Using link directive fle This is the link directive file to be used for linking This option corresponds to the Xlink_directive option of the cx commbnd Sa Common Options Compile Options Link Options ROMize Options Hex Output Options Output Drag the link directive file which has dir or dr Check here for its extension from explore etc and drop it in the blank area under the Project Tree to register Figure 4 1 Location of Link Directive File RO1AN1475EJ0100 Rev 1 00 Page 8 of 63 Mar 18 2013 RENESAS V850E2 ML4 Updating Program Code Using Flash Self Programming with Asynchronous Serial Interface J UARTJ SCONST LOAD R sconst PROGBITS A sconst CONST LOAD R V0x00001100 2 on i FSL_CONST const PROGBITS A FSL_CONST const FSL area Create section for FSL area in ROM TEXT LOAD RX pro_epi_runtime PROGBITS AX pro_epi_runtime text PROGBITS AX text J Spare area SparePRG LOAD RX V0x00006000 Create segment and section for spare area in ROM SparePRG text PROGBITS AX V0x00006000 SparePRG text Hi Reprogram area MasterPRG LOAD RX V0x00008000 MasterPRG text PROGBITS AX V0x00008000 MasterPRG text Create segment and section

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