Migration from IBM 750FX to MPC7447A
Contents
1. 91 yonoL J0199A 19 821 19 821 J0199A UOljgAJOseH uones 5 2 94222 gia 82 585 Beq 821 mopeys Sus suononasul 7 19 821 uononasul enss L Anu3 e enss Hdd zuun suoneis enssi g Au3 9 enss 91 uonels JoBo1u 10129A zuun JoBo1u 10129A wun 10129A uoneis uoneis uoneis 9114 HA enss g Ruu3 v enss Suononuisul dn sejejduio Anua 91 anand suononuisul 19 96 5 yoyedsiq Anu3 8v02 1 ulo Anu3 821 1 anenH uononysu j yun uononasu BuisseooJd youesg epoiq2. S4Q Aouenbes4 orueu q e e e 42019 Jejueuie10eq 4euno eseg Sul 4 Feature Overview 2 MPC7447A igure F from IBM 750FX to MPC7447A Rev 1 ion t igra M Freescale Semiconductor Feature Overview 2 1 1 Integer Units and 02 denote fixed point units 1 and 2 which the complex and simple integer units respectively The multiply and divide instructions of IU1 are multi cycle whereas all other operations are complete in a single cycle Both the integers operate on 32 32 bit registers Table 1 shows the operations that each fixed unit can perform Each unit consists of three units adder comparator logical and shift rotate units In addition to these standard units FXU1 also has a multiply divide unit Table 1 Fixed Point Unit Operations 101 102 shift logical functions Yes Yes Multiply divide Yes No Like the 750FX the MPC7447A has one complex integer unit with the same functionality as IU1 However it has three simple integer units like the U2 instead of one A good compiler can take advantage of these features when presented with a combination of instructions with multi cycle latencies that would tie up two of the integer units the remaining unit
3. Freescale Semiconductor 7 Feature Overview Maximum four instruction fetch per dock cycle Maximum three instruction dispatch Decode Dispatch per dock cycle VR Issue FPR Issue Queue Queue FIQ VPU EO VPU E1 VIU1 Maximum three instruction completion per clock cycle Complete Write Back Figure 4 MPC7447A Pipeline Diagram 2 3 L1 and L2 Cache Table 2 summarizes the differences between the 750FX and the MPC7447A inL1 and L2 cache configuration Table 2 L1 L2 Cache Configurations 750FX MPC7447A L1 Size configuration 32K byte instruction 32 Kbyte data 32 Kbyte instruction 32 Kbyte data eight way set eight way set associative associative Memory Coherency MEI data only MESI data only Migration from IBM 750FX to MPC7447A Rev 1 8 Freescale Semiconductor Table 2 L1 L2 Cache Configurations continued Feature Overview Locking Completely By way Replacement policy Pseudo least recently used PLRU Pseudo least recently used PLRU Per page block write configuration Write back or write through data Write back or write through data L2 Size configuration 512 Kbyte two way set associative Two 32 byte blocks line 512 Kbyte eight way set associative MPC7447A Two 32 byte blocks line Memory coherency MEI MESI Locking Yes independently by way C
4. 162 new powerful arithmetic and conditional instructions for intra and inter element that is parallelism support e Four operands per instructions three sources and one destination e Pipelined execution units to give the following One cycle latency for simple and permute operations 3 4 cycle latency for compound complex operations No penalty for issuing AltiVec Integer instruction mix The new instructions allow vector SIMD operations on 128 bit wide vector registers VRs through any of the four Alti Vec execution units permute simple complex and float which have two one four and four stage pipes respectively These 128 bit VRs can be used as a single 128 bit quantity but also to provide varying levels of parallelism to give a maximum of 16 operations per instruction on 8 bit quantities or to put into a more comparable format four 32 bit integer based operations per instruction These different levels of parallelism 16x8 bit 8x16 bit or 4x32 bit can be seen in Figure 7 Migration from IBM 750FX to MPC7447A Rev 1 Freescale Semiconductor 13 7447A Specific Features Figure 7 AltiVec Degrees of Parallelism 3 2 MESI vs MEI Comparison Another important difference to note is the difference between the MEI cache coherency features on the 750FX and the enhanced MESI capability of the MPC7447A These protocols are used as a coherency mechanism in SMP symmetric multi
5. CLKOUT selection HID1 9 11 1 PLLO internal configuration select HID1 PIO PLL select HID1 PS PLLO configuration HID1 PCO PLLO range select HID1 PRO PLL1 configuration HID1 PC1 PLL1 range select HID1 PR1 Note 1 000 Factory use 001 PLLO core clock freq 2 010 Factory use 011 PLL1 core clock freq 2 100 Factory use 101 Core clock freq 2 The PLL range is configured according to the frequency ranges shown in Table 6 Table 6 PLL Range Configuration PLL RNG 0 1 PLL Frequency Range 00 default 600 MHz 900 MHz 01 fast 900 MHz 1 0 GHz 10 slow 500 MHz 600 MHz 11 reserved Reserved Migration from IBM 750FX to MPC7447A Rev 1 Freescale Semiconductor 21 Programming Model 4 2 1 2 DFS Configuration The configuration of DFS is comparatively simple given that it does not use dual PLL DFS allows the core clock frequency to be halved To illustrate the simplicity of the DFS features 1 The frequency is switched completely the fly 2 This change occurs in only one clock cycle 3 It requires zero idle time or operations before or during the transition Considering the following equation P Cx V x f Pps Where P core power consumption effective capacitance approx as a constant V core voltage Vpp f core frequency Pps deep sleep mode power consumption Excluding deep sleep mode power consumption which is a minimum fixed p
6. Enable interrupt when RTCSELECT defined bit transitions off on MMCRO INTONBITTRANS MMCRO TBEE Threshold value 0 63 which can be varied to get to characterize the events occurring above the threshold MMCRO THRESHOLD MMCRO THRESHOLD Enable interrupt due to do PMC1 overflow MMCRO PMC1INTCONTROL MMCRO PMC1CE Enable interrupts due to PMCn overflow MMCRO PMCINTCONTROL MMCRO PMCnCE Trigger counting of PMC2 4 after PMC1 overflows or after a interrupt is signaled MMCRO PMCTRIGGER MMCRO TRIGGER 4 PMC1 event selector 128 events MMCRO PMC1 SELECT MMCRO PMC1SEL PMC2 event selector 64 events MMCRO PMC2SELECT MMCRO PMC2SEL MSR PM on the 750FX corresponds to MSR PMM on the MPC7447A For all PMCs not just PMCn 1 2 3 Enable overflow interrupts on PMC1 4 for 750FX and PMC1 6 for MPC7447A 4 Trigger counting of PMC2 6 for MPC7447A Table 12 750FX MMCR1 to MPC7447A Function 750FX MPC7447A event selector 32 events MMCR 1 PMCSSELECT MMCR1 PMCSSEL PMC4 event selector 32 events MMCR 1 PMCASELECT MMCR1 PMCASEL PMC5 event selector 32 events N A MMCR1 PMCSSEL PMC6 event selector 64 events N A MMCR1 PMC6SEL 1 5 and PMC6 not present in 750FX Migration from IBM 750FX to MPC7447A Rev 1 26 Freescale Semiconductor Hardware Considerations As me
7. SPR 25 SPR 930 IBATeL SPR565 DBAT6L SPR573 Sampled Instruction Condition Register IBAT7U SPR 566 DBAT7U SPR574 Address CR IBAT7L SPR567 DBAT7L SPR575 USIAR SPR 939 Exception Handling Registers Monitor Control SPRGs Data Address Save and Restore UMMCRO SPR 936 eee ean SPRGO SPR272 Register Registers UMMCR1 SPR 940 Control Register SPRG1 SPR 273 DAR SPR 19 SRRO SPR 26 2 SPR 928 FPSCR SEDGE 274 SPRG3 SPR275 DSISR AltiVec Registers SPRG4 SPR 276 DSISR Vector Save Restore Vector Registers SPRGS5 SPR 277 Register VRO SPRG6 SPR 278 VRSAVE SPR 256 SPRG7 SPR 279 Vector Status an Cache Memory Subsystem Registers Control Register Load Store Instruction Cache L3 Private Memory VSCR Control Register Interrupt Control Register 1 1 LDSTCR SPR 1016 Register L3PM SPR 983 Memory Subsystem L_USTRE L3 Cache Control Miscellaneous Registers Status Control L2 Cache Control Register Time Base Data Address Registers Register L3CR SPR 1018 For Writing Breakpoint Register MSSCRO SPR 1014 L2CR SPR 1017 S Cache noui Tiniha TBL SPR284 DABR__ SPR 1013 MSSSRO SPR 1015 L3 Cache Output Hold Control Register TBU SPR 285 External Access Control Register Regist L3ITCRO SPR 984 Instruction Address egister L3OHCR SPR 1000 Breakpoint Register EAR jSPR282 Performance Monitor IABR SPR 1010 pecrementer Counters Regi
8. Zr Monitor Control MMCHO _ SPR 952 MMCRI SPR 956 SPR 1022 SPR 920 1 These processor specific registers They might not be supported by other PowerPC processors Figure 8 750FX Registers Migration from IBM 750FX to MPC7447A Rev 1 Freescale Semiconductor 17 Programming Model SUPERVISOR MODEL OEA USER MODEL VEA Hardware Configuration Registers Machine State Register Time Base Facility For Reading Implementation Processor Version MSR TBL TBR 268 TBU TBR269 Registers Register HIDO SPR 1008 PVR SPR 287 Processor ID Register USER MODEL UISA HID1 SPR 1009 PIR jsPR1023 Count Register General Purpose Memory Management Registers CTR SPR9 Registers Instruction BAT Data BAT Segment Registers XER GPRO Registers Registers SRO XER SPR 1 GPR1 IBATOU SPR 528 DBATOU SPR 536 SR1 IBATOL SPR 529 DBATOL SPR 537 Link Register IBATIU SPR530 DBATIU SPR 538 LR SPR 8 GPR31 IBAT1L SPR 531 DBATiL 539 SR15 IBAT2U SPR 532 DBAT2U SPR 540 IBAT2L SPR 533 DBAT2L SPR541 IBAT3U SPR 534 DBATSU SPR 542 PTEHI SPR 981 IBAT3L SPR 535 DBATSL SPR 543 UPMC1 SPR 937 FPRO IBATAU SPR 560 DBAT4U SPR 568 PTELO SPR 982 ipea Eu 417 SPR561 DBAT4L sPRs69 TLB Miss Register SPR941 SPR562 DBATSU 570 TLBMISS SPR 980 ope IBATSL SPR 563 DBATSL SPR571 spRi SPR564 DBAT6U sPR572 5681
9. output WT output Data bus busy DBB input output N A Data bus write only DBWO N A Data bus disable DBDIS N A Data parity error DPE N A Data retry DRTRY N A Reservation RSRV N A TLB invalidate synchronize TLBISYNC N A Use A 4 35 for 32 bit addressing with A 0 3 pulled down if not in use 2 n 32 bit mode AP 0 should be pulled up In 36 bit mode use AP 0 4 as follows 0 contains odd parity for 0 3 AP 1 contains odd parity for A 4 11 AP 2 contains odd parity for A 12 19 AP 3 contains odd parity for A 20 27 AP 4 contains odd parity for A 28 35 Migration from IBM 750FX to MPC7447A Rev 1 Freescale Semiconductor 29 Revision History In the MPC7447A BMODE is sampled after HRESET is negated to set the processor ID in MSSCRO ID The value of the processor ID is important in a multiprocessor system in which one would want to define one processor with the value 0 by negating BMODE1 and make that processor responsible for booting and configuring other processors and system logic Other processors would have BMODEI tied high to differentiate In this case the processor 0 could also configure the other processors processor ID register PIR with unique values within the system Another important point is the fact the MPC7447A supports up to 16 pipelined transactions configured by MSSCR DTQ Note that the DBWO signal is not present on 7447A because 60x does not support out of order transac
10. data 200Mhz maximum bus speed 167Mhz maximum bus speed In addition the MPC7447A supports MPX bus mode offering up to 16 out of order transactions data streaming and data intervention for MP systems These features make the system bus operation much more efficient thus increasing the effective bandwidth available in the system The advantages of the MPX bus be found in Section 3 3 Mode 2 6 Thermal Assist Unit The thermal assist unit TAU used in the 750FX provides a means of monitoring the junction temperature offering an advantage over case or cabinet temperature readings given that the die temperature would be very different It can operate on a one or two threshold system whereby the threshold values are programmed into one or two of the TAU s four special purpose registers When the temperature reaches one of these thresholds Migration from IBM 750FX to MPC7447A Rev 1 Freescale Semiconductor 11 7447A Specific Features an interrupt is generated allowing software to take appropriate action to reduce the temperature accordingly Instead of the TAU the MPC7447A incorporates a temperature diode that connects to an external temperature monitor device These devices are widely available from vendors such as Analog Devices Maxim and National Semiconductor Using the negative temperature coefficient of the diode at a constant current the monitor device can determine the junction t
11. data cache data tag parity error status mask HID2 DCPS SRR1 2 L2 tag parity error status mask HID2 L2PS MSSSRO L2TAG Tag error MSSSRO L2DAT Data error Enable L1 instruction cache instruction tag HID2 ICPE ICTRL EICE checking ICTRL EICP 2 Enable L1 data cache data tag parity checking HID2 DCPE ICTRL EDEC Enable L2 parity checking HID2 L2PE L2CR L2PE 3 Not available in MPC7447A implementation 2 When the EICP bit is set the parity of any instructions fetched from the L1 instruction cache are checked Any errors found are reported as instruction cache parity errors in SRR1 If EICE is also set these instruction cache errors cause a machine check or checkstop If either EICP or EICE is cleared instruction cache parity is ignored Note that when parity checking and error reporting are both enabled errors are reported even on speculative fetches that are never actually executed Correct instruction cache parity is always loaded into the L1 instruction cache regardless of whether checking is enabled or not 3 Enables tag and data parity checking Migration from IBM 750FX to MPC7447A Rev 1 Freescale Semiconductor 23 Programming Model Table 10 shows the mapping of the 750FX s L2CR to the MPC7447A Table 10 750FX L2CR to MPC7447A Mapping Function 750FX MPC7447A L2 cache enable L2CR L2E L2CR L2E L2 double bit checkstop enable L2CR L2CE N A L2 data only
12. of greater than 256 Mbyte is enabled by asserting HIDO XBSEN and by using the BATA U XBL field in the upper BAT registers to select larger blocks up to 4 Gbytes The increased area of memory that can be mapped per BAT means that the programmer does not have to use multiple BATs to map multiple sequential 256 Mbyte blocks on the MPC7447A An added feature on the MPC7447A is software support for page table searching to offer a custom page table entry and searching operation 2 5 System Interface Both the 750FX and MPC7447A support the 60x bus protocol and the MPC7447A also supports the MPX bus protocol which is a more efficient protocol based on the 60x implementation Table 3 highlights the differences between the 750FX and MPC7447A 60x support Table 3 60x Bus Features 750FX 60x Features MPC7447A 60x Features 32 bit addressing with 4 bits odd parity 36 bit addressing with 5 bits odd parity 64 bit data bus with 8 bits odd parity 32 bit data bus 64 bit data bus with 8 bits odd parity support Three state MEI cache coherency protocol Four state MESI cache coherency protocol L1 and L2 snooping support for cache coherency L1 and L2 snooping support for cache coherency Address only broadcast instruction support Address only broadcast instruction support Address pipelining Address pipelining Support for up to two outstanding transactions one Support for up to 16 outstanding transactions instruction one data or two
13. other current MPC7450 family devices Migration from IBM 750FX to MPC7447A Rev 1 20 Freescale Semiconductor Programming Model For this reason there is not a direct mapping between the two The concept behind both schemes is to save power through reducing the core clock rate when full rate is not required 4 2 1 1 Dual PLL Configuration The 750FX has dual PLL allowing the frequency to be selected from PLLO or PLL1 where the transition is controlled through software A change in clock frequency will take three cycles to complete Due to the presence of dual PLL a change in frequency involves changing a few parameters in sequence An example of this is changing the source from PLLO to PLL1 as shown below 1 Configure PLL1 to produce the desired clock frequency by setting HIDI PR1 and HID1 PC1 to the appropriate values Note that it is necessary to wait until PLL1 locks 2 Set HIDI PS to select as the processor clock source 3 After three cycles PLL1 becomes the source and the HIDI status fields are updated Table 5 shows the fields in HIDI required to configure and change between the two PLLs Table 5 750FX HID1 Dual PLL Settings Function 750FX PLL external configuration PLL_CFG 0 4 Read only HID1 PCE PLL external range configuration Read only HID1 PRE PLL status selection HID1 PSTAT1 Enable external clock CLKOUT HID1 ECL Internal clock to output
14. processing configurations to indicate the relationship between 32 byte blocks stored in cache and their corresponding blocks in main memory In an SMP system some or all of the main memory is shared Therefore it is important to find the most efficient method of maintaining coherency across the caches and memory of the CPUs MEI refers to the cache coherency states available in the 750FX e M modified This block is modified with respect to main memory exclusive This block is valid and only present in this CPU s cache invalid This block is invalid with respect to main memory It is best to illustrate the MEI protocol operation by way of an example In a dual processor SMP system using 750FX processors we can refer to the processors and the CPU1 and CPU2 operating on a shared area of memory If CPUI loads a cache line from this area of main memory it is marked as exclusive with the assumption that the user has flushed cache on both CPUs If however CPU2 snoops the read request from CPU and already has a modified in its cache then it changes its MEI status to invalid and pushes the block into main memory causing CPU1 to wait for and then read the latest version of the data Then if Migration from IBM 750FX to MPC7447A Rev 1 14 Freescale Semiconductor 7447A Specific Features CPUZ2 tries to read the data again it must read it from main memory and to make the situation worse may
15. up to four instructions maximum per clock Two instructions can be dispatched simultaneously to fixed or floating point units the branch processing unit and the load store unit to execute in a four stage pipeline containing fetch dispatch execute and complete stages The MPC7447A offers a 12 slot instruction queue with a maximum of four fetches per cycle and can dispatch up to three instructions per cycle to any of the 11 instruction units the branch processing unit the four integer units the floating point unit the four 128 bit AltiVec vector units and the load store unit Migration from IBM 750FX to MPC7447A Rev 1 Freescale Semiconductor 5 Feature Overview 2 1 4 Branch Processing Unit The branch processing unit found in the 750FX can process one branch while resolving two speculative branches per cycle It uses a 512 entry deep BHT for dynamic branch prediction to produce four possible outcomes not taken strongly not taken taken and strongly taken It incorporates a 64 entry BTIC to reduce branch delay slots It incorporates a 64 entry BTIC which reduces idle cycles caused by branch instructions while new instructions from the branch target are fetched from the instruction cache A hit in the BTIC usually allows the first two instructions at the branch target to be supplied on the next clock cycle giving enough time for the next two instructions to be fetched from the instruction cache without any idle cycles in the instr
16. using the floating point unit Migration from IBM 750FX to MPC7447A Rev 1 6 Freescale Semiconductor Feature Overview Maximum 4 instruction fetch per clock cycle Maximum 3 instruction dispatch per clock cycle includes one branch instruction Execute Stage Maximum 2 instruction completion per Complete Write back clock cycle Figure 3 IBM750FX Pipeline Diagram If branch prediction does not work well for a particular application then having such a short pipeline is advantageous due to a fairly small pipeline flushing penalty However branch predication and modern compilers can prevent frequent pipeline flushes so the completion rate of two instruction retirements per clock becomes more of a performance bottleneck With a minimum depth of seven stages the MPC7447A pipeline shown in Figure 4 boasts efficient use of its additional hardware resources by dispatching three instructions per cycle to its execution units as well as the ability to retire three instructions per cycle The extra pipeline depth allows the MPC7447A to run at a higher frequency up to 1 5GHz The deeper pipeline is more efficient reducing the latency of many instructions including several floating point and complex integer instructions Compilers can take advantage of the extended pipeline to potentially reach a target maximum of sixteen instructions are in flight at any one time Migration from IBM 750FX to MPC7447A Rev 1
17. 6 For internal factory test Should be pulled up to OVdd for normal operation B10 E10 TEST 4 D10 For internal factory test Should be pulled down to GND VDD_SENSE G13 Internally connected to OVdd allowing an external device to know I O N12 voltage level Were OVdd in earlier MPC74xx implementations Migration from IBM 750FX to MPC7447A Rev 1 28 Freescale Semiconductor Hardware Considerations 5 2 Signal Differences One of the significant differences between the 750FX and the MPC7447A is the fact that the MPC7447A does not support 3 3V I O It only supports 1 8V and 2 5V as shown in Table 15 Table 15 Supported I O Voltages Voltage Level 750FX MPC7447A 1 8V BVSEL 0 LTTSTCLK 1 BVSEL 0 2 5V BVSEL 1 L1TSTCLK 1 BVSEL 1 3 3V BVSEL 1 L1TSTCLK 0 N A Table 16 shows some of the differences in 60x signals between the 750FX and MPC7447A The 750FX contains some optional 60x signals that are not implemented in the MPC7447A All other 60x signals are the same Table 16 60x Signal Differences Signal Description 750FX MPC7447A 60x bus mode select Default BMODEO OVdd BMODE1 OVdd Address bus 0 31 0 35 Address AP 0 3 AP 1 4 2 Address parity error APE N A Address bus busy ABB input output N A Transaction burst TBST input output TBST output Cache inhibited Cl output Cl output Write through WT
18. 7A registers The MPC7447A offers the extra registers to monitor more events including AltiVec based events that the 750FX obviously does not have to support Full listings of PMC events available in each implementation can be found in the IBM PowerPC 750FX RISC Microprocessor User s Manual and in the MPC7450 RISC Microprocessor Family Reference Manual Each implementation provides read only registers in user mode for PMC and MMCR registers with the prefix U For example UPMCI UMMCRI and so on Migration from IBM 750FX to MPC7447A Rev 1 Freescale Semiconductor 25 Programming Model 4 6 1 Monitor Mode Control Registers The mapping between the MMCRO and MMCRI is very similar but not identical Table 11 and Table 12 show this mapping for the 750FX MMCRO and respectively Table 11 750FX MMCRO to MPC7447A Function 750FX MPC7447A Disable counting unconditionally MMCRO DIS MMCRO FC Disable counting while in supervisor mode MMCRO DP MMCRO FCS Disable counting while in user mode MMCRO DU MMCRO FCP Disable counting while MSR PM is set MMCRO DMS MMCRO FCM1 1 Disable counting while MSR PM is zero MMCRO DMR MMCRO FCM1 Enable performance monitor interrupt signaling MMCRO ENINT MMCRO PMXE Disable counting of when a performance monitor interrupt is signalled MMCRO DISCOUNT MMCRO FCECE 64 bit time base transition selector MMCRO RTCSELECT MMCRO TBSEL
19. Freescale Semiconductor Application Note AN2808 Rev 1 06 2005 Migration from IBM 750FX to MPC7447A by Douglas Hamilton European Applications Engineering Networking and Computing Systems Group Freescale Semiconductor Inc 1 Scope and Definitions The purpose of this application note is to facilitate migration from IBM s 750FX based systems to Freescale s MPC7447A It addresses the differences between the systems explaining which features have changed and why before discussing the impact on migration in terms of hardware and software Throughout this document the following references are used e 750FX which applies to Freescale s MPC750 MPC740 MPC755 and MPC745 devices as well as to IBM s 750FX devices Any features specific to IBM s 750FX will be explicitly stated as such e MPC7447A which applies to Freescale s MPC7450 family of products MPC7450 MPC7451 MPC7441 MPC7455 MPC7445 MPC7457 MPC7447 and MPC7447A except where otherwise stated Because this document is to aid the migration from 750FX which does not support L3 cache the L3 cache features of the MPC745x devices are not mentioned Freescale Semiconductor Inc 2005 All rights reserved ON Contents Scope and 1 Feature Overview 42 eniti 2 7447 Specific Features 12 Programming 1 16 Hardware Cons
20. L2CR L2DO L2CR DO L2 global invalidate L2CR L2I L2CR L2I L2 write through L2CR L2WT 2 test support L2CR L2TS N A L2 cache way locking L2CR L2LOCKO L2CR L2LOCK1 2 L2CR DO and L2CR IO Snoop hit in locked line checkstop enable L2CR SHEE Snoop hit in locked line error L2CR SHEER N A L2 instruction only L2CR IO L2CR IO L2 global invalidate progress bit L2CR IP N A Notavailable in MPC7447A implementation 750 can lock each of the two ways independently MPC7447A locks completely or not at all 4 4 1 MPC7450 Extended Capabilities The MPC7447A also offers the choice of the first or second replacement algorithm L2CR L2REP and an L2 hardware flush feature L2CR L2HWF which the 750FX does not An L2 feature supported by the MPC7447A family but not by the 750FX is L2 prefetching This can offer an improvement in performance by loading the second block of a cache line after a cache miss on the line because the second block may be required in the near future even if it is not required right now The MPC7447A family capitalizes of this concept known as spatial locality using up to three hardware prefetch engines The L2 prefetching feature can be enabled by setting the L2 prefetch enable bit in the memory configuration subsystem register MSSCRO L2PFE provided that the L2 cache is enabled and not configured as data or instruction only 4 4 2 L1 and L2 Cache Locking The MPC7447A co
21. LBISYNC W11 Low TLB invalidate synchronize As in Table 6 PLL Range Configuration Migration from IBM 750FX to MPC7447A Rev 1 Freescale Semiconductor 27 Hardware Considerations 5 1 2 MPC7447A Uncommon Pins Table 14 shows the signal name pin number and a description of the signal Table 14 MPC7447A Additional Signals m Signal Name Number Active W O Description AVdd A8 PLL supply voltage BMODEO G9 Low Bus mode select 0 BMODE1 F8 Low Bus mode select 1 DRDY R3 Low Data ready output signal to system arbiter DTI 0 3 G1 K1 High Data transfer index for outstanding bus transactions P1 N1 EXT QUAL A11 High Extension qualifier GND SENSE G12 Internally connected to GND allowing an external device to know core N13 ground level HIT B2 Low MPX support for cache to cache transfers and local bus slaves OVDD SENSE E18 Supply voltage connection for system interface G18 PMON D9 Low Transitions counted by PMC1 event 7 PMON_OUT A9 Low Asserted when any performance monitor threshold or condition occurs regardless of whether exceptions are enabled or not SHD 0 1 E4 H5 Low l O Assertion indicates processor contains data from the snooped address Second SHD signal required for MPX bus mode TEMP ANODE N18 Anode from internal temperature diode TEMP CATHODE N19 Cathode from internal temperature diode TEST 0 3 A12 B
22. able searching is enabled and a TLB miss exception occurs the bits of the page table entry PTE for this access are located by software and saved in the PTE registers A full explanation of software page table searching can be found in the MPC7450 RISC Microprocessor Family Reference Manual 4 6 Performance Monitor Although it is optional both implementations support the performance monitor features Performance monitors give the user software the ability to monitor and count specific events including processor clocks L1 and L2 cache misses types of instructions dispatched and branch prediction statistics among others The count of these events can be used to trigger an exception The performance monitor has three key objectives 1 To increase system performance with efficient software especially in a multiprocessing system Memory hierarchy behavior can be monitored and studied in order to develop algorithms that schedule tasks and perhaps partition them and that structure and distribute data optimally 2 characterize processors Some environments may not be easily characterized by a benchmark or trace 3 help system developers bring up and debug their systems The MPC7447A contains two additional performance counters PMCS and PMC6 a breakpoint address mask register BAM and an extra monitor control register MMCR2 This section looks at any differences in the common registers and the purpose of the extra MPC744
23. e parameters for MPC745x devices It MSSSCRO also defines the number of outstanding bus transactions MSSCRO DTQ and intervention for MPX mode MSSCRO EIDIS 4 4 Differences in L1 and L2 cache configuration Due to the differences in programming models the L1 and L2 cache configuration and status bits are located in different registers in the MPC7447A than in the 750FX In the 750FX the HID2 is used for L1 and L2 cache parity error settings and status but this register is not present in the MPC7447A Table 9 shows which register bits in the MPC7447A give the same functionality as the HID2 These functions are spread across SSR1 which is present in the 750FX but its bits are reserved MSSSRO the instruction cache and interrupt control register ICTRL which is not present in the 750FX and L2CR Table 9 750FX HID2 to MPC7447A Mapping Function 750FX MPC7447A Isolate guarded requests on the bus This bit HID2 IGRE N A prevents pipelining of guarded requests with any other requests on the bus L2 cache low voltage enable and is only available HID2 L2LVE N A Force instruction cache bad parity HID2 FICBP N A 1 Force instruction tag bad parity HID2 FI TBP N A Force data cache bad parity HID2 FDCBP N A Force data tag bad parity HID2 FDTBP Force L2 tag bad parity HID2 FL2TBP L1 instruction cache instruction tag parity error HID2 ICPS SRR1 1 status mask L1
24. emperature Figure 6 shows how the monitoring device can be connected directly to the anode and cathode of temperature diode on the MPC7447A The monitor chip is also connected via the 60x or MPX bus to a bridge chip system controller which then communicates with the monitor chip itself using This second connection allows thresholding values to be defined so that the monitor chip can generate interrupts via the bridge chip in a similar manner to the TAU in the 750FX MPC7447A Monitor Chip TEMP_CATHODE D ALERT IRQ 60x MPX Bus Bridgechip INT Figure 6 Temperature Monitoring Device Connection 3 7447A Specific Features This section briefly introduces some major features of MPC7447A devices that are not available on the 750FX and explains how they can offer significant performance improvements Migration from IBM 750FX to MPC7447A Rev 1 12 Freescale Semiconductor 7447A Specific Features 3 1 AltiVec Perhaps the most notable difference between the 750FX and MPC7447A is that of AltiVec It is a SIMD single instruction multiple data extension of the PowerPC architecture in terms of both instructions and hardware It is available on all G4 devices and can offer significant performance improvements on applications that benefit from SIMD programming such as graphics certain DSP algorithms and many computationally intensive vector applications The following are key features of Alti Vec
25. have since modified the data in its cache If CPU1 has modified the data then CPU2 has to wait for CPU1 to write its data back to memory for the CPU2 to access The extra bandwidth used and time wasted in waiting for each CPU to write its cache block back to memory for the other CPU to access is a very inefficient use of the bus To help combat this problem the MPC7447A supports the MPX bus which extends the 60x functionality with some efficiency improvements as discussed in the next section The main method used to improve performance on MPC7447A was to incorporate the MESI protocol which includes the new shared state S This block exists in multiple caches and is consistent with main memory That is it is read only The addition of this state reduces the wasted time and bandwidth associated with MEI coherency and requires an additional 60x MPX signal called SHD If we look at the previous example it is easy to see the benefits of the MESI over MEI If CPUI tried to read a block of main memory to its cache CPU2 would snoop the transaction as before but this time assert the SHD signal to tell CPUI that it also has a cached copy of this block too CPU1 would load the block into its cache with shared status and CPU2 would change its cache entry to shared from exclusive allowing both CPUs to access the data quickly from cache provided they are only reading it 3 3 MPX Mode The MPX bus protocol is based on the 60x bus protocol It al
26. iderations 27 Revision History 30 gt oe 2 freescale semiconductor Feature Overview 2 Feature Overview There are many differences between the 750FX and the MPC7447A devices beyond the clear differences of the core complex This section covers the differences between the cores and then other areas of interest including the cache configuration and system interfaces 2 1 Cores The key processing elements of the G3 core complex used in the 750FX are shown below in Figure 1 and the G4 complex used in the 7447A is shown in Figure 2 Migration from IBM 750FX to MPC7447A Rev 1 2 Freescale Semiconductor Feature Overview zng ERC ang EE smg mappy HEEE IPH AHE 15 71 aran PEO ERY eue 27 NAR me quf dua zuun uuri pun BOS 22 jurog pexi4 OES uo enu sarl er ONES eser Isucuonagu 2 E n Ss a opun ILEULEEEUEJN ETELE arenp ACL adyn 2057 eu pun auopnsu 187861 Figure 1 750FX Core Migration from IBM 750FX to MPC7447A Rev 1 Freescale Semiconductor sng 9 sng sso
27. igration from IBM 750FX to MPC7447A Rev 1 18 Freescale Semiconductor 4 1 Differences in HIDO and HID1 Although the 750FX and the MPC7447A have both the HIDO and the HID1 registers defined in their implementations however their bit settings can differ Table 4 summarizes these differences and shows the mapping of fields between devices Table 4 750FX HIDO to MPC7447A Mapping Programming Model Function 750FX MPC7447A Enable MCP HIDO EMCP HID1 EMCP Disable 60x bus address and data HIDO DBP parity generation Enable 60x bus address parity HIDO EBA HID1 EBA checking Enable 60x bus data parity checking HIDO EBD HID1 EBA Disable precharge of ARTRY HIDO PAR HID1 PAR Doze mode enable HIDO DOZE N A Nap mode enable enable HIDO NAP HIDO NAP Sleep mode enable enable HIDO SLEEP HIDO SLEEP Dynamic power management HIDO DPM HIDO DPM enable Read instruction segment register HIDO RISEG N A 3 Miss under miss enable HIDO MUM N A Not a hard reset HIDO NHR HIDO NHR Instruction cache enable HIDO ICE HIDO ICE Data cache enable HIDO DCE HIDO DCE Instruction cache lock HIDO ILOCK HIDO ILOCK Data cache lock HIDO DLOCK HIDO DLOCK Instruction cache flush invalidate HIDO ICFI HIDO ICFI Data cache flush invalidate HIDO DCFI HIDO DCFI Speculative data and instruction HIDO SPD HIDO SPD cache disable Enable M bit on bus for instructio
28. local bus slave to the system arbiter This signal indicates a valid snoop response in the address retry window the cycle after an AACK that indicates that the MPC7447A will supply intervention data Intervention occurs when the MPC7447A has Migration from IBM 750FX to MPC7447A Rev 1 Freescale Semiconductor 15 Programming Model the data that has been requested by another master s bus transaction in its L1 or L2 Instead of asserting ARTRY and flushing the data to memory the MPC7447A may assert HIT to indicate that it can supply the data directly to the other master This external intervention functionality is disabled by MSSCRO EIDIS The DRDY signal is also used by the MPX bus protocol to implement data intervention in the case of a cache hit The SHD1 signal operates in conjunction with the SHDO signal to indicate that a cached item is shared MPX mode offers one final improvement to the 60x with support for out of order transactions As mentioned previously the MPC7447A supports up to 16 outstanding transactions as compared to the two supported by the 750FX This means that the MPC7447A has increased efficiency with its deeper pipeline of transactions A further improvement that is specific only to MPX mode is the fact that these transactions can be out of order allowing lower latency devices to return data as soon as they are ready without waiting for higher latency devices to return data first just because their tra
29. n HIDO IFEM HIDO 23 5 fetches M from WIM states Store gathering enable HIDO SGE HIDO SGE Data cache flush assist HIDO DCFA HIDO 25 6 BTIC enable HIDO BTIC HIDO BTIC Address broadcast enable HIDO ABE HID1 ABE 7 Migration from IBM 750FX to MPC7447A Rev 1 Freescale Semiconductor 19 Programming Model Table 4 750FX HIDO to MPC7447A Mapping continued Branch history table enable HIDO BHT HIDO BHT No op the data cache touch HIDO NOOPTI HIDO NOOPTI instructions 1 Not available in MPC7447A implementation Not required on MPC7447A due to processor system handshake protocol system explained in Power Management 3 Not implemented For test only on the 750FX Always enabled in MPC7447A implementation The 750FX supports two outstanding data misses and the MPC7447A supports five outstanding data misses Reserved Used for IFEM in earlier processors but is also used for extended BAT block size enable Reserved Defined as DCFA on earlier processors Must be enabled in multiprocessing systems HID1 SYNCBE enables address broadcast for sync and eieio instructions Oo 4 2 Power Management Although they are very similar there are a couple of differences between the 750FX and MPC7447A power management functionality This section only mentions the differences Features like instruction cache throttling to slow the instruction dispatch rate are the same in both implementa
30. nsaction was first This is achieved using the four DTI Data Transaction Index signals on the MPX bus The DTI signals act as a pointer to the outstanding transactions queue and indicate which of the outstanding transactions is to be serviced by subsequent data tenure 4 Programming Model Both the IBM 750FX and MPC7447A have to support the PowerPC standard architecture in order to retain compatibility in user mode Recompilation is not necessary for the IBM 750FX user code to execute properly on the MPC7447A However in supervisor mode there are many differences between device dependent registers even though some of the names are the same the fields are often changed in name and or bit position There are also additional registers in different PowerPC implementations to support additional features This section maps the supervisor level registers between 750FX and MPC7447A and points out any additional or device specific features The diagrams in Figure 8 and Figure 9 show the 750FX and MPC7447A programming models respectively Migration from IBM 750FX to MPC7447A Rev 1 16 Freescale Semiconductor SUPERVISOR MODEL OEA Programming Model Configuration Resi USER HODEL VEA Hardware Processor Machine XY Implementation Version State Time Base Facility For Reading Registers Register Register TEL TER 268 TBU TBR 269 Hibo 1009 PVA SPH287 HIDI SPR 1009 HIDZ PH 1015 Ee sizie
31. ntains a load store control register that configures L1 data cache locking by way The LDSTCR is not present in the 750FX because L1 way locking is not supported It can be configured on the MPC7447A using the eight bits in LDSTCR DCWL indicating which way s to lock There are equivalent bits in the instruction cache and interrupt control register ICTRL The eight bits of ICTRL ICWL indicates which way s to lock Migration from IBM 750FX to MPC7447A Rev 1 24 Freescale Semiconductor Programming Model The 750FX has the ability to lock L2 cache by way using L2CR LOCKn bits And L2CR DO or L2CR IO will setup the L2 as data only or instruction only respectively The MPC74474 does not support locking the L2 by way but the whole cache can be locked by setting both L2CR DO and L2CR IO L2CR DO and L2CR IO individually behave identically as the 750FX 4 5 Memory Management Registers Because the 750FX does not have the ability to resolve page table entries in software it has no need for PTEHI PTELO and TLBMISS registers known as SPR 981 982 and 980 respectively The TLBMISS register is automatically loaded when software searching is enabled HIDO STEN 1 and a TLB miss exception occurs Its contents are used by the TLB miss exception handlers the software table search routines to start the search process The PTEHI PTELO registers are used by tlbld and tlbli instructions to create a TLB entry When software t
32. ntioned previously the MPC7447A also has an MMCR2 with a one bit field MMCR2 THRESHMULT This can be used to extend the range of the MMCRO THRESHOLD by multiplying by 2 if set at 0 or by 32 if set at 1 The MPC7447A also has a breakpoint address mask register BAMR that is used as a mask for debug purposes to compare to IABR 0 29 when PMC is set to monitor event 42 This event monitors for IABR hits specifically by checking that they match BAMR A match is defined as IABR 0 29 amp 0 29 instruction addr 0 29 amp BAMR 0 29 5 Hardware Considerations 5 1 Pinout Comparison Because there is no footprint pinout compatibility the easiest way to compare the 750FX and MPC7447A pins is to look at the different pins on the 750FX that do not exist on the MPC7447A and then to look at the pins present on the MPC7447A but not on the 750FX 5 1 1 750FX Uncommon Pins Table 13 shows the signal name pin number and a description of the signal Table 13 750FX Additional Signals 1 ae Active yo Description A1Vdd Y15 PLLO supply voltage A2Vdd Y16 PLL1 supply voltage AACK A8 Low Input ABB Y6 Low Address bus busy AGND Y14 Ground for PLL DBB U7 Low 1 0 Data bus busy DBDIS A10 Low Data bus disable DBWO A6 Low Data bus write only DRTRY W3 Low Data retry PLL_RNG W15 U14 High Specifies PLL range RSRV 4 Low Internal reservation coherency bit T
33. ompletely Replacement policy Cast out replacement only 3 bit counter or pseudo random Parity 8 bits 64 bytes on tags 8 bits 64 bytes on tags and data Migration from IBM 750FX to MPC7447A Rev 1 Freescale Semiconductor Feature Overview 2 4 MMU Figure 5 shows the standard PowerPC MMU translation method The presence of TLBs and page table search logic are optional although both the IBM 750CX and Freescale 7447A implement them Data Instruction Accesses Accesses A 20 31 15 19 IBATOU IBAT7L Upper 24 Bits of Virtual Address EA 0 14 DBATOU TLBs Optional t i Page Table Search Logic Optional On Chip 1 PA 15 19 5081 SPR 25 A 20 31 k Optional 0 311 Figure 5 Effective to Physical Mapping Both the 750FX and the MPC7447A offer the following features e 128 two way set associative instruction TLB and data TLB e Eight data BAT and eight instruction BAT pairs e Translation for 4 Kbyte page size and 256 Mbyte segment size Migration from IBM 750FX to MPC7447A Rev 1 10 Freescale Semiconductor Feature Overview e Block sizes from 128 Kbyte to 256 Mbyte up to4 Gbytes for MPC7447A The other significant difference is the fact that the MPC7447A can support 36 bit physical addressing by enabling HIDO XAEN thus allowing the increased 64 Gbyte memory space The extended block size
34. ong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 800 441 2447 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor Q hibbertgroup com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights no
35. ower cost for an inactive core the dynamic power consumption of the device is halved when DFS is applied Note that static leakage power is not affected by DFS so the power consumption with DFS enabled is not exactly 5096 of the full power consumption For more information see Section 4 2 1 2 DFS Configuration This provides a significant advantage in supporting dynamic processing requirements in power sensitive applications Table 7 shows the bits corresponding with DFS mode Table 7 MPC7447A HID1 DFS Settings Feature MPC7447A DFS divide by two enable HID1 DFS2 PLL configuration PLL_CFG 0 4 Read only HID1 PCO PC4 4 3 Cache Memory Subsystem Configuration The MPC7447A implements two registers named memory subsystem status and control registers MSSSRO MSSCRO that do not exist in the 750FX Some of the functions in these extra registers are held in another 750FX register Table 8 summarizes this relationship Table 8 750FX Mapping to MPC7447A MSSSRO MSSCRO Registers Function 750FX MPC7447A Address bus parity error SRR1 AP MSSSRO APE Data bus parity error SRR1 DP MSSSRO DPE Bus transfer error acknowledge SRR1 TEA MSSSRO TEA Migration from IBM 750FX to MPC7447A Rev 1 22 Freescale Semiconductor Programming Model In addition MSSCRO stores more configuration data This configuration relates to features not available in the 750FX including L3 cach
36. r USER MODEL UISA Instruction BAT Data BAT e Registers Registers egisters Count Register SPR 528 DATO SPH 525 SHO XER f XR SPRI IBATOL SPR 529 DBATOL 527 SHi IBATIU SPR 530 DBAT1U EX TIME IBATTL SPR EST Link Register General Purpose IHAT2U SPA 532 DBAT2U SPAS SRIS LR SPR8 Registers IBAT2L SPR 533 DBAT2L 541 IBAT3L SPA 535 DBATAL 542 SDR1 IBAT4L SPR 560 Le ala 568 SDHi 5 25 Condition Register IBAT4L SPR 561 t c Save and Restore esa ra user ores Performance Monitor Regis ters IBATGL SPR 565 For Reading IBAT7U SPR 555 SHHO SPH26 SPR ear Fur Performance Counters Floating Point Exception Harxlling Registers Registers SPRGs Data Add ress DSISR SPHG __ 272 Register DSSA SPA Ie SPHG SsPR273 DAR SPR 19 SPAG2 SPR274 SPHG3 5 275 Monitor Control VI T4 UMMGR1 SPA 540 rede External Access Time Base Decrementer Register For Writing FPSOR DEC SPR 22 cic SPR 242 TBL SPR 284 instruction TEU SPR 235 Instruction Address Address Data Address Breakpoint Register usi SPA 920 Breakpoint Register L2 Control SPH 1010 DABR 1013 Register L2CR SPR 1017 Performance Sampled Instruction Thermal Assist Unit Registers Instruction Cache Throttling Counters Address Control Register SPR 953 SPR 1020 2 SPR 954 Srna 2 SPR 1021 Tr mmm
37. r the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc The described product is a PowerPC microprocessor The PowerPC name is a trademark of IBM Corp and used under license All other product or service names are the property of their respective owners Q Freescale Semiconductor Inc 2005 AN2808 Rev 1 06 2005 gt oe 2 freescale semiconductor
38. s can start executing thus preventing stalling Also the MPC7447A has sixteen GPR rename buffers to support the 16 entry completion queue as compared to the 6 entry completion queue for the 750FX The floating point can also source rename buffers as a source operand without waiting for the value to be committed and retrieved from GPR 2 1 2 Floating point Units The 750FX floating point unit has 32 64 bit registers for single precision and double precision IEEE 754 standards Different operations have various latencies associated with them due to the three stage pipeline with multiply add and normalize stages The latency throughput varies from 3 1 clock cycles for single multiply add increasing to 4 1 clocks for double multiply and double multiply add because two cycles are required in the multiply unit The MPC7447A floating point unit meets the same standards for IEEE 754 precision and in addition has an increased pipeline depth of five stages to allow even double precision calculations to have a one cycle throughput Although the latency is increased the overall throughput is better for the majority of double precision calculations The floating point can also source rename buffers as a source operand without waiting for the value to be committed and retrieved from FPR 2 1 3 Instruction Queues The instruction queue in the 750FX can hold up to six instructions While the instruction queue depth allows the instruction fetcher retrieves
39. so includes several additional features that allow it to provide higher memory bandwidth than the 60x bus and more efficient utilization of the system bus in a multiprocessing environment Memory accesses that use the MPX bus protocol are separated into address and data tenures Each tenure has three phases arbitration transfer and termination The separation of the address and data tenures allows advanced bus techniques such as split bus transactions enveloped transactions and pipelining to be implemented at the system level in multiprocessor systems The MPX bus protocol also supports address only transactions One benefit that MPX has over 60x is the fact that the MPX does not require an idle cycle between tenures To illustrate the importance of this difference consider the following example e 00Mhz 60x bus Transfer rate 32 bytes 5 clock cycles 100MHz 640 Mbyte s e 100Mhz MPX bus Transfer rate 32 bytes 4 clock cycles 100MHz 800 Mbytes s Also given the higher bus speeds of 167MHz available on the 74474 the transfer rate is scaled accordingly to give significant increase to 1336 Mbytes s which compares favorably to the 750GX 1280 Mbytes s maximum with its 200MHz 60x bus The MPX bus mode s support for data intervention and full data streaming for burst reads and writes is realized through the addition of two new signals HIT and DRDY The HIT signal is a point to point signal output from the processor or
40. sters Breakpoint Address DEC SPR22 1 SPR953 Monitor Control Mask Register PMC2 SPR 954 Registers BAMR SPR 951 _ 5 957 MMCRO SPR952 Sampled Instruction PMC4 SPR958 MMCR1 sPRose Address Register PMC5 SPR 945 2 SPR 944 SIAR SPR 955 PMC6 SPR 946 Performance Monitor Registers Floating Point Performance Counters Registers PTE High Low Registers 1 Thermal Management Register Instruction Cache Throttling Control Register ICTC SPR 1019 1 MPC7445 MPC7447 MPC7455 and MPC7457 specific register may not be supported on other processors that implement the PowerPC architecture 2 Register defined as optional in the PowerPC architecture Register defined by the AltiVec technology MPC7455 and MPC7457 specific register 5 MPC7457 specific register Figure 9 MPC7447A Register Set M
41. tions Both implementations support the four states full power doze nap and sleep From Table 4 above note that there is no HIDO DOZE bit for the MPC7447A This is because the MPC7447A enters doze mode when requested by the processor system protocol The processor can transition to doze mode from the following 1 Full power if HIDO NAP or HIDO SLEEP and MSR POW are asserted and the core is idle 2 Nap if the system negates QACK to signal a snoop operation is outstanding It can transition from doze mode to the following 1 Full power following one of many possible interrupts external SMI interrupt SRESET HRESET machine check or decrementer interrupt 2 Nap if the system asserts QACK with HIDO NAP and MSR POW set or 3 Sleep if system asserts QACK with HIDO SLEEP and MSR POW set Additionally the MPC7447A has a deep sleep mode which can offer further power savings from sleep mode turning off the PLL by setting PLL_CFG to OxF thus allowing the SYSCLK source to be disabled For further explanation on standard power management features between both implementations please refer to the MPC7450 RISC Microprocessor Family Reference Manual 4 2 1 PLL Configuration HID1 primarily holds PLL configuration and other control bits in both the 750FX and the MPC7447A although there are a couple of differences as shown below due to the dual PLL in the 750FX vs the dynamic frequency selection DFS in the MPC7447A but not in
42. tions Therefore in this mode the data transaction index pins DTI 0 3 should be pulled low 6 Revision History Table 17 gives a revision history for this application note Table 17 Revision History Revision Release Date Substantive Change s 1 6 22 2005 Minor editing 0 5 9 2005 Initial release Migration from IBM 750FX to MPC7447A Rev 1 30 Freescale Semiconductor Revision History THIS PAGE INTENTIONALLY LEFT BLANK Migration from IBM 750FX to MPC7447A Rev 1 Freescale Semiconductor 31 How to Reach Us Home Page www freescale com email support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 800 521 6274 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 81 2666 8080 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T H
43. uction stream In contrast the MPC7447A processes one branch per cycle like the 750FX but can resolve three speculative branches per cycle The increased BHT with 2048 entries offers the same four predication states but with the advantage of the larger size In addition to these four predication states the BHT using HIDO BHTCLR can be cleared to a fifth state weakly not taken The BTIC is twice the size of the 750FX providing 128 entries arranged as 32 sets using a four way set associative arrangement 2 1 5 Completion Unit In the 750FX the completion unit works with the dispatch unit to track dispatched instructions and retire them in order to the completion queue Up to two instructions can be retired per clock cycle The instruction is removed from the completion queue if the rename buffers have been freed and results have been written into processor registers such as GPRs FPRs LR and CTR For the MPC7447A due to deeper pipelines we can have up to 16 instructions at some stage of pipeline processing and retire a maximum of three instructions per clock to one of the 16 completion queue slots 2 2 Pipeline Comparison The difference in pipeline depths between the 750FX and MPC7447A is significant The 750 pipeline is four stages including instruction fetch dispatch decode execute and complete write back The pipeline diagram for the 750FX is shown in Figure 3 Note that the 750FX has a maximum depth of six stages when
44. uppy 9 96 usnd 10J ejqejre e Buunsue seujue 6 oi s asy NOSED 941 9 JO peuiquuoo e eAeu uons seounosai usng pue 1nojse SeJoN 1 ssi eoig ______ sng 1 9 suonuoAJ9jul usnd 6 811101580 r1 057 21015 21 4 2 yaad 21 usnd anano eneno sng LL anano peo o2eji91u sng uiejis S 2 2018 eu2e2 215 671816 2 0 2018 eurj S ssiN peo1 11 senenp anand 1 1 957 anand 9J0lS 1 waysAsqns SSI peo 591015 17 1ulod Buneol4 suoneis 91 alld e 591015 1101520 1 s pausiul4 uonejnope v3 euiBu3 uono 10129A
Download Pdf Manuals
Related Search