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1. N MKY02 56 lcog2 COE1 4 55 cop2 1 54 cop2 cop1 COHR SO 25 53 cipi ciP2 426 4 _ 58 2 27 e gt CIHR WA 7 7 M A Fig 3 15 Handling of Cascade Connection Pins 3 6 Cautions for Designing HUB When designing a HUB configured using one MKY 02 note the following points 1 When connecting the analog signal lines to the driver receiver pulse transformer and network cable connector do not cross each other or do not extend the anaog signla lines unnecessarily except digi tal signal lines between the 02 and components do not use overlong cables in order to avoid crosstalk interference 2 Connect a termination resistor when HUB ports are connected to the end of the network cable Do not connect a termination resistor when HUB ports are connected in the intermediate position of the network cable 3 If ports 1 to 7 of the satellite side receive a packet simultaneously priority is given to the port with smaller port number 4 The recommended pulse transformer SPT 401 series supports 3 to 12 5 Mbps When designing a HUB using a baud rate other than these values the designer needs to select an appropriate pulse trans former other than the SPT 401 series TEP S TECHNICA Co LTD MKY02 User s Manual for Hi speed Link System 3 7 Example Circuit for Single Connection of MKY02 Figure 3 16 shows an example circuit for a HUB
2. Pulse shield 6 transformer gt 3 12 3 5 1 sic 4 Rt ai 2 SIG j Pulse 6 shield 8 SIG TXE3 15 1 transformer RXD5 MKY02 2 a MKY02 2 shield 6 Pulse 2 transformer 1 4 RXD3 4 5 ADM1485 5 V Port 11 9 6 5 2 a7 06 05 04 Q2 01 00 42 WM 9 Port receive monitor circuit 6 2 1 SIG 7 7 7 71 A 5 2 SIG Uu of of 5 6 5 Pulse 5 5 1 transformer Le shield 2 O Sb 77 1 decir EE TEE m 31 40 36 17 53 19 18 16 17 15 14 12 13 9 8 6 7 5 4 2 Q7 D7 Q6 06 Q5 0504 D4 Q3 D3 Q2 0291 D1Q0 39 52 1 CLK 34 re 10 38 64 17 32 49 46 33V 1 16 33 48 1093 7 7 Zr 7H 2 CIE1 COE1 2 s tc 2 gt CID1 55 i 1 i MKY02 1 cor 57 conr 2 2 3 CIE2 lt 56 CIE2 p COE2 CIP2 4 55 2 2 COP2 i CID2 4 54 f 2 PP i COD2 i RST 35 37 39 43 AXS2 gt AXS1 AXSO aS gt gt To 3 3 e gt e D Fig 4 10 Example Circuit for HUB with 22 Ports 2 3 TEP TECHNICA Co LTD MKY02 User s Manual for Hi speed Link System 3 3V Ws Port 15 ADM1485 5 V 7 7 SIG 1 R SIG 2 shield 6 Pulse transformer Port 16 SIG 1
3. Schmitt trigger for TTL level input VDD or 5 5 V max liL Vss max Type C 5 0 V tolerant push pull output Von loH 100 min loH 4 mA min VoL loL 100 uA max VoL loL 4 mA max max loL max GND 5 0 V tolerant pull up input Type B Schmitt trigger for TTL level input Vt max Vt min VDD max VH 5 5 V max liL VL Vss max Type D 5 0 V tolerant push pull output 100 uA Vpp 0 2 V Vou loH 8 mA min Rpu typ 50 Fig 2 2 Pin Electrical Characteristics Circuit Types of 02 Chapter 3 Single Connection of 02 This chapter describes the pin functions and how to connect pins required to design a HUB with two to eight ports configured using one MK Y02 inserted into the HLS 3 1 3 2 3 3 3 4 3 5 3 6 3 7 Voltage Levels of Pins Connecting to Signal Pins 3 4 Supplying Driving Clock and Hardware Reset Signal 3 5 Connecting Network 22 4 1 31 21 3 8 Connecting Monitor _ 0 3 11 Handling Cascade Connection Pins 3 15 Cautions for Designing HUB 3 15 Example Circuit for Single Connection of
4. TEP S TECHNICA Co LTD HuB ic MK Y0O2 User s Manual for Hi speed Link System Note 1 The information in this document is subject to change without prior notice Before using this product please confirm that this is the latest version of this document 2 Technical information in this document such as explanations and circuit examples are refer ences for this product When actually using this product always fully evaluate the entire sys tem according to the design purpose based on considerations of peripheral circuits and the PC board environment We assume no responsibility for any incompatibility between this product and your system 3 We assume no responsibility whatsoever for any losses or damages arising from the use of the information products and circuits in this document or for infringement of patents and any other rights of a third party 4 When using this product and the information and circuits in this document we do not guaran tee the right to use any property rights intellectual property rights and any other rights of a third party 5 This product is not designed for use in critical applications such as life support systems Con tact us when considering such applications 6 No part of this document may be copied or reproduced in any form or by any means without prior written permission from StepTechnica Co Ltd TEP MKYO02 User s Manual ST ECHNICA CO LTD Pref
5. essen 3 13 Fig 3 13 8 port Receive 3 14 Fig 3 14 4 port Receive 01 1 111 1 nennen nennen 3 14 Fig 3 15 Handling of Cascade Connection Pins 3 15 Fig 3 16 Example of Single Connection Circuit in Half duplex Mode 3 16 Fig 3 17 Example of Single Connection Circuit in Full duplex Mode 3 17 vii TEP ECHNICA MKY02 User s Manual for Hi speed Link System Fig 4 1 Addition of Three stacked Ports 4 3 Fig 4 2 Port Addition by Three Cascade 4 4 Fig 4 3 Cascade Pin Connection for Three 025 4 5 Fig 4 4 Cascade Pin Connection for Two 25 4 5 Fig 4 5 Center Ports and Operation during 4 6 Fig 4 6 Satellite Ports and Operation during Receiving 4 6 Fig 47 Connection of Cascade Clocks 44404 0 4 7 Fig 4 8 Selection of Communication 4 8 Fig 4 9 Monitor Placement Example for Port added HUB 4 9 Fig 4 10 Example Ci
6. 2 3 16 TEP Chapter 3 Single Connection of 02 S TECHNICA CO LTD Chapter 3 Single Connection of MKY02 This chapter describes the pin functions and how to connect pins required to design a HUB with two to eight ports configured using one MKY02 inserted into the HLS Before connecting the MKY02 be sure to connect the TESTI pin 46 and TEST2 pin pin 47 to the GND pins In a HUB configured using one 02 to be inserted into the HLS be sure to fix the function select pin HC pin 50 at High Be sure to connect all GND pins pins 1 16 24 33 41 48 to the 0 V power supply and all VDD pins pin 10 17 32 38 49 64 to the 3 3 V power supply In addition connect a 0 1 uF capacitor 10 V 104 between adjacent VDD pins and GND pins TEP S TECHNICA Co LTD MKY02 User s Manual for Hi speed Link System 3 1 Voltage Levels of Pins Connecting to Signal Pins signal pins except those connected to VDD pins GND pins of the MKYO2 are tolerant types that can be connected to 5 0 V TTL signals 1 The pins can directly be connected to peripheral logic circuits driven by the 3 3 V power supply 2 The pins can be connected to TTL level signals of peripheral logic circuits driven by the 5 0 V power supply A pull up resistor can also be connected between the 5 0 V power supplies However if the input voltage of the MKY02 pins exceed 3 3 V leakage current flows i
7. To design a HUB with 22 ports port O of the center side and ports 1 to 21 of the satellite side in full duplex mode change the connection of the TRX and FH pin pin 51 in Figure 4 10 to those in Figure 4 11 Pulse transformer E Pulse transformer 5 SN751178 5 V 44 RPSIG 3 H 4 1 CPSIG lt 3 RPSIG 4 gt 2 CPSIG CPSIG 1 i 3 RPSIG i Tz cpsic 2 4 RPSIG AL NR shield 6 6 shield CPSIG 1 CPSIG Rt CPSIG 2 CPSIG RPSIG 3 RPSIG RPSIG 4 3 RPSIG MS ey shield 6 Pulse shield transformer transformer F Pulse transformer m Pulse transformer SN751178 5 V 143 CPSIG 124 CPSIG CPSIG gt CPSIG RPSIG RPSIG RPSIG RPSIG shield shield CPSIG CPSIG CPSIG CPSIG RPSIG am RPSIG RPSIG RPSIG shield od shield Pulse transformer transformer Fig 4 11 Example of Connection in Full duplex Mode TEP S TECHNICA Co LTD MKY02 User s Manual for Hi speed Link System Chapter 5 Ratings This chapter describes the ratings of the MKY02 5 1 5 2 5 3 5 4 5 5 Electrical Ratings sisi 5 3 AC Characteristics asii 5 3 Package 5 8 Recommended Soldering
8. Q6 06 Q5 05 Q4 04 Q2 02 Q1 QO CLK RLCK DO RLDT 74273 3 3 V type etc CLRO lt RST Fig 3 13 8 Receive Monitor Port3 2 Port1 Porto CLK RLLD 74273 3 3 V type etc Ds D7 06 05 04 03 GER RST Q2 D2 D1 QO CLK RLCK 74273 3 3 V type etc DOST REDT D7 D6 D5 D4 CLRIO lt RST Fig 3 14 4 port Receive Monitor Leave the RLDT pin RLCK pin and RLLD pin open when an additional circuit is not connected to them Reference Packet Receive Monitor also go on Mounting both LEDs may cause confusion among If any ofthe receive monitor LEDs for individual ports go on the LEDs described in 3 4 1 the HUB users The HUB designer or user system designer needs to determine the mount ing of receive monitors TEP Chapter 3 Single Connection of 02 S TECHNICA CO LTD 3 5 Handling Cascade Connection Pins When designing a HUB with two to eight ports configured using one 02 be sure to perform the fol lowing processing so that the cascade pins of the MK Y02 do not function Fig 3 15 1 Fix the CIEI pin pin 60 CIPI pin pin 59 CIDI pin pin 58 CIHR pin pin 57 CIE2 pin pin 25 CIP2 pin pin 26 and CID2 pin pin 27 at Low 2 Leave the COEI pin pin 20 COPI pin pin 21 CODI pin pin 22 COHR pin pin 23 COE2 pin pin 56 COP2 pin pin 55 and COD2 pin pin 54 open
9. multiport HUB with nine or more ports refer to 1 6 Port Addition to HUB config ured using multiple MK Y02s to be inserted into the HLS 4 1 Concepts of Port Addition 4 3 4 2 Practical Side of Cascade Connection 4 5 4 3 Example Circuit for Port added HUB by Cascade Connection 11 eere 4 10 Chapter 4 Cascade Connection of MKY02 TEP S TECHNICA Co LTD Chapter 4 Cascade Connection of MKY02 This chapter describes the pin functions and how to connect pins required to design a multiport HUB with nine or more ports refer to 1 6 Port Addition to HUB configured using multiple MK Y02s to be inserted into the HLS 4 1 Concepts of Port Addition This section describes the concepts of port addition to a HUB using multiple HUB ICs 4 1 1 Port Addition by Stacking Method To add HUB ports using multiple MKY02s HUB ICs stacking is suitable as shown in the Figure 4 1 Stacking is to connect one port of the sattelite side to the port 0 of the next MK Y02 The connection by stacking has the following demerits 1 Time lag refer to 1 7 1 Receiving and Send ing of Packets increas in subsequent stacked ports 2 One satellite side port of the 02 cannot be used The increased time lag in the above 1 may be unuse ful especially for the HLS
10. Be sure to connect this pin to GND pin manufacturer test pin 50 Be sure to fix this pin at High This is input pin to set MK Y02 as HLS HUB 51 Input pin that selects MK Y02 communication mode Set this pin High when selecting Full duplex mode and Low when selecting half duplex mode Input pin that selects MK Y02 baud rate For details refer to 3 2 2 Setting Cascade Clock and Baud Rate Input pin that selects MK Y02 baud rate For details refer to 3 2 2 Setting Cascade Clock and Baud Rate Output pin for cascade connection Connect to the CID2 pin of the MK Y02 for higher cascade connection Leave this pin open when it is not cascade connected Output pin for cascade connection Connect to the CIP2 pin of the MK Y02 for higher cascade connection Leave this pin open when it is not cascade connected CIHR CID1 57 Positive Positive Output pin for cascade connection Connect to the CIE2 pin of the 02 for higher cascade connection Leave this pin open when it is not cascade connected Input pin for cascade connection Connect to the COHR pin of the 02 for higher cascade connection Fix this pin at Low when it is not cascade connected Input pin for cascade connection Connect to the CODI pin of the 02 for higher cascade connection Fix this pin at Low when it is not cascade connected CIP1 Positive Input pin for cascade connection Connect to th
11. Power creen 19 ADM1485 ae 42 DIP SW Picus RLDT 53 25 V 100 uF BPS1 mes NC open BPSO os Note Add as necessary ro two 74273 1 pins 33 7 7 10 38 34 Oscillator 48 MHz MM ANN 64 17 32 49 dum L 1163348 T 1044 3V 24 41 2 RST Voltage detection reset IC etc detection reset IC etc 35 51 104 P our o A Low level is output at reset GND n RST TEP Chapter 3 Single Connection of MKY02 9T ECHNICA Figure 3 17 shows an example circuit for with eight ports in full duplex mode Representative monitor for all ports Receive Not necessary if port receive 5600 be b monitor circuit added LEDRZE V7 Red 5602 Green 3 3V SN751178 5 V SN751178 5 V Pulse transformer Pulse transformer Port 7 i 14 CTS RPSIG 3 62 1 CPSIG Rt 6 Rt RPSIG 4 18 2 cpsic CPSIG 1 3 RPSIG 3 61 Rt 1 Rt CPSIG 2 i q 4 RPSIG uuu shield 6 6 shield Poti 7 7 Port6 CPSIG 1 12 6 1 cpsic Rt i 9 1 Rt CPSIG 2 11 y 2 cPsic 6 RPSIG 3 2 3 RPSIG Rt RPSIG 4 4 Resic DEP LR v GALOS shield 6 Pulse Pulse 6 shield transformer transformer F
12. 212 1 x TAX1 RLDT Setup 211 1 x 1 211 x TAX1 2111 x TAX1 RLDT Hold 211 1 x TAX1 211 x 1 21141 x TAX1 RLCK High level width 211 1 x 1 211 x 1 2111 x TAX1 RLCK Low level width 211 1 x TAX1 211 TAX1 21141 x TAX1 TEP S TECHNICA Co LTD 02 User s Manual for Hi speed Link System 5 3 Package Dimensions 2 64 pins TQFP 12 0 0 2 10 0 0 1 12 0 0 2 0 08 0 22 007 e 0 1 0 0 05 1 2 MAX Unit mm TEP Chapter 5 Ratings S Ttc HNICA CO LTD 5 4 Recommended Soldering Conditions Parameter Symbol Reflow Manual soldering iron Peak temperature resin surface Tp 2559 max 380 max Peak temperature holding time tp 10 s max 5 Caution 1 Product storage conditions 40 max 85 for prevention of moisture absorption 2 Manual soldering Temperature of the tip of soldering iron 380 C 5 s max Device lead temperature 260 C 10 s max package surface temperature 150 C 3 Reflow Twice max 4 Flux Non chlorine flux should be cleaned sufficiently 5 Ultrasonic cleaning Depending on frequencies and circuit board shapes ultrasonic cleaning may cause resonance affecting lead strength 5 5 Recommended Reflow Conditions Package surface temperature Pa
13. The HLS uses a RZ signal format for signals constituting a packet Even if the signal format of the received packet is transformed up to 49 the MK Y02 which is a kind of HUB IC that can be inserted into the HLS network corrects the packet into a RZ signal format to send it Fig 1 12 Therefore in a system in which a signal propagates via multiple HUBs the user can extend the network cable length by the number of inserted 1 without cumulative signal transformation refer to 1 3 1 Extending Total Length of Network Cable gt RZ 1 RZ 1 RZ 0 RZ 0 RZ 1 RZ 1 Signal of transmitting pin Receiver input signal transformed by transmission Signal of receiver DOR E output pin RZ 1 RZ 1 RZ 0 RZ 0 RZ 1 RZ 1 Corrected transmitting signal Passage of time gt Fig 1 12 Example of Signal Transformation and Correction 1 7 3 Detection of Error Packet If the signal transformation of the received packet exceeds 49 the 02 recognizes the packet as an error packet If the 02 detects an error in the received packet during sending the MK Y02 immediately stops sending to prevent improper correction and prevent the error packet from passing When the MK Y02 detects an error packet it outputs pulses to the LEDRZE pin for a given time and notifies the user Generally the main causes for detection of an error packet are as follows 1
14. while RLLD at Low level RLDT X P6X P5 RLCK RLCK at Low level while RLLD at High level TRLDS TRLDH 12 Mbps 341 33 us 2 93 kHz 6 Mbps 682 67 us 5 86 kHz 3 Mbps 1 37 ms 11 72 kHz Pn 1 Pn 1 HN TRLDS min 211 1 x TAX1 TRLDH min 211 1 x TAX1 Fig 3 12 RLLD RLDT and RLCK Outputs As shown in Figure 3 13 adding an 8 bit shift register and 8 bit latch enables to add port receive monitors corresponding to individual ports Figure 3 14 gives an example of the additional circuit for a HUB with four ports when eight ports are not used When the 02 is inserted into an HLS that operates correctly and continuously several cycles of packets are transmitted and received for a time of 2 7 x TAXI Therefore the receive monitors corresponding to the ports connected to the center IC or satellite ICs may always be on TEP S TECHNICA Co LTD MKY02 User s Manual for Hi speed Link System The hardware designer of a HUB needs to determine the port receive monitor LEDs for individual ports and the values of current limiting resistors shown in Figures 3 13 and 3 14 to meet the output specifications for added latches The green LED indicating stability should be connected as a port receive monitor LED Port7 Port6 5 4 Port3 Port2 Port1 Port 0 74273 3 3 V type etc 04 03 02 Q7
15. Port 5 Port 2 Pulse transformer N751178 5 V d P 1 cpsic CPSIG 7 2 CPSIG CPSIG 3 rPSIG RPSIG s 4 rrsiG 6 shield shield Port4 1 CPSIG CPSIG 8 E 2 CPSIG CPSIG gt 3 RPSIG RPSIG A Rt 4 RPSIG EUA RSS Pulse 6 shield ses transformer transformer 56 60 25 Port receive monitor circuit A 20 OI a UE cia E 3 pin regulator etc 33V 54 a 58 27 o N e x 22 5 5 5 5 5 5 5 527 55 a a a 5 26 o 59 0 0 04 y Y 104 2 s e e 2 15 e 1 23 Hr 01 Q2 Q3 Q4 Q5 7 74273 3 3 V 02 03 04 05 1 4 7 8 13 14 17 18 5 7 6 8 9 13 12 14 15 17 16 18 19 16 V 100 uF DC DC power supply etc Power DC5V dq gt 40 t i Green SN751178_Vpp 43 111 RLLD ok 42 80 1kQ 29 GND e ere RLDT CLR JL BPS1 NC open 25 V 100 uF 77 BPSO 3 50 Note Add as necessary two 74273 1 pins 53 10 38 VDD 34 104 AWW 64 17 32 49 Oscillator 48 MHz GND 33V 104 4 1 16 33 48 us 33V 2441 RST Voltage detection reset IC etc Voo 35 51 104 OUT G RsT 46 A Low level is output at reset GND 7 RST TEP S TECHNICA Co LTD MKY02 User s Manual for Hi speed Link System Chapter 4 Cascade Connection of 02 This chapter describes the pin functions and how to connect pins required to design a
16. 3 SIG 2 shield 6 Pulse transformer Port 17 SIG SIG Pulse shield transformer 62 63 50 51 7 3 Error Port 15 to Port 21 45 LEDRZE 9 33V LEDRCV 4 ADM1485 5 V Port 21 nec L4 3 A 1 SIG 4 Rt 6 2 Sic 48 Pulse 6 shield 1 transformer 20 P 77 ADM1485 5 V Pulse transformer Pulse 6 1 u transformer 20 2 n ADM1485 5 V 9 Port receive monitor circuit 4 6 a is 7 7 9 z ES x MKY02 3 t t Pulse o o o o o c e e D a 9 5 1 transformer RXD4 0 40 y 5 R 19 16 15 9 5 2 29 y or as 05 04 Axs2 42 n dcir Pa 3 axs1 40 D7 05 D4 axso 36 2 53 52 1 11 30 x 34 G CLR 29 10 38 64 17 32 49 46 3 3V 1 16 33 48 T 194 77 24 41 7 7 COE4 0 20 33v 0194609 COP1 gt 29 H2 COD1 gt 58 02 2 p B 2 104 55 2 CIP2 cip2 RST AX AX2 nt AXS1 1kQ AXSO RST gt SNS 77 Fig 4 10 Example Circuit for with 22 Ports 3 3 25 V 100 uF SIG shield 7 Port 19 12 1 xm sic 15 DC DC power supply etc TEP Chapter 4 Cascade Connection of MKY02 ST ECHNICA CO LTD
17. 33 48 amp 0 4 OS 2447 11 19 16 15 12 9 6 5 2 Q5 04 0 4e 1 a dcir 115 51 Oscillator 48 MHz D6 05 D4 03 02 D1 7 7 33V 4 3 34 VoD AM OUT 104 rendida 0707 Q6 06 Q5 0504 04 D3 02 0201 D1Q0 53 1 11 30 q CLR CLK 52 WM DO 9 et 20 CIP1 21 Voltage detection reset IC etc cibi CODI 22 eit A Low level is output at reset a CIHR COHR 38 02 2 7 7 COE2 CIE2 COE2 55 26 33V m COP2 CIP2 COP2 COD2 CID2 COD2 OUT 904 o o o o 007 aus RSTAXSO 1 AX1 AXS2 AX2 36 37 40 39 42 43 MI To 2 3 Fig 4 10 Example Circuit for with 22 Ports 1 3 TEP Chapter 4 Cascade Connection of MKY02 S TECHNICA CO LTD Figure 4 10 shows an example circuit for a with 22 ports port 0 of the center side and ports 1 to 21 of the satellite side in half duplex mode In the example the baud rates of 12 Mbps 6 Mbps and 3 Mbps can be set by DIP SW and a port receive monitor circuit 15 added 62 63 Error Port 8 to Port 14 50 LEDRZE o 3 3V LEDRCV JoY ADM1485 5 V Port 14 14 3 1 56 A 2 SIG Port 8 a Pulse i SIG 1 19 lt transformer S shield Rt SIG 2 gt shield 6 Pulse transformer a ADM1485 5 V Port 13 3 1 SIG En Port 9 ADM1485 5 v 4 m 2 we Pulse i Sie 1 6 18 transformer 6 J shield Rt sic 2 NJ
18. Conditions 5 9 Recommended Reflow Conditions 5 9 Chapter 5 Ratings TEP S TECHNICA Co LTD Chapter 5 Ratings This chapter describes the ratings of the MK Y02 5 1 Electrical Ratings Table 5 1 lists the absolute maximum ratings of the MKY02 Table 5 1 Absolute Maximum Ratings Vss 0 V Power supply voltage 0 3 to 4 6 Input voltage Output voltage Vss 0 3 to 6 0 Vss 0 3 to 6 0 Signal pin input current 6 to 6 Peak output current Peak 20 Allowable power dissipation 345 40 to 85 65 to 150 Operating temperature Storage temperature Table 5 2 lists the electrical ratings of the MKY02 Table 5 2 Electrical Ratings 25 Vss 0V Operating power supply voltage Vi VDD or Vss Xi 50 MHz 50 MHz output open Mean operating current Vi VDD or Vss Xi 48 MHz 24 MHz output open Mean operating current operating at 6 Mbps Vi VDD or Vss Xi 48 MHz 12 MHz output open Mean operating current operating at 3 Mbps External input frequency Input to Xi pin Input pin capacitance VpD Vi 0V Output pin capacitance f21MHz 25 capacitance Rise fall time of input signal Rise fall time of input signal Schmitt trigger input 5 2 AC Characteristics Table 5 3 lists the measur
19. EN ER x 12 Function of second cascade connected MKY02 Function of third cascade connected 02 G Fig 1 9 Adding Ports by Cascading MKY02s If a HUB with ports added by cascading MKY02s is added to a network the number of inserted HUBs between terminals and the center IC connected to each port of the HUB is 1 Fig 1 10 Center equipment In this configuration the inserted count of HUBs o viewed from all terminals is 1 Center IC with ports added by cascading three MKYO2s All ports with Rt Center side connection port port 0 Terminal Satellite side connection port Satellite IC Satellite IC Rt Terminal Satellite 19 20 21 Terminal tc Satellite IC Satellite IC Satellite IC Rt Terminal Terminal Terminal Satellite IC satelite lC Satellite IC Terminal Terminal Terminal V Fig 1 10 Inserted Count of HUBs with Added Ports Adding ports by cascading MKY 02s is helpful to setup cables on multi drop network or star topology For details of cascading MK Y 02s refer to Chapter 4 Cascade Connection of MKY02 1 12 TEP Chapter 1 Concepts for Using 02 S TECHNICA CO LTD 1 7 02 Operation This section describes the operation of the 02 Be sure to read this section before adding HUBS to the HLS 1 7 1 Receiving and Sending Packets The 02 operat
20. Figure 3 10 is possible In this case the hard ware designer of a HUB needs to determine values of the 2 current limiting resistors according to the LED rating LEDRCV 50V To test the LED the LEDRCV pin outputs a Low level for 500000 x TAXI while a hardware reset is activated When a High level is output the pin goes to 3 3 V This connection is impossible because leakage current flows and after the hardware reset is canceled Fig 3 10 Connection of Receive Monitor LED The Low pulse output from the ZLEDRCV pin is generated by a retriggerable one shot multivibrator with a minimum time of 500000 x TAX Xi 48 MHz 12 Mbps 43 69 ms 6 Mbps 87 38 ms 3 Mbps 174 76 ms Therefore if any of the eight ports receives a packet again within a given time the Low pulse width becomes wide Even if 12 Mbps is selected as the baud rate of the 02 the narrowest time of the Low pulse is about 43 69 ms and the user can find that the LED is lit The green LED indicating stability should be connected to the ZLEDRCV pin When not used leave this pin open If the MKYO2 is inserted into an HLS that operates correctly and continuously the MINIM FLEDRCV pin outputs a Low level concecutively TEP S TECHNICA Co LTD MKY02 User s Manual for Hi speed Link System 3 4 2 Packet Error Monitor The MKY02 has a ZLEDRZE pin pin 45 that outputs a Low level for a given time when any port receive
21. Single Connection of 02 S TECHNICA CO LTD 3 2 Supplying Driving Clock and Hardware Reset Signal This section describes how to supply a clock that drives the MKY02 and the hardware reset signal 3 2 1 Supplying Driving Clock Connect an oscillator generated 48 MHz clock to the Xi pin pin 34 of the MKY02 for driving clock The specifications for supplying an external clock to the Xi pin are as follows 1 The upper frequency limit is 50 MHz and there is no lower frequency limit 2 For the electrical specifications of the Xi pin refer to Chapter 2 MKY02 Hardware 3 Connect a clock with a signal rise and fall time of 20 ns or less 4 Connect a clock with a minimum High level or Low level time of 5 ns or more 5 Connect a clock with a jitter component of e 250 ps or less at input frequency of 25 MHz or more e 500 ps or less at input frequency of less than 25 MHz 6 Connect a clock with a frequency accuracy of 200 ppm or better TEP S TECHNICA Co LTD MKY02 User s Manual for Hi speed Link System 3 2 2 Setting Cascade Clock and Baud Rate The MKY02 uses three cascade clocks 0 AXI and AX2 It has three cascade clock output pins AXSO AXS1 and AXS2 Fig 3 2 A cascade clock is generated from the external clock supplied to the Xi pin based on a division ratio determined by the settings of the BPSO and BPSI pins Conform the settings of the BPSO pin HUB Function core AXS2 Casca
22. be kept Low for 10 clocks of the AX0 pin cascade clock or more Fig 3 4 while supplying a cascade clock to the pin axo MIN OM NM NM EN NE E EH EH EH EE RST No reaction to pulse Must be kept Low for 10 or more clocks with less than 1 clock Fig 3 4 Hardware Reset Caution Design the circuit so that a hardware reset is surely activated immediately after MK Y02 power on TEP S TECHNICA Co LTD MKY02 User s Manual for Hi speed Link System 3 3 Connecting Network Interface This section describes connection of a network interface network The MKY02 is a IC with eight ports The MKY02 has one communication mode select pin common to all ports and eight sets of network I F pins Port 0 has three network I F pins RXDO TXEO and TXDO Ports 1 to 7 correspond to RXD1 pin to RXD7 pin and TXE pin to TXE7 pin respectively but there is no individual TXDn pin There is one common TXD17 pin 3 3 1 Selecting Communication Mode When the specification of the HLS containing a HUB configured using the MK Y02 is full duplex mode fix the FH pin pin 51 at High When the specification is half duplex mode fix the FH pin at Low Fig 3 5 In addition conform the specification of the TRX driver receiver components of the network cable con nected to each port to the setting of the FH pin a Full duplex Half duplex MKY02 MKY02 Fig 3 5 Selectin
23. cascade connected Output pin for cascade connection Positive Connect to the CID1 pin of the 02 for lower cascade connection Leave this pin open when is not cascade connected Output pin for cascade connection Positive Connect to the CIHR pin of the 2 for lower cascade connection Leave this pin open when is not cascade connected Input pin for cascade connection Positive Connect to the 2 pin of the 02 for lower cascade connection Fix this pin at Low when is not cascade connected Input pin for cascade connection Positive Connect to the COP2 pin of the 02 for lower cascade connection Fix this pin at Low when it is not cascade connected Input pin for cascade connection Positive Connect to the COD2 pin of the 02 for lower cascade connection Fix this pin at Low when is not cascade connected Positive Be sure to leave this pin open Data signal output pin for receive monitor LED drive circuit of individual port Positive EE SA Leave this pin open when it is not used Data clock output pin for receiving monitor LED drive circuit of individual port Positive 555 50 089 Leave this pin open when it is not used Data load signal output pin for receiving monitor LED drive circuit of individual port Positive E D Leave this pin open when it is not used Positive External clock input pin 48 MHz recommended MKY02 hardware reset input pin Negative Keep this pin Low fo
24. center side Packet Port 0 receive Port 0 send Port 1 send Port 1 receive Port 2 send Port 2 receive gt Ports other than the active port do not receive Port 3 send Port 3 receive a packet Port 4 send Port 4 receive If the ports receive packets e E simultaneously priority is given Port 5 send Port 5 receive i to the small port number Port 6 send Port 6 receive Port 7 send Port 7 receive Passage of time 52 x TBPS max 52 x TBPS max V Fig 1 11 02 Operating Principles Reference 1 Most of communication HUBs other than StepTechnica s are designed to start sending after receiving the full packet length This mechanism decreases the signal response speed of the entire system significantly in particular in a system with inserted a lot of HUBs As shown in Figure 1 11 the 02 sends the corrected packet while receiving the packet which causes only a slight decrease in the signal response time of the entire system 1 13 TEP S TECHNICA Co LTD MKY02 User s Manual for Hi speed Link System 1 7 2 Signal Correction To lengthen the total extension of a network cable in general a buffer is inserted to amplify signals When the baud rate is relatively low buffer insertion is practical However when the baud rate is high fast buffer insertion 1 impractical because signals transformed by signal propagation along network cables cannot be corrected even if they are amplified
25. of Network Cable Length The user system can extend the recommended network cable length by adding the inserted count of HUBs 1 to the basic HLS configuration For example adding a single HUB doubles cable length adding two HUBs triples cable length and adding seven HUBs increases the cable length eightfold Table 1 1 shows the baud rates and the recommended total extension based on the number of the inserted HUBs when using the recommended network connection Table 1 1 Baud Rates and Recommended Total Extension Number of Inserted HUBs Number of inserted HUBs Baud rate 0 Basic configuration 1 2 4 5 6 7 TEP Chapter 1 Concepts for Using MKY02 HUB S TECHNICA CO LTD Reference DAE ers cable types cabling environments and how many cables are multi drop connected The practical limit of network cable length varies with the performance of drivers receiv StepTechnica s recommended network cable length is about 1 2 of the cable length limit obtained from our practical experiments These values are provided as a guide for stable HLS operation in various user systems but performance is not guaranteed Therefore in many user systems the user can use the network cable longer than the total length shown in Table 1 1 Caution The maximum number of HUBs that can be added is determined by the function of the cen ter IC For example if the user system uses the MKY36 as
26. 0 Inserted Count of HUBs with Added 1 12 Fig 1 11 02 Operating 4 44 222 00 nn 1 13 Fig 1 12 Example of Signal Transformation and Correction 1 14 Fig 2 1 MKYO2 Pin 5 00 gna ni iii 2 3 Fig 2 2 Pin Electrical Characteristics in I O Circuit Types of 02 2 6 Fig 3 1 Connection Causing Leakage Current eene 3 4 Fig 3 2 Cascade Clock Generation 3 6 Fig 3 3 Clock GonnectDHh iuuenes irl undi cao cus Rada s So UE FEY YEAR 3 6 Fig 3 4 Hardware cuti nei ras arms CEU Rd edi 3 7 Fig 3 5 Selecting Communication Mode 4 408 502 0 4 3 8 Fig 3 6 Connection of Port seccional 3 8 Fig 3 7 Connection of Ports 1 07 200 800 3 9 Fig 38 Connection of HUB with 4 Ports 3 9 Fig 3 9 Recommended Network Connection 1 3 10 Fig 3 10 Connection of Receive Monitor LED eene 3 11 Fig 3 11 Connection of Packet Error Monitor LED eene 3 12 Fig 3 12 RLLD RLDT and RLCK Outputs
27. 5 2 2 Port Pin Timing TXEO to 7 TXDO TXD17 RXDO 7 5 5 5 2 3 Cascade Connection Pin Timing esee nennen nennen nennen 5 6 5 2 4 Output Timing of ZLEDRCV and ZLEDRZE Pins eee 5 6 5 2 5 Timing of Receive Monitor Pin of Individual Port RLLD RLDT 5 7 5 9 Package DIMENSION Sii 5 8 5 4 Recommended Soldering Conditions 444 22 5 9 5 5 Recommended Reflow Conditions eene nnn 5 9 TEP 2 User s Manual S TEcHNICA 9 Figures Fig 1 1 Basic HLS Config ratlofi 1 3 Fig 1 2 Extension of Network Cable Length 1 4 Fig 1 3 Multipoint Connection of Network Cables eee 1 6 Fig 1 4 Eliminating Problems with Termination Resistors 1 7 Fig 1 5 Stark TOPOLOGY io Sac FEY DERE 1 8 Fig 1 6 Serial Connection of Fiber optic 22 1 9 Fig 1 7 Basic Connection and Number of Inserted HUBS 1 10 Fig 1 8 in Intermediate Position of Multi drop Network 1 11 Fig 1 9 Adding Ports by Cascading 25 1 12 Fig 1 1
28. 7 Port 0 Port 3 M Port 7 E Port 4 4 Signal connection between Port 5 cascade connection pins Port 6 CIE1 CIP1 CID1 CIHR For Port 8 Port 7 Port 9 Port 8 Port 10 Port 0 Port 9 Port 11 Port 10 t Port 12 Port 11 COE1 COP1 COD1 COHR Port 13 2 Port 7 CIE2 CIP2 CID2 M Port 14 Port 13 Port 14 COE2 COP2 COD2 Panis CIE1 CIP1 CID1 CIHR Port 15 Port 16 Port 16 Port 17 En Port 17 Port 18 Port 48 Port 19 Port 19 Port 20 Port 6 o Port 20 Port 21 Port 7 M Port 21 COE1 COP1 COD1 COHR CIE2 CIP2 CID2 Fig 4 2 Port Addition by Three Cascade Connections 4 1 3 Maximum Available Cascade Connections When configuring a HUB for HLS up to 9 MKYO2s can be cascade connected Therefore the to which ports were added by cascade connection has a maximum number of one port of the center side and 63 ports 7 ports x 9 of the satellite side Chapter 4 Cascade Connection of MKY02 4 2 Practical Side of Cascade Connection This section describes the practical side of cascade connection 4 2 1 Cascade Pins TEP S TECHNICA Co LTD The 2 has the priority cascade pins CIEI pin 60 pin 59 CIDI pin 58 CIHR pin 57 COE pin 20 COPI pin 21 CODI pin 22 and COHR pin 23 and the reverse priority cascade pins CIE2 pin 25 CIP2 pin 26 CID2 pin 27 COE2 pin 56 COP2 pin 55 and COD2 pin 54 To cascade connect the 02 proceed as fo
29. DO RXD6 VDD VDD Sonoros LILILILILILILILILILILILILILILILI CN c s ON CO s OQ r 10 zoooouuuuoruuu lz 955 gt 09 Note Pins prefixed with negative logic active Low Leavethe NC pin pin 28 open 9 2 1 2 Pin Assignment TEP S TECHNICA CO LTD 02 User s Manual for Hi speed Link System Table 2 1 lists the pin functions of the MK Y02 Table 2 1 Pin Functions of MKY02 resume Pine T use uo Input pins that input response packets RP from satellite ICs RXD1 to 2105 Ge Connect to output pins target port receivers When multiple ports input signals simulta ositive RXD7 15 18 19 neously priority is given to pins with smaller port number Fix these pins at High or Low when not in use These pins go High when the ports of satellite ICs are enabled for sending TXE1 to 6 to9 TXE7 12 to 14 Positive Connect to gate pins of target port drivers Leave these pins open when not in use Output pin that output command packets CP to ports of satellite ICs Positi i i Connect to input pins of port 1 to 7 drivers Output pin for cascade connection Positive Connect to the pin of the 02 for lower cascade connection Leave this pin open when it is not cascade connected Output pin for cascade connection Positive Connect to the pin of the 02 for lower cascade connection Leave this pin open when is not
30. O2 other than the highest priority one open Fix the RXDO pin pin 61 of any 02 other than the highest priority one at a High or Low level Connect the TRX to each satellite port of multiple MKY 02s refer to 3 3 3 Connection of Ports 1 to 7 and use it as a port to connect to the satellite IC For the handling of unused ports refer to 3 3 3 tion of Ports 1 to 7 If multiple MKY 02s are cascade connected ports are assigned priorities in descending order Therefore number the satellite ports according to priority Fig 4 2 i Even if TRX is connected to port 0 of any MKY02 other than the highest priority one like port 0 of the highest priority 2 there is no problem because no packet is received unless the communication lines are connected This is effective when designing circuit boards for the single connection and cascade connection to be shared EP T Chapter 4 Cascade Connection of MKY02 S Tc HNICA CO LTD 4 2 7 Placement of Monitor LEDs The 2 has the function to connect various monitor LEDs refert to 3 4 Connecting Monitor LEDs In the port added HUB by cascade connecting multiple MK Y02s depending on the placement of monitor LEDs the level of convenience increases in user system installation network cable setup and vari ous maintenance works refer to Fig 4 9 7 Port added HUB by cascade connecting three MKY02s 0 e ma Center side connect
31. OP2 2 2655 COP2 2 C 21 59 21 59 CIP1 Pul COP1 2 7 1 CIHR COHR 29 9r CIHR COHR 28090 CIHR M Priority MKY02 1 MKY02 2 COE2 COE2 CIE1 1 CIE1 1 COD2 CID2 COD2 CID2 CID1 COD1 CID1 COD1 2 2 2 2 1 COP1 23 57 CIHR COHR CIHR COHR Fig 4 3 Cascade Pin Connection for Three 025 Fig 4 4 Cascade Pin Connection for Two MKY02s TEP S TECHNICA Co LTD 4 2 2 Operation of Cascade Connection Pins MKYO02 User s Manual for Hi speed Link System The cascade connection pins of the cascade connected MK Y02 operate as follows 1 The packets which port 0 of the highest priority MK Y02 received are transmitted from ports 1 to 7 and are also transmitted from ports 1 to 7 of another MK Y02 via the priority cascade connection pins COE1 COPI CODI COHR CIEI CID1 Fig 4 5 At this time the transmit packet data that is of an NRZ signal format is output from the COD1 pin and its minimum pulse width is a time of 2 x TBPS The High level status signals for packet transmission control are output from the COEI COPI and COHR pins 2 The packets which ports 1 to 7 of the non highest priority 2 received are transmitted from port 0 of the highest priority 02 the
32. RXD of terminal 3 Passage of time The serial signal quality is excessively degraded For example if serial signals with a High level width of 100 ns 10 Mbps are E O converted at a distortion of 30 ns and signal distortion is accumulated three times the signals will be distorted from 30 ns to 90 ns Fig 1 6 Serial Connection of Fiber optic Cables Adding HUBs into the network using the HLS to connect ports and terminals one on one as shown in Fig ure 1 4 and 1 5 excluding multi drop connected part makes it easy to use fiber optic cables A one connection between ports and terminals does not cause cumulative signal distortion 02 User s Manual for Hi speed Link System TEP S TECHNICA Co LTD 1 4 Basic HUB Connection When adding HUBs to the HLS connect them so that the HLS can be a tree structure as shown in Figure 1 7 In such a tree structure the route node close to the center equipment is called the center side Be sure to connect port 0 to the center side The number of HUBs to be added in the routes derived from the center equipment is called the number of inserted HUBs The number of inserted HUBs is determined by the type of center IC and settings made at the center IC by the user system N Center equipment Center ec HUB Number of inserted HUB 1 Rt Terminal Satellite IC HUB Num
33. Terminal Satellite Rt c Terminal Center equipment Satellite IC Rt CenterIC HUB IC Rt o Terminal Rt Satellite IC Rt o Terminal Satellite A network cable in a star topology can also be multi drop connected m Satellite IC Satellite Satellite IC Satellite Terminal Terminal Terminal Terminal V Fig 1 5 Star Topology TEP Chapter 1 Concepts for Using 02 S TECHNICA CO LTD 1 3 5 Handling Fiber optic Cables There will be difficulties in multi drop network of transmission signals using fiber optic cables 1 Branching or connection of optical signals is extremely difficult 2 Optical to electrical O E conversion and branching or connecting and then electrical to optical E O conversion can cause cumulative signal distortion Therefore it is impractical to transmit in signals at high baud rates via fiber optic cables Fig 1 6 Center equipment E 0 Conversion of signals OE Conversion of signals Center IC Fiber optic cables Selector x A Selector ii Selector S B S B S B wE T eu Ix met ho Terminal 1 Satellite IC Terminal 2 Satellite IC Terminal 3 Satellite IC Example of signal propagation Extreme example where signal conversion causes delay in propagation and increases High level width resulting in cumulative signal distortion TXD of center equipment RXD of terminal 1 RXD of terminal 2
34. The center equipment and the terminal with satellite ICs were disconnected or system failure or the network cables were disconnected 2 The packet format was damaged by external noise and improper environments 3 The network performance reached the limit 4 Improper setup of the system or cables including the satellite address SA overlap 5 The system is operating in an extremely poor environment The detection frequency of error packets increases in the order of 1 to 5 above For example in 1 error packets are detected only when the terminal 15 disconnected but in 5 above error packets are detected fre quently If error packets are detected the user needs to improve the system and environment 1 14 TEP Chapter 1 Concepts for Using MKY02 HUB S TECHNICA CO LTD 1 8 Features of MKY02 This section describes the features of the MKY02 HUB IC for the HLS 1 Supports full and half duplex communication modes 2 Supports any baud rates up to 12 5 Mbps including standard baud rates of 12 6 and 3 Mbps 3 Has a dedicated port port 0 connecting the center IC and seven ports ports 1 to 7 connecting satel lite ICs This can facilitate configuration of a HUB with two to eight ports using one MKY02 4 Has output pins that can turn on monitor LEDs when any one or more of the eight ports receive a packet 5 Has output pins for receiving monitor for each port to turn on monitor LEDs when eight ports receiv
35. a center IC the user can add up to seven HUBs For details refer to Center IC User s Manual TEP S TECHNICA Co LTD MKY02 User s Manual for Hi speed Link System 1 3 2 Branching Multi dropped Network Cables The network cables can be branched by adding HUBs to the HLS network Figure 1 3 shows an example of an HLS configuration in which network cables are branched N Branching network cables in basic HLS configuration Branching network cables is impossible due to impedance mismatches Center equipment Rt Satellite IC a Satellite IC Satellite IC o Satellite IC Terminal Terminal Terminal Terminal Satellite Terminal Satellite IC R Terminal Branching network cables by addition of HUB Adding HUB enables branch of network cables Center equipment HUB Center IC Rt Satellite Satellite Satellite Satellite Terminal Terminal Terminal Terminal Recommended cable length t 12 Mbps 7100 Satellite IC 6 Mbps 200 3 Mbps 300 Terminal o Satellite IC Terminal M P Fig 1 3 Multipoint Connection of Network Cables Figure 1 3 shows the network cables that are branched in T shape Adding HUB using the MKY02 also enables multiple branchings with man
36. ace This manual describes the MKYO2 or a kind of HUB IC in a Hi speed Link System Be sure to read Hi speed Link System Introduction Guide before understanding this manual and the MKY02 In this manual the Hi speed Link System is abbreviated as HLS e Target Readers This manual is for Those who first build an HLS Those who first use StepTechnica s various ICs to build an HLS e Prerequisites This manual assumes that you are familiar with Network technology e Semiconductor products especially microcontrollers and memory Related Manuals Hi speed Link System Introduction Guide Hi speed Link System Technical Guide Hi speed Link System Center IC Manuals Caution Some terms in this manual are different from those used on our website and in our product bro chures The brochure uses ordinary terms to help many people in various industries understand our products Please understand technical information on HLS Family and CUnet Family based on technical documents manuals B This manual has been prepared based on Standard English M meeting the requirements of the International Organization for Standardization ISO and the American National Standards Institute ANSI This English manual is consistent with the Japanese document STD 502 1 5 Standard English is a trademark of Win Corporation ii TEP S TECHNICA CO LTD MKY02 User s Manual for Hi speed Link Syst
37. be within 40 cm 4 2 4 Connection of Hardware Reset Signal Connect the hardware reset signal common to all MK Y02s to be cascade connected to the RST pin pin 35 Fig 4 7 For the specification of the hardware reset signal follow the description in 3 2 3 Hardware Reset TEP S TECHNICA Co LTD MKY02 User s Manual for Hi speed Link System 4 2 5 Selecting Communication Mode When the specification for the HLS inserted the port added HUB configured by cascade connecting mul tiple 025 is full duplex mode fix the FH pin pin 51 of all MKY02 at High When the specification indicates half duplex mode fix the FH pin at Low Fig 4 8 In addition conform the specification for the TRX driver receiver components of the communication line connected to each port to the setting of the FH pin 2 Full duplex mode Half duplex mode All MKY02 All MKY02 celsa EN FH Fig 4 8 Selection of Communication Mode Caution The full duplex mode and half duplex mode cannot be mixed for cascade connection Be sure to select the same mode for the MKYO2s to be cascade connected 4 2 6 Connection of Each Port In the port added HUB configured by cascade connecting multiple 025 connect TRX to port 0 of the highest priority 02 refer to 3 3 2 Connection of Port 0 and use it as a port to connect to the center IC Leave the TXEO pin pin 62 and TXDO pin pin 63 of any MKY
38. ber of inserted HUBs 2 Rt Rt a Rt o Terminal Satellite IC Satellite IC Satellite IC Terminal Satellite Terminal Terminal Satellite IC Number of inserted HUBs 3 Rt Rt Rt Rt Rt Rt Rt Satellite IC Satellite IC Satellite IC Satellite IC m m Satellite Satellite IC Satellite Terminal Terminal Terminal Terminal Terminal Terminal Terminal Fig 1 7 Basic Connection and Number of Inserted HUBs Caution the system using the MKY36 as a center IC the user can add up to seven HUBs No HUBS can be into a system using the MK Y33 as a center IC For details on each of center ICs refer to User s for the center IC 1 10 EP T Chapter 1 Concepts for Using 02 S TECHNICA CO LTD 1 5 Multi drop Network of HUBs When adding HUBs to the HLS the user can connect HUBs as multi drop Fig 1 8 The multi drop network of HUBs is suitable for a user system in which the network cables should be divided The number of inserted HUBs shown in Figure 1 8 is 1 As shown in Figure 1 8 in cases where port 0 of the HUB is placed in the intermediate position the halfway position in the network cable of a multi drop network do not connect a termination resistor to the port 0 For details of the connection of a termination resistor refer to Hi speed Link System Technical Guide 2 Ce
39. bles with impedance of 100 Q Connect a 100 Q termination resistor to the end of the network cables Connecting the resistor before or after the pulse transformer has the same effect Half duplex mode MKY02 Equivalent to ADM1485 LSI driven at 5 0 V Pulse transformer Network cable One twisted pair cable with impedance of 100 Q Connect a 100 Q termination resistor to the end of the network cables Connecting the resistor before or after the pulse transformer has the same effect Fig 3 9 Recommended Network Connection Reference described in Hi speed Link System Technical Guide For more information about how to select components or to get recommended components visit our Web site at Background information to help build a netwok and details of termination resistor are http www steptechnica com TEP Chapter 3 Single Connection of 02 S TECHNICA CO LTD 3 4 Connecting Monitor LEDs This section describes connection of monitor LEDs 3 4 1 Packet Receive Monitor The MKY02 has a LEDRCV pin pin 44 that outputs a Low level for a given time when any of the eight ports receives a packet When an LED that goes on at Low level is connected to this ZLEDRCV pin it indi cates that the HUB of the MK Y02 is operating correctly MKY02 This FLEDRCV pin has a drive capability of 8 mA If a mA 3 V the LED can go on even at 8 mA or less the connection Green shown in
40. d in 4 2 2 Operation of Cascade Connection Pins Therefore in the port added HUB by cascade connecting the MKY02 place the packet receive monitor and packet error monitor by the number of 02 to be used TEP S TECHNICA Co LTD MKY02 User s Manual for Hi speed Link System 4 3 Example Circuit for Port added HUB by Cascade Connection 33 V 50 51 n Port 0 ADM1485 5 V SIG 1 6 3 62 Rt 4 63 SIG 2 gt shield 6 Pulse 61 transformer 1 A 2 n Port 1 ADM1485 5 V SIG SIG aN Error Port 0 to Port 7 45 LEDRZE e 33V eorcv p Pet 44 3 E 1 96 4 E 2 sic Pulse 19 transformer shield 20 P ix 7 7 Port 6 ADM1485 5 V 4 shield Pulse 18 Pulse shield transformer transformer Q 6 2 M Port 2 ADM1485 5 V o Rt Port 5 SIG 1 3 7 12 3 1 SIG 6 6 SIG 2 e gt 6 2 SIG i Pulse Pulse sie transformer 1 3 19 1 transformer Sp snes 76 2 29 D 111 77 2 1 Port 3 ADM1485 5 V ADM1485 5 V Port 4 516 3 9 3 1 96 SIG ES 2 sic QM i Pulse Pulse shield transformer gt 4 5 1 transformer 6 shield Q 2 2 D n 7 111 Port receive monitor circuit 10 38 UE A o o PTA a 3 3V M 2 2 2 N vea 104 x4 o 22 22 22 22 22 2 1 16
41. de clock generator AXS1 AXSO Fig 3 2 Cascade Clock Generation 52 and BPS1 pin 53 pins to the baud rates of the HLS system into which the HUB is inserted To use a cascade clock connect the output signal of the AXSO pin to the pin of the AXSI pin to the AXI pin and of the AXS2 pin to the AX2 pin as shown in Figure 3 3 Table 3 1 shows the output frequencies of cascade clocks from the 50 AXSI and AXS2 pins corresponding to the settings of the 50 and BPS1 pins when connecting a 48 MHz external clock to the Fig 3 3 Clock Connection Xi pin Table 3 1 Output Frequencies of Cascade Clocks i i 6 MHz 3 MHz 1 5 MHz 750 kHz 7 Reference The configuration to input cascade clocks output from the pins of the MKY 02 to the pins of cu I the MKYO02 again enables cascade connection of the 02 described in Chapter 4 Cascade Connection of MKY02 To design the with two to eight ports config ured using one MKY O02 connect the output signals as shown in Figure 3 3 TEP Chapter 3 Single Connection of 02 S TECHNICA CO LTD 3 2 3 Hardware Reset When a Low level signal is input to the RST ReSeT pin pin 35 the 02 is hardware reset Ifa period in which the Low level signal has been input is less than one clock of the 0 cascade clock the signal is ignored to prevent a malfunction To reset the MKY02 completely RST pin must
42. e packet 6 Has output pins that can turn on monitor LEDs when any one or more of the eight ports receive an error packet 7 Has pins for cascade connection that can add ports 8 Can be connected to both 5 0 V and 3 3 V TTL level signals using 5 0 V tolerant signal pins 9 Operates 3 3 V single power supply and available 0 5 mm pitch 64 pins Caution The 02 can be used as the CUnet family of HUBs by setting the HC pin pin 50 However HLS and CUnet networks cannot be connected via the that the MKY 02 is not a bridge for connecting networks using different family products 1 15 TEP S TECHNICA Co LTD 02 User s Manual for Hi speed Link System Chapter 2 MKY02 Hardware This chapter describes the hardware such as pin assignment pin functions and input out put circuit type of the 02 TEP Chapter 2 MKY02 Hardware S TECHNICA CO LTD Chapter 2 MKY02 Hardware This chapter describes the 02 hardware such as pin assignment pin functions and I O circuit type Figure 2 1 shows the MKY02 pin assignment MKY02 64 pins TQFP 55 SONS 0 0 YN NN 0 0 ATLETI 1008 000000000000 LEE ELE FE EE EE FL ELE FE FEL EE FE O DD I 9 9399 9858858 VDD VDD HC RLLD FH RLCK BPSO RLDT BPS1 T E P N C open COD2 CID2 COP2 5 CIP2 COE2 CIE2 CIHR GND MKYO2 CIP1 COD1 CIE1 COP1 RXDO COE1 TXEO RXD7 TX
43. e COPI pin of the MK Y02 for higher cascade connection Fix this pin at Low when it is not cascade connected CIE1 Positive Input pin for cascade connection Connect to the COEI pin of the 02 for higher cascade connection Fix this pin at Low when it is not cascade connected RXDO Positive Input pin that inputs command packet CP from center IC Connect this pin to output pin including receiver etc TXEO Positive This pin goes High when sending to the center IC is enabled Connect this pin to gate pin including driver etc TXDO 63 Positive Pin that sends response packet RP to center IC Connect this pin to drive input pin including driver etc VDD 10 17 32 38 49 64 Power pins for 3 3 V supply GND 1 16 24 33 41 48 Positive Positive Positive Positive Positive Positive Positive Positive Positive Power pins connected to 0 Note Pins prefixed with are negative logic active Low TEP S TECHNICA Co LTD MKY02 User s Manual for Hi speed Link System Table 2 2 and Figure 2 2 shows the electrical ratings of the MK Y02 pins Table 2 2 Electrical Ratings of MKY02 Negative logic gt OJO oJo gt gt gt gt Ol eS LEDRCV LEDRZE TEST1 gt TEST2 5 0 V tolerant input
44. e pulse width as RZ signal Long pulse width of input signal 1 51 x TAX1 2 0 x TAX1 2 49 x TAX1 Allowable pulse width as RZ signal TEP S TECHNICA Co LTD 5 2 3 Cascade Connection Pin Timing 02 User s Manual for Hi speed Link System Tcs1 COE1 CIE1 COHR CIHR COE2 CIE2 idu COP 1 CIP1 COP2 CIP2 CODI CID1 COD2 CID2 Tcs3 Tcs3 Cascade connection signal 1 146 x TAX1 Passage of time 146 x TAX1 5 ns Cascade connection signal 2 142 x TAX1 Cascade connection signal 3 High or Low level short pulse width 2 x TAX1 5 ns 5 2 4 Output Timing of ZLEDRCV and LEDRZE Pins 142 x TAX1 5 ns 2 x TAX1 5 ns HLEDRCV LEDRZE CUR 7 TLED Pin Low level width 500 000 x TAX1 po TEP Chapter 5 Ratings S Tc HNICA CO LTD 5 2 5 Timing of Receive Monitor Pin of Individual Port RLLD RLDT RLCK TRLLD TRLLL gt RLLD RLDT X Pe P5X PAX P3 P2 P1X PO P7 XP6XP5 RLCK Hmmm TRLD Passage of time Hi TRLDS TRLDH 1 1 TRLCH TRLCL Name Monitor status update interval 217 1 x TAX1 217 21741 x TAX1 RLDT output time RLDT bit time 219 1 x TAX1 212 1 x TAx1 215 x TAX1 212 x TAX1 215 1 x TAX1
45. eiver output Port2 TRX Port 1 TRX Driver input Driver input Driver enable Driver enable Receiver output Receiver output Port 3 TRX Port 2 TRX Driver input river input Driver enable river enable Receiver output eceiver output Port 4 TRX Port 3 TRX Driver input Driver input Driver enable Driver enable Receiver output Receiver output Port 5 TRX Driver input Driver enable Receiver output Port 6 TRX Driver input Driver enable Receiver output Port 7 TRX Driver input Driver enable Receiver output J N Fig 3 7 TRX Connection of Ports 1 to 7 Fig 3 8 TRX Connection of HUB with 4 Ports TEP S TECHNICA Co LTD MK Y02 User s Manual for Hi speed Link System 3 3 4 Recommended Network Connection Figure 3 9 shows a recommended network connection The TRX driver receiver components consists of an RS 485 driver receiver LSI driven at 5 0 V and a pulse transformer Recommended network cables include Ethernet LAN network cables LOBASE T Category 3 or higher and shielded network cables When operating the HLS full duplex mode requires two twisted pair cables and half duplex requires one twisted pair cable When HUB ports are connected at the end of the network cable connect a termination resistor When HUB ports are connected in the intermediate position of the network cable do not connect a termina tion resistor Full duplex mode Equivalent to SN751178 MKY02 LSI driven at 5 0 V Two twisted pair ca
46. em TEP S TECHNICA Co LTD 02 User s Manual CONTENTS Chapter 1 Concepts for Using 02 17 AAA PP O 1 3 1 2 Basic HES ConfiguraliOri aii as ia ey E RR RE 1 3 1 3 HLS Configuration using HUBS nnne nnn 1 4 1 3 1 Extending Total Length of Network Cable eene 1 4 1 3 2 Branching Multi dropped Network Cables esses 1 6 1 3 3 Eliminating Connection or Disconnection of Termination Resistor t or from 1 7 1 3 4 Star Topology rennen te cada aci aa RE acid ta 1 8 1 3 5 Handling Fiber optic nennen nennen 1 9 1 4 Basic HUB Connection 1 10 1 5 Multi drop Network 2 2 1 11 1 6 Port Addition to HUB Sen ro nents 1 12 1 7 2 1 13 1 7 4 Receiving and Sending Packets seen nnne nnns 1 13 1 7 2 Signal Correction eontra 1 14 1 7 3 Detection of Error Packet nennen nnne nnn nennen 1 14 1 8 Features OF MICYO2 conidios 1 15 Chapter 2 MKYO02 Hardware 2 3 Chapter 3 Single Connection o
47. ement conditions for AC characteristics of the 2 Table 5 3 AC Characteristics Measurement Conditions Output load capacitance Power supply voltage Temperature TEP S TECHNICA Co LTD MKY02 User s Manual for Hi speed Link System 5 2 1 Clock and Reset Timing Passage of time Xi TXIL 50 51 AXS1 TAxs2 AXS2 TRST 50 RST Clock period width Clock High level width Clock Low level width Reset enable Low level width TAXS2 TAX2 1 50 pin TAXSO TAXO TAXS1 TAX1 4 x TXI 8 x TXI Remarks Xi 48 MHz 8 x TXI 16 x TXI 16 x TXI 32 x TXI 32 x TXI 64 x TXI Input the clock output from AXSO pin to pin Reference Input the clock output from AXSI pin to AXI pin Input the clock output from AXS2 pin to AX2 pin Chapter 5 Ratings TEP S TECHNICA CO LTD 5 2 2 Port Pin Timing TXEO to 7 TXDO TXD17 RXDO to 7 TTXEH TXEO to 7 RZ 1 RZ 1 RZ 0 RZ 0 RZ 1 TXDO TXD17 5 RZ 1 RZ 1 RZ 0 RZ 0 RZ 1 RXDO to 7 TRNW TRWW TRWW Passage of time Symbol Short pulse width of sendng signal Unit Period in which TXE pin goes High 146 x TAX1 146 x TAX1 5 ns Remarks Short pulse width of input signal 0 51 x TAX1 1 0 x TAX1 1 49 x TAX1 Allowabl
48. es as follows 1 When the 02 receives a packet from port 0 center side port it corrects the signals constituting the packet into a complete format and sends the corrected packet to ports 1 to 7 2 When the 02 receives a packet from any one of the ports 1 to 7 satellite side ports it corrects the signals constituting the packet into a complete format and sends the corrected packet to port 0 During a series of operations ports other than the active port do not receive a packet For example while port 3 is active ports 1 2 and 4 to 7 do not receive a packet 3 When the FH pin of 02 is High level full duplex mode the above operations 1 and 2 function independently 4 When the FH pin is Low level half duplex mode either of the above operations 1 and 2 starting first functions During this period no ports receive a packet As described in 1 and 2 above the MK Y02 corrects the received packet into a complete format and sends it resulting in a time lag of 52 x TBPS max from receiving to sending packets Fig 1 11 Each port of the 2 has priorities to handle system exceptions generated when multiple ports receive a packet simulta neously 02 starts operation in ascending order of port numbers Fig 1 11 In full duplex mode ports 0 and 1 have no priorities Functions from center side to satellite side Functions from satellite side to
49. f MKY02 3 1 Voltage Levels of Pins Connecting to Signal 3 4 3 2 Supplying Driving Clock and Hardware Reset Signal 3 5 3 2 1 Supplying Driving 3 5 3 2 2 Setting Cascade Clock and Baud Rate eene 3 6 3 2 3 A AA reet nee 3 7 3 3 Connecting Network Interface 3 8 3 3 4 Selecting Communication Mode eee 3 8 3 3 2 Connection of Port O eene 3 8 3 3 3 Connection of Ports 1 to 7 nennt nennen nnn 3 9 3 3 4 Recommended Network Connection esee nnne nnns 3 10 3 4 Connecting Monitor LEDs niit nra rias di inicias 3 11 3 4 1 Packet Receive Monitor eese nnne nnne nnne nenne nennen 3 11 3 4 2 Packet Error Monitor eren eene 3 12 3 4 3 Port Receive nennen nennen nenne nennen inen nennen 3 13 3 5 Handling Cascade Connection Pins eene 3 15 3 6 Cautions for Designing arc exer pinus ach CR COUR C DT A nn da a a ERE 3 15 3 7 Example Circuit for Single Connection of MKYO2 3 16 TEP S TECHNICA Co LTD MKY02 Use
50. g Communication Mode Reference In half duplex mode signals output from the TXD pins of the MKY02 may be input directly to RXD pins of 02 while the 02 is sending command packets The 02 is designed not to input data when the pin is High when operated in half duplex mode so there is no problem 3 3 2 Connection of Port 0 Connect of port 0 to three network I F pins RXDO TXEO and TXDO Fig 3 6 02 TRX Driver input Driver enable Receiver output Network Fig 3 6 TRX Connection of Port 0 EP T Chapter 3 Single Connection of 02 S TECHNICA CO LTD 3 3 3 Connection of Ports 1 to 7 Connect the output signals of the TXD17 pin to the driver input pins of the TRX driver receiver compo nents connected to ports 1 to 7 Connect the output signals of the transmit enable pins TXE1 to TXE7 of the 02 to the driver enable input pins of the TRX connected to ports 1 to 7 Connect the receiver out put signals of TRX to the input pins RXD1 to RXD7 of the MKYO2 Fig 3 7 When using selected ports of the satellite side in the use the ports in the order of lowest to highest port number In this case fix the input pins RXDn of unused ports at High or Low and leave the transmit enable pins open Fig 3 8 Port 1 TRX PortO TRX Driver input Driver input Driver enable Driver enable Receiver output Rec
51. he settings of the 51 and BPSO pins from the clock to be input to the Xi pin refer to 3 2 2 Setting Cas cade Clock and Baud Rate When multiple MK Y02s 15 cascade connected for use the cascade clock generated by the highest prior ity MKY 02 is supplied to another MK Y02 Fig 4 7 The baud rate set for the highest priority MK Y02 also applies to another MK Y02 Handle any MK Y02 other than the highest priority one as follows refer to Fig 4 7 1 Fix the Xi pin pin 34 at a Low level or a High level when left open this pin can be fixed at a High level due to an internal pull up resistor 2 Fix the BPSO pin pin 52 and BPS1 pin 53 pin at a Low level or a High level when left open these pins can be fixed at a High level due to an internal pull up resistor 3 Leave the AXSO pin pin 36 AXSI pin pin 40 and AXS2 pin pin 42 pin open Open Fix at High level or Low level or leave open Xi j MKY02 1 Baud rate setting 1 AX2 RST 1 2 RST DIP SW etc O O 35 3 3 V 104 e GNO Voltage detection IC etc Low level at reset 7 7 V Caution Fig 4 7 Connection of Cascade Clocks In phase clocks must be supplied to AXI and AX2 pins of all MKYO02s to be cascade connected Therefore when connecting cascade clocks equalize the circuit pat tern length of three clock lines The circuit pattern length must
52. ion port port 0 Function of first Satellite side connection ports highest priority 02 1 2 3 4 5 6 7 em om om 8 9 10 11 12 13 14 Function of second em om o cascade connected MKY02 15 16 17 18 19 20 21 Function of third em om omm oum cascade connected 02 Port connector Port receive monitor green Packet error monitor red as representative of row port which one MKYO2 serves M Fig 4 9 Monitor Placement Example for Port added HUB StepTechnica recommends monitor LEDs be placed as follows 1 Place the port receive monitor LED beside each port connector Fig 4 9 For details of the port receive monitor refer to 3 4 3 Port Receive Monitor 2 Place the packet error monitor LED as a representative of the port which one MKY02 serves by the number of 2 to be used Fig 4 9 For details of the packet error monitor refer to 3 4 2 Packet Error Monitor The user who designs a HUB needs to determine the placement of monitor LEDs Reference i The packet receive monitor described in 3 4 1 Packet Receive Monitor and the packet error monitor described in 3 4 2 Packet Error Monitor function only when they receive packets from the input pins RXDO to RXD7 of each port These monitors do not function for packets passing through the priority cascade connection signals and reverse priority cascade connection signals describe
53. llows refer to Fig 4 3 and Fig 4 4 1 Fix the cascade pins CIx1 CIE1 CID1 and CIHR of the highest priority 02 at Low 2 Connect the cascade pins COx1 COEI CODI and COHR of the 02 to the cascade pins CIx1 and CIHR of the 2 with next priority 3 Leave the cascade pins COx1 COEI CODI COPI and COHR of the 2 with the lowest ority open 4 Fix the cascade pins CIx2 CIE2 CID2 CIP2 of the 2 with the lowest priority at Low 5 Connect the cascade pins COx2 2 COD2 COP2 of the MKYO02 to the cascade pins CIx2 CIE2 CID2 CIP2 of the 02 with next reverse priority 6 Leave the cascade pins COx2 COE2 COD2 COP2 of the 2 with highest priority open Figure 4 2 shows that of the three 025 the MKYO2 on the upper side is given the highest priority If multiple MKY 02s are cascade connected ports are assigned priorities in descending order Therefore num ber the satellite side ports according to priority Fig 4 2 For a center side port use port 0 of the MK Y02 with highest priority and do not use port 0 of other 02 Fig 4 2 Priority High Low MKY02 1 MKY02 2 MKY02 3 25 56 25 56 COE2 COE2 COE2 CIE1 1 CIET 1 CIE1 1 COD2 CID2 COD2 CID2 22 COD2 2 CID1 COD1 22 88 CID1 COD1 22298 CID1 001 2 28
54. n The LEDRZE pin may cause the LED to go on the following cases If the cable con ED gre cap nected to the HUB is near its length limit if impedance mismatch occurs in network cables if there is interference including external noise to external the system Or if an error occurs in terminals or the center equipment StepTechnica recommends the user put the LED where the user can check the LED indicator on the HUB easily TEP Chapter 3 Single Connection of 02 S TECHNICA CO LTD 3 4 3 Port Receive Monitor The 2 has three output pins RLDT RLLD that can be used to add more port receive moni tors corresponding to individual ports The RLDT pin pin 29 RLCK pin pin 30 and RLLD pin pin 31 operate as follows 1 If a hardware reset is activated all of the pins output a Low level 2 If a hardware reset is not activated all ofthe pins output the signals shown in Figure 3 12 using a time of 217 x TAXI as one unit The 02 stores the status of the port that has received a packet for a time of 2 7 x TAXI The MKY02 outputs the stored status to the RLDT pin as the signal format shown in Figure 3 12 for a next time of 21 x TAXI 7 Passage of time gt 12 Mbps 10 92 ms 6 Mbps 21 85 ms Monitor status updating interval 217 x Tax1 rat 4 12 Mbps 2 73 ms 15 6 Mbps 5 46 ms 2 xTAaxt 3 Mbps 10 92 ms r Data for LED output RLLD
55. nter equipment Center IC Rt HUB Port 0 Port 0 Do not connect a termination resistor 123 45 6 7 Ports 1 to 7 Connect a termination resistor Rt re REV REX RE REN Rt Multi drop network of terminals Rt Satellite Satellite IC Satellite Satellite Satellite IC Satellite IC Terminal Terminal Terminal Terminal Terminal Terminal gt Multi drop network of terminals c Terminal Satellite IC HUB Port 0 Port 0 Do not connect a termination resistor 123 4 5 6 7 Ports 1 to 7 Connect a termination resistor Rt re REA REX RE REN Rt Multi drop network of terminals Rt Satellite Satellite Satellite Satellite Satellite Satellite Terminal Terminal Terminal Terminal Satellite IC Multi drop network of terminals Terminal Fig 1 8 HUB in Intermediate Position of Multi drop Network 1 11 TEP S TECHNICA Co LTD MKY02 User s Manual for Hi speed Link System 1 6 Port Addition to HUB By cascading MKY 02s the user can add more ports to HUB composed of the MK Y02 For example a cascade connection of three MK Y02s enables the HUB to have port 0 connecting the center side and 21 ports 7 ports x 3 connecting the satellite side Fig 1 9 7 to which more ports are added by cascading three 025 EH Center side connection port port 0 Satellite side connection ports Function of first 02 123456 7 EH EE
56. nto the MK Y02 pins Fig 3 1 Because the High level voltages does not meet the 5 0 V CMOS input specifications the MKY 02 out put pins cannot be connected to the CMOS input pins of peripheral logic circuits driven by the 5 0 V power supply This pins cannot be connected even if a pull up resistor is used between the 5 0 V 3 power supplies Fig 3 1 5 0 V 50 Type C D 5 0 V TTL Input 3 3 V 5 0V 5 0 V Output Type B Pull up 5 0 V TTL Input output 5 0 V ay 5 0 V CMOS Input High output Fig 3 1 Connection Causing Leakage Current Caution 1 When signal connecting to LSIs with different power supply voltages be sure to check the input output electric specifications for the LSIs to connect Also a voltage must not stay supplied to signal pins when the MK Y02 is power off 2 In the MK Y02 if an external pull up resistor is connected between non pull up input pin and the 5 0 V power supply the voltage level rises up to 5 0 V Depending on the circuit conditions on the board with the MK Y02 several tens of us to several ms may be required for the voltage level to rise Step Technica recommends pull up resistors of 3 to 30 be connected 3 A pull up resistor can be connected between the MKY02 output pins and the 5 0 V power supply In this case the High level output 15 increased up to 3 3 V but not to 5 0 V Fig 3 1 TEP Chapter 3
57. on shown in Figure 1 1 TEP S TECHNICA Co LTD 02 User s Manual for Hi speed Link System 1 3 HLS Configuration using HUBs Adding HUBs to the HLS network the user system can satisfy it s own needs 1 to 4 described above Caution When adding a HUB to the network the center IC constituting the HLS must be compati ble with the HUB If incompatible the center IC does not link correctly with satellite ICs 1 3 1 Extending Total Length of Network Cable Adding HUB s to the HLS network the user can extend the total length of the network cable Figure 1 2 shows an example of extending the total length of the network cable Rt in the figure indicates a termination resistor Adding a single HUB makes the total extension two times longer than recommended 12 Mbps 200 m 6 Mbps 400 m 3 Mbps 600 Center gt equipment HUB Rt Satellite Center IC Rt Satellite IC Satellite IC Satellite IC Terminal Terminal Terminal Terminal Adding two HUBs makes the total extension three times longer than recommended 12 Mbps 300 m 6 Mbps 600 m 3 Mbps 900 m gt Center equipment HUB HUB Rt Rt Rt Rt Rt Center IC HUB IC HUB IC Rt Satellite IC Satellite IC Satellite IC Satellite IC Satellite IC Satellite IC Terminal Terminal Terminal Terminal Terminal Terminal Fig 1 2 Extension
58. r 10 or more clocks of the clock to be input to the pin immedi ately after power on or when resetting hardware intentionally Cascade clock output pin Reeling For details refer to 3 2 2 Setting Cascade Clock and Baud Rate Cascade clock input pin Positive For details refer to 3 2 2 Setting Cascade Clock and Baud Rate Cascade clock input pin GSC For details refer to 3 2 2 Setting Cascade Clock and Baud Rate Cascade clock output pin Poste For details refer to 3 2 2 Setting Cascade Clock and Baud Rate Cascade clock output pin Eositve For details refer to 3 2 2 Setting Cascade Clock and Baud Rate Continue Chapter 2 MKY02 Hardware TEP S TECHNICA Co LTD Positive Table 2 1 Pin Functions of MKY02 Continued Cascade clock input pin For details refer to 3 2 2 Setting Cascade Clock and Baud Rate LEDRCV Negative The LED driving output pin that keeps Low for a given time when an HLS packet is received from any port This pin also keeps Low when a hardware reset is activated Leave this pin open when it is not used LEDRZE 43 44 45 46 Negative The LED driving output pin that keeps Low for a given time when an error HLS packet is received from any port This pin also keeps Low when a hardware reset is activated Leave this pin open when it is not used Be sure to connect this pin to GND pin manufacturer test pin 47
59. r s Manual for Hi speed Link System Chapter 4 Cascade Connection of MKY02 4 1 Concepts of Port Additlon eene nnn 4 3 4 1 1 Port Addition by Stacking 4 3 4 1 2 Port Addition by Cascade Connection eeeeeeeenen enn 4 4 4 1 3 Maximum Available Cascade 400 42 4 4 4 2 Practical Side of Cascade 44 4 11 4 5 4 2 1 Cascade Pi iii 4 5 4 2 2 Operation of Cascade Connection 4 6 4 23 Connection of Cascade Clocks and Determination of Baud Rate 4 7 4 2 4 Connection of Hardware Reset Signal eene een 4 7 4 2 5 Selecting Communication Mode eee nnne nnns 4 8 4 2 6 Connection of Each Port iier Estee eter Bree e CORR Deni 4 8 4 2 7 Placement of Monitor nennen nnn nn tnnt nne nennen ns 4 9 4 3 Example Circuit for Port added HUB by Cascade Connection 4 10 Chapter 5 Ratings 5 1 Electrical Ratings ie 5 3 5 2 Characteristics msc dasani wenns 5 3 5 2 1 Clock and Reset Timing cccccesssseceeeseeceneeeeeseeeeeeeneeceeeeeeeseceneeeeeasseeeeenseeeeeneeneeesneneees 5 4
60. rameter Pre heat time 60 to 80 s Pre heat temperature 150 to 190 Temperature rise rate 1 to 4 C s Peak condition time 10 s max Peak condition temperature 255 Cooling rate to 1 5 5 Cooling rate to 0 5 C s High temperature area 220 C 60 s max Removal temperature lt 100 C Caution The recommended conditions apply to hot air reflow or infrared reflow Temperature indi cates resin surface temperature of the package B North America Distributor Trans Data Technologies Inc 340 Arthur Ave Roselle IL 60172 Telephone 630 440 4075 Facsimile 630 539 4475 e mail info steptechnica us http www steptechnica us Developed and manufactured by StepTechnica Co Ltd 757 3 Shimo fujisawa Iruma shi Saitama 358 0011 TEL 04 2964 8804 FAX 04 2964 7653 http www steptechnica com info steptechnica com HUB IC MKYO2 User s Manual for Hi speed Link System Document No STD HLS02 V1 5E Issued April 2009
61. rcuit for HUB with 22 4 10 Fig 4 11 Example of Connection in Full duplex Mode 4 13 Tables Table 1 1 Baud Rates and Recommended Total Extension Number Of Inserted ani 1 4 Table 2 1 Pin Functions of 02 44 4 nennen nennen 2 4 Table 2 2 Electrical Ratings of 02 00 84 00000000 2 6 Table 3 1 Output Frequencies of Cascade 3 6 Table 5 1 Absolute Maximum 65 4 4 00000 5 3 Table 5 2 Electrical RatingS secundada 5 3 Table 5 3 AC Characteristics Measurement Conditions 5 3 viii Chapter 1 Concepts for Using 02 This chapter describes the concepts for using the 02 in the Hi speed Link System HLS 1 1 Role oT MKYU2 once eta teer et ee et 1 3 1 2 Basic HLS Configuration 1 3 1 3 HLS Configuration using 2 1 4 1 4 Basic HUB 1 10 1 5 Multi drop Network of HUBs eene 1 11 1 6 Port Addition to 442 22 1 12 1 7 MKY02 Operation oou tect rc ecto ee ete ee ees iaa 1 13 1 8 Feature
62. reverse priority cascade connection pins COE2 COP2 COD2 CIE2 CIP2 CID2 Fig 4 6 At this time the transmit packet data that is of an NRZ signal format is output from the COD2 pin and its minimum pulse width is a time of 2 x TBPS High level status signals for packet transmission control are output from the COE2 and COP2 pins 3 The COE1 COPI CODI and COHR pins output a Low level in cases other than the above 1 4 The COE2 COP2 and COD2 pins output a Low level in cases other than the above 2 N VN CIE1 CIP1 COE2 CIE1 CIP1 COE2 CID1 CIHR COP2 cipi ciHR COP2 OD2 COD2 Port 1 Port 1 1100000 L js Priority cascade Reverse priority cascade Priority cascade Reverse priority cascade Port 1 Port 1 to Port 7 8 to Port 7 lt gt gt I Port 0 Example of port 3 of second 02 receiving packets Port 1 to Port 7 E E I 77 Port 1 Port 0 Port 0 to Port 7 COE1 COP1 COE1 COP1 2 CIE2 CIP2 CID2 COD1 COHR CIE2 CIP2 CID2 COD1 COHR V 22 Fig 4 5 Center Ports and Operation Fig 4 6 Satellite Ports and Operation during Receiving during Receiving Chapter 4 Cascade Connection of MKY02 TEP S TECHNICA Co LTD 4 2 3 Connection of Cascade Clocks and Determination of Baud Rate The 2 has a circuit which generates a cascade clock A cascade clock for a baud rate suitable for t
63. s an error packet When an LED that goes on at Low level is connected to this LEDRZE pin it indicates that any port of the 02 has received an error packet MKY02 This LEDRZE pin has a drive capability of 8 mA If the LED can go on even at 8 mA or less the connec 560 Approx 4 mA 3 3 y 45 ou LEDRZE p UY Red tion in Figure 3 11 is possible In this case the hard ware designer of a HUB needs to determine the values MKY02 of current limiting resistors according to the LED rat S Ing ZLEDRZE p 5 0V To test the LED the LEDRZE pin outputs a Low When a High level is output the pin goes to 3 3 V level for 500000 x TAXI while a hardware reset is This connection is impossible because leakage current flows activated and after the hardware reset is canceled Fig 3 11 Connection of Packet Error Monitor LED The Low pulse output from the ZLEDRZE pin is generated by a retriggerable one shot multivibrator with a minimum time of 500000 x TAX Xi 48 MHz 12 Mbps 43 69 ms 6 Mbps 87 38 ms 3 Mbps 174 76 ms Therefore if any of the eight ports receives an error packet again within a given time the Low pulse width becomes wide Even if 12 Mbps is selected as the baud rate of the MK Y02 the narrowest time of the Low pulse is about 43 69 ms and the user can find that the LED is lit The red LED to indicating an error should be connected to the LEDRZE pin When not used leave this pin ope
64. s of MKYUS roe ee 1 15 TEP Chapter 1 Concepts for Using 02 HUB S TECHNICA Co LTD Chapter 1 Concepts for Using MKY02 HUB This chapter describes the concepts for use of the MK Y02 HUB in the HLS 1 1 Role of MKY02 MKY02 is a kind of HUB IC that constitutes a HUB to be used in HLS network Be sure to read Hi speed Link System Introduction Guide and Center IC User s Manuals before using the MK Y02 and understanding this manual 1 2 Basic HLS Configuration Figure 1 1 shows the basic HLS configuration with one center IC and multiple satellite ICs connected on a multi drop network Rt in the figure indicates a termination resistor Recommended full cable extension Center 12 Mbps 100 m 6 Mbps 200 m 3 Mbps 300 m equipment gt o Multi drop network Center IC Rt Rt Satellite IC Satellite IC Satellite IC Satellite IC Terminal Terminal Terminal Terminal Connect a termination resistor Rt at both ends of the network cables Fig 1 1 Basic HLS Configuration Some user systems may need the following for the basic HLS configuration 1 To extend the total length of a network cable 2 To branch pieces of multi dropped network 3 To eliminate connection or disconnection of termination resistor to or from each device 4 To use transmission systems such as optical fiber cables There will be difficulty solving these needs using such basic HLS configurati
65. used by a user system requiring high real timeness In addition some types of center ICs used in the HLS into which a HUB is inserted have restrictions on the stacked count the number of available ports or the number of actually insertable HUBs may not meet the user system needs Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 10 Port 11 Port 12 Port 13 Port 14 Port 15 Port 16 Port 17 Port 18 Port 19 Fig 4 1 Addition of Three stacked Ports TEP S TECHNICA Co LTD MKYO02 User s Manual for Hi speed Link System 4 1 2 Port Addition by Cascade Connection The 02 has cascade connection pins to solve the problems caused by stacking If more than one MKYO2 is used the MK Y02s can be handled as if they were one HUB IC by connecting the cascade connection pins Fig 4 2 If multiple 25 are cascade connected the time lag from receiving to sending packets described in 1 7 1 Receiving and Sending Packets is consistent across any port and the 15 identical to the designed using one 02 V ClE1 cIP1 2 CID1 CIHR COP2 COD2 Port1 gt Port 1 Port 2 t 91 Port 2 Handled as one HUB IC with one Port 3 port of center side and 21 ports PS i P gt 7 ports x 3 of satellite side 3 Ol lt 02 E Port 4 Port 5 Port 5 Port 1 Port 6 COE1 COP1 COD1 COHR NEUES Qa Porte Port 2 Port
66. with eight ports port 0 of the center side and ports to 7 of the satellite side in half duplex mode In the example circuit 3 6 and 12 Mbps can be set by DIP Switch DIP SW and a receive monitor circuit has been added Representative monitor for all ports Receive Not necessary if port receive 33V Error d LEDRCV b44 monitor circuit added LEDRZE V7 Red Port 0 ADM1485 5 V SIG 5 3 62 4 63 SIG shield 6 Pulse E i 61 6 2 7 5600 Green 3 3V ADM1485 5 V Port 7 PLAN shield transformer 14 7 transformer 77 ADM1485 5 V Port 6 Port 1 ADM1485 5 V sic 1 6 Rt lt 11 SIG 2 shield 6 Pulse 2 transformer h 2 Port 2 ADM1485 5 V 96 4 SIG Li shield 6 Pulse 3 transformer Pulse 6 shield transformer 13 1 siG Rt 2 SIG 5 21 ADM1485 5 Port 5 12 910 bey SIG 45 Pulse shield transformer 20 AN Port 3 ADM1485 5 V ADM1485 5V Port 4 8 9 SIG 1 5 3 6 1 SIG Rt Rt sic 2 2 sic shield 6 Pulse B Pulse 6 shield transformer gt y transformer 462 56 29 SM 77 60 B 7 7 Port receive monitor circuit 20 ATIUM TEE TEIN SER SAGAS NE ASIE UR 3 regulator etc 3 3 V 54 a 58 PS 55 Du 59 4 do 104 16 19 16 V 100 uF 74273 3 etc D7 itd
67. y ports TEP Chapter 1 Concepts for Using MKY02 HUB S TECHNICA CO LTD 1 3 3 Eliminating Connection or Disconnection of Termination Resistor to or from Each Device In a network using the HLS termination resistors Rt cannot be connected to the terminal connected in the intermediate position the halfway position in the network cable of the multi drop network However a one to one connection between all terminals can eliminate connection or disconnection of termination resistor to or from each device and simplifies the complexity of system installation as shown in Figure 1 4 7 Center equipment HUB Rt Rt Terminal Center IC Port 0 Satellite IC c Terminal Satellite c Terminal o Terminal Satellite Terminal IC c Terminal Satellite HUB Rt Rt Terminal Satellite IC Rt Rt Terminal Satellite IC Rt Rt Terminal Satellite IC Rt Rt Terminal Satellite IC Rt Rt Terminal Satellite IC Rt Rt Terminal Satellite IC Rt Rt Terminal Satellite IC Fig 1 4 Eliminating Problems with Termination Resistors MKY02 User s Manual for Hi speed Link System TEP S TECHNICA Co LTD 1 3 4 Star Topology Mounting a HUB IC to the terminal containing the center IC of the HLS can offer a star topology Fig 1 5 Furthermore network cables in a star topology can also be multi drop connected

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