Mitsubishi Q00CPU Datasheet
Contents
1. SH NA 080039 Instructions Error Codes General Description Instruction Tables Configuration of Instructions How To QCPU Q Mode QnACPU Programming Read Instructions Sequence Instructions Basic Instructions Application anual Common Instructions Instructions Instructions For Data Link QCPU Instructions Redundant System purchase separa SH NA 080041 QCPU Q Mode QnACPU Programming General Description System Configuration Specifications SFC Program anual SFC Configuration SFC Program Processing Sequence SFC Program Execution purchase separate SH NA 080076 Q CPU Q Mode Programming Manual General Description System Configuration Specifications SFC Program MELSAP L Configuration SFC Program Processing Sequence SFC Program Execution purchase separate QCPU Q Mode QnACPU Programming SH NA 080040 anual PID Control Instructions General Description System Configuration for PID Control PID Control Specifications Functions of PID Control PID Control Procedure PID Control Instructions How To Read Explanations For Instructions Incomplete Derivative purchase separate PID Control Instructions and Program Examples Complete Derivative PID Control Instructions and Program Examples SH NA 080366 Programming Guide Book for Note Many of these manuals are available by free download from our website www meau com MELSEC Q Series CPUs Basic Model Sequence CPUs T2. speed timers is set by instruction Retentive Timer ST Low speed high speed timer timing increments are parameter set Low speed timer 1 to 1000ms 1ms increments default 100ms High speed timer 0 1 to 100ms 0 1ms increments default 10ms Counter C Normal counters Default 512 points C0 to 511 Interrupt counters Max 128 Default 0 points parameter setting Data Register D Default 11136 points D0 to 11135 Link Register W Default 2048 points WO to 7FF Annunciator F Default 1024 points F0 to 1023 Edge Relay V fault 1024 points VO to 1023 File Register Special Link Relay SB 1024 points SBO to 3FF Special Link Register SW 1024 points SWO to 3FF Step Relay 4 2048 points SWO to 3FF Index Register Z 10 points Z0 to 9 Pointer P 300 points P0 to 299 128 points 10 to 127 In parameters set the cyclic intervals of the system interrupt pointers 128 to 131 2 to 1000ms 1ms increments Special Relay SM 1024 points SMO to 1023 Special Register SD 1024 points SD0 to 1023 Function Input FX 16 points FXO to F Function Output FY 16 points FY 0 to F Function Register FD 5 points FDO to 4 Device for direct access to link device Dedicated Specified format J Device for direct access to buffer memory of intelligent function module Specified format UID G LO to 2047 default Latch range setting can be made for B F V T ST C W and D Remote RUN PAUSE Contact 1 point can be set for
3. The MELSEC Q Series Automation Platform Q Series PACs are multi disciplinary automation platforms addressing the needs of both OEMs and end users The Q Series is the original multi CPU system with up to 4 CPUs to divide and conquer larger applications It provides scalable automation solutions to both small and very large systems offering a broad spectrum of automation capabilities Additional CPUs and intelligent function module expansions allow the Q series to handle sophisti cated motion process control PC and C language based control MES IT interfacing and numerous types of communication and networking Key Features m CPU types ranging from small medium systems to complex networked systems with tens of thousands of I O m Reduced lifecycle costs via remote system management amp maintenance m Redundant CPU capability available for hot backup of critical systems m Multiple CPU capability up to 4 CPUs adding open ended system per formance and flexibility Required Manuals Model Number Description Contents m Multiple programs allowing concurrent development code reuse better program organization and faster troubleshooting for less downtime m Multiple simultaneous access to the system allowing for faster system debugging and maintenance m Networking amp communication options distribute Q Series systems over wide areas while reducing wiring costs m Sequence CPUs can also address process applications by means of built
4. e Processing Speed LD X0 200ns T60ns Sequence Instruct MOV MOV DO D1 700ns 560ns Total Number of Instructions 249 excluding intelligent function module dedicated instructions Hardware Format CPU only CPU only Relay symbol type ladder logic symbolic language list Constant Scan ms Program Start at Given Time Intervals 1 to 2000ms can be specified in 1ms increments Program Capacity 1 8k steps 32 kbyte 8k steps 32 kbyte 14k steps 56 kbyte Program Memory Drive 0 58 kbyte 94 kbyte Memory Capacity Standard RAM Drive 3 0 128 kbyte Standard ROM Drive 4 58 kbyte 94 kbyte Program Memory Number of Stored Programs Standard ROM Number of Stored File Registers SEIEEENAE Number of I O Device Points 2048 points X Y0 to 7FF 2 Number of I O Points 256 points X Y0 to FF 1024 points X Y 0 to 3FF 3 Internal Relay M Default 8192 points MO to 8191 Latch Relay L 2048 points LO to 2047 Link Relay B 2048 points BO to 7FF Default 512 points T0 to 511 used as low speed or high speed timer Switching between low speed and high speed timers is set by instruction Timer T Low speed high speed timer timing increments are parameter se Low speed timer 1 to 1000ms 1ms increments default 100ms High speed timer 0 1 to 100ms 0 1ms increments default 10ms D ti ti p Switching between low speed and high
5. each RUN and PAUSE contacts from X0 7FF Year month day hour minute second day of week Automatic leap year judgment Clock Function Accuracy 3 2 to 5 27 TYP 1 98 s day at 0 C Accuracy 2 57 to 5 27 TYP 2 22 s day at 25 C Accuracy 11 68 to 3 65 TYP 2 64 s day at 55 C 32768 points RO to 32767 65536 points ZRO to 65535 Interrupt Pointer I Link Direct Device Intelligent Function Module Direct Device Latch Power Failure Comp Range Permissible Instantaneous Power Failure Time 20ms Depends on power supply module 5VDC Internal Current Consumption A 0 25 Weight kg 0 13 F 7 245 9 65 x 98 3 86 x 328 12 92 x 98 3 86 x Dimensions W x H x D mn in 98 3 86 98 3 86 27 4 1 08 x 98 3 86 x 89 3 3 52 Notes 1 Maximum actual program size is program capacity 34 steps 2 Sum of the number of I O points on the main extension base directly controlled by the CPU module and the number of I O points controlled as remote I O by the remote I O network 3 Number of 1 0 points on the main extension base directly controlled by the CPU module 4 The Step relay is a device for the SFC function only applicable to version B CPUs or higher 5 Q00 CPU S8 has the same functionalities as Q00 CPU E http store iiic cc
6. hese CPUs offer an economical entry level version of the Q Series for small scale systems Key Features m Multiple CPU support use up to three CPUs to combine sequence process motion amp PC control on a single system Version B or later Compatible with Q Series Intelligent Function Utility configuration tools m Offers full range of Q Series network amp communication features including CC Link IE LOOMbit Ethernet MELSECNET H m Integrated PSU CPU and base unit available to simplify system construction with Q00J CPUs Mitsubishi Electric Automatiani Pyogrammable Automation Controller PAC 17 Structured Text ST Covers Structured Text programming method purchase separate a je cz m Built in serial communications via CPU port using MELSEC Communication MC protocol m Security functions m Flash memory for programs amp parameters m Supports floating point function block PID and SFC programming Version B or later E PROGRAMMABLE AUTOMATION CONTROLLER PAC MELSEC Q Series Basic Sequence CPU Model Number QO0JCPU E QOOJCPU S8 5 QOOCPU Q01CPU Stocked Item S S 5 S Certification UL cUL CE UL cUL CE UL cUL CE UL cUL CE Combined CPU PSU and Combined CPU PSU and 5 Slot Base Unit 8 slot Base Unit Control Method Repeated operation using stored program 1 0 Control Method Refresh mode Programming Language Sequence Control Dedicated Languag
7. in PID capabilities m Extremely compact package saves panel costs m Certified by UL cUL CE as indicated as well as DNV ABS RINA BV LR and NK shipping approvals for all Q Series products Included with CPU Stk Item IB NA 0800061 QCPU Q mode CPU Module User s Manual General specs CE compliance information Installation safety requirements No Hardware Power supply wiring overview of system parts included with base uni SH NA 080483ENG Q CPU Q Mode User s Manual Hardware CPU HW specs PSU spec Base Unit specs CE compliance information Design Maintenance amp Inspection Maintenance amp inspection Installation Troubleshooting No purchase separa SH NA 080484ENG SH NA 080485ENG CPU specifications system configuration programming basics I O assignments mem QCPU Q Mode User s Manual Function ory organization CPU functions communication with intelligent function modules Explanation Program Fundamentals parameters amp devices program up downloads overview of multiple program architec ture programming basics overview of multiple CPU system Outline system configuration concept for multiple CPU system communication QCPU User s Manual Multiple CPU between CPU modules processing time of QCPU in multiple CPU system param System eter added for multiple CPU system precautions for use of AnS Series module starting up the multiple CPU system purchase separa purchase separa
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