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A High-Resolution, Multi-Hit, VME64x Time-to

1. A 512x8 serial EEPROM stores the sequence RAM and other user data The EEPROM is accessed through an EEPROM controller and an SPI compatible interface The controller provides a random access read write interface to the EEPROM It manages device opcodes status and data The SPI interface contains a clock manager and a serializer deserializer Since the Sequence RAM and end address occupy only 385 bytes of the 512 byte EEPROM the remaining space is available for user data The Master Controller module provides a host interface to the control logic and interconnects the register file sequencer and EEPROM modules It permits read and write access to the Register File RAM Sequence RAM and EEPROM The host can trigger TDC configuration from Sequence RAM and transfer of Sequence RAM to or from the EEPROM At power up the Sequence RAM and end address are automatically loaded from EEPROM then passed to the register file and serializer to configure the TDCs This automatic power up configuration removes considerable software overhead for a large number of TDC boards A description of all the configuration registers can be found in Appendix A Sample values of the registers under various operating conditions are found in Appendix B 10 4 1 Connections Front Panel 4 1 1 Input Connectors Time measurements are performed on differential ECL signals connected to the top and bottom stacked headers Each header has 17 pairs of pins with the true
2. adjust_k10 3 adjust_k10 2 adjust_k10 1 adjust_k9 0 adjust_k9 5 adjust_k9 4 adjust_k9 3 adjust_k9 2 adjust_k9 1 adjust_k9 0 Name beinit refstart counter 8 refstart counter 7 refstart counter 6 refstart counter 5 refstart counter 4 refstart counter 3 refstart counter 2 refstart counter 1 refstart counter 0 hit time 5 hit time 4 hit time 3 hit time 2 hit time 1 hit time O Description Bus clock delay bit 3 Bus clock delay bit 2 Bus clock delay bit 1 Bus clock delay bit 0 Channel adjust high resolution reference channel B bit 5 Channel adjust high resolution reference channel B bit 4 Channel adjust high resolution reference channel B bit 3 Channel adjust high resolution reference channel B bit 2 Channel adjust high resolution reference channel B bit 1 Channel adjust high resolution reference channel B bit 0 Channel adjust high resolution reference channel A bit 5 Channel adjust high resolution reference channel A bit 4 Channel adjust high resolution reference channel A bit 3 Channel adjust high resolution reference channel A bit 2 Channel adjust high resolution reference channel A bit 1 Channel adjust high resolution reference channel A bit 0 Description Flag to F1 indicates that initialisation is finished O not initialised I completely initialised Sets measurement range in synchronous mode bit 8 Sets measurement range in synchronous mode bit 7 Sets measurement range in synchronous
3. on the side of the orientation key left side and the complement on the right side as illustrated in figure 5 and differentially terminated into 110 Ohm impedance The ie pair is not used or connected in any manner Only the rightmost headers on each of the top and bottom stacks are used during high resolution measurements Please notice the orientation of the socket and cable when making connections to the module F1TDC High or Low Resolution ECL Signal Inputs Odd Numbered Channels 2 1 Channels 1 to 31 Notice Socket Key Orientation KN Sockets NUAN Headers Low Resolution Only ECL Signal Inputs Eyen Numbered Channels Channels 2 to 32 ECL ECL HIGH RESOLUTION TT E J TN Signal Cables 17 pair Twisted ECL LVPECL Timing amp Control Signals High or Low Resolution ECL Signal Inputs Odd Numbered Channels Channels 33 to 63 Low Resolution Only ECL Signal Inputs Even Numbered Channels Channels 34 to 64 ECL ECL HIGH RESOLUTION JLAB Figure 5 Front Panel Connections 11 4 1 2 Timing amp Control Connector Timing and control signals are supplied through either the front panel or backplane Front panel connections are appropriate for small data acquisition systems and require the us
4. 6 bit 2 Channel adjust high resolution channel 6 bit 1 Channel adjust high resolution channel 6 bit O enable falling edge channel 5 enable rising edge channel 5 Channel adjust high resolution channel 5 bit 5 Channel adjust high resolution channel 5 bit 4 Channel adjust high resolution channel 5 bit 3 Channel adjust high resolution channel 5 bit 2 Channel adjust high resolution channel 5 bit 1 Channel adjust high resolution channel 5 bit 0 Description enable falling edge channel 8 enable rising edge channel 8 Channel adjust high resolution channel 8 bit 5 Channel adjust high resolution channel 8 bit 4 Channel adjust high resolution channel 8 bit 3 Channel adjust high resolution channel 8 bit 2 Channel adjust high resolution channel 8 bit 1 Channel adjust high resolution channel 8 bit 0 enable falling edge channel 7 enable rising edge channel 7 Channel adjust high resolution channel 7 bit 5 Channel adjust high resolution channel 7 bit 4 Channel adjust high resolution channel 7 bit 3 Channel adjust high resolution channel 7 bit 2 Channel adjust high resolution channel 7 bit 1 Channel adjust high resolution channel 7 bit 0 28 Default ceococeoeoooooooooooo Default ceoeceoceeoooooooooooo Register 6 Address 6 Bit No 15 14 13 12 11 10 OrFNWHRANAANA CWO Register 7 Address 7 Bit No 15 OrFNwWwhkNOAN Name busclkdelay 3 busclkdelay 2 busclkdelay 1 busclkdelay 0 adjust_k10 5 adjust_k10 4
5. Time address address The header trailer words can be enabled for each channel of the chip In this case the output stream of data words for a trigger appears as follows header channel 0 data channel O earliest hit data channel O latest hit trailer channel 0 header channel 1 data channel 1 earliest hit data channel 1 latest hit trailer channel 1 header channel 7 data channel 7 earliest hit data channel 7 latest hit trailer channel 7 23 In this case the headers trailers take up space in the F1TDC chip s output buffer while providing redundant information A better solution is to enable only the header for channel O and the trailer for channel 7 The chip data stream then appears as follows header channel O data channel O earliest hit data channel O latest hit data channel 1 earliest hit data channel 1 latest hit data channel 7 earliest hit data channel 7 latest hit trailer channel 7 In our application of the FITDC chip we require that af least the header for channel O and the trailer for channel 7 be enabled for each chip that is to be read out The chips to be read out are specified by CTRL 23 16 This minimal header trailer information is used to assemble event fragments from different chips into a single event fragment that is associated with a given trigger for the board During readout the defaul
6. W Interrupt ID vector 10 8 R W Interrupt Level 2 0 Valid values 1 7 11 15 not used 20 16 R Geographic Address slot number in VME64x chassis 21 22 not used 23 R Parity Error in Geographic Address 24 31 not used 20 ADR32 Address for data access 0x14 0 R W Enable 32 bit address decoding 1 5 not used read as 0 15 6 R W Base Address for 32 bit addressing mode 4 Mbyte total ADR_MB Multiblock Address for data access 0x18 0 R W Enable Multiblock address decoding 1 5 not used read as 0 15 6 R W Lower Limit address ADR_MIN for Multiblock access 16 21 not used read as 0 31 22 R W Upper Limit address ADR MAX for Multiblock access The board that has the TOKEN will respond with data when the VME address satisfies the following condition ADR_MIN lt Address lt ADR MAX TDC STATUS 4 registers OxXX TDC chips B amp A Ox1C TDC chips 1 amp 0 0x20 TDC chips 3 amp 2 0x24 TDC chips 5 amp 4 0x28 TDC chips 7 amp 6 bits 0 15 for chip A bits 16 31 for chip B 0 Resolution LOCKED A 1 TDC Hit FIFO Overflow A 2 TDC Trigger FIFO Overflow A 3 TDC Output FIFO Overflow A 4 External FIFO Full A 21 5 External FIFO Almost Full BUSY as
7. following describes the setup and operation of the TDC in single and multiple module applications Single Module After a reset of the module CSR 31 1 the FI chip configuration registers may be written directly through the A24 address space 800 9FF The source for the control signals is set to Front CTRL 0 O and the internal clock is selected and turned on CTRL 2 0 CTRL 1 1 The EVENT LEVEL register is loaded with the number of events i e triggers that constitute a block The INTERRUPT register may be loaded with the interrupt ID and level if the module is to initiate an interrupt when the defined block of data is available for readout The address for data access is loaded ADR32 and the F1 chips that are to participate in the readout are selected CTRL 23 16 The event level interrupt CTRL 3 1 is enabled if interrupt generation is desired The BERR response is enabled CTRL 6 1 to allow the module to indicate when the complete block of data has been read out When the programmed number of triggers has been received the event level flag CSR 3 will be set and an interrupt will be generated if enabled The user should initiate a DMA block read 32 or 64 bit from the address in stored in ADR32 The length of the block read should be programmed to be larger than the expected size of the data block e g 4 Mbytes The module will terminate the DMA transfer by issuing BERR when all data from the block has be
8. i transfered to OUTPUT FIFO ald hits will be erased from HIT FIFO Figure 3 Trigger Matching 3 2 Module Architecture The eight F1 TDC chips on our module provide 64 channels in normal mode or 32 channels in high resolution mode Front panel input signal levels are differential ECL to be compatible with existing systems Timing control signals are provided on the front panel and are also available through backplane connections for ease of system integration A 128K word deep FIFO capable of simultaneous reads and writes is attached to each FI TDC chip to buffer its output data The VME interface and all control logic and registers are implemented in a single Field Programmable Gate Array FPGA All VME bus tranceivers are compatible with the high speed protocols of the VME64x standard The RAM shown in Figure 1 is an option not present on this version of the TDC Output data from the F1 TDC chip is ordered according to channel number channel O first channel 7 last Within each channel hit data is ordered from earliest to latest Each F1 TDC chip may be configured to supply a header word for channel O and a trailer word for channel 7 in its output data stream whenever a trigger occurs This takes place even if there is no valid hit data for the trigger During readout control logic uses these markers to switch between the FIFOs that supply the data In this way data from multiple chips that are associated with the same trigger may be as
9. mode bit 6 Sets measurement range in synchronous mode bit 5 Sets measurement range in synchronous mode bit 4 Sets measurement range in synchronous mode bit 3 Sets measurement range in synchronous mode bit 2 Sets measurement range in synchronous mode bit 1 Sets measurement range in synchronous mode bit 0 Sets time for hit sampling bit 5 Sets time for hit sampling bit 4 Sets time for hit sampling bit 3 Sets time for hit sampling bit 2 Sets time for hit sampling bit 1 Sets time for hit sampling bit 0 29 Default cecceoeoceooooooooooo Default ceoeceoeoeoooooooooo Register 8 Address 8 Bit No 15 14 13 12 11 10 OrFNWHRANAANA CWO Register 9 Address 9 Bit No 15 14 WANNA Name breite 15 breite 14 breite 13 breite 12 breite 11 breite 10 breite 9 breite 8 breite 7 breite 6 breite 5 breite 4 breite 3 breite 2 breite 1 breite 0 Name offset 15 offset 14 offset 13 offset 12 offset 11 offset 10 offset 9 offset 8 offset 7 offset 6 offset 5 offset 4 offset 3 offset 2 offset 1 offset O Description Trigger window width bit 15 Trigger window width bit 14 Trigger window width bit 13 Trigger window width bit 12 Trigger window width bit 11 Trigger window width bit 10 Trigger window width bit 9 Trigger window width bit 8 Trigger window width bit 7 Trigger window width bit 6 Trigger window width bit 5 Trigger window width bit 4 Trigger window
10. module is read or data is not yet ready to be extracted Slot ID 0 is the tag for a filler word This is a non valid data word that is inserted to make the block of data output from the module consist of an even number of words An even number of words simplifies 64 bit readout mode Data should be ignored if Slot ID 0 or 30 25 Appendix A F1 ASIC Configuration Registers and Addresses The F1 ASIC Chip contains sixteen 16 16 bit registers which can be programmed for specific applications and requirements and must be downloaded in a specific order The following tables provide detailed information on register functionality However note that some registers may not be available to the user of the FITDC module Register overview Addr D15 D14 O18 D12 D11 DIO D9 Da D D6 D5 D D3 D2 D1 DO O headen 2 fee free ch fet rei adchl ooo 3 fea fret sich fe re8 asdjch fe6 re6 Pach fe eS PE msdch 5 fe8 re8 adjch8 fe7 rez adje a a_i gt SS ee trite 10 doni pl track neg rad refclkdiv a a O ee bm 4 _ me _______________ 15 done htest stest jdiaG diae diat diaO rosta sync com 8 24 Adr Name Description Adr Name Description o headen Enable header output 4 beini initialize chip trailen Enable trailer output refent Set counter synchron Mode hitt strobe time for hit mode 1 hires set high resolution mode hitm set hit mode 8 tri
11. start stop and synchronous measurement modes In common start stop mode a Start signal resets the internal measurement counter and a Trigger signal sets the measurement window Hits falling within these two signals will always be accepted by the trigger matching unit In synchronous mode a Synch Reset signal is used to reset the internal measurement counter and thus synchronize all TDCs in an experiment Internal start signals are automatically generated at a programmable rate The trigger matching unit validates hits within the programmed window and latency Headers and trailers identifying the channel chip trigger time and event number can be output to delineate events The dynamic range is 7 8 uS at 120 pS LSB and 3 9 uS at 60 pS with a 40 MHz Reference Clock To ensure stability and measurement reliability each F1 chip is PLL regulated against temperature drifts and manufacturing tolerances The feedback loop employs a phase frequency detector a loop filter and a voltage regulator which drives the substrate or core of the F1 chip In this manner delays within the internal Delay Locked Loop DLL are kept constant which translates into a stable LSB resolution or bin size The F1 chip is configured via a serial interface port which accesses 16 registers Readout of data is via a 24 bit parallel port Further information on the Fl ASIC Chip can be obtained by contacting acam messelectronic gmbh at www acam de matching hits will be
12. width bit 3 Trigger window width bit 2 Trigger window width bit 1 Trigger window width bit 0 Description Trigger window offset bit 15 Trigger window offset bit 14 Trigger window offset bit 13 Trigger window offset bit 12 Trigger window offset bit 11 Trigger window offset bit 10 Trigger window offset bit 9 Trigger window offset bit 8 Trigger window offset bit 7 Trigger window offset bit 6 Trigger window offset bit 5 Trigger window offset bit 4 Trigger window offset bit 3 Trigger window offset bit 2 Trigger window offset bit 1 Trigger window offset bit 0 30 Default ceoceoeoeoooooooooooo Default ceocoeoceoooooooooooo Register 10 Address 10 Bit No 15 14 13 12 11 10 oc n Gh dd CWO Register 11 Address 11 Bit No 15 14 9 2 eb oc eo Name Description diagon1 Select diagnosis mode bit 1 testpll Diagnosis PLL track Cut the regulation loop of the PLL negphase Negotiation of the phase output PLL Res Adj Switch on resolution adjust mode Ref Clk Div 2 Ref Clk Div 1 Ref Clk Div 0 Reference clock divider bit 2 Reference clock divider bit 1 Reference clock divider bit 0 Highspeed Div 7 PLL divider bit 7 Highspeed Div 6 PLL divider bit 6 Highspeed Div 5 PLL divider bit 5 Highspeed Div 4 PLL divider bit 4 Highspeed Div 3 PLL divider bit 3 Highspeed Div 2 PLL divider bit 2 Highspeed Div 1 PLL divider bit 1 Highspeed Div 0 PLL divider bit 0 Name Description dac2 7 T
13. 03F A400 Register 8 15 31D2 66F6 1FBC 0000 0000 0000 0000 0008 rising edge refcnt 144 tframe 3650 ns 40 MHz clock refclkdiv 128 hsdiv 188 bin size 0 056 ns full range 3669 4 ns trigwin 12754 window 1428 2 ns triglat 26358 latency 2951 6 ns High Resolution Synchronous Mode Register 0 7 0180 8000 407F 407F 407F 407F 003F A400 Register 8 15 31D2 66F6 1FBC 0000 0000 0000 0000 000C rising edge refcnt 144 tframe 3650 ns 40 MHz clock refclkdiv 128 hsdiv 188 bin size 0 056 ns full range 3669 4 ns trigwin 12754 window 1428 2 ns triglat 26358 latency 2951 6 ns synchronous range 65189 bins 35
14. 13 R TDC chip 5 error 14 R TDC chip 6 error 15 R TDC chip 7 error 16 23 R Output Enable for external FIFO 0 7 24 27 not used 28 W Pulse Spare Out if CTRL 12 1 29 W Pulse Soft Trigger if CTRL 5 1 30 W Pulse Soft Reset 31 W Pulse Hard Reset CTRL Control 0x4 0 R W Front Back Control Signals select 0 Front 1 Back 1 R W Internal Clock Control 0 Clock OFF 1 Clock ON 2 R W Clock Select O Internal Gf CTRL O 0 1 External 3 R W Enable Event Level Interrupt 4 R W Enable Error Interrupt 5 R W Enable Soft Trigger 6 R W Enable BERR response 7 R W Enable Multiblock protocol 8 R W FIRST board in Multiblock system 19 9 R W LAST board in Multiblock system 10 R W Enable readout of all F1 chip headers trailers 11 R W Enable BUSY output to front panel 12 R W Enable Spare output 13 15 not used read as 0 16 23 R W Enable Readout from TDC 0 7 24 31 not used read as 1 EVENT COUNT 0x8 15 0 R Event Count 15 0 Event Count 0 CSR 4 1 31 16 not used EVENT LEVEL 0xC 15 0 R W Event Level 15 0 Event Count gt Event Level CSR 3 1 31 16 not used INTERRUPT 0x10 7 0 R
15. C7 bit 3 Transfer data to DAC7 bit 2 Transfer data to DAC7 bit 1 Transfer data to DAC7 bit 0 Description Select diagnosis mode bit 2 not used not used not used not used not used not used not used Diagnosis selector bit 3 Diagnosis selector bit 2 Diagnosis selector bit 1 Diagnosis selector bit 0 Start ring oscillator 0 off 1 on Select synchronous mode 0 off 1 on Select common mode Select bus width 0 24 Bit 1 8 Bit 33 Default ceoceoeoeoeooooooooooo Default ceocoeoceoooooooooooo 34 Appendix B Sample F1 ASIC Configuration Registers Values Normal Resolution Non synchronous Mode Register 0 7 0180 0000 4040 4040 4040 4040 003F C880 Register 8 15 63A4 CDEC 1FBC 0000 0000 0000 0000 0008 rising edge refcnt 290 tframe 7300 ns 40 MHz clock refclkdiv 128 hsdiv 188 bin size 0 112 ns full range 7338 9 ns trigwin 25508 window 2856 4 ns triglat 52716 latency 5903 2 ns Normal Resolution Synchronous Mode Register 0 7 0180 0000 4040 4040 4040 4040 003F C880 Register 8 15 63A4 CDEC 1FBC 0000 0000 0000 0000 000C rising edge refcnt 290 tframe 7300 ns 40 MHz clock refclkdiv 128 hsdiv 188 bin size 0 112 ns full range 7338 9 ns trigwin 25508 window 2856 4 ns triglat 52716 latency 5903 2 ns synchronous range 65189 bins High Resolution Non synchronous Mode Register 0 7 0180 8000 407F 407F 407F 407F 0
16. F1TDC A High Resolution Multi Hit VME64x Time to Digital Converter User s Manual V1 1 23 April 2004 U 5 Department of Energy s HOB THOMAS JEFFERSON NATIONAL ACCELERATOR FACILITY Table of Contents us RI RS AY N 2 Specifications O OO O WR 3 The FITDC Architecture _ onversneden 3 1 The F1 ASIC Chip zenne 3 2 Module Architecture aia YAR GU 3 3 Configuring the FITDC 4 Connections 4 1 Front Panel De Dd Dd Gn 4 1 1 Input Connectors annemarie 4 1 2 Timing amp Control Connector _ 4 2 Backplane smeten 5 Using the Module 5 1 Controlling the Module gadsaccsscacciandass 5 2 Module Operation sussen 5 3 Module Registers ceisid Ui UG DD iw 5 4 Data ay ME AO OU O FF EF RNA Appendices A F1 ASIC Configuration Registers and Addresses B Sample F1 ASIC Configuration Register Values C F1 TDC Configuration Control Manual __ ry ry or eeseeese a ry ee eee eee cece 25 34 35 1 Introduction FITDC A VME64x High Resolution Multi Hit Time to Digital Converter Multi Hit Differential ECL Inputs High Resolution up to 60 pS LSB Wide Dynamic Range up to 7 8 uS High Stability by PLL Feedback Loop Data Validation by Trigger Matching with Zero Suppression Programmable Trigger Window and Latency Data Storage up to 1 Million Hits Flexible Control Inputs Via Front Panel or Backplane VME64x Compliant with 2eVME Data Transfer Cycles The F1TDC is
17. RT_B_IN UD 29 UD UD DV30 REFCLK_B_IN UD 30 AGND AGND DV31 REFCLK_B_IN UD 31 AGND REFCLK_B_OUT AGND SYNCRES_B_ IN AGND 32 AGND REFCLK_B_OUT 5IN SYNCRES_B_IN VPC 14 15 5__ Using the Module 5 1 Controlling the Module Communication with the module is by standard VME bus protocols All registers and memory locations are defined to be 4 byte entities The VME slave module has three distinct address ranges A24 The base address of this range is set by a 12 element DIP switch on the board It occupies 4 Kbytes of VME address space organized in 1 K 32 bit words Relative to the base address this space is divided as follows 000 7FF Register space to control and monitor the module 800 FFF F1 chip configuration space Detailed information about the F1 chip configuration space is found in Appendix C To summarize the F1 chip configuration space is divided as follows 800 9FF Configuration register file The 4 byte registers are ordered as Chip 0 register O 1 2 15 Chip 1 register 0 1 2 15 Chip 7 register 0 1 2 15 Direct writes to an F1 chip register may be made to the address Address 800 40 chip 4 register ff The order in which the registers are written should be the following register 15 10 0 1 2 3 4 5 6 8 9 11 12 13 14 7 Sample values of the F1 chip registers under several operating conditions are found in Appendix B A00 BFF Set
18. a Common Address Range used exclusively for multiblock transfers Only the TDC having the token will actually respond to such an address cycle The TDC module of the set that is furthest left in the crate is configured to be the first module and initially claims the token The module furthest to the right is set as the last module All modules except the last one are configured to pass the token when they have transferred the programmed number of events The last module is instead configured to respond with BERR In addition the first module may be configured to initiate readout by interrupting the crate controller when the data from a programmed number of triggers is available in its buffers A slave terminated block transfer using the Common Address Range will accomplish the readout of the data from the programmed number of triggers for all boards of the set When BERR occurs signaling the completion of this transfer the first module seizes the token again 3 3__ Configuring the FITDC The TDC module contains eight F1 TDC devices that must be configured prior to operation Each device contains sixteen 16 bit write only configuration registers that are accessed through a synchronous serial bus The TDC configuration control logic is implemented in the FPGA It contains a serializer for the TDCs a register file RAM a configuration sequence RAM an EEPROM controller and host interface logic An overview of the configuration control logic architecture
19. a high resolution Time to Digital Converter TDC This module is particularly suited for applications requiring high resolution time measurements with multi hit capability at high event rates and where high channel densities are desirable Wide dynamic range combined with trigger matching zero suppression and deep storage alleviates the need for further data manipulation and reduces intermediate data storage requirements A standard VME64x data acquisition bus guarantees the user will have high data throughput combined with long term industry support 2 Specifications Packaging Tnputs Control Clock Dynamic Range Standard Deviation INL DNL Acguisition FIFO Interface Power 6U VME64x Differential ECL 110 Ohm 64 Channels 120 pS LSB 32 Channels 60 pS LSB START SYNCRES TRIGGER Front Panel Differential ECL 110 Ohm Backplane Differential LVPECL 110 Ohm Differential LVPECL 110 Ohm 40 MHz Internal Front Panel Backplane 7 8 uS for 120 pS LSB 3 9 uS for 60 pS LSB Less than 0 9 LSB 0 LSB 10 50 LSB Trigger Matching w Zero suppression Programmable Trigger Window and Latency 1 M TDC Data Words 32 bit VME Block Transfers gt 20 Mbyte s 64 bit VME Block Transfers gt 40 Mbyte s 12V G 0 5A 12V G 04A 43 3V 9 73A 5V 1 8A 3 The F1TDC Architecture The block diagram for the FITDC module is shown in figure 1 The front end section of the FITDC encompasses the
20. a output Register 0 Address 0 Bit No 15 14 13 12 11 10 OrFNWHRANAANA CWO Register 1 Address 1 Bit No 15 14 WANNA Name head en 8 head en 7 head en 6 head en 5 head en 4 head en 3 head en 2 head en 1 trail en 8 trail en 7 trail en 6 trail en 5 trail en 4 trail en 3 trail en 2 trail en 1 Name highres hitmode letramode sq 1 sq 0 fakehalf ovlaphigh ibspeed 1 ibspeed 0 obspeed m_inh slow 3 slow 2 slow 1 slow 0 DACstart Description Header Enable Kanal8 Header Enable Kanal7 Header Enable Kanal6 Header Enable Kanal5 Header Enable Kanal4 Header Enable Kanal3 Header Enable Kanal2 Header Enable Kanal 1 Trailer Enable Kanal8 Trailer Enable Kanal7 Trailer Enable Kanal6 Trailer Enable Kanal5 Trailer Enable Kanal4 Trailer Enable Kanal3 Trailer Enable Kanal2 Trailer Enable Kanall Description O noral resolution 1 high resolution 32 channel hit mode Leading trailing edge mode Measurement core adjust bit 1 Measurement core adjust bit 0 Not relevant for common mode Not relevant for common mode Processing speed Trigger Bit1 Processing speed Trigger BitO Transfer rate output FIFO to interface FIFO Software disable for all stop inputs 0 on 1 off Measurement result processing speed Bit3 Measurement result processing speed Bit2 Measurement result processing speed Bit1 Measurement result processing speed Bit0 Start flag for data transfer to 8 f
21. annels at 60 pS LSB when a reference clock of 40 MHz is used Internal FIFOs allow for storage of 16 hits per channel in leading and or trailing edge modes The following outline pertains to the use of the F1 chip in our TDC module A key feature of the F1 chip is a Trigger Matching processing unit which allows for selection of hits within a programmable time window and latency from the occurrence of a valid trigger input Hits that fall outside of the window and latency settings are suppressed from the output buffer and cleared from the hit FIFO Figure 3 depicts the operation of the trigger matching function Reference clock ie reference start reset counter Start Input start 1 gt reset time to 0 b Synch Reset b Trigger actual time mre Trigger time stopn 1 9 gg disable 1 CH 1 time stamps CH 8 disablen 1 4 11 l4 6 x 16 16 3 E16 16 Trigger 4 Trigger hit 1 3 HIT FIFOS EHITFIFOS FIFO counte hitn 1 3 9 i t f hit 1 4 hitn 1 4 o Ar tees o Trigger iii matching di unit k 8 17 e e o o 8 17 4 ouTPuT J headers E OUTPUT rf 7 FIFO time FIFO headers Channel 8 stamps i cat ed i dn ol Soe ae Setup Registers 16 24 INTERFACEFIFO E 16 16 4 Parallel 1 0 INTERFACE DAC Interface 24 bit or 8 bit Serial Interface Figure 2 The F1 ASIC Chip The trigger matching feature is used in common
22. distribution Note that all reference clock paths are differential and all the external LVPECL inputs are capacitively coupled for safety reasons Systems employing PECL signals with receivers and sources powered from separate power supplies should have all inputs capacitively coupled as damage to receivers may occur when input signals forward bias the input ESD structures and the input base collector junction of un powered receivers Internal REF CLK Enable 4 MHz Clock 108 ppm Internal or External Front Panel External Bacplane REF_ CLK Select Internal External Front Panel Front Panel REF_ CLK Select REF_ CLK Output LVPECL 1 to 8 Buffer To F1 ASIC Chips External Front Panel REF_ CLK Input LVPECL External Backplane REF_ CLK Input prey gt Backplane REF_ CLK Output LVPECL Figure 7 Reference Clock Distribution Once the internal REF CLK is enabled its output is always available at the front panel and the backplane In systems with multiple modules and where clock synchronization is required a single module can be configured as the REF_CLK master clock The use of an external LVPECL clock distribution module will then be required Figure 8 illustrates possible implementations for small and large scale systems Master REF CLK F1TDC VME64x Modules Source 1 to N LVPECL REF_ CLK Buffer VME64x Backplane VME64x Sub Rack F
23. en transferred Interrupt generation must be re enabled by writing 0x80000000 to the address in ADR32 Multiple Modules All modules should be reset and loaded with the configuration register values as described above for a single module The source of the control signals for the modules is set to Front or Back depending on the distribution system used The internal clocks need not be turned on as a clock source is provided as part of the distribution system The EVENT LEVEL register and the chips selected for readout are loaded into each module A unique address for data access is loaded into ADR32 for each 17 module The common address range for the Multiblock protocol is loaded into ADR_MB for each module All modules are programmed to participate in the Multiblock protocol CTRL 7 1 The left most TDC module in the system is programmed as the first module CTRL 8 1 and the right most TDC module is designated the last module CTRL 9 1 For the first module the INTERRUPT register may be loaded and the event level interrupt bit enabled if desired The BERR response is enabled for the last module only For backplane mounted signal distribution systems the token passing lines are included in the system Front signal distribution systems need additional connections to the backplane for token passing lines see Table 2 When the programmed number of triggers has been received the event level flag will be set in each module and an i
24. er to provide connections to a 14 pin header by individual pair sockets or 14 pin socket with twisted pair cable figure 6 All inputs are differential and terminated into 110 Ohm impedance CLKO CLKI STRT SYNC TRIG LVPECL ECL BUSY Figure 6 Timing amp Control Signals CLK0 Reference Clock Output Differential LVPECL 40 MHz CLKI Reference Clock Input Differential LVPECL Capacitively Coupled STRT Start Differential ECL Input Resets the Internal Measurement Counter on all F1 ASIC Chips in Common Start Stop Mode The Signal Inputs Function as Stops SYNC Synch Reset Differential ECL Input Resets the Internal Measurement Counter on all F1 ASIC Chips in Synchronous Mode TRIG Trigger Differential ECL Input Sets the Measurement Validation Window The Trigger Window and Latency are Programmable During Configuration BUSY Busy Differential ECL Output Data FIFO Memory Almost Full Condition Triggers should be stopped to avoid loss of data 12 The user has the option of selecting the reference clock source through the VME interface The internal reference clock source has a freguency stability of 100 ppm As the timing resolution of the Fl ASIC Chips depends on the stability of the reference clock the user should exercise caution when selecting and implementing external reference sources Figure 7 shows a simplified diagram of the reference clock
25. gwin trigger window width lerta set Leading trailing mode sq safety bits set to O 9 triglat trigger latency fake periodicity of fake triggers ovlap overlap hit mode 10 dont diagnosis mode ibs safety bits set to O pil test PLL obspd safety bits set to O track cut regulation loop of PLL m_in disable all signal inputs neg invert phase output of PLL slow safety bits set to O r_adj switch on resolution adjust DA Start data transfer to DAC refclkdiv reference clock divider PLL hsdiv high speed divider PLL 2 fe2 1 activate falling edges chan 2 1 read activate rising edges chan 2 1 11 dac 2 1 DAC data adjch2 1 delay adjustments chan 2 1 12 dac 4 3 DAC data 3 fe4 3 activate falling edges chan 4 3 re4 3 activate rising edges chan 4 3 13 dac 6 5 DAC data adjch4 3 delay adjustments chan 4 3 14 dac 8 7 DAC data 4 feB 5 activate falling edges chan B 5 re6 5 activate rising edges chan 5 5 15 don diagnosis mode adjch6 5 delay adjustments chan 6 5 htest for diagnosis purposes set O stest for diagnosis purposes set O 5 feB 7 activate falling edges chan B 7 dia3 for diagnosis purposes set O re8 7 activate rising edges chan B 7 diae for diagnosis purposes set O adjch8 7 delay adjustments chan 8 7 dia for diagnosis purposes set O diaD for diagnosis purposes set O 6 busclkdel delay for skewed bus clock rosta start ring oszillator adjch1D 11 delay adjustments ref chan sync synchronous mode com common mode B 24 Bbit 24bit dat
26. hannel adjust high resolution channel 4 bit 4 Channel adjust high resolution channel 4 bit 3 Channel adjust high resolution channel 4 bit 2 Channel adjust high resolution channel 4 bit 1 Channel adjust high resolution channel 4 bit 0 enable falling edge channel 3 enable rising edge channel 3 Channel adjust high resolution channel 3 bit 5 Channel adjust high resolution channel 3 bit 4 Channel adjust high resolution channel 3 bit 3 Channel adjust high resolution channel 3 bit 2 Channel adjust high resolution channel 3 bit 1 Channel adjust high resolution channel 3 bit 0 27 Default cocoococoocoococjoocooco Default ceoceoceoeoooooooooooo Register 4 Address 4 Bit No 15 14 13 12 11 10 OrFNWHRANAANA CWO Register 5 Address 5 Bit No 15 14 WANNA Name tra_k6 lead k6 adjust k6 5 adjust k6 4 adjust k6 3 adjust k6 2 adjust k6 1 adjust _k6 0 tra_k5 lead_k5 adjust_k5 5 adjust_k5 4 adjust_k5 3 adjust_k5 2 adjust_k5 1 adjust_k5 0 Name tra_k8 lead k8 adjust k8 5 adjust k8 4 adjust k8 3 adjust k8 2 adjust k8 1 adjust _k8 0 tra_k7 lead_k7 adjust_k7 5 adjust_k7 4 adjust_k7 3 adjust_k7 2 adjust_k7 1 adjust_k7 0 Description enable falling edge channel 6 enable rising edge channel 6 Channel adjust high resolution channel 6 bit 5 Channel adjust high resolution channel 6 bit 4 Channel adjust high resolution channel 6 bit 3 Channel adjust high resolution channel
27. igure 8 REF CLK Distribution 13 Larger systems employing multiple sub racks may benefit from integration of the various timing and control signals into a single board located within each sub rack further providing ECL to LVPECL or Optical to LVPECL translation Additional care should be taken to minimize signal skews Figure 9 depicts various high speed differential signal standards A 4 045 V P EC L 3 295 V 2 345 V LVP ECL 1 595 V el de LVDS 3848 LF TLV RSPECL ov 0 955 V MEWN ECL 1 705 V 1348 v RSNECL Figure 9 Typical High Speed Differential Signal Standards 4 2 _ Connections Backplane The VME64x standard specifies that 160 pin DIN connectors be used for connectors P1 and P2 Tables 1 and 2 show the pin allocations for P1 and P2 respectively Table 1 P1 Pin allocation Z A B C D 1 MPR DVO BBSY DV8 VPC 2 AGND DVI BCLR DV9 AGND 3 MCLK DV2 ACFAIL DV10 V1 4 AGND DV3 BGOIO DVII V2 5 MSD DV4 BGOIO DV12 RsvU 6 AGND DV5 BGIIO DV13 VI J MMD DV6 BG1IO DV14 V2 8 AGND DV7 BG2IO DV15 RsvU 9 MCTL AGND BG2IO AGND GAP 10 AGND SYSCLK BG3IO SYSFAIL GAO 11 RESP AGND BG3IO BERRV GAI 12 AGND DSV 1 BRO SYSRESETV 3 3IN 13 RsvBus DSVO BRI LWV GA2 14 AGND WV BR2 AMV5 3 3IN 15 RsvBus AGND BR3 AV23 GA3 16 AGND DTACKV AMVO AV22 3 3IN 17 RsvB
28. is shown in Figure 4 A 24 bit frame is transmitted to 8 TDCs on a synchronous serial bus This frame consists of a 3 bit device address one broadcast bit a 4 bit register address and 16 bit data A TDC will accept a frame if its unique hardware address matches the device address transmitted in the frame The TDC configuration registers are write only Read back is accomplished using a local copy of the registers stored in FPGA RAM A 128x16 register file RAM stores all 16 registers from each of 8 TDCs Any write to the register file will store the data in RAM and serialize the data to the TDCs The serializer constructs the TDC data frame based on the register file address and write data Jojfonuog I9 SEJA 91807 90eJ19 U SPI Interface Serial EEPROM 512 x 8 Figure 4 Fl TDC Configuration Control Logic For the TDCs to function properly the TDC registers must be configured in a specific order A configuration sequence RAM is provided to remove this burden from the host software The 128x24 sequence RAM permits configuration of any register on any TDC in any order This is accomplished by storing entire 24 bit serial data frames sequentially in RAM A programmable end address is used to mark the end of sequence When the configuration sequence is triggered the RAM is read sequentially from address 0 to the end address The 24 bit data is decoded and passed to the register file where it is stored and serialized
29. nsfer data to DAC3 bit 3 Transfer data to DAC3 bit 2 Transfer data to DAC3 bit 1 Transfer data to DAC3 bit 0 Description Transfer data to DAC6 bit 7 Transfer data to DAC6 bit 6 Transfer data to DAC6 bit 5 Transfer data to DAC6 bit 4 Transfer data to DAC6 bit 3 Transfer data to DAC6 bit 2 Transfer data to DAC6 bit 1 Transfer data to DAC6 bit 0 Transfer data to DACS bit 7 Transfer data to DACS bit 6 Transfer data to DAC5 bit 5 Transfer data to DACS bit 4 Transfer data to DACS bit 3 Transfer data to DACS bit 2 Transfer data to DACS bit 1 Transfer data to DACS bit 0 32 Default ceoceoeoeoooooooooooo Default ceoeceoeoeoooooooooooo Register 14 Address 14 Bit No 15 14 13 12 11 10 oc n Gh dd CWO Register 15 Address 15 Bit No 15 14 9 2 eb oc eo Name dac8 7 dac8 6 dac8 5 dac8 4 dac8 3 dac8 2 dac8 1 dac8 0 dac8 7 dac7 6 dac7 5 dac7 4 dac7 3 dac7 2 dac7 1 dac7 0 Name diagon2 nu nu nu nu nu nu nu diasel 3 diasel 2 diasel 1 diasel 0 rosta syncstart com_mode bus824 Description Transfer data to DACS bit 7 Transfer data to DACS bit 6 Transfer data to DACS bit 5 Transfer data to DACS bit 4 Transfer data to DACS bit 3 Transfer data to DACS bit 2 Transfer data to DACS bit 1 Transfer data to DACS bit 0 Transfer data to DAC7 bit 7 Transfer data to DAC7 bit 6 Transfer data to DAC7 bit 5 Transfer data to DAC7 bit 4 Transfer data to DA
30. nterrupt will be generated by the first module if enabled The user should initiate a DMA block read 32 or 64 bit from the address stored in ADR_MB The length of the block read should be programmed to be larger than the total size of data from all modules e g 4 Mbytes x modules Since the first module initially has the token it will respond with data to the VME bus cycles When data from the first module s block has been depleted it passes the token to the next module in the chain This module will respond with data until its data block is exhausted and the token is passed to the next module The last module will terminate the DMA transfer by issuing BERR when all data from its block has been transferred Upon detecting BERR the first module takes possession of the token Interrupt generation must be re enabled by writing 0x80000000 to the address in ADR32 of the first module 5 3 __ Module Registers CSR Control Status 0x0 0 R W spare control bit 1 R W TDC chip configuration error writing 1 clears status 2 R TDC chip configuration active 3 R event level flag asserted 4 R zero events in buffer 5 R BERR status 6 R Token status 7 R ERROR condition exists for an enabled TDC chip 8 R TDC chip 0 error 9 R TDC chip 1 error 18 10 R TDC chip 2 error 11 R TDC chip 3 error 12 R TDC chip 4 error
31. old DAC 26 Default ceoceoeoeoooooooooooo Default ceoeceoeoeoooooooooooo Register 2 Address 2 Bit No 15 14 13 12 11 10 OrFNWHRANAANA CWO Register 3 Address 3 Bit No 15 14 WANNA Name tra_k2 lead_k2 adjust_k2 5 adjust_k2 4 adjust_k2 3 adjust_k2 2 adjust_k2 1 adjust_k2 0 tra_k1 lead kl adjust k1 5 adjust _k1 4 adjust k1 3 adjust _k1 2 adjust_k1 1 adjust_k1 0 Name tra_k4 lead_k4 adjust_k4 5 adjust_k4 4 adjust_k4 3 adjust_k4 2 adjust_k4 1 adjust_k4 0 tra_k3 lead_k3 adjust_k3 5 adjust_k3 4 adjust_k3 3 adjust_k3 2 adjust_k3 1 adjust_k3 0 Description enable falling edge channel 2 enable rising edge channel 2 Channel adjust high resolution channel 2 bit 5 Channel adjust high resolution channel 2 bit 4 Channel adjust high resolution channel 2 bit 3 Channel adjust high resolution channel 2 bit 2 Channel adjust high resolution channel 2 bit 1 Channel adjust high resolution channel 2 bit 0 enable falling edge channel 1 enable rising edge channel 1 Channel adjust high resolution channel 1 bit 5 Channel adjust high resolution channel 1 bit 4 Channel adjust high resolution channel 1 bit 3 Channel adjust high resolution channel 1 bit 2 Channel adjust high resolution channel 1 bit 1 Channel adjust high resolution channel 1 bit 0 Description enable falling edge channel 4 enable rising edge channel 4 Channel adjust high resolution channel 4 bit 5 C
32. ransfer data to DAC2 bit 7 dac2 6 Transfer data to DAC2 bit 6 dac2 5 Transfer data to DAC2 bit 5 dac2 4 Transfer data to DAC2 bit 4 dac2 3 Transfer data to DAC2 bit 3 dac2 2 Transfer data to DAC2 bit 2 dac2 1 Transfer data to DAC2 bit 1 dac2 0 Transfer data to DAC2 bit 0 dac1 7 Transfer data to DACI bit 7 dac1 6 Transfer data to DACI bit 6 dac1 5 Transfer data to DACI bit 5 dac1 4 Transfer data to DACI bit 4 dac1 3 Transfer data to DACI bit 3 dac1 2 Transfer data to DACI bit 2 dacl 1 Transfer data to DACI bit 1 dac1 0 Transfer data to DACI bit 0 31 Default ceoceoeoeoooooooooooo Default ceoecoeoeoooooooooooo Register 12 Address 12 Bit No 15 14 13 12 11 10 oc n Gh dd CWO Register 13 Address 13 Bit No 15 14 9 2 eb oc eo Name dac4 7 dac4 6 dac4 5 dac4 4 dac4 3 dac4 2 dac4 1 dac4 0 dac4 7 dac3 6 dac3 5 dac3 4 dac3 3 dac3 2 dac3 1 dac3 0 Name dac6 7 dac6 6 dac6 5 dac6 4 dac6 3 dac6 2 dac6 1 dac6 0 dac6 7 dac5 6 dac5 5 dac5 4 dac5 3 dac5 2 dac5 1 dac5 0 Description Transfer data to DAC4 bit 7 Transfer data to DAC4 bit 6 Transfer data to DAC4 bit 5 Transfer data to DAC4 bit 4 Transfer data to DAC4 bit 3 Transfer data to DAC4 bit 2 Transfer data to DAC4 bit 1 Transfer data to DAC4 bit 0 Transfer data to DAC3 bit 7 Transfer data to DAC3 bit 6 Transfer data to DAC3 bit 5 Transfer data to DAC3 bit 4 Tra
33. sembled into an event fragment for the module Individual channels may be disabled during configuration of the F1 TDC chips The FIFO for an individual F1 TDC chip may also be bypassed from the readout seguence The module can be configured to set a flag in a register when the data from a programmed number of triggers is available in its buffers This flag may be optionally used to interrupt the crate controller Readout is accomplished most efficiently using a block transfer protocol Because the number of data words currently stored in the module is not available to the crate controller a slave terminated block transfer is used instead The crate controller is programmed to read out via block mode a number of words that is beyond the storage capacity of the module During readout the module will provide the block of data associated with the programmed number of triggers When this data is depleted the module terminates the block transfer by issuing a bus error BERR A register bit in the module is set when this occurs The crate controller can guery this bit to verify that the bus error was generated deliberately by the module and does not signify a system failure To enhance system performance a set of TDC modules may be read out as a single logical read using a multiblock protocol This involves passing a token between modules along a private line It is implemented in the following way All TDC modules in the set are programmed to respond to
34. serted if chip enabled A 6 External FIFO Empty A 7 TDC Initialized A 8 Loss of Resolution Lock Occurred A 9 TDC Hit FIFO Overflow Occurred A 10 TDC Trigger FIFO Overflow Occurred A 11 TDC Output FIFO Overflow Occurred A 12 External FIFO Full Occurred A 13 15 not used read as 0 16 Resolution LOCKED B 17 TDC Hit FIFO Overflow B 18 TDC Trigger FIFO Overflow B 19 TDC Output FIFO Overflow B 20 External FIFO Full B 21 External FIFO Almost Full BUSY asserted if chip enabled B 22 External FIFO Empty B 23 TDC Initialized B 24 Loss of Resolution Lock Occurred B 25 TDC Hit FIFO Overflow Occurred B 26 TDC Trigger FIFO Overflow Occurred B 27 TDC Output FIFO Overflow Occurred B 28 External FIFO Full Occurred B 29 31 not used read as 0 22 5 4 Data Format The F1TDC chip outputs 24 bit words The words are of 2 types header trailer and data The header trailer words are used as event or channel separators and provide information such as the event number and trigger time A data word contains the time measurement for a hit The bit assignments are shown below Header Trailer word 1 Bit 6 Bit 9 Bit 1 Bit 3 Bit 3 Bit Trigger FIFO Event Trigger Xor setup Chip Channel overflow number time register address address data word 3 Bit 3 Bit 16 Bit time measurement Chip Channel
35. signal inputs with ECL to LVPECL translators the timing control inputs reference clock router translator resolution adjust control and eight 8 F1 ASIC chips The back end section encompasses the FIFOs data bus control logic initialization controls and VME64x interface functions RESOLUTION ADJUST F1 ASIC Chip CONTROL 1 OF 8 64 CH d 120 pS RESOLUTION Mg FO 26 DATA RAM g 1 OF 8 gt 7 DIFFERENTIAL es INPUTS BUS Optional CH an w 24 WRITE READ 24 64 60 pS RESOLUTION BE 9 fe amp Wi z EE HZR as DATA BUS B BE CNIRL CONTROL CLOCK LOGIC 50 MHz wie 64 E6 DATA CONTROL urea STATUS Locic F1 SERIAL SETUP EP1k100 484 RY RESET aro PLD BGA CEX 1K 4 MHz ae oe ROUTER ROUTER TRANSLATOR POWER TIMING CONTROL SNe TIMING CONTROL TRIGGER Z gt em c START DIFFERENTIAL T lt 4 4 BUSY Figure 1 FITDC Module Block Diagram 3 1__ The F1 ASIC Chip The core of our TDC module is the F1 TDC chip A functional block diagram of the Fl ASIC chip is shown in figure 2 This chip uses purely digital delay techniques to measure time by means of a 19 tap asymmetric ring oscillator with phase locked loop PLL control Each of the pipelined F1 chips provides eight channels at 120 pS LSB or four ch
36. t mode is to suppress all headers trailers except the header for channel 0 of the first chip enabled for readout and the trailer for the last chip enabled for readout If all chips 0 7 are enabled the data from the board associated with a trigger will appear as follows header chip 0 channel 0 data chip 0 channel 0 earliest hit data chip 0 channel 0 latest hit data chip 0 channel 7 earliest hit data chip 0 channel 7 latest hit data chip 7 channel 0 earliest hit data chip 7 channel 0 latest hit 24 data chip 7 channel 7 earliest hit data chip 7 channel 7 latest hit trailer chip 7 channel 7 Whenever a suppressed intermediate chip header trailer indicates an error condition Trigger FIFO overflow it will be forced into the data stream so that this condition will not be missed All intermediate chip headers trailers can be forced to be read out by setting register bit CTRL 10 1 The data word transferred across the VME bus includes the 24 bit TDC word and additional board location and F1TDC chip error information as follows DATA module data word 4 Mbyte address range base programmed in register ADR32 23 0 Fl chip word 24 F1 chip Hit FIFO Overflow 25 F1 chip Output FIFO Overflow 26 FI chip Resolution Locked 31 27 Slot ID Slot ID 1 21 indicates valid data The module will return Slot ID 30 when the data is not valid e g an empty
37. up RAM see Appendix C C00 DFF Configuration control registers see Appendix C E00 FFF Spare A32 The base address of this range is programmed into register ADR32 It occupies 4 Mbytes of VME address space organized in 1 M 32 bit words A read of any address in this range will yield the next TDC data word from the module Even though the module is 16 a FIFO the expanded address range allows the VME master to increment the address during block transfers This address range can participate in single cycle 32 bit block and 64 bit block reads The only valid write to this address range is the data value 0x80000000 which re enables the module to generate interrupts after one has occurred The address range must be enabled by setting ADR32 0 1 A32 The lower and upper limits of this address range are programmed into register ADR_MB This common address range for a set of TDC modules in the crate is used to implement the Multiblock protocol By means of token passing TDC data may be read out from multiple TDC modules using a single logical block read The board possessing the token will respond to a read cycle in this address range with the next TDC data word from that module The token is passed along a private daisy chain line to the next module when it has transferred all data from a programmed number of events register EVENT LEVEL The address range must be enabled by setting ADR_MB 0 1 5 2 Module Operation The
38. us AGND AMVI AV21 GA4 18 AGND ASV AMV2 AV20 3 3IN 19 RsvBus AGND AMV3 AV19 RsvBus 20 AGND IACKV AGND AV18 3 3IN 21 RsvBus IACKINV SERA AV17 RsvBus 22 AGND IACKOUTV SERB AV16 3 3IN 23 RsvBus AMV4 AGND AV15 RsvBus 24 AGND AV7 IRQV7 AV14 3 3IN 25 RsvBus AV6 IROV6 AV13 RsvBus 26 AGND AV5 IRQV5 AV12 3 3IN 27 RsvBus AV4 IRQV4 AV11 LI I 28 AGND AV3 IRQV3 AV10 3 3IN 29 RsvBus AV2 IROV2 AV09 Lyo 30 AGND AVI IROVI AVOS 3 3IN 31 RsvBus 12IN 5VSTDBY 12IN AGND 32 AGND 5IN 5IN 5IN VPC Table 2 P2 Pin allocation Pins with shaded entries are not used Z A B C D 1 UD UD 5IN UD UD 2 AGND UD AGND LOOP UD 3 UD UD RETRY LOOP UD 4 AGND UD AV24 AGND UD 5 UD UD AV25 UD UD 6 AGND UD AV26 3 3IN UD 7 UD UD AV27 3 3IN UD 8 AGND UD AV28 3 3IN UD 9 UD UD AV29 3 3IN UD 10 AGND UD AV30 AGND UD 11 UD UD AV31 3 3IN UD 12 AGND UD AGND AGND UD 13 UD UD 5IN UD UD 14 AGND UD DV16 UD UD 15 UD UD DV17 UD UD 16 AGND UD DVIS UD UD 17 UD UD DV19 AGND UD 18 AGND UD DV20 SPARE OUT_R AGND 19 UD UD DV21 TOKEN_OUT_R AGND 20 AGND UD DV22 SPARE IN_R AGND 21 UD UD DV23 TOKEN_IN_R AGND 22 AGND UD AGND BUSY_B_OUT UD 23 UD UD DV24 BUSY_B_OUT UD 24 AGND UD DV25 AGND UD 25 UD UD DV26 TRIGGER_B_IN UD 26 AGND UD DV27 TRIGGER_B_IN UD 27 UD UD DV28 START_B_IN UD 28 AGND UD DV29 STA

A High-Resolution, Multi-Hit, VME64x Time-to

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