µPD70F3116, 70F3116(A), 70F3116(A1)
Contents
1. Internal RAM 10 KB 10 KB NBD Non Break Debug function Provided TRIG DBG ADO DBG to AD3 DBG SYNG CLK DBG None IC1 to IC4 Flash memory programming pin Provided VPP None IC5 Flash memory programming mode Provided MODEO H L MODE1 H MODE2 L VPP 7 8 V None Electrical specifications Current consumption etc differs see individual data sheets Other Cautions 1 Circuit scale and mask layout differ thus noise immunity noise radiation etc differ There are differences in noise immunity and noise radiation between the flash memory version and mask ROM version When pre producing an application set with the flash memory version and then mass producing it with the mask ROM version be sure to conduct sufficient evaluation for commercial samples not engineering samples of the mask ROM version When switching from the flash memory version to the mask ROM version write the same code to the free area of the internal ROM Preliminary Data Sheet U15299EJ1VODS NIEC PD70F3116 70F3116 A 70F3116 A1 2 PIN FUNCTIONS 2 1 Port Pins 1 3 Pin Name 10 Alternate Function Port 0 8 bit input only port ESOO INTPO 0 N ESO1 INTP1 ADTRGO INTP2 ADTRG1 INTP3 INTP4 INTP5 INTP6 Port 1 TIUD10 TO10 6 bit I O port TCUD10 INTP100 Input output can be specified in 1 bit units TCLRIO NTP101 TIUD11 TO11 TCUD11 INTP110 TCLR11 INTP111 Port 2 TI2 INTP2. AC test output test points a Other than b below 0 8VDD5 ee 0 8Vpps Test points 0 2Vpps aa Rss 0 2Vpps b ADO DBG to AD3 DBG TRIG DBG 0 8VDDs ss o ud 0 8Vpps Test points 0 2Vpo3 0 2Vpo3 Load condition DUT Device under test J C 50 pF Caution In cases where the load capacitance is greater than 50 pF due to the circuit configuration insert a buffer or other element to reduce the device s load capacitance to 50 pF or lower Preliminary Data Sheet U15299EJ1VODS 27 NIEC PD70F3116 70F3116 A 70F3116 A1 1 Clock timing 1 2 TA 40 to 85 C uPD70F3116 70F3116 A TA 40 to 110 C uPD70F3116 A1 VDD3 CVDD 3 0 to 3 6 V VDD5 5 V 0 5 V Vss3 Vss5 CVss 0 V output pin load capacitance CL 50 pF s mme 9 fm mme 9 mme eo mme H E wa a x we Nut ma 20 om CLKOUT high level width O8T 9 ms CLKOUT rise time CLKOUT fall time n S Notes 1 40 C lt Ta 110 C 2 40 C lt Ta lt 85 C 3 When interfacing to the external devices using the CLKOUT signal make the internal system clock frequency fx 32 MHz or lower Remark T tcyk 28 Preliminary Data Sheet U15299EJ1VODS NIEC uPD70F3116 70F3116 A 70F3116 A1 1 Clock timing 2 2 X1 PLL mode X1 direct mode CLKOUT output 2 Output waveform except for X1 and CLKOUT TA
3. 40 to 85 C uPD70F3116 70F3116 A TA 40 to 110 C uPD70F3116 A1 Vpp3 CVDD 3 0 to 3 6 V VDD5 5 V 0 5 V Vss3 Vss5 CVss 0 V output pin load capacitance CL 50 pF Signals other than X1 and CLKOUT Preliminary Data Sheet U15299EJ1VODS 29 NEC PD70F3116 70F3116 A 70F3116 A1 3 Reset timing TA 40 to 85 C uPD70F3116 70F3116 A TA 40 to 110 C uPD70F3116 A1 VDD3 CVDD 3 0 to 3 6 V VDD5 5 V 0 5 V Vss3 Vss5 CVss 0 V output pin load capacitance CL 50 pF Symbol RESET pinhighevel with M wes 80 rs RESET pin low level width 15 twrsL At power on and at STOP mode 500 Tos ns release Other than at power on and at 500 ns STOP mode release Caution Thoroughly evaluate the oscillation stabilization time Remark Tos Oscillation stabilization time RESET input 30 Preliminary Data Sheet U15299EJ1VODS NIEC uPD70F3116 70F3116 A 70F3116 A1 4 Multiplex Bus Timing a CLKOUT asynchronous TA 40 to 85 C uPD70F3116 70F3116 A TA 40 to 110 C uPD70F3116 A1 Vpp3 CVDD 3 0 to 3 6 V VDD5 5 V 0 5 V Vss3 Vss5 CVss 0 V output pin load capacitance CL 50 pF Wueesewemama E sr Te tresort tomaste am ae os me amem H tm om fm paven G wo femme me bur wensROi wo Terra mm Daly ne tom aaret ORB TWR OWL lt gt fm os mo estate mori f le
4. CVss 0 V Westover seme a gt wen Lo I Lo wieREETenwme ml 1 1 us RESET wecunsatime 07 wor weersv wreme fm cmo om www f m Ver counterhighevel width 2 toe ts Ver counterlowievelwath e ta J ts Ver counterrisetime Mm te ts Ver counterfalltime e e ts Verl to Voosl resettime o tre tos Remark T tcv RESET input 46 Preliminary Data Sheet U15299EJ1VODS NEC 5 PACKAGE DRAWING 144 PIN PLASTIC LQFP FINE PITCH 20x20 Al NS NOTE Each lead centerline is located within 0 08 mm of its true position T P at maximum material condition Preliminary Data Sheet U15299EJ1VODS uPD70F3116 70F3116 A 70F3116 A1 detail of lead end S ITEM MILLIMETERS A 22 0 0 2 20 0 0 2 20 0 0 2 22 0 0 2 1 25 1 25 0 22 0 05 0 08 0 5 T P 1 0 0 2 0 5 0 2 0 03 0 17 9 07 0 08 1 4 0 10 0 05 o 4 3 30 MO I O VUIZ Z Iri XIL l I Oln ol olw 1 5 0 1 144GJ 50 UEN 47 NIEC uPD70F3116 70F3116 A 70F3116 A1 6 RECOMMENDED SOLDERING CONDITIONS The uPD70F3116 should be soldered and mounted under the following recommended conditions For details of the recommended soldering conditions refer to the document Semiconductor
5. 110 C uPD70F3116 A1 Vpp3 CVDD 3 0 to 3 6 V VDD5 5 V 40 5 V Vss3 Vss5 CVss 0 V output pin load capacitance CL 50 pF nos falso wma mm e sota igh wan 2 mo arem 0 no Uxoreewa d wow mo arem ro monsupimeqo SEG alum Tee me Conros ime tomasen em em I mw fm on ouput delay tine rom ASTD e www fans Tron ct ot tme trom ASST a von rear o Remarks 1 T tcv 2 k Setting value of PRSCMn register of UARTn 3 n 1 2 Preliminary Data Sheet U15299EJ1VODS 41 NEC uPD70F3116 70F3116 A 70F3116 A1 10 UART1 UART2 timing 2 2 ASCKn 1 0 lt 76 gt lt gt lt 8 gt Remark n 1 2 42 Preliminary Data Sheet U15299EJ1VODS NIEC uPD70F3116 70F3116 A 70F3116 A1 11 NBD timing TA 0 to 40 C VDD3 CVDD 3 0 to 3 6 V VDD5 5 V 0 5 V Vss3 Vss5 CVss 0 V output pin load capacitance C 100 pF E me ws lp wa woomwedwm e e 8 mw NSD at ovputceeytine ae wo 5 wem m wpsmopum me ar es 2 me NSD at int sep tine e es m fm wosmmumem sew fs mw src pateo tner ess m fm swomuwme C wom 8 fm CLK DBG input lt 83 gt moosswrsostmmn XXX lt 84 gt a lt 85 gt oswa om L XEO XT TN lt 87 gt SYNC input NN di Preliminary Data Sheet U15299EJ1VODS 43 NIEC uPD70F3116 70F3116 A 70F3116 A1 A D Converter Characteris
6. AVrero AVpo ADTRG1 ANI10 to ANI17 gt Preliminary Data Sheet U15299EJ1VODS AVss AVrer AVpo controller NIEC uPD70F3116 70F3116 A 70F3116 A1 CONTENTS 1 DIFFERENCES BETWEEN uPD70F3116 AND UPD703116 e eere 7 Za PINFUNCTONS ia 8 Z POP PINO Je 8 22 NORPOL ad 9 ee t RHRm 11 2 3 Pin I O Circuits and Recommended Connection of Unused Pins eese 14 3 PROGRAMMING FLASH MEMORY eesnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnennnennnennnennnnnnnennnnnnnnnnnnnnnnnnnennnennnennne 17 3 1 Selecting Communication Mode cinc ci 17 3 2 Flash Memory Programming Functions aria 18 3 3 Connecting Dedicated Flash Programmer nnxxrnnnnnnnnnnnnvnnnnnnnennnnnnnnnnnnnnnnnernnnnnennnnnnnnnnnnernnnnernnnnnnnnnnnnuenn 18 4 ELECTRICAL SPECIFICA DON S Sn 20 4 1 Normal Operation Mode asso DS ADO eee 20 4 2 Flash Memory Programming Mode rrnnnnrnnnnvnnnnvnnnnnnnnnnnnnnnnnnnnnnnnernnnnrnnnnnnnnnnnnnnernnnnnnnnnnnnnnennnnnnnnnrnnnnnnnnnr 45 5 PACKAGE DRAWING coin is 47 6 RECOMMENDED SOLDERING CONDITIONS renurnnernnennnnnnnnnnnannnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnennnnnnnnnnnunnn 48 6 Preliminary Data Sheet U15299EJ1VODS NEC uPD70F3116 70F3116 A 70F3116 A1 1 DIFFERENCES BETWEEN uPD70F3116 AND uPD703116 Internal ROM Part Number uPD70F3116 Flash memory 256 KB uPD703116 Mask ROM 256 KB
7. KM lA O IN O MODE 1 MODE2 Vee o e Power application input for flash memory write md N Preliminary Data Sheet U15299EJ1VODS NE uPD70F3116 70F3116 A 70F3116 A1 3 3 Input Control signal input to insert wait in bus cycle PCMO Output Bus hold acknowledge output PCM2 N Pin Name SIE A gt 4 A HLDRQ Input Bus hold request input PCM3 LWR Output External data lower byte write enable signal output PCTO UWR Output External data higher byte write enable signal output PCT1 Output External data bus read strobe signal output PCT4 Output External data bus address strobe signal output PCT6 Ol gt D O oj 4 UJ Output Chip select signal output PCSO CS1 PCS1 CS2 PCS2 CS3 PCS3 CS4 PCS4 CS5 PCS5 CS6 PCS6 CS7 PCS7 I O 16 bit address data bus for external memory PDLO to PDL15 Output Higher 8 bit address bus for external memory PLHO to PLH7 Input System reset input 3 V interface 5 V tolerance Input Crystal resonator connection pin for system clock oscillation 3 V interface Input to X1 pin when providing clocks from outside Output System clock output PCM1 NO lt O gt O O X xX Al gt gt S lt A mialg e g QA P oO m O mia las PIE gt gt QR q Input Input specifying clock generator operation mode Input Reference voltage input for A D converter O AVREFO AVREF1 Input Reference voltage input for A D c
8. TI2 INTP20 P21 TO21 INTP21 to P24 TO24 INTP24 P25 TCLR2 INTP25 P26 TI3 TCLR3 INTP30 P27 TO3 INTP31 P30 RXDO P31 TXDO P32 RXD1 P33 TXD1 P34 ASCK 1 P35 RXD2 P36 TXD2 P37 ASCK2 5 AC P40 SIO P41 SO0 P42 SCKO P43 SM P44 SO1 P45 SCK1 5 AC P46 CRXD P47 CTXD 5 AC a on gt o on O e on gt o O 4 Preliminary Data Sheet U15299EJ1VODS NE A uPD70F3116 70F3116 A 70F3116 A1 Table 2 1 Types of Pin I O Circuits and Recommended Connection 2 2 I O Circuit Type Recommended Connection Input Independently connect to Voos or Vsss via a resistor Output Leave open PCMO WAIT PCM1 CLKOUT PCM2 HLDAK PCM3 HLDRQ PCM4 PCTO LWR PCT1 UWR PCT2 PCT3 PCT4 RD PCT5 PCT6 ASTB PCT7 PCSO CSO PCS1 CS1 PCS2 CS2 PCS3 CS3 PCS4 CS4 PCS5 CS5 PCS6 CS6 PCS7 CS7 PDHO A16 to PDH7 A23 PDLO ADO to PDL15 AD15 ADO DBG to AD3 DBG TRIG DBG CLK DBG SYNC ANIOO to ANIO7 ANI10 to ANI17 TO000 to TO005 TO010 to TO015 MODEO to MODE2 5 AC Independently connect to CVoo or CVss via a resistor 3 Leave open low level output Independently connect to CVss via a resistor Independently connect to CVpp via a resistor 7 Connect to AVss 4 Connect to Vsss Connect to Vsss Connect to Vsss Connect to Vpps NO lt PP RESET CKSEL gt lt N Uy 5 AVss AVrero AVREF1 AVDD oO Preliminary Data Sheet U15299EJ1VODS 1 NI EC D D70F3116 70F3116 A
9. TO000 to TO005 Timer output HLDRQ Hold request TOO010 to TOO15 INTPO to INTP6 Interrupt request from peripherals TO10 TO11 INTP100 INTP101 TO21 to TO24 TO3 INTP110 INTP111 TRIG DBG Debug trigger INTP20 to INTP25 TXDO to TXD2 Transmit data INTP30 INTP31 UWR Upper write strobe LWR Lower write strobe VDD3 VDD5 Power supply MODEO to MODE2 Mode VPP Programming power supply NMI Non maskable interrupt request Vss3 Vss5 Ground POO to PO7 Port O WAIT Wait P10 to P15 Port 1 X1 X2 Crystal 4 Preliminary Data Sheet U15299EJ1VODS NEC INTERNAL BLOCK DIAGRAM INTP20 to INTP25 INTP30 INTP31 INTP100 INTP101 INTP110 INTP111 ESOO ESO1 TOO000 to TODOS lt TOO10 to TOO15 TIUD10 TO10 lt gt TCUD10 TCLR10 TIUD11 TO11 TCUD11 TCLR11 TI2 TCLR2 TO21 to TO24 TIS TCLRS TOS TXDO RXDO CLK DBG gt SYNC ADO DBG to AD3 DBG lt gt gt TRG DBG TMO 2ch TM1 2ch TM2 2ch TM3 ich TM4 ich uPD70F3116 70F3116 A 70F3116 A1 32 bit barrel shifter System registers General purpose registers 32bitsx32 Multiplier 32x32 gt 64 Instruction queue HLDRQ HLDAK CSO to CS7 gt A16 to A23 lt gt ADO to AD15 PDLO to PDL15 lt gt PDHO to PDH7 lt gt PCSO to PCS7 lt gt PCTO to PCT7 lt gt PCMO to PCM4 lt gt P40 to P47 lt gt P30 to P37 lt gt P20 to P27 lt gt P10 to P15 lt gt POO to PO7 gt AVss
10. function have not yet been initialized Hence power on does not guarantee out pin levels I O settings or contents of registers Device is not initialized until the reset signalis received Reset operation must be executed immediately after power on for devices having reset function 50 Preliminary Data Sheet U15299EJ1VODS NEC uPD70F3116 70F3116 A 70F3116 A1 Regional Information Some information contained in this document may vary from country to country Before using any NEC product in your application please contact the NEC office in your country to obtain a list of authorized representatives and distributors They will verify e Device availability e Ordering information e Product release schedule e Availability of related technical literature e Development environment specifications for example specifications for third party tools and components host computers power plugs AC supply voltages and so forth e Network requirements In addition trademarks registered trademarks export restrictions and other legal issues may also vary from country to country NEC Electronics Inc U S Santa Clara California Tel 408 588 6000 800 366 9782 Fax 408 588 6130 800 729 9288 NEC Electronics Germany GmbH Duesseldorf Germany Tel 0211 65 03 02 Fax 0211 65 03 490 NEC Electronics UK Ltd Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Italiana s r l Milano Italy Te
11. lines indicate high impedance 2 n 0 1 Preliminary Data Sheet U15299EJ1VODS 39 NEC PD70F3116 70F3116 A 70F3116 A1 9 UARTO timing TA 40 to 85 C uPD70F3116 70F3116 A TA 40 to 110 C uPD70F3116 A1 VDD3 CVDD 3 0 to 3 6 V VDD5 5 V 0 5 V Vss3 Vss5 CVss 0 V output pin load capacitance CL 50 pF Symbol UARTO baud rate generator input fBRG 25 MHz frequency Remark fare UARTO baud rate generator input frequency can be selected from fx fx 2 fx 4 fx 8 fx 16 fx 32 fx 64 1 128 fx 256 fx 512 fx 1024 and fx 2048 by setting the TPS3 to TPSO bits of clock select register 0 CKSRO fx Internal system clock frequency 40 Preliminary Data Sheet U15299EJ1VODS NIEC uPD70F3116 70F3116 A 70F3116 A1 10 UART1 UART2 timing 1 2 a Clocked master mode TA 40 to 85 C uPD70F3116 70F3116 A TA 40 to 110 C uPD70F3116 A1 Vpp3 CVDD 3 0 to 3 6 V VDD5 5 V 40 5 V Vss3 Vss5 CVss 0 V output pin load capacitance CL 50 pF ASCKneyote irei Output 000 om RSCKnhighiewiweth 74 meos Output kT 20 m ASCKn lowlevel width T ts Output kT 20 ns wonse as se m ste fm mone metis em em I eo 1 e Tron eur ot tme trom ASST a von ra eo Remarks 1 T tcyk 2 k Setting value of PRSCMn register of UARTn 3 n 1 2 b Clocked slave mode TA 40 to 85 C uPD70F3116 70F3116 A TA 40 to
12. 1 P15 O TCUD11 INTP110 P14 O INTP6 P07 O INTP5 P06 O INTP4 P05 O NMI P00 O AVss O AVDD O TO015 O TO014 O TO013 O TO012 O TO011 O TO010 O VDD3 O Vss3 O Vss5 O VDD5 O TO005 O TO004 O TO003 O TO002 O TO001 O TO000 cr NC co T r r r r r r r rrr ANIO7 O 1 8 O TIUD11 TO11 P13 AVpp O 2 7 O TCLR10 INTP101 P12 AVss O 3 6 O TCUD10 INTP100 P11 AVREF1 O 4 5 O TIUD10 TO10 P10 ANI10 O 5 4 O PCM4 ANI11 O 6 3 O HLDRQ PCM3 ANI12 O 7 2 O HLDAK PCM2 ANI13 O 8 O CLKOUT PCM1 ANI14 O 9 O WAIT PCMO ANI15 O 10 O PCT7 ANI16 O 11 O ASTB PCT6 ANI17 O 12 O PCT5 TRIG DBG O 13 O RD PCT4 AD3_DBG O 14 O PCT3 AD2 DBG O 15 O PCT2 AD1 DBG O 16 O UWR PCT1 ADO DBG O 17 O LWR PCTO SYNC O 18 O VDD5 CLK_DBG O 19 O Vss5 RESET O 20 O VPP CVpp O O CS7 PCS7 CVss O O CS6 PCS6 X10 O CS5 PCS5 X20 O CSA PCSA CKSEL O O CS3 PCS3 MODEO O O CS2 PCS2 MODE1 O O CS1 PCS1 MODE2 O O CSO PCSO SIO P40 O O A23 PDH7 SO0 P41 O O A22 PDH6 SCKO P42 O O A21 PDH5 SH PA3 O O A20 PDH4 SO1 P44 O O A19 PDH3 SCK1 P45 O O A18 PDH2 CRXD P46 O O A17 PDH1 CTXD P47 O O A16 PDHO 000000000000000000000000000000000000 MICO COM 00 C0 CO CV CN CN CL EV CN GV QN 3 9 o gt SS SS der Q aacandcaaoanaaoanac2222n00n00000000aua 2 GC CO G GG C G ODO 00000000006 000000 Se 392992902 Qe 222202 LALLLLLLLLLAAADAR SESO3SSD C C t C C c FO000 42H FFFFOS E Caution When used in normal operation mode connect the
13. 1 TO21 INTP21 to P24 TO24 INTP24 P25 TCLR2 INTP25 P26 TI3 TCLR3 INTP30 P27 TO3 INTP31 P30 RXDO P32 RXD1 P34 ASCK1 P35 RXD2 P37 ASCK2 P40 SIO PA2 SCKO P43 SI1 PA5 SCK1 P46 CRXD MODEO to MODE2 CKSEL RESET 2 CLK DBG SYNC ADO DBG to AD3 DBG Remark The TYP value is a reference value for when Ta 25 C STOP mode setup Voos V DDS Vppor HVpppr RESET input NMI input Release by falling edge NMI input Release by rising edge Preliminary Data Sheet U15299EJ1VODS 25 NIEC uPD70F3116 70F3116 A 70F3116 A1 AC Characteristics TA 40 to 85 C uPD70F3116 70F3116 A TA 40 to 110 C uPD70F3116 A1 Vpp3 CVDD 3 0 to 3 6 V VDD5 5 V 40 5 V Vss3 Vss5 CVss 0 V output pin load capacitance CL 50 pF AC test input test points a Other than b to e below 0 8VDD5 id 0 8VDD5 Test points 0 2Vpps mp uid BE 0 2Vpps b P31 TXDO P33 TXD1 P36 TXD2 P41 500 P44 SO1 P47 CTXD 0 7VDD5 sd 0 7Vbo5 Test pionts 0 3VDD5 0 3VDD5 c ADO PDLO to AD15 PDL15 A16 PDHO to A23 PDH7 LWR PCTO UWR PCT1 PCT2 PCT3 RD PCT4 PCT5 ASTB PCT6 PCT7 WAIT PCMO CLKOUT PCM1 HLDAK PCM2 HLDRQ PCM3 PCM4 CSO PCSO to CS7 PCS7 Test points d CLK DBG SYNC ADO DBG to AD3 DBG RESET 0 8VDD3 Test points 0 2Vpps 26 Preliminary Data Sheet U15299EJ1VODS NIEC uPD70F3116 70F3116 A 70F3116 A1 e X1 0 8Vpps Test points 0 15Voo3
14. 116 Caution To supply the operating clock for the uPD70F3116 configure an oscillator with resonators and capacitors on the circuit board on which the uPD70F3116 is incorporated Figure 3 3 Connection of Dedicated Flash Programmer for CSIO Mode Dedicated flash programmer uPD70F3116 Caution To supply the operating clock for the uPD70F3116 configure an oscillator with resonators and capacitors on the circuit board on which the uPD70F3116 is incorporated 18 Preliminary Data Sheet U15299EJ1VODS NIEC uPD70F3116 70F3116 A 70F3116 A1 Figure 3 4 Connection of Dedicated Flash Programmer for Handshake Supporting CSI Mode Dedicated flash programmer uPD70F3116 rn e Caution To supply the operating clock for the uPD70F3116 configure an oscillator with resonators and capacitors on the circuit board on which the uPD70F3116 is incorporated Preliminary Data Sheet U15299EJ1VODS 19 NIEC uPD70F3116 70F3116 A 70F3116 A1 4 ELECTRICAL SPECIFICATIONS 4 1 Normal Operation Mode Absolute Maximum Ratings Ta 25 C Power supply voltage ws vem aero v om ovem oswus v ow espinosas v Am Amon ostovemeos v Aves AVepn 10500408 v wo qvem aaas vo rvs Pinsfornso ostovemeos v vu RESET pin when Veis sumie oster v Gexmuwime ue om toro v Analog input voltage VIAN ANIOO to ANIO7 pins 0 5 to Vpps 0 5 ANI10 to ANI17 pins 0 5 to AVpp 0 5 Analog reference i
15. 20 8 bit I O port TO21 INTP21 Input output can be specified in 1 bit units TO22 INTP22 TO23 INTP23 TO24 INTP24 TCLR2 INTP25 T13 TCLR3 INTP30 TO3 INTP31 Port 3 RXDO 8 bit I O port TXDO Input output can be specified in 1 bit units TU U O O Eh l G Y al 0 I 0 NO U U U N1INININ gt A JIO IN 0 N IN N IO 0 Q G N QD NO al RXD1 TXD1 ASCK1 0 L Co 417 Z X X lt FATTA GLE THE gt QD O A N 8 Preliminary Data Sheet U15299EJ1VODS e T Pin Name 0 A O RR TR TR TR TR O lO LEIO nn 0 I N PCMO PCM1 PCM2 PCM3 PCM4 PCTO PCT1 PCT2 PCT3 PCT4 PCT5 PCT6 PCT7 PCSO PCS1 PCS2 PCS3 PCS4 PCS5 PCS6 PCS7 PDHO PDH1 PDH2 PDH3 PDH4 PDH5 PDH6 PDH7 uPD70F3116 70F3116 A 70F3116 A1 2 3 Vo Alternate Function Port 4 8 bit I O port Input output can be specified in 1 bit units e O O I O Port CM 5 bit I O port Input output can be specified in 1 bit units ERE A lEI o all ole 5 Cc El GE Clio S N ES A gt Ol A I O Port CT 8 bit I O port Input output can be specified in 1 bit units 0 c 0 0 O gt o O UJ I O Port CS 8 bit I O port CS1 Input output can be specified in 1 bit units O 09 Pe ses qum gl o o o Xllo I O Port DH 8 bit I O port Input output can be specified in 1 bit units A20 A21 A22 A23 Oo Preliminary Da
16. 70F3116 A1 Figure 2 1 Pin I O Circuits Type2 Type 5 V DD Data P ch IN e O IN OUT O gt Output F N ch disable 777 Schmitt triggered input with hysteresis characteristics Input enable Type 3 Type 5 AC VDD Vpp Data IN OUT O P ch Output O OUT disable N ch Input enable Type 4 Type 7 VDD Data P ch P ch EM IN OUT IN Comparator Output N ch N ch disable AT gt Vrer threshold voltage 16 Push pull output with possible high impedance output P ch N ch both off Preliminary Data Sheet U15299EJ1VODS NIEC uPD70F3116 70F3116 A 70F3116 A1 3 PROGRAMMING FLASH MEMORY The following two flash memory programming methods are available 1 On board programming The program is written to the flash memory using the dedicated flash programmer after the uPD70F3116 is mounted on the target board Install the connectors etc required for communication with the dedicated flash programmer on the target board 2 Off board programming The program is written to the flash memory using the dedicated adapter before the uPD70F3116 is mounted on the target board 3 1 Selecting Communication Mode Writing to the flash memory is done via serial communication using the dedicated flash programmer Select one of the communication modes listed in Table 3 1 Base selection of the communication mode on the selection format shown in Figure 3 1 Refer to the number o
17. Device Mounting Technology Manual C10535E For soldering methods and conditions other than those recommended below contact an NEC sales representative Table 6 1 Surface Mounting Type Soldering Conditions uPD70F3116GJ UEN 144 pin plastic LQFP fine pitch 20 x 20 uPD70 F3116GJ A UEN 144 pin plastic LQFP fine pitch 20 x 20 uPD70 F3116GJ A1 UEN 144 pin plastic LQFP fine pitch 20 x 20 Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature 230 C Time 30 seconds max at 210 C or higher IR30 103 2 Count Two times or less Exposure limit 3 days after that prebake at 125 C for 10 hours Partial heating Pin temperature 300 C max Time 3 seconds max per pin row E Note After opening the dry pack store it at 25 C or less and 65 RH or less for the allowable storage period 48 Preliminary Data Sheet U15299EJ1VODS NIEC uPD70F3116 70F3116 A 70F3116 A1 MEMO Preliminary Data Sheet U15299EJ1VODS 49 NIEC uPD70F3116 70F3116 A 70F3116 A1 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note Strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it once when it has occurred Environmental control must be adequate When it is dry
18. LKOUT output HLDRQ input HLDAK output A16 to A23 output ADO to AD15 I O ASTB output RD output LWR output UWR output Preliminary Data Sheet U15299EJ1VODS 35 NIEC PD70F3116 70F3116 A 70F3116 A1 5 Interrupt timing TA 40 to 85 C uPD70F3116 70F3116 A TA 40 to 110 C uPD70F3116 A1 Vpp3 CVDD 3 0 to 3 6 V VDD5 5 V 0 5 V Vss3 Vss5 CVss 0 V output pin load capacitance CL 50 pF meea ue me 9 e raar ue ome om p emos sew mo aa arero neia o0 r 12201025 ten dt Merspesites sre m RRR te me 12201025 tunen arero neia m r n 20 to 25 when digital filter specified TRA ons Remark T Digital filter sampling clock T can be selected by setting the following registers e INTP100 INTP101 Can be selected from fxrM10 fxTM10 2 fxTM10 4 and fxTM10 8 by setting the NRC101 and NRC100 bits of the timer 10 noise elimination time select register NRC10 fxrM10 clock selected with the timer 1n timer 2n clock select register PRMO2 n 0 1 e INTP110 INTP111 Can be selected from fxTM11 fxTM11 2 fxTM11 4 and fxTM11 8 by setting the NRC111 and NRC110 bits of the timer 11 noise elimination time select register NRC11 fxrM11 clock selected with the timer 1n timer 2n clock select register PRMO2 n 0 1 e INTP30 Can be selected from fxrM3 2 fxrM3 4 and fxrM3 8 fxTM3 16 by setting the NRC31 an
19. NIEC uPD70F3116 70F3116 A 70F3116 A1 Notes 1 ADO PDLO to AD15 PDL15 A16 PDHO to A23 PDH7 LWR PCTO UWR PCT1 PCT2 PCT3 RD PCT4 PCT5 ASTB PCT6 PCT7 WAIT PCMO CLKOUT PCM1 HLDAK PCM2 HLDRQ PCM3 PCM4 CSO PCSO to CS7 PCS7 CLK DBG SYNC ADO DBG to AD3 DBG P31 TXDO P33 TXD1 P36 TXD2 P41 S00 P44 SO1 P47 CTXD ADO DBG to AD3 DBG TRIG DBG TO000 to TO005 TO010 to TO015 Value in the PLL mode Determine the value by calculating fx from the operating conditions The current of TOOOO to T0005 and TO010 to TOO15 pins is not included pa E e ou e ope T9 Remark fx Internal system clock frequency 24 Preliminary Data Sheet U15299EJ1VODS NIEC uPD70F3116 70F3116 A 70F3116 A1 Data Retention Characteristics Ta 40 to 85 C uPD70F3116 70F3116 A Ta 40 to 110 C uPD70F3116 A1 a E ee aot ET BEN Data retention current IDDDR VDD 40 0 lt Ta lt 85C 20 eo ua emere ue O p lI LL L4 Power supply voltage retention time from STOP mode setting STOP release signal input time El la Data retention input voltage high VIHDR Noe sd 0 8HVooor HVDDDR wa Joven Mme Data retention input voltage low ViLDR Notet 05 0 2HVpoor nor 05 Notes 1 POO NMI P01 ESOO INTPO P02 ESO1 INTP1 PO3 ADTRGO INTP2 P04 ADTRG1 INTP3 PO5 INTP4 to PO7 INTP6 P10 TIUD10 TO10 P11 TCUD10 INTP100 P12 TCLR10 INTP101 P13 TIUD11 TO11 P14 TCUD11 INTP110 P15 TCLR11 INTP111 P20 TI2 INTP20 P2
20. PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT NIEC uPD70F3116 70F3116 A 70F3116 A1 V850E IA1 32 BIT SINGLE CHIP MICROCONTROLLER DESCRIPTION The uPD70F3116 70F3116 A and 70F3116 A1 are products of the V850 Family of 32 bit single chip microcontrollers for real time control applications These microcontrollers integrate a 32 bit CPU ROM RAM an interrupt controller timers such as a 3 phase sine wave PWM timer for motor a serial interface an FCAN controller an A D converter a DMA controller and other functions on a single chip The uPD70F3116 70F3116 A and 70F3116 A1 are products that substitute flash memory for the internal mask ROM of the uPD703116 703116 A and 703116 A1 This enables users to perform on board program writing and erasure making this product effective for evaluation during system development small lot production of multiple devices and rapid production start Detailed function descriptions are provided in the following user s manuals Be sure to read them before designing V850E IA1 User s Manual Hardware U14492E V850E1 User s Manual Architecture U14559E FEATURES O O O O O QOO Number of instructions 83 Minimum instruction execution time 20 ns with a 50 MHz internal clock General purpose registers 32 bits x 32 registers Instruction set suitable for control applications Internal memory Flash memory 256 KB RAM 10 KB Memory access control supporting SRAM and ROM So
21. Vpr pin directly to Vsss pin or pull it down In a system where an on chip flash memory is rewritten while mounted on board pull the Vpp pin down Connecting via a resister of 5 kQ or more and 50 kQ or less is recommended for pull down connection Preliminary Data Sheet U15299EJ1VODS 3 NIEC uPD70F3116 70F3116 A 70F3116 A1 PIN IDENTIFICATION A16 to A23 Address bus P20 to P27 Port 2 ADO to AD15 Address data bus P30 to P37 Port 3 ADO DBG to AD3 DBG Debug address data bus P40 to P47 Port 4 ADTRGO ADTRG1 AD trigger input PCMO to PCM4 Port CM ANIOO to ANIO7 Analog input PCSO to PCS7 Port CS ANI10 to ANI17 PCTO to PCT7 Port CT ASCK1 ASCK2 Asynchronous serial clock PDHO to PDH7 Port DH ASTB Address strobe PDLO to PLD15 Port DL AV bb Analog power supply RD Read AVREFo AVREF1 Analog reference voltage RESET Reset AVss Analog ground RXDO to RXD2 Receive data CKSEL Clock generator operating mode select SCKO SCK1 Serial clock CLK DBG Debug clock SIO SIT Serial input CLKOUT Clock output SO S01 Serial output CRXD Receive data for controller area network SYNC Sync CSO to CS7 Chip select TCLR10 TCLR11 Timer clear CTXD Transmit data for controller area network TCLR2 TCLRS CVDD Clock generator power supply TCUD10 TCUD11 Timer control pulse input CVss Clock generator ground TI2 TI3 Timer input ESOO ESO1 Emergency shut off TIUD10 TIUD11 Timer count pulse input HLDAK Hold acknowledge
22. d CMOS inverter as closely to the X1 pin as possible 2 Thoroughly evaluate the matching between the uPD70F3116 and the high speed CMOS inverter 22 Preliminary Data Sheet U15299EJ1VODS NIEC uPD70F3116 70F3116 A 70F3116 A1 DC Characteristics TA 40 to 85 C uPD70F3116 70F3116 A TA 40 to 110 C uPD70F3116 A1 VDD3 CVDD 3 0 to 3 6 V VDD5 5 V 10 5 V Vss3 Vss5 CVss 0 V We meewoms om we fv We eana aeae ome we vo We mm iw ves vo we sem omm ss Y We feno fo am vo we mam m 9 p eom v ve mememewnwmenas o omm V We mm E ume v Vite RESET pin Output voltage high ol VoH1 Pins other than lou 2 5 mA Vpps 1 0 V Note 4 Vou Pins for NBD lou 12 5 mA PWM outputN ts 3 Vop3 1 0 Output voltage low Vout lo 15 mA lo 2 5 mA VoLz Pins other than lo 2 5 mA Notes 4 5 VOLS lo 2 5 mA Analog pin input leakage ILIAN Current In HALT mode lona Note 7 In IDLE mode loo3 Vpp3 CVpp In STOP Ipp4 Vpp3 CVpo 40 C lt Ta 85 C mode 40 C lt TA lt amp 110 C Preliminary Data Sheet U15299EJ1VODS 23 10 10 Power 2 4fx 25 4 5fx mA supply current During normal operation o e 3 Note 6 1 2fx 2 3fx mA D O gt m 10 gt m 0 5 3 E IE E E IE IE IE E N N W N w O O olo oO 0 1000 NO AC gt O olov O o Ola pI BR O
23. d NRC30 bits of the timer 3 noise elimination time select register NRC3 fxTM3 clock selected with the timer 3 clock select register PRMO3 e INTP31 Can be selected from fxrM3 32 fxrM3 64 and fxTM3 128 fxTM3 256 by setting the NRC33 and NRC32 bits of the timer 3 noise elimination time select register NRC3 fxtm3 clock selected with the timer 3 clock select register PRMO3 NMI input INTPn input Remark n 0 to 6 100 101 110 111 20 to 25 30 31 36 Preliminary Data Sheet U15299EJ1VODS O NEC pPD7OF3116 7OF3116 A 70F3116 A1 6 Timer input timing TA 40 to 85 C uPD70F3116 70F3116 A TA 40 to 110 C uPD70F3116 A1 Vpp3 CVDD 3 0 to 3 6 V VDD5 5 V 0 5 V Vss3 Vss5 CVss 0 V output pin load capacitance CL 50 pF TE TIUDn TCUDn high low level width n 10 11 BT 10 os TIUDn TCUDn input time difference n 10 11 5T 10 pm TCLRn high low level width 64 twrcH twrcL n 10 11 2 other than for 5T 10 through input 3 n 2 for through input 2T 10 E TIn high low level width 65 wnn twriL n 2 other than 5T 10 through 3 n 2 for through input 2T 10 om Note When setting the timer 2 count clock control edge select register 0 CSEO s CESE1 bit to 1 and CESEO bit to 0 Remarks 1 T Digital filter sampling clock T can be selected by setting the following registers e When using TIUDn TCUD
24. e prior to its production Not all devices types available in every country Please check with local NEC representative for availability and additional information Document No U15299EJ1VODSOO 1st edition Date Published April 2001 N CP K Printed in Japan NEC Corporation 2001 NIEC PD70F3116 70F3116 A 70F3116 A1 ORDERING INFORMATION Part Number Package Quality Grade UPD70F3116GJ UEN 144 pin plastic LQFP fine pitch 20 x 20 Standard for general electrical equipment uPD70F3116GJ A UEN 144 pin plastic LQFP fine pitch 20 x 20 Special for high reliability electrical equipment uPD70F3116GJ A1 UEN 144 pin plastic LQFP fine pitch 20 x 20 Special for high reliability electrical equipment Please refer to Quality Grades on NEC Semiconductor Devices Document No C11531E published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications DIFFERENCES BETWEEN uPD70F3116 70F3116 A AND 70F3116 A1 In Part Number uPD70F3116 uPD70F3116 A uPD70F3116 A1 Quality grade Operating ambient 40 to 85 C 40 to 110 C temperature Ta 2 Preliminary Data Sheet U15299EJ1VODS NIEC uPD70F3116 70F3116 A 70F3116 A1 PIN CONFIGURATION TOP VIEW e 144 pin plastic LQFP fine pitch 20 x 20 UPD70F3116GJ UEN UPD70F3116GJ A UEN uPD70F3116GJ A1 UEN O ADTRG1 INTP3 P04 O ADTRGO INTP2 P03 O ESO1 INTP1 P02 O ESOO INTPO P01 O TCLR11 INTP11
25. e prior to its production No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation NEC Corporation assumes no responsibility for any errors which may appear in this document NEC Corporation does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device No license either express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Corporation or others Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits software and information in the design of the customer s equipment shall be done under the full responsibility of the customer NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits software and information While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices the possibility of defects cannot be eliminated entirely To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device customers must inc
26. e tono sw s Peev imetoa ona se e mm o Paty ne tom court tectos an we um m Remark Observe at least one of the data input hold times tuxio or throi 32 Preliminary Data Sheet U15299EJ1VODS NIEC uPD70F3116 70F3116 A 70F3116 A1 c Read cycle CLKOUT synchronous asynchronous 1 wait CLKOUT output 45 o as i i Es DO Ea E EL ASTB output lt 2 gt RD output lt 26 gt lt 35 gt 52 lt 53 gt 52 gt lt 53 lt 37 gt 96 Lo less gt p WAIT input N lt 31 gt p lt 33 gt lt 32 gt lt 34 gt Remark LWR and UWR are high level Preliminary Data Sheet U15299EJ1VODS 33 NEC PD70F3116 70F3116 A 70F3116 A1 d Write cycle CLKOUT synchronous asynchronous 1 wait CLKOUT output lt 45 gt A16 to A23 output B ADO to AD15 I O Address lt 47 gt lt 16 gt lt 17 gt ASTB output La ea el lt 48 gt lt 24 gt lt 28 gt lt 48 gt lt 21 gt lt 29 gt al is lt 30 gt LWR output UWR output lt 35 gt lt 52 gt 532 lt 52 gt 53 gt lt 37 gt lt 36 gt lt 38 gt i WAIT input lt 31 gt lt 33 gt lt 32 gt lt 34 gt Remark RD is high level 34 Preliminary Data Sheet U15299EJ1VODS NIEC uPD70F3116 70F3116 A 70F3116 A1 e Bus hold C
27. eliminary Data Sheet U15299EJ1VODS e EC PD70F3116 70F3116 A 70F3116 A1 2 3 Input External maskable interrupt request input and timer 10 external capture P11 TCUD10 pm trigger input P12 TCLR10 Input External maskable interrupt request input and timer 11 external capture P14 TCUD11 mo a trigger input P15 TCLR11 INTP20 Input External maskable interrupt request input and timer 2 external capture INTP21 trigger input P20 T12 P21 TO21 P22 TO22 P23 TO23 P24 TO24 P2S TCLR2 Input External maskable interrupt request input and timer 3 external capture P26 TIS TCLR3 Output Serial transmit data output 3 wire to CSIO and CSI1 P41 SO1 4 SIO Input Serial transmit data input 3 wire to CSIO and CSI 1 4 SI1 4 SCKO I O 4 SCK1 4 3 3 3 Serial receive data input to UARTO to UART2 P30 P32 P35 I O UART1 and UART2 serial clock I O P34 P37 Output FCAN serial transmit data output Input FCAN serial receive data input Input Analog input to A D converter 0 I U U al 0 0 OO Serial clock I O 3 wire to CSIO and CSI1 0 NO Output Serial transmit data output to UARTO to UART2 v w la 0 O Input ASCK2 P47 P46 ANIOO to ANIC7 ANI10 to ANI17 ADTRGO ADTRG1 Non maskable interrupt request input MODEO Specifies V850E IA1 operation mode PO3 INTP2 PO4 INTP4 Input External trigger input to A D converter OJO il 0 lda IA IX SSL 3 16610195 310 XII
28. f Vr pulses shown in Table 3 1 when selecting the communication mode Table 3 1 Communication Modes SOO serial data output SIO serial data input SCKO serial clock input Handshake supporting CSI SOO serial data output SIO serial data input SCKO serial clock input PDHO signal for handshake UARTO TXDO serial data output RXDO serial data input Figure 3 1 Communication Mode Selection Format RESET input Preliminary Data Sheet U15299EJ1VODS 17 NIEC uPD70F3116 70F3116 A 70F3116 A1 3 2 Flash Memory Programming Functions Flash memory programming is performed by transmitting and receiving commands and data according to the selected communication mode Table 3 2 shows the main flash memory programming functions Table 3 2 Main Flash Memory Programming Functions Erases the contents of the entire memory Erases memory contents 128 KB at a time Batch blank check Checks whether the entire memory has been erased Writes data to flash memory based on the write start address and the number of bytes to be written Batch verify Compares the contents of the entire memory with the input data 3 3 Connecting Dedicated Flash Programmer The connection of the dedicated flash programmer to the uPD70F3116 differs depending on the communication mode The connection diagrams for each mode are shown below Figure 3 2 Connection of Dedicated Flash Programmer for UARTO Mode Dedicated flash programmer uPD70F3
29. g us word time 20 us 1 word 4 bytes Note 6 Number of rewrites per area CERWR 1 erase 1 write after Count area erase 1 rewrite Note 7 Notes 1 The recommended setting value of the step erase time is 0 4 s 2 The prewrite time prior to erasure and the erase verify time write back time are not included 3 The recommended setting value of the write back time is 1 ms 4 Write back is executed once by the issuance of the write back command Therefore the retry count must be the maximum value minus the number of commands issued 5 The recommended setting value of the step writing time is 20 us 6 100 us is added to the actual writing time per word The internal verify time during and after the writing is not included 7 When writing initially to shipped products it is counted as one rewrite for both erase to write and write only Example P Write E Erase Shipped product P E gt P E P 3 rewrites Shipped product gt E gt P5 E gt P gt ESP 3 rewrites Remarks 1 When the PG FP3 is used a time parameter required for writing erasing by downloading parameter files is automatically set Do not change the settings unless otherwise specified 2 Area O 00000H to 1FFFFH area 1 20000H to 3FFFFH Preliminary Data Sheet U15299EJ1VODS 45 NEC uPD70F3116 70F3116 A 70F3116 A1 Serial Write Operation Characteristics TA 20 to 85 C Vons CVpp 3 0 to 3 6 V Vpps 5 V 40 5 V Vss3 Vsss
30. humidifier should be used It is recommended to avoid using insulators that easily build static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with semiconductor devices on it 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note No connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins itis possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Inputlevels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to Voo or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must be judged device by device and related specifications governing the devices 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note Power on does not necessarily define initial status of MOS device Production process of MOS does not define the initial operation status of the device Immediately after the power source is turned ON the devices with reset
31. l 02 66 75 41 Fax 02 66 75 42 99 NEC Electronics Germany GmbH Benelux Office Eindhoven The Netherlands Tel 040 2445845 Fax 040 2444580 NEC Electronics France S A Velizy Villacoublay France Tel 01 3067 5800 Fax 01 3067 5899 NEC Electronics France S A Madrid Office Madrid Spain Tel 091 504 2787 Fax 091 504 2860 NEC Electronics Germany GmbH Scandinavia Office Taeby Sweden Tel 08 63 80 820 Fax 08 63 80 388 Preliminary Data Sheet U15299EJ1VODS NEC Electronics Hong Kong Ltd Hong Kong Tel 2886 9318 Fax 2886 9022 9044 NEC Electronics Hong Kong Ltd Seoul Branch Seoul Korea Tel 02 528 0303 Fax 02 528 4411 NEC Electronics Singapore Pte Ltd Novena Square Singapore Tel 253 831 1 Fax 250 3583 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 2719 2377 Fax 02 2719 5951 NEC do Brasil S A Electron Devices Division Guarulhos SP Brasil Tel 11 6462 6810 Fax 11 6462 6829 J01 2 51 NEC uPD70F3116 70F3116 A 70F3116 A1 Reference document Electrical Characteristics for Microcomputer U151704J ete Note This document number is that of the Japanese version V850E IA1 and V850 Family are trademarks of NEC Corporation The information contained in this document is being issued in advance of the production cycle for the device The parameters for the device may change before final production or NEC Corporation at its own discretion may withdraw the devic
32. n and TCLRn n 10 11 the following cycles can be selected by setting the NRCn1 and NRCn0 bits of timer n noise elimination time select register NRCn When fx 2 is selected for the timer 1n basic clock fx 2 fx 4 fx 8 fx 16 When fx 4 is selected for the timer 1n basic clock fx 4 fx 8 fx 16 fx 32 e When using TCLRn and Tin n 2 the following cycles can be selected by setting the PRM2 bit of the timer 1m timer 2m clock select register PRMO2 m 0 1 When fx 2 is selected for the timer 2n basic clock fx 2 When fx 4 is selected for the timer 2n basic clock fx 4 e When using TCLRn and Tin n 3 the following cycles can be selected by setting the NRC31 and NRC30 bits of timer 3 noise elimination time select register NRC30 When fx is selected for the timer 3 basic clock fx 2 fx 4 fx 8 fx 16 When fx 2 is selected for the timer 3 basic clock fx 4 fx 8 fx 16 fx 32 2 fx Internal system clock frequency TIUDm input TCUDm input TCLRn input lt 65 gt lt 65 gt TIx input Remark m 10 11 n 10 11 2 3 x 2 3 Preliminary Data Sheet U15299EJ1VODS 37 NIEC PD70F3116 70F3116 A 70F3116 A1 7 Timer operating frequency TA 40 to 85 C uPD70F3116 70F3116 A TA 40 to 110 C uPD70F3116 A1 Vpp3 CVDD 3 0 to 3 6 V VDD5 5 V 40 5 V Vss3 Vss5 CVss 0 V output pin load capacitance CL 50 pF Symbol Conditions MN gt TMOO TMO1 operating f
33. nput voltage AVREF AVRrero pin 0 5 to Vpps 0 5 AVREF1 pin 0 5 to AVpp 0 5 Output current low lot Per pin for TOOOO to TOOO5 and TOO10 to TO015 Per pin other than for TOOOO to 4 0 TOO005 and TO010 to TOO15 lt I lt X lt I lt X lt I lt lt I lt lt I lt Note CLK DBG SYNC ADO DBG to AD3 DBG pins gt Output current high Operating ambient temperature A 312183 3 3 Cautions 1 Do not directly connect output or I O pins of IC products to each other or to Vpp Vcc and GND Open drain pins or open collector pins however can be directly connected to each other Direct connection of the output pins between an IC product and an external circuit is possible if the output pins can be set to the high impedance state and the output timing of the external circuit is designed to avoid output conflict 2 Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded The ratings and conditions shown below for DC characteristics and AC characteristics are within the range for normal operation and quality assurance 20 Preliminary Data Sheet U15299EJ1VODS NIEC uPD70F3116 70F3116 A 70F3116 A1 Capacitance Ta 25 C V
34. ons Vpps Vss3 Vsss 0 V Symbol Input capacitance fo 1 MHz Pas RM I O capacitance Unmeasured pins returned to O V o 45 ov Output capacitance 1 fe Operating Conditions Operation Mode Internal System Clock Frequency fx Operating Ambient Power Supply Voltage Direct mode uPD70F3116 70F3116 A 4 to 25 MHz 40 to 85 C 3 3 V 0 3 V 5 0 V 0 5 V uPD70F3116 A1 4 to 16 MHz 40 to 110 C 3 3 V 40 3 V 5 0 V 0 5 V PLL mode uPD70F3116 70F3116 A 4 to 50 MHz 40 to 85 C 3 3 V 0 3 V 5 0 V 0 5 V uPD70F3116 A1 4 to 32 MHz 40 to 110 C 3 3 V 40 3 V 5 0 V 40 5 V Caution When interfacing to the external devices using the CLKOUT signal make the internal system clock frequency fx 32 MHz or lower Preliminary Data Sheet U15299EJ1VODS 21 NIEC uPD70F3116 70F3116 A 70F3116 A1 Recommended Oscillator a Ceramic resonator or crystal resonator connection Ta 40 to 85 C uPD70F3116 70F3116 A Ta 40 to 110 C uPD70F3116 A1 Cautions 1 Connect the oscillator as close to the X1 and X2 pins as possible 2 Do not wire any other signal lines in the area indicated by the broken lines 3 For the resonator selection and oscillator constant customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation b External clock input X2 Open A High speed CMOS inverter O External clock Cautions 1 Connect the high spee
35. onverter 1 Positive power supply for A D converter AVss N DD CVss N DDS Vss5 Ground potential for peripheral interface Ground pin for internal CPU Input Debugging interface clock input 3 V interface Input Debugging interface command synchronization input 3 V interface Vss3 CLK_DBG SYNC ADO_DBG AD1_DBG AD2 DBG AD3_DBG TRIG_DBG 3 V positive power supply pin for internal CPU O Command interface input for debugging 3 V interface Output Address match trigger signal output for debugging 3 V interface oo Preliminary Data Sheet U15299EJ1VODS 1 e EC PD70F3116 70F3116 A 70F3116 A1 2 3 Pin I O Circuits and Recommended Connection of Unused Pins The I O circuit type of each pin and recommended connection of unused pins are shown in Table 2 1 The I O circuit configuration of each type is schematically shown in Figure 2 1 It is recommended that 1 to 10 kQ resistors be used when connecting to Voos Vsss CVpp CVss or AVss via a resistor Table 2 1 Types of Pin I O Circuits and Recommended Connection 1 2 I O Circuit Type Recommended Connection Connect directly to Vsss P 5 POO NMI PO1 ESOO INTPO PO2 ESO1 INTP1 POS ADTRGO INTP2 POA ADTRG1 INTP3 POS INTP4 to PO7 INTP6 4 P10 TIUD10 TO10 5 AC Input Independently connect to Voos or Vsss via a resistor P11 TCUD10 INTP100 Output Leave open P12 TCLR10 INTP101 P13 TIUD11 TO11 P14 TCUD11 INTP110 P15 TCLR11 INTP111 P20
36. orporate sufficient safety measures in its design such as redundancy fire containment and anti failure features NEC devices are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application The recommended applications of a device depend on its quality grade as indicated below Customers must check the quality grade of each device before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems life support systems or medical equipment for life support etc The quality grade of NEC devices is Standard unless otherwise specified in NEC s Data Sheets or Data Books If customers intend to use NEC devices for applications other than those specified for Standard quality grade they should contact an NEC sales representative in advance M5 98 8
37. phisticated internal interrupt controller Real time pulse unit suitable for control applications e 16 bit timers for 3 phase sine wave PWM inverter control 2 ch e 16 bit up down counter timers for 2 phase encoder input 2 ch e 16 bit general purpose timer counters 2 ch e 16 bit general purpose timer event counter 1 ch e 16 bit interval timer 1 ch APPLICATIONS UPD70F3116 Consumer appliances inverter air conditioners etc Industrial machines motor control general purpose inverters etc uPD70F3116 A 70F3116 A1 Electrical equipment electric power steering electric car control etc O O D O O O O Powerful serial interface with dedicated on chip baud rate generator e Asynchronous serial interfaces 3 ch e Clocked serial interfaces 2 ch Automotive LAN FCAN controller 1 ch NBD Non Break Debug function e RAM monitor function e Event detection function Clock generator 10 bit resolution A D converter 8 inputs x 2 circuits DMA controller 4 ch Power saving functions Can be replaced with mask ROM incorporated uPD703116 703116 A or 703116 A1 for mass production Unless otherwise specified the uPD70F3116 is used in this document as the representative product The information contained in this document is being issued in advance of the production cycle for the device The parameters for the device may change before final production or NEC Corporation at its own discretion may withdraw the devic
38. requency To 40 C lt Ta 85 C TM10 TM11 operating frequency ny nl TH mu epg feawney Te e TM30 operating frequency nm fe fue 8 CSI timing 1 2 a Master mode TA 40 to 85 C uPD70F3116 70F3116 A TA 40 to 110 C uPD70F3116 A1 Vpp3 CVDD 3 0 to 3 6 V VDD5 5 V 0 5 V Vss3 Vss5 CVss 0 V output pin load capacitance CL 50 pF Parameter Conditions SCKn cycle tcysk1 200 SCKn high level width twsk1H 0 5tcysk1 25 SCKn low level width twskaL 0 5tcysk1 25 Sin setup time to SCKnT tssisk 35 Sin hold time from SCKn7 tusksi 30 SOn output delay time from SCKnl toskso SOn output hold time from SCKnT tHskso 0 5tcysk1 20 Remark n O 1 b Slave mode TA 40 to 85 C uPD70F3116 70F3116 A TA 40 to 110 C uPD70F3116 A1 VDD3 CVDD 3 0 to 3 6 V VDD5 5 V 0 5 V Vss3 Vss5 CVss 0 V output pin load capacitance CL 50 pF Parameter Conditions SCKn cycle tcysk1 SCKn high level width twsk1H SCKn low level width tWSK1L SIn setup time to SCKnT tssisk Sin hold time from SCKn7 tusksi SOn output delay time from SCKnJ toskso SOn output hold time from SCKnT tuskso twskiH Remark n 0 1 38 Preliminary Data Sheet U15299EJ1VODS NEC uPD70F3116 70F3116 A 70F3116 A1 8 CSI timing 2 2 SCKn I O SOn output Remarks 1 The broken
39. ta Sheet U15299EJ1VODS NIEC uPD70F3116 70F3116 A 70F3116 A1 3 3 Alternate Function PDLO I O Port DL 8 16 bit I O port Input output can be specified in 1 bit units 10 Preliminary Data Sheet U15299EJ1VODS NE A uPD70F3116 70F3116 A 70F3116 A1 2 2 Non Port Pins 1 3 Alternate Function TOOOO Output Timer 00 pulse signal output TO001 TOO02 e TO003 TO004 TOO05 TOO10 Output Timer 01 pulse signal output TO011 TO012 Output Timer 10 or 11 pulse signal output or n TO21 Output Timer 2 pulse signal output TO22 P10 TIUD10 P13 TIUD11 P21 INTP21 P22 INTP22 TO23 P23 INTP23 TO24 P24 INTP24 TO3 Output Timer 3 pulse signal output P27 INTP31 ESOO Input Timer 00 or 01 output stop signal input PO1 INTPO ESO1 POZ INTP1 TIUD10 P10 TO10 TIUD11 P13 TO11 TCUD10 P11 INTP100 TCUD11 P14 INTP110 TCLR10 P12 INTP101 TCLR11 P15 INTP111 T P20 INTP20 T P26 INTP30 TCLR3 TCLR2 P25 INTP25 TCLR3 P26 INTP31 TI3 INTPO P01 ESOO INTP1 P02 ESO1 INTP2 PO3 ADTRGO INTP3 POA ADTRG1 INTP4 PO5 INTP5 INTP6 Input External count clock input to up down counter timer 10 or 11 Input Count operation switching signal to up down counter timer 10 or 11 Input Clear signal input to up down counter timer 10 or 11 N Input Timer 2 or 3 external count input Input Timer 2 or 3 clear signal input Input External maskable interrupt request input e N P Pr
40. tics TA 40 to 85 C uPD70F3116 70F3116 A Ta 40 to 110 C uPD70F3116 A1 Vons CVpp 3 0 to 3 6 V AVpp Voos 5 V 0 5 V AVss Vss3 Vsss CVss 0 V mew 9 if jm omatt am ue Famwsmew H pp ae fue omen C fs elm smweme C fm fm mos H pf 3 is mae H o pf 3 us mewew momo um Ames v anogreirncevotago Avr avec I as I ss v C t ae 1 2 mo Avo poner supo T pp 3 ma Note The uPD70F3116 incorporates two A D converters This is the rated value for one converter Remark n 0 1 44 Preliminary Data Sheet U15299EJ1VODS NIEC uPD70F3116 70F3116 A 70F3116 A1 4 2 Flash Memory Programming Mode Basic Characteristics Ta 10 to 40 C during rewrite TA 40 to 85 C except during rewrite uPD70F3116 70F3116 A Ta 40 to 110 C except during rewrite uPD70F3116 A1 Vpp3 CVpp 3 0 to 3 6 V Voos 5 V 40 5 V Vss3 Vsss CVss 0 V Symbol Operating frequency eee O E VPP supply voltage VPP1 During flash memory 8 1 prec Vee o V pp Ver low level detection detection EH 8VoD3 Vos 12Vom 2VDp3 VPPH Vpp high voltage level 7 5 8 1 vn Voos supply current lan Vee Vem 0 Ver 4 EEE Overall erase time per area When the step erase time s area 0 4 s Note 2 Write back time Number of write backs per When the write back time Count write write back command 1 ms Note 4 back command When the step writin
41. um hen capa meso ROT E fame m Daly ne fom EWR UNA E une or aaee Temm a tee use mo CET E O E e pstenahiewiwan ES wow re i aia cupdtine rom Om amos O m Dass H ES wom uem O m EE E pee roe T me pep 2 la user pw fee few mel me ae le wem mo meme ewe rm CEC E tom re Daly ne tom sares HHH fm Daly ne to BART ea E fm Peev merona onon a wow am fm E ES wow om um mm Remarks 1 T lt tcyk 2 n Number of wait clocks inserted in the bus cycle The sampling timing changes when a programmable wait is inserted 3 i Number of idle states inserted after the read cycle 0 or 1 4 Observe at least either of the data input hold time tukio or thro Preliminary Data Sheet U15299EJ1VODS 31 NIEC uPD70F3116 70F3116 A 70F3116 A1 b CLKOUT synchronous TA 40 to 85 C uPD70F3116 70F3116 A TA 40 to 110 C uPD70F3116 A1 Vpp3 CVDD 3 0 to 3 6 V VDD5 5 V 40 5 V Vss3 Vss5 CVss 0 V output pin load capacitance CL 50 pF Bays meom eae fae w e Daly ne fom ekout wasters ost m m 5 9 Paty imetoa osse ar we o Daly ine fom CLKOUTT o AS ENANA Tar tum e esmas muco fam um s fe bainaarola me rom cuxourty ww s fe Daly ima tomou eamm fr mm mm e araa ara wm a mm Fraime rom oro we s fe Fasmer e an ora o m
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