V850ES/Fx3 - Renesas Electronics
Contents
1. 00000780H Workaround Do not use the above mentioned interrupts handlers in self programming mode Customer Notification U19002EE3VOIFOO 15 Operating Precautions for V850ES FX3 No 4 Subclock selection for WT TAA TMM Specification change notice Details If both of the following conditions are met the fa 240 kHz internal oscillator clock is selected as the input clock for a timer rather than the fxr subclock Conditions e The SUBCLK bit in the option byte at address 0x7B is set to 1 in order to select the fp 240 kHz internal oscillator as clock source for the subclock operating mode e fxr subclock is selected as the input clock for the Watchtimer WT Timer AA TAA or Timer M TMM The above applies for the following timers in subclock operation mode e Watchtimer WT e Timer AA TAA only odd numbered macros of TAA are concerned if available on a specific device e g TAAn n 1 3 5 7 e Timer M TMM In other words In subclock operation mode i e subclock is selected as the CPU clock the above men tioned timers WT TAA TMM are supplied by the same clock as the CPU in this case fa rather than by a fixed fxr clock generated by the subclock oscillator 16 Customer Notification U19002EE3VOIFOO No 5 Operating Precautions for V850ES FX3 TAA TAB Anytime write delay Direction of use Details This direction of use is applicable only for updating c2. AAnCKS2 0 TABnCKS2 0 Customer Notification U19002EE3VOIFOO 17 Operating Precautions for V850ES FX3 No 5 TAA TAB Anytime write delay Direction of use There are two possible solutions for this purpose 1 Writing twice to the compare register same value two times This is a simple solution to ensure a takeover before the CPU executes the next instruction The CPU has to wait because the peripheral will generate an active wait request This solution always takes more time than required The advantage is a simple usage and short additional 4 Bytes implementation but takes a few more CPU clock cycles than required See User s Manual Appendix B for details of Register Access Times 2 Insert a minimum count of CPU clocks A simple way to wait for a few CPU clocks is to execute NOP instructions It is also possible to replace the NOP instructions by any useful code before clearing checking the interrupt flag Formula Required CPU clocks 4 x fcpu fxp1 3 Examples 1 Writing the compare register twice Valid for any possible CPU and peripheral clock configuration sth r6 TAB1CCR2 r0 st h r6 TAB1CCR2 r0 clri 7 TAB1CCIC2 r0 Clear interrupt flag TAB1CCIF2 2 Insert NOP instructions to ensure wait time fxp1 fxx 2 PRSI 1 fcpu fxx PCC 3 0 0000b sth r7 TAAOCCR1 r0 Write new compare value nop 1111 NOPs necessary nop nop nop nop nop nop nop nop nop nop clr1 7 TAAOCCIC1 r0 Clea
3. Direction of usage Boot Cluster Swapping Il Direction of usage Interrupt handling during self programming mode Specifi cation change notice Subclock selection for WT TAA TMM Specification change notice TAA TAB Anytime write delay Direction of use Code Flash and Data Flash operation Specification Change Notice a The rank is indicated by the letter appearing at the 5th position from the left in the lot number marked on each product uPD70F3384 Boot Cluster Swapping I Direction of usage Boot Cluster Swapping Il Direction of usage Interrupt handling during self programming mode Specifi cation change notice Subclock selection for WT TAA TMM Specification change notice TAA TAB Anytime write delay Direction of use Code Flash and Data Flash operation Specification Change Notice a The rank is indicated by the letter appearing at the 5th position from the left in the lot number marked on each product Customer Notification U19002EE3VOIFOO 13 Operating Precautions for V850ES FX3 uPD70F3385 Boot Cluster Swapping l Direction of usage Boot Cluster Swapping II Direction of usage Interrupt handling during self programming mode Specifi cation change notice Subclock selection for WT TAA TMM Specification change notice TAA TAB Anytime write delay Direction of use Code Flash and Data F
4. LS means hardware and or software development tools for NEC semiconductor products developed manufactured and supplied by NEC and or hardware and or software development tools supplied by NEC but developed and or manufactured by independent 3rd Party vendors worldwide as their own product or on contract from NEC Customer Notification U19002EE3VOIFOO 2 A B C D Operating Precautions for V850ES FX3 Table of Operating Precautions 5 Description of Operating Precautions 15 Valid Specitication 2404 inaron anti aagi ka caascase tees tae ks 19 Revision HISIOly ere sis ter aGecedude ode ekidans Ceti wands can ad 19 Customer Notification U19002EE3VOIFOO Operating Precautions for V850ES FX3 Customer Notification U19002EE3V0IF00 Operating Precautions for V850ES FX3 A Table of Operating Precautions V850ES FE3 uPD70F3370A Boot Cluster Swapping I Direction of usage Boot Cluster Swapping Il Direction of usage Interrupt handling during self programming mode Specifi cation change notice Subclock selection for WT TAA TMM Specification change notice TAA TAB Anytime write delay Direction of use Code Flash and Data Flash operation Specification Change Notice a Therankis indicated by the letter appearing at the 5th position from the left in the lot number marked on each product
5. NEC Customer Notification V850ES Fx3 32 Bit Single Chip Microcontroller Operating Precautions V850ES FE3 V850ES FF3 V850ES FG3 uPD70F3370A UPD70F3372 UPD70F3374 uPD70F3371 UPD70F3373 UPD70F3375 uPD70F3376A UPD70F3377A V850ES Fu3 V850ES FK3 uPD70F3378 uPD70F3383 UPD70F3379 UPD70F3384 UPD70F3380 yPD70F3385 uPD70F3381 uPD70F3382 Document No U19002EE3VOIFOO Date Published November 2009 NEC Electronics Europe GmbH Operating Precautions for V850ES FX3 DISCLAIMER The related documents in this customer notification may include preliminary versions However preliminary versions may not have been marked as such The information in this customer notification is current as of its date of publication The information is subject to change without notice For actual design in refer to the latest publications of NEC s data sheets or data books etc for the most up to date specifications of NEC PRODUCT S Not all PRODUCT S and or types are available in every country Please check with an NEC sales representative for availability and additional information No part of this customer notification may be copied or reproduced in any form or by any means without prior written consent of NEC NEC assumes no responsibility for any errors that may appear in this customer notifi cation NEC does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or ari
6. are register has to be inserted The reason for the delayed takeover of the new compare register value is the timer s internal synchronisation and the different clock supply for the CPU and peripherals The timers internal logic is clocked by the periph eral clock fxp1 The ralationship of CPU clock and clock fxp1 has to be included in the delay time calculation Conditions e Timer in Free running mode external event count mode one shot pulse mode or interval timer mode e TAAnCCRm and TABnCCRm in compare mode e Writing new compare value during timer operation e Timer value equal to compare register value while updating the compare register Example CPU Timer TAAn TABn sh CCRn old value Write new value to Compare Register terial if Timer old value seid h izati E Delay Time required for data takeover Synchronization SFR 1 p CCRn new value Clear Check interrupt flag Direction of use If the possible interrupt flag generation could influence the application operation the following direction of use can avoid the interrupt flag generation The delay time for the compare register update should be allowed to pass before clearing or checking the interrupt flag The delay time depend on the peripheral clock setting for fxp1 gt PRSI The delay time depend on the CPU clock setting for fcpu gt PCC 3 0 The delay time does NOT depend on the VSWC setting The delay time does NOT depend on the timer count clock T
7. caused by one or more of the items listed in the enclosed table of content of this customer notification for PRODUCT S supplied after the date of publication Applicable Law The law of the Federal Republic of Germany applies to all information provided by NEC to the Customer under this Operating Precaution document without the possibility of recourse to the Conflicts Law or the law of 5 July 1989 relating to the UN Convention on Contracts for the International Sale of Goods the Vienna CISG agreement Dusseldorf is the court of jurisdiction for all legal disputes arising directly or indirectly from this information NEC is also entitled to make a claim against the Customer at his general court of jurisdiction If the supplied goods information are subject to German European and or North American export controls the Customer shall comply with the relevant export control regulations in the event that the goods are exported and or re exported If deliveries are exported without payment of duty at the request of the Customer the Customer accepts liability for any subsequent customs administration claims with respect to NEC Notes 1 NEC as used in this statement means NEC Corporation and also includes its direct or indirect owned or controlled subsidiaries 2 PRODUCT S means NEC semiconductor products NEC semiconductor products means any semiconductor product developed or manufactured by or for NEC and or TOOLS TOO
8. duct Customer Notification U19002EE3VOIFOO 7 Operating Precautions for V850ES FX3 Boot Cluster Swapping I Direction of usage Boot Cluster Swapping II Direction of usage Interrupt handling during self programming mode Specifi cation change notice Subclock selection for WT TAA TMM Specification change notice TAA TAB Anytime write delay Direction of use Code Flash and Data Flash operation Specification Change Notice a The rank is indicated by the letter appearing at the 5th position from the left in the lot number marked on each product 8 Customer Notification U19002EE3VOIFOO Operating Precautions for V850ES FX3 uPD70F3377A Boot Cluster Swapping I Direction of usage Boot Cluster Swapping Il Direction of usage Interrupt handling during self programming mode Specifi cation change notice Subclock selection for WT TAA TMM Specification change notice TAA TAB Anytime write delay Direction of use Code Flash and Data Flash operation Specification Change Notice a The rank is indicated by the letter appearing at the 5th position from the left in the lot number marked on each product v Not applicable x Applicable Customer Notification U19002EE3VOIFOO 9 Operating Precautions for V850ES FX3 V850ES FJ3 HPD70F3378 Boot Cluster Swapping I Direction of usage Boot Cluster Swapping II Direct
9. he rank is indicated by the letter appearing at the 5th position from the left in the lot number marked on each product HPD70F3381 Boot Cluster Swapping I Direction of usage Boot Cluster Swapping Il Direction of usage Interrupt handling during self programming mode Specifi cation change notice Subclock selection for WT TAA TMM Specification change notice TAA TAB Anytime write delay Direction of use Code Flash and Data Flash operation Specification Change Notice a The rank is indicated by the letter appearing at the 5th position from the left in the lot number marked on each product Customer Notification U19002EE3VOIFOO 11 Operating Precautions for V850ES FX3 HPD70F3382 Boot Cluster Swapping l Direction of usage Boot Cluster Swapping II Direction of usage Interrupt handling during self programming mode Specifi cation change notice Subclock selection for WT TAA TMM Specification change notice TAA TAB Anytime write delay Direction of use Code Flash and Data Flash operation Specification Change Notice a The rank is indicated by the letter appearing at the 5th position from the left in the lot number marked on each product v Not applicable x Applicable 12 Customer Notification U19002EE3VOIFOO Operating Precautions for V850ES FX3 V850ES FK3 uPD70F3383 Boot Cluster Swapping I
10. ion of usage Interrupt handling during self programming mode Specifi cation change notice Subclock selection for WT TAA TMM Specification change notice TAA TAB Anytime write delay Direction of use Code Flash and Data Flash operation Specification Change Notice a The rank is indicated by the letter appearing at the 5th position from the left in the lot number marked on each product HPD70F3379 Boot Cluster Swapping I Direction of usage Boot Cluster Swapping II Direction of usage Interrupt handling during self programming mode Specifi cation change notice Subclock selection for WT TAA TMM Specification change notice TAA TAB Anytime write delay Direction of use Code Flash and Data Flash operation Specification Change Notice a The rankis indicated by the letter appearing at the 5th position from the left in the lot number marked on each product 10 Customer Notification U19002EE3VOIFOO Operating Precautions for V850ES FX3 uPD70F3380 Boot Cluster Swapping I Direction of usage Boot Cluster Swapping Il Direction of usage Interrupt handling during self programming mode Specifi cation change notice Subclock selection for WT TAA TMM Specification change notice TAA TAB Anytime write delay Direction of use Code Flash and Data Flash operation Specification Change Notice a T
11. lash operation Specification Change Notice a The rank is indicated by the letter appearing at the 5th position from the left in the lot number marked on each product v Not applicable x Applicable 14 Customer Notification U19002EE3VOIFOO Operating Precautions for V850ES FX3 B Description of Operating Precautions No 1 Boot Cluster Swapping I Direction of usage Details When modifying the Code Flash while the boot cluster swapping is enabled use the single voltage flash self programming library available V1 20 or later When executing on chip debugging by connecting a NWIRE emulator use the EXEC dll version V1 81 or later No 2 Boot Cluster Swapping Il Direction of usage Details On the PG FP4 or PG FP5 Flash Programmer before modifying the Code Flash while the boot cluster swap ping is enabled issue the ChipErase Command Read of data in swapped state will return the data in the unswapped stated thus the addresses of data in the swapped area are wrong No 3 Interrupt handling during self programming mode Specification change notice Details When the device is in self programming mode the following interrupt handlers will not be executed and the related interrupts will not be serviced Name Source Handler address INTUD6S UARTD6 status interrupt 00000720H INTUD7S UARTD7 status interrupt 00000750H INTAD1 A D1 conversion completion
12. n change notice TAA TAB Anytime write delay Direction of use Code Flash and Data Flash operation Specification Change Notice a The rank is indicated by the letter appearing at the 5th position from the left in the lot number marked on each product v Not applicable x Applicable 6 Customer Notification U19002EE3VOIFOO Operating Precautions for V850ES FX3 V850ES FG3 uPD70F3374 Boot Cluster Swapping I Direction of usage Boot Cluster Swapping Il Direction of usage Interrupt handling during self programming mode Specifi cation change notice Subclock selection for WT TAA TMM Specification change notice TAA TAB Anytime write delay Direction of use Code Flash and Data Flash operation Specification Change Notice a The rank is indicated by the letter appearing at the 5th position from the left in the lot number marked on each product HPD70F3375 Boot Cluster Swapping I Direction of usage Boot Cluster Swapping Il Direction of usage Interrupt handling during self programming mode Specifi cation change notice Subclock selection for WT TAA TMM Specification change notice TAA TAB Anytime write delay Direction of use Code Flash and Data Flash operation Specification Change Notice a Therankis indicated by the letter appearing at the 5th position from the left in the lot number marked on each pro
13. ompare registers during timer operation with anytime write mechanism The time for the takeover of the new Compare value to the Compare register has to be taken into account regarding to the interrupt flag generation The interrupt flag could be set during the delayed takeover of the compare value This could happen if the old compare value matches the timer counter This will set the inter rupt flag even when the CPU already wrote a new value to the compare register TAAnCCRm and TABnCCRm register rewrite is possible during timer operation but the write method any time write or reload differs depending on the mode The anytime write method is only possible in following modes Free running mode external event count mode one shot pulse mode and interval timer mode PWM mode amp external trigger pulse output mode use the reload mechanism Rewriting the value of the compare register is enabled during timer operation and a value can be written to the register at any time when the value to be compared is written to the register it is synchronized with the internal clock and compared with the value of the 16 bit counter Depending on the application requirements the possible interrupt flag generation after updating the compare register value could influence the application operation The time for updating the compare register has to be taken into account If the interrupt should be reset by software a certain delay after writing to the comp
14. r interrupt flag TAAOCCIF1 No 6 Code Flash and Data Flash operation Specification Change Notice Details Before starting any operation e g write erase verify in Code or Data Flash it is mandatory to ensure that no other operation beside read in either Code or Data Flash is in progress 18 Customer Notification U19002EE3VOIFOO Operating Precautions for V850ES FX3 C Valid Specification November 2007 U17793EE2V2UM00 V850ES Fx3 Hardware Users Manual April 2004 U15943EJ3VOUMOO V850ES Architecture Users Manual D Revision History Date published Document No Comment November 2007 U19002EE1V0IF00 Initial release April 2008 U19002EE1V1IFOO Added No 3 for FK3 devices April 2008 U19002EE1V2IF00 Added information for uPD70F3378 uPD70F3381 uPD70F3382 August 2008 U19002EE2V1IF00 Added No 4 April 2009 U19002EE2V21F00 Added No 5 November 2009 U19002EE3VOIFOO Added No 6 Customer Notification U19002EE3VOIFOO 19 20 Operating Precautions for V850ES FX3 Customer Notification U19002EE3VOIFOO
15. sing from the use of NEC PRODUCT S listed in this customer notification or any other liability arising from the use of such PRODUCT S No license express implied or otherwise is granted under any patents copyrights or other intellectual prop erty rights of NEC or others Descriptions of circuits software and other related information in this customer notification are provided for illustrative purposes of PRODUCT S operation and or application examples only The incorporation of these circuits software and information in the design of customer s equipment shall be done under the full responsibility of customer NEC assumes no responsibility for any losses incurred by cus tomers or third parties arising from the use of these circuits software and information While wherever feasible NEC endeavors to enhance the quality reliability and safe operation of PROD UCT S the customer agree and acknowledge that the possibility of defects and or erroneous thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects and or errors in PRODUCT S the customer must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features The customer agrees to indemnify NEC against and hold NEC harmless from any and all consequences of any and all claims suits actions or demands asserted against NEC made by a third party for damages
16. uPD70F3371 Boot Cluster Swapping I Direction of usage Boot Cluster Swapping Il Direction of usage Interrupt handling during self programming mode Specifi cation change notice Subclock selection for WT TAA TMM Specification change notice TAA TAB Anytime write delay Direction of use Code Flash and Data Flash operation Specification Change Notice a The rank is indicated by the letter appearing at the 5th position from the left in the lot number marked on each product v Not applicable x Applicable Customer Notification U19002EE3VOIFOO 5 Operating Precautions for V850ES FX3 V850ES FF3 uPD70F3372 Boot Cluster Swapping I Direction of usage Boot Cluster Swapping II Direction of usage Interrupt handling during self programming mode Specifi cation change notice Subclock selection for WT TAA TMM Specification change notice TAA TAB Anytime write delay Direction of use Code Flash and Data Flash operation Specification Change Notice a The rank is indicated by the letter appearing at the 5th position from the left in the lot number marked on each product HPD70F3373 Boot Cluster Swapping I Direction of usage Boot Cluster Swapping II Direction of usage Interrupt handling during self programming mode Specifi cation change notice Subclock selection for WT TAA TMM Specificatio
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