6244 LFA User Manual - Digalog Systems, Inc.
Contents
1. 26 02 DAC Programming Register Bit Definitions 26 04 Power Supply Control Register Bit Definition 28 05 Power Supply Monitor Bit Definitions esses 28 06 NML Detection Control Register Bit Definitions 29 07 Power Supply Fault Detect Bit Definitions 29 08 DAC Load Strobe VOH eeen 30 09 DAC Load Strobe VOL ecce 30 OA DAC Programming Clock Enable DAC Load Strobe VIH 30 OB DAC Load Strobe VIL ecce 30 40 Relay Data Register Bit Definitions ss 30 41 Three State Control Register Bit Definitions 30 Map BIOCKA C tutes 31 42 Relay Disconnect Control Reg Bit Definitions 31 46 NML Detection Control Register Bit Definitions 31 48 Relay Disconnect Latch Bits 0 7 esssse 31 49 Relay Disconnect Latch Bits 8 15 sess 31 4A Relay Disconnect Latch Bits 16 23 32 4B Relay Disconnect Latch Bits 24 31 33 4C Relay Multiplexer Latch Bits 0 7 sssse 33 4D Relay Multiplexer Latch Bits 8 15 33 4E Relay Multiplexer Latch Bits 16 23 33 4F Relay Multiplexer2. High DAC s Enables serial program DAC s Disables serial progra DAC s Enables serial program Resets all DAC outputs to zero volts Disables fault detection latch and allows programming of the shutdown m m m m m m m m m ing of t ming of ing of t ming of ing of t ming of ing of t ming of Control of Nibbles 3 0 Control of Nibbles 3 0 he Level Output the Level Output he Level Output Low the Level Output Low he Threshold Input High the Threshold Input he Threshold Input Low the Threshold Input Low ing of all DAC s Disables Fault EPIO 6244 Logic Family Adapter 6244 LFA Power Supply Control Register 0 Enables fault detection latch and Fault shutdown Write mo a Three State Control Register p poese ps Nt Daeron Comi Regnier NMI Detection ConiRege m eese exem 0 bs pacim mmegon b Dac toa suate wou pa DAC toad srove DAC Progamming nck Fable m emaemeon 0000 Fault shutdown disconnects power supplies clears power supply EPIO 6244 Logic Family Adapter 27 6244 LFA control register if any of the Power Supply Monitor bits are low or os os ba os o2 oo BDIR BDIR BDIR BDIR Fixed3 Fixed2 Fixed1 Fixed7 Fixed6 Fixed5 Fixed4 Tf Fault shutdown occurs the fault detection latch circuit identifies the supply that caused the problem 04 Power Supply Control
3. SerByte The byte of data to be written to the LFA register EPIO 6244 Logic Family Adapter 17 6244 LFA Lfa6244SetLogicLevel Each 6244 LFA has four voltage reference levels that need to be set Voltage Out High VOH Voltage Out Low VOL Voltage In High VIH and Voltage In Low VIL Each of the four bytes on a 6244 LFA need to have these levels set separately there are 16 DACs on each 6244 LFA four bytes with four levels each If a channel is configured as a driver or as bi directional the VOH and VOL levels must be programmed for that byte If a channel is configured as a receiver or as bi directional the VIH and VOL levels must be programmed for that byte This functional call is used to program one of the levels on one of the bytes Therefore if all of the possible 28 channels are configured as bi directional channel numbers 28 31 can not be bi directional this call needs to be made 16 times If all 32 channels are fixed drivers this call only needs to be made eight times to set the VOH and VOL levels on the four bytes If all 32 channels are fixed receivers this call only needs to be made eight times to set the VIH and VIL levels on the four bytes Visual Basic Declaration I a6244 bas Public Sub Lfa6244SetLogicLevel ByVal BdNum As Integer ByVal ByteNum As Integer ByVal VoltLevSel As Integer ByVal Volts As Double CVI Declaration dli6244 h u int32 DLI6244 LFA6244SetLogicLevel int16 bdNum int16 byteNum int16 v
4. and references will be shut down Therefore there will be bits set in the third byte of the returned status The third byte of the returned status contains which on board supplies are shut down Most likely there will be more than one This is because once the on board supplies are up and then a fault occurs the fault will cause the rails and references to shut down The supply that caused the fault is contained in the second byte of the returned status The supplies that are down is returned just for information purposes Visual Basic Declaration I a6244 bas Public Sub Lfa6244Status ByVal BdNum As Integer ByRef Status as Long CVI Declaration dli6244 h u int32 DLI6244 LFA6244Status int16 bdNum int32 status EPIO 6244 Logic Family Adapter 23 6244 LFA Call Lfa6244Status ByVal BdNum As Integer ByRef Status As Long 24 Status g mo QS UNITS The EPIO board number associated with the 6244 LFA that is going to be accessed to 7 The returned status Each bit is defined below Description LFA ID 1 LFA ID 2 Reserved Reserved Reserved Reserved Reserved Reserved 5 Volt over current for LVDS channels 0 15 caused this fault 5 Volt over current for LVDS channels 16 31 caused this fault 9 Volt reference caused this fault 9 Volt reference caused this fault 9 Volt rail caused this fault 9 Volt rail caused this fault Vcc over current caused this fault Reserved 5 Volt for LVDS
5. te a ee p ene die ede RU 2 5ns maximum Receiver Input Voltage 13 0Volt Range Maximum 2 5V away from Rail Receiver Propagation Delay ani tourene i ne o tete EE i 24ns maximum Receiver Propagation Delay NML csssseseeeeeeee eee 46 5ns maximum RECEIVER SKEW sar nt i d i cti RR DP era edits 2 5ns maximum Receiver Threshold Precision ssssee 9 8mV programmable precision Receiver Threshold Accuracy Uncalibrated sess 120mV maximum System Clocking grege EA Asynchronous no on board latches Serial Interface Clock Frequency 3 oct ete e itte t a i E Eae 500 kHz ClockcVoltages t ree e b OP RR HO p eI 0 0 to 5 0 Volts SerialiData Voltage i nette eee Pte tet 0 0 to 5 0 Volts EPIO 6244 Logic Family Adapter 25 6244 LFA Address Maps Map 1 Block 0 01 Three State Control Register Bit Definitions BDI BDI R FIXI R FIXI D D im P im a FIXI FIXI 7 4 Thr Stat 1 Bi directional 0 Fixed receiver Thr Stat 1 Fixed driver O0 Not a fixed driver 02 DAC Programming Register Bit Definitions ENVOH 1 0 ENVOL 1 0 ENVIH 1 0 ENVIL 1 0 DACCLR 1 0 PSCONT 1 26 Enables serial program High DAC s Disables serial progra High DAC s Enables serial program DAC s Disables serial progra DAC s Enables serial program DAC s Disables serial progra
6. to 0 volts RAILVPWR 1 Rail voltage input is greater than 5 volts O0 Rail voltage input is less than or equal to 5 RAILPWRI RAILPWR 15VPWR H 15VPWR 5USB 5USA volts RAILVPWR 1 Rail voltage input is less than 0 volts 0 Rail voltage input is greater than or equal to 0 volts VCCOC 1 5 Volt input is drawing less than 0 9 amps 0 5 Volt input is drawing greater than 0 9 amps over current Note A zero on any bit indicates a possible fault condition 06 NML Detection Control Register Bit Definitions ENNML 3 0 NML Control of Nibbles 3 0 ENNML 1 NML detection Enabled O NML detection Disabled 07 Power Supply Fault Detect Bit Definitions 5BUSAOC 1 LVDS circuitry is drawing less than 0 9 amps 0 LVDS circuitry is drawing greater than 0 9 amps or os os ba os D2 NU VCCOC RAILPWRHRAILPWRI 15VPWR j 15VPWRH5BUSBOCH5BUSAOQ over current 5BUSBOC 1 Adjustable I O logic circuitry is drawing less than 0 9 amps 0 Adjustable I O logic circuitry is drawing greater than 0 9 amps over current 15VPWR 1 15 Volt input is greater than 5 volts 0 15 Volt input is less than or equal to 5 volts 15VPWR 1 15 Volt input is less than 0 volts 0 15 Volt input is greater than or equal to 0 volts TRAILVPWR 1 Rail voltage input is greater than 5 volts EPIO 6244 Logic Family Adapter 29 6244
7. 4 LFA are the serial read and write calls These calls allow the EPIO to communicate to the 6244 LFA through the serial interface on the Patchboard The configuration functional calls use the serial calls to configure the 6244 LFA but the serial communication calls can also be used to configure user added capabilities to an LFA EPIO 6244 Logic Family Adapter 9 6244 LFA Lfa6244CalLogicLevel This functional call is used when calibrating one of the eight driver output levels or one of the eight receiver threshold levels on a 6244 LFA This routine is separate from Lfa6244SetLogicLevel because it will accept a bit count instead of a voltage By using this call the DAC can be set to a bit count and the output voltage measured Therefore the input bit counts and the measured voltages can be used to determine the DACs gain in Bits Volt and the offset in Bits Visual Basic Declaration I a6244 bas Public Sub Lfa6244CalLogicLevel ByVal BdNum As Integer ByVal ByteNum As Integer ByVal VoltLevSel As Integer ByVal DacBits As Integer CVI Declaration dli6244 h u int32 DLI6244 LFA6244CalLogicLevel int16 bdNum int16 byteNum int16 voltLevSel int16 DACBits Call Lfa6244CalLogicLevel BdNum ByteNum VoltLevSel DacBits BdNum The EPIO board associated with the RFALLFA that is going to accessed O0 to7 ByteNum The byte number of the DAC whose gain and offset is going to be stored 0 to3 VoltLevSel Selects which voltage re
8. 6244 LFA User Manual rsion Table of Contents ZA EPA uobis bee pae uade eben veri wenn dn Mac e liu iniguuse EO UP aba Mie ee RR QURE 5 EPICI B2 44 LFA irae Ta EE ER EEEE PEE EEAO EERE 7 mie rr esien EONA 7 OVOIVIEW seca es his anani Nei wi EEEE E EE CESE AEE REES 7 Adjustable Voltages ns i pei e eia E ORI A RE EEEE EE 7 Digital Interface sorarken aro e E E EE ER N 7 Configuration Calibration and Selftest octo tret ie 7 Power Considerations seemed dort oriee s UR eee Deu aee E HER 8 Producbmelt3ee aros racket p cpu QU DaP ROAD DER DIEN MD 8 6244 LEA PurscttonalCalles sedes ciertos tt ratdtiriate od nva C pa Cea ordin 9 lfa6244Caltogiclev MEC 10 Liao 244ChannelSetU p v ascen REP docendo Reni EEN 11 Hao 74 AR SLAY a sepoeiiteodper DARNOS GRUPO EAD EA DATI RUP UTI RLON 13 Li362 44ResetLogl CLEVE rrie inr is umbo d i s 15 Wa 24 AS eral RG i enr taris QM ese RIED aet ose ka aH to aub 16 Ei3624456Hta WEIT teer orien tue attach decode ad ute dens 17 Late 2 4A Ctl OSI sape rser ei alpes E aH RE CA REat dp QU Pre DESDE 18 Liao 445etbogtelevelGali ceiespedirie i ep icc ocn nd b IR Pe Rupe 20 Lab 24456 ID ORTIB snas Mira centr e Hep e e a EFE D EDU 22 Bri AAS CAL US m m 23 Board Specifications asi uo pe PERO I PARURE QURE CE ORI oun D emp wea 25 Address Maps d 26 Mapes Block D syntes ienee e P Nope rumes 26 01 Three State Control Register Bit Definitions
9. In Low Il Wn Ao Gain The gain to use for this voltage reference on this byte for this LFA in Bits Volt Offset The offset to use for this voltage reference on this byte for this LFA in Bits EPIO 6244 Logic Family Adapter 21 6244 LFA Lfa6244SetupConfig This routine is used to configure a 6244 LFA based on the information contained in the configuration file generated by the EPIO Pattern Editor This call takes the place of Lfa6244ChannelSetup Lfa6244SetLogicLevel and Lfa6244Relay The configuration options handled by this routine are LFA channel directions drive or receive Logic Levels driver outputs amp receiver thresholds Closes the relays between the LFA and DUT connects the LFA to the DUT Disables NML Detection Before configuring the 6244 LFA this functional call also enables the onboard power Therefore the 5 volt and 9 volt power supplies must be turned on and applied to the 6244 LFA before using this call Because the configuration file does not contain information for the NML Detection it is always disabled The user will have to enable NML Detection after calling this function Visual Basic Declaration lfa6244 bas Lfa6244SetupConfig ByVal ConfigFileName As String CVI Declaration dli6244 h u int32 DLI6244 LFA6244SetupConfig char configFilename Call Lfa6244SetupConfig ByVal ConfigFileName As String WHERE ConfigFileName The full path to the configuration file created by t
10. LFA 0 Rail voltage input is less than or equal to 5 volts RAILVPWR 1 Rail voltage input is less than 0 volts 0 Rail voltage input is greater than or equal to 0 volts VCCOC 1 5 Volt supply is drawing less than 0 9 amps 0 5 Volt supply is drawing greater than 0 9 amps over current Note A zero on any bit indicates a possible fault condition 08 DAC Load Strobe VOH Read from address 0x08 to load VOH DAC NU ENNML3 ENNML2 ENNML1 ENNMLO 09 DAC Load Strobe VOL Read from address 0x09 to load VOL DAC 0A DAC Programming Clock Enable DAC Load Strobe VIH 57 oe os NU VCCOC RAILPWRH RAILPWR 15VPWR H 15VPWR BUSBOC BUSAOQ Read from address 0x0A to load VIH DAC Write to address 0x0A to enable DAC programming clock OB DAC Load Strobe VIL Read from address OxOB to load VIL DAC 40 Relay Data Register Bit Definitions RDATA 1 Relay on 0 Relay off 41 Three State Control Register Bit Definitions BDIR FIXED 7 4 Thr State Control of Nibbles 7 4 BDIR FIXED 1 Bi directional 30 EPIO 6244 Logic Family Adapter 6244 LFA 0 Fixed receiver FIXED 3 0 Thr State Control of Nibbles 7 4 FIXED 1 Fixed driver 0 Not a fixed driver Map2 Block4 42 Relay Disconnect Control Reg Bit Definitions RMCLEAR 1 Relay Multiplexer Registers Enabled 0 Relay Multiplexer Registers Cle
11. Latch Bits 24 31 34 Recommended Power Up Sequence 6244 LFA 6244 LFA EPIO 6244 Logic Family Adapter 5 6244 LFA 6 EPIO 6244 Logic Family Adapter 6244 LFA EPIO 6244 LFA Hardware Overview The EPIO 6244 Logic Family Adapter LFA board is designed to connect the Extended Pattern Input Output EPIO board to the device under test DUT through the Digalog 2040 Series Tester s Patchboard receiver The LFA receives data from the EPIO and converts it to programmable output voltage levels Differential drivers and receivers are used on the EPIO and the LFA to drive receive data through the Patchboard Adjustable Voltages The adjustable logic levels between the LFA and the DUT can cover a 13 volt differential range The rails are set by the user but they cannot have more than an 18 volt differential There are four types of digital to analog converters DAC on the LFA to program the four I O logic levels driver voltage output high VOH driver voltage output low VOL receiver voltage input high VIH minimum and receiver voltage input low VIL maximum Each group of eight channels has its own set of user programmable I O voltages The receiver thresholds can be programmed over a voltage range that is 2 5 volts less that the upper rail and 2 5 volts more than the lower rails 13 volt differential Digital Interface The LFA supports the bi directional capabilities of the EPIO board The
12. Register Bit Definition 5BUSA 1 Switch 5 V supply to LVDS circuitry 0 Disconnect 5 V supply from LVDS circuitry 5BUSB 1 Switch to Adjustable I O logic circuitry PSCONT NU NU DACCLR ENVIL ENVIH ENVOL ENVOH 0 Disconnect 5 V supply from Adjustable I O logic cCroultf y 15VPWR 1 Switch 15 V supply to internal analog circuitry 0 Disconnect 15 V supply from internal analog circuitry 15VPWR 1 Switch 15 V supply to internal analog circuitry 0 Disconnect 15 V supply from internal analog circuitry RAILVPWR 1 Switch Rail supply to internal analog circuitry 0 Disconnect Rail supply from internal analog circuitry RAILVPWR 1 Switch Rail supply to internal analog circuitry 0 Disconnect Rail supply from internal analog circuitry 05 Power Supply Monitor Bit Definitions 5BUSAOC 1 LVDS circuitry is drawing less than 0 9 amps 0 LVDS circuitry is drawing greater than 0 9 amps over current Adjustable I O logic circuitry is drawing less than 0 9 amps 0 Adjustable I O logic circuitry is drawing greater than 0 9 amps over current 15VPWR 1 15 Volt input is greater than 5 volts 0 15 Volt input is less than or equal to 5 volts 5BUSBOC ll p 28 EPIO 6244 Logic Family Adapter 6244 LFA 15VPWR 1 15 Volt input is less than 0 volts 0 15 Volt input is greater than or equal
13. ared and Disabled untill released RDCLEAR 1 Relay Disconnect Registers Enabled 0 Relay Disconnect Registers Cleared and Disabled untill released 46 NML Detection Control Register Bit Definitions ENNML 3 0 NML Control of Nibbles 7 4 ENNML 1 NML detection Enabled O0 NML detection Disabled 48 Relay Disconnect Latch Bits 0 7 Write to address 0x48 to latch contents of Relay Data Register into Relay Disconnect Control Register Read from address 0x48 to latch contents of Relay Disconnect or ps os os os o2 pi oo on e Control Register into Relay Data Register RDATA 0 7 RELAY DISCONNECT 0 7 o e oa os p po cee sn mm om Fixed7 Fixed6 Fixed5 Fixed4 49 Relay Disconnect Latch Bits 8 15 Write to address 0x49 to latch contents of Relay Data Register into Relay Disconnect Control Register Read from address 0x49 to latch contents of Relay Disconnect Control Register into Relay Data Register EPIO 6244 Logic Family Adapter 31 6244 LFA RDATA 0 7 RELAY DISCONNECTI8 15 Maema dW m p fe i ena ope Pea Coa B E oz bs os oa Di DO RMCLEAR 4A Relay Disconnect Latch Bits 16 23 Write to address 0x4A to latch contents of Relay Data Register into Relay Disconnect Control Register Read from address 0x4A to latch contents of Relay Disconnect Control Register into Relay Data Register 32 EPIO 6244 Logic Fa
14. channels 0 15 is down 5 Volt for LVDS channels 16 31 is down 9 Volt reference is down 9 Volt reference is down 9 Volt rail is down 9 Volt rail is down Vcc is down Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved EPIO 6244 Logic Family Adapter 6244 LFA Board Specifications Digital Inputs Outputs Number leat o aede edd petto eer ee ot 32 Drivers Receivers TVBesscau itn NECS Differential Line Drivers Receivers 3 3V 50 ohm driver Analog Inputs Outputs Driver Output Voltage 0 0 0 eee eee eens 13 V range maximum 2 5V away from each rail Driver Output CUrTent 5 t ERE USER ERE R RR nae 80 mA per byte Driver Leakage CUIT6DL ite oreet nct er ist 10 0 nA per bit Driver Output Impedance 4 2 2 ip te etti Pat preis 33 Ohms maximum MEE ee e tete desea E a e TO e etg a eda Typical 12 Ohm output 15 Ohm posistor Driver Output Capacitance s peint epe eerte tH ede Fen EUR ET 34pF maximum Driver Propagation Delay inis cte rte o med der 26ns maximum Driver Disable Propagation Delay sse 45ns maximum Driver Enable Propagation Delay sssssseee nee 37ns maximum Driver Transition TIME crece pe rte Hte ic a entreprendre RES ERIR 3 2ns 13V swing typical Driver Output Precision esses 9 8mV programmable precision Driver Output Accuracy Uncalibrated ess 120mV maximum Driver SKEW esee
15. dapter 6244 LFA Lfa6244Relay This functional call is used to either connect one DUT pin to the LFA the Mux output to the fixture motherboard or connect an LFA output to the Mux pin for calibration It is also used to completely disconnect the DUT pin from both the LFA and the Mux In addition if ChanNum 1 this function can be used to disconnect all 32 of the DUT pins associated with this LFA from either the LFA the Mux or from both based on the value of State When the LFA is first powered up the DUT pins are disconnected from both the LFA and the Mux Therefore the command to connect a DUT pin to either one must be given every time the LFA is powered up By doing this the LFA does not need to be powered down every time the DUT is changed However the power to the DUT must then be controlled by relays or be separate supplies than those used by the LFA Multiple DUT pins can be connected to the LFA at once This would be the normal operation when testing a DUT with an EPIO DPIO The normal operation for using the Mux input to the fixture s motherboard would be to only connect one DUT pin to the Mux input at a time However the hardware and software allow for more than one DUT pin to be connected to the Mux at a time This is allowed for selftest purposes two or more DUT pins can be connected to each other on the bus input to the Mux Therefore if only one DUT pin is to be connected to the Mux input at a time the use
16. e Patchboard fixed supplies or UUT power supplies Supply Power Per LFA Use Minimum Typical Maximum Vcc 0 9A Digital Logic 4 75V 5V 5 25V 9 0 05A DACs and Reference 8V 9V 10V 9 0 05A DACs and Reference 8V 9V 10V Rail DUT Driver and Receiver 8V 9 10V Provide necessary output power Rail DUT Driver and Receiver 8V 9 OV Provide necessary output power Note Rail to Rail differential must be between 12VDC and 18 VDC Product Interface The LFA to DUT connections consist of several protection devices First disconnect relays are in place to break the connection with the DUT before or after a test This allows other testing to be done to each pin without removing the fixture Second posistors and SCR Diode clamps protect the LFA driver s and receivers from the DUT The pin voltage is held to the rail voltage plus about 0 7 volts Both of these devices increase the pin capacitance and or the output series resistance 8 EPIO 6244 Logic Family Adapter 6244 LFA 6244 LFA Functional Calls The functional calls associated with the EPIO s 6244 Level Logic Family Adapter 6244 LFA card gives the user the ability to configure the 6244 LFA The configuration capabilities include setting the Driver output logic levels and the Receiver threshold logic levels setting the channel direction retrieving the LFA s status and controlling the disconnect relays In addition to the functional calls that configure the 624
17. er
18. ference is going to be set to the given bit count Voltage Out High VOH Voltage Out Low VOL Voltage In High VIH Voltage In Low VIL Il Wn Ao DacBits The bit count the given reference DAC is going to be set to O to4095 10 EPIO 6244 Logic Family Adapter 6244 LFA Lfa6244ChannelSetup This functional call is used to configure 6244 LFA channels as fixed drivers fixed receivers or bi directional Two separate eight bit values are used to control the 32 channels on each board One value is used for the driver channels and the other is used for the receiver channels High logic values in the bits of the DriverEnable byte fix those channels as full time drivers High logic values in the bits of the ReceiverEnable byte fix those channels as full time receivers Channels that are specified as both drivers and receivers will be configured as bi directional The last four channel group on the 6244 LFA may only be configured as fixed drivers or fixed receivers If any channels on an LFA are bi directional then this last nibble on the LFA channels 28 31 must be configured as fixed drivers or errors will result The last four channels on each LFA control the I O direction of eight channels that are configured as bi directional although channel 31 only controls the direction of four channels A high logic bit on any control channel will cause the corresponding group of bi directional channels to drive out to the LFA A log
19. he EPIO Editor program 22 EPIO 6244 Logic Family Adapter 6244 LFA Lfa6244Status This functional call returns the status of an LFA connected to the EPIO given by BdNum The status information returned is LFA IDs which on board power supplies are down and which on board supply caused a fault If a bit is set in the returned status there is a problem See the table below to find out what the bit correlates to If the returned status is zero there is no problem The IDs are read to determine if the FPGAs are up All the FPGAs need to be power up is the 5 volts applied to the LFA There is no second step needed to bring the FPGAs up like there is to enable the on board rails and references The FPGAs need to be up before the on board rails and references can be enabled In addition reading the IDs checks the serial link between the EPIO and the LFA Please note that if there is a problem reading one of the IDs the power supplies will also report problems because they could probably not be enabled because the FPGA is not up However if there is a problem with the rails or references this could cause the FPGA to go down although this would be a slim chance The second byte of the returned status contains which on board supply faulted and caused the other supplies to shut down If there was a fault there should only be one bit set in the second byte It should be noted that if one of the supplies fault out the on board rails
20. ible eight 6244 LFA boards The gains should be stored as bits volt and the offsets as bits When the LFA DLL is loaded default values for the gain and offset are stored into the calibration structure The default values used are for a 12 bit DAC with references of 5 volts A zero volt output from the DAC is its mid point in the bit count Therefore the default value for the gain is 2 12 bits 10 volts 2 204 8 Bits Volt and the default offset is 2048 bits mid scale of a 12 bit DAC The divide by 2 has been inserted into the gain equation because there is an amplifier after each DAC with a gain of 2 which must be account for Visual Basic Declaration I a6244 bas Public Sub Lfa6244SetLogicLevelGain ByVal BdNum As Integer ByVal ByteNum As Integer ByVal VoltLevSel As Integer ByVal Gain As Double ByVal Offset As Double CVI Declaration dli6244 h u int32 DLI6244 LFA6244SetLogicLevelCain int16 bdNum int16 byteNum int16 voltLevSel double gain double offset Call Lfa6244SetLogicLevelGain BdNum ByteNum VoltLevSel Gain Offset 20 EPIO 6244 Logic Family Adapter 6244 LFA BdNum The EPIO board number associated with the RFALLFA whose gain and offset is going to be stored O0 to7 ByteNum The byte number of the DAC whose gain and offset is going to be stored O0 to3 VoltLevSel The voltage reference level to be set VOH Voltage Out High VOL Voltage Out Low VIH Voltage In High VIL Voltage
21. ic Family Adapter 15 6244 LFA Lfa6244SerialRd This functional call serially reads an eight bit value from the LFA board associated with the EPIO board given by BdNum from the LFA s offset given by Offset The eight bit value is returned in SerRetByte Visual Basic Declaration I a6244 bas Public Sub Lfa6244SerialRd ByRef SerRetByte As Byte ByVal BdNum As Integer ByVal Offset As Integer CVI Declaration dli6244 h u int32 DLI6244 LFA6244SerialRd char serRetByte int16 bdNum int16 offset Call Lfa6244SerialRd SerRetByte BdNum Offset WHERE SerRetByte The byte of data read from the LFA BdNum The number of the EPIO board connected to the LFA to be accessed O toZ Offset The register offset on the LFA board 16 EPIO 6244 Logic Family Adapter 6244 LFA Lfa6244SerialWrt This functional call serially writes an eight bit value to the LFA board associated with the EPIO board given by BdNum to the LFA s offset given by Offset The eight bit value written is in SerByte Visual Basic Declaration I a6244 bas Public Sub Lfa6244SerialWrt ByVal BdNum As Integer ByVal Offset As Integer ByVal SerByte As Byte CVI Declaration dli6244 h u int32 DLI6244 LFA6244SerialWrt int16 bdNum int16 offset char serByte Call Lfa6244SerialWrt BdNum Offset SerByte WHERE BdNum The number of the EPIO board connected to the LFA to be accessed 1 to7 Offset The register offset on the LFA board
22. ic low will disable the drivers allowing data to be received from the LFA This ability follows the RO Driver format regardless of what format may be selected elsewhere Unspecified channels will be configured as receivers It is recommended that these channels should be masked out by clearing that bit in the Mask memory Visual Basic Declaration I a6244 bas Public Sub Lfa6244ChannelSetup ByVal BdNum As Integer ByVal DriverEnable As Byte ByVal ReceiverEnable As Byte CVI Declaration dli6244 h u int32 DLI6244_LFA6244ChannelSetup int16 bdNum u_char driverEnable u_char receiverEnable Call Lfa6244ChannelSetup BdNum DriverEnable ReceiverEnable WHERE BdNum The number of the EPIO board connected to the LFA to be set O toZ EPIO 6244 Logic Family Adapter 11 6244 LFA 12 DriverEnable A logic one specifies which channels are to be enabled as drivers to the DUT Channels 0 3 Channels 4 7 Channels 8 11 Channels 12 15 Channels 16 19 Channels 20 23 Channels 24 27 Channels 28 31 Il NOUBWN OO ReceiverEnable A logic one specifies which channels are to be enabled as receivers from the DUT Channels 0 3 Channels 4 7 Channels 8 11 Channels 12 15 Channels 16 19 Channels 20 23 Channels 24 27 Channels 28 31 Il o0 U0KN Co NOTE If a bit is high in both DriverEnable and ReceiverEnable the corresponding group of four channels will be configured as Bi Directional EPIO 6244 Logic Family A
23. l 32 of the DUT pins will be disconnected from either The LFA and the Mux if State 0 The LFA if State 1 The Mux input if State 2 The LFA and the Mux if state 3 If the ChanNum parameter is 0 31 the State parameter specifies whether or not a single DUT pin should be connected to the LFA the Mux or disconnected from both Disconnect the DUT pin from the LFA and the Mux Connect the DUT pin to the LFA Connect the DUT pin to the Mux Configure for calibration close both relays If the ChanNum parameter is 1 the State parameter specifies whether all 32 of the DUT pins should be disconnected from the LFA the Mux or both Disconnect all 32 DUT pins from the LFA and the Mux Disconnect all 32 DUT pins from the LFA Disconnect all 32 DUT pins from the Mux Disconnect all 32 DUT pins from the LFA and the Mux EPIO 6244 Logic Family Adapter 6244 LFA Lfa6244ResetLogicLevel This functional call is used to reset all 16 DACs to 0 volts on the LFA connected to the EPIO board designated by the BdNum parameter The 16 DACs include the four VOH DACs four VOL DACs four VIH DACs and four VIL DACs Visual Basic Declaration lfa6244 bas Public Sub Lfa6244ResetLogicLevel ByVal BdNum As Integer CVI Declaration dli6244 h u int32 DLI6244_LFA6244ResetLogicLevel int16 bdNum Call Lfa6244ResetLogicLevel BdNum WHERE BdNum The number of the EPIO board connected to the LFA to be reset O toZ EPIO 6244 Log
24. last four channels on each LFA numbered 28 31 are used to control the three states of the driver to the DUT as well as the drivers that carry data back to the EPIO This option is user configurable per nibble on the LFA The LFA can detect no man s land NML data from the DUT by checking the outputs of the two receiver comparators window If the DUT pin voltage level is above the lower threshold but not above the upper threshold the driver that sends data back to the EPIO will be disabled The EPIO board is capable of detecting this condition and evaluating it accordingly Configuration Calibration and Selftest The EPIO and LFA communicate by a serial link It is used to enable disable the driver receivers on the LFA program the driver output voltages program the receiver threshold voltage and read the ID of the LFA It is also used to perform functional selftest routines on the EPIO to LFA connection EPIO 6244 Logic Family Adapter 7 6244 LFA Power Considerations The LFA requires power to be provided externally The 6244 LFA board needs three external voltage sources One is for the 5 volts needed for the digital circuitry on the LFA including the differential drivers and receivers The other two are for the rails needed for the adjustable level circuitry that connects to the DUT including any DACs amplifiers references and comparators used It is up to the user to supply these power sources Possible tester resources ar
25. ltiplexer Control Register Read from address Ox4F to latch contents of Relay Multiplexer Control Register into Relay Data Register RDATA 0 7 RELAY MULTIPLEXER 24 31 Recommended Power Up Sequence If not using LFA6244SetupConfig 34 EPIO 6244 Logic Family Adapter 3 6244 LFA Apply 5 Volt Power Powers FPGA s Apply 9V and Rail power to the LFA Set PSCONT bit7 at address 0x02 to enable power up Note Use masked data with previous register contents when modifying control register contents for bit wise control 4 Enable all supplies at once by writing Ox3F to address 0x04 This will apply the 15V and Rail power supplies to the internal circuitry Wait some settling time approximately 0 2 seconds Read power supply status from Power Supply Monitor Register at address 0x05 Should be Ox7F if no fault occurred Note Bit 7 is not used and should be ignored when reading the Power Supply Monitor Register 7 If fault occurs determine the source of problem at fault detection register latched at address 0x07 Clear PSCONT bit7 at address 0x02 to enable Fault shutdown protection Parts on the LFA may be damaged if an external supply is disconnected prematurely Fault shutdown disconnects all supplies if any fault condition occurs See Power Supply Monitor Register Power up sequence complete if no fault occurred EPIO 6244 Logic Family Adapter 35 6244 LFA 36 EPIO 6244 Logic Family Adapt
26. mily Adapter 6244 LFA RDATA 0 7 RELAY DISCONNECT 16 23 5 os os ba os 4B Relay Disconnect Latch Bits 24 31 Write to address 0x4B to latch contents of Relay Data Register into Relay Disconnect Control Register Read from address 0x4B to latch contents of Relay Disconnect Control Register into Relay Data Register RDATA 0 7 RELAY DISCONNECT 24 31 4C Relay Multiplexer Latch Bits 0 7 Write to address 0x4C to latch contents of Relay Data Register into Relay Multiplexer Control Register Read from address 0x4C to latch contents of Relay Multiplexer Control Register into Relay Data Register RDATA 0 7 RELAY MULTIPLEXER O 7 4D Relay Multiplexer Latch Bits 8 15 Write to address 0x4D to latch contents of Relay Data Register into Relay Multiplexer Control Register Read from address 0x4D to latch contents of Relay Multiplexer Control Register into Relay Data Register RDATA 0 7 RELAY MULTIPLEXER 8 15 4E Relay Multiplexer Latch Bits 16 23 Write to address 0x4E to latch contents of Relay Data Register into Relay Multiplexer Control Register Read from address Ox4E to latch contents of Relay Multiplexer Control Register into Relay Data Register EPIO 6244 Logic Family Adapter 33 6244 LFA RDATA 0 7 RELAY MULTIPLEXER 16 23 4F Relay Multiplexer Latch Bits 24 31 Write to address Ox4F to latch contents of Relay Data Register into Relay Mu
27. oltLevSel double volts Call Lfa6244SetLogicLevel BdNum ByteNum VoltLevSel Volts BdNum The number of the EPIO board connected to the LFA to be set O toZ ByteNum The byte number of the DAC to be set LFA Channels 0 7 LFA Channels 8 15 LFA Channels 16 23 LFA Channels 24 31 Il C l2 OQ 18 EPIO 6244 Logic Family Adapter 6244 LFA VoltLevSel The voltage reference level to be set VOH Voltage Out High VOL Voltage Out Low VIH Voltage In High VIL Voltage In Low Il WNO Volts The voltage level to set the given DAC to 7 to 7 Volts EPIO 6244 Logic Family Adapter 19 6244 LFA Lfa6244SetLogicLevelGain This routine is used to store a DAC s gain and offset so that calibrated voltages can be used for the voltage reference levels It also allows for LFAs with different DAC references to be used When different references are used the user can specify the ideal gain and offset for their reference without having to calibrate the logic levels However if they want to calibrate the voltages they can use this function to download and store the calibrated gain and offset Then when the DAC is being programmed it will use the stored value based on which board byte and logic level is being programmed Each of the four voltage levels VOH VOL VIH and VIL on each of the four bytes has a separate gain and offset These 16 gain and offset pairs are stored separately for each of the poss
28. r has to disconnect the previous DUT pin every time a different one is connected to the Mux It should be noted that connecting a DUT pin to the LFA or to the Mux input is mutually exclusive unless the State parameter is configured for the calibration mode The software prevents a DUT pin from being connected to both the LFA and the Mux input at the same time unless in calibration mode NOTE There is a maximum value for the turn on time of the relays The time needed to turn on a relay was not included in this function because the total time to turn on more than 100 relays would be excessive Therefore it was determined that the delay time should be up to the user and it should be done after all of the channels have been configured One relay needs 6 milliseconds to turn on EPIO 6244 Logic Family Adapter 13 6244 LFA Visual Basic Declaration I a6244 bas Public Sub Lfa6244Relay ByVal BdNum As Integer ByVal ChanNum As Integer ByVal CVI Declaration 14 State As Integer dli6244 h u_int32 DLI6244_LFA6244Relay int16 bdNum int16 chanNum int16 state Call Lfa6244Relay BdNum ChanNum State WHERE BdNum ChanNum State Wry oOo Wry od The number of the EPIO board connected to the LFA to be set to 7 If this number is O 31 this parameter specifies which DUT pin is to be configured The number given designates the LFA channel which is connected to the pin on the DUT If ChanNum is minus one 1 al
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