SuperHTM Family E10A-USB Emulator Additional
Contents
1. e Example To enable use of a user stack gt SH2A_SBSTK enable 25 ENESAS 2 2 5 Notes on Setting the Event Condition Dialog Box and the BREAKCONDITION SET Command 1 When Go to cursor Step In Step Over or Step Out is selected the settings of Event Condition 3 are disabled 2 When an Event Condition is satisfied emulation may stop after two or more instructions have been executed 2 2 6 Performance Measurement Function The emulator supports the performance measurement function 1 Setting the performance measurement conditions To set the performance measurement conditions use the Performance Analysis dialog box and the PERFORMANCE_SET command When any line in the Performance Analysis window is clicked with the right mouse button a popup menu is displayed and the Performance Analysis dialog box can be displayed by selecting Setting Note For the command line syntax refer to the online help 26 ENESAS a Specifying the measurement start end conditions The measurement start end conditions are specified by using Event Condition 1 2 The Ch1 2 3 list box of the Combination action Sequential or PtoP dialog box can be used Table 2 12 Measurement Period Classification Item Description Selection in Ch2 to Ch1 The period from the satisfaction of the condition set in Event the Ch1 2 3 PA Condition 2 start condition to the satisfaction of the condition set list box in Event Condi2. e When the emulator is used the sleep state can be cleared with either the clearing function or with the STOP button and a break will occur e The memory must not be accessed or modified in software standby state e The memory must not be accessed or modified in deep standby state e Do not stop inputting the clock to the H UDI module by using the module standby function 4 Reset Signals The MCU reset signals are only valid during emulation started with clicking the GO or STEP type button If these signals are enabled on the user system in command input wait state they are not sent to the MCU Note Do not break the user program when the RES BREQ or WAIT signal is being low A TIMEOUT error will occur If the BREQ or WAIT signal is fixed to low during break a TIMEOUT error will occur at memory access 5 Direct Memory Access Controller DMAC The DMAC operates even when the emulator is used When a data transfer request is generated the DMAC executes DMA transfer 6 Memory Access during User Program Execution During execution of the user program memory is accessed by the following two methods as shown in table 2 2 each method offers advantages and disadvantages Table 2 2 Memory Access during User Program Execution Method Advantage Disadvantage H UDI read write The stopping time of the user Cache access is disabled Actual program is short because memory memory is always accessed by the is accessed by the dedicat
3. North Tower World Finance Centre Harbour City 1 Canton Road Tsimshatsui Kowloon Hong Kong Tel lt 852 gt 2265 6688 Fax lt 852 gt 2730 6071 Renesas Technology Taiwan Co Ltd 10th Floor No 99 Fushing North Road Taipei Taiwan Tel lt 886 gt 2 2715 2888 Fax lt 886 gt 2 2713 2999 Renesas Technology Singapore Pte Ltd 1 Harbour Front Avenue 06 10 Keppel Bay Tower Singapore 098632 Tel lt 65 gt 6213 0200 Fax lt 65 gt 6278 8001 Renesas Technology Korea Co Ltd Kukje Center Bldg 18th FI 191 2 ka Hangang ro Yongsan ku Seoul 140 702 Korea Tel lt 82 gt 2 796 3115 Fax lt 82 gt 2 796 2145 Renesas Technology Malaysia Sdn Bhd Unit 906 Block B Menara Amcorp Amcorp Trade Centre No 18 Jalan Persiaran Barat 46050 Petaling Jaya Selangor Darul Ehsan Malaysia Tel lt 603 gt 7955 9390 Fax lt 603 gt 7955 9510 Colophon 6 0 SuperH Family E10A USB Emulator Additional Document for User s Manual Supplementary Information on Using the SH7670 SH7671 SH7672 and SH7673 ENESAS Renesas Technology Corp 2 6 2 Ote machi Chiyoda ku Tokyo 100 0004 Japan
4. as H 1000 in the Event Condition 5 dialog box Set the address condition as H 2000 in the Event Condition 4 dialog box Set I Trace as Ch5 to Ch4 PtoP in the Combination action Sequential or PtoP dialog box When point to point and trace acquisition condition are set simultaneously they are ANDed 22 ENESAS Notes on Internal Trace Timestamp The timestamp is the clock counts of Bd 48 bit counter Table 2 11 shows the timing for acquiring the timestamp Table 2 11 Timing for the Timestamp Acquisition Item Acquisition Information Counter Value Stored in the Trace Memory M bus data access Counter value when data access read or write has been completed Branch Counter value when the next bus cycle has been completed after a branch I bus Fetch Counter value when a fetch has been completed Data access Counter value when data access has been completed Point to point The trace start condition is satisfied when the specified instruction has been fetched Accordingly if the trace start condition has been set for the overrun fetched instruction an instruction that is not executed although it has been fetched at a branch or transition to an interrupt tracing is started during overrun fetching of the instruction However when overrun fetching is achieved a branch is completed tracing is automatically suspended If the start and end conditions are satisfied closely trace information will not be acquired corre
5. to be suspended during execution of the program is a maximum of about 20480 peripheral clocks Pq 4096 bus clocks B If the peripheral clock P is 33 3 MHz and the bus clock Bo is 66 6 MHz the program will be suspended for 676 52 us Branch trace If breaks occur immediately after executing non delayed branch and TRAPA instructions and generating a branch due to exception or interrupt a trace for one branch will not be acquired immediately before such breaks However this does not affect on generation of breaks caused by a BREAKPOINT and a break before executing instructions of Event Condition Writing memory immediately before generating a break If an instruction is executed to write memory immediately before generating a break trace acquisition may not be performed ENESAS 2 2 3 Notes on Using the JTAG H UDI Clock TCK 1 Set the JTAG clock TCK frequency to lower than the frequency of the peripheral module clock and to 20 MHz or lower 2 The initial value of the JTAG clock TCK is 10 00 MHz 3 A value to be set for the JTAG clock TCK is initialized after executing Reset CPU or Reset Go Thus the TCK value will be 10 00 MHz 2 2 4 Notes on Setting the Breakpoint Dialog Box 1 When an odd address is set the next lowest even address is used 2 A BREAKPOINT is accomplished by replacing instructions of the specified address It cannot be set to the following addresses e An area other than CS and the i
6. 01HE SH7671 SH7672 and SH7673 and Test program manual for HS0005KCU01H and HS0005KCU02H HS0005TMO1HJ and HS0005TMO1HE provided on a CD R Note Additional document for the MCUs supported by the emulator is included Check the target MCU and refer to its additional document RENESAS 1 2 Connecting the Emulator with the User System To connect the EIOA USB emulator hereinafter referred to as the emulator the H UDI port connector must be installed on the user system to connect the user system interface cable When designing the user system refer to the recommended circuit between the H UDI port connector and the MCU In addition read the EIOA USB emulator user s manual and hardware manual for the related device Table 1 2 Type Number and Connector Type Type Number Connector AUD Function HS0005KCU02H 14 pin connector Available 13 _ Installing the H UDI Port Connector on the User System Table 1 3 shows the recommended H UDI port connectors for the emulator Table 1 3 Recommended H UDI Port Connectors Connector Type Number Manufacturer Specifications 14 pin connector 7614 6002 Minnesota Mining and 14 pin straight type Manufacturing Ltd Note Do not place any components within 3 mm of the H UDI port connector 1 4 Pin Assignments of the H UDI Port Connector Figure 1 1 shows the pin assignments of the H UDI port connector Note Note that the pin number assignments of the H UDI port connector shown on the fol
7. 08a p_sam gt s5 aL5 0x0000108e p_sam gt s6 aL6 0x00001092 p_sam gt s7 al 0200001096 p_sam gt s8 aL8 0x0000109a p_sam gt s9 aL9 0x0000109e delete p_sam Figure 2 1 Source Window at Execution Halted Sequential Break If the sequential condition performance measurement start end or point to point for the internal trace is set conditions of Event Condition to be used will be disabled Such conditions must be enabled from the popup menu by clicking the right mouse button on the Event Condition sheet Notes 1 18 If the Event condition is set for the slot in the delayed branch instruction by the program counter after execution of the instruction the condition is satisfied before executing the instruction in the branch destination when a break has been set it occurs before executing the instruction in the branch destination Do not set the Event condition for the SLEEP instruction by the program counter after execution of the instruction When the Event condition is set for the 32 bit instruction by the program counter set that condition in the upper 16 bits of the instruction If the power on reset and the Event condition are matched simultaneously no condition will be satisfied Do not set the Event condition for the DIVU or DIVS instruction by the program counter after execution of the instruction If a condition of which intervals are satisfied closely is set no seq
8. REJ10J1706 0101 everywhere you imagine a CE NIC SAS SuperH Family E10A USB Emulator Additional Document for User s Manual Supplementary Information on Using the SH7670 SH7671 SH7672 and SH7673 Renesas Microcomputer Development Environment System SuperH Family E10A USB for SH7673 HS7673KCU01HE Rev 1 01 Renesas Technology Revision Date Aug 23 2007 zn Notes regarding these materials This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document including but not limited to product data diagrams charts programs algorithms and application circuit examples You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use When exporting the products or technology described herein you should follow the applicable export control laws and reg
9. Trace stop Ch3 2 1 Reset point Halts acquisition of an internal trace when a condition is satisfied in the order of Event Condition 3 2 1 Enables the reset point I Trace stop Ch2 1 Halts acquisition of an internal trace when a condition is satisfied in the order of Event Condition 2 1 I Trace stop Ch2 1 Reset point Halts acquisition of an internal trace when a condition is satisfied in the order of Event Condition 2 1 Enables the reset point Ch2 to Ch1 PA Sets the performance measurement period during the time from the satisfaction of the condition set in Event Condition 2 start condition to the satisfaction of the condition set in Event Condition 1 end condition ENESAS 15 Table 2 8 Conditions to Be Set cont Classification Ch1 2 3 list box cont Item Ch1 to Ch2 PA Description Sets the performance measurement period during the time from the satisfaction of the condition set in Event Condition 1 start condition to the satisfaction of the condition set in Event Condition 2 end condition Ch4 5 list box Sets the point to point of the internal trace the start or end condition of trace acquisition using Event Conditions 4 and 5 Don t care Sets no start or end condition of trace acquisition I Trace Ch5 to Ch4 PtoP Sets the acquisition period during the time from the satisfaction of the condition set in Event Condition 5 start condition to t
10. ctly The execution cycle of the instruction fetched before the start condition is satisfied may be traced When the I bus is acquired do not specify point to point Memory access may not be acquired by the internal trace if it occurs at several instructions immediately before satisfaction of the point to point end condition Halting a trace Do not set the trace end condition for the sleep instruction and the branch instruction that the delay slot becomes the sleep instruction 23 ENESAS 24 Trace acquisition condition Do not set the trace end condition for the sleep instruction and the branch instruction according to which the delay slot becomes the sleep instruction When I Bus M Bus amp Branch is selected and the trace acquisition condition is set for the M bus and I bus with Event Condition set the M bus condition and the I bus condition for Event Condition 1 and Event Condition 2 respectively If the settings of I Trace mode are changed during execution of the program execution will be suspended The number of clocks to be suspended during execution of the program is a maximum of about 51 peripheral clocks Pd 15 bus clocks B If the peripheral clock Pd is 33 3 MHz and the bus clock B is 66 6 MHz the program will be suspended for 1 757 us Displaying a trace If a trace is displayed during execution of the program execution will be suspended to acquire the trace information The number of clocks
11. d by generating a break and executing the user program again For the change of the multiplication rate of PLL circuit 1 and the FRQCR register refer to the hardware manual for the MCU ENESAS 2 2 Specific Functions for the Emulator when Using the SH7670 SH7671 SH7672 and SH7673 2 2 1 Event Condition Functions The emulator is used to set event conditions for the following three functions e Break of the user program e Internal trace e Start or end of performance measurement Table 2 6 lists the types of Event Condition Table 2 6 Types of Event Condition Event Condition Type Address bus condition Address Description Sets a condition when the address bus data access value or the program counter value before or after execution of instructions is matched Data bus condition Data Sets a condition when the data bus value is matched Byte word or longword can be specified as the access data size Bus state condition Bus State There are two bus state condition settings Bus state condition Sets a condition when the data bus value is matched Read Write condition Sets a condition when the read write condition is matched Count Sets a condition when the specified other conditions are satisfied for the specified counts Reset point A reset point is set when the count and the sequential condition are specified Action Selects the operation when a condition such as a break a t
12. ed bus H UDI read or write master Short break Cache access is enabled The stopping time of the user program is long because the user program temporarily breaks Note Accessing memory to cache control registers 1 and 2 is fixed as a short break during execution of the user program The method for accessing memory during execution of the user program is specified by using the Configuration dialog box ENESAS Table 2 3 Stopping Time by Memory Access Reference Method Condition Stopping Time H UDI read write Reading of one longword for the Reading Maximum three bus clocks internal RAM Bo Writing of one longword for the Writing Maximum two bus clocks internal RAM Bo Short break CPU clock 160 MHz About 50 ms JTAG clock 20 MHz Reading or writing of one longword for the external area 7 Memory Access to the External Flash Memory Area The emulator can download the load module to the external flash memory area for details refer to section 6 22 Download Function to the Flash Memory Area in the SuperH Family E10A USB Emulator User s Manual Other memory write operations are enabled for the RAM area Therefore an operation such as memory write or BREAKPOINT should be set only for the RAM area ENESAS 8 Operation while Cache is Enabled When cache is enabled the emulator operates as shown in table 2 4 Table 2 4 Operation while Cache is Enabled Function Operation Notes Searches for whether or n
13. es the data on the I bus e Data access read write e Selection of the bus master on the I bus CPU DMA A DMA e Instruction fetch I Bus M Bus amp Branch Acquires the contents of M Bus amp Branch and I Bus After selecting Type of I Trace mode select the content to be acquired from Acquisition Typical examples are described below note that items disabled for Acquisition are not acquired e Example of acquiring branch information only Select M Bus amp Branch from Type and enable Branch on Acquisition e Example of acquiring the read or write access M bus only by a user program Select M Bus amp Branch from Type and enable Read Write and Data access on Acquisition e Example of acquiring the read access only by DMA I bus Select I Bus from Type and enable Read DMA and Data access on Acquisition Using Event Condition restricts the condition the following three items are set as the internal trace conditions Table 2 10 Trace Conditions of the Internal Trace Item Trace halt Acquisition Information Acquires the internal trace until the Event Condition is satisfied The trace content is displayed in the Trace window after a trace has been halted No break occurs in the user program Trace acquisition Acquires only the data access where the Event Condition is satisfied Point to point Traces the period from the satisfaction of Event Cond
14. gure 1 2 Recommended Circuit for Connection between the H UDI Port Connector and MCU when the Emulator is in Use 14 Pin Type ENESAS ENESAS Section 2 Software Specifications when Using the SH7670 SH7671 SH7672 and SH7673 2 1 Differences between the MCU and the Emulator 1 When the emulator system is initiated it initializes the general registers and part of the control registers as shown in table 2 1 The initial values of the MCU are undefined When the emulator is initiated from the workspace a value to be entered is saved in a session Table 2 1 Register Initial Values at Emulator Link Up Register Emulator at Link Up RO to R14 H 00000000 R15 SP Value of the SP in the power on reset vector table PC Value of the PC in the power on reset vector table SR H 000000FO GBR H 00000000 VBR H 00000000 TBR H 00000000 MACH H 00000000 MACL H 00000000 PR H 00000000 FPSCR H 00040001 FPUL H 00000000 FPRO 15 H 00000000 Note If the MCU does not incorporate the floating point unit FPU these registers are not displayed Note When a value of the interrupt mask bit in the SR register is changed in the Registers window it is actually reflected in that register immediately before execution of the user program is started It also applies when the value is changed by the REGISTER_SET command 2 The emulator uses the H UDI do not access the H UDI RENESAS 3 Low Power States
15. halt is enabled for the internal trace T3 Setting the trace halt and point to point is enabled for the internal trace P Setting a performance measurement start or end condition is enabled The Event Condition 11 dialog box is used to specify the count of Event Condition 1 and becomes a reset point when the sequential condition is specified ENESAS Sequential Setting Using the Combination action Sequential or PtoP dialog box specifies the sequential condition and the start or end of performance measurement Table 2 8 Conditions to Be Set Classification Ch1 2 3 list box Item Description Sets the sequential condition and the start or end of performance measurement using Event Conditions 1 to 3 and 11 Don t care Sets no sequential condition or the start or end of performance measurement Break Ch3 2 1 Breaks when a condition is satisfied in the order of Event Condition 3 2 1 Break Ch3 2 1 Breaks when a condition is satisfied in the order of Reset point Event Condition 3 2 1 Enables the reset point of Event Condition 11 Break Ch2 1 Breaks when a condition is satisfied in the order of Event Condition 2 1 Break Ch2 1 Breaks when a condition is satisfied in the order of Reset point Event Condition 2 1 Enables the reset point I Trace stop Ch3 2 1 Halts acquisition of an internal trace when a condition is satisfied in the order of Event Condition 3 2 1 I
16. he area cache is not searched for but the external area is accessed 10 ENESAS 9 Using WDT The WDT does not operate during break 10 Loading Sessions Information in JTAG clock of the Configuration dialog box cannot be recovered by loading sessions Thus the TCK value will be as follows When HS0005KCU01H or HS0005KCU02H is used TCK 10 00 MHz 11 10 Window Display and modification There are two registers to be separately used for write and read operations Table 2 5 Register with Different Access Size Register Name Usage Register WTCSR W Write Watchdog timer control status register WTCNT W Write Watchdog timer counter WTCSR R Read Watchdog timer control status register WTCNT R Read Watchdog timer counter WRCSR W Write Watchdog reset control status register WRCSR R Read Watchdog reset control status register Customization of the I O register definition file The internal I O registers can be accessed from the IO window However note the following when accessing the SDMR register of the bus state controller Before accessing the SDMR register specify addresses to be accessed in the I O register definition file SH7670 10 SH7671 10 SH7672 10 and SH7673 10 and then activate the High performance Embedded Workshop After the I O register definition file is created the MCU s specifications may be changed If each VO register in the I O register definition file differs from addresses de
17. he satisfaction of the condition set in Event Condition 4 end condition I Trace Ch5 to Ch4 PtoP power on reset Sets the acquisition period during the time from the satisfaction of the condition set in Event Condition 5 start condition to the satisfaction of the condition set in Event Condition 4 end condition or the power on reset Notes 1 After the sequential condition and the count specification condition of Event Condition 1 have been set break and trace acquisition will be halted if the sequential condition is satisfied for the specified count 2 Ifa reset point is satisfied the satisfaction of the condition set in Event Condition will be disabled For example if the condition is satisfied in the order of Event Condition 3 2 reset point 1 the break or trace acquisition will not be halted If the condition is satisfied in the order of Event Condition 3 2 reset point 3 2 1 the break and trace acquisition will be halted 3 If the start condition is satisfied after the end condition has been satisfied by measuring performance performance measurement will be restarted For the measurement result after a break the measurement results during performance measurement are added 4 If the start condition is satisfied after the end condition has been satisfied by the point to point of the internal trace trace acquisition will be restarted 16 ENESAS Usage Example of Sequential Break Extension Setting A tutor
18. i it sve leben daa rinda kin A adri 19 2 2 3 Notes on Using the JTAG H UDI Clock TCK oooooonncccioccconoccnonccoonccnonccinnccnnno 25 2 2 4 Notes on Setting the Breakpoint Dialog BOX ooonnccnnnninnnoconocononcnnnnanonanonnonnnos 25 2 2 5 Notes on Setting the Event Condition Dialog Box and the BREAKCONDITION_SET Command cedcccccnnnncnnnnononnnonnnonnnananononnconnnnnnnnnnnonos 26 2 2 6 Performance Measurement Function ooooccnncnnnooononnnnconanonnnonnnononannonnnnnncnnnnannnnnos 26 RENESAS ENESAS Section 1 Connecting the Emulator with the User System 1 1 Components of the Emulator The E10A USB emulator supports the SH7670 SH7671 SH7672 and SH7673 Table 1 1 lists the components of the emulator Table 1 1 Components of the Emulator Classi Quan fication Component Appearance tity Remarks Hard Emulator box HSO005KCU01H ware Depth 65 0 mm Width 97 0 mm Height 20 0 mm Mass 72 9 g or HS0005KCU02H Depth 65 0 mm Width 97 0 mm Height 20 0 mm Mass 73 7 g User system interface gt 1 14 pin type cable Length 20 cm Mass 33 1 g User system interface 1 36 pin type cable oo Length 20 cm Mass 49 2 g only for HS0005KCUO2H USB cable 1 Length 150 cm Mass 50 6 g Soft E10A USB emulator setup 1 HS0005KCUO1SR ware program SD SuperH Family E10A HS0005KCUO1HJ USB Emulator User s HSOOO5KCU01HE Manual Supplementary Information HS7652KCU01 Hu on Using the SH7670 HS7652KCU
19. ial program provided for the product is used as an example For the tutorial program refer to section 6 Tutorial in the SuperH Family EIOA USB Emulator User s Manual The conditions of Event Condition are set as follows 1 Ch3 Breaks address H 00001068 when the condition Only program fetched address after is satisfied 2 Ch2 Breaks address H 0000107a when the condition Only program fetched address after is satisfied 3 Chl Breaks address H 00001086 when the condition Only program fetched address after is satisfied Note Do not set other channels 4 Sets the content of the Ch1 2 3 list box to Break Ch 3 2 1 in the Combination action Sequential or PtoP dialog box 5 Enables the condition of Event Condition 1 from the popup menu by clicking the right mouse button on the Event Condition sheet Then set the program counter and stack pointer PC H 00000800 R15 H 00010000 in the Registers window and click the Go button If this does not execute normally issue a reset and execute the above procedures The program is executed up to the condition of Ch1 and halted Here the condition is satisfied in the order of Ch3 gt 2 gt 1 RENESAS i 0x00001058 ali j 0x00001068 p_sam gt sort a 0x00001070 p_sam gt change a 0x00001076 p_sam gt s0 a 0 Ox0000107a p_sam gt sl al1 0x0000107e p_sam gt s al 0x00001082 p_sam gt s3 al3 0x00001086 p_sam gt s4 a 4 0x00001
20. ing operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges Although Renesas endeavors to improve the quality and reliability of its products IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Please be sure to implement safety measures to guard against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other applicable measures Among others since the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed the risk of accident such as swallowing by infants and small children is very high You should implement safety measures so that Renesas products may not be easily detached from your products Renesas shall have no liability for damages arising out of such detachment This docume
21. ition 4 to the satisfaction of Event Condition 5 21 RENESAS To restrict trace acquisition to access for only a specific address or specific function of a program an Event Condition can be used Typical examples are described below e Example of halting a trace with a write access M bus to H FFF80000 by the user program as a condition trace halt Set the condition to be acquired on I Trace mode Set the following in the Event Condition 1 or Event Condition 2 dialog box Address condition Set Address and H FFF80000 Bus state condition Set M Bus and Write Action condition Disable Acquire Break and set Acquire Trace for Stop e Example of acquiring the write access M bus only to H FFF80000 by the user program trace acquisition condition Select M Bus amp Branch from Type and enable Write and Data access on Acquisition Set the following in the Event Condition 1 or Event Condition 2 dialog box Address condition Set Address and H FFF80000 Bus state condition Set M Bus and Write Action condition Disable Acquire Break and set Acquire Trace for Condition For the trace acquisition condition the condition to be acquired by Event Condition should be acquired by I Trace mode e Example of acquiring a trace for the period while the program passes H 1000 through H 2000 point to point Set the condition to be acquired on I Trace mode Set the address condition
22. lowing pages differ from those of the connector manufacturer ENESAS SH7670 SH7671 SH7672 Input SH7673 Pin No Signal Output Pin No 1 TCK Input V17 TRST Input Y18 TDO Output W19 ASEBRKAK Input T20 ASEBRK output TMS Input Y19 TDI Input V18 RES Output W18 User reset N C GND UVCC GND GND 3 Output Input to or output from the user system The symbol means that the signal is active low The emulator monitors the GND signal of the user system and detects whether or not the user system is connected When the user system interface cable is connected to this pin and the ASEMD pin is set to 0 do not connect to GND but to the ASEMD pin directly Pin 1 mark H UDI port connector top view fa flo fe A ie pa 1 H UDI port connector 230 6x 2 54 15 24 top view ies Pin 1 mark Unit mm Figure 1 1 Pin Assignments of the H UDI Port Connector 14 Pins ENESAS 1 3 1 5 1 Recommended Circuit between the H UDI Port Connector and the MCU Recommended Circuit 14 Pin Type Figure 1 2 shows a recommended circuit for connection between the H UDI port connector 14 pins and the MCU when the emulator is in use Notes 1 Do not connect anything to the N C pins of the H UDI port connector Ze The ASEMD pin must be 0 when the emulator is connected and 1 when the emulator is not connected respectively 1 When the emulator is used ASEMD 0 2 When the em
23. mber of execution 32bit instructions 132 Exception interrupt counts EA Interrupt counts INT Data cache miss counts DC Instruction cache miss counts IC All area access counts ARN All area instruction access counts ARIN All area data access counts ARND Cacheable area access counts CDN data access Cacheable area instruction access counts CIN Non cacheable area data access counts NCN URAM area access counts UN URAM area instruction access counts UIN URAM area data access counts UDN Internal I O area data access counts IODN Internal ROM area access counts RN Internal ROM area instruction access counts RIN Internal ROM area data access counts RDN All area access cycle ARC All area instruction access cycle ARIC All area data access cycle ARDC All area access stall ARS All area instruction access stall ARIS All area data access stall ARDS Note Selected names are displayed for CONDITION in the Performance Analysis window Options are parameters for lt mode gt of the PERFORMANCE_SET command 29 RENESAS Note If the internal ROM is not installed on the product do not set the measurement item for the internal ROM area 2 Displaying the measured result The measured result is displayed in the Performance Analysis window or the PERFORMANCE_ANALYSIS command with hexadecimal 32 bits Note Ifa performance counter overflows as a result of measurement will be displayed 3 Initializing the mea
24. nesas products are not designed manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems or equipment or systems for transportation and traffic healthcare combustion control aerospace and aeronautics nuclear power or undersea communication transmission If you are considering the use of our products for such purposes please contact a Renesas sales office beforehand Renesas shall have no liability for damages arising out of the uses set forth above Notwithstanding the preceding paragraph you should not use Renesas products for the purposes listed below 1 artificial life support devices or systems 2 surgical implantations 3 healthcare intervention e g excision administration of medication etc 4 any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp its affiliated companies and their officers directors and employees against any and all damages arising out of such applications You should use the products described herein within the range specified by Renesas especially with respect to the maximum rat
25. nt may not be reproduced or duplicated in any form in whole or in part without prior written approval from Renesas Please contact a Renesas sales office if you have any questions regarding the information contained in this document Renesas semiconductor products or if you have any other inquiries Contents Section 1 Connecting the Emulator with the User System 1 1 1 Components of the Emulator oonncnnnnnnoninocnnonconnconnnonnnononnnonnnonnncnnn conc cnn aieu reseso asipi raia 1 1 2 Connecting the Emulator with the User System oooocnnnnninnnonnnonnnononononancnncnncrnnonnonanonnccnns 2 1 3 Installing the H UDI Port Connector on the User System ooooncnnnnnocinonononcnnnnanananonaninnncnns 2 1 4 Pin Assignments of the H UDI Port Connector oooccocnnonnnonononcnnnnanonononononononnncnnn ron crono nenn 2 1 5 Recommended Circuit between the H UDI Port Connector and the MCU 4 1 5 1 Recommended Circuit 14 Pin Type ooonnccnncnnononoccnnncnnnconnconanonona nono nono nana nnnncnnnons 4 Section 2 Software Specifications when Using the SH7670 SH7671 2 1 2 2 SH7672 and HITO caia ia T Differences between the MCU and the Emulator cccnnnnooooonncnnnonononcnonocononananononononnnnnnnnns 7 Specific Functions for the Emulator when Using the SH7670 SH7671 SH7672 and NP NO 13 2 2 1 Event Condition Functions occcccccnnnoonnnnnncnonnnannnnnnncnononannnnnnncononnnnonnnnnccnonannnnnnnos 13 2 2 2 TRACE FUnclONS eii
26. nternal RAM e An instruction in which Break Condition 2 is satisfied e A slot instruction of a delayed branch instruction 3 During step operation specifying BREAKPOINTs and Event Condition breaks are disabled 4 When execution resumes from the address where a BREAKPOINT is specified and a break occurs before Event Condition execution single step operation is performed at the address before execution resumes Therefore realtime operation cannot be performed 5 When a BREAKPOINT is set to the slot instruction of a delayed branch instruction the PC value becomes an illegal value Accordingly do not seta BREAKPOINT to the slot instruction of a delayed branch instruction 6 If an address of a BREAKPOINT cannot be correctly set in the ROM or flash memory area a mark will be displayed in the BP area of the address on the Source or Disassembly window by refreshing the Memory window etc after Go execution However no break will occur at this address When the program halts with the event condition the mark disappears 7 If you wish to use a BREAKPOINT software break specify the SH2A_SBSTK command to enable use of a user stack before setting a PC break While enabled extra four bytes of a user stack are used when a break occurs The value of the stack pointer R15 must be correctly set in advance because a user stack is to be used By default use of a user stack is disabled For details on the command refer to the help file
27. ot the address to be Memory write written hits the instruction and operand caches e When the address hits the corresponding position of the data array is changed by the data to be written and single write is performed to the external area e When the address does not hit the cache contents are not changed and single write is performed to the external area The contents of the address array are not changed before or after writing of memory Memory read Searches for whether or not the address to be read hits the operand cache e When the address hits the corresponding position of the data array is read e When the address does not hit single write is performed to the external area The instruction cache is not searched for The contents of the address array are not changed before or after reading of memory BREAKPOINT Clears the V and LRU bits of all entries in the instruction cache to 0 if a BREAKPOINT is set or canceled Clears the V and LRU bits of all entries in the instruction cache to O if a break occurs when a BREAKPOINT has been set Use the Event Condition if you do not wish to change the contents of the instruction cache Program load Writes the contents of the data cache to the external memory and clears the V and LRU bits of entries in the instruction and data caches to 0 after loading of the program has been completed If memory is read from or written to the disabled cac
28. race halt condition or a trace acquisition condition is matched Using the Combination action Sequential or PtoP dialog box which is opened by selecting Combination action Sequential or PtoP from the pop up menu on the Event Condition sheet specifies the sequential condition and the start or end of performance measurement Table 2 7 lists the combinations of conditions that can be set under Chl to Ch11 and the software trace 13 ENESAS Table 2 7 Dialog Boxes for Setting Event Conditions Function Address Bus Data Bus Bus State Count Condition Condition Condition BusCondition Dialog Box Address Data Status Count Action Event Ch1 O O O O O Condition 1 B T1 and P Event Ch2 O O O x O Condition 2 B T1 and P Event Ch3 O x x x O Condition 3 B and T2 Event Ch4 O X X X O Condition 4 B and T3 Event Ch5 O X X X O Condition 5 B and T3 Event Ch6 O x x x O Condition 6 B and T2 Event Ch7 O x x x O Condition 7 B and T2 Event Ch8 O x x x O Condition 8 B and T2 Event Ch9 O x x x O Condition 9 B and T2 Event Ch10 O X X X O Condition 10 B and T2 Event Ch11 O X x x O Condition 11 reset point B and T2 Notes 1 O Can be setin the dialog box X Cannot be set in the dialog box 2 For the Action item B Setting a break is enabled T1 Setting the trace halt and acquisition conditions are enabled for the internal trace T2 Setting the trace
29. rectly displayed The factor for halting a break due to the break condition after executing an instruction will be displayed even if a break is halted by the break condition before executing an instruction 11 Do not set the break condition after executing instructions and BREAKPOINT software break to the same address 12 When the emulator is being connected the user break controller UBC function is not available 2 2 2 Trace Functions The emulator supports the internal trace function The AUD trace is not available for this MCU The internal traces are set in the Acquisition dialog box of the Trace window ENESAS Internal Trace Function When I Trace is selected for Trace type on the Trace Mode page of the Acquisition dialog box the internal trace can be used ik M Bus amp Branch v M M GEMI JE DMG JE A DMAG Instruction Ketch Trace continue ha E Gamel E E Camel E AD 7 Norm UL rat le race continue Era Spay rante Start panter End pointer Figure 2 2 Acquisition Dialog Box Internal Trace Function 20 RENESAS The following three items can be selected as the internal trace from Type of I Trace mode Table 2 9 Information on Acquiring the Internal Trace Item M Bus amp Branch Acquisition Information Acquires the data and branch information on the M bus e Data access read write e PC relative access e Branch information I Bus Acquir
30. scribed in the hardware manual change the I O register definition file according to the description in the hardware manual The I O register definition file can be customized depending on its format However the emulator does not support the bit field function Verify In the IO window the verify function of the input value is disabled ENESAS 12 Illegal Instructions 13 Do not execute illegal instructions with STEP type commands Reset Input During execution of the user program the emulator may not operate correctly if a contention occurs between the following operations for the emulator and the reset input to the target device Setting an Event Condition Setting an internal trace Displaying the content acquired by an internal trace Reading or writing of a memory Note that those operations should not contend with the reset input to the target device 14 Contention between the Change of the FRQCR Register and the Debugging Functions The following notes are required for the user program for changing the multiplication rate of PLL circuit 1 to change the frequency Avoid contention between the change of the FRQCR register in the user program and the memory access from the Memory window etc When the automatic updating function is used in the Monitor window or Watch window generate and set a break of Event Condition for an instruction immediately before changing the FRQCR register Contention will be avoide
31. sured result To initialize the measured result select Initialize from the popup menu in the Performance Analysis window or specify INIT with the PERFORMANCE_ANALYSIS command 30 ENESAS SuperH Family E10A USB Emulator Additional Document for User s Manual Supplementary Information on Using the SH7670 SH7671 SH7672 and SH7673 Publication Date Rev 1 01 August 23 2007 Published by Sales Strategic Planning Div Renesas Technology Corp Edited by Customer Support Department Global Strategic Communication Div Renesas Solutions Corp 2007 Renesas Technology Corp All rights reserved Printed in Japan Renesas Technology Corp Sales Strategic Planning Div Nippon Bldg 2 6 2 Ohte machi Chiyoda ku Tokyo 100 0004 Japan ENESAS RENESAS SALES OFFICES http www renesas com Refer to http www renesas com en network for the latest and detailed information Renesas Technology America Inc 450 Holger Way San Jose CA 95134 1368 U S A Tel lt 1 gt 408 382 7500 Fax lt 1 gt 408 382 7501 Renesas Technology Europe Limited Dukes Meadow Millboard Road Bourne End Buckinghamshire SL8 5FH U K Tel lt 44 gt 1628 585 100 Fax lt 44 gt 1628 585 900 Renesas Technology Shanghai Co Ltd Unit 204 205 AZIACenter No 1233 Lujiazui Ring Rd Pudong District Shanghai China 200120 Tel lt 86 gt 21 5877 1818 Fax lt 86 gt 21 6887 7898 Renesas Technology Hong Kong Ltd 7th Floor
32. tion 1 end condition is set as the performance measurement period Ch1 to Ch2 The period from the satisfaction of the condition set in Event PA Condition 1 start condition to the satisfaction of the condition set in Event Condition 2 end condition is set as the performance measurement period Other than The period from the start of execution of the user program to the above occurrence of a break is measured Perfomance Analysi Condition Channel 1 Elapsed time s i s OCC Channel 2 Disabled SY Channel 3 PS Channel4 Disabled OOOO OK Cancel Figure 2 3 Performance Analysis Dialog Box For measurement tolerance e The measured value includes tolerance e Tolerance will be generated before or after a break 27 RENESAS Note When Ch2 to Ch1 PA or Chl to Ch2 PA is selected to execute the user program specify conditions set in Event Condition 2 and Event Condition 1 and one or more items for performance measurement b Measurement item Items are measured with Channel 1 to 4 in the Performance Analysis dialog box Maximum four conditions can be specified at the same time 28 ENESAS Table 2 13 Measurement Item Selected Name Option Disabled None Elapsed time AC The number of execution cycles I is set as the measurement item Branch instruction counts BT Number of execution instructions l Nu
33. uential condition will be satisfied e Set the Event conditions which are satisfied closely by the program counter with intervals of two or more instructions e After the Event condition has been matched by accessing data set the Event condition by the program counter with intervals of 17 or more instructions RENESAS 7 If the settings of the Event condition or the sequential conditions are changed during execution of the program execution will be suspended The number of clocks to be suspended during execution of the program is a maximum of about 102 bus clocks B If the bus clock Bo is 66 6 MHz the program will be suspended for 1 53 us 8 If the settings of Event conditions or the sequential conditions are changed during execution of the program the emulator temporarily disables all Event conditions to change the settings During this period no Event condition will be satisfied 9 Ifthe break condition before executing an instruction is set to the instruction followed by DIVU and DIVS the factor for halting a break will be incorrect under the following condition If a break occurs during execution of the above DIVU and DIVS instructions the break condition before executing an instruction which has been set to the next instruction may be displayed as the factor for halting a break 10 If the break conditions before and after executing instructions are set to the same address the factor for halting a break will be incor
34. ulations and procedures required by such laws and regulations All information included in this document such as product data diagrams charts programs algorithms and application circuit examples is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas products listed in this document please confirm the latest product information with a Renesas sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website http www renesas com Renesas has used reasonable care in compiling the information included in this document but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document When using or otherwise relying on the information in this document you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application Renesas makes no representations warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products With the exception of products specified by Renesas as suitable for automobile applications Re
35. ulator is not used ASEMD 1 Figure 1 2 shows an example of circuits that allow the ASEMD pin to be GND 0 whenever the emulator is connected by using the user system interface cable When the ASEMD pin is changed by switches etc ground pin 9 Do not connect this pin to the ASEMD pin When a network resistance is used for pull up it may be affected by a noise Separate TCK from other resistances The pattern between the H UDI port connector and the MCU must be as short as possible Do not connect the signal lines to other components on the board Since the H UDI of the MCU operates with the VCCQ supply only the VCCQ to the UVCC pin Make the emulator s switch settings so that the user power will be supplied SW2 1 and SW3 1 The resistance value shown in figure 1 2 is for reference The TRST pin must be at the low level for a certain period when the power is supplied whether the H UDI is used or not For the pin processing in cases where the emulator is not used refer to the hardware manual of the related MCU ENESAS When the circuit is connected as shown in figure 1 2 the switches of the emulator are set as SW2 1 and SW3 1 For details refer to section 3 8 Setting the DIP Switches in the SuperH Family El0A USB Emulator User s Manual VCCQ I O power supply All pulled up at 4 7 kQ VCCQ VCCQ VCCQ VCCQ VCCQ VCCQ Ll H UDI port connector Target MCU 14 pin type Reset signal User system Fi
Download Pdf Manuals
Related Search