Alex Milenkovich 1
Contents
1. CPE EE 421 521 Microcomputers Asynchronous Serial Interface cont d gt MARK level or OFF or 1 state or 1 level This is also the idle state before the transfer begins gt SPACE level or ON or O state or 0 level gt One character Start bit space level Data bits Optional parity bit Optional stop bit Ore cohen rmdir CPE EE 421 521 Microcomputers Alex Milenkovich Asynchronous Serial Interface gt Asynchronous Transmitted and received data are not synchronized over any extended period No synchronization between receiver and transmitter clocks gt Serial Usually character oriented Data stream divided into individual bits at the transmitter side Individual bits are grouped into characters at the receiving side gt Information is usually transmitted as ASCII encoded characters 7 or 8 bits of information plus control bits CPE EE 421 521 Microcomputers Asynchronous Serial Interface cont d gt 12 possible basic formats 7 or 8 bits of data Odd even or no parity 1 or 2 stop bits Others exist also no stop bits 4 5 6 data bits 1 5 stop bits etc Least significant bit Example Leter M ASCII 40 1007101 even panty Mark 1 Spaca CPE EE 421 521 Microcomputers Receiver Clock Timing RS 232 Interface Standard Stat bit Bi polar 3 to 12V ON O state or SPACE condition 3 to 12V OFF2. 1 state or MARK condition Modern computers accept OV as MARK Dead area between 3V and 3V is designed to absorb line noise Originally developed as a standard for communication oe A ated pi between computer equipment and modems ss From the point of view of this standard gt For N 9 bits 7 data parity stop maximum tolerable error is 5 MODEM data communications equipment DCE assume that the receiver clock is slow T dt instead of T Computer equipment data terminal equipment DTE T 2 gt 2N 1 ot 2 Therefore RS 232C was intended for DTE DCE links t 2 lt 1 2N 1 not for DTE DTE links as it is frequently used now t T lt 100 2N 1 as a percentage CPE EE 421 521 Microcomputers CPE EE 421 521 Microcomputers RS 232 Interface Standard RS 232 Interface Standard another example gt Each manufacturer may choose to implement only a subset of functions defined by this standard gt Two widely used connectors DB 9 and DB 25 gt Three types of link Simplex Half duplex Full duplex Indeterminate gt Basic control signals RTS Request to send Seven Data Bits DTE indicates to the DCE that it wants to send data CTS Clear to send DCE indicates that it is ready to receive data DSR Data set ready indication from the DCE i e the modem that it is on DTR Data terminal ready indication from the DTE that it is on DTR Data terminal ready indication from th
3. and TA_0 ISR Toggle rate is void main void set at 50000 DCO SMCLK cycles Default DCO frequency used for TACLK Durring the TA_0 ISR P0 1 is toggled and 50000 clock cycles are added to WDTCTL WDTPW WDTHOLD Stop WDT CCRO TA_O ISR is triggered exactly 50000 cycles CPU is normally P1DIR 0x01 P1 0 output off and CCTLO CCIE CCRO interrupt enabled used only durring TA_ISR ACLK n a MCLK SMCLK TACLK DCO 800k CCRO 50000 TACTL TASSEL_2 MC_2 SMCLK contmode MSP430F149 _BIS_SR LPMO_bits GIE Enter LPMO w interrupt Timer AO interrupt service routine interrupt TIMERAO_VECTOR void TimerA void M Buccini P10UT 0x01 Toggle P1 0 P1 0 gt LED Texas Instruments Ine CCRO 50000 Add Offset to CCRO September 2003 Built with IAR Embedded Workbench Version 1 26B December 2003 Updated for IAR Embedded Workbench Version 2 21B Z E e e e e e e He e e e He k Ae e e Ae e Ae e e k AE e e e k e e e e e E e e e E e Ae e E e E e Ae e E e AE e e e E e AE K e e A E A AE CPE EE 421 521 Microcomputers Serial I O Interface Functional Units Terminal Ser pirs Inirared bann Sanal interno Uiirasame baam E Line drwg p Translates the TTL level signals processed by the ACIA into a form suitable for the transmission path Translates data between the internal computer form and the form in which it is transmitted over the data link
4. iene aol ey eer capture modules of the timers are tied to external pins of the MSP Meter re When the control registers of timer A and the specific capture eRe compare module have been properly configured then the capture will record the count in the timer when the pin in question makes a specific transition either from low to high or any transition This capturing event can be used to trigger an interrupt so that the data can be processed before the next event In combination with the rollover interrupt on Capture module 0 you can measure intervals longer than 1 cycle UP Mode Continuous Mode gt Com pa re Timer counts between 0 and CCRO Timer continuously counts up OFFFFh The inverse of a capture While capture mode is used to measure Continuous Mode the time of an incoming pulse width modulation signal a signal SEEEN whose information is encoded by the time variation between signal edges compare mode is used to generate a pulse width modulation PWM signal When the timer reaches the value in a compare register the module will give an interrupt and change the state of an output according to the other mode bits By updating the compare register numbers you change the timing of the signal level transitions CPE EE 421 521 Microcomputers 11 CPE EE 421 521 Microcomputers Alex Milenkovich Timer_A 16 bit Counter Timer_A Capture Compare Blocks Timer Block Capture 3 Capture Comp
5. outgoing signals This function is necessary to meet arbitrary timing requirements from outside components and the ability is useful Bit 0 No interrupt is pending in phase locking scenarios Bit 1 An interrupt is pending gt Features 16 bit counter with 4 operating modes Selectable and configurable clock sources internal ACLK SMCLK external INCLK TBCLk Three or five independently configurable capture compare registers Interrupt Edge Select Registers P1IES P2IES with configurable inputs only for P1 and P2 Three or five individually configurable output modules with 8 output modes Multiple simultaneous timings multiple capture compares Bit 0 The PnIFGx flag is set with a low to high transition multiple output waveforms such as PWM signals and any combination of these Bit 1 The PnIFGx flag is set with a high to low transition Interrupt capabilities Only transitions not static levels cause interrupts Each PnlES bit selects the interrupt edge for the corresponding I O pin e each capture compare block individually configurable CPE EE 421 521 Microcomputers CPE EE 421 521 Microcomputers Timer_A3 Timer_A5 MSP430x1xx Block Diagram f oe CPE EE 421 521 Microcomputers Capture and Compare Registers Timer_A Counting Modes gt What is a capture Stop Halt Mode UP DOWN Mode A record of the timer count when a specific event occurs The erie caida
6. Course Administration gt Instructor Aleksandar Milenkovic milenka ece uah edu CPE F F 42 1 www ece uah edu milenka EB 217 L Mon 5 30 PM 6 30 PM Microcomputers Wen 12 30 13 30 PM Instructor Dr Aleksandar Milenkovic gt URL http www ece uah edu milenka cpe421 05F Lecture Note gt TA Joel Wilder S17 gt Labs Lab 4 is on Hw 2 is posted gt Test I Graded Solutions are in scr gt Text Microprocessor Systems Design 68000 Hardware Software and Interfacing gt Review M68K Chapter 1 Chapter 2 Chapter 3 MSP430 Introduction Arch Basic Clock System WDT Low Power Modes Digital 1 0 CPE EE 421 521 Microcomputers gt Today MSP43 Digitet pmbiexers USART 2 Review Digital I O all MSP430 Digital I O Introduction gt MSP430 family up to 6 digital I O ports implemented P1 P6 Porti Ports gt MSP430F 14x all 6 ports implemented Port2 Port6 P Ports P1 and P2 have interrupt capability erup Edge Select Register PXIES Each interrupt for the P1 and P2 I O lines can be individually enabled and Se e e configured to provide an interrupt on a rising edge or falling edge of an input Direction Register PxDIR Output Register PXOUT Se ee AVES Cee ee a Lino Reaister e The digital I O features include gt Independently programmable individual I Os gt Any combination of input or output gt Individually configurable P1 and P2 interrupts Chapter 9 User s Manual g
7. are Register Synchronize Capture TASSEL unused i w w mw w z Compare Path 0 0 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw mw o 0 0 0 0 0 0 0 0 0 T T CAPTURE INPUT ae MqDE sevect SCS SCClhiceg CAP OUTMODx CCIE joci jout cov CIF rw rw rw rw rw rw rw rw rw rw rw f rw rw rw 0 0 0 0 0 0 0 0 0 Page 11 12 User s Manual CPE EE 421 521 Microcomputers CPE EE 421 521 Microcomputers Timer_A Output Units Timer_A Continuous Mode Example Logic Output Oh CCRO TAO Input j l l iti p Capture Mode Positive Edge CCR1 Capture Mode Both Edges Px y TA1 Input OMx2 OMx1 OMx0 Function Operational Conditions CCR2 TA2 Input Capture Mode Negative Edge 0 Output Mode Outx signal is set according to Outx bit 0 Set EQUx sets Outx signal clock synchronous with timer clock PWM Toggle Reset EQUx toggles Outx signal reset with EQUO clock sync with timer clock CERO PWM Set Reset EQUx sets Outx signal reset with EQUO clock synchronous with timer clock Gene cen eCRl GORT CCRT CORT Interrupts can be generated Toggle EQUx toggles Outx signal clock synchronous with timer clock CCR2 Reset EQUx resets Outx signal clock synchronous with timer clock PWM Toggle Reset EQUx toggles Outx signal set with EQUO clock synchronous with t
8. ate support Status flags for error detection Independent interrupt capability for transmit and receive CPE EE 421 521 Microcomputers 37 Initialization Sequence amp Character Format gt Initialization Sequence Set SWRST bit Initialize all USART registers with SWRST 1 Enable USART module via the MEx SFRs URXEx and or UTXEx Clear SWRST via software releases the USART for operation Optional enable interrupts vie Ex SFRs gt Character format Alex Milenkovich
9. e DTE that it is on CPE EE 421 521 Microcomputers CPE EE 421 521 Microcomputers RS 232 Interface Standard RS 232 Interface Standard Example 9 to 25 pin cable layout for asynchronous data gt DB 25 connector is described in the book let s take a look at DB 9 12 93 4 6 Description Source DTE or DEC Carrier Detect from Modem Receive Data from Modem Transmit Data from Terminal Computer Data Terminal Ready from Terminal Computer Signal Ground from Modem Data Set Ready from Modem from Terminal Computer igna Phn Sy Request to Send Data Carrig ala Se Hoag Poraa Dai _ Requestip Send Clear to Send from Modem 5809999309 Tran mifled Daj rik ef Ba Signal Ground Ring Indicator from Modem CPE EE 421 521 Microcomputers CPE EE 421 521 Microcomputers Alex Milenkovich The Minimal RS 232 Function DTE to DCE in simplex mode gt DTE to DTE in simplex mode gt CPE EE 421 521 Microcomputers The Minimal RS 232 Function DTE to DCE with remote control gt gt lt DTE to DTE with remote control f ps CPE EE 421 521 Microcomputers Null Modem gt Null modem simulates a DTE DCE DCE DTE circuit DTE Aing indicalor Data tonrenal ready Carnor detec Signal grou
10. imer clock Example shows th ree independent HW event captu res PWM Set Reset EQUx resets Outx signal set with EQUO clock synchronous with timer clock cc Rx stam ps time of event M Conti nuous Mode is ideal CPE EE 421 521 Microcomputers CPE EE 421 521 Microcomputers Timer _A PWM Up Mode Example Timer_A PWM Up Down Mode Example OFFFFh CCRO CCR1 CCR2 Oh PWM Set Reset een P TA1 Output 0 Degrees ai Px x 0 5xVmotor X j CCR2 PWM Reset Set TA2 Output TA2 Output Px y 3 Px y PWM Toggle TAO Output xed A Pz iy uto 120 Degrees TAO Output Re loa A EQU2 E EQU2 a Eau a ens Fou Quo Interrupts can be generated 0 07xVmotor j gt 120 Degrees 0 93xVmotor TIMOV EQUO TIMOV EQUO TIMOV Interrupts can be generated Output Mode 4 PWM Toggle Example shows three different asymmetric Example shows Symmetric PWM Generation PWM Timings generated with the Up Mode Digital Motor Control CPE EE 421 521 Microcomputers CPE EE 421 521 Microcomputers Alex Milenkovich C Examples Z E e e e e e e He e e e e k Ae e e e Ae e e e Ae k Ae e e e e k e K e E e e e E e AE e E e E e AE e E e AE e e E E e AE E e df tf tt ir tt include lt msp430x14x h gt MSP FET430P140 Demo Timer_A Toggle P1 0 CCRO Contmode ISR DCO SMCLK Description Toggle P1 0 using software
11. nd Duta sti mewdy Clonar to sond Fagota to sond Hisce data Tmnamited data Pro etieve ground CPE EE 421 521 Microcomputers Alex Milenkovich The Minimal RS 232 Function DTE to DCE in full duplex mode gt DTE to DTE in full duplex mode gt CPE EE 421 521 Microcomputers Handshaking Between RTS and CTS CPE EE 421 521 Microcomputers USART Peripheral Interface gt Universal Synchronous Asynchronous Receive Transmit USART peripheral interface Supports two modes Asynchronous UART mode User manual Ch 13 Synchronous Peripheral Interface SPI mode User manual Ch 14 gt UART mode Transmit receive characters at a bit rate asynchronous to another device Connects to an external system via two external pins URXD and UTXD P3 4 P3 5 Timing is based on selected baud rate both transmit and receive use the same baud rate CPE EE 421 521 Microcomputers UART Features USART Block Diagram UART mode 7 or 8 bit data width odd even or non parity et AERA SA Independent transmit and receive shift reg al Separate transmit and receive buffer registers LSB first data transmit and receive Built in idle line and address bit communication protocols for multiprocessor systems Receiver start edge detection for auto wake up from LPMx modes Programmable baud rate with modulation for fractional baud r
12. t Independent input and output data registers pages 9 1 to 9 7 The digital I O is configured with user software CPE EE 421 521 Microcomputers CPE EE 421 521 Microcomputers Digital I O Registers Operation Digital I O Operation Input Register PniN Direction Registers PnDIR Each bit in each PnIN register reflects the value of the input signal eck at the corresponding I O pin when the pin is configured as I O Bit 0 The port pin is switched to input direction function Do not write to PxIN It will result Bit 1 The port pin is switched to output direction Bit 0 The input is low in increased current consumption Bit 1 The input is high Function Select Registers PnSEL Output Registers PnOUT Port pins are often multiplexed with other peripheral module Each bit in each PnOUT register is the value to be output on the functions Saar eons tie when the pin is configured as I O function Sit 0 0 Function ie selected forthepih Bit 0 The output is low Bit 1 Peripheral module function is selected for the pin Bit 1 The output is high CPE EE 421 521 Microcomputers CPE EE 421 521 Microcomputers Alex Milenkovich Digital I O Operation Timer A MSP430x1xx gt Purpose A The Timer A and B systems on the MSP are a versatile means to measure Interrupt Flag Registers P1IFG P2IFG time intervals The timers can measure the timing on incoming signals or only for P1 and P2 control the timing on
Download Pdf Manuals
Related Search