Home

82930A Universal Serial Bus Microcontroller User`s Manual

1. Bytes 4 3 States 2 2 Encoding 0111 1110 tttt 1001 5555 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV Rm lt WRj MOV Rm DRk Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 0111 1110 uuuu 1011 5555 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV Rm lt DRk MOV WRjd WRijs Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 0000 1011 TTTT 1000 tttt 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV WRjd lt WRjs MOV WRj DRk Binary Mode Source Mode Bytes 4 3 States 5 4 Encoding 0000 1011 uuuu 1010 tttt 0000 A 91 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV WRj lt DRk intel MOV dir8 Rm Binary Mode Source Mode Bytes 4 3 States 4t 3t tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 0111 1010 5555 0011 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV dir8 lt Rm MOV dir8 WRj Binary Mode Source Mode Bytes 4 3 States 5 4 Encoding 0111 1010 tttt 0101 direct addr Hex Code in Binary Mode A5 En
2. ORL WRjd WRjs Binary Mode Source Mode Bytes 3 2 States 3 2 Encoding 0100 1101 tttt TTTT Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ORL WRijd lt WRid V WRjs ORL Rm data Binary Mode Source Mode Bytes 4 3 States 3 2 Encoding 0100 1110 5555 0000 data Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ORL Rm Rm V data ORL WRij data16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding 0100 1110 tttt 0100 data hi data low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ORL A 110 lt WRj V stdata16 intel INSTRUCTION SET REFERENCE ORL 8 Binary Mode Source Mode Bytes 4 3 States 3t 2T tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 0100 1110 ssss 0001 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ORL Rm Rm V dir8 ORL WRj dir8 Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 0100 1111 tttt 0101 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ORL lt V ORL Rm dir16 Binary Mode Source Mode Bytes 5 4 States 3 2 Encoding 0100 1110 ssss 0011 d
3. Logical AND ANL lt dest gt lt src gt dest opnd dest opnd A src opnd Logical OR ORL lt dest gt lt src gt dest opnd lt dest opnd V src opnd Logical Exclusive OR XRL lt dest gt lt srce gt dest lt dest v src Clear CLRA 0 Complement CPLA Ai lt O Ai Rotate RXX A 1 Shift SXX Rm or Wj 1 SWAP A A3 0 o 7 4 Binary Mode Source Mode Mnemonic dest src Notes Bytes States Bytes States A Rn Reg to acc 1 1 2 2 A dir8 Dir byte to acc 2 1 3 2 1 3 A Ri Indir addr to acc 1 2 2 3 A data Immediate data to acc 2 1 2 1 dir8 A Acc to dir byte 2 2 4 2 2 4 dir8 data Immediate data to dir byte 3 3 4 3 3 4 Rmd Rms Byte reg to byte reg 3 2 2 1 p WRjd WRjs Word reg to word reg 3 3 2 2 HS Rm data 8 bit data to byte reg 4 3 3 2 WRj data16 16 bit data to word reg 5 4 4 3 Rm dir8 Dir addr to byte reg 4 3 3 3 2 3 WRi dir8 Dir addr to word reg 4 4 3 3 Rm dir16 Dir addr 64K to byte reg 5 3 4 2 WRi dir16 Dir addr 64K to word reg 5 4 4 3 Rm WRj Indir addr 64K to byte reg 4 3 3 2 Rm DRk Indir addr 16M to byte reg 4 4 3 3 CLR A Clear acc 1 1 1 1 CPL A Complement acc 1 1 1 1 RL A Rotate acc left 1 1 1 1 RLC A Rotate acc left through the carry 1 1 1 1 RR A Rotate acc right 1 1 1 1 Rotate acc right through the carry 1 1 1 1 Rm Shift byte reg left 3 1 SLL WRj Shift word reg left 3 1 NOTES 1
4. Binary Mode Source Mode Mnemonic lt dest gt lt src gt Notes Bytes States Bytes States DRk dir8 Dir addr to dword reg 4 6 3 5 DRk dir16 Dir addr 64K to dword reg 5 6 4 5 Rm dir8 Dir addr to byte reg 4 3 3 3 2 3 WRij dir8 Dir addr to word reg 4 4 3 3 Rm dir16 Dir addr 64K to byte reg 5 3 4 2 WRij dir16 Dir addr 64K to word reg 5 4 4 3 Rm WRj Indir addr 64K to byte reg 4 2 3 2 Rm DRk Indir addr 16M to byte reg 4 4 3 3 WRid WRis Indir addr 64K to word reg 4 4 3 3 WRj DRk Indir addr 16M to word reg 4 5 3 4 dir8 Rm Byte reg to dir addr 4 4 3 3 3 3 dire WRj Word reg to dir addr 4 5 3 4 MOV dir16 Rm Byte reg to dir addr 64K 5 4 4 3 dir16 WRj Word reg to dir addr 64K 5 5 4 4 WRj Rm Byte reg to indir addr 64K 4 4 3 3 DRk Rm Byte reg to indir addr 16M 4 5 3 4 WRid WRijs Word reg to indir addr 64K 4 5 3 4 DRk WRj Word reg to indir addr 16M 4 6 3 5 dir8 DRk Dword reg to dir addr 4 7 3 6 dir16 DRk Dword reg to dir addr 64K 5 7 4 6 Rm WRij dis16 Indir addr with disp 64K to byte reg 5 6 4 5 WRj WRij dis16 Indir addr with disp 64K to word reg 5 7 4 6 Rm DRk dis24 Indir addr with disp 16M to byte reg 5 7 4 6 WRj DRk dis24_ Indir addr with disp 16M to word reg 5 8 4 7 WRi dis16 Rm Byte reg to Indir addr with disp 64K 5 6 4 5 NOTES 1 2 3 4 A shaded cell denotes an instruction in the MCS 51 architecture Instructions that move bits
5. Function 7 T SEQ Transmitters current sequence bit This bit will be transmitted in the next PID and toggled on a valid ACK handshake 6 3 Reserved Values read from these bits are indeterminate Write zeros to these bits 2 T VOID A time out condition has occurred in response to a valid IN token Transmit time out is closely associated with NACK STALL handshake returned by function after a valid IN token due to the following conditions 1 There is no data in TXFIFO to send 2 STL TX is set This bit does not affect TXD bit Updated in respond to a valid IN token 1 T ERR An error condition has occurred with the transmission Complete or partial data has been transmitted It can be one of the following 1 Data transmitted successfully but no handshake received 2 TXFIFO goes into underrun condition while transmitting Corresponding TXD bit is set when active Updated together with T ACK bit at the end of data transmission mutually exclusive with T ACK 0 T ACK Data transmission completed and acknowledged successfully Corre sponding TXD bit is set when active Updated together with T ERR bit at the end of data transmission mutually exclusive with T ERR Figure 7 15 TXSTATx Transmitter Status Register 7 23 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Table 7 16 TXSTATx Addresses and Reset Values Register Address Reset
6. MOV DRk Rm Binary Mode Source Mode Bytes 4 3 States 5 4 Encoding 0111 1010 uuuu 1011 ssss 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV DRK lt Rm MOV QWRjd WRjs Binary Mode Source Mode Bytes 4 3 States 5 4 Encoding 0001 1011 tttt 1000 TTTT 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV WRjg lt WRjs MOV QDRK WRj Binary Mode Source Mode Bytes 4 3 States 6 5 Encoding 0001 1011 uuuu 1010 tttt 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV DRk lt WRj MOV Rm WRj dis16 Binary Mode Source Mode Bytes 5 4 States 6 5 A 94 intel INSTRUCTION SET REFERENCE Encoding 0000 1001 5555 dis hi dis low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV Rm lt WRj dis MOV WRj WRj dis16 Binary Mode Source Mode Bytes 5 4 States 7 6 Encoding 0100 1001 tttt TTTT dis hi dis low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV WRj lt WRj dis MOV Rm DRk dis24 Binary Mode Source Mode Bytes 5 4 States 7 6 Encoding 0010 1001 5555 uuuu dis hi dis low Hex Code in B
7. Binary Mode A5 Encoding Source Mode Encoding XRL WRds lt WRjd v WRjs Binary Mode Source Mode 4 3 3 2 0110 1110 5555 0000 data Binary Mode A5 Encoding Source Mode Encoding XRL Rm lt Rm v data XRL WRj data16 A 139 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding 0110 1110 tttt 0100 data hi data low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation XRL WRJ lt WRj data16 XRL Rm dir8 Binary Mode Source Mode Bytes 4 3 States 3t 2t tlf this instruction addresses port Px x 0 3 add 1 state Encoding 0110 1110 5555 0001 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation XRL Rm Rm dir8 XRL 8 Source Mode Bytes 4 3 States 4 3 Encoding 0110 1110 tttt 0101 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation XRL WRJ lt v dir8 XRL Rm dir16 Binary Mode Source Mode Bytes 5 4 States 3 2 A 140 intel INSTRUCTION SET REFERENCE Encoding 0110 1110 5555 0
8. ADDR Match ENDP Match CRC5 Passed RXEP E Endpoint Enabled Yes Yes Yes 1 Yes No X X X No X No X X No X X No X No X X X 0 No A SeeTable 5 7 RX for RX enabled See Table 5 8 for RX ready enable Set up NACK STALL Set up NACK hshk hshk Receive data but do not write to RXFIFO Set R_VOID RXSTATx 2 Done A4199 01 Figure 8 16 SIU Receive Operations for Non isochronous Data Details Part A 8 21 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Table 8 7 Truth Table For RX Enable STL RX RX IE COM Handshake To Return After Data Phase 0 No NACK after data phase 1 Yes Result of data reception 1 0 No STALL after data phase 1 1 No STALL after data phase Table 8 8 Truth Table For RX Ready RX Ready RXSPM RXFIFO Condition Sampled End Of Token Phase No 0 FIF 1 0 11 OVF lt gt WM Yes 0 FIF 1 0 11 amp Not OVF amp Not URF amp WP WM No 1 FIF 1 0 01 OVF WP lt gt WM Yes 1 FIF 1 0 00 amp Not OVF amp Not amp WP WM Table 8 9 Truth Table For RXFIFO Error RXFIFO Error RXFIFO Condition Checked After Every Write In Data Phase No Not OVF Yes OVF Table 8 10 RX Status Interpretation On R ERR R ERR Bit OVF Bit Interpretation 1 0 Data failed CRC check 1 Incomplete data reception data packet ov
9. Add to the TIME column Binary Source Case 1 Case 2 Case 3 ORL CY bit51 1 1 2 3 4 ORL dir8 data 3 3 2 3 4 ORL dir8 A 2 2 4 6 8 ORL Rm dir8 3 2 2 3 4 SETB bit 4 3 4 6 8 SETB bit51 2 2 4 6 8 SUB Rm dir8 3 2 2 3 4 SUBB A dir8 1 1 2 3 4 A dir8 3 3 4 6 8 XRL A dir8 1 1 2 3 4 XRL dir8 data 3 3 4 6 8 XRL dir8 A 2 2 4 6 8 XRL Rm dir8 3 2 2 3 4 tel intel INSTRUCTION SET REFERENCE A 3 2 Instruction Summaries Table A 19 Summary of Add and Subtract Instructions Add ADD lt dest gt lt sre gt dest dest src Subtract SUB lt dest gt lt src gt dest opnd dest opnd src opnd Add with Carry Subtract with Borrow ADDC lt dest gt lt src gt SUBB lt dest gt lt src gt lt src carry bit A A src opnd carry bit Binary Mode Source Mode Mnemonic lt dest gt lt src gt Notes Bytes States Bytes States A Rn Reg to acc 1 1 2 2 ABD A dir8 Dir byte to acc 2 1 2 2 1 2 A Ri Indir addr to acc 1 2 2 3 Immediate data to 2 1 2 1 Rmd Rms Byte reg to from byte reg 3 2 2 1 WRjd WRjs Word reg to from word reg 3 3 2 2 DRkd DRks Dword reg to from dword reg 3 5 2 4 Rm data Immediate 8 bit data to from byte reg 4 3 3 2 WRij data16 Immediate 16 bit data to from word reg 5 4 4 3 ADD DRk 0d
10. terne recreo ne Pere 6 10 6 8 INTERRUPT PROCESSING 6 13 6 8 1 Minimum Fixed Interrupt Time essem emm 6 14 6 8 2 Variable Interrupt Parameters 2 6 14 6 8 2 1 Response Time Variables 4044400 0 0 0 6 15 6 8 2 2 Computation of Worst case Latency With Variables 6 16 6 8 2 3 Latency Calculations 2 6 8 2 4 Blocking 6 18 6 8 2 5 Interrupt Vector Cycle ete derer ede neces 6 18 6 8 3 RILCHLIBdIe ELE 6 19 CHAPTER 7 UNIVERSAL SERIAL BUS 7 1 USB EIEOQS e rre mene ect 7 1 7 2 TRANSMIT ied ier lee eee 7 1 7 2 1 Transmit rte Fes Ope wid asda en ain 7 1 7 2 2 Data and Byte Count Registers sess eee eem emere 7 8 7 2 3 Data Managerment rete tree oto oec aei eed ur 7 8 7 2 4 Transmit FIFO Registers ni eere cervi terit aee 7 7 7 3 RECEIVE FIFOS i onore te ete em cire e 7 12 7 8 1 Receive FIFO OVervIQW dir De in aes na 7 12 7 4 SERIAL BUS INTERFACE UNIT 7 21 7 4 1 Serial Bus Manager SBM i eiie ee ie eto rn dues 7 21 7 4 2 Serial Bus Interface Engine SIE
11. after token phase None proceed to data phase No STALL after token phase No STALL after token phase Table 8 3 Truth Table For Transmit Ready TX Ready TXFIFO Condition Sampled End Of Token Phase No FIF 1 0 00 OVF lt gt RM Yes FIF 1 0 lt gt 00 amp Not OVF amp Not URF amp RP RM Table 8 4 Truth Table For TXFIFO Error TXFIFO Error TXFIFO Condition Checked After Every Read In Data Phase No Not URF Not underrun Yes URF Underrun Table 8 5 TX Status Interpretation On T ERR T ERR Bit URF Bit Interpretation 1 0 Data failed CRC check at the host 1 Incomplete data transmission TXFIFO underrun by TX 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Toggle SEQ Toggle SEQ bit TXSTATX 7 Update TX status TXSTATx Set TXDx Set TXD interrupt flag SBIFLG 2x TXD interrupt 1 enabled SBIE 2x y Generate TXD interrupt Done A4194 01 Figure 8 8 SIU Transmit Operations for Non isochronous Data Details Part 2 8 12 intel USB OPERATING MODES 8 2 3 2 SIU Transmit Isochronous Data For isochronous data data packets are not retransmitted following a bad transmission Accord ingly the SIU does not respond to the handshake does not toggle the SEQ bit and does
12. 14 2 2 14 3 1 Entering Idle 14 3 2 Exiting Idle Mode 1441 Entering Powerdown Mode sss emen 14 4 2 Exiting Powerdown Mode 14 5 ON CIRCUIT EMULATION ONCE MODE GU e eu e o Ld viii intel CONTENTS 14 5 1 Entering ONCE Mode enm aee dei eee 14 7 14 5 2 Exiting ONCE Mode 2 14 7 CHAPTER 15 EXTERNAL MEMORY INTERFACE 15 2 EXTERNAL BUS CYCLES SA WH FC 15 21 Bus Cycle Definitlons Pn Cete 15 3 15 2 2 Nonpage Mode Bus 5 9 15 2 3 Mode Bus Cycles gu 15 3 EXTERNAL BUS CYCLES WITH WAIT STATES beds id ats To 15 3 1 Extending RD WR PSEN MINORE OUEST ALSO 2 15 8 2 Extending ALE ds a 15 9 15 4 CONFIGURATION BYTE BUS 1 D 9 15 5 PORTO AND PORT 2 STATUS taran naian uen nre enne 15 10 15 5 1 Port 0 and Port 2 Pin Status Nonpage Mode 15 11 15 5 2 Port 0 and Port 2 Pin Status in Page Mode eee 15 11 15 6 EXTERNAL MEMORY DESIGN EXAMPLES esee 15 11 15 6 1 Example 1
13. 7 27 7 4 2 1 USB interface ocv cero iet eo 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel CHAPTER 8 USB OPERATING MODES 8 1 OVERVIEW OF OPERATING nens 8 1 8 1 1 82930A Unenumerated Mode 2 8 2 8 1 2 82930A outset 8 2 8 1 3 Transmit and Receive Modes 8 2 8 2 TRANSMIT OPERATIONS e t ere re ev rae tee i ded e dra as 8 2 8 2 1 Overview EE o 8 2 2 Transmit Request ISR E A EU RE EE cet ee OS 8 23 SIU Transmit Operations 8 2 3 1 SIU Transmit Non isochronous Data T bE Me 8 7 8 2 3 2 SIU Transmit Isochronous Data 8 13 8 2 4 Post transmit Operations 8 15 8 3 RECEIVE 65 nene enne se rene 8 18 8 3 1 OVerViIeW cc et tendo tue ud e unti UU EM 8 18 8 3 2 SIU Receive Operations nnnm 8 19 8 3 2 1 SIU Receive Non isochronous Data 8 19 8 3 2 2 SIU Receive Isochronous Data 8 24 8 3 3 Post receive Operations 4 4 4 8 27 8 4 SIU OPERATIONS FOR A SETUP 8 31 8 5 SIU OPERAT
14. R15 i e the range of m is 0 15 Table 5 2 summarizes the notation used for the register indices When an instruction contains two registers of the same type e g MOV Rmd Rms the first index denotes destination and the second index s denotes source 5 2 3 Address Notation In the 82930A architecture memory addresses include a region number 00 01 FF Figure 3 4 SFR addresses have a prefix 8 S 000H S 1FFH The distinction between memory ad dresses and SFR addresses is necessary because memory locations 00 0000H 00 01FFH and SFR locations S 000H S 1FFH can both be directly addressed in an instruction 5 2 INSTRUCTIONS AND ADDRESSING Memory 200H 201H A3H 202H Register File 0 1 2 3 4 5 6 7 eT T Low mpm WRO Contents of register file and memory after execution rae MOV WRO A3B6H MOV 00 0201H WRO MOV DR4 0000C4D7H DR4 A4242 01 Figure 5 1 Word and Double word Storage in Big Endien Form Table 5 2 Notation for Byte Registers Word Registers and Dword Registers eoa Register Destination Sou rce Register Range ype Symbol Register Register Ri RO R1 Byte Rn RO R7 Rm Rmd Rms RO R15 Word WRj WRid WRjs WRO WR2 WR30 Dword DRk DRkd DRks DRO DR4 DR8 DR28 DR56 DR60 Instructions in the MCS 51 architecture use 80 as a
15. Figure 10 5 TMOD Timer Counter Mode Control Register 10 7 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel TCON Address 5 88 Reset State 0000 0000B 7 0 TF1 TR1 TFO TRO IE1 IT1 IEO ITO Bit Bit Number Mnemonic Function 7 TF1 Timer 1 Overflow Flag Set by hardware when the timer 1 register overflows Cleared by hardware when the processor vectors to the interrupt routine 6 TR1 Timer 1 Run Control Bit Set cleared by software to turn timer 1 on off 5 TFO Timer 0 Overflow Flag Set by hardware when the timer 0 register overflows Cleared by hardware when the processor vectors to the interrupt routine 4 TRO Timer 0 Run Control Bit Set cleared by software to turn timer 1 on off 3 IE1 Interrupt 1 Flag Set by hardware when an external interrupt is detected on the INT1 pin Edge or level triggered see IT1 Cleared when interrupt is processed if edge triggered 2 IT1 Interrupt 1 Type Control Bit Set this bit to select edge triggered high to low for external interrupt 1 Clear this bit to select level triggered active low 1 IEO Interrupt 1 Flag Set by hardware when an external interrupt is detected on the INTO pin Edge or level triggered see ITO Cleared when interrupt is processed if edge triggered 0 ITO Interrupt O Type Control Bit Set this bit to select edge triggered high to low for external interrupt 0 C
16. 1 4 1 How to Use Intel s FaxBack seice 1 7 1 4 2 How to Use Intel s Application BBS 1 8 1 4 3 How to Find the Latest ADBUILDER Files and Hypertext Manuals and Data Sheets on the BBS 88 1 8 CHAPTER 2 INTRODUCTION 2 1 PRODUCT OVERVIEW nene tent entere ca e Cede D cedere deter 2 3 2 2 82930A FEAT U RE n eh o e HUE ES 2 5 2 3 MCS 251 MICROCONTROLLER 2 6 2 3 2 ahd Reset Unit n 2 7 2 3 3 InterruptiHandler cest i meo dece nde ht Ped t ret 2 7 2 4 ON CHIP PERIPHERALS an erected ee ttis iie 4010 2 4 1 Universal Serial eere e hee rer e endende 2 8 2 4 2 Timer Counters and Watchdog TimMer 2 8 2 4 3 Programmable Counter Array 2 8 244 5 arret tesi do tus a e utc a elei 2 9 2 5 OPERATING CONDITIONS te esistente 229 CHAPTER 3 82930A MEMORY PARTITIONS 3 1 ADDRESS SPACES FOR 82930 mne eene 3 1 3 1 1 Compatibility with the MCS 51 Architecture 2 0 3 2 3 2 82930A MEMORY SPAGE n n eei e la ee eel 3 5 3 2 1 On chip General purpose Data RAM seen 378 3 2 2 External Memory 3
17. Figure 6 2 SBI USB Event Register intel INTERRUPTS 6 6 INTERRUPT ENABLE Each interrupt source with the exception of TRAP may be individually enabled or disabled by the appropriate interrupt enable bit in the IEO register at S A8H see Figure 6 3 or the register at S B1H Note IEO also contains a global disable bit EA If EA is set interrupts are individually enabled or disabled by bits in IEO If EA is clear all interrupts are disabled IEO Address S A8H Reset State 0000 0000B 7 0 EA EC ET2 ES ETO Bit Bit Function Number Mnemonic 7 EA Global Interrupt Enable Setting this bit enables all interrupts that are individually enabled by bits 0 6 Clearing this bit disables all interrupts except the TRAP interrupt which is always enabled 6 EC PCA Interrupt Enable Setting this bit enables the PCA interrupt 5 ET2 Timer 2 Overflow Interrupt Enable Setting this bit enables the timer 2 overflow interrupt 4 ES Serial I O Port Interrupt Enable Setting this bit enables the serial I O port interrupt 3 ET1 Timer 1 Overflow Interrupt Enable Setting this bit enables the timer 1 overflow interrupt 2 EX1 External Interrupt 1 Enable Setting this bit enables external interrupt 1 1 Timer 0 Overflow Interrupt Enable Setting this bit enables the timer 0 overflow interrupt 0 EXO External Interrupt O Enable Setting this
18. 0000 0100 Binary Mode Encoding Source Mode Encoding INC A lt 1 Binary Mode Source Mode 2 2 intel States Encoding Hex Code in Operation INC Bytes States Encoding Hex Code in Operation INC Rn Bytes States Encoding Hex Code in Operation 21 INSTRUCTION SET REFERENCE 21 tlf this instruction addresses a port x 0 3 add 2 states 0000 0101 direct addr Binary Mode Encoding Source Mode Encoding INC dir8 dir8 1 Binary Mode Source Mode 1 2 3 4 0000 011i Binary Mode Encoding Source Mode A5 Encoding INC Ri lt Ri 1 Binary Mode Source Mode 1 2 1 2 0000 dirrr Binary Mode Encoding Source Mode A5 Encoding INC Rn lt Rn 1 INC dest src Function Description Flags Increment Increments the specified variable by 1 2 or 4 An original value of OFFH overflows to OV N 2 65 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Example Register O contains 7EH 011111110B After executing the instruction INC RO 1 register 0 contains 7FH Variations INC Rm short Binary Mode Source Mode Bytes 3 2 States 2 1 Encoding 00
19. 15 The source address is a byte word or dword The two architectures do indirect addressing via different registers MCS 251 architecture Memory is indirectly addressed via word and dword registers Word register j 0 2 4 30 The 16 bit address in can access locations 00 0000H 00 FFFFH Dword register 0 4 8 28 56 and 60 The 24 least significant bits can access the entire 16 Mbyte address space The upper eight bits of DRk must be 0 If you use DR60 as a general data pointer be aware that DR60 is the extended stack pointer register SPX MCS 51 architecture Instructions use indirect addressing to access on chip RAM code memory and external data RAM See the second note on page 5 4 regarding the region of external data RAM that is addressed by instructions in the MCS 51 architecture Byte register Ri i 1 2 Registers RO and indirectly address on chip memory locations 00H FFH and the lowest 256 bytes of external data RAM 16 bit data pointer DPTR A DPTR The MOVC and instructions use these indirect modes to access code memory and external data RAM 16 bit program counter The MOVC instruction uses this indirect mode to access code memory 5 6 intel INSTRUCTIONS AND ADDRESSING Table 5 4 Addressing Modes for Data Instructions in the MCS 251 Architecture Address Range of Assembly Lang
20. OV N 2 The accumulator contains 5CH 01011100B instruction CLRA clears the accumulator to 00H 00000000B Binary Mode Source Mode 1 1 1 1 1110 0100 Binary Mode Encoding Source Mode Encoding CLR 0 Clear bit Clears the specified bit CLR can operate on the CY flag or any directly addressable bit A 45 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Flags Example Variations CLR bit51 Bytes States Encoding Hex Code in Operation CLR CY Bytes States Encoding Hex Code in Operation CLR bit Bytes A 46 intel Only for instructions with CY as the operand OV N 2 z Port 1 contains 5DH 01011101B After executing the instruction CLR P1 2 port 1 contains 59H 01011001B Binary Mode Source Mode 4 3 2t 2t tlf this instruction addresses a port Px x 0 3 add 2 states 1100 0010 Bit addr Binary Mode Encoding Source Mode Encoding CLR bitb1 0 Binary Mode Source Mode 1 1 1 il 1100 0011 Binary Mode Encoding Source Mode Encoding CLR CY 0 Binary Mode Source Mode 4 4 intel INSTRUCTION SET REFERENCE States 4T 3t tlf this instruction addresses a port x 0 3 add 2 states Encoding 1010 1001 1100 0 yy
21. block diagram in Figure 10 1 depicts the basic logic of the timers Here timer registers THx TLx x 0 1 and 2 connect in cascade to form a 16 bit timer Setting the run control bit TRx tums the timer on by allowing the selected input to increment TLx When TLx overflows it increments THx when overflows it sets the timer overflow flag in the TCON or T2CON register Setting the run control bit does not clear the THx and TLx timer registers The timer registers can be accessed to obtain the current count or to enter preset values Timer 0 and timer 1 can also be controlled by external pin INTx to facilitate pulse width measurements 10 1 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Table 10 1 Timer Counter and Watchdog Timer SFRs Mnemonic Description Address TLO Timer 0 Timer Registers Used separately as 8 bit counters or in cascade S 8AH THO as a 16 bit counter Counts an internal clock signal with frequency 12 S 8CH timer operation or an external input event counter operation TL1 Timer 1 Timer Registers Used separately as 8 bit counters or in cascade S 8BH TH1 as a 16 bit counter Counts an internal clock signal with frequency Fosc 12 S 8DH timer operation or an external input event counter operation TL2 Timer 2 Timer Registers TL2 and TH2 connect in cascade to provide a S CCH TH2 16 bit counter Counts an internal clock signal with
22. 000 0 000 0 000 00 1000 00 1000 00xx1000 00xx1000 CCON CMOD CCAPMO CCAPM1 CCAPM2 CCAPM3 CCAPM4 DF 00000000 00xxx000 x0000000 x0000000 x0000000 x0000000 x0000000 PSW PSW1 SOFL SOFH RXCONO 1 RXCON2 RXCON3 D7 00000000 00000000 00000000 00000000 0xx00000 0 00000 0 00000 0 00000 T2CON T2MOD RCAP2L RCAP2H TL2 TH2 CF 00000000 00 00000000 00000000 00000000 00000000 EPCON1 RXDATO RXDAT1 RXDAT2 RXDAT3 C7 00101111 00001111 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX IPLO SADEN EPCON2 SPH BF x0000000 00000000 00001111 00001111 00000000 P3 IE1 IPH1 IPHO B7 11111111 00000000 00000000 00000000 x0000000 IEO SADDR TXCNTO TXCNT1 TXCNT2 TXCNT3 AF 00000000 00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX P2 SBIE TXFLGO TXFLG1 TXFLG2 TXFLG3 WDTRST A7 11111111 00000000 00xx1000 00xx1000 00xx1000 00xx1000 XXXXXXXX SCON SBUF TXCONO TXCON1 TXCON2 TXCON3 9F 00000000 XXXXXXXX 0 0000 0 0000 0 0000 0 0000 1 SBI TXDATO TXDAT1 TXDAT2 TXDAT3 97 11111111 00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX TCON TMOD TLO TL1 THO TH1 FADDR 8F 00000000 00000000 00000000 00000000 00000000 00000000 00000000 SP DPL DPH DPXL DPXH PCON 87 11111111 00000111 00000000 00000000 00000001 00000000 00xx0000 RESERVED intel 82930A MEMORY PARTITIONS The following tables list the mnemonics names and addresses of the SFRs Table 3 5 Core SFRs Table 3 6 I O Port SFR
23. Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation JNB PC 3 IF bit 2 0 THEN PC PC rel JNC rel Function Jump if carry not set Description If the CY flag is clear branch to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice to point to the next instruction The CY flag is not modified A 74 intel Flags Example Bytes States Encoding Hex Code in Operation JNE rel Function Description Flags Example Bytes States Encoding INSTRUCTION SET REFERENCE 2 The CY flag is set instruction sequence JNC LABEL1 CPL CY JNC LABEL2 clears the CY flag and causes program execution to continue at label LABEL2 Binary Mode Source Mode Not Taken Taken Not Taken Taken 2 2 2 2 1 4 1 4 0101 0000 rel addr Binary Mode Encoding Source Mode Encoding JNC PC PC 2 IF CY 0 THEN PO rel Jump if not equal If the Z flag is clear branch to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice
24. 0100 Binary Mode Encoding Source Mode Encoding MUL A low byte of A X B lt high byte of A X B No operation Execution continues at the following instruction Affects the PC register only intel Flags Example Bytes States Encoding Hex Code in Operation INSTRUCTION SET REFERENCE OV N 2 You want to produce a low going output pulse on bit 7 of Port 2 that lasts exactly 11 states simple CLR SETB sequence generates an eight state pulse Each instruction requires four states to write to a port SFR You can insert three additional states if no interrupts are enabled with the following instruction sequence CLR P2 7 NOP NOP NOP SETB 2 7 Binary Mode Source Mode 1 1 1 1 0000 0000 Binary Mode Encoding Source Mode Encoding NOP PC lt 1 ORL dest src Function Description Flags Example Logical OR for byte variables Performs the bitwise logical OR operation V between the specified variables storing the results in the destination operand The destination operand can be a register an accumulator or direct address The two operands allow twelve addressing mode combinations When the destination is the accumulator the source can be register direct register indirect or immediate addressing when the destination is a direct address the source can
25. 82930 Universal Serial Bus Microcontroller User s Manual January 1996 Information this document is provided in connection with Intel products Intel assumes liability whatsoever including in fringement of any patent or copyright for sale and use of Intel products except as provided in Intel s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcontroller products may have minor variations to this specification known as errata Other brands and names are the property of their respective owners Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained from Intel Corporation Literature Sales P O Box 7641 Mt Prospect IL 60056 7641 or call 1 800 548 4725 COPYRIGHT INTEL CORPORATION 1996 intel CONTENTS CHAPTER 1 GUIDE TO THIS MANUAL 1 1 MANUAL CONTENTS iterare tr er cue de dete ne 1 1 1 2 NOTATIONAL CONVENTIONS AND TERMINOLOGY 1 3 1 3 RELATED e yeei en nene enne erre 1 5 1 3 1 Data Sheet iem e cce noii ee pP 1 5 1 4 CUSTOMER SERVICE
26. 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Table 4 2 Memory Signal Selections RD1 0 intel RD1 0 P1 7 CEX A17 P3 7 RD A16 PSEN WR Features 00 17 A16 Asserted for Asserted for writes to 256 Kbyte external all addresses all memory locations memory 01 P1 7 CEX4 A16 Asserted for Asserted for writes to 128 Kbyte external all addresses all memory locations memory 1 0 P1 7 CEX4 P3 7 only Asserted for Asserted for writes to 64 Kbyte external all addresses all memory locations memory One additional port pin 1 1 P1 7 CEX4 RD asserted Asserted for Asserted only for 64 Kbyte external for addresses gt 80 0000H writes to MCS 51 memory Compatible lt 7F FFFFH microcontroller data with MCS 51 memory locations microcontrollers 4 4 CONFIGURING THE EXTERNAL MEMORY INTERFACE This section describes the configuration options that affect the external memory interface The configuration bits described here determine the following interface features page mode or mode the number of external address pins 16 17 or 18 RD1 0 the memory regions assigned to the read signals RD and PSEN RDI 0 the external wait states WSA1 0 WSB1 0 WSA XALE 4 4 4 Page Mode and Nonpage Mode PAGE The bit UCONFIGO 1 selects page mode or nonpage mode code fetches and deter mines whether data is transmit
27. OV N 2 The instruction JNE LABEL 1 causes program execution to continue at LABEL 1 if the Z flag is clear Binary Mode Source Mode Not Taken Taken Not Taken Taken 3 3 2 2 2 5 1 4 0111 1000 A 75 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Hex Code in Operation JNZ rel Function Description Flags Example Bytes States Encoding Hex Code in Operation JSG rel Function A 76 Binary Mode A5 Encoding Source Mode Encoding JNE lt 2 IF Z 0 THEN PO rel Jump if accumulator not zero If any bit of the accumulator is set branch to the specified address otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice The accumulator is not modified OV N 2 The accumulator contains OOH After executing the instruction sequence JNZ LABEL1 INCA JNZ LABEL2 the accumulator contains 01H and program execution continues at label LABEL2 Binary Mode Source Mode Not Taken Taken Not Taken Taken 2 2 2 2 2 5 2 5 0111 0000 rel addr Binary Mode Encoding Source Mode Encoding JNZ PC 2 IF A 0 THEN lt PC rel Jump if greater than signe
28. 0011 0011 Binary Mode Encoding Source Mode Encoding RLC 1 lt 0 CY A 7 Rotate accumulator right Rotates the 8 or 16 bits the accumulator one bit to the right Bit 0 is moved into the bit 7 or 15 position OV N 2 accumulator contains 0C5H 11000101 After executing the instruction RRA the accumulator contains OE2H 11100010B and the CY flag is unaffected Binary Mode Source Mode 1 1 1 1 0000 0011 Binary Mode Encoding Source Mode Encoding RR lt A a41 7 lt 0 121 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Function Description Flags Example Bytes States Encoding Hex Code in Operation SETB lt bit gt Function Description Flags Example SETB bit51 A 122 intel Rotate accumulator right through carry flag Rotates the eight bits in the accumulator and the CY flag one bit to the right Bit 0 moves into the CY flag position the original value of the CY flag moves into the bit 7 position OV N 2 The accumulator contains 0C5H 11000101B and the CY flag is clear After executing the instruction RRCA the accumulator contains 62 01100010B and the CY flag is set Binary Mode Source Mode 1 1 1 1 0001 0011 Binary
29. 5 8 5 3 3 Logical Instr ctlOns 2 dei Ree dive ee 5 9 5 3 4 Data Transfer 5 9 5 4 BIT INSTRUCTIONS 2 0222 0 01 0 eene nee nnn nias sensn seti rin nnn 5 10 5 4 1 Bit Addressing net deduc eee dee 5 10 5 5 CONTROL INSTRUCTIONS sssssesssssseseen ener nenne teneret nen terere 5 11 intel CONTENTS 5 5 1 Addressing Modes for Control Instructions 2 11 5 5 2 Conditional Jumps REPE ORE 5 12 5 5 3 Unconditional Jumps eiit rhe Een tte Literie inde tup terat e 5 13 554 ad Returns e ined 5 14 5 6 PROGRAM STATUS WORDS eene 5 14 CHAPTER 6 INTERRUPTS 6 1 OVERVIEW rade pte tee Iu to dence dicet eget ie pr 6 1 6 2 82930A INTERRUPT 5 emere enne 6 3 6 2 1 External Interr pts eene rra ee oid alien 6 3 6 2 2 irmerlntert pts er ih ertet me 65 6 3 PROGRAMMABLE COUNTER ARRAY 6 5 6 4 SERIAL PORT INTERRUPT ioan tremere aes odisea eec rt 6 5 6 5 USB ENDPOINT 5 6 6 6 6 INTERRUPT Dre OFF 6 7 INTERRUPT PRIORITIES
30. 7 0 ECOMx CAPPx CAPNx PWMx Bit Bit Number Mnemonic Function 7 Reserved The value read from this bit is indeterminate Write a zero to this bit 6 ECOMx Compare Modes 1 enables the module comparator function The comparator is used to implement the software timer high speed output pulse width modulation and watchdog timer modes 5 CAPPx Capture Mode Positive CAPPx 1 enables the capture function with capture triggered by positive edge on pin CEXx 4 Capture Mode Negative CAPNx 1 enables the capture function with capture triggered by negative edge on pin CEXx 3 MATx Match Set ECOMx and MAT x to implement the software timer mode When MATx 1 a match of the timer counter with the compare capture register sets the CCFx bit in the CCON register flagging an interrupt 2 TOGx Toggle Set ECOMx MATx and TOGx to implement the high speed output mode When TOGx 1 a match of the timer counter with the compare capture register toggles the CEXx pin 1 PWMx Pulse Width Modulation Mode PWMx 1 configures the module for operation as an 8 bit pulse width modulator with output waveform on the CEXx pin 0 ECCFx Enable CCFx Interrupt Enables compare capture flag CCF x in the CCON register to generate an interrupt request Figure 11 9 CCAPMx PCA Compare Capture Module Mode Registers
31. SP DPL DPH DPXL DPXH PCON 87 11111111 00000111 00000000 00000000 00000001 00000000 00xx0000 RESERVED C 1 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Table C 2 Core SFRs Mnemonic Name Address Accumulator S E0H Bt B register S FOH PSW Program Status Word S DOH PSW1 Program Status Word 1 S D1H SP Stack Pointer LSB of SPX S 81H 5 Stack Pointer High MSB of SPX S BEH DPTR Data Pointer 2 bytes DPL Low Byte of DPTR 5 82 High Byte of DPTR S 83H DPXL Data Pointer Extended Low 5 84 DPXH Data Pointer Extended High S 85H PCON Power Control 5 87 IEO Interrupt Enable Control 0 S A8H IPHO Interrupt Priority Control High 0 S B7H IPLO Interrupt Priority Control Low 0 S B8H SFRs can also be accessed by their corresponding registers in the register file Table C 3 Port SFRs Mnemonic Name Address Port 0 5 80 1 1 5 90 2 Port 2 S A0H P3 Port 3 S BOH intel intel REGISTERS Table C 4 Serial 1 0 SFRs Mnemonic Name Address SCON Serial Control 5 98 SBUF Serial Data Buffer S 99H SADEN Slave Address Mask S B9H SADDR Slave Address S A9H Table C 5 Timer Counter and Watchdog Timer SFRs Mnemonic Name Address TLO Timer Counter 0 Low Byte S 8AH THO Timer Coun
32. Multiplexe Signal A Type Description d Name With A17 Address Line 17 Eighteenth external address bit 17 in extended P1 7 CEX4 bus applications Selected by configuration bits RD1 0 UCONFIGO 3 2 See Table B 4 A16 Address Line 16 Seventeenth external address bit A16 in RD extended bus applications Selected by configuration bits RD1 0 UCONFIGO 3 2 See Table B 4 A15 8 Address Lines Upper address lines of the external bus P2 7 0 7 01 Address Data Lines Multiplexed lower address lines and data lines 0 7 0 of the external bus ALE Address Latch Enable ALE signals the start of an external bus cycle and indicates that valid address information is available on lines 15 8 and AD7 0 An external latch can use ALE to demultiplex the address from the address data bus Mec PWR Analog Vec A separate Voc input for the phase locked loop circuitry CEX4 0 Programmable Counter Array PCA Input Output Leads These P1 6 3 are input signals for the PCA capture mode and output signals forthe P1 7 A17 PCA compare mode and PCA PWM mode t The descriptions of A15 8 P2 7 0 and AD7 0 P0 7 0 are for the nonpage mode chip configuration If the chip is configured for page mode operation port 0 carries the lower address bits A7 0 and port 2 carries the upper address bits A15 8 and the data 07 0 B 3 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Table B 3 Signal Descriptio
33. PSEN code in Mode Data Read 2 ALE RD PSEN data in Data Write 2 ALE WR WRi high data out NOTES 1 Signal timing implied by this table is approximate idealized 2 Data read page mode data read nonpage mode and write page mode write mode except that in page mode data appears on P2 multiplexed with A15 0 whereas in nonpage mode data appears on PO multiplexed with A7 0 3 The initial code read page hit bus cycle can execute only following a code read page miss cycle 15 2 2 Nonpage Mode Bus Cycles In nonpage mode the external bus structure is the same as for MCS 51 microcontrollers The up per address bits A15 8 are on port 2 and the lower address bits A7 0 are multiplexed with the 15 3 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel data D7 0 on port 0 External code read bus cycles execute in approximately two state times See Table 15 2 and Figure 15 2 External data read bus cycles Figure 15 3 and external write bus cycles Figure 15 4 execute in approximately three state times For the write cycle Figure 15 4 a third state is appended to provide recovery time for the bus Note that the write signal WR is asserted for all memory regions except for the case of RD1 0 11 where is assert ed for regions 00 03 but not for regions State 1 State 2 XTAL ALE RD PSEN PO A17 A16 P2 A4282 01 Figure 15 2
34. Receive host hshk Manage SEQ bit Generate TXD Done interrupt 4262 01 Figure 8 2 High level View of Transmit Operations A transmit operation typically begins with an interrupt request from a function e g a keyboard entry The interrupt service routine ISR for that function writes the data from the function to the TXFIFO On the next valid IN token the SIU transmits the data packet through the USB line The second firmware routine checks the transmission status and performs data management tasks Two bits in TXCONXx have a major influence on the transmit operation The ISO bit TXCONx 3 determines whether the transmission is for isochronous data ISO 1 or non isochronous data ISO z 0 For non isochronous data only the SIU receives a handshake from the host toggles or does not toggle the sequence bit and generates a 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel transmission done TXD interrupt Figure 8 2 Also for non isochronous data the post transmit routine is an ISR for isochronous data the post transmit routine can be a normal subroutine or ISR that is initiated by an SOF token The ARM bit TXCONx 2 determines whether the FIFO read marker and read pointer are managed automatically by the FIFO hardware ARM 1 or manually by the second firmware routine ARM 0 8 2 2 Transmit Request ISR Transmitted data comes from functions such as a keyboard mouse
35. S6P2 S6P2 Eee rr Receive mE cr ser S3P1 S6P1 Write to REN CI RI SCON Set Clear S6P2 Shift 55 _ 56 2 56 2 56 2 56 2 4124 02 Figure 12 3 Mode 0 Timing 12 2 1 2 Reception Mode 0 To start a reception in mode 0 write to the SCON register Clear bits SMO 5 and RI and set the REN bit Hardware executes the write to SCON in the last phase S6P2 ofa peripheral cycle Figure 12 3 In the second peripheral cycle following the write to SCON goes low at S3P1 for the first clock signal pulse and the LSB DO is sampled on pin at S5P2 The DO bit is then shift ed into the shift register After eight shifts at S6P2 of every peripheral cycle the LSB D7 is shift ed into the shift register and hardware asserts RI S1P1 to indicate a completed reception Software can then read the received byte from SBUF 12 5 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel 12 2 2 Asynchronous Modes Modes 1 2 and 3 The serial port has three asynchronous modes of operation e Mode 1 Mode 1 is a full duplex asynchronous mode The data frame Figure 12 4 consists of 10 bits one start bit eight data bits and one stop bit Serial data is transmitted on the TXD pin and received on the RXD pin When a message is received the stop bit is read in the 8 bit in the SCON register The baud rate is generated by overflow of timer
36. 01 00 00 0000H External EPROM 64 Kbytes External RAM 1056 Bytes On chip RAM 4175 02 15 18 Figure 15 17 Memory Space for Examples 3 and 4 intel EXTERNAL MEMORY INTERFACE 15 6 4 Example 4 RD1 0 11 16 bit Bus External EPROM and RAM In this example an 82930A operates in page mode with a 16 bit external address bus interfaced to 64 Kbytes of EPROM and 64 Kbytes of RAM Figure 15 18 The 82930A is configured so that RD is asserted for addresses 7F FFFFH and PSEN is asserted for addresses gt 80 0000 This system is the same as Example 5 Figure 15 16 except that it operates in page mode Ac cordingly the two systems have the same memory map Figure 15 17 and the comments on ad dressing external RAM apply here also EPROM RAM 82930A 64 Kbytes 64 Kbytes D7 0 A15 8 D7 0 EA CE WR RD PSEN OE WE A4288 01 Figure 15 18 Bus Diagram for Example 4 82930A in Page Mode 15 19 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel 15 6 5 Example 5 RD1 0 01 17 bit Bus External Flash In this example an 82930A operates in page mode with a 17 bit external address bus interfaced to 128 Kbytes of flash memory Figure 15 19 Port 2 carries both the upper address bits A15 0 and the data D7 0 while port 0 carries only the lower address bits A7 0 The 82930A is con figured for a single read signal PSEN The 128 Kbytes of external
37. 12 The WDTRST special function register at address 5 provides control access to the WDT Two operations control the WDT e Device reset clears and disables the WDT see section 13 4 Reset Writing a specific two byte sequence to the WDTRST register clears and enables the WDT If it is not cleared the WDT overflows on count 3FFFH 1 With Fog 12 MHz a peripheral cycle is 1 us and the WDT overflows in 1 us x 16384 16 384 ms The WDTRST is a write only register Attempts to read it return FFH The WDT itself is not read or write accessible The WDT does not drive the external RESET pin 10 16 intel TIMER COUNTERS AND WATCHDOG TIMER T2CON Address S C8H Reset State 0000 0000B 7 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C T2 CP RL2 Bit Bit Number Mnemonic Function 7 TF2 Timer 2 Overflow Flag Set by timer 2 overflow Must be cleared by software TF2 is not set if RCLK 1 or TCLK 1 6 EXF2 Timer 2 External Flag If EXEN2 1 capture or reload caused by a negative transition on T2EX Sets EFX2 EXF2 does not cause an interrupt in up down counter mode DCEN 1 5 RCLK Receive Clock Bit Selects timer 2 overflow pulses RCLK 1 or timer 1 overflow pulses RCLK 0 as the baud rate generator for serial port modes 1 and 3 4 TCLK Transmit Clock Bit Selects timer 2 overflow pulses TCLK 1 or timer 1 overflow pulses TCLK 0 as the baud rate generator for serial port m
38. 128 Kbytes 128 Kbytes 17 WR A4285 01 Figure 15 12 Bus Diagram for Example 1 82930A in Page Mode 15 12 intel EXTERNAL MEMORY INTERFACE Memory Address Space 512 Kbytes FFFFH FF 0000H 128 Kbytes External Flash FE FD FC 03 02 01 128 Kbytes 1056 Bytes FFFFH External RAM 00 0420H 00 0000H 1056 Bytes On chip RAM 4220 01 Figure 15 13 Memory Space for Example 1 15 6 2 Example 2 RD1 0 z 01 17 bit Bus External Flash and RAM In this example an 82930A operates in page mode with a 17 bit external address bus interfaced to 64 Kbytes of flash memory for code storage and 32 Kbytes of external RAM Figure 15 14 The 82930A is configured so that PSEN is asserted for all reads and RD functions as A16 RD1 0 01 Figure 15 15 shows how the external flash and RAM are addressed in the internal memory space Addresses 0420H 7FFFH in external RAM are addressed in region 00 On chip data RAM 1056 bytes occupies the lowest addresses in region 00 15 13 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel 82930A FLASH 32 Kbytes 64 Kbytes D7 0 D7 0 A15 8 D7 0 4286 01 Figure 15 14 Bus Diagram for Example 2 82930A in Page Mode 15 14 EXTERNAL MEMORY INTERFACE FF FE FD FC 03 02 01 00 00 0000H Memory Address Space 512 K
39. 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel 6 5 USB ENDPOINT INTERRUPTS The 82930A has four interrupts one for each endpoint each triggered by the completion of ei ther a transmission or a reception The SBI register contains eight flags a transmit flag and a re ceive flag for each endpoint A pair of flags share the same interrupt vector The register Figure 6 4 contains the enable bits for the four endpoints and the SBIE register Figure 6 5 contains the enable bits for the eight flags To enable an interrupt for a transmit or receive operation Three bits must be set the transmit enable bit or the receive enable bit in the SBIE register the endpoint enable bit in the IEI register the global enable bit EA in the IEO register SBI Address S 91H Reset State 00H USB Interrupt Register The bits in SBl indicate which event caused an interrupt 7 0 RXD3 TXD3 RXD2 TXD2 RXD1 TXD1 RXDO TXDO Bit Bit Number Function 7 RXD3 6 TXD3 ADS Xx 0 3 E Receive Done Endpoint x Hardware sets this bit indicate that the 5 RXD2 RXFIFO for endpoint x has received data and the 82930A has sent a 4 TXD2 handshake 3 RXD1 XE TXDx x 0 3 2 Transmit Done Endpoint x Hardware sets this bit to indicate that the 1 RXDO TXFIFO for endpoint x has transmitted data and the 82930A has received a 0 TXDO handshake
40. Bytes States Encoding Hex Code in INSTRUCTION SET REFERENCE The Z flag is set After executing the instruction JE LABEL 1 program execution continues at label LABEL1 Binary Mode Source Mode Not Taken Taken Not Taken Taken 3 3 2 2 2 5 1 4 0110 1000 Binary Mode A5 Encoding Source Mode Encoding JE PC 2 IF 2 1 THEN rel Jump if greater than If the Z flag and the CY flag are both clear branch to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice OV N 2 The instruction JG LABEL1 causes program execution to continue at label LABEL 1 if the Z flag and the CY flag are both clear Binary Mode Source Mode Not Taken Taken Not Taken Taken 3 3 2 2 2 5 1 4 0011 1000 rel addr Binary Mode A5 Encoding Source Mode Encoding 71 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Operation JG PC PC 2 2 0 AND CY 0 THEN JLE rel Function Jump if less than or equal Description Ifthe Z flag or the CY flag is set branch to the address specified otherwise proceed with the next instruction The branc
41. Encoding Operation ORL CY lt CY V bit POP src Function Pop from stack Description Reads the contents of the on chip RAM location addressed by the stack pointer then decrements the stack pointer by one The value read at the original RAM location is transferred to the newly addressed location which can be 8 bit or 16 bit Flags CY AC OV N 2 stack pointer contains 32H and RAM locations 30H through 32H contain 01H 23H and 20H respectively After executing the instruction sequence POP DPH POP DPL the stack pointer contains 30H and the data pointer contains 0123H After executing the instruction POP SP the stack pointer contains 20H Note that in this special case the stack pointer was decremented to 2FH before it was loaded with the value popped 20H Variations POP dir8 Binary Mode Source Mode Bytes 2 2 A 114 intel States Encoding Hex Code in Operation POP Rm Bytes States Encoding Hex Code in Operation POP WRj Bytes States Encoding Hex Code in Operation POP DRk Bytes States Encoding Hex Code in Operation 1101 0000 direct addr Binary Mode Encoding Source Mode Encoding POP lt 5 SP SP 1 INSTRUCTION SET REFERENCE Binary Mode Source Mode 3 2 3 2 1101 1010 5555 1000 Binary
42. Operation intel moves the contents of register Rm 01010101B to register WRj i e WRj contains 00000000 01010101B Binary Mode Source Mode 3 2 2 1 0001 1010 tttt 5555 Binary Mode A5 Encoding Source Mode Encoding MOVS WRj 7 0 lt 7 0 WRj 15 8 lt MSB MOVX lt dest gt lt src gt Function Description Flags Example A 102 Move external Transfers data between the accumulator and a byte in external data RAM There are two types of instructions One provides an 8 bit indirect address to external data RAM the second provides a 16 bit indirect address to external data RAM In the first type of MOVX instruction the contents of RO or R1 in the current register bank provides an 8 bit address on port 0 Eight bits are sufficient for external expansion decoding or for a relatively small RAM array For larger arrays any port pins can be used to output higher address bits These pins would be controlled by an output instruction preceding the MOVX In the second type of MOVX instruction the data pointer generates a 16 bit address Port 2 outputs the upper eight address bits from while port 0 outputs the lower eight address bits from DPL For both types of moves in nonpage mode the data is multiplexed with the lower address bits on port 0 In page mode the data is multiplexed with the contents of P2 on port 2 8 bit address or with the upper addres
43. Size Location Addressing Location Indirect using 3 Code 64 Kbytes 0000H FFFFH MOVC instr FF 0000H FF FFFFH Indirect using External Data 64 Kbytes 0000H FFFFH MOVX instr 01 0000H 01 FFFFH 128 bytes 00H 7FH Direct Indirect 00 0000H 00 007FH Internal Data 128 bytes 80H FFH Indirect 00 0080H 00 00FFH SFRs 128 bytes S 80H S FFH Direct 5 080 5 0 Register File 8 bytes RO R7 Register RO R7 intel 82930A MEMORY PARTITIONS The 64 Kbyte external data memory for MCS 51 microcontrollers is mapped into the memory region specified by bits 16 23 of the data pointer DPX i e DPXL DPXL is accessible as register file location 57 and also as the SFR at S 084H see section 3 3 2 Dedicated Registers The re set value of DPXL is 01H which maps the external memory to region 01 as shown in Figure 3 3 You can change this mapping by writing a different value to DPXL A mapping of the MCS 51 microcontroller external data memory into any 64 Kbyte memory region in the MCS 251 archi tecture provides complete run time compatibility because the lower 16 address bits are identical in the two address spaces 256 bytes of on chip data memory for MCS 51 microcontrollers 00H FFH are mapped to addresses 00 0000H 00 00FFH to ensure complete run time compatibility In the MCS 51 archi tecture the lower 128 bytes 00H 7FH are directly and indirectly addressable however the up per 128 bytes are accessible by indirect addressing
44. Source mode and Binary mode refer to the two ways of assigning opcodes to the instruction set of the 82930 Depending on the application one mode or the other may produce more efficient code The mode is established during device reset based on the value of the SRC bit in configu ration byte UCONFIGO For information regarding the selection of the opcode mode see section 4 5 Opcode Configurations SRC 5 2 PROGRAMMING FEATURES OF THE 82930A ARCHITECTURE instruction set for 82930A microcontrollers provides the user with instructions that exploit the features of the MCS 251 architecture while maintaining compatibility with the instruction set for MCS 51 microcontrollers Many of the MCS 251 architecture instructions operate on 8 bit 16 bit or 32 bit operands In comparison with 8 bit and 16 bit operands 32 bit operands are ac cessed with fewer addressing modes This capability increases the ease and efficiency of pro gramming the 82930A microcontroller in a high level language such as C The instruction set is divided into data instructions bit instructions and control instructions These are described in this chapter Data instructions process 8 bit 16 bit and 32 bit data bit in structions manipulate bits and control instructions manage program flow 5 2 4 Data Types Table 5 1 lists the data types that are addressed by the instruction set Words or dwords double Words can be in stored memory starting at any byte a
45. The state time is divided into phase 1 and phase 2 82930A peripherals operate on a peripheral cycle which is six state times A one clock in terval in a peripheral cycle is denoted by its state and phase For example the PCA timer is in cremented once each peripheral cycle in phase 2 of state 5 denoted as S5P2 The reset unit places the 82930A into a known state chip reset is initiated by asserting the RST pin or allow ing the watchdog timer to time out see Chapter 13 Minimum Hardware Setup Phase 1 Phase 2 P1 P2 XTAL1 2 State Time State 1 State 2 State 3 State 4 State 5 State 6 P1 1 2 P1 P2 P1 1 2 P1 P2 P1 P2 P1 P2 Peripheral Cycle Figure 2 5 Clocking Definitions 2604 02 2 3 8 Interrupt Handler The interrupt handler can receive interrupt requests from eleven maskable sources and the TRAP instruction When the interrupt handler grants an interrupt request the CPU discontinues the nor mal flow of instructions and branches to a routine that services the source that requested the in terrupt You can enable or disable the interrupts individually except for TRAP and you can assign one of four priority levels to each interrupt See Chapter 6 Interrupts for a detailed de scription 2 7 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel 2 3 4 RAM 82930 has 1 Kbyte of on chip data RAM at lo
46. and FF This selection provides a 128 Kbyte external address space The advantage of this selection in comparison with the 256 Kbyte external memory space with RD1 0 00 is the availability of pin P1 7 CEX4 for general I O or PCA I O I O P3 7 is unavailable All four 64 Kbyte regions are strobed by PSEN and WR Chapter 15 External Memory Interface shows examples of memory designs with this option 4 7 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel RD1 0 00 18 external address bits PO P2 A16 A17 Notes 1 Maximum external memory 2 Single read signal RD1 0 01 17 external address bits PO P2 A16 Note Single read signal Internal Memory with Read Write Signals PSEN WR Internal Memory with Read Write Signals External Memory 256 Kbytes A17 16 11 03 FF 10 02 FE 01 01 FD 00 00 FC External Memory 128 Kbytes 01 03 FD FF 00 02 FC FE A4218 01 Figure 4 4 Internal External Memory Mapping RD1 0 00 and 01 tel DEVICE CONFIGURATION RD1 0 10 16 external address bits PO P2 Notes 1 Single read signal 2 P3 7 RD A16 functions only as P3 7 RD1 0 11 16 external address bits P2 Notes 1 Compatible with MCS 51 microcontrollers 2 Cannot write to regions FC FF Internal Memory and Read Write Signals Internal Memory and Read Write Signals 64 Kbytes
47. bitb1 0 PC PC rel JC rel A 69 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Function Description Flags Example Bytes States Encoding Hex Code in Operation JE rel Function Description Flags A 70 Jump if carry is set If the CY flag is set branch to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice OV N 2 The CY flag is clear After the instruction sequence JC LABEL 1 CPL CY JC LABEL 2 the CY flag is set and program execution continues at label LABEL2 Binary Mode Source Mode Not Taken Taken Not Taken Taken 2 2 2 2 1 4 1 4 0100 0000 rel addr Binary Mode Encoding Source Mode Encoding JC PC 2 IF 1 THEN lt rel Jump if equal If the Z flag is set branch to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice OV N 2 intel Example Bytes States Encoding Hex Code in Operation JG rel Function Description Flags Example
48. less than or equal X For each relation there are two instructions one for signed operands and one for unsigned oper ands Table 5 9 Table 5 9 Compare conditional Jump Instructions Operand Relation gt lt Unsigned JG JL JGE JLE JE JNE Signed JSG JSL JSGE JSLE 5 5 3 Unconditional Jumps There are five unconditional jumps NOP and SJMP jump to addresses relative to the program counter AJMP LJMP and EJMP jump to direct or indirect addresses NOP No Operation is an unconditional jump to the next instruction SJMP Short Jump jumps to any instruction within 128 to 127 of the next instruction AJMP Absolute Jump changes the lowest 11 bits of the PC to jump anywhere within the current 2 Kbyte block of memory The address can be direct or indirect LJMP Long Jump changes the lowest 16 bits of the PC to jump anywhere within the current 64 Kbyte region EJMP Extended Jump changes all 24 bits of the PC to jump anywhere in the 16 Mbyte address space The address can be direct or indirect 5 13 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel 5 5 4 Calls and Returns The 82930A architecture provides relative direct and indirect calls and returns ACALL Absolute Call pushes the lower 16 bits of the next instruction address onto the stack and then changes the lower 11 bits of the PC to the 11 bit address specified by the instruc
49. 11 16 intel 12 Serial I O Port 12 SERIAL I O PORT The serial input output port supports communication with modems and other external peripheral devices This chapter provides instructions on programming the serial port and generating the se rial I O baud rates with timer 1 and timer 2 12 1 OVERVIEW The serial I O port provides both synchronous and asynchronous communication modes It oper ates as a universal asynchronous receiver and transmitter UART in three full duplex modes modes 1 2 and 3 Asynchronous transmission and reception can occur simultaneously and at different baud rates The UART supports framing bit error detection multiprocessor communi cation and automatic address recognition The serial port also operates in a single synchronous mode mode 0 The synchronous mode mode 0 operates at a single baud rate Mode 2 operates at two baud rates Modes 1 and 3 operate over a wide range of baud rates which are generated by timer 1 and timer 2 Baud rates are detailed in section 12 6 Baud Rates The serial port signals are defined in Table 12 1 and the serial port special function registers are described in Table 12 2 Figure 12 1 is a block diagram of the serial port For the three asynchronous modes the UART transmits on the TXD pin and receives on the RXD pin For the synchronous mode mode 0 the UART outputs a clock signal on the TXD pin and sends and receives messages on the RXD pi
50. A 18 A 24 CMOD 3 16 11 13 C 4 C 11 interrupts 6 5 Index 1 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL CMP instruction 5 8 5 13 A 16 Code fetches external 15 1 15 5 internal 15 5 page hit and page miss 15 5 page mode 15 5 Code memory MCS 51 architecture 3 3 See also On chip code memory External code memory Compatibility MCS 251 and MCS 51 architectures 3 2 3 5 address spaces 3 2 3 4 external memory 3 5 instruction set 5 1 SFR space 3 5 See also Binary and source modes Configuration array 4 1 external 4 3 bits 4 2 external memory 4 6 overview 4 1 Configuration bytes bus cycles 15 9 UCONFIGO table 4 4 UCONFIGI table 4 5 Control instructions 5 11 5 14 addressing modes 5 11 5 12 table of A 25 Core 2 6 SFRs 3 15 C 2 CPL instruction 5 9 5 10 A 18 A 24 CPU 2 6 block diagram 2 6 Crystal for on chip oscillator 13 2 CY flag 5 16 5 17 D DA instruction A 17 Data instructions 5 4 5 10 addressing modes 5 4 Data pointer See DPH DPL DPTR DPX DPXL Data transfer instructions 5 9 5 10 table of A 23 See also Move instructions Index 2 intel Data types 5 1 DEC instruction 5 8 A 16 Destination register 5 3 dirl6 3 dir8 A 3 Direct addressing 5 4 in control instructions 5 12 Displacement addressing 5 4 5 7 DIV instruction 5 8 A 17 Division 5 8 DJNZ instruction A 26 Documents related 1 5 DPH DPL 3 13 C 12 as SFRs 3 15 C
51. Additional State Times Add to the BASE_TIME column Binary Source Case 1 Case 2 Case 3 ADD A dir8 1 1 A ADD 8 ADDC A dir8 ANL A dir8 ANL CY bit ANL CY bit51 ANL CY bit ANL CY bit51 ANL dir8 data ANL dir8 A ANL Rm dir8 CLR bit CLR bit51 CMP Rm dir8 CPL bit CPL bit51 DEC dir8 INC dir8 AR WO mM HR M DM WI NINI NINJ MOV A dir8 e MOV bit CY MOV bit51 CY MOV NI N MOV CY bit51 MOV dir8 data MOV dir8 A MOV dir8 Rm MOV dir8 Rn MOV Rm dir8 MOV Rn dir8 ORL A dir8 ORL CY bit ORL CY bit51 ORL CY bit MINI N MLM MH MM HA HA MO B Bm BR MM MP NI MY MH oO oO oal WD AD DD WIAD WI DD DM 0 O0 Ww AL BR RB CO OO HR MO HR OO oO 5 AHR HR HR BR AR 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Table A 18 State Times to Access the Port SFRs Continued In Additional State Times
52. DJNZ decrement and jump if not zero e g DJNZ P3 LABEL MOV PX Y C move carry bit to bit Y of port X CLR PX Y clear bit Y of port X SETB PX Y set bit Y of port x It is not obvious the last three instructions in this list are read modify write instructions These instructions read the port all 8 bits modify the specifically addressed bit and write the new byte back to the latch These read modify write instructions are directed to the latch rather than the pin in order to avoid possible misinterpretation of voltage and therefore logic levels at the pin For example a port bit used to drive the base of an external bipolar transistor cannot rise above the transistor s base emitter junction voltage a value lower thanV With a logic one written to the bit attempts by the CPU to read the port at the pin are misinterpreted as logic zero A read of the latch rather than the pin returns the correct logic one value 9 6 QUASI BIDIRECTIONAL PORT OPERATION Port 1 port 2 and port 3 have fixed internal pullups and are referred to as quasi bidirectional ports When configured as an input the pin impedance appears as logic one and sources current see 82930A datasheet in response to an external logic zero condition Port 0 is a true bidirec tional pin The pin floats when configured as input Resets write logical one to all port latches If logical zero is subsequently written to a port latch it can be returned to input condit
53. Data failed CRC check 2 RXFIFO goes into overrun or underrun condition while receiving Corresponding RXD bit is set when active Updated together with R_ACK bit at the end of data reception mutually exclusive with R_ACK 0 R_ACK Data is received completely into RXFIFO and ACK handshake is returned Corresponding RXD bit is set when active Updated together with R_ERR bit at the end of data reception mutually exclusive with R_ERR Figure 7 16 RXSTATx Receiver Status Register Continued 7 25 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Table 7 17 RXSTATx Addresses and Reset Values Register Address Reset Value RXSTATO S F8H Oxxx x000 RXSTAT1 S F1H 0 000 RXSTAT2 S F2H 0 000 RXSTAT3 S F3H Oxxx x000 SOFL Address S D2H Reset State 00H 7 0 TS7 0 Bit Bit Number Runcton 7 0 TS7 0 Time stamp received from host This time stamp is valid only if the SFACK bit in the SOFH register is set TS7 0 are the lower eight bits of the 11 bit frame number issued with a SOF token 7 26 Figure 7 17 SOFL Start of Frame Low Register intel UNIVERSAL SERIAL BUS SOFH Address S D3H Reset State 00H 7 0 SFACK RXSOF TS10 TS9 TS8 Bit Bit Function Number Mnemonic 7 SFACK SOF token received without error When set it indicates that the 11 b
54. Encoding Operation CMP Rm DRk CPLA Function Complement accumulator Description Logically complements each bit of the accumulator one s complement Clear bits are set and set bits are cleared Flags OV N Z Example The accumulator contains 5CH 01011100B After executing the instruction CPLA the accumulator contains 10100011B Binary Mode Source Mode Bytes 1 1 States 1 1 Encoding 1111 0100 Hex Code in Binary Mode Encoding Source Mode Encoding Operation CPL CPL bit Function Complement bit A 51 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Description Complements the specified bit variable A clear bit is set and a set bit is cleared CPL can operate on the CY or any directly addressable bit Note When this instruction is used to modify an output pin the value used as the original data is read from the output data latch not the input pin Flags Only for instructions with CY as the operand OV N 2 VA mE mE Example Port 1 contains 5BH 01011101B After executing the instruction sequence CPL P1 1 CPL P1 2 port 1 contains 5BH 01011011B Variations CPL bit51 Binary Mode Source Mode Bytes 2 2 States 2t 21 tlf this instruction addresses a port x 0 3 add 2 states Encoding 1011 0010 bit addr H
55. External Bus Cycle Code Fetch Nonpage Mode XTAL ALE RD PSEN PO A17 A16 P2 A4283 01 Figure 15 3 External Bus Cycle Data Read Nonpage Mode 15 4 intel EXTERNAL MEMORY INTERFACE XTAL ALE WR PO A17 A16 P2 A17 A16 A15 8 A4284 01 Figure 15 4 External Bus Cycle Data Write Nonpage Mode 15 2 3 Page Mode Bus Cycles Page mode increases performance by reducing the time for external code fetches Under certain conditions the controller fetches an instruction from external memory in one state time instead of two Table 15 2 Page mode does not affect internal code fetches The first code fetch to a 256 byte page of memory always uses a two state bus cycle Subse quent successive code fetches to the same page page hits require only a one state bus cycle When a subsequent fetch is to a different page a page miss it again requires a two state bus cy cle The following external code fetches are always page miss cycles the first external code fetch after a page rollovert the first external code fetch after an external data bus cycle the first external code fetch after powerdown or idle mode the first external code fetch after a branch return interrupt etc In page mode the 82930A bus structure differs from the bus structure in MCS 51 controllers Fig ure 15 1 The upper address bits A15 8 are multiplexed with the data D7 0 on port 2 and th
56. If the received address matches the slave s address the receiver hardware sets the RB8 bit and the RI bit in the SCON register generating an interrupt NOTE The ES bit must be set in the IE register to allow the RI bit to generate an interrupt The IE register is described in Chapter 8 Interrupts The addressed slave s software then clears the SM2 bit in the SCON register and prepares to re ceive the data bytes The other slaves are unaffected by these data bytes because they are waiting to respond to their own addresses 12 5 AUTOMATIC ADDRESS RECOGNITION The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled the SM2 bit is set in the SCON register Implemented in hardware automatic address recognition enhances the multiprocessor communi cation feature by allowing the serial port to examine the address of each incoming command frame Only when the serial port recognizes its own address does the receiver set the RI bit in the SCON register to generate an interrupt This ensures that the CPU is not interrupted by command frames addressed to other devices 12 7 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel If desired you may enable the automatic address recognition feature in mode 1 In this configu ration the stop bit takes the place of the ninth data bit The RI bit is set only when the received command frame address matches the device s address and is
57. Immediate 82930 551 Data Description Arch Arch data An 8 bit constant that is immediately addressed in an instruction v v 16 16 bit constant that is immediately addressed in an instruction v 0data16 A 32 bit constant that is immediately addressed in an instruction The v 1data16 upper word is filled with zeros 0data16 or ones 1data16 short A constant equal to 1 2 or 4 that is immediately addressed in an instruction v Binary representation of short Table A 4 Notation for Bit Addressing Bit D ipti 82930A MCS 51 Address esenpton Arch Arch bit A directly addressed bit in memory locations 00 0020 00 007 or in any defined SFR v yyy A binary representation of the bit number 0 7 within a byte bit51 A directly addressed bit bit number 00H FFH in memory or an SFR Bits 00H 7FH are the 128 bits in byte locations 20H 2FH in the on chip v RAM Bits 80H FFH are the 128 bits in the 16 SFR s with addresses that end in or 8H S 80H 5 88 S 90H S FOH S F8H Table A 5 Notation for Destinations in Control Instructions Destination Met 82930A MCS 51 Address Description Arch Arch rel A signed two s complement 8 bit relative address The destination is v v 128 to 127 bytes relative to first byte of the next instruction addr11 An 11 bit destination address The destination is in the same 2 Kbyte v v block of memory as the first byte of the next instruction addr16 A
58. Operations in box in this routine for 0 and are executed automatically by hardware for ATM 1 4196 01 Figure 8 12 Post transmit Operations for Non Isochronous Data Details USB OPERATING MODES Start Read status registers TXSTATx SBI Identify endpoint and Clear status flags TXSTATx 0 i T_ERR bit TXSTATx 1 must 1 URF bit Advance read marker Advance read Set ADV_RM marker TXCONx 1 Set ADV RM Clear bit TXCONx 1 TXCONx 7 RET RETI Note Operations in box in this routine for 0 and are executed automatically by hardware for ATM 1 1 4197 01 Figure 8 13 Post transmit Operations for Isochronous Data Details 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel 8 3 RECEIVE OPERATIONS 8 3 1 Overview A receive operation is always initiated by the host which sends an OUT token to the 82930 The operation occurs in two major steps 1 Data packet reception by the SIU hardware 2 Post receive management by firmware These steps are depicted in a high level view of the receive operations Figure 8 14 The post receive operations are executed by the firmware routine on the left side The SIU hardware right side receives the data packet over the USB line Details of these two operations are described in SIU Receive Operations on page 8 19 and Post
59. PORT 12 3 FRAMING BIT ERROR DETECTION MODES 1 2 AND 3 Framing bit error detection is provided for the three asynchronous modes To enable the framing bit error detection feature set the SMODO bit in the PCON register see Figure 14 1 When this feature is enabled the receiver checks each incoming data frame for a valid stop bit An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two CPUs If a valid stop bit is not found the software sets the FE bit in the SCON register see Figure 12 2 Software may examine the FE bit after each reception to check for data errors Once set only soft ware or a reset can clear the FE bit Subsequently received frames with valid stop bits cannot clear the FE bit 12 4 MULTIPROCESSOR COMMUNICATION MODES 2 AND 3 Modes 2 and 3 provide a ninth bit mode to facilitate multiprocessor communication To enable this feature set the SM2 bit in the SCON register see Figure 12 2 When the multiprocessor communication feature is enabled the serial port can differentiate between data frames ninth bit clear and address frames ninth bit set This allows the microcontroller to function as a slave processor in an environment where multiple slave processors share a single serial line When the multiprocessor communication feature is enabled the receiver ignores frames with the ninth bit clear The receiver examines frames with the ninth bit set for an address match
60. PSEN pulse and or extending the ALE pulse Each additional wait state extends the pulse by 2Tosc A separate wait state specification for external accesses via region 01 permits a slow external device to be ad dressed in region 01 without slowing accesses to other external devices Table 4 3 summarizes the wait state selections for RD WR PSEN For waveform diagrams showing wait states see External Bus Cycles with Wait States in Chapter 15 External Memory Interface 4 4 3 1 Configuration Bits WSA1 0 WSB1 0 The WSA1 0 wait state bits UCONFIGO 6 5 permit RD WR and to be extended by 1 2 or 3 wait states for accesses to external memory via all regions except region 01 The WSB1 0 wait state bits UCONFIG1 2 1 permit RD WR and PSEN to be extended by 1 2 or 3 wait states for accesses to external memory via region 01 4 4 3 2 Configuration Bit XALE Clearing XALE UCONFIGO 4 extends the time ALE is asserted from to 3 This ac commodates an address latch that is too slow for the normal ALE signal Extending ALE in Chapter 15 External Memory Interface shows an external bus cycle with ALE extended 4 10 intel DEVICE CONFIGURATION Table 4 3 RD WR PSEN External Wait States 82930A Regions WSA1 WSAO 00 02 03 0 0 3 Wait States FC FD FE FF 0 1 2 Wait States 1 0 1 Wait State 1 1 0 Wait States Region 01 WSB1 WSBO 0 0 3 Wait States 0 1 2 Wait States 1
61. TRO inter rupt flag and interrupt type control ITO For normal timer operation GATEO 0 setting TRO allows TLO to be incremented by the se lected input Setting GATEO and TRO allows external pin INTO to control timer operation This setup can be used to make pulse width measurements See section 10 5 2 Pulse Width Measure ments Timer 0 overflow count rolls over from all 1s to all 06 sets the flag generating an interrupt request 10 3 1 Mode 0 13 bit Timer Mode 0 configures timer 0 as an 13 bit timer which is set up as 8 bit timer THO register with a modulo 32 prescaler implemented with the lower five bits of the TLO register Figure 10 2 The upper three bits of the TLO register are indeterminate and should be ignored Prescaler overflow increments the THO register Interrupt Request THx TLx 8 Bits 8 Bits TRY Mode 0 13 bit Timer Counter Mode 1 16 bit Timer Counter GATEx x Oor IN Dat A4110 02 Figure 10 2 Timer 0 1 in Mode 0 and Mode 1 10 4 intel TIMER COUNTERS AND WATCHDOG TIMER 10 3 2 Mode 1 16 bit Timer Mode 1 configures timer 0 as a 16 bit timer with THO and TLO connected in cascade Figure 10 2 The selected input increments TLO 10 3 3 Mode 2 8 bit Timer With Auto reload Mode 2 configures timer 0 as an 8 bit timer TLO register that automatically reloads from the THO register Figure 10 3 TLO overflow sets the timer over
62. The 82930A has twelve interrupt sources elev en maskable sources and the TRAP instruction always enabled The maskable sources include two external interrupts INTO and INT 1 three timer interrupts timers 0 1 and 2 one pro grammable counter array PCA interrupt one serial port interrupt and four USB interrupts Each interrupt except TRAP has an interrupt request flag which can be set by software as well as by hardware see Table 6 3 For some interrupts hardware clears the request flag when it grants an interrupt Software can clear any request flag to cancel an impending interrupt 6 2 4 External Interrupts External interrupts INTO and INT 1 INTx pins may each be programmed to be level trig gered or edge triggered dependent upon bits ITO and IT1 in the TCON register see Figure 10 6 on page 10 8 If ITx 0 INTx is triggered by a detected low at the pin If ITx 1 INTx is negative edge triggered External interrupts are enabled with bits and EX1 EXx in the register see Figure 6 3 Events on the external interrupt pins set the interrupt request flags IEx in TCON These request bits are cleared by hardware vectors to service routines only if the inter rupt is negative edge triggered If the interrupt is level triggered the interrupt service routine must clear the request bit External hardware must deassert INT x before the service routine com pletes or an additional interrupt is requested Exter
63. To minimize noise and waveform distortion follow good board layout techniques Use sufficient decoupling capacitors and transient absorbers to keep noise within acceptable limits Connect 0 01 uF bypass capacitors between V oc and each V pin Place the capacitors close to the device to minimize path lengths Multilayer printed circuit boards with separate and ground planes help minimize noise For additional information on noise reduction see Application Note AP 125 Designing Microcon troller Systems for Noisy Environments 13 3 CLOCK SOURCES The 82930A can obtain the system clock signal from an external clock source Figure 13 3 or it can generate the clock signal using the on chip oscillator amplifier and external capacitors and resonator Figure 13 2 13 3 1 On chip Oscillator Crystal This clock source uses an external quartz crystal connected from XTAL1 to XTAL2 as the fre quency determining element Figure 13 2 The crystal operates in its fundamental mode as an inductive reactance in parallel resonance with capacitance external to the crystal Oscillator de sign considerations include crystal specifications operating temperature range and parasitic board capacitance Consult the crystal manufacturer s data sheet for parameter values With high quality components C2 30 pF is adequate for this application 13 2 intel MINIMUM HARDWARE SETUP Pins XTAL1 and XTAL2 are protected by on chip electrostatic d
64. WRj EJMP DIV DIV EJMP DRk addr24 Rm Rm WRj WRj 9 LCALL WRj ECALL SUB SUB SUB SUB ECALL addr24 Rm Rm WRj WRj reg op2 DRk DRk DRk 2 Bit ERET MUL MUL Instructions 3 Rm Rm WRj WRj B TRAP CMP CMP CMP CMP Rm Rm WRj WRj reg op2 DRk DRk 2 NOTES 1 2 3 4 R Rm WRj DRk op1 op2 are defined in Table A 8 See Tables A 10 and A 11 See Table A 12 A 5 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Table A 7 Instructions for the 82930A Architecture Bin A5x8 A5x9 A5xA A5xB A5xC A5xD A5xE A5xF PUSH 4 DRk PC D POP op 4 E F NOTES 1 R Rm WRj DRk 2 op2 are defined in Table 8 3 See Tables A 10 and A 11 4 See Table A 12 A 6 intel INSTRUCTION SET REFERENCE Table A 8 Data Instructions Instruction Byte 0 Byte 1 Byte 2 Byte 3 Oper Rmd Rms x C md ms Oper WRjd WRjs x D jd 2 js 2 Oper DRkd DRks XCF kd 4 ks 4 Oper Rm data x 0000 data Oper WRj data16 x j 2 0100 data high data low Oper DRk data16 4 1000 data high data low MOV DRk h data16 7 A k4 1100 data high low MOV DRk 1data16 CMP DRk 1data16 Oper Rm dir8 x E m 0001 dir8 addr Oper WRj dir8 x j 2 0101 dir8 addr Oper DRk dir8 x E k 4 1101 dir8
65. WRjd WRjs For word operands lt dest gt lt src gt WRjd WHjs the 16 bit quotient is WR jd 2 and the 16 bit remainder is in WRjd For example for a destination register WR4 assume the quotient is 1122H and the remainder is 3344H Then the results are stored in these register file locations Location 4 5 6 7 Contents 33H 44H 11H 22H DIV AB Function Divide A 58 intel Description Flags Hex Code in Example Bytes States Encoding Hex Code in Operation INSTRUCTION SET REFERENCE Divides the unsigned 8 bit integer in the accumulator by the unsigned 8 bit integer in register B The accumulator receives the integer part of the quotient register B receives the integer remainder The CY and OV flags are cleared Exception if register B contains the values returned in the accumulator and register are undefined the CY flag is cleared and the OV flag is set OV N 2 0 V For division by zero OV N 2 0 m 1 Binary Encoding Source Encoding The accumulator contains 251 OFBH or 11111011 and register B contains 18 12H or 00010010B After executing the instruction DIV AB the accumulator contains 13 or 00001101 register B contains 17 11H or 00010001B since 251 13 X 18 17 and the CY and OV flags are clear Binary Mode So
66. baud rate generator 10 6 interrupt 10 6 mode 0 10 6 mode 1 10 9 mode 2 10 9 mode 3 10 9 INDEX pulse width measurements 10 10 Timer 2 10 10 10 17 auto reload mode 10 12 baud rate generator 10 14 capture mode 10 11 clock out mode 10 14 interrupt 10 11 mode select 10 15 Timer counters 10 1 10 17 external input sampling 10 3 internal clock 10 3 interrupts 10 1 overview 10 1 10 3 registers 10 2 SFRs 3 16 C 3 signal descriptions 10 3 See also Timer 0 Timer 1 Timer 2 TMOD 3 16 10 1 10 2 10 4 10 6 10 7 12 11 C 3 C 45 Tosc 2 7 See also Oscillator TRAP instruction 5 14 6 3 6 7 6 19 A 26 TXD 9 1 12 1 mode 0 12 4 modes 1 2 3 12 6 U UART 12 1 UD flag 5 16 USB Operating Modes Overview 8 1 Receive Post receive Operations 8 27 SIU 8 31 8 33 Transmit 8 2 interrupt request 8 3 Request ISR 8 4 SIU Operations 8 7 Transmit Receive Overview 8 2 USB FIFO Information 7 1 Receive 7 12 Operational Model 7 15 read pointer 7 13 RXCNTx 7 17 RXCONx 7 18 RXDATx 7 16 Index 7 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL RXFLGx 7 20 C 31 capacitance loading 13 4 scooping 7 13 write pointer 7 12 Z Transmit Z flag 5 9 5 17 Capacities 7 1 Data Set Management 7 3 Data Byte Count Registers 7 3 read pointer 7 2 Transmit FIFO 7 1 TXCNTx 7 8 7 9 TXDATx 7 7 TXFIFO Operational Model 7 6 TXFLGx 7 11
67. en nennen en 10 9 10 531 A uto load Setup Example ettet i eene ip du 10 9 10 5 2 Pulse Width Measurements 10 10 10 65 TIMER 22 5 tit bam uie he e e irate OR BE e ete nis 10 10 10 61 Capture Mode aee E IO e OE dan eens 10 11 10 6 2 Auto reload cessisse iste renti 10 12 10 6 2 1 Up Counter Operation 2 10 12 10 6 2 2 Up Down Counter Operation seem emen 10 13 10 6 3 Baud Rate Generator Mode seen em ene nennen 10 14 106 4 Glockeout Mode segete tree i RR RE 10 14 10 7 WATCHDOG nr Ertrag 10 16 10 71 DescriptlOn hore retten rd cr fien ed ir t t n 10 16 10 7 2 Using the WDT ete ee dtm ip oe det 10 18 10 7 3 During Idle Mode esent 10 18 10 7 4 WDT During PowerDown emen nene 10 18 CHAPTER 11 PROGRAMMABLE COUNTER ARRAY 111 PCA DESCRIPTION uen ertet e tet ftue Dre dtes 11 1 11 27 PCA TIMER COUNTER itid a entitled crine i e ar e ve ene 11 1 11 3 COMPARE CAPTURE MODULES eem 11 5 11 971 16 bit Capture Mode iui ciet ie edet t dat 11 5 113 22 Compare Modes ee c eade ec reden deel teed 1126 11 3 3 16 bit Software Timer Mode 11 7 11 3 4 High speed Ou
68. exiting powerdown mode 14 6 externally initiated 13 5 need for 13 6 operation 13 6 power on 13 6 power on setup 13 1 timing sequence 13 6 13 7 warm start 13 5 14 1 RET instruction 5 14 A 25 RETI instruction 6 1 6 18 6 19 A 25 Return instructions 5 14 RL instruction A 18 RLC instruction 18 Rotate instructions 5 9 RR instruction 18 RRC instruction A 18 RST 13 5 13 6 exiting idle mode 14 5 exiting powerdown mode 14 6 ONCE mode 14 7 power on reset 13 6 RXD 9 1 12 1 mode 0 12 4 modes 1 2 3 12 6 S SADDR 3 16 12 2 12 8 12 9 C 3 C 33 SADEN 3 16 12 2 12 8 12 9 C 3 C 34 Sampled input B 3 5 3 16 12 2 12 4 12 5 C 3 36 5 3 16 12 2 12 3 12 4 12 5 12 6 12 7 3 37 38 bit definitions 12 3 interrupts 6 5 Serial Bus Interface Engine 7 27 Index 6 USB interface 7 27 Serial Bus Interface Unit SIU 7 21 7 22 FADDR 7 27 RXSTATx 7 24 Serial Bus Manager 7 21 SOFH 7 26 SOFL 7 26 TXSTATx 7 23 Serial I O port 12 1 12 14 asynchronous modes 12 6 automatic address recognition 12 7 12 9 baud rate generator 10 6 baud rate mode 0 12 4 12 10 baud rate modes 1 2 3 12 6 12 10 12 14 broadcast address 12 9 data frame modes 1 2 3 12 6 framing bit error detection 12 7 full duplex 12 6 given address 12 8 half duplex 12 4 interrupts 12 1 12 7 mode 0 12 4 12 5 1 2 3 12 6 multiprocessor communic
69. immed data Hex Code in Binary Mode Encoding Source Mode Encoding Operation ORL dir8 lt dir8 V data ORL A data Binary Mode Source Mode Bytes 2 2 States 1 1 Encoding 0100 0100 immed data Hex Code in Binary Mode Encoding Source Mode Encoding A 108 intel Operation ORL A dir8 Bytes States Encoding Hex Code in Operation ORL A Ri Bytes States Encoding Hex Code in Operation ORL A Rn Bytes States Encoding Hex Code in Operation ORL Rmd Rms Bytes States Encoding INSTRUCTION SET REFERENCE ORL A A V stdata Binary Mode Source Mode 2 2 11 11 tlf this instruction addresses a port Px x 0 3 add 1 state 0100 0101 direct addr Binary Mode Encoding Source Mode Encoding ORL lt A V dir8 Binary Mode Source Mode 1 2 2 3 0100 011i Binary Mode Encoding Source Mode A5 Encoding ORL A lt V Ri Binary Mode Source Mode 1 2 1 2 0100 1rrr Binary Mode Encoding Source Mode A5 Encoding ORL A lt A V Rn Binary Mode Source Mode 3 2 2 1 0100 1100 5555 5555 109 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ORL V Rms
70. ke gee locations 5 5 CONTROL INSTRUCTIONS Control instructions instructions that change program flow include calls returns and condi tional and unconditional jumps see Table A 27 Instead of executing the next instruction in the queue the processor executes a target instruction The control instruction provides the address of a target instruction either implicitly as in a return from a subroutine or explicitly in the form of a relative direct or indirect address The 82930A has a 24 bit program counter PC which allows a target instruction to be anywhere in the 16 Mbyte address space However as discussed in this section some control instructions restrict the target address to the current 2 Kbyte or 64 Kbyte address range by allowing only the lowest 11 or lowest 16 bits of the program counter to change 5 5 1 Addressing Modes for Control Instructions Table 5 8 lists the addressing modes for the control instructions 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Relative addressing The control instruction provides the target address as an 8 bit signed offset rel from the address of the next instruction Direct addressing The control instruction provides a target address which can have 11 bits addr11 16 bits addr16 or 24 bits addr24 The target address is written to the PC addr11 Only the lower 11 bits of the PC are changed i e the target address must be in the current 2 K
71. manual is intended for use by both software and hardware designers familiar with the principles of microcontroller architecture 11 MANUAL CONTENTS This chapter provides an overview of the manual This section summarizes the contents of the remaining chapters and appendixes This chapter also describes notational conventions and ter minology used throughout the manual and provides references to related documentation Chapter 2 Introduction provides an overview of device hardware It covers core functions pipelined CPU clock and reset unit and on chip memory and on chip peripherals USB fifos timer counters watchdog timer programmable counter array and serial I O port Chapter 3 82930A Memory Partitions describes the three address spaces of the 82930A memory address space special function register SFR space and the register file It also provides a map of the SFR space showing the location of the SFRs and their reset values and explains the mapping of the address spaces relative to the MCS9 51and MCS 251 architectures into the ad dress spaces of the 82930A Chapter 4 Device Configuration describes features that are configured at device reset in cluding the external memory interface the number of external address bits the number of wait states memory regions for asserting RD WR and PSEN page mode binary source op codes and the interrupt stack mode It describes the configuration bytes and how to
72. or based on the transmission process itself isochronous da ta For a non isochronous transfer the SIU generates a transmit done interrupt The function of post transmit service routine is to manage the transmitter s state and to ensure data integrity for the next transmission For isochronous data the post transmit routine should be embedded within the transfer request routine because both are triggered by an SOF A typical flow of a post trans mit routine is illustrated in Figure 8 11 Details are given in Figure 8 12 for non isochronous data and in Figure 8 13 for isochronous data Initiation TXD interrupt for non ISO data SOF token for ISO data Start Identify endpoint Read and clear status flags If ATM 0 Check TXSTATx Adjust read marker and read pointer For underrun clear FIFO RETI non ISO data RET RETI ISO data Note If ATM 1 operations in this block are executed automatically in hardware A4195 01 Figure 8 11 Post transmit Operations Overview 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Start Identify interrupt endpoint SBI Clear interrupt flag Read and clear status flags SBI TXSTATX T_ACK bit i TXSTATXO T ERR bit TXSTATx 1 must 1 URF bit TXFLAGx 1 Advance read marker Set ADV RM Reverse read pointer 1 Set REV RP Clear bit 0 7 RETI Note
73. port 2 pins In nonpage mode port 0 uses a strong internal pullup FET to output ones or a strong internal pull down FET to output zeros for the lower address byte and the data Port 0 is in a high impedance 9 6 intel INPUT OUTPUT PORTS state for data input In page mode port 0 uses a strong internal pullup FET to output ones or a strong internal pulldown FET to output zeros for the lower address byte or a strong internal pull down FET to output zeros for the upper address byte In nonpage mode port 2 uses a strong internal pullup FET to output ones or a strong internal pull down FET to output zeros for the upper address byte In page mode port 2 uses a strong internal pullup FET to output ones or a strong internal pulldown FET to output zeros for the upper address byte and data Port 2 is in a high impedance state for data input NOTE In external bus mode port 0 outputs do not require external pullups There are two types of external memory accesses external program memory and external data memory see Chapter 15 External Memory Interface External program memories utilize sig nal PSEN as a read strobe MCS 51 microcontrollers use RD read write to strobe memory for data accesses Depending on its RD1 0 configuration bits the 82930A uses PSEN or RD for data reads Configuration Bits RD1 0 on page 4 6 During instruction fetches external program memory can transfer instructions with 16 bit ad d
74. tlf this instruction addresses a port Px x 0 3 add 1 state 1000 direct addr Binary Mode Encoding Source Mode A5 Encoding MOV dir8 Rn Binary Mode Source Mode intel Bytes States Encoding Hex Code in Operation MOV Rn dir8 Bytes States Encoding Hex Code in Operation MOV AJir8 Bytes States Encoding Hex Code in Operation MOV A Ri Bytes States Encoding Hex Code in Operation INSTRUCTION SET REFERENCE 1010 011i direct addr Binary Mode Encoding Source Mode A5 Encoding MOV Ri lt dir8 Binary Mode Source Mode 2 3 11 21 Tlf this instruction addresses a port x 0 3 add 1 state 1010 direct addr Binary Mode Encoding Source Mode A5 Encoding MOV Rn lt dir8 Binary Mode Source Mode 2 2 11 11 Tlf this instruction addresses a port x 0 3 add 1 state 1110 0101 direct addr Binary Mode Encoding Source Mode Encoding MOV A dir8 Binary Mode 1 2 Source Mode 2 3 1110 011i Binary Mode Encoding Source Mode A5 Encoding MOV A lt Ri A 85 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL MOV A Rn Bytes States Encoding Hex Code in Operation dir8 A Bytes State
75. when necessary roll out into the slower external RAM See the left side of Figure 15 17 In this case the external RAM can have wait states only if the EPROM has wait states Otherwise if the stack rolls out above location 00 041FH the external RAM would be accessed with no wait state 15 6 3 2 Application Requiring Fast Access to Data If fast access to a block of data is more important than fast access to the stack the data can be stored in the on chip data RAM and the stack can be located entirely in external memory If the external RAM requires a different number of wait states than the EPROM address the external RAM entirely in region 01 See the right side of Figure 15 17 Addresses above 00 041FH roll out to external memory beginning at 0420H gt 15 16 tel EXTERNAL MEMORY INTERFACE EPROM 82930A 64 Kbytes WR RD PSEN RAM 64 Kbytes CE D7 0 OE A4287 01 Figure 15 16 Bus Diagram for Example 3 82930A in Nonpage Mode 15 17 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel FF FE FD FC 03 02 01 00 Memory Address Space 512 Kbytes FFFFH 64 Kbytes External EPROM 0000H External RAM FFFFH 64 Kbytes 1056 Bytes 0420H 1056 Bytes On chip RAM Memory Address Space 512 Kbytes FFFFH 64 Kbytes FF 0000H FE FD FC 03 02 FFFFH
76. 0 1 Wait State 1 1 0 Wait States 4 5 OPCODE CONFIGURATIONS SRC The SRC configuration bit UCONFIGO 0 selects the source mode or binary mode opcode ar rangement Opcodes for the 82930A architecture are listed in Table A 6 and Table A 7 in Appen dix A Instruction Set Reference Note that in Table A 6 every opcode 00H FFH is used for an instruction except ASH ESC which provides an alternative set of opcodes for columns 6H through FH The SRC bit selects which set of opcodes is assigned to columns 6H through FH and which set is the alternative Binary mode and source mode refer to two ways of assigning opcodes to the instruction set for the 82930A architecture One of these modes must be selected when the chip is configured De pending on the application binary mode or source mode may produce more efficient code This section describes the binary and source modes and provides some guidelines for selecting the mode for your application The 82930A architecture has two types of instructions instructions that originate in the MCS 51 architecture instructions that are common with the MCS 251 architecture Figure 4 6 shows the opcode map for binary mode Area I columns 1 through 5 in Table A 7 and area II columns 6 through F make up the opcode map for the instructions that originate in the MCS 51 architecture Area III in Figure 4 6 represents the opcode map for the instructions that are common with the MCS 251
77. 0xxxx000 0xxxx000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX E8 TXSTATO CL CCAPOL CCAP1L CCAP2L CCAP3L CCAP4L EF 0 000 00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EO ACC TXSTAT1 TXSTAT2 TXSTAT3 RXFLGO RXFLG1 RXFLG2 RXFLG3 E7 00000000 0 000 0 000 0 000 00 1000 00 1000 00xx1000 00xx1000 D8 CCON CMOD CCAPMO CCAPM1 CCAPM2 CCAPM3 CCAPM4 DF 00000000 00xxx000 x0000000 x0000000 x0000000 x0000000 x0000000 DO PSW PSW1 SOFL SOFH RXCONO RXCON1 RXCON2 RXCON3 D7 00000000 00000000 00000000 00000000 0xx00000 0 00000 0 00000 0 00000 C8 T2CON T2MOD RCAP2L RCAP2H TL2 TH2 CF 00000000 00 00000000 00000000 00000000 00000000 EPCON1 RXDATO RXDAT1 RXDAT2 RXDAT3 00101111 00001111 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX B8 IPLO SADEN EPCON2 SPH BF x0000000 00000000 00001111 00001111 00000000 Bo IE1 IPL 1 IPH1 IPHO B7 11111111 00000000 00000000 00000000 x0000000 A8 IEO SADDR TXCNTO TXCNT1 TXCNT2 TXCNT3 AF 00000000 00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0 P2 SBIE TXFLGO TXFLG1 TXFLG2 TXFLG3 WDTRST A7 11111111 00000000 00xx1000 00xx1000 00xx1000 00xx1000 XXXXXXXX 98 SCON SBUF TXCONO TXCON1 TXCON2 TXCON3 9F 00000000 XXXXXXXX 0xxx0000 0 0000 0 0000 0 0000 90 P1 SBI TXDATO TXDAT1 TXDAT2 TXDAT3 97 11111111 00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 88 TCON TMOD TLO TL1 THO TH1 FADDR 8F 00000000 00000000 00000000 00000000 00000000 00000000 00000000 80
78. 1 When EA 0 the reset routine retrieves UCONFIGO and UCONFIG1 from external memory using the internal addresses FF FFF8H and FF FFF9H which appear on the external address bus A17 A16 A15 0 as shown in this table See Figure 4 1 2 The upper six bytes of the configuration array are reserved for future use intel DEVICE CONFIGURATION 8 Kbytes 16 Kbytes 32 Kbytes 64 Kbytes 9 F FR 4 1 9 1 E E 128 Kbytes X srry 256 Kbytes elk 1 FFF8H F 7 F XxFFEH x xFFDH Reserved XxxFF9H UCONFIG1 Detail Configuration array in external memory This figure shows the addresses of configuration bytes UCONFIG1 and UCONFIGO in external memory for several memory implementations For 0 the 82930A obtains configuration information from configuration bytes in external memory using internal addresses FF FFF8H and FF FFF9H In external memory the eight byte configuration array is located at the highest addresses implemented A4281 01 Figure 4 1 Configuration Array External 4 3 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel UCONFIGO Address FF FFF8H 2 1 7 0 WSA1 WSAO XALE RD1 RDO PAGE SRC Bit Bit Number Mnemonic Function Reserved write one to this bit 6 5 WSA1 0 Wait State A all re
79. 1 Register Addressing Both architectures address registers directly MCS 251 architecture In the register addressing mode the operand s in a data instruction in byte registers RO R15 word registers WRO WR2 WR30 or dword registers DRO DR4 DR28 DR56 DR60 MCS 51 architecture Instructions address registers RO R7 only 5 3 1 2 Immediate Both architectures use immediate addressing MCS 251 architecture In the immediate addressing mode the instruction contains the data operand itself Byte operations use 8 bit immediate data data word operations use 16 bit immediate data data16 Dword operations use 16 bit immediate data in the lower word and either zeros in the upper word denoted by 0data16 or ones in the upper word denoted by 14 16 MOV instructions that place 16 bit immediate data into a dword register DRk place the data either into the upper word while leaving the lower word unchanged or into the lower word with a sign extension or a zero extension The increment and decrement instructions contain immediate data short 1 2 or 4 which specifies the amount of the increment decrement MCS 51 architecture Instructions use only 8 bit immediate data data 5 3 1 3 Direct MCS 251 architecture In the direct addressing mode the instruction contains the address of the data operand The 8 bit direct mode addresses on chip RAM dir8 00 0000H 00 007 as both by
80. 16 bit destination address A destination can be anywhere within v v the same 64 Kbyte region as the first byte of the next instruction addr24 A 24 bit destination address A destination can be anywhere within v the 16 Mbyte address space A 3 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL 2 MAP AND SUPPORTING TABLES Table A 6 Instructions for 59 51 Microcontrollers intel Bin 0 1 2 3 4 5 6 7 8 F Src 0 1 2 3 4 5 A5x6 A5x7 5 8 5 0 NOP AJMP LJMP RR INC INC INC INC addr11 addri 6 A A dir8 Ri Rn 1 JBC ACALL LCALL RRC DEC DEC DEC DEC bit rel addr11 addri6 A A dir8 Ri Rn 2 JB AJMP RET RLA ADD ADD ADD ADD bit rel addr11 A data A dir8 A Ri A Rn 3 JNB ACALL RETI RLCA ADDC ADDC ADDC ADDC bit rel addr11 A data A dir8 A Rn 4 JC AJMP ORL ORL ORL ORL ORL ORL rel addr11 dir8 A dir8 data A data A dir8 A Ri A Rn 5 JNC ACALL ANL ANL ANL ANL ANL ANL rel addr11 dir8 A dir8 data A data A dir8 A Ri A Rn 6 JZ AJMP XRL XRL XRL XRL XRL XRL rel addr11 dir8 A dir8 data A data A dir8 A Ri A Rn 7 JNZ ORL JMP MOV MOV MOV MOV rel addrii CY bit A DPTR A data dir8 data Ri data Rn data 8 SJMP AJMP ANL MOVC DIV MOV MOV MOV rel addr11 CY bit A A PC AB dir8 dir8 dir8 Ri dir8 Rn 9 MOV ACALL MOV MOVC SUBB SUBB SUBB SUBB DPTR data16 addr11
81. 3 6 5 6 7 IEO 3 15 6 7 6 18 12 11 C 2 C 16 Immediate addressing 5 4 INC instruction 5 8 A 16 Indirect addressing 5 4 in control instructions 5 12 in data instructions 5 6 INDEX Input pins level sensitive B 3 sampled B 3 Instruction set MCS 51 architecture 5 1 Instructions arithmetic 5 8 bit 5 10 data 5 4 data transfer 5 9 logical 5 9 instructions INT1 0 6 1 9 1 10 1 10 3 pulse width measurements 10 10 Interrupt request 6 1 cleared by hardware 6 4 Interrupt service routine exiting idle mode 14 5 exiting powerdown mode 14 6 Interrupts 6 1 6 19 blocking conditions 6 18 detection 6 4 edge triggered 6 4 enable disable 6 7 exiting idle mode 14 5 exiting powerdown mode 14 6 external 6 3 6 15 global enable 6 7 instruction completion time 6 14 latency 6 14 6 17 level triggered 6 4 PCA 6 5 polling 6 14 priority 6 1 6 3 6 4 6 10 6 12 priority within level 6 10 processing 6 13 6 19 request See Interrupt request response time 6 14 6 15 sampling 6 3 6 14 6 15 serial port 6 5 service routine ISR 6 4 6 13 6 18 6 19 sources 6 3 timer counters 6 5 vector cycle 6 18 vectors 3 3 6 4 INTR bit and RETI instruction 4 13 5 14 IPHO 3 15 6 3 6 11 6 18 C 2 C 18 Index 3 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL bit definitions 6 10 IPLO 3 15 6 3 6 12 6 18 C 2 C 19 bit definitions 6 10 ISR See Interrupts service routine
82. 3 2t WRi dir8 Dir addr from word reg 4 4 3 3 Rm dir16 Dir addr 64K from byte reg 5 3 4 2 WRi dir16 Dir addr 64K from word reg 5 4 4 3 Rm WRj Indir addr 64K from byte reg 4 3 3 2 Rm DRk Indir addr 16M from byte reg 4 4 3 3 Tf this instruction addresses an I O port Px x 3 0 add 1 to the number of states Table A 21 Summary of Increment and Decrement Instructions Increment INC DPTR DPTR DPTR 1 Increment INC byte byte lt byte 1 Increment INC lt dest gt lt src gt dest opnd lt dest opnd src opnd Decrement DEC byte byte lt byte 1 Decrement DEC lt dest gt lt sre gt dest opnd dest opnd src opnd Binary Mode Source Mode Mnemonic lt dest gt lt src gt Notes Bytes States Bytes States A acc 1 1 1 1 Rn Reg 1 1 2 2 dir8 Dir byte 2 2 2 2 2 2 INC Ri Indir RAM 1 3 2 4 DEC Rm short Byte reg by 1 2 or 4 3 2 2 1 WRi short Word reg by 1 2 or 4 3 2 2 1 DRk short Double word reg by 1 2 or 4 3 4 2 3 NOTES 1 Ashaded cell denotes an instruction in the MCS 51 architecture 2 If this instruction addresses an I O port x 0 3 add 2 to the number of states A 16 intel INSTRUCTION SET REFERENCE Table A 21 Summary of Increment and Decrement Instructions Increment INC DPTR DPTR DPTR 1 Increment INC byte byte lt byte 1 Increment
83. 82930A 82930A AT 0 E Nonpage Mode Page Mode 4273 01 Figure 15 1 Bus Structure Nonpage Mode and Page Mode 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Table 15 1 External Memory Interface Signals intel Signal Name Type Description Multiplexed With A17 Address Line 17 P1 7 CEX4 16 Address Line 16 See RD P3 7 RD 15 8 Address Lines Upper address lines for the external bus P2 7 0 AD7 0t Address Data Lines Multiplexed lower address lines and data lines for the external bus P0 7 0 ALE Address Latch Enable ALE signals the start of an external bus cycle and indicates that valid address information is available on lines A15 8 and AD7 0 An external latch can use ALE to demultiplex the address from the address data bus PROG EA External Access Directs portions of application memory accesses to on chip or off chip code locations For EA strapped to ground all program memory accesses are off chip For EA strapped to Vec access is to on chip memory if the address is within the range of the on chip memory otherwise the access is off chip The value of EA is latched at reset EA must be strapped to ground for production devices with on chip memory PSEN Program Store Enable Read signal output This output is asserted for amemory address range that depends on bits RDO and RD1 in configuration b
84. 8CH TLO S 8AH Reset State 0000 0000B THO TLO Timer Registers These registers operate in cascade to form the 16 bit timer register in timer 0 or separately as 8 bit timer counters 7 0 High Low Byte of Timer 0 Register Bit Bit Number Mnemonic Function 7 0 THO 7 0 High byte of the timer 0 timer register TLO 7 0 Low byte of the timer 0 timer register C 46 intel REGISTERS TH1 TL 1 Address 1 S 8DH TL1 S 8BH Reset State 0000 0000B TH1 TL1 Timer Registers These registers operate in cascade to form the 16 bit timer register in timer 1 or separately as 8 bit timer counters 7 0 High Low Byte of Timer 1 Register Bit Bit Number Mnemonic Function 7 0 TH1 7 0 High byte of the timer 1 timer register TL1 7 0 Low byte of the timer 1 timer register C 47 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel TH2 TL2 Address 2 S CDH TL2 S CCH Reset State 0000 0000B TH2 TL2 Timer Registers These registers operate in cascade to form the 16 bit timer register in timer 2 7 0 High Low Byte of Timer 2 Register Bit Bit Number Mnemonic Function 7 0 TH2 7 0 High byte of the timer 2 timer register TL2 7 0 Low byte of the timer 2 timer register 48 intel REGISTERS TXCNTx Address See Table 7 6 x 0 3 Reset State See Table 7 6 USB Transmit FIFO Byte Cou
85. Action at End of Transfer Cycle X X 0 0 No operation X 0 1 0 Read marker and read pointer managed by software they do not change automatically X 0 0 1 Read marker and read pointer managed by software they do not change automatically 0 1 0 1 Read marker advanced automatically FIF bit for corresponding data set is cleared 0 1 1 0 Read pointer reversed automatically FIF bits remain unchanged 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel REV TXFIFOx m E ai 2 2 e z lt T lt 8 o write 9 5 uite TXFIFOx Ol Alc bad read REV RP 1 bad read REV RP 1 4186 01 Figure 7 3 TXFIFO Operational Model 7 6 intel UNIVERSAL SERIAL BUS 7 2 4 Transmit FIFO Registers TXDATx Address See Table 7 5 x 0 3 Reset State See Table 7 5 USB Transmit FIFO Data Register Endpoint x 7 0 Transmit Data Byte Bit Bit Number Mnemonic Function 7 0 TXDATx7 0 To write data to the TXFIFO the 82930A writes to this register To read data from the TXFIFO the SIU reads from this register The write pointer and read pointer are incremented automatically after a write and read respectively Figure 7 4 TXDATx USB Transmit FIFO Byte count Register Table 7 5 TXDATx Addresses and Reset Values Register Address Reset Value TXDATO S 92H
86. BUS MICROCONTROLLER USER S MANUAL intel Valid IN token See Table 5 1 for Endpoint TX endpoint enable enabled Endpoint prepared to send Send NACK STALL hshk and set timeout status Send data If TXFIFO error send error For good hshk from host toggle SEQ bit Update status for TXFIFO Generate TXD interrupt if enabled Done A4192 01 Figure 8 6 SIU Transmit Operations for Non isochronous Data Overview 8 8 intel USB OPERATING MODES Table 8 1 Truth Table For TX Endpoint Enable ADDR Match ENDP Match CRC5 Passed TXEP E Eds Yes Yes Yes 1 Yes No X X X No X No X X No X X No X No X X X 0 8 9 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel See Table 5 2 for transmit enable TX Set up Enabled NACK STALL hshk See Table 5 3 for transmit ready MN NACK hshk Send hshk TXSTAT 2 B Set T VOID TXS Done TXCNTx Read byte count See Table 5 4 and 5 5 for TXFIFO error TXFIFO error status Insert bit stuff error and force last data Transmit data over USB 4193 01 Figure 8 7 SIU Transmit Operations for Non isochronous Data Details Part 1 8 10 USB OPERATING MODES Table 8 2 Truth Table For Transmit Enable STL TX TX OE TX Enabled Handshake To Return After Token Phase 0
87. CY and AC flags are clear and the OV flag is set Notice that OC9H minus 54H is 75H The difference between this and the above result is due to the CY borrow flag being set before the operation If the state of the carry is not known before starting a single or multiple precision subtraction it should be explicitly cleared by a CLR CY instruction Binary Mode Source Mode 2 2 1 1 1001 0100 immed data Binary Mode Encoding Source Mode Encoding SUBB lt A CY data Binary Mode Source Mode 2 2 11 11 tlf this instruction addresses a port Px x 0 3 add 1 state 1001 0101 direct addr Binary Mode Encoding Source Mode Encoding SUBB A A CY dir8 Binary Mode Source Mode 1 2 2 3 1001 011i Binary Mode Encoding Source Mode A5 Encoding SUBB intel SUBB A Rn Bytes States Encoding Hex Code in Operation SWAPA Function Description Flags Example Bytes States Encoding Hex Code in Operation TRAP Function lt A CY Ri Binary Mode Source Mode 1 1 2 2 1001 drrr Binary Mode Encoding Source Mode A5 Encoding SUBB A lt A CY Rn Swap nibbles within the accumulator INSTRUCTION SET REFERENCE Interchanges the low and high nibbles 4 bit fields of the accumulator bi
88. Control A9 P2 1 8 P3 1 TXD 21 P3 2 INTO 22 A10 P2 2 7 P3 4 TO 24 P3 3 INT1 23 A11 P2 3 6 P3 5 T1 25 EA 67 A12 P2 4 5 RST 4 A13 P2 5 4 Bus Control amp Status 38 A15 P2 7 2 P3 6 WR 26 P3 7 RD A16 27 P3 7 RD A16 27 P1 7 CEX4 A17 35 ALE 66 PSEN 65 Power amp Ground Name Lead Voc 36 56 68 Nec 40 EA 67 Vss 1 18 37 52 57 intel SIGNAL DESCRIPTIONS Table B 2 Description of Columns of Table B 3 Column Heading Description Signal Name pin is listed in the Multiplexed With column Lists the signals arranged alphabetically Many pins have two functions so there are more entries in this column than there are pins Every signal is listed in this column for each signal the alternate function that shares the Type EXTINTx as a level sensitive input Identifies the pin function listed in the Signal Name column as an input I output bidirectional 1 0 power PWR or ground GND Note that all inputs except RESET are sampled inputs RESET is a level sensitive input During powerdown mode the powerdown circuitry uses Description Signal Name column Briefly describes the function of the pin for the specific signal listed in the Multiplexed With provides if applicable Lists the multiplexed signal name for the alternate function that the pin Table B 3 Signal Descriptions
89. Counter 0 High Byte S 8CH TL1 Timer Counter 1 Low Byte S 8BH TH1 Timer Counter 1 High Byte S 8DH TL2 Timer Counter 2 Low Byte S CCH TH2 Timer Counter 2 High Byte S CDH TCON Timer Counter 0 and 1 Control 5 88 TMOD Timer Counter 0 and 1 Mode Control 5 89 T2CON Timer Counter 2 Control S C8H T2MOD Timer Counter 2 Mode Control S C9H RCAP2L Timer 2 Reload Capture Low Byte S CAH RCAP2H Timer 2 Reload Capture High Byte S CBH WDTRST WatchDog Timer Reset S A6H Table 3 9 Programmable Counter Array PCA SFRs Mnemonic Name Address CCON PCA Timer Counter Control S D8H CMOD PCA Timer Counter Mode S D9H CCAPMO PCA Timer Counter Mode 0 S DAH CCAPM 1 PCA Timer Counter Mode 1 S DBH CCAPM2 PCA Timer Counter Mode 2 S DCH PCA Timer Counter Mode 3 S DDH CCAPM4 PCA Timer Counter Mode 4 S DEH intel 82930A MEMORY PARTITIONS Table 3 9 Programmable Counter Array PCA SFRs Continued Mnemonic Name Address CL PCA Timer Counter Low Byte S E9H CH PCA Timer Counter High Byte S F9H CCAPOL PCA Compare Capture Module 0 Low Byte S EAH CCAP1L PCA Compare Capture Module 1 Low Byte S EBH CCAP2L PCA Compare Capture Module 2 Low Byte S ECH CCAP3L PCA Compare Capture Module 3 Low Byte S EDH CCAP4L PCA Compare Capture Module 4 Low Byte S EEH CCAPOH PCA Compare Capture Module 0 High Byte S FAH CCAP1H PCA Compare Capture Module 1 High Byte S FBH CCAP2H PC
90. DPL is the low byte of the 16 bit data pointer DPTR Instructions in the MCS 51 architecture use the 16 bit data pointer for data moves code moves and for a jump instruction JMP A DPTR See also and DPXL 7 0 DPL Contents Bit Bit Number Mnemonic Function 7 0 DPL 7 0 Data Pointer Low Bits 0 7 of the extended data pointer DPX DR56 C 12 intel REGISTERS DPXL Address S 84H Reset State 0000 0001B Data Pointer Extended Low DPXL provides SFR access to register file location 57 also named DPXL Location 57 is the lower byte of the upper word of the extended data pointer DPX DR56 whose lower word is the 16 bit data pointer DPTR See also DPH and DPL 7 0 DPXL Contents Bit Bit Function Number Mnemonic 7 0 DPXL 7 0 Data Pointer Extended Low Bits 16 23 of the extended data pointer DPX DR56 DPXH Address 5 85 Reset State 0000 0000B Data Pointer Extended High DPXH provides SFR access to register file location 56 also named DPXH Location 56 is the upper byte of the upper word of the extended data pointer DPX DR56 whose lower word is the 16 bit data pointer DPTR See also DPH and DPL 7 0 DPXL Contents Bit Bit 3 Number Mnemonic Functio 7 0 DPXH 7 0 Data Pointer Extended High Bits 24 31 of the extended data pointer DPX DR56 82930
91. External Memory 00 01 02 03 FC FD FE FF External Memory 128 Kbytes FC FD FE FF 00 01 02 03 A4217 01 4 4 2 3 For RD1 0 10 the 16 external address bits A15 0 on ports PO and P2 provide a single 64 Kbyte region in external memory top of Figure 4 5 This selection provides the smallest exter Figure 4 5 Internal External Memory Mapping RD1 0 10 and 11 RD1 0 10 16 External Address Bits 4 9 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel nal memory space however pin P3 7 RD A16 is available for general I O and pin P1 7 CEX4 A17 is available for general I O or PCA I O This selection is useful when the avail ability of these pins is required and or a small amount of external memory is sufficient 4 4 2 4 RD1 0 z 11 Compatible with MCS 51 Microcontrollers The selection RD1 0 11 provides only 16 external address bits A15 0 on ports PO and P2 However is the read signal for regions while RD is the read signal for regions 00 03 bottom of Figure 4 5 The two read signals effectively expand the external memory space to two 64 Kbyte regions WR is asserted only for writes to regions 00 03 This selection provides compatibility with MCS 51 microcontrollers which have separate external memory spaces for code and data 4 4 3 Wait State Configuration Bits You can add wait states to external bus cycles by extending the RD WR
92. For discussions of external memory see section 4 4 Configuring the External Memory Interface and Chapter 15 External Memory Interface 3 3 82930A REGISTER FILE The 82930A register file consists of 40 locations 0 31 and 56 63 as shown in Figure 3 6 These locations are accessible as bytes words and dwords as described in section 3 3 1 Byte Word and Dword Registers Several locations are dedicated to special registers see section 3 3 2 Dedicated Registers the others are general purpose registers Register file locations 0 7 actually consist of four switchable banks of eight registers each as il lustrated in Figure 3 7 The four banks are implemented as the first 32 bytes of on chip RAM and are always accessible as locations 00 0000H 00 001FH in the memory address space Only one of the four banks is accessible via the register file at a given time The accessible or active bank is selected by bits RS1 and RSO in the PSW register as shown in Table 3 2 The PSW is described in section 5 6 Program Status Words This bank selection can be used for fast con text switches Register file locations 8 31 and 56 63 are always accessible These locations are implemented as registers in the CPU Register file locations 32 55 are reserved and cannot be accessed Because these locations are dedicated to the register file they are not considered a part of the general purpose 1 Kbyte on chip RAM locat
93. Interrupt Enable Endpoint 1 Setting this bit enables the interrupt for flag bit TXD1 in the SBI register 1 RXIEO Receive Done Interrupt Enable Endpoint 0 Setting this bit enables the interrupt for flag bit RXDO in the SBI register 0 TXIEO Transmit Done Interrupt Enable Endpoint 0 Setting this bit enables the interrupt for flag bit TXDO in the SBI register Figure 6 5 SBIE USB Endpoint Interrupt Enable Register 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel 6 7 INTERRUPT PRIORITIES Each of the eleven 829304 interrupt sources may be individually programmed to one of four pri ority levels This is accomplished with the IPHX x IPLX x bit pairs in the interrupt priority high in Figure 6 6 and 6 8 and interrupt priority low IPL1 IPLO registers Figures 6 7 and 6 9 Specify the priority level as shown in Table 6 5 using IPHO x as the MSB and IPLO x as the LSB Table 6 5 Level of Priority IPH1 x IPHO x MSB IPL1 x IPLO x LSB Priority Level 0 0 0 Lowest Priority 0 1 1 1 0 2 1 1 3 Highest Priority A low priority interrupt is always interrupted by a higher priority interrupt but not by another in terrupt of equal or lower priority The highest priority interrupt is not interrupted by any other in terrupt source Higher priority interrupts are serviced before lower priority interrupts The response to simultaneous occurrence of equal prio
94. J JB instruction 5 13 A 25 JBC instruction 5 13 A 25 JC instruction A 25 JE instruction A 25 JG instruction A 25 JLE instruction A 25 JMP instruction A 25 JNB instruction 5 13 A 25 JNC instruction 25 JNE instruction A 25 JNZ instruction A 25 JSG instruction A 26 JSGE instruction A 26 JSL instruction A 25 JSLE instruction A 26 Jump instructions bit conditional 5 12 compare conditional 5 12 5 13 unconditional 5 13 JZ instruction A 25 L LCALL instruction 5 14 A 25 Level sensitive input B 3 LJMP instruction 5 13 A 25 Logical instructions 5 9 table of A 18 M MCS 251 microcontroller core 2 6 Memory space 2 5 3 1 3 5 3 8 compatibility See Compatibility MCS 251 and MCS 51 architectures regions 3 2 3 5 reserved locations 3 5 Miller effect 13 4 instruction A 20 A 21 A 22 for bits 5 10 A 24 MOVC instruction 3 2 5 9 A 22 Move instructions Index 4 intel table of A 20 MOVH instruction 5 9 A 22 MOVS instruction 5 9 A 22 MOV X instruction 3 2 5 9 A 22 MOVZ instruction 5 9 A 22 instruction 5 8 Multiplication 5 8 N N flag 5 9 5 17 Noise reduction 13 2 13 3 13 4 Nonpage mode bus cycles See External bus cycles Nonpage mode bus structure 15 1 configuration 4 6 design example 15 16 port pin status 15 11 NOP instruction 5 13 A 26 On chip code memory 15 7 idle mode 14 4 powerdown mode 14 5 On chip
95. MICROCONTROLLER USER S MANUAL intel Table 11 3 lists the bit combinations for selecting module modes For modules in the capture mode detection of a valid signal transition at the I O pin CEXx causes hardware to load the cur rent PCA timer counter value into the compare capture registers CCAPxH CCAPxL and to set the module s compare capture flag CCFx in the CCON register If the corresponding interrupt enable bit ECCFx in the register is set Figure 11 9 the PCA sends an interrupt re quest to the interrupt handler Since hardware does not clear the event flag when the interrupt is processed the user must clear the flag in software A subsequent capture by the same module overwrites the existing captured value To preserve a captured value save itin RAM with the interrupt service routine before the next capture event occurs PCA Timer Counter CH CL 8 Bits 8 Bits Count Input Capture CCAPxL Interrupt Request X 0 1 2 3 or 4 X Don t Care CCON Register Enable x Ts own awn Te Ts Tem CCAPMx Mode Register 4163 02 Figure 11 2 PCA 16 bit Capture Mode 11 3 2 Compare Modes The compare function provides the capability for operating the five modules as timers event counters or pulse width modulators Four modes employ the compare function 16 bit software timer mode high speed output mode WDT mode and PWM mode
96. Manual Order Number 272383 3 2 intel 82930A MEMORY PARTITIONS 64 Kbyte code memory for MCS 51 microcontrollers maps into region FF of the memory space for MCS 251 microcontrollers Assemblers for MCS 251 microcontrollers assemble code for MCS 51 microcontrollers into region FF and data accesses to code memory are directed to this region The assembler also maps the interrupt vectors to region FF This mapping is trans parent to the user code executes just as before without modification RO Register File R7 External Data MOVX Internal Data SFRs indirect direct Internal Data direct indirect 4139 01 Figure 3 2 Address Spaces for the MCS 51 Architecture 3 3 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Memory Address Space 16 Mbytes FFFFH SFR Space MCS 51 Architecture 512 Bytes Code Memory S 1FFH FF 0000H 0000H 100H 02 0000H FFH MCS 51 Architecture SFRs S 07FH S 000H FFFFH MCS 51 Architecture External Data Memory Register File 64 Bytes ___ 01 0000H 0000H MCS 51 Architecture nr Internal Data Memory 0 MCS 51 Architecture 7 00 0000H 00H 4133 01 Figure 3 3 Address Space Mappings 5 51 Architecture to 5 251 Architecture Table 3 1 Address Mappings MCS 51 Architecture MCS 251 Architecture Memory Type Data
97. Mode A5 Encoding Source Mode Encoding Operation ANL WRJ lt WRj data16 ANL Rm dir8 Binary Mode Source Mode Bytes 4 3 States 3t 2T tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 0101 1110 SSSS 0001 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ANL Rm Rm A dir8 ANL WRi dir8 Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 0101 11 10 tttt 0101 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ANL WRJ lt WRj A dir8 ANL 16 Binary Mode Source Mode Bytes 5 4 States 3 2 Encoding 0101 1110 5555 0011 direct direct A 39 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ANL Rm Rm A dir16 ANL WRi dir16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding 0101 1110 tttt 0111 direct direct Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ANL WRJ lt WRj A dir16 ANL Rm WRj Binary Mode Source Mode Bytes 4 3 States 3 2 Encoding 0101 1110 tttt 1001 5556 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ANL Rm lt Rm A WR ANL Rm DRk Binary Mode Source
98. Mode A5 Encoding Source Mode Encoding POP Rm lt SP SP lt SP 1 Binary Mode Source Mode 3 2 5 4 1101 1010 tttt 1001 Binary Mode A5 Encoding Source Mode Encoding POP SP lt SP 1 WHj lt 5 SP lt SP 1 Binary Mode Source Mode 3 2 10 9 1101 1010 uuuu 1011 Binary Mode A5 Encoding Source Mode Encoding POP A 115 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL PUSH dest Function Description Flags Example Variations PUSH dir8 Bytes States Encoding Hex Code in Operation PUSH data Bytes States Encoding Hex Code in Operation A 116 intel SP SP 3 lt SP SP SP 1 Push onto stack Increments the stack pointer by one The contents of the specified variable are then copied into the on chip RAM location addressed by the stack pointer OV N 2 On entering an interrupt routine the stack pointer contains 09H and the data pointer contains 0123H After executing the instruction sequence PUSH DPL PUSH DPH the stack pointer contains OBH and on chip RAM locations OAH and OBH contain 01H and 23H respectively Binary Mode Source Mode 2 2 4 4 1100 0000 direct addr Binary Mode Encoding Source Mode Encoding PUSH SP lt SP 1 SP Binary Mode Source
99. Mode 4 3 4 3 1100 1010 0000 0010 data Binary Mode Encoding Source Mode Encoding PUSH SP lt SP 1 SP lt data intel INSTRUCTION SET REFERENCE PUSH data16 Binary Mode Source Mode Bytes 5 4 States 6 5 Encoding 1100 1010 0000 0110 data hi data lo Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation PUSH SP SP 2 SP lt MSB of data16 SP lt LSB of data16 PUSH Rm Binary Mode Source Mode Bytes 3 2 States 4 3 Encoding 1100 1010 5555 1000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation PUSH SP lt SP 1 SP lt Rm PUSH WRj Binary Mode Source Mode Bytes 3 2 States 5 4 Encoding 1100 1010 tttt 1001 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation PUSH SP lt SP 1 SP lt WHj SP lt SP 1 PUSH DRk Binary Mode Source Mode Bytes 3 2 A 117 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL States Encoding Hex Code in Operation RET Function Description Flags Example Bytes States Encoding Hex Code in Operation RETI Function Description A 118 1100 1010 uuuu 1011 Binary Mode A5 Encoding Source Mode Encoding PUSH SP SP 1
100. Receive endpoint enable This bit is used to enable the receive endpoint When disabled the endpoint does not respond to a valid OUT token The state of this bit is sampled on a valid OUT token 1 TX OE Transmit output enable This bit is used to enable the data in the TXFIFO to be transmitted If disabled the endpoint returns a NACK handshake to a valid IN token if the STL TX bit is not set The state of this bit is sampled on a valid IN token 0 TXEP E Transmit endpoint enable This bit is used to enable the transmit endpoint When disabled the endpoint does not respond to a valid IN token The state of this bit is sampled on a valid IN token C 14 REGISTERS Address S 8FH FADDR Reset State 00H 7 0 A6 0 Bit Bit Number Funerien 7 Reserved The value read from this bit is indeterminate Write a zero to this bit 6 0 A6 0 7 bit programmable function address This register is programmed through the commands received via endpoint 0 on configuration 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel IEO Address Reset State S A8H 0000 0000B Interrupt Enable Register 0 IEO contains two types of interrupt enable bits The global enable bit EA enables disables all of the interrupts except the TRAP interrupt which is always enabled The remaining bits enable disable the other individual interrupt
101. Receiver Transmitter UART standard MCS 51 microcontroller UART three timers timers 0 1 2 four input output ports 1 open drain port 3 quasi bidirectional ports dedicated 14 bit hardware watchdog timer The 82930A supports four function endpoints 0 3 endpoint 0 is dedicated to control Figure 2 3 is a block diagram showing the 8XC251SB and the peripheral USB components that are add ed to comprise the 82930A These USB device components are FIFO memory two FIFOs of 256 bytes depth one for transmission and one for reception six FIFOs of 16 bytes depth 3 for transmission and 3 for reception serial bus interface unit SIU standard universal serial bus interface phase locked loop selectable 12 Mbps or 1 5 Mbps data rate 2 4 intel INTRODUCTION 2 2 82930A FEATURES The 82930A peripherals include an on chip USB interface dedicated watchdog timer a tim er counter unit a programmable counter array PCA and a serial I O unit The 82930A has four 8 bit I O ports PO P3 Each port pin can be individually programmed as a general I O signal or as a special function signal that supports the external bus or one of the on chip peripherals Ports and P2 comprise a 16 line external bus which transmits a 16 bit address multiplexed with 8 data bits You can also configure the 82930A to have a 17 bit or an 18 bit external address bus See Configuring the External Memory Interface in Ch
102. SFR Space 512 Bytes Register File 64 Bytes 63 A4100 01 Figure 3 1 Address Spaces for the 82930A 3 1 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Itis convenient to view the unsegmented 16 Mbyte memory space as consisting of 256 64 Kbyte regions numbered 00 to FF NOTE memory space in the 82930A is unsegmented The 64 Kbyte regions 00 01 FF are introduced only as a convenience for discussions Addressing in the 82930A is linear there are no segment registers On chip RAM is located at the bottom of the memory space begining at location 00 0000H The first 32 bytes 00 0000H 00 001FH provide storage for part of the register file The on chip 1024 byte general purpose data RAM resides just above this begining at location 00 0020H register file has its own address space Figure 3 1 The 64 locations in the register file are numbered decimally from 0 to 63 Locations 0 7 represent one of four switchable register banks each having 8 registers The 32 bytes required for these banks occupy locations 00 0000H 00 001FH in the memory space Register file locations 8 63 do not appear in the memory space See section 3 3 82930A Register File for a further description of the register file The SFR space accommodates up to 512 8 bit special function registers with addresses 5 000 5 1 SRFs implemented in the 82930 are shown in Table 3 4 In the MC
103. See binary mode Stack pointer Extended stack pointer The basic time unit of the device the combined period of the two internal timing signals PH1 and PH2 The internal clock generator produces PH1 and PH2 by halving the frequency of the signal on With a 16 MHz crystal one state time Glossary 5 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel UART WDT word wraparound Glossary 6 equals 125 ns Because the device can operate at many frequencies this manual defines time requirements in terms of state times rather than in specific units of time Universal asynchronous receiver and transmitter A part of the serial I O port Watchdog timer an internal timer that resets the device if the software fails to operate properly A 16 bit unit of data In memory a word comprises two contiguous bytes The result of interpreting an address whose hexadecimal expression uses more bits than the number of available address lines Wraparound ignores the upper address bits and directs access to the value expressed by the lower bits intel Index intel 0datal6 3 1 16 3 data definition A 3 datal6 A 3 short A 3 82930A 1 1 block diagram 2 2 A 15 8 9 1 description 15 2 16 description 15 2 AC flag 5 16 5 17 ACALL instruction 5 14 A 25 A 27 ACC 3 11 3 15 C2 C 5 Accumulator 3 13 in register file 3 11 AD7 0 9 1 description 15 2 ADD
104. States 3 2 Encoding 1011 1110 tttt TTTT Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CMP WRjd WRjs CMP DRkd DRks Binary Mode Source Mode Bytes 3 2 States 5 4 Encoding 1011 1111 uuuu UUUU Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CMP DRkd DRks CMP Rm data Binary Mode Source Mode Bytes 4 3 States 3 2 Encoding 1011 1110 ssss 0000 data Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CMP Rm data WRj data16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding 1011 1110 tttt 0100 data hi data low A 48 intel INSTRUCTION SET REFERENCE Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CMP WRj data16 CMP DRk 0data16 Binary Mode Source Mode Bytes 5 4 States 6 5 Encoding 1011 1110 uuuu 1000 data hi data low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CMP DRk 0data16 CMP DRk 1data16 Binary Mode Source Mode Bytes 5 4 States 6 5 Encoding 1011 1110 uuuu 1100 data hi data hi Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CMP DRk 1data16 CMP 8 Binary Mode Source Mode Bytes 4 3 States 3t 21 tlf this instruction add
105. This data transaction management is based on the transfer type and the state of the FIFOs and it includes monitoring the transaction status managing the FIFOs and relaying control events to the 82930 CPU via interrupt requests 7 21 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel 0 3 7 Address See Table 7 15 Reset State See Table 7 15 STL RX STL TX CTL EP RXSPM TXEP E Bit Number Bit Mnemonic Function 7 STL RX Stall Receive Endpoint Set this bit to stall the receive endpoint Clear this bit only when the host has intervened through commands sent down endpoint 0 The state of this bit is sampled on a valid OUT token STL TX Stall transmit endpoint This bit is used to stall the transmit endpoint and it should only be cleared when the host has intervened through commands sent down endpoint 0 The state of this bit is sampled on a valid IN token CTL EP Control endpoint Set this bit to configure the endpoint as control endpoint The state of this bit is sampled on a valid OUT token RXSPM Receive single packet mode This bit is used to configure the receive endpoint for single data packet operation When enabled only a single data packet is allowed to reside in the RXFIFO The state of this bit is sampled on a valid OUT token RX IE Receive input enable This bi
106. Value TXSTATO S E8H 0 000 TXSTAT1 S E1H Oxxx x000 TXSTAT2 S E2H Oxxx x000 TXSTAT3 S E3H Oxxx x000 RXSTATx Address See Table 7 17 x 0 3 Reset State See Table 7 17 7 0 R_SEQ R_SETUP R VOID R ERR R_ACK Bit Bit Number Function 7 R SEQ Receiver s current sequence bit This bit will be toggled on a ACK ed reception 6 R SETUP Received Setup Token This bit is set by hardware and must be cleared by software 53 Reserved Values read from these bits are indeterminate Write zeros to these bits 2 R VOID A time out condition has occurred in response to a valid OUT token No data is received into RXFIFO Receive time out is closely associated with NACK STALL handshake returned by function at the end of reception It can be one of the following 1 RXFIFO cannot be written 2 STL_RX is set This bit does not affect RXD bit Updated in respond to a valid OUT token 7 24 Figure 7 16 RXSTATx Receiver Status Register intel UNIVERSAL SERIAL BUS RXSTATx Address See Table 7 17 0 3 Reset State See Table 7 17 7 0 R SEQ R SETUP R VOID R ERR R ACK Bit Bit Function Number Mnemonic 1 R ERR An error condition has occurred with the reception Complete or partial data has been written into RXFIFO No handshake is returned It can be one of the following condition 1
107. When a byte is saved PUSHed on the stack SPX is incremented and then the byte is written to the top of stack When a byte is retrieved POPped from the stack it is copied from the top of stack and then SPX is decremented 7 0 SP Contents Bit Bit Number Mnemonic 7 0 SP 7 0 Stack Pointer Bits 0 7 of the extended stack pointer SPX DR60 Function C 40 intel REGISTERS SPH Address S BEH Reset State 0000 0000B Stack Pointer High SPH provides SFR access to location 62 in the register file also named SPH SPH is the upper byte of the lower word of DR60 the extended stack pointer SPX The extended stack pointer points to the current top of stack When a byte is saved PUSHed on the stack SPX is incremented and then the byte is written to the top of stack When a byte is retrieved POPped from the stack it is copied from the top of stack and then SPX is decremented 7 0 SPH Contents BI Bit Function Number Mnemonic 7 0 SPH 7 0 Stack Pointer High Bits 8 15 of the extended stack pointer SPX DR 60 C 41 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel T2CON Address S C8H Reset State 0000 0000B Timer 2 Control Register Contains the receive clock transmit clock and capture reload bits used to configure timer 2 Also contains the run control bit counter timer select bit overflow flag external flag and ext
108. XXH TXDAT1 5 93 XXH TXDAT2 S 94H XXH TXDAT3 5 95 XXH 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel TXCNTx x 0 3 Reset State See Table 7 6 See Table 7 6 USB Transmit FIFO Byte Count Register Endpoint x This two byte ring buffer stores the number of bytes in data set 0 and data set 1 E 0 Byte Count 0 255 Bit Bit Number Mnemonic Function 7 0 TXCNTx7 0 Byte Count The number of bytes in data set 0 or data set 1 When this register is accessed the byte count written read is for data set 0 or data set 1 depending on the data set index bits FIF1 0 in TXFLAGx as shown Table 7 2 and Table 7 3 Following a read of this register the read write index is unchanged following a write the read write index is toggled Write the byte count to this register after writing the data to TXDATx Figure 7 5 USB Transmit FIFO Byte Count Register Table 7 6 TXCNTx Addresses and Reset Values Register Address Reset Value TXCNTO S AAH XXH TXONT1 S ABH XXH 2 S ACH XXH S ADH XXH intel UNIVERSAL SERIAL BUS TXCONx Address See Table 7 7 0 3 Reset State See Table 7 7 USB Transmit FIFO Control Register Endpoint x The bits in this register control the operation of TXFIFOx 7 0 CLR ISO ATM ADV RM REV RP Bit Bit ion Number
109. a port Px x 0 3 add 2 states Encoding 1010 1001 1001 0 yyy direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV bit CY MOV CY bit Binary Mode Source Mode Bytes 4 3 States 31 21 Tlf this instruction addresses port x 0 3 add 1 state Encoding 1010 1001 1010 0 yyy direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV CY bit MOV DPTR data16 Function Load data pointer with a 16 bit constant Description Loads the 16 bit data pointer DPTR with the specified 16 bit constant The high byte of the A 98 constant is loaded into the high byte of the data pointer DPH The low byte of the constant is loaded into the low byte of the data pointer DPL intel Flags Example Bytes States Encoding Hex Code in Operation INSTRUCTION SET REFERENCE OV After executing the instruction MOV DPTR 1234H DPTR contains 1234H DPH contains 12H and DPL contains 34H Binary Mode Source Mode 3 3 2 2 1001 0000 data hi data low Binary Mode Encoding Source Mode Encoding MOV DPTR lt stdata16 MOVC A A lt base reg gt Function Description Flags Move code byte Loads the accumulator with a code byte or constant from program memory The address of the byte fetched is the sum of the original unsign
110. addr Oper Rm dir16 0011 dir16 addr high dir16 addr low Oper WRi dir16 x E 12 0111 dir16 addr high dir16 addr low Oper DRk dir16 1 x k 4 1111 dir16 addr high dir16 addr low Oper Rm WRj x j 2 1001 m 00 Oper Rm DRk k 4 1011 m 00 NOTE 1 For this instruction the only valid operation is MOV Table A 9 High Nibble Byte 0 of Data Instructions Operation Notes 2 ADD reg op2 9 SUB reg op2 B CMP 2 1 All addressing modes are 4 ORL reg op2 2 supported 5 ANL reg op2 2 6 XRL reg op2 2 7 MOV reg op2 8 DIV reg op2 Two modes only reg op2 Rmd Rms A MUL reg op2 reg op2 Wjd Wis NOTES 1 The CMP operation does not support direct16 2 Forthe ORL ANL and XRL operations neither reg nor op2 can be DRk 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel All of the bit instructions in the 82930A architecture Table 7 have opcode 9 which serves as an escape byte similar to A5 The high nibble of byte 1 specifies the bit instruction as given in Table A 10 Table A 10 Bit Instructions Instruction Byte 0 Byte 1 Byte 2 Byte 3 1 BitInstr dir8 A 9 xxxx 0 bit dir8 addr rel addr Table A 11 Byte 1 High Nibble for Bit Instructions XXXX Bit Instruction 0001 JBC bit 0010 JB bit
111. and shows how they are generated by timer 1 12 11 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Table 12 4 Timer 1 Generated Baud Rates for Serial Modes 1 and 3 Baud E Uy SMOD1 Lh hate Fosc Mode Reload 62 5 Kbaud Max 12 0 MHz 1 2 FFH 19 2 Kbaud 11 059 MHz 1 2 FDH 9 6 Kbaud 11 059 MHz 0 2 FDH 4 8 Kbaud 11 059 MHz 0 ol 2 FAH 2 4 Kbaud 11 059 2 0 2 1 2 Kbaud 11 059 MHz 0 2 137 5 Baud 11 986 MHz 0 2 1DH 110 0 Baud 6 0 MHz 0 2 72H 110 0 Baud 12 0 2 0 1 FEEBH 12 6 33 Timer 2 Generated Baud Rates Modes 1 3 Timer 2 may be selected as the baud rate generator for the transmitter and or receiver Figure 12 5 The timer 2 baud rate generator mode is similar to the auto reload mode A rollover in the TH register reloads registers TH2 TL2 with the 16 bit value in registers RCAP2H and RCAP2L which are preset by software The timer 2 baud rate is expressed by the following formula Timer 2 Overflow Rate Serial I O Modes 1 and Baud Rate 16 12 6 3 4 Selecting Timer 2 as the Baud Rate Generator NOTE Turn the timer off clear the TR2 bit in the T2CON register before accessing registers TH2 TL2 RCAP2H and RCAP2L To select timer 2 as the baud rate generator for the transmitter and or receiver program the RCLCK and TCLCK bits in the T2CON register as shown in T
112. and the five compare capture modules share a single interrupt vector The EC bit in the IE special function register is a global interrupt enable for the PCA Capture events compare events in some modes and PCA timer counter overflow set flags in the CCON register Setting the overflow flag CF generates a PCA interrupt request if the PCA timer counter inter rupt enable bit ECF in the CMOD register is set Figure 11 1 Setting a compare capture flag CCFx generates a PCA interrupt request if the ECCFx interrupt enable bit in the corresponding CCAPM lt x register is set Figures 11 2 and 11 3 For a description of the 82930A interrupt system see Chapter 6 Interrupts 11 2 PCA TIMER COUNTER Figure 11 1 depicts the basic logic of the timer counter portion of the PCA The CH CL special function register pair operates as a 16 bit timer counter The selected input increments the CL low byte register When CL overflows the CH high byte register increments after two oscil lator periods when CH overflows it sets the PCA overflow flag CF in the CCON register gen erating a PCA interrupt request if the ECF bit in the CMOD register is set 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel The CPS1 and CPSO bits in the register select one of four signals as the input to the timer counter Figure 11 7 Fos 12 Provides an clock pulse at S5P2 of every peripheral cycle With 12 MHz the time counte
113. architecture Table A 7 Some of these opcodes are reserved for future instructions Note that the opcode values for areas and III are identical 06H FFH To distinguish between the two areas in binary mode the opcodes in area III are given the prefix ASH The area III opcodes are thus AS06H ASFFH Figure 4 7 shows the opcode map for source mode Areas II and III have switched places com pare with Figure 4 6 In source mode opcodes for instructions in area II require the 5 escape prefix while opcodes for instructions in area III do not To illustrate the difference between the binary mode and source mode opcodes Table 4 4 shows the opcode assignments for three sample instructions 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Table 4 4 Examples of Opcodes in Binary and Source Modes Opcode Instruction Binary Mode Source Mode DECA 14H 14H SUBB A R4 9CH A59CH SUB R4 R4 A59CH 9CH 4 5 1 Selecting Binary Mode or Source Mode If you have code that was written for an MCS 51 microcontroller and you want to run it unmod ified on an 82930A choose binary mode You can use the object code without reassembling the source code You can also assemble the source code with an assembler for the MCS 251 architec ture and have it produce object code that is binary compatible with MCS 51 microcontrollers The remainder of this section discusses the selection of binary mode or source mod
114. are in Table A 26 If this instruction addresses an I O port Px x 0 3 add 1 to the number of states External memory addressed by instructions in the MCS 51 architecture is in the region specified by DPXL reset value 01H See Compatibility with the MCS 51 Architecture in Chapter 3 A 21 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Table A 24 Summary of Move Instructions Continued Move 2 Move with Sign Extension Move with Zero Extension Move Code Byte Move to External Mem Move from External Mem MOV lt dest gt lt src gt MOVS lt dest gt lt src gt MOVZ lt dest gt lt src gt MOVC lt dest gt lt src gt MOVX dest src MOVX lt dest gt lt srce gt destination lt src destination lt src with sign extend destination src with zero extend A lt code byte external mem lt A lt source in external mem Binary Mode Source Mode Mnemonic lt dest gt lt src gt Notes Bytes States Bytes States WRij dis16 WRj_ Word reg to Indir addr with disp 64K 5 7 4 6 MOV DRk dis24 Rm_ Byte reg to Indir addr with disp 16M 5 7 4 6 DRk dis24 WRj Word reg to Indir addr with disp 5 8 4 7 16M MOVH DRk hi data16 16 bit immediate data into upper 5 3 4 2 word of dword reg MOVS WRj Rm Byte reg to word reg with sign 3 2 2 1 extension WRj Rm Byt
115. automatically following a read When a good transmission is completed the read marker can be advanced to the position of the read pointer to set up for reading the next data set When a bad transmission is completed the read pointer can be reversed to the position of the read marker to enable the SIU to re read the last data set for retransmission The read marker advance and read pointer reversal can be accom plished two ways explicitly by software or automatically by hardware as specified by bits in the TXFIFOXx control register Four registers are directly involved in the operation of the transmit FIFO for endpoint x x 2 0 3 e TXDATx the transmit FIFO data register e TXCNTx the transmit FIFO byte count register e the transmit FIFO control register e TXFLG x the transmit FIFO flag register 7 2 intel UNIVERSAL SERIAL BUS 7 2 2 Data and Byte Count Registers Bytes are read from or written to TXFIFOx via the transmit FIFO data register TXDATx TXCNTx the transmit FIFO byte count register is a two byte ring buffer that stores the number of bytes in the two data sets data set 0 450 and data set 1 451 The FIFO logic for maintaining the data sets assumes that data is written to the FIFO in the following sequence 1 The 82930A first writes bytes of data to TXDATx 2 82930A writes the number of bytes written to TXDATx to the byte count register TXCNTx The SIU reads the byte count register to find
116. bit CY A A DPTR A data A dir8 ORL AJMP MOV INC MUL ESC MOV MOV CY bit addr11 CY bit DPTR AB Ri dir8 Rn dir8 B ANL ACALL CPL CPL CJNE CJNE CJNE CJNE CY bit addr11 bit CY A data rel A dir8 rel Ri data rel Rn data rel C PUSH AJMP CLR CLR SWAP XCH XCH XCH dir8 addr11 bit CY A A dir8 A Ri A Rn D POP ACALL SETB SETB DA DJNZ XCHD DJNZ dir8 addr11 bit CY A dir8 rel A Ri Rn rel E MOVX AJMP MOVX CLR MOV MOV MOV A DPTR addr11 A Ri A A dir8 A Ri A Rn F MOV ACALL MOVX CPL MOV MOV MOV DPTR A addr11 Ri A A dir8 A Ri A Rn A A 4 Table A 7 Instructions for the 82930A Architecture INSTRUCTION SET REFERENCE Bin A5x8 5 9 5 A5xB A5xC A5xD 5 5 Src x8 x9 xA xB xC xD xE xF 0 JSLE MOV MOVZ INC R short 1 SRA rel WRj4dis WRj Rm MOV reg ind reg 1 JSG MOV MOVS DEC R short 1 SRL rel WRj dis Rm WRj Rm MOV ind reg reg 2 JLE MOV ADD ADD ADD ADD rel Rm DRk dis Rm Rm WRj WRj reg op2 DRk DRk 2 3 JG MOV SLL rel DRk dis Rm reg 4 14 MOV ORL ORL ORL rel WRj OWRj dis Rm Rm WRj WRj reg op2 2 5 JSGE MOV ANL ANL ANL rel WRi dis WRj Rm Rm WRj WRj reg op2 2 6 JE MOV XRL XRL XRL rel WRj DRk d RmRm WRjWRj reg op2 is 2 7 rel DRk dis W_ opl reg 2 Rm Rm WRj WRj reg op2 DRk DRk Rj 2 8
117. cause these addresses to be accessed due to call returns or prefetches should not be located at addresses immediately below the configuration array Use an EJMP instruction five or more addresses below the configuration array to continue execution in other areas of memory 4 3 THE CONFIGURATION BITS This section provides a brief description of the configuration bits contained in the configuration bytes Figures 4 2 through 4 5 UCONFIGI 0 have five wait state bits WSA 1 0 and WSB1 0 as well as other control bits SRC Selects source mode or binary mode opcode configuration INTR Selects the bytes pushed onto the stack by interrupts The following bits configure the external memory interface PAGE Selects page nonpage mode and specifies the data port e RD1 0 Selects the number of external address bus pins and the address range for RD WR and PSEN XALE Extends the ALE pulse e WSA1 0 Selects 0 1 2 or 3 wait states for all memory regions except 01 WSB1 0 Selects 0 1 2 or 3 wait states for memory region 01 Table 4 1 External Addresses for Configuration Array Size of External Address of Address of Address Bus Configuration Array on Configuration Bytes Bits External Bus 2 on External Bus 1 16 FFF8H FFFFH UCONFIG1 FFF9H UCONFIGO FFF8H 17 1FFF8H 1FFFFH UCONFIG1 1FFF9H UCONFIGO 1FFF8H 18 3FFF8H 3FFFFH UCONFIG1 UCONFIGO 3FFF8H NOTES
118. character it represents more than one register For example represents the five registers CCAPMO through CCAPMA Some registers contain reserved bits These bits are not used in this device but they may be used in future implementations Do not write 1 to a reserved bit The value read from a reserved bit is indeter minate The terms set and clear refer to the value of a bit or the act of giving it a value If a bit is set its value is 1 setting a bit gives it a 1 value If a bit is clear its value is 0 clearing a bit gives it 0 value Signal names are shown in upper case When several signals share a common name an individual signal is represented by the signal name followed by a number Port pins are represented by the port abbrevi ation a period and the pin number e g 0 0 1 pound symbol appended to a signal name identifies an active low signal The following abbreviations are used to represent units of measure A amps amperes DCV direct current volts Kbyte kilobytes KQ kilo ohms mA milliamps milliamperes Mbyte megabytes MHz megahertz intel GUIDE TO THIS MANUAL ms milliseconds mW milliwatts ns nanoseconds pF picofarads W watts V volts uA microamps microamperes uF microfarads us microseconds microwatts 1 3 RELATED DOCUMENTS The following documents contain additional information that is useful in designing systems that in
119. counter is turned on and off with the CR bit in the CCON register To disable any given module program it for the no operation mode The occur rence of a capture software timer or high speed output event in a compare capture module sets the module s compare capture flag CCFx in the CCON register and generates PCA interrupt request if the corresponding enable bit in the register is set The CPU can read or write the CCAPxH and CCAPXxL registers at any time 11 3 1 16 bit Capture Mode The capture mode Figure 11 2 provides the PCA with the ability to measure periods pulse widths duty cycles and phase differences at up to five separate inputs External I O pins CEXO through are sampled for signal transitions positive and or negative as specified When compare capture module programmed for the capture mode detects the specified transition it captures the PCA timer counter value This records the time at which an external event is detect ed with a resolution equal to the timer counter clock period To program a compare capture module for the 16 bit capture mode program the CAPPx and CAPNx bits in the module s CCAPMXx register as follows To trigger the capture on a positive transition set CAPPx and clear CAPNx To trigger the capture on a negative transition set CAPNx and clear CAPPx To trigger the capture on a positive or negative transition set both CAPPx and CAPNx 82930A UNIVERSAL SERIAL BUS
120. destination operand SUB sets the CY borrow flag if a borrow is needed for bit 7 Otherwise CY is clear When subtracting signed integers the OV flag indicates a negative number produced when a negative value is subtracted from a positive value or a positive result when a positive number is subtracted from a negative number Bit 7 in this description refers to the most significant byte of the operand 8 16 or 32 bit The source operand allows four addressing modes immediate indirect register and direct CY AC OV N 2 Vt tFor word and dword subtractions AC is not affected Register 1 contains 11001001B and register 0 contains 54H 01010100B After executing the instruction A 127 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel SUB R1 R0 register 1 contains 75H 01110101B the CY and AC flags are clear and the OV flag is set Variations SUB Rmd Rms Binary Mode Source Mode Bytes 3 2 States 2 1 Encoding 1001 1100 5555 5556 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation SUB Rms SUB WRjd WRjs Binary Mode Source Mode Bytes 3 2 States 3 2 Encoding 1001 1101 tttt TTTT Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation SUB WRjd lt WRjd WRjs SUB DRkd DRks Binary Mode Source Mode Bytes 3 2 States 5 4 Encod
121. dual set mode FIF 1 0 Operation NextFIF 1 0 Next Flag 00 Wr RXCNT X 01 Unchanged 01 Wr RXCNT X 11 Unchanged 10 Wr RXCNT X 11 Unchanged 00 Set FFRC X 00 Unchanged 01 Set FFRC X 00 Unchanged 11 Set FFRC X 10 01 Unchanged 10 Set FFRC X 00 Unchanged XX Rev WP X Unchanged Unchanged XX Adv WM X Unchanged Unchanged When the RXFIFO is programmed to operate in single set mode valid FIF states are 00 and 01 only 5 4 Reserved Values read from these bits are indeterminate Write zeros to these bits 3 EMPTY RXFIFO Empty Flag Hardware sets this bit when the write pointer is at the same location as the read pointer Hardware clears the bit when this condition no longer holds Software can read and write this bit 2 FULL RXFIFO Full Flag Hardware sets this bit after a byte is written to RXFIFO when the write pointer is one location below the read pointer or the write marker Hardware clears the bit when this condition no longer holds Software can read and write this bit 1 URF RXFIFO Underrun Flag Hardware sets this bit when an additional byte is read from an empty RXFIFO Hardware does not clear the bit Software can read and write this bit 0 OVF RXFIFO Overrun Flag This bit is set when the SIU writes an additional byte to a full FIFO or writes a byte count to TXCNTx with FIF1 0 11 Hardware does not clear this bit Software can read and write this bit C 31 82930A UNIV
122. flash are accessed via inter nal memory regions FE and FF in the internal memory space 82930A FLASH 128 Kbytes 4289 01 Figure 15 19 Bus Diagram for Example 5 82930A in Page Mode 15 20 intel Instruction Set Reference lel APPENDIX A INSTRUCTION SET REFERENCE This appendix contains reference material for the instructions in the 82930 and is identical to the MCS 251 architecture It includes an opcode map a summary of the instructions with instruction lengths and execution times and a detailed description of each instruction It con tains the following tables Tables A 1 through A 4 describe the notation used for the instruction operands Table A 5 describes the notation used for control instruction destinations Table A 6 and Table A 7 comprise the opcode map for the instruction set Table A 8 through Table A 17 contain supporting material for the opcode map Table A 18 lists execution times for a group of instructions that access the port SFRs The following tables list the instructions giving length in bytes and execution time Add and Subtract Instructions Table A 19 Compare Instructions Table A 20 Increment and Decrement Instructions Table A 21 Multiply Divide and Decimal adjust Instructions Table A 22 Logical Instructions Table A 23 Move Instructions Table A 24 Exchange Push and Pop Instructions Table A 25 Bit Instructions Table A 26 Control In
123. from the RXFIFO the 82930A reads from this register The write pointer and read pointer are incremented automatically after a write and read respectively Figure 7 10 RXDATx Receive FIFO Data Registe Endpoint x Table 7 11 RXDATx Addresses and Reset Values Register Address Reset Value RXDATO S C4H XXH RXDAT1 S C5H XXH RXDAT2 S C6H XXH RXDAT3 S C7H XXH 7 16 intel UNIVERSAL SERIAL BUS Address See Table 7 12 x 0 3 Reset State See Table 7 12 Receive FIFO Byte Count Register 7 0 Byte Count 0 255 sm Function 7 0 RXCNTx 7 0 Byte Count The number of bytes in data set 0 or data set 1 When this register is accessed the byte count written read is for data set 0 or data set 1 depending on the data set index bits FIF1 0 in RXFLGx Following a read of this register the read write index is unchanged following a write the read write index is toggled After the SIU writes a data set to RXFIFOx it writes the byte count to this register The 82930A reads the byte count from this register to determine how many bytes to read from RXFIFOx Figure 7 11 RXCNTx Receive FIFO Byte Count Register Endpoint x WARNING Do not read RXCNTX to determine if data is present in the RXFIFO Always read the FIF bits in the appropriate RXFLGx register RXCNTXx contains random data during a receive operation read attempt to RXCNTXx du
124. handle an isochronous data transfer This bit must be cleared by software ARM Auto Receive Management If software sets this bit the write pointer and write marker are adjusted automatically based on the following conditions ISO RX Status Write Pointer Write Marker X ACK Unchanged Advanced 0 Not ACK Reversed Unchanged 1 Not ACK Unchanged Advanced When this bit is set setting REV WP or ADV WM has no effect Software can read and write this blt hardware neither clears nor sets this bit ADV WM Advance Write Marker Software sets this bit to advance the write marker to the origin of the next data set Advancing the write marker is used for back to back receptions Hardware clears this bit after the write marker is advanced Setting this bit is effective only when the REV WP ARM and bits are clear REV WP Reverse Write Pointer Software sets this bit to return the write pointer to the origin of the last data Set received as identified by the write marker REV WP is used when a data packet is bad When the SIU receives the data packet again the write starts at the origin of the previous bad data set Hardware clears this bit after the write pointer is reversed Setting this bit is effective only when the ADV WM ARM and CLR bits are all clear 7 18 Figure 7 12 RXCONx Read FIFO Control Register Endpoint x Table 7 13 RXCONx Addresses and Reset Values UNIVERSAL SER
125. has received a 0 TXDO handshake C 34 intel REGISTERS SBIE Address S A1H Reset State 00H USB Interrupt Enable Register 7 0 RXIE3 RXIE2 TXIE2 RXIE1 TXIE1 RXIEO TXIEO Function 7 RXIES Receive Done Interrupt Enable Endpoint 3 Setting this bit enables the interrupt for flag bit RXD3 in the SBI register 6 Transmit Done Interrupt Enable Endpoint 3 Setting this bit enables the interrupt for flag bit TXD3 in the SBI register 5 RXIE2 Receive Done Interrupt Enable Endpoint 2 Setting this bit enables the interrupt for flag bit RXD2 in the SBI register 4 TXIE2 Transmit Done Interrupt Enable Endpoint 2 Setting this bit enables the interrupt for flag bit TXD2 in the SBI register 3 RXIE1 Receive Done Interrupt Enable Endpoint 1 Setting this bit enables the interrupt for flag bit RXD1 in the SBI register 2 TXIE1 Transmit Done Interrupt Enable Endpoint 1 Setting this bit enables the interrupt for flag bit TXD1 in the SBI register 1 RXIEO Receive Done Interrupt Enable Endpoint 0 Setting this bit enables the interrupt for flag bit RXDO in the SBI register 0 TXIEO Transmit Done Interrupt Enable Endpoint 0 Setting this bit enables the interrupt for flag bit TXDO in the SBI register C 35 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel SBUF Address Reset
126. have the same value 77 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Bytes States Encoding Hex Code in Operation JSL rel Function Description Flags Example Bytes States Encoding Hex Code in Operation JSLE rel Function A 78 Binary Mode Source Mode Not Taken Taken Not Taken Taken 3 3 2 2 2 5 1 4 0101 1000 rel addr Binary Mode A5 Encoding Source Mode Encoding JSGE PC 2 IF OV THEN PO rel Jump if less than signed If the N flag and the OV flag have different values branch to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice The instruction JSL LABEL1 causes program execution to continue at LABEL 1 if the N flag and the OV flag have different values Binary Mode Source Mode Not Taken Taken Not Taken Taken 3 3 2 2 2 5 1 4 0100 1000 rel addr Binary Mode A5 Encoding Source Mode Encoding JSL PC PC 2 IF N OV THEN PC lt PC rel Jump if less than or equal signed intel Description Flags Example Bytes States Encoding Hex Code in Operation JZ rel Function Description Fla
127. identical to the PSW register in MCS 51 microcontrollers The PSW1 regis ter exists only in MCS 251 microcontrollers Bits CY AC RSO RS1 and OV in PSWI are iden tical to the corresponding bits in PSW i e the same bit can be accessed in either register Table 5 10 lists the instructions that affect the CY AC OV N and Z bits Table 5 10 The Effects of Instructions on the PSW and PSW1 Flags Flags Affected 1 5 Instruction Type Instruction AC 2 N Z ADD ADDC SUB X X X X X SUBB CMP Arithmetic INC DEC MUL 3 0 X X X DA X X X ANL ORL XRL CLR A X X CPL A RL RR SWAP Logical RLC RRC SRL SLL X X X SRA 4 CJNE X X X Program Control DJNE X X NOTES 1 X the flag can be affected by the instruction 0 the flag is cleared by the instruction The AC flag is affected only by operations on 8 bit operands If the divisor is zero the OV flag is set and the other bits are meaningless For SRL SLL and SRA instructions the last bit shifted out is stored in the CY bit The parity bit PSW 0 is set or cleared by instructions that change the contents of the accumulator ACC Register R11 RON 5 15 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel PSW Address S DOH Reset State 0000 0000B 0 FO RS1 RSO OV UD P 44 Function 7 Carry Flag The car
128. interrupt status but PSW is not restored to its pre interrupt status No other registers are affected For either value of INTR hardware restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed Program execution continues at the return address which normally is the instruction immediately after the point at which the interrupt request was detected If an interrupt of the same or lower priority is pending when the RETI instruction is executed that one instruction is executed before the pending interrupt is processed Flags OV N 2 Example INTR 0 The stack pointer contains OBH An interrupt was detected during the instruction ending at location 0122H On chip RAM locations 0AH and OBH contain 01H and 23H respectively After executing the instruction RETI the stack pointer contains 09H and program execution continues at location 0123H Binary Mode Source Mode Bytes 1 1 States INTR 0 9 9 States INTR 1 12 12 Encoding 0011 0010 Hex Code in Binary Mode Encoding Source Mode Encoding Operation for INTR z 0 RETI PC 15 8 SP lt SP 1 7 07 SP SP SP 5 1 119 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Operation for INTR z 1 RLA Function Description Flags Example Bytes States Encoding Hex Code in O
129. is shifted by hardware into CCAPxL when CL rolls over from FFH to 00H The frequency of the PWM output equals the frequency of the PCA timer counter input signal divided by 256 The highest frequency occurs when the Fo 4 input is selected for the tim er counter For Fose 12 MHz this is 11 7 KHz 11 11 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel To program a compare capture module for the PWM mode set the and bits in the module s register Table 11 3 lists the bit combinations for selecting module modes Also select the desired input for the timer counter by programming the CPSO and CPS1 bits in the register see Figure 11 7 Enter an 8 bit value in to specify the duty cycle of the first period of the PWM output waveform Enter an 8 bit value in to specify the duty cycle of the second period Set the timer counter run control bit CR in the CCON register to start the PCA timer counter Duty CCAPxL Cycle Output Waveform 255 0 4 0 230 10 1 128 50 0 1 25 90 0 0 100 0 4161 01 Figure 11 6 PWM Variable Duty Cycle 11 12 intel PROGRAMMABLE COUNTER ARRAY CMOD Address S D9H Reset State 00 X000B 7 0 CIDL WDTE CPS1 CPSO ECF Bit Bit Function Number Mnemonic 7 CIDL PCA Timer Coun
130. level triggered An array of key bytes used to encrypt user code in the on chip code memory as that code is read protects against unauthorized access to user s code Eraseable programmable read only memory A 16 bit or 17 bit address presented on the device pins The address decoded by an external device depends on how many of these address bits the external system uses See also internal address Field effect transistor The power conservation mode that freezes the core clocks but leaves the peripheral clocks running Current leakage from an input pin to power or ground Any member of the set consisting of the positive and negative whole numbers and zero The 24 bit address that the device generates See also external address The module responsible for handling interrupts that are to be serviced by user written interrupt service routines The delay between an interrupt request and the time when the first instruction in the interrupt service routine begins execution The time delay between an interrupt request and the resulting break in the current instruction stream The software routine that services an interrupt Glossary 3 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel level triggered LSB maskable interrupt MSB multiplexed bus n channel FET n type material nonmaskable interrupt npn transistor OTPROM p channel FET p type material PC program memory powerd
131. line It can accept a message intended for itself or a message that is being broadcast to all of the slaves and it can ignore a message sent to another slave 2 5 OPERATING CONDITIONS The 82930A is designed to operate at commercial specifications and limited operating frequen cies only This is to accommodate the Universal Serial Bus Interface which operates either at 12 Mbps or 1 5 Mbps Table 2 1 summarizes the valid operating frequencies for the 82930 and the required crystal frequency Table 2 1 82930A Operating Frequency PLLSEL2 PLLSEL1 USB Rate Internal 82930A External XTAL1 Pin 43 Pin 42 Clock Frequency Frequency Required 0 0 N A N A N A 0 1 N A N A N A 1 0 1 5 Mbps 6 Mhz 12 Mhz 1 1 12 Mbps 12 Mhz 12 Mhz 2 9 intel 82930 Memory Partitions 3 82930A MEMORY PARTITIONS 82930A has three address spaces a memory space a special function register SFR space and a register file This chapter describes these address spaces as they apply to the 829304 It also discusses the compatibility of the MCS 251 architecture and the MCS 51 architecture in terms of their address spaces 3 1 ADDRESS SPACES FOR 82930A Figure 3 1 shows the memory space the SFR space and the register file for 82930A The ad dress spaces are depicted as being eight bytes wide with addresses increasing from left to right and from bottom to top Memory Address Space 16 Mbytes
132. lt high byte of the X Rms Rmd lt low byte of the Rmd X Rms MUL WRjd WRjs Binary Mode Source Mode Bytes 3 2 A 105 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL States Encoding Hex Code in Operation MUL AB Function Description Flags Example Bytes States Encoding Hex Code in Operation NOP Function Description A 106 11 1010 1101 tttt tttt Binary Mode A5 Encoding Source Mode Encoding MUL 16 bit operands if dest jd 0 4 8 28 WRid lt high word of the WRjd X WRjs WRijd 2 lt low word of the WRjd X WRjs if dest jd 2 6 10 30 WRjd 2 lt high word of the WRjd X WRjs WRid low word of the WRjd X WRjs Multiply Multiplies the unsigned 8 bit integers in the accumulator and register B The low byte of the 16 bit product is left in the accumulator and the high byte is left in register B If the product is greater than 255 OFFH the OV flag is set otherwise it is clear The CY flag is always clear OV N 2 0 The accumulator contains 80 50H and register contains 160 0 After executing the instruction MUL AB which gives the product 12 800 3200H register B contains 32H 00110010B the accumulator contains the OV flag is set and the CY flag is clear Binary Mode 1 5 Source Mode 1 5 1010
133. m 0000 2 SRAWRj 0 E 2 0100 3 SRL Rm 1 E m 0000 4 SRL WRj 1 E 2 0100 5 SLL Rm 0000 6 SLL WRj j2 0100 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel A 3 INSTRUCTION SET SUMMARY This section contains tables that summarize the instruction set For each instruction there is a short description its length in bytes and its execution time in states NOTE Execution times are increased by executing code from external memory accessing peripheral SFRs accessing data in external memory using a wait state or extending the ALE pulse For some instructions accessing the port SFRs Px x 2 0 3 increases the execution time These cases are noted individually in the tables A 3 1 Execution Times for Instructions Accessing the Port SFRs Table A 18 lists these instructions and the execution times Case Code executes from external memory with no wait state and a short ALE not extended and accesses a port SFR Case 2 Code executes from external memory with one wait state and a short ALE not extended and accesses a port SFR e Case 3 Code executes from external memory with one wait state and an extended ALE and accesses a port SFR Times for each case are expressed as the number of state times to be added to the BASE TIME tel Table A 18 State Times to Access the Port SFRs INSTRUCTION SET REFERENCE Instruction BASE_TIME
134. of four regions 256 Kbytes See section 4 4 Configuring the External Memory Interface and section 15 6 External Memory Design Examples Locations FF FFF8H FF FFFFH are reserved for the configuration array see Chapter 4 Device Configuration The two configuration bytes for the 82930A are accessed at locations FF FFF8H FF FFF9H locations FF FFFAH FF FFFFH are reserved for configuration bytes in future products Do not attempt to execute code from locations FF FFF8H FF FFFFH Also see the caution on page 4 1 regarding execution of code from locations immediately below the configu ration array Figure 3 4 also indicates the addressing modes that can be used to access different areas of mem ory The first 64 Kbytes can be directly addressed The first 96 bytes of general purpose RAM 00 0020H 00 007FH are bit addressable Chapter 5 Instructions and Addressing discusses addressing modes 3 5 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Register Addressing 32 Bytes F Memory Address Space 16 Mbytes FF FFF8H FF FFFFH FF FFF7H FF 0000H FE 0000H FD 0000H FC FFFFH Regions 04 FB are Reserved 03 FFFFH 03 0000H 02 FFFFH 02 0000H 01 0000H 00 FFFFH 00 0080H 00 0000 8 Byte Configuration Array Indirect and Displacement Addressing 16 Mbytes Direct Addressing 64 Kbytes Bit Addressing 96 Byt x ytes A4101 02
135. read Unchanged Figure 7 3 an operational model of TXFIFOx shows the management of the data sets for writes by the 82930 to the FIFO and reads of the FIFO by the SIU After a reset the FIFO is empty upper right 007 The first write by the 82930A fills data set 0 upper left 01 If the SIU now reads the FIFO and the transmission is good software sets the ADV RM bit in TXCONx and the FIFO returns to 00 The diagram shows the other possible states of the FIFO and the transi tions between them Note that the case of both sets full 11 actually represents two states which differ in the order of the data sets The write transition from 01 to 11 places data set 1 after data set 0 in the FIFO whereas the write transition from 10 to 11 places data set 0 after data set 1 in the FIFO In Figure 7 3 software manages the movement of the read marker and read pointer If This bit pair is shorthand for FIF1 0 00 similarly 01 is shorthand for FIF1 0 01 etc 7 4 intel UNIVERSAL SERIAL BUS you set the ATM bit in TXCONXx the hardware automatically moves the read marker and read pointer and software does not set ADV RM or REV RP Table 7 4 summarizes how the actions following a transmission depend on the ISO bit the ATM bit the T ACK bit and the T ERR bit Table 7 4 Truth Table for TXFIFO Management ISO ATM T ERR T ACK gt 3 TXCONx 2 TXSTATx 1 TXSTATx 0
136. result was zero This instruction provides a simple way of executing a program loop a given number of times or for adding a moderate time delay from 2 to 512 machine cycles with a single instruction The instruction sequence R2 8 CPL P1 7 DJNZ R2 TOGGLE TOGGLE toggles P1 7 eight times causing four output pulses to appear at bit 7 of output Port 1 Each pulse lasts three states two for DJNZ and one to alter the pin Binary Mode Source Mode Not Taken Taken Not Taken Taken 3 3 3 3 3 6 3 6 1101 0101 direct addr rel addr Binary Mode Encoding Source Mode Encoding intel INSTRUCTION SET REFERENCE Operation DJNZ PC PC 2 dir8 dir8 1 IF dir8 gt 0 or dir8 0 THEN PC PC rel DJNZ Rn rel Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes 2 2 3 3 States 2 5 3 6 Encoding 1101 irrr rel addr Hex Code in Binary Mode Encoding Source Mode A5 Encoding Operation DJNZ lt 2 lt Rn 1 IF Rn gt 0 or Rn 0 THEN lt PC rel ECALL dest Function Extended call Description Calls subroutine located at the specified address The instruction adds four to the program counter to generate the address of the next instruction and then pushes the 24 bit result onto the stack high byte first incrementing the stack pointer by three The 8 bits of the high w
137. routine should be called on an SOF token Post receive flow diagrams for non isochronous data are in Figures 8 21 and Figures 8 22 Post receive flow diagrams for isochronous data are in Figure 8 23 and Figure 8 24 Start Identify endpoint Clear interrupt Read and clear status flags If ATM 0 Check hshk from host Adjust write marker and write pointer Check hshk and errors save or discard data RETI A4268 01 Figure 8 21 Post receive Operations for Non isochronous Data Overview 8 27 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Start RXSTATX R_ERR bit RXSTATx 1 must 1 OVF bit RXFLGx 1 marker Set ADV_WM CON cip Another data y Set REV WP Rx 0 set in FIFO Read FIFO OE pensum Oe Clear bit 7 RETI Note Operations in box are in this routine for ARM 0 and are executed automatically by hardware for ARM 1 A4271 01 Figure 8 22 Post receive Operations for Non isochronous Data Detail 8 28 intel USB OPERATING MODES Start Identify endpoint Read and clear status flags If ARM 0 Check hshk from host Adjust write marker and write pointer Read data packet or make up zero length packet RET 4269 01 Figure 8 23 Post receive Operations for Isochronous Data Overview 8 29 82930A UNIVER
138. serial I O mode select bit SMODO z 0 See Figure 14 1 and Figure 12 2 SCON 14 2 2 Power Off Flag Hardware sets the Power Off Flag POF in PCON when Vcc rises from lt 3 V to gt 3 V to indicate that on chip volatile memory is indeterminate e g at power on The POF can be set or cleared by software In general after a reset check the status of this bit to determine whether a cold start reset or a warm start reset occurred see section 13 4 Reset After a cold start user software should clear the If POF 1 is detected at other times do a reset to reinitialize the chip since for 3 V data may have been lost or some logic may malfunctioned 14 1 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel PCON Address 5 87 Reset State 00 00008 7 0 SMOD1 SMODO POF GF1 GFO PD IDL Bit Bit Function Number Mnemonic unctio 7 SMOD1 Double Baud Rate Bit When set doubles the baud rate when timer 1 is used and mode 1 2 or 3 is selected in the SCON register See Baud Rates in Chapter 12 6 SMODO SCON 7 Select When set read write accesses to SCON 7 are to the FE bit When clear read write accesses to SCON 7 to the SMO bit See Figure 12 2 SCON Serial Port Control Register 5 Reserved The value read from this bit is indeterminate Write a zero to this bit 4 POF Power Off Flag Set by hardware as Vcc rises
139. states are added for the current instruction to complete The actual latency is 26 states Worst case latency calculations predict 43 states for this example due to inclusion of total DIV instruction time less One state Table 6 8 Actual vs Predicted Latency Calculations Latency Factors Actual Predicted Base Case Minimum Fixed Time 16 16 INTO External Request 1 1 External Execution 2 64K Byte Stack Location 4 Execution Time for Current DIV Instruction 3 20 TOTAL 26 43 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel 6 8 2 4 Blocking Conditions If all enable and priority requirements have been met a single prioritized interrupt request at a time generates a vector cycle to an interrupt service routine see CALL instructions Appendix A Instruction Set Reference There are three causes of blocking conditions with hardware gen erated vectors 1 An interrupt of equal or higher priority level is already in progress defined as any point after the flag has been set and the RETI of the ISR has not executed 2 The current polling cycle is not the final cycle of the instruction in progress 3 The instruction in progress is RETI or any write to the IE1 IPHO IPH1 IPLO or IPL1 registers Any of these conditions blocks calls to interrupt service routines Condition two ensures the in struction in progress completes before the system vectors to the ISR Condition t
140. terface between the SIE and the 8XC251SB core as described in section 7 4 1 7 4 2 1 USB interface The SIE is connected to the USB data signal via a differential output driver and a differential sen sor transceiver Please refer to Driver Characteristics section the Receiver Characteristics section in the Electrical chapter of Universal Serial Bus Specification for more information on the driver and receiver characteristics The USB data signal timing and electrical characteristics can be found in the Timing Electrical Characteristics section and the Timing Diagram section Data signaling within a packet is done with differential signals Refer to the signaling levels table in the Electrical chapter of Universal Serial Bus Specification The defined data signaling con sists of differential 1 differential O idle state non idle K state start of packet end of packet disconnect connect reset and resume The USB employs NRZI data encoding when transmitting packets Refer to the Data Encoding Decoding in the Universal Serial Bus Speci fication for the description of NRZI data encoding and decoding To ensure adequate signal tran sitions bit stuffing is employed by SIE when transmitting data The SIE also does bit unstuffing when receiving data Please refer to the Flow Diagram for Bit Stuffing figure in the Stuff ing section of the Electrical chapter for more information on bit s
141. terminated by a valid stop bit NOTE The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 i e setting the SM2 bit in the SCON register in mode 0 has no effect To support automatic address recognition a device is identified by a given address and a broad cast address 12 5 4 Given Address Each device has an individual address that is specified in the SADDR register the SADEN reg Ister is a mask byte that contains don t care bits defined by zeros to form the device s given ad dress These don t care bits provide the flexibility to address one or more slaves at a time The following example illustrates how a given address is formed To address a device by its individ ual address the SADEN mask byte must be 1111 1111 SADDR 0101 0110 SADEN 1111 1100 Given 010101XX The following is an example of how to use given addresses to address different slaves Slave A SADDR 1111 0001 Slave C SADDR 11110010 SADEN 11111010 SADEN 1111 1101 Given 11110X0X Given 1111 00X1 Slave B SADDR 1111 0011 SADEN 1111 1001 Given 1111 0XX1 The SADEN byte is selected so that each slave may be addressed separately For Slave A bit 0 the LSB is a don t care bit for Slaves B and C bit 0 is a 1 To communicate with Slave A only the master must send an address where bit 0 is clear e g 1111 0000 For Slave A bit 1 is a 0 for Slaves B and C bit 1 is a don t care bit T
142. the external interrupt requests service in the state just prior to the next sample re sponse is much quicker One state asserts the request one state samples and one state requests the context switch If at that point the same instruction conditions exist one additional state time is needed to complete the 10 state instruction prior to the context switch see Figure 6 12 The total response time in this case is four state times The programmer must evaluate all pertinent conditions for accurate predictability Response Time 4 OSC State Time INTO WN 7 Sample INTO Request Ten State muon 0 A4154 02 Figure 6 12 Response Time Example 2 6 8 2 2 Computation of Worst case Latency With Variables Worst case latency calculations assume that the longest 82930A instruction used in the program must fully execute prior to a context switch The instruction execution time is reduced by one state with the assumption the instruction state overlaps the request state therefore 16 bit DIV is 21 state times 1 20 states for latency calculations The calculations add fixed and variable interrupt times see Table 6 7 to this instruction time to predict latency The worst case latency both fixed and variable times included is expressed by a pseudo formula FIXED TIME VARIABLES LONGEST INSTRUCTION MAXIMUM LATENCY PREDICTION intel INTERRUPTS Table
143. the jump address bit addressing The instruction contains the bit address More detailed descriptions of the addressing modes are given in Data Addressing Modes Bit Addressing and Addressing Modes for Control Instructions in this chapter 5 3 DATA INSTRUCTIONS Data instructions consist of arithmetic logical and data transfer instructions for 8 bit 16 bit and 32 bit data This section describes the data addressing modes and the set of data instructions 5 3 4 Data Addressing Modes This section describes the data addressing modes which are summarized in two tables Table 5 4 for the instructions that are native to the MCS 51 architecture and Table 5 4 for the data instruc tions in the MCS 251architecture 5 4 NOTE References to registers RO R7 WRO WRO DRO and DR2 always refer to the register bank that is currently selected by the PSW and PSWI registers see section 5 6 Program Status Words Registers in all banks active and inactive can be accessed as memory locations in the range 00H 1FH NOTE Instructions from the MCS 51 architecture access external memory through the region of memory specified by byte DPXL in the extended data pointer register DPX DR56 Following reset DPXL contains 01H which maps the external memory to region 01 You can specify a different region by writing to DR56 or the DPXL SFR See section 3 3 2 Dedicated Registers INSTRUCTIONS AND ADDRESSING intel 5 3 1
144. the pin value prior to a poll of interrupts The sample occurs in the first half of the state time and the poll request occurs in the second half of the next state time Therefore this sample and poll request portion of the minimum fixed response and latency time is five states for internal interrupts and six states for external interrupts External interrupts must remain active for at least five state times to guarantee interrupt recognition when the request occurs immediately after a sample has been taken 1 requested in the second half of a sample state time If the external interrupt goes active one state after the sample state the pin is not resampled for another three states After the second sample is taken and the interrupt request is recognized the interrupt controller requests the context switch The programmer must also consider the time to complete the instruction at the moment the context switch request is sent to the execution unit If 9 states of a 10 state instruction have completed when the context switch is requested the total response time is 6 states with a context switch immediately after the final state of the 10 state instruction see Figure 6 11 Response Time 6 OSC State Time INTO Sample INTO __10 LT LI LI Request LJ Ten State Pee A4155 02 Figure 6 11 Response Time Example 1 6 15 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Conversely if
145. timer or counter operation T C 1 and mode of operation M11 and MOI The TCON register provides timer 1 control functions overflow flag TF1 run control TR1 inter rupt flag IE1 and interrupt type control Timer 1 operation in modes 0 1 and 2 is identical to timer 0 Timer 1 can serve as the baud rate generator for the serial port Mode 2 is best suited for this purpose For normal timer operation GATEI 0 setting TR1 allows timer register TL1 to be increment ed by the selected input Setting and allows external pin INT1 to control timer op eration This setup can be used to make pulse width measurements See section 10 5 2 Pulse Width Measurements Timer 1 overflow count rolls over from all 1s to all 06 sets the flag generating an interrupt request When timer 0 is in mode 3 it uses timer 175 overflow flag TF1 and run control bit TR1 For this situation use timer 1 only for applications that do not require an interrupt such as a baud rate generator for the serial interface port and switch timer 1 in and out of mode 3 to turn it off and on Interrupt Request Interrupt Request Overflow A4112 02 Figure 10 4 Timer 0 in Mode 3 Two 8 bit Timers 10 6 intel TIMER COUNTERS AND WATCHDOG TIMER TMOD Address 5 89 Reset State 0000 0000B 7 0 GATE1 C T1 M11 01 GATEO C TOst M10 00 Bit Bit Function N
146. to the timer register When GATE1 1 and TR1 1 external signal INT1 gates the timer input 6 1 Timer 1 Counter Timer Select 1 0 selects timer operation timer 1 counts the divided down System clock 1 1 selects counter operation timer 1 counts negative transitions on external pin T1 5 4 M11 M01 Timer 1 Mode Select M11 M01 0 0 Mode 0 8 bit timer counter TH1 with 5 bit prescalar TL1 0 1 Mode 1 16 bit timer counter 1 0 Mode 2 8 bit auto reload timer counter TL1 Reloaded from 1 at overflow 1 1 Mode 3 Timer 1 halted Retains count 3 GATEO Timer 0 Gate When GATEO 0 run control bit TRO gates the input signal to the timer register When GATEO 1 and TRO 1 external signal INTO gates the timer input 2 Timer 0 Counter Timer Select 0 selects timer operation timer 0 counts the divided down System clock 0 1 selects counter operation timer 0 counts negative transitions on external pin TO 1 0 M10 00 Timer 0 Mode Select M10 00 0 0 Mode 0 8 bit timer counter TO with 5 bit prescaler TLO 0 1 Mode 1 16 bit timer counter 1 0 Mode 2 8 bit auto reload timer counter TLO Reloaded from THO at overflow 1 1 Mode 3 TLO is an 8 bit timer counter THO is an 8 bit timer using timer 1 s TR1 and TF1 bits C 45 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel THO TLO Address THO S
147. two bytes in the reverse order and uses them as the 16 bit return address in region FF For INTR 1 an interrupt pushes the three PC bytes and the PSW1 register onto the stack in the following order PSW1 PC 23 16 PC 7 0 PC 15 8 The RETI instruction pops these four bytes and then returns to the specified 24 bit address which can be anywhere in the 16 Mbyte address space 4 13 intel Instructions and Addressing intel CHAPTER 5 INSTRUCTIONS AND ADDRESSING The instruction set for the 82930A architecture supports the instruction set for the MCS 51 ar chitecture and MCS 251 architecture This chapter describes the addressing modes and summa rizes the instruction set which is divided into data instructions bit instructions and control instructions Appendix A Instruction Set Reference contains an opcode map and a detailed de scription of each instruction The program status word registers PSW and PSW1 are also de scribed NOTE The instruction execution times given in Appendix are for code executing from external memory and for data that is read from and written to on chip RAM Execution times are increased by accessing peripheral SFRs accessing data in external memory using a wait state or extending the ALE pulse For some instructions accessing the port SFRs Px x 3 0 increases the execution time These cases are noted individually in the tables in Appendix A 51 SOURCE MODE OR BINARY MODE OPCODES
148. with internal pullups RXD P3 1 TXD P3 3 2 0 5 4 1 0 P3 6 3 7 RD A16 PLLSEL1 Phase Locked Loop Select 1 Selects data rate see Table B 5 xx PLLSEL2 Phase Locked Loop Select 2 Selects data see Table B 5 PSEN Program Store Enable Read signal output Asserted for the memory address range specified by configuration bits RD1 0 UCONFIGO 3 2 See RD and Table B 4 RD Read Read signal output Asserted for the memory address range P3 7 A16 specified in Table B 4 Alternately as determined by configuration bits RD1 0 UCONFIGO 3 2 this signal pin serves as external address bit A16 See PSEN and Table B 4 The descriptions of A15 8 P2 7 0 and 7 0 0 7 0 for the nonpage mode chip configuration If the chip is configured for page mode operation port 0 carries the lower address bits A7 0 and port 2 carries the upper address bits A15 8 and the data 07 0 B 4 SIGNAL DESCRIPTIONS Table B 3 Signal Descriptions Continued Signal Name Type Description Multiplexe d With RST Reset Reset input to the chip Holding this lead high for 64 oscillator periods while the oscillator is running resets the device The port leads are driven to their reset conditions when a voltage greater than is applied whether or not the oscillator is running This lead has an internal pulldown resistor which allows the device to be reset by connectin
149. write pointer 7 2 V Vcc 13 2 during reset 13 5 power off flag 14 1 power on reset 13 6 powerdown mode 14 5 14 6 W Wait state 4 10 5 1 A 1 A 12 configuration bits 4 2 4 10 extended ALE 4 10 RD WR PSEN 4 10 4 11 Watchdog timer SFRs C 3 Watchdog timer hardware 10 16 10 18 enabling disabling 10 16 in idle mode 10 18 in powerdown mode 10 18 initiating reset 13 5 overflow 10 16 SFR WDTRST 3 16 WDTRST 3 16 10 2 10 16 C 3 C 54 WR 9 1 described 15 2 X XALE bit 4 10 XCH instruction 5 9 A 23 XCHD instruction 5 9 A 23 XRL instruction 5 9 XTALI XTAL2 13 2 Index 8 In tel
150. 00 1011 5555 00 Hex Code Binary Mode A5 Encoding Source Mode Encoding Operation INC Rm lt Rm short INC WRj short Binary Mode Source Mode Bytes 3 2 States 2 1 Encoding 0000 1011 tttt 01 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation INC WRj lt WRj short INC DRk short Binary Mode Source Mode Bytes 3 2 States 4 3 Encoding 0000 1011 uuuu 11 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation INC shortdata pointer INC DPTR Function Increment data pointer A 66 intel Description Flags Example Bytes States Encoding Hex Code in Operation JB bit51 rel JB bit rel Function Description Flags Example Variations JB bit51 rel INSTRUCTION SET REFERENCE Increments the 16 bit data pointer by one A 16 bit increment modulo 219 is performed an overflow of the low byte of the data pointer DPL from OFFH to 00H increments the high byte of the data pointer DPH by one An overflow of the high byte DPH does not increment the high word of the extended data pointer DPX DR56 OV N 2 Registers DPH and DPL contain 12H and OFEH respectively After the instruction sequence INC DPTR INC DPTR INC DPTR DPH and DPL contain 18H and 01H respectively Binary Mode Source Mode 1 1 1 1 1010 00
151. 0011 JNB bit 0111 ORL CY bit 1000 ANL CYbit 1001 MOV bit CY 1010 MOV CY bit 1011 CPL bit 1100 CLR bit 1101 SETB bit 1110 ORL bit 1111 ANL CY bit A 8 intel INSTRUCTION SET REFERENCE Table A 12 PUSH POP Instructions Instruction Byte O x Byte 1 Byte 2 Byte 3 PUSH 0000 0010 data PUSH data16 0000 0110 data16 high data16 low PUSH Rm 1000 PUSH WRj 2 1001 PUSH DRk C A k 4 1011 MOV DRk PC k 4 0001 POP Rm D A m 1000 D A j 2 1001 POP DRk D A k 4 1011 Table A 13 Control Instructions Instruction Byte 0 Byte 1 Byte 2 Byte 3 EJMP addr24 8 23 16 115 8 7 0 ECALL addr24 9 addr 23 16 addr 15 8 addr 7 0 LUMP WRj 8 9 j 2 0100 WRj 9 9 j 2 0100 EJMP DRk 8 9 k 4 1000 ECALL DRk 9 9 k 4 1000 ERET A A JE rel 8 8 rel JNE rel 7 8 JLE rel 2 8 rel JG rel 3 8 rel JSL rel 4 8 rel JSGE rel 5 8 rel JSLE rel 0 8 rel JSG rel 1 8 rel TRAP B 9 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Table A 14 Displacement Extended MOVs intel Instruction Byte 0 Byte 1 Byte 2 Byte 3 Rm WRi dis 0 9 m 2 dis 15 8 dis 7 0 WRk WRi dis 419 2 k2 dis
152. 011 direct addr dir8 addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation XRL Rm Rm v 9 16 XRL WRij dir16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding 0110 1110 tttt 0111 direct addr direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation XRL WRJ lt WRj v dir16 XRL Rm QWrj Binary Mode Source Mode Bytes 4 3 States 3 2 Encoding 0110 1110 tttt 1001 5556 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation XRL Rm lt Rm WR XRL Rm Drk Binary Mode Source Mode Bytes 4 3 States 4 3 A 141 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Encoding 0110 1110 uuuu 1011 5556 0000 Hex Code In Binary Mode A5 Encoding Source Mode Encoding Operation XRL Rm lt Rm v DRk A 142 intel B signal Descriptions APPENDIX SIGNAL DESCRIPTIONS This appendix provides reference information for the pin functions of the 82930A Pinouts for the 68 lead cerquad package are shown in Figure B 1 Table B 1 lists the signals grouped by func tion Table B 2 defines the columns used in Table B 3 which describes the signals Table B 4 lists the memory signal selections for configuration bits RD1 0 referred to in Table B 3 A8 P2 0 8 A A9 P2 1 9 7 M A10 P2 2 6 FA
153. 1 or timer 2 see section 12 6 Baud Rates Modes 2 and 3 Modes 2 and 3 are full duplex asynchronous modes The data frame Figure 12 4 consists of 11 bits one start bit eight data bits transmitted and received LSB first one programmable ninth data bit and one stop bit Serial data is transmitted on the TXD pin and received pin On receive the ninth bit is read from the RB8 bit in the SCON register On transmit the ninth data bit is written to the TB8 bit in the SCON register Alternatively you can use the ninth bit as a command data flag mode 2 the baud rate is programmable to 1 32 or 1 64 of the oscillator frequency mode 3 the baud rate is generated by overflow of timer 1 or timer 2 Data Byte Start Bit Ninth Data Bit Modes 2 and 3 only Stop Bit A2261 01 Figure 12 4 Data Frame Modes 1 2 and 3 12 2 2 1 Transmission Modes 1 2 3 Follow these steps to initiate a transmission 1 Write to the SCON register Select the mode with the SMO and SM1 bits and clear the REN bit For modes 2 and 3 also write the ninth bit to the TB8 bit 2 Wirite the byte to be transmitted to the SBUF register This write starts the transmission 12 2 2 2 Reception Modes 1 2 3 To prepare for a reception set the REN bit in the SCON register The actual reception is then ini tiated by a detected high to low transition on the RXD pin 12 6 intel SERIAL
154. 11 Binary Mode Encoding Source Mode Encoding INC DPTR DPTR 1 Jump if bit set If the specified bit is a one jump to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC after incrementing the PC to the first byte of the next instruction The bit tested is not modified OV N 2 Input port 1 contains 11001010 and the accumulator contains 56 01010110B After the instruction sequence JB P1 2 LABEL1 JB ACC 2 LABEL2 program execution continues at label LABEL2 A 67 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes 3 3 3 3 States 2 5 2 5 Encoding 0010 0000 bit addr rel addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation JB lt 3 IF 0451 1 THEN lt PC rel JB bit rel Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes 5 5 4 4 States 4 7 3 6 Encoding 1010 1001 0010 0 yy direct addr rel addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation JB lt 3 IF bit 1 THEN PC rel JBC bit51 rel JBC bit rel Function Jump if bit is set and clear bit Descr
155. 126 0000 1110 SSSS 0000 Binary Mode A5 Encoding Source Mode Encoding SRA Rm 7 lt Rm 7 Rm a lt Rm a 1 CY lt Rm 0 Binary Mode Source Mode 3 2 2 1 0000 1110 tttt 0100 Binary Mode A5 Encoding Source Mode Encoding SRA WRj 15 lt WRj 15 WRj b lt WRj b 1 CYc WR 0 Shift logical right by 1 bit SRL shifts the specified variable to the right by 1 bit replacing the MSB with a zero The bit shifted out LSB is stored in the CY bit OV N 2 Register 1 contains OC5H 11000101 After executing the instruction SRL register 1 Register 1 contains 62H 01100010B and CY 1 Binary Mode Source Mode 3 2 intel States Encoding Hex Code in Operation SRL WRj Bytes States Encoding Hex Code in Operation INSTRUCTION SET REFERENCE 2 1 0001 1110 5556 0000 Binary Mode A5 Encoding Source Mode Encoding SRL Rm 7 0 Rm a lt Rm a 1 lt Rm 0 Binary Mode Source Mode 3 2 2 1 0001 1110 tttt 0100 Binary Mode A5 Encoding Source Mode Encoding SRL WRj 15 0 WRj b lt WRj b 1 CYc WRj 0 SUB dest src Function Description Flags Example Subtract Subtracts the specified variable from the destination operand leaving the result in the
156. 15 8 dis 7 0 MOV Rm DRk dis 219 m 4 dis 15 8 dis 7 0 MOV WRj DRk dis 6 9 j2 k 4 dis 15 8 dis 7 0 MOV QWRj dis Rm 119 2 dis 15 8 dis 7 0 MOV WRi dis WRk 5 9 k2 dis 15 8 dis 7 0 DRk dis Rm 3 9 m k 4 dis 15 8 dis 7 0 MOV QDRk dis WRj 7 9 j2 k 4 dis 15 8 dis 7 0 MOVS WRj Rm 1 j 2 m MOVZ WRj Rm OJA j2 m MOV WRj WRj 0 B j2 1000 j 2 0000 MOV WRj DRk 0 B k 4 1010 2 0000 MOV QWRj WRj 1 B 2 1000 2 0000 MOV DRk WRj 1 B k 4 1010 j 2 0000 MOV dir8 Rm 7 m 0001 dir8 addr MOV dir8 WRj 7 2 0101 dir8 addr MOV dir8 DRk 7 k 4 1101 dir8 addr MOV dir16 Rm 7 A m 0011 dir16 addr high dir16 addr low MOV dir16 WRj 7 2 011 6 addr high dir16 addr low MOV dir16 DRk 7 1111 dir16 addr high dir16 addr low MOV WRj Rm 7 2 1001 0000 MOV DRk Rm 7 k 4 1011 m 0000 A 10 Table 15 INC DEC INSTRUCTION SET REFERENCE Instruction Byte 0 Byte 1 1 INC Rm short 0 m 00 55 2 INC WRj short O B j 2 01 55 3 INC DRk short 0 B 11 ss 4 DEC Rm short 1 B m 00 55 5 DEC WRj short 1 j2 01 ss 6 DEC DRk short 1 B 11 ss Table A 16 Encoding for INC DEC 55 short 00 1 01 10 Table A 17 Shifts Instruction Byte 0 Byte 1 1 SRARm 0 E
157. 2 DPTR 3 13 in jump instruction 5 12 DPX 3 5 3 11 3 13 5 4 DPXL 3 13 C 13 as SFR 3 15 C 2 external data memory mapping 3 5 5 4 5 9 reset value 3 5 E EA description 15 2 ECALL instruction 5 14 A 25 ECI 9 1 EJMP instruction 5 13 A 25 ERET instruction 5 14 A 25 Escape prefix A5H 4 11 extended ALE A 1 A 12 Extended stack pointer See SPX External address lines number of 4 6 See also External bus External bus inactive 15 3 pin status 15 10 15 11 structure in page mode nonpage mode 15 5 External bus cycles 15 3 definitions 15 3 extended ALE wait state 15 9 extended PSEN RD WR wait state 15 7 extended RD WR PSEN wait state 15 7 nonpage mode 15 3 15 5 page mode 15 5 15 7 page hit vs page miss 15 5 intel External code memory example 15 13 15 20 idle mode 14 4 powerdown mode 14 5 External memory 3 8 design examples 15 11 15 20 MCS 51 architecture 3 2 3 4 3 5 External memory interface 15 1 configuring 4 6 signals 15 1 External RAM example 15 16 exiting idle mode 14 5 F FO flag 5 16 Flash memory example 15 11 15 13 15 20 G Given address See Serial I O port H Hardware application notes 1 5 ports 9 1 9 7 external memory access 9 6 9 7 latches 9 1 loading 9 6 pullups 9 5 quasi bidirectional 9 5 SFRs 3 15 See also Ports 0 3 Idle mode 2 5 14 1 14 4 14 5 entering 14 4 exiting 13 5 14 5 external bus 15 3 IE 6
158. 2 7 0 15 8 Address Lines Nonpage Mode Address Data Lines Mode y o P3 0 RXD Serial Port Receive Data Input P3 1 TXD Serial Port Transmit Data Output O O P3 2 INTO External Interrupt 0 P3 3 VO INT1 External Interrupt 1 P3 4 VO TO Timer 0 Input P3 5 VO T1 Timer 1 Input 3 6 WR Write Signal to External Memory 7 I O RD A16 Read Signal to External Memory or 17th Address Bit 9 2 1 0 CONFIGURATIONS Each port SFR operates via type D latches as illustrated in Figure 9 1 for ports 1 and 3 A CPU write to latch signal initiates transfer of internal bus data into the type D latch A CPU read 9 1 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel latch signal transfers the latched Q output onto the internal bus Similarly a read pin signal transfers the logical level of the port pin Some port data instructions activate the read latch sig nal while others activate the read pin signal Latch instructions are referred to as read modify write instructions see Read Modify Write Instructions on page 9 4 Each I O line may be in dependently programmed as input or output 9 3 PORT 1 AND PORT 3 Figure 9 1 shows the structure of ports 1 and 3 which have internal pullups An external source can pull the pin low Each port pin can be configured either for general purpose I O or for its al ternate input or output function Tabl
159. 23 16 SP lt SP 1 SP lt PC 15 8 SP SP 1 SP lt PC 7 0 lt DRk Extended jump Causes an unconditional branch to the specified address by loading the 8 bits of the high order and 16 bits of the low order words of the PC with the second third and fourth instruction bytes The destination may be therefore be anywhere in the full 16 Mbyte memory space OV N intel INSTRUCTION SET REFERENCE Example The label JMPADR is assigned to the instruction at program memory location 123456H The instruction is EJMP JMPADR Variations EJMP addr24 Binary Mode Source Mode Bytes 5 4 States 6 5 Encoding 1000 1010 23 addr15 addr8 addr7 addro addr16 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation EJMP PC addr 23 0 EJMP DRk Binary Mode Source Mode Bytes 3 2 States 7 6 Encoding 1000 1001 uuuu Hex Code in Binary Mode Encoding Source Mode Encoding Operation EJMP PC DRK ERET Function Extended return Description Pops byte 2 byte 1 and byte 0 of the 3 byte PC successively from the stack and decrements the stack pointer by 3 Program execution continues at the resulting address which normally is the instruction immediately following ECALL Flags No flags are affected Example The stack pointer contains OBH On chip RAM locations 08H 09
160. 3 State Configuration Bits essem eene 4 10 4 4 3 1 Configuration Bits WSA1 02 WSB1 08 esses 4 10 4 4 8 2 Configuration Bit XALE esses 410 4 5 OPCODE CONFIGURATIONS 4 11 4 5 1 Selecting Binary Mode or Source 4 12 4 6 INTERRUPT STACK MODE INTR eese enne enne nns 4 13 CHAPTER 5 INSTRUCTIONS AND ADDRESSING 5 1 SOURCE MODE OR BINARY MODE OPCODES RUE 5 2 PROGRAMMING FEATURES OF THE 82930A 5 1 5 2 1 Data LEE 5 1 5 2 1 1 Order of Byte Storage for Words and Double Words 5 2 5 2 2 Register Notation reete acai tie dodo i d UL ce E ERI seeds 5 2 5 2 3 Address Notation itt E RE EE ERG Ue RM RENAL 5 2 5 2 4 X Addressing Modes 5 4 5 3 DATA INSTRUCTIONS eren nennen 5 4 5 3 1 Data Addressing 5 4 5 8 1 1 Register Addressing eene emen enne nnne rnnt 7D 6 31 2 Immediate deren WEN IIT iH DID S303 be e M eat io 5 5 5 9sT1 4 0 5 3 1 5 Displacement 5 7 5 3 2 Arithmetic
161. 3 6 Figure 3 4 82930A Memory Space intel 82930A MEMORY PARTITIONS Memory Address Space 16 Mbytes Region FF Detail Configuration Array FF FFF8H FF FFFFH FF FFF7H FE FFFFH External Memory External Memory FE 0000H FD FFFFH External Memory FD 0000H FF 0000H FC FFFFH External Memory FC 0000H Regions 04 are Reserved 03 FFFFH External Memory 03 0000H 02 FFFFH Region 00 Detail External Memory 00 FFFFH 02 0000H External Memory 01 FFFFH 00 0420H External Memory 01 0000H 00 041FH 1 Kbyte On chip RAM 00 FFFFH 00 0020H 00 001FH 32 byte Register File 00 0000H A4264 01 Figure 3 5 Hardware Implementation of the 82930A Memory Space Figure 3 5 shows how areas of the memory space are implemented by on chip RAM and external memory The first 32 bytes of on chip RAM store banks 0 3 of the register file see section 3 3 82930A Register File 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel 3 2 1 On chip General purpose Data RAM On chip RAM 1 Kbyte provides general data storage Figure 3 5 Instructions cannot execute from on chip data RAM The data is accessible by direct indirect and displacement addressing Locations 00 0020H 00 007FH are also bit addressable 3 2 2 External Memory Regions 01 02 03 FC FD FE and FF and portions of regions 00 of the memory space are implemented as external memory Figure 3 5
162. 4 4 2 3 3 2 CY Complement carry 1 1 1 1 CPL bit51 Complement dir bit 2 2 2 2 2 2 bit Complement dir bit 4 4 2 3 3 2 RU CY bit5 1 AND dir bit to carry 2 1 3 2 1 3 CY bit AND dir bit to carry 4 3 3 3 2 3 CY bit51 AND complemented dir bit to carry 2 1 3 2 1 3 CY bit AND complemented dir bit to carry 4 3 3 3 2 3 BE CY bit5 1 OR dir bit to carry 2 1 3 2 1 3 OR dir bit to carry 4 3 3 3 2 3 CY bit51 OR complemented dir bit to carry 2 1 3 2 1 3 CY bit OR complemented dir bit to carry 4 3 3 3 2 3 CY bit51 Move dir bit to carry 2 1 3 2 1 3 MOV CY bit Move dir bit to carry 4 3 3 3 2 3 bitb1 CY Move carry to dir bit 2 2 2 2 2 2 bit CY Move carry to dir bit 4 4 2 3 3 2 NOTES 1 A shaded cell denotes an instruction in the 59 51 architecture 2 If this instruction addresses an I O port Px x 0 3 add 2 to the number of states 3 If this instruction addresses an I O port Px x 0 3 add 1 to the number of states A 24 intel INSTRUCTION SET REFERENCE Table A 27 Summary of Control Instructions Binary Mode Source Mode Mnemonic dest src Notes Bytes States 2 Bytes States 2 ACALL addr11 Absolute subroutine call 2 9 2 9 DRk Extended subroutine call indirect 3 12 2 11 ECALL addr24 Extended su
163. 41H 01000001 When the destination is a directly addressed byte this instruction clears combinations of bits in any RAM location or hardware register The mask byte determining the pattern of bits to be cleared would either be an immediate constant contained in the instruction or a value computed in the register or accumulator at run time The instruction ANL P1 01110011B clears bits 7 3 and 2 of output port 1 Binary Mode Source Mode 2 2 2t 2t tlf this instruction addresses a port x 0 3 add 2 states 0101 0010 direct addr Binary Mode Encoding Source Mode Encoding ANL dir8 lt dir8 A Binary Mode Source Mode 3 3 3t 3t tlf this instruction addresses a port Px x 0 3 add 1 state 0101 0011 direct addr immed data Binary Mode Encoding Source Mode Encoding ANL dir8 lt dir8 A data Binary Mode Source Mode 2 2 intel States Encoding Hex Code in Operation ANL A dir8 Bytes States Encoding Hex Code in Operation ANL A GRi Bytes States Encoding Hex Code in Operation ANL A Rn Bytes States Encoding INSTRUCTION SET REFERENCE 0101 0100 immed data Binary Mode Encoding Source Mode Encoding ANL lt A A data Binary Mode Source Mode 2 2 11 11 tlf this instruction addresses a port Px x 0 3 add 1 state 0101 0101 dire
164. 5 can serve for these tasks As a result the accumulator does not play the central role that it has in MCS 51 microcontrollers t Bits in the PSW and PSWI registers reflect the status of the accumulator There no equivalent status indicators for the other registers 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL In Register File SFRs Stack Pointer High Stack Pointer 60 61 62 63 DR60 Extended Stack Pointer SPX Data Pointer Extended High Data Pointer Extended Low Data Pointer High S 83H Data Pointer Low S 82H 56 57 58 59 DR56 Extended Data Pointer DPX R10 B Register R11 Accumulator ACC 4292 01 Figure 3 8 Dedicated Registers the Register File and their Corresponding SFRs 3 3 2 2 Extended Data Pointer DPX Dword register DR56 is the extended data pointer DPX Figure 3 8 The four bytes of DPX DPL DPH DPXL and DPXH are accessible as SFRs DPL and DPH comprise the 16 bit data pointer DPTR While instructions in the MCS 51 architecture always use DPTR as the dat er instructions in the MCS 251 architecture can use any word or dword register as a data DPXL the byte in location 57 specifies the region of memory 00 FF that maps into a point pointer the 64 Kbyte external data memory space in the MCS 51 architecture In other words the MOVX in struction addresses the region specified by DPXL when it moves data to and from external mem
165. 6 7 Interrupt Latency Variables External INTO gt 64K External External External Variable INT1 Jump to gea Stack Stack Stack 2 ISR 1 State 64K 1 gt 64 1 Wait State Number of 1 per 1 per States 1 2 1 bus cycle 4 8 Added NOTES 1 64K 64K means inside outside the 64 Kbyte memory region where code is executing 2 Base case fixed time is 16 states and assumes A 2 byte instruction is the first ISR byte 64K jump to ISR Internal peripheral interrupt Internal execution Internal stack 6 8 2 3 Latency Calculations Assume the use of a zero wait state external memory where current instructions the ISR and the stack are located within the same 64 Kbyte memory region compatible with memory maps for MCS 51 microcontrollers Further assume there are 3 states yet to complete in the current 21 state DIV instruction when INTO requests service Also assume INTO has made the request one state prior to the sample state as in Figure 6 12 Unlike Figure 6 12 the response time for this assumption is three state times as the current instruction completes in time for the branch to occur Latency calculations begin with the minimum fixed latency of 16 states From Table 6 7 one state is added for an INTO request from external hardware two states are added for external execu tion and four states for an external stack in the current 64 Kbyte region Finally three
166. 8 3 3 82930A REGISTER FILE 3 8 3 8 1 Byte Word and Dword Registers aont het 3 10 3 3 2 Dedicated Registers 5 ertet 3 11 3 3 2 1 Accumulator and Register emm 3 11 3 3 2 2 Extended Data Pointer 3 12 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel 3 3 2 3 Extended Stack Pointer SPX 22 000000 0 nnn nne 3 13 3 4 SPECIAL FUNCTION REGISTERS SFRS seen 9 13 CHAPTER 4 DEVICE CONFIGURATION 4 1 CONFIGURATION OVERVIEW 4020 eene nnne en nnne nennen 4 1 4 2 DEVICE CONEIGURBAT QN irent ite cette le ene 4 1 4 3 0 i ciet rt rto restet ee eee d pee E 4 2 4 4 CONFIGURING THE EXTERNAL MEMORY 4 6 4 4 1 Page Mode and Nonpage Mode PAGE 4 6 4 4 2 Configuration Bits RD1 0 sese emere eren 4 6 4 4 2 1 RD1 0 00 18 External Address Bits esee 4 7 4 4 8 2 RD1 0 01 17 External Address Bits sse 4 7 4 4 8 8 RD1 0 10 16 External Address Bits sse 4 9 4 4 24 RD1 0 11 Compatible with MCS 51 Microcontrollers 4 10 4 4
167. 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Table A 24 Summary of Move Instructions intel Move 2 Move with Sign Extension Move with Zero Extension Move Code Byte Move to External Mem Move from External Mem MOV lt dest gt lt src gt MOVS lt dest gt lt src gt MOVZ lt dest gt lt sre gt MOVC lt dest gt lt src gt MOVX lt dest gt lt srce gt MOVX lt dest gt lt sre gt destination lt src destination lt src with sign extend destination lt src with zero extend A lt code byte external mem lt A A lt source in external mem Binary Mode Source Mode Mnemonic lt dest gt lt src gt Notes Bytes States Bytes States A Rn Reg to acc 1 1 2 2 A dir8 Dir byte to acc 2 1 3 2 1 3 A Ri Indir RAM to acc 1 2 2 3 Immediate data to acc 2 1 2 1 Rn A Acc to reg 1 1 2 2 Rn dir8 Dir byte to reg 2 1 3 3 2 3 Rn data Immediate data to reg 2 1 3 2 dir8 A Acc to dir byte 2 2 3 2 2 3 dir8 Rn Reg to dir byte 2 2 3 3 3 3 dir8 dir8 Dir byte to dir byte 3 3 3 3 dir8 Ri Indir RAM to dir byte 2 3 3 4 dir8 data Immediate data to dir byte 3 3 3 3 3 3 MOV Ri A Acc to indir RAM 1 3 2 4 Ri dir8 Dir byte to indir RAM 2 3 3 4 Ri data Immediate data to indir RAM 2 3 3 4 DPTR data16 Load Data Pointer with a 16 bit const 3 2 3 2 Rm
168. A MOVX Ri A A 103 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Bytes States Encoding Hex Code in Operation MOVZ WRj Rm Function Description Flags Example Variations MOVZ WRj Rm Bytes States Encoding Hex Code in Operation Binary Mode 1 4 Source Mode 1 4 1111 001i Binary Mode Encoding Source Mode A5 Encoding MOVX Ri lt Move 8 bit register to 16 bit register with zero extension Moves the contents of an 8 bit register to the low byte of a 16 bit register The upper byte of the 16 bit register is filled with zeros OV N 2 Eight bit register Rm contains 055H 01010101 and 16 bit register WRj contains OFFFFH 11111111 11111111B The instruction MOVZ WRj Rm moves the contents of register Rm 01010101B to register WRj At the end of the operation WRj contains 00000000 01010101 Binary Mode Source Mode 3 2 2 1 0000 1010 tttt 5555 Binary Mode A5 Encoding Source Mode Encoding MOVZ WRj 7 0 lt Rm 7 0 WRj 15 8 0 MUL lt dest gt lt src gt Function A 104 Multiply intel INSTRUCTION SET REFERENCE Description _ Multiplies the unsigned integer in the source register with the unsigned integer in the destination register Only register addressin
169. A Compare Capture Module 2 High Byte S FCH Compare Capture Module 3 High Byte S FDH Compare Capture Module 4 High Byte S FEH intel Device Configuration 4 DEVICE CONFIGURATION 829304 provides design flexibility by configuring certain operating features during the de vice reset These features fall into the following categories external memory interface page mode address bits wait states range for RD WR and PSEN source mode binary mode opcodes selection of bytes stored on the stack by an interrupt You can specify a 16 bit 17 bit or 18 bit external addresses bus 256 Kbyte external address space Wait state selection provides 0 1 2 or 3 wait states This chapter provides a detailed discussion of device configuration It describes the configuration bytes and provides information to aid you in selecting a suitable configuration for your applica tion It discusses the choices involved in configuring the external memory interface and shows how the internal memory space maps into external memory See Configuring the External Mem ory Interface Opcode Configurations SRC discusses the choice of source mode or binary mode opcode arrangements 41 CONFIGURATION OVERVIEW The configuration of the 82930A is established by the reset routine based on information stored in configuration bytes The 82930A stores configuration information in two user
170. A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel EPCONx Address See Table 7 15 xz 0 3 Reset State See Table 7 15 7 0 STL RX STL TX CTL EP RXSPM RX IE RXEP E TX OE TXEP E Bit Bit Function 7 STL RX Stall Receive Endpoint Set this bit to stall the receive endpoint Clear this bit only when the host has intervened through commands sent down endpoint 0 The state of this bit is sampled on a valid OUT token 6 STL TX Stall transmit endpoint This bit is used to stall the transmit endpoint and it should only be cleared when the host has intervened through commands sent down endpoint 0 The state of this bit is sampled on a valid IN token 5 CTL EP Control endpoint Set this bit to configure the endpoint as control endpoint The state of this bit is sampled on a valid OUT token 4 RXSPM Receive single packet mode This bit is used to configure the receive endpoint for single data packet operation When enabled only a single data packet is allowed to reside in the RXFIFO The state of this bit is sampled on a valid OUT token 3 RX IE Receive input enable This bit is used to enable data from the USB to be written into RXFIFO If disabled the endpoint will not write the received data into RXFIFO and at the end of reception it returns a NACK handshake if STL_RX bit is not set The state of this bit is sampled on a valid OUT token 2 RXEP E
171. A11 P2 3 5 H A12 P2 4 4 A13 P2 5 3 F A14 P2 6 2 A15 P2 7 65 PSEN 64 Reserved 63 Reserved 62 Reserved 61 Reserved AD7 7 amp Reserved AD6 P0 6 amp Reserved AD5 P0 5 Reserved AD4 P0 4 5 Vss AD3 P0 3 5 AD2 P0 2 4 Vp AD1 P0 1 E 82930A ADO P0 0 4 Vss amp Vss Reserved View of component as Reserved P3 0 20 SOF P3 1 TXD 6421 mounted on PC board Reserved P3 2 INTO 22 Reserved P3 3 INT1 23 Reserved P3 4 TO 124 Reserved P3 5 T1 25 Reserved P3 6 WR E 26 Reserved A16 P3 7 RD 27 P1 0 T2 Q 28 P1 1 T2EX 29 P1 2 ECI 30 P1 3 CEX0 31 P1 4 CEX1 32 P1 5 CEX2 33 1 6 34 A17 P1 7 35 RESET 41 PLLSEL1 42 PLLSEL2 43 4232 01 Figure B 1 82930A 68 lead PLCC Package B 1 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Table B 1 Signals Arranged by Functional Categories In tel Address amp Data Input Output USB Name Lead Name Lead Name Lead ADO P0 0 17 P1 0 T2 28 PLLSEL1 42 AD1 P0 1 16 1 1 2 29 PLLSEL2 43 AD2 P0 2 15 1 2 30 SOF 50 AD3 P0 3 14 P1 3 CEXO 31 ECAP 53 AD4 P0 4 13 P1 4 CEX1 32 VM 54 AD5 P0 5 12 P1 5 CEX2 33 VP 55 AD6 P0 6 11 1 6 34 AD7 P0 7 1 0 P1 7 CEX4 A1 7 35 Processor
172. ANUAL intel Address Control Read Internal Latch Internal Bus Write to Latch Read Pin 2240 01 Figure 9 3 Port 2 Structure When port 0 and port 2 are used for an external memory cycle an internal control signal switches the output driver input from the latch output to the internal address data line External Memory Access on page 9 6 discusses the operation of port 0 and port 2 as the external address data bus NOTE Port 0 and port 2 are precluded from use as general purpose I O ports when used as address data bus drivers Port 0 internal pullups assist the logic one output for memory bus cycles only Except for these bus cycles the pullup FET is off other port 0 outputs are open drain 9 5 READ MODIFY WRITE INSTRUCTIONS Some instructions read the latch data rather than the pin data The latch based instructions read the data modify the data and then rewrite the latch These are called read modify write in structions Below is a complete list of these special instructions When the destination operand is a port or a port bit these instructions read the latch rather than the pin ANL logical AND e g ANL Pl A ORL logical OR e g ORL P2 A 9 4 intel INPUT OUTPUT PORTS XRL logical EX OR e g XRL P3 A JBC jump if bit 1 and clear bit e g JBC P1 1 LABEL CPL complement bit e g CPL P3 0 INC increment e g INC P2 DEC decrement e g DEC P2
173. Baud Rates Modes 1 3 12 6 3 2 Selecting Timer 1 as the Baud Rate Generator 12 6 8 3 Timer 2 Generated Baud Rates Modes 1 3 12 6 3 4 Selecting Timer 2 as the Baud Rate Generator CHAPTER 13 MINIMUM HARDWARE SETUP 131 MINIMUM HARDWARE 202 220200200 0000 00 0000 132 ELECTRICAL ENVIRONMENT 20 00 0000 0 0 000000000000 13 2 1 Power and Ground enne nennen nnn 19 2 2 Un sed Pifis iR eie eo ipei 13 2 3 Noise Considerations essere 13 31 On chip Oscillator Crystal 13 3 2 On chip Oscillator Ceramic Resonator 139 3 3 External C OOk rne eee eee eis 13 4 RESET CHAPTER 14 SPECIAL OPERATING MODES 14 4 GENERAL 18 1 18 2 pim EEA 13 2 13 2 13 2 13 2 13 2 13 3 PEE 13 4 18 5 13 4 1 Externally Initiated Resets was FM At iiem e 13 5 134 2 WDT Initiated Resets adh el ae Roe ER 13 4 8 Reset Operation 13 4 4 e tu tnde e M MM 13 5 MEE 13 6 EA 13 6 142 POWER CONTROL REGISTER TO P DATUR 14 2 1 Serial Control Bits
174. CAP4L Enter a 16 bit initial value in the timer counter CH CL or use the reset value OOOOH The difference between these values multiplied by the PCA input pulse rate determines the running time to expiration Set the timer counter run control bit CR in the CCON register to start the PCA WDT The PCA WDT generates a reset signal each time a match occurs To hold off a PCA WDT reset the user has three options periodically change the comparison value in CCAPAH CCAPAL so a match never occurs periodically change the PCA timer counter value so a match never occurs disable the module 4 reset output signal by clearing the WDTE bit before a match occurs then later re enable it The first two options are more reliable because the WDT is not disabled as in the third option second option is not recommended if other PCA modules are in use since the five modules share a common time base Thus in most applications the first option is the best one 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Compare Capture PCA Timer Counter Module CH CL CCAP4L 8 Bits 8 Bits 8 EU 8 Bits Count PCA WDT Reset CCAPM4 Mode Register Reset Write to CCAPAL X Don t Care Write to CCAP4H A4165 01 Figure 11 4 PCA Watchdog Timer Mode 11 3 6 Pulse Width Modulation Mode The five PCA comparator capture modules can be independently progr
175. CCF4 0 PCA Module Compare Capture Flags Set by hardware when a match or capture occurs This generates a PCA interrupt request if the ECCFx interrupt enable bit in the corresponding register is set Must be cleared by software Figure 11 8 CCON PCA Timer Counter Control Register 11 14 PROGRAMMABLE COUNTER ARRAY Table 11 3 PCA Module Modes ECOMx CAPPx CAPNx MATx TOGx PWMx ECCFx Module Mode 0 0 0 0 0 0 0 No operation X 1 0 0 0 0 X 16 bit capture on positive edge trigger at CEXx X 0 1 0 0 0 X 16 bit capture on negative edge trigger at CEXx X 1 1 0 0 0 X 16 bit capture on positive or negative edge trigger at CEXx 1 0 0 1 0 X Compare software timer 1 0 0 1 1 X Compare high speed output 1 0 0 0 0 1 0 Compare 8 bit PWM 1 0 0 1 X 0 X Compare PCA WDT CCAPM4 only Note 3 NOTES 1 This table shows the CCAPMx register bit combinations for selecting the operating modes of the PCA compare capture modules Other bit combinations are invalid See Figure 11 9 for bit definitions 2 X 20 4 X Dont 3 For PCA WDT mode also set the WDTE bit in the CMOD register to enable the reset output signal 11 15 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel CCAPMx x 0 4 Address S DAH CCAPM2 S DCH S DDH CCAPM4 S DEH Reset State X000 0000B
176. E Some programs written for MCS 51 microcontrollers use RETI instead of RET to return from a subroutine that is called by ACALL or LCALL i e not an interrupt service routine ISR In the 82930 this causes a compatibility problem if INTR 1 in configuration byte CONFIGI In this case the CPU pushes four bytes the three byte PC and PSWI onto the stack when the routine is called and pops the same four bytes when the RETI is executed In contrast RET pushes and pops only the lower two bytes of the PC To maintain compatibility configure the 82930A with INTR 0 With the exception of TRAP the start addresses of consecutive interrupt service routines are eight bytes apart If consecutive interrupts are used and for example or and 12 1 the first interrupt routine if more than seven bytes long must execute a jump to some other memory location This prevents overlap of the start address of the following interrupt routine 6 19 intel 7 Universal Serial Bus intel CHAPTER 7 UNIVERSAL SERIAL BUS 7 1 USBFIFOS The 82930A has eight FIFOS four transmit FIFOs TXFIFOx x 0 3 and four receive FIFOs RXFIFOx x 0 3 A transmit FIFO TXFIFOXx is written by the 82930A and then read by the SIE Interface Unit SIU for transmission A receive FIFO RXFIFOx is written by the SIU fol lowing reception and then read by the 82930A The FIFO pair for endpoint 1 has a capacity of 256 bytes each FIFO The FIFOs f
177. EN PO A17 A16 P2 A17 A16 A15 8 A4277 01 Figure 15 8 External Bus Cycle Code Fetch with One RD PSEN Wait State Nonpage Mode State 1 State 2 State 3 State 4 XTAL ALE WR PO A17 A16 P2 A17 A16 A15 8 A4278 01 Figure 15 9 External Bus Cycle Data Write with One WR Wait State Nonpage Mode 15 8 intel EXTERNAL MEMORY INTERFACE 15 3 2 Extending ALE Figure 15 10 shows the nonpage mode code fetch external bus cycle with ALE extended The wait state extends the bus cycle from two states to three For read and write external bus cycles the extended ALE extends the bus cycle from three states to four State 1 State 2 State 3 XTAL ALE RD PSEN PO A17 A16 P2 A4279 01 Figure 15 10 External Bus Cycle Code Fetch with One ALE Wait State Nonpage Mode 15 4 CONFIGURATION BYTE BUS CYCLES If EA 0 82930A devices obtain configuration information from a configuration array in ex ternal memory This section describes the bus cycles executed by the reset routine to fetch user configuration bytes from external memory Configuration bytes are discussed in Chapter 4 De vice Configuration To determine whether the external memory is set up for page mode or nonpage mode operation the 82930A accesses external memory using internal address FF FFF8H UCONFIGO See states 1 4 in Figure 15 11 If the external memory is set up fo
178. ER S MANUAL Table A 27 Summary of Control Instructions Continued intel Binary Mode Source Mode Mnemonic dest src Notes Bytes States 2 Bytes States 2 JSLE rel Jump if less than or equal signed 3 2 5 2 1 4 JSG rel Jump if greater than signed 3 2 5 2 1 4 JSGE rel Jump if greater than or equal 3 2 5 2 1 4 signed Compare dir byte to acc and jump 3 2 5 3 2 5 if not equal A data rel Compare immediate to acc and 3 2 5 3 2 5 jump if not equal CJNE Rn data rel Compare immediate to reg and 3 2 5 4 3 6 jump if not equal Ri data rel Compare immediate to indir and 3 3 6 4 4 7 jump if not equal Rn rel Decrement reg and jump if not 2 2 5 3 3 6 zero DJNZ gt dir8 rel Decrement dir byte and jump if not 3 3 6 3 3 6 zero TRAP Jump to the trap interrupt vector 2 10 1 9 NOP 1 1 1 1 NOTES 1 shaded cell denotes an instruction in the MCS 51 architecture 2 For conditional jumps times are given as not taken taken A 26 intel INSTRUCTION SET REFERENCE 4 INSTRUCTION DESCRIPTIONS This section describes each instruction in the 82930A architecture See the note on page A 12 re garding execution times Table A 28 defines the symbols v 1 0 2 used to indicate the effect of the instruction on the flags in the PSW and PSW1 registers For a conditional jump instruction indi
179. ERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel RXSTATx Address See Table 7 17 x 0 3 Reset State See Table 7 17 7 0 R SEQ R SETUP R VOID R ERR R_ACK Bit Bit 3 Number Mnemonic Function 7 R_SEQ Receiver s current sequence bit This bit will be toggled on a ACK ed reception 6 R SETUP Received Setup Token This bit is set by hardware and must be cleared by software 53 Reserved Values read from these bits are indeterminate Write zeros to these bits 2 R VOID A time out condition has occurred in response to a valid OUT token No data is received into RXFIFO Receive time out is closely associated with NACK STALL handshake returned by function at the end of reception It can be one of the following 1 RXFIFO cannot be written 2 STL_RX is set This bit does not affect RXD bit Updated in respond to a valid OUT token 1 R ERR An error condition has occurred with the reception Complete or partial data has been written into RXFIFO No handshake is returned It can be one of the following condition 1 Data failed CRC check 2 RXFIFO goes into overrun or underrun condition while receiving Corresponding RXD bit is set when active Updated together with R_ACK bit at the end of data reception mutually exclusive with R_ACK 0 R_ACK Data is received completely into RXFIFO and ACK handshake is returned Corresponding RXD bit is set when active Updated together w
180. ESCRIPTION The programmable counter array PCA consists of a 16 bit timer counter Pand five 16 bit com pare capture modules The timer counter serves as a common time base and event counter for the compare capture modules distributing the current count to the modules by means of a 16 bit bus A special function register SFR pair CH CL maintains the count in the timer counter while five SFR pairs CCAPxH CCAPAL store values for the modules see Figure 11 1 Additional SFRs provide control and mode select functions as follows The PCA timer counter mode register CMOD and the PCA timer counter control register CCON control the operation of the timer counter See Figures 11 7 and 11 8 Five PCA module mode registers CCAPMx specify the operating modes of the compare capture modules See Figure 11 9 For a list of SFRs associated with the PCA see Table 11 1 For an SFR address map see Table 3 4 Port 1 provides external I O for the PCA on a shared basis with other functions Table 11 2 identifies the port pins associated with the timer counter and compare capture modules When not used for PCA I O these pins can be used for standard I O functions The operating modes of the five compare capture modules determine the functions performed by the PCA Each module can be independently programmed to provide input capture output com pare or pulse width modulation Module 4 only also has a watchdog timer mode The timer counter
181. EX DJ EXEN2 A4116 02 Figure 10 10 Timer 2 Clock Out Mode Table 10 3 Timer 2 Modes of Operation Mode RCLK OR TCLK CP RL2 2 2 T2CON T2MOD Auto reload Mode 0 0 0 Capture Mode 0 1 0 Baud Rate Generator Mode 1 X X Programmable Clock Out X 0 1 10 15 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel T2MOD Address S C9H Reset State XX00B 7 0 T20E DCEN Function 7 2 Reserved Values read from these bits are indeterminate Write zeros to these bits 1 T20E Timer 2 Output Enable Bit In the timer 2 clock out mode connects the programmable clock output to external pin T2 0 DCEN Down Count Enable Bit Configures timer 2 as an up down counter Figure 10 11 T2MOD Timer 2 Mode Control Register 10 7 WATCHDOG TIMER peripheral section of the 82930A contains a dedicated hardware watchdog timer WDT that automatically resets the chip if it is allowed to time out The WDT provides a means of recovering from routines that do not complete successfully due to software malfunctions The WDT de scribed in this section is not associated with the PCA watchdog timer which is implemented in software 10 7 1 Description The WDT is a 14 bit counter that counts peripheral cycles i e the system clock divided by twelve
182. External Bus Cycle Code Fetch Page Mode State 1 State 2 State 3 XTAL ALE RD PSEN 17 16 0 2 4275 01 Figure 15 6 External Bus Cycle Data Read Page Mode 15 6 intel EXTERNAL MEMORY INTERFACE State 1 State 2 State 3 XTAL ALE WR P2 A4276 01 Figure 15 7 External Bus Cycle Data Write Page Mode 15 3 EXTERNAL BUS CYCLES WITH WAIT STATES The 82930A can be configured to add wait states to the external bus cycles by extending the RD WR PSEN pulses or by extending the ALE pulse Configuration bites WSA1 0 and WSB1 0 specify 0 1 2 or 3 wait states for RD WR PSEN The XALE configuration bit specifies 0 or 1 wait state for ALE See Wait State Configuration Bits in Chapter 4 Device Configuration You can also configure the chip to use both types of wait states Accesses to on chip code and data memory always use zero wait states 15 3 1 Extending RD WR PSEN Figure 15 8 shows the nonpage mode code fetch bus cycle with one RD PSEN wait state The wait state extends the bus cycle to three states Figure 15 9 shows the nonpage mode data write bus cycle with one WR wait state The wait state extends the bus cycle to four states The wave forms in Figure 15 9 also apply to the nonpage mode data read external bus cycle if RD PSEN is substituted for WR 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel XTAL ALE RD PS
183. F FF 0033 002BH 0023H 001BH 0013H 000BH 0003H t The 82930A also contains a TRAP interrupt not cleared by hardware with a vector address of FF007BH For a discussion of TRAP and other interrupt sources see section 6 2 82930A Interrupt Sources Additional interrupts specific to USB operation appear in Table 6 4 Table 6 4 USB Interrupt Sources Interrupt Source E Vector Address USB EPO Transmit Receive Done RXDO No FF 0043H USB EP1 Transmit Receive Done TXD1 RXD1 No FF 004BH USB EP2 Transmit Receive Done TXD2 RXD2 No FF 0053H USB EP3 Transmit Receive Done TXD3 RXD3 No FF 005BH 6 4 intel INTERRUPTS 6 2 2 Timer Interrupts Two timer interrupt request bits and see TCON register Figure 10 6 are set by timer overflow the exception is Timer 0 in Mode 3 see Figure 10 4 When a timer interrupt is gener ated the bit is cleared by an on chip hardware vector to an interrupt service routine Timer inter are enabled by bits ETO and ET2 in the register see Figure 6 3 Timer 2 interrupts are generated by a logical OR of bits TF2 and EXE2 in register T2CON see Figure 10 12 Neither flag is cleared by a hardware vector to a service routine In fact the inter rupt service routine must determine if TF2 or EXF2 generated the interrupt and then clear the bit Timer 2 interrupt is en
184. H and contain 01H 23H and 49H respectively After executing the instruction ERET the stack pointer contains 08H and program execution continues at location 012349H Binary Mode Source Mode Bytes 3 2 States 10 9 Encoding 1010 1010 A 63 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Hex Code in Operation INC Byte Function Description Flags Example Variations INCA Bytes States Encoding Hex Code in Operation INC dir8 Bytes A 64 Binary Mode A5 Encoding Source Mode Encoding ERET 15 8 lt SP SP SP 1 PC 7 0 SP SP lt SP 1 PC 23 16 SP SP SP 1 Increment Increments the specified byte variable by 1 An original value of FFH overflows to 00H Three addressing modes are allowed for 8 bit operands register direct or register indirect Note When this instruction is used to modify an output port the value used as the original port data is read from the output data latch not the input pins OV N 2 Register 0 contains 7EH 011111110 and RAM locations 7EH and 7FH contain OFFH and 40H respectively After executing the instruction sequence INC RO INC RO INC RO register 0 contains 7FH and on chip RAM locations 7EH and 7FH contain 00H and 41H respectively Binary Mode Source Mode 1 1 1 1
185. H or 00001101B register 0 contains 17 11H or 00010001 since 251 13 X 18 17 and the CY and OV bits are clear see Flags The CY flag is cleared The N flag is set if the MSB of the quotient is set The Z flag is set if the quotient is zero OV N 2 0 V Exception if src contains 00H the values returned in both operands are undefined the CY flag is cleared OV flag is set and the rest of the flags are undefined OV N 2 0 1 A 57 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL DIV Rmd Rms Binary Mode Source Mode Bytes 3 2 States 11 10 Encoding 1000 1100 ssss ssss Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation DIV 8 bit operands lt remainder Rms if dest md 0 2 4 14 Rmd 1 lt quotient Rms Rmd 1 remainder Rmd Rms if dest md 1 3 5 15 quotient Rmd Rms DIV WRjd WRjs Binary Mode Source Mode Bytes 3 2 States 22 21 Encoding 1000 1101 tttt TTTT Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation DIV 16 bit operands WRjd remainder WRjd WRjd 2 lt quotient WRjd WRjs if dest jd 0 4 8 28 WRjs WRjd 2 lt remainder WRid WRis if dest jd 2 6 10 30 WRjd lt quotient
186. IAL BUS Register Address Reset Value RXCONO D4H 0XX00000B RXCON 1 S D5H 0XX00000B RXCON2 S D6H 0XX00000B RXCONS S D7H 0XX00000B 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel RXFLGx Address See Table 7 14 0 3 Reset State See Table 7 14 7 0 FIF1 FIFO EMPTY FULL URF OVF Function 7 6 FIF1 0 FIFO Index Flags These read only flags indicate which data sets are present in the RXFIFO see Table 7 9 The FIF bits are updated after each write to RXCNTx to reflect the addition of a data set Likewise the FIF bits are updated after the FFRC bit is set The next state table for FIF bits is shown below for operation in dual set mode FIF 1 0 Operation Flag Next FIF 1 0 Next Flag 00 Wr RXCNT X 01 Unchanged 01 Wr RXCNT X 11 Unchanged 10 Wr RXCNT X 11 Unchanged 00 Set FFRC X 00 Unchanged 01 Set FFRC X 00 Unchanged 11 Set FFRC X 10 01 Unchanged 10 Set FFRC X 00 Unchanged XX Rev WP X Unchanged Unchanged XX Adv WM X Unchanged Unchanged When the RXFIFO is programmed to operate in single set mode valid FIF states are 00 and 01 only 5 4 Reserved Values read from these bits are indeterminate Write zeros to these bits 3 EMPTY RXFIFO Empty Flag Hardware sets this bit when the write pointer is at the same location as the read pointer Hardware clears the bit when this condition no longer holds Software can read and writ
187. INC lt dest gt lt src gt dest opnd lt dest opnd src opnd Decrement DEC byte byte byte 1 Decrement DEC lt dest gt lt sre gt dest opnd dest opnd src opnd Binary Mode Source Mode Mnemonic lt dest gt lt src gt Notes Bytes States Bytes States INC DPTR Data pointer 1 1 1 1 NOTES 1 Ashaded cell denotes an instruction in the MCS 51 architecture 2 If this instruction addresses an I O port Px x 0 3 add 2 to the number of states Table A 22 Summary of Multiply Divide and Decimal adjust Instructions Multiply MUL lt reg1 reg2 gt 2 MUL AB B A AxB Divide DIV lt reg1 gt lt reg2 gt 2 DIV AB A Quotient B Remainder Decimal adjust ACC DAA 2 for Addition BCD Binary Mode Source Mode Mnemonic dest src Notes Bytes States Bytes States AB Multiply A and B 1 5 1 5 MUL Rmd Rms Multiply byte reg and byte reg 3 6 2 5 WRjd WRjs Multiply word reg and word reg 3 12 2 11 AB Divide A by B 1 10 1 10 DIV Rmd Rms Divide byte reg by byte reg 3 11 2 10 WRjd WRjs Divide word reg by word reg 3 21 2 20 DA A Decimal adjust acc 1 1 1 1 NOTES 1 A shaded cell denotes an instruction in the MCS 51 architecture 2 See section 4 Instruction Descriptions 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Table A 23 Summary of Logical Instructions
188. ING Output buffers of port 1 port 2 and port 3 can each sink 1 6 mA at logic zero see Vo specifica tions in the 82930A data sheet These port pins can be driven by open collector and open drain devices Logic zero to one transitions occur slowly as limited current pulls the pin to a logic one condition Figure 9 4 on page 9 6 A logic zero input turns off pFET 3 This leaves only pFET 2 weakly in support of the transition In external bus mode port 0 output buffers each sink 3 2 mA at logic zero see Vo in the 82930A data sheet However the port 0 pins require external pullups to drive external gate inputs See the latest revision of the 82930A datasheet for complete electrical design information External circuits must be designed to limit current requirements to these conditions 9 8 EXTERNAL MEMORY ACCESS The external bus structure is different for page mode and nonpage mode In nonpage mode used by MCS 51 microcontrollers port 2 outputs the upper address byte the lower address byte and the data are multiplexed on port 0 In page mode the upper address byte and the data are multi plexed on port 2 while port 0 outputs the lower address byte The 82930A CPU writes FFH to the PO register for all external memory bus cycles This over writes previous information in PO In contrast the P2 register is unmodified for external bus cy cles When address bits or data bits are not on the port 2 pins the bit values in P2 appear on the
189. IONS FOR A START OF FRAME SOF TOKEN 8 33 CHAPTER 9 INPUT OUTPUT PORTS 9 1 INPUT OUTPUT PORT 2 9 1 9 2 V O CONFIGURATIONS 9 1 9 3 PORT AND PORT iit er 9 2 9 4 PORT 2 tite rea trenta led loda 9 2 9 5 READ MODIFY WRITE 9 4 9 6 QUASI BIDIRECTIONAL PORT 00519 5 9 7 PORT LOADING es EE s 9 8 EXTERNAL MEMORY ACCESS ieiuna 9 6 CHAPTER 10 TIMER COUNTERS AND WATCHDOG TIMER 10 1 emnes 10 1 10 2 TIMER COUNTER 10 1 10 3 1 0 13 bit Timer IE 10 4 10 3 2 Mode 1 16 bit Timer 8 10 5 10 3 3 Mode 2 8 bit Timer With Auto reload seem 10 5 10 3 4 Mode 3 Two 8 bit Timers seemed 0 5 pP vi intel CONTENTS 10 4 1 Mode O 18 bit Timer entera n e se ee terti ee 10 9 10 4 2 Mode 1 16 bit eren nnne enne nn e 10 9 10 4 8 Mode 2 8 bit Timer with Auto reload seem 10 9 10 4 4 Mode 3 Halt nc ee DERE 10 9 10 5 0 1 APPLICATIONG essen nennen mener
190. IU to the FIFO and reads of the FIFO by the 82930A After a reset the FIFO is empty upper right 007 The first write by the SIU fills data set 0 upper left 01 If the 82930A now reads the FIFO and the transmission is good software sets the FFRC bit to indicate that the FIFO read is complete and the FIFO returns to the 00 state The diagram shows the other possible states of the FIFO and the transitions between them Note that the case of both sets full 11 actually represents two states which differ in the order of the data sets The write transition from 01 to 11 places data set 1 after data set 0 in the FIFO whereas the write transition from 10 to 11 places data set 0 after data set 1 in the FIFO In Figure 7 9 software manages the movement of the write marker and write pointer If you set the ARM bit the hardware automatically moves the write marker and write pointer and software does not set ADV_WM or REV_WP However for ARM 1 software must still set the FFRC bit after a read is completed Table 7 10 summarizes how the actions following a reception depend on the ISO bit the ARM bit and the handshake issued by the 82930A This bit pair is shorthand for FIF1 0 00 similarly 01 is shorthand for FIF1 0 01 etc 7 13 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Table 7 10 Truth Table for RXFIFO Management ISO ARM R ERR R ACK RXCONx 3 RXCONx 2 RXSTATx 1 RXSTATx 0 Action at End o
191. In the first three of these the compare capture module continuously compares the 16 bit PCA timer counter value with the 16 bit value pre loaded into the module s CCAPxH CCAPXxL register pair In the PWM mode the module continuously compares the value in the low byte PCA timer counter register CL with an 8 bit value in the CCAPxL module register Comparisons are made three times per peripheral intel PROGRAMMABLE COUNTER ARRAY cycle to match the fastest PCA timer counter clocking rate Fosc 4 For a description of periph eral cycle timing see section 2 3 2 Clock and Reset Unit Setting the bit in module s mode register CCAPMx selects the compare function for that module Figure 11 9 To use the modules in the compare modes observe the following gen eral procedure 1 Select the module s mode of operation Select the input signal for the PCA timer counter Load the comparison value into the module s compare capture register pair Set the PCA timer counter run control bit Qn 9 After a match causes an interrupt clear the module s compare capture flag 11 3 3 16 bit Software Timer Mode To program a compare capture module for the 16 bit software timer mode Figure 11 3 set the and bits in the module s CCAPMXx register Table 11 3 lists the bit combinations for selecting module modes A match between the timer counter and the compare capture registers CCAPxH CCAPxL s
192. L BUS MICROCONTROLLER USER S MANUAL intel Bytes States Encoding Hex Code in Operation DEC byte Function Description Flags Example Variations A 54 BCD variables can be incremented or decremented by adding 01H or 99H If the accumulator contains 30H representing the digits of 30 decimal then the instruction sequence ADD A 99H DAA leaves the CY flag set and 29H in the accumulator since 30 99 129 The low byte of the sum can be interpreted to mean 30 1 29 Binary Mode Source Mode 1 1 1 1 1101 0100 Binary Mode Encoding Source Mode Encoding DA Contents of accumulator are BCD IF A 3 0 gt 9 V 1 THEN A 3 0 A 3 0 6 AND IF A 7 4 gt 9 V 1 THEN 7 4 A 7 4 6 Decrement Decrements the specified byte variable by 1 An original value of 00H underflows to OFFH Four operands addressing modes are allowed accumulator register direct or register indirect Note When this instruction is used to modify an output port the value used as the original port data is read from the output data latch not the input pins OV N 2 Register 0 contains 7FH 01111111 On chip RAM locations 7EH 7FH contain 00H and 40H respectively After executing the instruction sequence DEC RO DEC RO DEC RO register 0 contains 7EH and on chip RAM locations 7EH and 7FH are s
193. L intel OVF 1 TXFLGx 0 Set CLR Clear TXCONx 7 error TXFIFO FIF1 0 4 11 TXFIFO TXFLGx 7 6 D 12 TXFLGx 0 Write byte count RETI 4190 01 Figure 8 5 Transmit Request ISR Details Part 2 8 6 intel USB OPERATING MODES 8 2 3 SIU Transmit Operations This section describes the SIU transmit operations shown on the right side of Figure 8 2 8 2 3 1 SIU Transmit Non isochronous Data Figure 8 6 summarizes the flow of SIU operations for transmitting non isochronous data The SIU hardware transmits the data packet and then responds to the resulting handshake from the host For a good transmission ACK reply from the host it toggles the sequence bit and if ARM 1 the FIFO hardware automatically prepares the read marker and read pointer for transmission of the next data packet For a bad transmission non ACK reply from the host the SIU does not toggle the SEQ bit and if ARM 1 the FIFO hardware automatically prepares the read marker and read pointer for retransmission of the same data packet For either reply the SIU generates a transmit done interrupt TXD which initiates the second firmware routine an ISR This ISR checks the transmission status and if ARM 0 it adjusts the FIFO read marker and read pointer accordingly for the next transmission Figure 8 7 and Figure 8 8 show details of the flow 8 7 82930A UNIVERSAL SERIAL
194. LJMP WRj Bytes States Encoding Hex Code in Operation Binary Mode Source Mode 3 2 6 5 1000 1001 ttt 0100 Binary Mode Encoding Source Mode Encoding LJMP PC lt WR MOV lt dest gt lt src gt Function Description Flags Example A 82 Move byte variable Copies the byte variable specified by the second operand into the location specified by the first operand The source byte is not affected This is by far the most flexible operation Twenty four combinations of source and destination addressing modes are allowed OV N 2 On chip RAM location 30H contains 40H RAM location 40H contains 10H and input port 1 contains 11001010B After executing the instruction sequence MOV MOV MOV MOV MOV MOV R0 430H RO lt 30H AGRO A lt 40H R1 lt 40H B GR1 B 10H QR1 P1 40H lt 2 1 P2 register 0 contains 30H the accumulator and register 1 contain 40H register B contains 10H and on chip RAM location 40H and output port 2 contain OCAH 11001010B INSTRUCTION SET REFERENCE intel Variations MOV A data Binary Mode Source Mode Bytes 2 2 States 1 1 Encoding 0111 0100 immed data Hex Code Binary Mode Encoding Source Mode Encoding Operation MOV lt data MOV dir8 data Bina
195. MOV lt dest bit gt lt src bit gt Function Description Flags Example Variations MOV bit51 CY Bytes States Encoding Hex Code in Operation MOV CY bit51 Bytes Move bit data Copies the Boolean variable specified by the second operand into the location specified by the first operand One of the operands must be the CY flag the other may be any directly addressable bit Does not affect any other register CY AC V OV N Z The CY flag is set input Port 3 contains 11000101B and output Port 1 contains 35H 00110101B After executing the instruction sequence MOV P1 3 CY MOV CY P3 3 MOV P1 2 CY the CY flag is clear and Port 1 contains 39H 00111001 Binary Mode Source Mode 2 2 2t 2t tlf this instruction addresses a port Px x 0 3 add 2 states 1001 0010 bit addr Binary Mode Encoding Source Mode Encoding MOV 6151 lt CY Binary Mode Source Mode 2 2 A 97 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel States 11 11 tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 1010 0010 bit addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation MOV CY lt bit51 MOV bit CY Binary Mode Source Mode Bytes 4 3 States 41 3t tlf this instruction addresses
196. MOVC A lt DPTR A 100 intel INSTRUCTION SET REFERENCE MOVH DRk data16 Function Description Flags Example Variations Move immediate 16 bit data to the high word of a dword double word register Moves 16 bit immediate data to the high word of a dword 32 bit register The low word of the dword register is unchanged OV N 2 The dword register DRk contains 5566 7788H After the instruction MOVH DRk 1122H executes DRk contains 1122 7788H MOVH DRk data16 Binary Mode Source Mode Bytes 5 4 States 3 2 Encoding 0111 1010 uuuu 1100 data hi data low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOVH DRk 31 16 data16 MOVS WRj Rm Function Move 8 bit register to 16 bit register with sign extension Description Moves the contents of an 8 bit register to the low byte of a 16 bit register The high byte of the 16 bit register is filled with the sign extension which is obtained from the MSB of the 8 bit source register Flags OV N 2 Eight bit register Rm contains 055H 01010101B and the 16 bit register WRj contains OFFFFH 11111111 11111111B The instruction MOVSE WRj Rm A 101 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Variations MOVS WRj Rm Bytes States Encoding Hex Code in
197. MREG are assumed to be defined in user code e Tl is bit 2 in TCON which is an SFR at location 88H Table 5 5 Bit addressable Locations Bit addressable Locations Architecture On chip RAM SFRs MCS 251 Architecture 20H 7FH All defined SFRs SFRs with addresses ending in OH or 8H 80H 88H 90H 98H F8H MCS 51 Architecture 20H 2FH 5 10 intel INSTRUCTIONS AND ADDRESSING Table 5 7 lists the addressing modes for bit instructions and Table A 26 in Appendix A summa rizes the bit instructions Bit denotes a bit that is addressed by an instruction in the MCS 251 architecture and bit51 denotes a bit that is addressed by an instruction in the MCS 51 architec ture Table 5 6 Addressing Two Sample Bits i Location ig APPS A ccu re Register Name RAMREG 5 RAMREG 5 On chip RAM Register Address 23H 5 23H 5 Bit Name RAMBIT RAMBIT Bit Address 1DH NA Register Name TCON 2 TCON 2 SFR Register Address 88 2H 5 88 2 Bit Name IT1 IT1 Bit Address 8A NA Table 5 7 Addressing Modes for Bit Instructions Architecture Variants Bit Address Memory SFR Address Comments MCS 251 Memory 20H 0 7FH 7 Architecture SFR NA All defined SFRs Memory 00H 7FH 20H 0 7FH 7 Hard SFR t defined Architecture 5 are not define bit51 SFR 80H F8H ae op ee 80 at all bit addressable
198. Mnemonic Functio 7 CLR Clear Setting this bit flushes TXFIFOx sets the EMPTY bit in TXFLGx and clears all other bits in TXFLGx After the flush hardware clears this bit Setting this bit does not affect the ATM and ISO bits 6 4 Reserved Values read from these bits are indeterminate Write zeros to these bits 3 ISO Isochronous Data Software sets this bit to indicate that TXFIFOx contains isochronous data This bit must be cleared by software The SIU uses this bit to set up the handshake protocol at the end of a transmission 2 ATM Automatic Transmit Management Setting this bit causes the read pointer and read marker to be adjusted automatically as indicated ISO Status Read Pointer Read Marker X ACK Unchanged Advanced 0 Not ACK Reversed Unchanged 1 Not ACK Unchanged Advanced to origin of next data set to origin of the data set last read When this bit is set setting REV RP or ADV RM has no effect Software can read and write this bit hardware neither clears nor sets this bit 1 ADV RM Advance Read Marker Setting this bit advances the read marker to point to the origin of next data the position of the read pointer to prepare for the next transmission Hardware clears this bit after the read marker is advanced Setting this bit is effective only when the REV RP and CLR bits are all clear 0 REV RP Reverse Read Pointer Setting this bit reverses the read pointer to
199. Mode Encoding Source Mode Encoding RRC lt A a41 7 lt lt 0 Set bit Sets the specified bit to one SETB can operate on the CY flag or any directly addressable bit No flags are affected except the CY flag for instruction with CY as the operand OV N 2 x aa The CY flag is clear and output Port 1 contains 34H 00110100B After executing the instruction sequence SETB CY SETB P1 0 the CY flag is set and output Port 1 contains 35H 00110101B intel INSTRUCTION SET REFERENCE Binary Mode Source Mode Bytes 2 2 States 2T 2t tlf this instruction addresses a port Px x 0 3 add 2 states Encoding 1101 0010 bit addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation SETB 6851 lt 1 SETB CY Binary Mode Source Mode Bytes 1 1 States 1 1 Encoding 1101 0011 Hex Code in Binary Mode Encoding Source Mode Encoding Operation SETB 1 SETB bit Binary Mode Source Mode Bytes 4 3 States 41 3t tlf this instruction addresses a port Px x 0 3 add 2 states Encoding 1010 1001 1101 0 yyy direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation SETB bit lt 1 SJMP rel Function Short jump Description Program control branches unconditionally to the specified address Th
200. Mode Bytes 4 3 States 4 3 Encoding 0101 1110 uuuu 1011 5555 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ANL Rm lt Rm A DRk ANL CY lt src bit gt Function A 40 Logical AND for bit variables intel Description Flags Example ANL CY bit51 Bytes States Encoding Hex Code in Operation ANL CY bit51 Bytes States Encoding Hex Code in Operation INSTRUCTION SET REFERENCE If the Boolean value of the source bit is a logical 0 clear the CY flag otherwise leave the CY flag in its current state A slash preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value but the source bit itself is not affected Only direct addressing is allowed for the source operand OV N A4 a 2 2 Set the CY flag if and only if P1 0 1 7 1 0 MOV 1 0 carry with input pin state ANL CY ACC 7 AND carry with accumulator bit 7 ANL CY OV AND with inverse of overflow flag Binary Mode Source Mode 2 2 11 11 tlf this instruction addresses a port Px x 0 3 add 1 state 1000 0010 bit addr Binary Mode Encoding Source Mode Encoding ANL CY lt CY A 6151 Binary Mode Source Mode 2 2 11 11 tlf this instruction addresses
201. Mode Positive 1 enables the capture function with capture triggered by a positive edge on pin CEXx 4 CAPNx Capture Mode Negative 1 enables the capture function with capture triggered by a negative edge on pin CEXx 3 MATx Match Set ECOMx and MATx to implement the software timer mode When MATx 1 a match of the PCA timer counter with the compare capture register sets the CCFx bit in the CCON register flagging an interrupt 2 TOGx Toggle Set TOGx to implement the high speed output mode When TOGx 1 a match of the PCA timer counter with the compare capture register toggles the CEXx pin 1 PWMx Pulse Width Modulation Mode PWMx 1 configures the module for operation as an 8 bit pulse width modulator with output waveform on the CEXx pin 0 Enable CCFx Interrupt Enables compare capture flag CCF x in the CCON register to generate an interrupt request C 8 intel REGISTERS CCON Address S D8H Reset State 00X0 0000B PCA Timer Counter Control Register Contains the run control bit and overflow flag for the PCA timer counter and the compare capture flags for the five PCA compare capture modules CF CR CCF4 CCF3 CCF2 CCF1 CCFO Bit Number Bit Mnemonic Function 7 CF PCA Timer Counter Overflow Flag Set by hardware when the PCA timer counter rolls over This generates an interru
202. O Data Register Endpoint x 7 0 Transmit Data Byte Bit Bit Function 7 0 TXDATx7 0 To write data to the TXFIFO the 82930A writes to this register To read data from the TXFIFO the SIU reads from this register The write pointer and read pointer are incremented automatically after a write and read respectively C 51 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel TXFLGx Address See Table 7 8 0 3 Reset State See Table 7 8 USB Transmit FIFO Flag Register Endpoint x The bits in this register provide information on the data in the FIFO 7 0 FIF1 FIFO FULL URF OVF Bit Bit Number Mnemonic Function 7 6 FIF1 0 FIFO Index Flags These read only flags indicate which data sets are present in the TXFIFO see Table 7 3 The FIF bits are updated after each write to TXCNTx to reflect the addition of a data set Likewise after the read marker is advanced because a set is no longer needed FIF1 or FIFO is cleared to indicate that the set is effectively discarded the bit is cleared whether the read marker is advanced by software setting ADV RM or automatically by hardware ATM 1 The next state table for FIF bits is shown below FIF 1 0 Operation Flag Next FIF 1 0 Next Flag 00 Wr TXCNTx X 01 Unchanged 01 Wr TXCNTx X 11 Unchanged 10 Wr TXCNTx X 11 Unchanged 11 Wr TXCNTx
203. RAM 1 4 2 5 8 bit addr dir8 Push dir byte onto stack 2 2 2 2 data Push immediate data onto stack data16 Push 16 bit immediate data onto 5 4 PUSH stack Rm Push byte reg onto stack 3 4 2 WRj Push word reg onto stack 3 6 2 DRk Push double word reg onto stack 3 10 2 Dir Pop dir byte from stack 2 3 3 2 3 3 B P Rm Pop byte reg from stack 3 2 2 WRj Pop word reg from stack 3 2 DRk Pop double word reg from stack 3 2 NOTES 1 A shaded cell denotes an instruction in the MCS 51 architecture 2 fthis instruction addresses an I O port Px x 0 3 add 2 to the number of states A 23 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Table A 26 Summary of Bit Instructions Clear Bit CLR bit bit 0 Set Bit SETB bit bit 1 Complement Bit CPL bit bit Obit AND Carry with Bit ANL CY bit CY CY A bit AND Carry with Complement of Bit ANL CY bit CY CY Obit OR Carry with Bit ORL CY bit lt CY V bit ORL Carry with Complement of Bit ORL CY bit CY lt CY V Obit Move Bit to Carry MOV CY bit CY lt bit Move Bit from Carry MOV bit CY bit CY Binary Mode Source Mode Mnemonic lt src gt lt dest gt Notes Bytes States Bytes States CY Clear carry 1 1 1 1 bit51 Clear dir bit 2 2 2 2 2 2 bit Clear dir bit 4 4 3 3 CY Set carry 1 1 1 1 SETB bit51 Set dir bit 2 2 2 2 2 2 bit Set dir bit
204. RD1 0 00 18 bit Bus External Flash and RAM 15 11 15 6 2 Example 2 RD1 0 01 17 bit Bus External Flash and RAM 15 13 15 6 3 Example 3 RD1 0 11 16 bit Bus External EPROM and RAM 15 16 15 6 3 1 Application Requiring Fast Access to the Stack 15 16 15 6 3 2 An Application Requiring Fast Access to Data 15 16 15 6 4 Example 4 RD1 0 11 16 bit Bus External EPROM and RAM 15 19 15 6 5 Example 5 RD1 0 01 17 bit Bus External Flash 15 20 APPENDIX A INSTRUCTION SET REFERENCE A 1 NOTATION FOR INSTRUCTION OPERANDS sese A 2 A 2 MAP AND SUPPORTING TABLES seen eee A 4 A 3 INSTRUCTION SET 2 00 0 0 nn 12 A 3 1 Execution Times for Instructions Accessing the Port SFRS A 12 A 3 2 Instruction Summaries GE ctr e eren Alaa A 15 A 4 INSTRUCTION DESCRIPTIONS sessi A 27 APPENDIX B SIGNAL DESCRIPTIONS APPENDIX C REGISTERS GLOSSARY INDEX intel Guide to This Manual CHAPTER 1 GUIDE TO THIS MANUAL This manual describes the 82930 a product for universal serial bus USB applications This
205. ROLLER USER S MANUAL intel P3 Address Reset State S BOH 1111 1111B Port 3 P3 is the SFR that contains data to be driven out from the port 3 pins Read modify write instructions that read port 3 read this register Other instructions that read port 3 read the port 3 pins 7 0 P3 Contents Bit Bit Number Mnemonic poneuon 7 0 P3 7 0 Port 3 Register Write data to be driven onto the port 3 pins to these bits C 24 intel REGISTERS PCON Address 5 87 Reset State 00 00008 Power Control Register Contains the power off flag POF and bits for enabling the idle and powerdown modes Also contains two general purpose flags and two bits that control serial functions the double baud rate bit and a bit that selects whether accesses to SCON 7 are to the FE bit or the SMO bit 7 0 SMOD1 SMODO POF GF1 GFO PD IDL Bit Bit Function Number Mnemonic une 7 SMOD1 Double Baud Rate Bit When set doubles the baud rate when timer 1 is used and mode 1 2 or 3 is selected in the SCON register See Baud Rates in Chapter 12 6 SMODO SCON 7 Select When set read write accesses to SCON 7 are to the FE bit When clear read write accesses to SCON 7 to the SMO bit See Figure 12 2 SCON Serial Port Control Register 5 Reserved The value read from this bit is indeterminate Write a zero to this bit 4 POF Power Of
206. Reset State X000 00008 7 0 0 6 0 5 0 4 0 3 0 2 0 1 0 0 UR Function 7 Reserved The value read from this bit is indeterminate Write a zero to this bit 6 IPLO 6 PCA Interrupt Priority Bit Low 5 IPLO 5 Timer 2 Overflow Interrupt Priority Bit Low 4 IPLO 4 Serial I O Port Interrupt Priority Bit Low 3 IPLO 3 Timer 1 Overflow Interrupt Priority Bit Low 2 IPLO 2 External Interrupt 1 Priority Bit Low 1 IPLO 1 Timer 0 Overflow Interrupt Priority Bit Low 0 IPLO O External Interrupt 0 Priority Bit Low Figure 6 7 IPLO Interrupt Priority Low Register 0 IPH1 Address S B3H Reset State 00H 7 0 IPH1 3 IPH1 2 IPH1 1 IPH1 0 eee Function 7 4 Reserved Values read from these bits are indeterminate Write zeros to these bits IPH1 3 Endpoint 3 Interrupt Priority Bit High 2 IPH1 2 Endpoint 2 Interrupt Priority Bit High 1 IPH1 1 Endpoint 1 Interrupt Priority Bit High 0 1 0 Endpoint 0 Interrupt Priority Bit High Figure 6 8 IPH1 Interrupt Priority High Register 1 6 12 intel INTERRUPTS IPL1 Address S B2H Reset State 00H 7 0 IPL1 2 IPL1 1 IPL1 0 unter eene Fuperion 7 4 Reserved Values read from these bits are indeterminate Write zeros to these bits IPL1 3 Endpoint 3 Interrupt Priority Bit Low 2 IPL1 2 Endpoint 2 Interrupt Priority Bit Low 1 IPL1 1 Endpoint 1 I
207. S 251 architecture use the prefix with SFR addresses to distinguish them from the memory space addresses 00 0000 00 01 See section 3 4 Special Function Registers SFRs for details on the SFR space 3 1 1 Compatibility with the MCS 51 Architecture The address spaces in the MCS 51 architecture are mapped into the address spaces in the MCS 251 architecture This mapping allows code written for MCS 51 microcontrollers to run on MCS 251 microcontrollers Chapter 5 Instructions and Addressing discusses the compatibility of the two instruction sets Figure 3 2 shows the address spaces for the MCS 51 architecture Internal data memory locations 00H 7FH can be addressed directly and indirectly Internal data locations 80H FFH can only be addressed indirectly Directly addressing these locations accesses the SFRs The 64 Kbyte code memory has a separate memory space Data in the code memory can be accessed only with the MOVC instruction Similarly the 64 Kbyte external data memory can be accessed only with the MOVX instruction The register file registers RO R7 comprises four switchable register banks each having 8 reg isters The 32 bytes required for the four banks occupy locations 00H 1FH in the on chip data memory Figure 3 3 shows how the address spaces in the MCS 51 architecture map into the address spaces in the MCS 251 architecture details are listed in Table 3 1 t MCS851 Microcontroller Family User s
208. SAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Start Read status registers RXSTATX SBI Identify endpoint and 5 Clear status flags RXSTATx 0 1 R ERR bit RXSTATx 1 must 1 OVF bit RXFLGx 1 Advance write marker Advance write Set ADV WM pointer RXCONx 1 Clear bit Rx CONx 7 Set REV WP Clear RXFIFO RFCONx 0 Read data set Make up zero length packet RET Note Operations in box are in this routine for ARM 0 and are executed automatically by hardware for ARM 1 A4270 01 Figure 8 24 Post receive Operations for Isochronous Data Detail 8 30 intel USB OPERATING MODES 8 4 SIU OPERATIONS FOR A SETUP TOKEN Figure 8 25 illustrates the SIU operations for a SETUP token The cycle is initiated by a valid SETUP token i e the token PID received is good The endpoint must be configured as a control endpoint to be enabled for the SETUP token Refer to the Protocol Layer section of the Uni versal Serial Bus specification for details of the SETUP token transactions and protocol 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Valid SETUP token n Endpoint enabled enabled 5 d lt lt Set R_SEQ T SEQ ready Receive data USB s data gt RXFIFO but discard n End of transfer 2 5 Write byte count register RXFIFO y overrun CRC passed 4 D
209. See section A 4 Instruction Descriptions A shaded cell denotes an instruction in the MCS 51 architecture 2 3 If this instruction addresses an I O port x 0 43 add 1 to the number of states 4 If this instruction addresses an I O port Px x 0 3 add 2 to the number of states A 18 intel INSTRUCTION SET REFERENCE Table A 23 Summary of Logical Instructions Continued Logical AND ANL lt dest gt lt src gt dest opnd dest opnd A src opnd Logical OR ORL lt dest gt lt src gt dest opnd lt dest opnd V src opnd Logical Exclusive OR XRL lt dest gt lt srce gt dest lt dest v src Clear CLRA 0 Complement CPLA Ai lt O Ai Rotate RXX A 1 Shift SXX Rm or Wj 1 SWAP A A3 0 o 7 4 Binary Mode Source Mode Mnemonic lt dest gt lt sre gt Notes Bytes States Bytes States ER Rm Shift byte reg right through the MSB 3 2 2 1 WRj Shift word reg right through the MSB 3 2 2 1 Rm Shift byte reg right 3 2 2 1 SRL y g rig WRj Shift word reg right 3 2 2 1 SWAP A Swap nibbles within the acc 1 2 1 2 NOTES 1 See section AA Instruction Descriptions 2 shaded cell denotes an instruction in the MCS 51 architecture 3 If this instruction addresses an I O port Px x 0 3 add 1 to the number of states 4 If this instruction addresses an I O port Px x 0 3 add 2 to the number of states
210. Software writes to bit SM2 to enable and disable the multiprocessor communication and automatic address recognition features This allows the serial port to differentiate between data and command frames and to recognize slave and broadcast addresses 4 REN Receiver Enable Bit To enable reception set this bit To enable transmission clear this bit 3 TB8 Transmit Bit 8 In modes 2 and 3 software writes the ninth data bit to be transmitted to TB8 Not used in modes 0 and 1 2 RB8 Receiver Bit 8 Mode 0 Not used Mode 1 5 2 clear Set or cleared by hardware to reflect the stop bit received Modes 2 and 3 5 2 set Set or cleared by hardware to reflect the ninth data bit received C 37 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel SCON select bits and the interrupt flag bits Address Reset State 98H 0000 0000B Serial Port Control Register SCON contains serial I O control and status bits including the mode Cleared by software Set by the receiver after the last data bit of a frame has been received 7 0 FE SMO SM1 SM2 REN TB8 RB8 TI RI Bit Bit Number Mnemonic Function 1 TI Transmit Interrupt Flag Bit Set by the transmitter after the last data bit is transmitted Cleared by software 0 Receive Interrupt Flag Bit C 38 intel REGISTERS SOFH Address S D3H Reset Sta
211. State 5 99 XXXX XXXXB Serial Data Buffer Writing to SBUF loads the transmit buffer of the serial I O port Reading SBUF reads the receive buffer of the serial port d 0 Data Sent Received by Serial I O Port Bit Bit Function 7 0 SBUF 7 0 C 36 intel REGISTERS SCON Address 98H Reset State 0000 0000B Serial Port Control Register SCON contains serial I O control and status bits including the mode select bits and the interrupt flag bits 7 0 FE SMO 5 SM2 REN TB8 RB8 TI RI Bit Bit Function Number Mnemonic 7 FE Framing Error Bit To select this function set the SMODO bit in the PCON register Set by hardware to indicate an invalid stop bit Cleared by software not by valid frames SMO Serial Port Mode Bit 0 To select this function clear the SMODO bit in the PCON register Software writes to bits SMO and SM1 to select the serial port operating mode Refer to the SM1 bit for the mode selections 6 SM1 Serial Port Mode Bit 1 Software writes to bits SM1 and SMO above to select the serial port operating mode SMO SM1 Mode Description Baud Rate 0 0 0 Shift register Fosc 12 0 1 1 8 bit UART Variable 1 0 2 9 bit UART Fosc 32 or Foso 64 1 1 3 9 bit UART Variable Select by programming the SMOD bit in the PCON register see section 12 6 Baud Rates 5 SM2 Serial Port Mode Bit 2
212. Sz gt 5 5 Serial amp Reset Register E Memory Interface lt gt USB eI Peripherals Microcontroller Core Clock amp Reset 4185 01 Figure 2 2 Functional Block Diagram of the 82930A 2 2 intel INTRODUCTION 21 PRODUCT OVERVIEW The 82930A can be briefly described as an 80C251SB microcontroller with an on chip USB pe ripheral and additional pinouts to provide the capabilities of a USB device The microcontroller core together with the USB provide the essential capabilities of a USB device The other periph erals of the 80 25 15 are not essential to the operation as a USB device The 82930A uses the standard instruction set of the MCS 251 architecture Clock PLL 80 2515 FIFO Data Bus Data Bus Note SIU Serial Bus Interface Unit tt SIE Serial Bus Interface Engine A4231 01 Figure 2 3 82930A USB Peripheral Interface 2 3 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel The 82930A is derived from the 80C251SB This section outlines some major features of the 80C251SB core and peripherals Core features include 256 Kbytes of external memory addressability Code compatibility with MCS 51 microcontrollers 1 Kbyte on chip data RAM The 80C251SB has the following peripherals programmable counter array PCA 5capture compare modules configurable to timer PWM Universal Asynchronous
213. TH2 TL2 in timer 2 7 0 High Low Byte of Timer 2 Reload Capture Value Bit Bit Mnemonic Function 7 0 RCAP2H 7 0 High byte of the timer 2 reload recapture register RCAP2L 7 0 Low byte of the timer 2 reload recapture register RXCNTx Address See Table 7 12 xz 0 3 Reset State See Table 7 12 Receive FIFO Byte Count Register 7 0 Byte Count 0 255 Bit Bit Number Mnemonic Function 7 0 7 0 Byte Count The number of bytes data set 0 or data set 1 When this register is accessed the byte count written read is for data set 0 or data set 1 depending on the data set index bits FIF1 0 in RXFLGx Following a read of this register the read write index is unchanged following a write the read write index is toggled After the SIU writes a data set to RXFIFOx it writes the byte count to this register The 82930A reads the byte count from this register to determine how many bytes to read from RXFIFOx C 28 intel REGISTERS RXCONx Address See Table 7 13 0 3 Reset State See Table 7 13 7 0 CLR FFRC ISO ARM ADV WM REV WP Bit Bit 2 Number Mnemonic Function 7 CLR Clear the FIFO Software sets this bit to flush the entire FIFO All flags in RXFLGx revert to their reset states EMPTY is set all other flags clear The ARM and ISO bits are not affected by this operat
214. UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Table 7 8 TXFLGx Addresses and Reset Values Register Address Reset Value TXFLGO S A2H 00XX1000B TXFLG1 S A3H 00XX1000B TXFLG2 S A4H 00XX1000B TXFLG3 S A5H 00XX1000B 7 3 RECEIVE FIFOS 7 3 1 Receive FIFO Overview The RXFIFO is a circulating FIFO with the following features support for up to two separate data sets of variable sizes a byte count register that accesses the number of bytes in the data sets flags to signal a full FIFO and an empty FIFO capability to rereceive the last data set intel Figure 7 8 illustrates a receive FIFO RXFIFOx and its associated logic can manage up to two data sets data set 0 450 and data set 1 ds1 The ability to have two data sets in the FIFO sup ports back to back receptions Read Pointer 82930 CPU Reads FIFO Write Pointer ADV WM Write Marker SIU Writes to FIFO 4259 01 Figure 7 8 Receive RXFIFOx In many ways the receive FIFO is symmetrical to the transmit FIFO The SIU writes to the FIFO location specified by the write pointer which increments by one automatically following a write The write marker points to the first byte of data written to a data set and the read pointer points 7 12 intel UNIVERSAL SERIAL BUS to the next FIFO location to be read by the 82930A The read pointer increments by one automat ically following a read
215. WRij dir8 Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 1001 1110 tttt 0101 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation SUB WRJ lt dir8 SUB 116 Source Mode Bytes 5 4 States 3 2 Encoding 1001 1110 5555 0011 direct addr direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation SUB Rm Rm dir16 SUB WhRj dir16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding 1001 1110 tttt 0111 direct addr direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation SUB WRj WRj dir16 SUB Rm OWRj Binary Mode Source Mode Bytes 4 3 States 3 2 A 130 intel INSTRUCTION SET REFERENCE Encoding 1001 1110 tttt 1001 5556 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation SUB Rm lt Rm WRj SUB Rm DRk Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 1001 1110 uuuu 1011 5555 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation SUB Rm lt Rm DRk SUBB A src byte Function Description Flags Example Subtract with borrow SUBB subtracts the specified variable and the CY flag together from the accumulator leaving the result in the accumulator SUBB sets the CY bor
216. Watchdog Timer Address S A6H Reset State XXXX XXXXB 7 0 WDTRST Contents Write only Bit Bit Number Mnemonic Function 7 0 WDTRST 7 0 Provides user control of the hardware WDT C 54 intel Glossary intel GLOSSARY This glossary defines acronyms abbreviations and terms that have special meaning in this man ual Chapter 1 Guide to this Manual discusses notational conventions and general terminol 0datal6 1datal6 data datal6 short accumulator addr11 addr16 addr24 ALU assert A 32 bit constant that is immediately addressed in an instruction The upper word is filled with zeros A 32 bit constant that is immediately addressed in an instruction The upper word is filled with ones An 8 bit constant that is immediately addressed in an instruction A 16 bit constant that is immediately addressed in an instruction A constant equal to 1 2 or 4 that is immediately addressed in an instruction A register or storage location that forms the result of an arithmetic or logical operation An 11 bit destination address The destination can be anywhere in the same 2 Kbyte block of memory as the first byte of the next instruction A 16 bit destination address The destination can be anywhere within the same 64 Kbyte region as the first byte of the next instruction A 24 bit destination address The destination can be anywhere
217. When a good reception is completed the write marker can be advanced to the position ofthe write pointer to set up for writing the next data set When a bad receptionis completed the write pointer can be reversed to the position of the write marker to enable the SIU to rewrite the last data set after receiving the data again The write marker advance and write pointer reversal can be accom plished two ways explicitly by software or automatically by hardware as specified by bits in the RXFIFOx control register It is not practical for the 82930A to begin scooping the RXFIFO before all bytes are received and successfully acknowledged because the reception may be bad Once it begins scooping the FIFO the 82930 can use the FIFO empty flag to signal an end to reading data The SIU can monitor the FIFO full flag FULL bit in RXFLGx to avoid overwriting data in the RXFIFO The 82930A can monitor the FIFO empty flag EMPTY bit in RXFLGx to avoid read ing a byte when the FIFO is empty As in the transmit FIFO the receive FIFO uses a pair of bits FIF1 0 in the register to indicate which data sets are present in the RXFIFO see Table 7 9 Table 7 9 Status of the RXFIFO Data Sets Data Sets Written FIF1 0 ds1 450 0 Yes 1 set 1 0 Yes No 1 set 1 1 Yes Yes 2 sets Figure 7 9 an operational model of RXFIFOx shows the management of the data sets for writes by the S
218. When not used by P1 4 CEX2 the PCA these pins can handle standard I O P1 5 1 6 1 7 17 intel PROGRAMMABLE COUNTER ARRAY 11 3 PCA COMPARE CAPTURE MODULES Each compare capture module is made up of compare capture register pair a 16 bit comparator and various logic gates and signal transition selectors The registers store the time or count at which an external event occurred capture or at which an action should occur comparison In the PWM mode the low byte register controls the duty cy cle of the output waveform The logical configuration of a compare capture module depends on its mode of operation Fig ures 11 2 through 11 5 Each module can be independently programmed for operation in any of the following modes 16 bit capture mode with triggering on the positive edge negative edge or either edge Compare modes 16 bit software timer 16 bit high speed output 16 bit WDT module 4 only or 8 bit pulse width modulation No operation Bit combinations programmed into a compare capture module s mode register CCAPMx deter mine the operating mode Figure 11 9 provides bit definitions and Table 11 3 lists the bit combi nations of the available modes Other bit combinations are invalid and produce undefined results The compare capture modules perform their programmed functions when their common time base the timer counter runs The timer
219. X 11 1 00 ADV_RM X 00 Unchanged 01 ADV_RM X 00 Unchanged 11 ADV_RM X 10 01 Unchanged 10 ADV RM X 00 Unchanged XX REV RP X Unchanged Unchanged 5 4 Reserved Values read from these bits are indeterminate Write zeros to these bits 3 EMPTY TXFIFO Empty Flag Hardware sets this bit when the write pointer is at the same location as read pointer Hardware clears this bit when the pointers are at different locations Software can read and write this bit 2 FULL TXFIFO Full Flag Hardware sets this bit after a byte is written to TXFIFO when the write pointer is one location below the read marker Hardware clears this bit when this condition no longer holds Software can read and write this bit 1 URF TXFIFO Underrun Flag Hardware sets this bit when the SIU reads a byte from an empty FIFO Hardware does not clear this bit Software can read and write this bit 0 OVF TXFIFO Overrun Flag This bit is set when the 82930A writes an additional byte to a full FIFO or writes a byte count to with FIF1 0 11 Hardware does not clear this bit Software can read and write this bit 52 intel REGISTERS TXSTATx Address See Table 7 16 0 3 Reset State See Table 7 16 7 0 T SEQ T VOID T ERR T ACK Bit Bit Number Mnemonic Function 7 T SEQ Transmitters current sequence bit This bit will be transmitted in the next PID and toggled o
220. a port Px x 0 3 add 1 state 1011 0000 bit addr Binary Mode Encoding Source Mode Encoding ANL lt CY bit51 A 41 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel ANL Binary Mode Source Mode Bytes 4 3 States 3t 2T tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 1010 1001 1000 0 diradar Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ANL CY lt CY A bit ANL CY bit Binary Mode Source Mode Bytes 4 3 States 3t 21 Tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 1010 1001 1111 0 yyy dir addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ANL CY lt CY A bit CJNE lt dest gt lt src gt rel Function Description A 42 Compare and jump if not equal Compares the magnitudes of the first two operands and branches if their values not equal The branch destination is computed by adding the signed relative displacement in the last instruction byte to the PC after incrementing the PC to the start of the next instruction If the unsigned integer value of lt dest byte gt is less than the unsigned integer value of src byte the CY flag is set Neither operand is affected The first two operands allow four addressing mode combinations the accumu
221. able 12 5 You may select differ ent baud rates for the transmitter and receiver Setting RCLK and or TCLK puts timer 2 into its baud rate generator mode Figure 12 5 In this mode a rollover in the TH2 register does not set the TF2 bit in the T2CON register Also a high to low transition at the T2EX pin sets the EXF2 bit in the T2CON register but does not cause a reload from RCAP2H RCAP2L to TH2 TL2 You can use the T2EX pin as an additional external interrupt by setting the EXEN2 bit in T2CON You may configure timer 2 as a timer or a counter In most applications it is configured for timer operation i e the C T2 bit is clear in the T2CON register 12 12 intel SERIAL I O PORT Table 12 5 Selecting the Baud Rate Generator s RCLCK TCLCK Receiver Transmitter Bit Bit Baud Rate Generator Baud Rate Generator 0 Timer 1 Timer 1 1 Timer 1 Timer 2 1 0 Timer 2 Timer 1 1 1 Timer 2 Timer 2 Note Oscillator frequency Ti 1 is divided by 2 not 12 DUET RX Clock TX Clock RCAP2H RCAP2L TCLCK Interrupt T2EX 5 4 EXF2 Reuse EXEN2 Note availability of additional external interrupt 4120 01 Figure 12 5 Timer 2 Baud Rate Generator Mode 12 18 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Note that timer 2 increments every state time 2Tosc when it is in the baud rate generator mode In the baud rate formula tha
222. abled by ET2 in register IEO 6 3 PROGRAMMABLE COUNTER ARRAY PCA INTERRUPT The programmable counter array PCA interrupt is generated by logical OR of five event flags CCFx and the PCA timer overflow flag CF in the CCON register see Figure 11 8 All PCA interrupts share a common interrupt vector Bits are not cleared by hardware vectors to service routines Normally interrupt service routines resolve interrupt requests and clear flag bits This allows the user to define the relative priorities of the five PCA interrupts The PCA interrupt is enabled by bit EC in the IEO register see Figure 6 1 In addition the CF flag and each of the CCFx flags must also be individually enabled by bits ECF and in reg isters and CCAPM lt x respectively for the flag to generate an interrupt see Figure 11 8 and Figure 11 9 NOTE CCFx refers to 5 separate bits one for each PCA module CCFO CCF1 CCF2 CCF3 CCF4 refers to 5 separate registers one for each PCA module CCAPMO CCAPM2 CCAPM3 CCAPMA 6 4 SERIAL PORT INTERRUPT Serial port interrupts are generated by the logical OR of bits RI and TI in the SCON register see Figure 12 2 Neither flag is cleared by a hardware vector to the service routine The service rou tine resolves RI or TI interrupt generation and clears the serial port request flag The serial port interrupt is enabled by bit ES in the IEO register see Figure 6 3 6 5
223. above 3 V to indicate that power has been off or had fallen below 3 V and that on chip volatile memory is indeterminate Set or cleared by software 3 GF1 General Purpose Flag Set or cleared by software One use is to indicate whether an interrupt occurred during normal operation or during idle mode 2 GFO General Purpose Flag Set or cleared by software One use is to indicate whether an interrupt occurred during normal operation or during idle mode 1 PD Powerdown Mode Bit When set activates powerdown mode Cleared by hardware when an interrupt or reset occurs 0 IDL Idle Mode Bit When set activates idle mode Cleared by hardware when an interrupt or reset occurs If IDL PD are both set PD takes precedence Figure 14 1 Power Control PCON Register 14 2 intel Table 14 1 Pin Conditions in Various Modes SPECIAL OPERATING MODES Mode Program ALE PSEN Port 0 Port 1 Port 2 Port 3 Memory Pin Pin Pins Pins Pins Pins Reset Don t Care Weak High Weak High Floating Weak High Weak High Weak High Idle Internal 1 1 Data Data Data Data Idle External 1 1 Floating Data Data Data Powerdown Internal 0 0 Data Data Data Data Powerdown External 0 0 Floating Data Data Data ONCE Don t Care Floating Floating Floating Weak High Weak High Weak High XTAL1 PD IDL Interrupt Serial Port Timer Bl
224. ammed to function as pulse width modulators Figure 11 5 The modulated output which has a pulse width resolution of eight bits is available at the CEXx pin The PWM output can be used to convert digital data to an analog signal with simple external circuitry In this mode the value in the low byte of the PCA timer counter CL is continuously compared with the value in the low byte of the compare capture register CCAPxL When CL lt CCAPxL the output waveform Figure 11 6 is low When a match occurs CL CCAPxL the output waveform goes high and remains high until CL rolls over from FFH to 00H ending the period At rollover the output returns to a low the value in is loaded into CCAPxL and a new period begins 11 10 intel PROGRAMMABLE COUNTER ARRAY CL rollover from to 00H loads contents into CCAPxL X Don t Care x 0 1 2 3 4 8 Bit Comparator 1 4166 01 Figure 11 5 PCA 8 bit PWM Mode The value in CCAPxL determines the duty cycle of the current period The value in CCAPxH de termines the duty cycle of the following period Changing the value in CCAPxL over time mod ulates the pulse width As depicted in Figure 11 6 the 8 bit value in CCAPxL can vary from 0 10046 duty cycle to 255 0 496 duty cycle NOTE To change the value in CCAPxL without glitches write the new value to the high byte register This value
225. an interrupt request The overflow also causes the 16 bit value in RCAP2H and RCAP2L to be loaded into the timer registers TH2 and TL2 When T2EX is low timer 2 counts down Timer underflow occurs when the count in the timer registers TH2 TL2 equals the value stored in RCAP2H and RCAP2L The underflow sets the TF2 bit and reloads FFFFH into the timer registers The EXF2 bit toggles when timer 2 overflows or underflows changing the direction of the count When timer 2 operates as an up down counter EXF2 does not generate an interrupt This bit can be used to provide 17 bit resolution Down Counting Reload Value FFH FFH Interrupt Request Count Direction 1 0 Down RCAP2H RCAP2L Up Counting Reload Value A4114 01 Figure 10 9 Timer 2 Auto Reload Mode DCEN 1 10 13 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel 10 6 3 Baud Rate Generator Mode This mode configures timer 2 as a baud rate generator for use with the serial port Select this mode by setting the RCLK and or TCLK bits in T2CON See Table 10 3 For details regarding this mode of operation refer to section 12 6 Baud Rates 10 6 4 Clock out Mode In the clock out mode timer 2 functions as a 50 duty cycle variable frequency clock Figure 10 10 The input clock increments TLO at frequency Fosc 2 The timer repeatedly counts to over flow from a preloaded value At overflow the conte
226. apter 4 Ports P1 and P3 carry bus con trol and peripheral signals The 82930A has two power saving modes In idle mode the CPU clock is stopped while clocks to the peripherals continue to run In powerdown mode the on chip oscillator is stopped and the chip enters a static state An enabled interrupt or a hardware reset can bring the chip back to its normal operating mode from idle or powerdown See Chapter 14 Special Operating Modes for details on the power saving modes Many instructions can operate on 8 16 or 32 bit operands providing easier and more efficient programming in high level languages such as C Additional features include the TRAP instruc tion a displacement addressing mode and several conditional jump instructions Chapter 5 structions and Addressing describes the instruction set and compares it with the instruction set for MCS 51 microcontrollers You can configure the 82930A to run in binary mode or source mode Either mode executes all of the MCS 51 architecture instructions and all of the MCS 251 architecture instructions How ever source mode is more efficient for MCS 251 architecture instructions and binary mode is more efficient for MCS 51 architecture instructions In binary mode object code for an MCS 51 microcontroller runs on the 82930A without recompiling If a system was originally developed using an MCS 51 microcontroller and if the new 82930A based system will run code written for t
227. ared to receive Receive data but discard Set timeout status Receive data and write to RXFIFO Check for overrun and CRC Set status and latch Done Note This branch should never be allowed under proper ISO operation dictated by firmware 4203 01 Figure 8 19 SIU Receive Operations for Isochronous Data Overview 8 25 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel A See Table 5 7 for RX enable See Table 5 8 for RX ready Set R VOID RXSTATx 2 B Receive data and write to RXFIFO End of transfer RXCNT See Table 5 9 1 amp Table 5 10 RXFLGx 1 Set R ERR RXSTATx 1 Set error status Set R ACK RXSTATx 0 Set ACK status Latch status Done A4202 01 Figure 8 20 SIU Receive Operations for Isochronous Data Details 8 26 intel USB OPERATING MODES 8 3 3 Operations Reception status is updated at the end of data reception based on the handshake received from the host non isochronous data or based on the transmission process itself isochronous data For a non isochronous transfer the SIU generates a receive done interrupt RXD The function of the post receive service routine is to manage the receiver s state to ensure data integrity and latency for the next reception The post receive routine also transfers the received data set to the end func tion For isochronous data the post receive
228. at the same priority level as the one just processed For INTR 1 an interrupt pushes the three PC bytes and PSW1 onto the stack in the following order PSW 1 PC 23 16 7 0 PC 15 8 The RETI instruction pops these four bytes and then returns to the specified 24 bit address which can be anywhere in the 16 Mbyte address space RETI also clears the interrupt request line See the note in Table 5 8 regarding compatibility with code written for MCS 51 microcontrollers The TRAP instruction is useful for the development of emulations of an 82930A microcontroller 5 6 PROGRAM STATUS WORDS The Program Status Word PSW register Figure 5 2 and the Program Status Word 1 PSWI register Figure 5 3 contain four types of bits CY AC OV N and Z are flags set by hardware to indicate the result of an operation The P bit indicates the parity of the accumulator e Bits RSO and RS1 are programmed by software to select the active register bank for registers RO R7 FO and UD are available to the user as general purpose flags 5 14 intel INSTRUCTIONS AND ADDRESSING The PSW and PSWI registers are read write registers however the parity bit in the PSW is not affected by a write Individual bits can be addressed with the bit instructions see section 5 4 1 Bit Instructions The PSW and PSWI bits are used implicitly in the conditional jump instruc tions see section 5 5 2 Conditional Jumps The PSW register is
229. ata16 16 bit unsigned immediate data to from 5 6 4 5 dword reg Sug Rm dir8 Dir addr to from byte reg 4 3 2 3 2 2 WRij dir8 Dir addr to from word reg 4 4 3 3 Rm dir16 Dir addr 64K to from byte reg 5 3 4 2 WRj dir16 Dir addr 64K to from word reg 5 4 4 3 Rm WRj Indir addr 64k to from byte reg 4 3 3 2 Rm DRk Indir addr 16M to from byte reg 4 4 3 3 A Rn Reg to from acc with carry 1 1 2 2 ADDC A dir8 Dir byte to from acc with carry 2 1 2 2 1 2 SUBB Indir RAM to from acc with carry 1 2 2 3 A data Immediate data to from acc with carry 2 1 2 1 NOTES 1 A shaded cell denotes an instruction in the MCS 51 architecture 2 If this instruction addresses an I O port Px x 3 0 add 1 to the number of states 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Table A 20 Summary of Compare Instructions intel Compare CMP lt dest gt lt src gt dest src Binary Mode Source Mode Mnemonic lt dest gt lt src gt Notes Bytes States Bytes States Rmd Rms Reg with reg 3 2 2 1 WRijd WRjs Word reg with word reg 3 3 2 2 DRkd DRks Dword reg with dword reg 3 5 2 4 Rm data Reg with immediate data 4 3 3 2 WR j data16 Word reg with immediate 16 bit data 5 4 4 3 DRk 0data16 Dword reg with zero extended 16 bit 5 6 4 5 immediate data CMP DRk 1data16 Dword reg with one extended 16 bit 5 6 4 5 immediate data Rm dir8 Dir addr from byte reg 4 3t
230. ation 12 7 SFRs 3 16 12 1 12 2 C 3 synchronous mode 12 4 timer 1 baud rate 12 10 12 12 timer 2 baud rate 12 12 12 14 timing mode 0 12 5 SETB instruction 5 10 A 24 SETUP Token 8 31 SFRs accessing 3 13 address space 3 1 3 2 idle mode 14 4 MCS 51 architecture 3 4 powerdown mode 14 5 reset initialization 13 6 reset values 3 13 tables of 3 15 unimplemented 3 13 Shift instruction 5 9 SJMP instruction 5 13 A 25 SLL instruction 5 9 A 18 Software application notes 1 5 Source register 5 3 intel SP 3 13 3 15 C 2 C 40 Special function registers See SFRs SPH 3 13 3 15 C 2 C 41 SPX 3 11 3 13 SRA instruction 5 9 A 19 SRL instruction 5 9 A 19 Start of frame SOF Token 8 33 State time 2 7 SUB instruction 5 8 A 15 SUBB instruction 5 8 A 15 SWAP instruction 5 9 A 19 T T1 0 9 1 10 3 T2 9 1 10 3 T2CON 3 16 10 1 10 2 10 10 10 17 12 12 C 3 C 42 baud rate generator 12 12 T2EX 9 1 10 3 10 11 12 12 T2MOD 3 16 10 1 10 2 10 10 10 16 C 3 C 43 Target address 5 4 TCON 3 16 10 1 10 2 10 4 10 6 10 8 C 3 44 interrupts 6 1 TH2 TL2 baud rate generator 12 14 baud rate generator 12 12 THx TLx x 0 1 2 3 16 10 2 C 3 C 46 C 47 C 48 Timer 0 10 4 10 8 applications 10 9 auto reload 10 5 interrupt 10 4 mode 0 10 4 mode 1 10 5 mode 2 10 5 mode 3 10 5 pulse width measurements 10 10 Timer 1 applications 10 9 auto reload 10 9
231. ation branches to a subroutine and performs some service in response to the interrupt When the subroutine completes execution resumes at the point where the interrupt oc curred Interrupts may occur as a result of internal 82930A activity e g timer overflow or at the initiation of electrical signals external to the microcontroller e g serial port communication In all cases interrupt operation is programmed by the system designer who determines priority of interrupt service relative to normal code execution and other interrupt service routines Eleven of the twelve interrupts are enabled or disabled by the system designer and may be manipulated dy namically A typical interrupt event chain occurs as follows An internal or external device initiates an inter rupt request signal This signal connected to an input pin see Table 6 1 and periodically sam pled by the 82930A latches the event into a flag buffer The priority of the flag see Table 6 2 Interrupt System Special Function Registers is compared to the priority of other interrupts by the interrupt handler A high priority causes the handler to set an interrupt flag This signals the in struction execution unit to execute a context switch This context switch breaks the current flow of instruction sequences The execution unit completes the current instruction prior to a save of the program counter PC and reloads the PC with the start address of a software service routine The sof
232. ator to memory The external memory is in the region specified by DPXL whose reset value is 01H See section 3 3 2 Dedicated Registers in Chapter 3 The MOVC Move Code instruction moves a byte from code memory region FF to the accu mulator MOVS Move with Sign Extension and MOVZ Move with Zero Extension move the contents of an 8 bit register to the lower byte of a 16 bit register The upper byte is filled with the sign bit MOVS or zeros MOVZ The MOVH Move to High Word instruction places 16 bit immedi ate data into the high word of a dword register The XCH Exchange instruction interchanges the contents of the accumulator with a register or memory location The XCHD Exchange Digit instruction interchanges the lower nibble of the accumulator with the lower nibble of a byte in on chip RAM XCHD is useful for BCD binary coded decimal operations 5 9 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel The PUSH and POP instructions facilitate storing information PUSH and then retrieving it POP in reverse order Push can push a byte a word or a dword onto the stack using the imme diate direct or register addressing modes POP can pop a byte or a word from the stack to a reg ister or to memory 5 4 BIT INSTRUCTIONS A bit instruction addresses a specific bit in a memory location or SFR There are four categories of bit instructions SETB Set Bit CLR Clear Bit CPL Complement Bit Thes
233. be the accumulator or immediate data When the destination is register the source can be register immediate direct and indirect addressing Note When this instruction is used to modify an output port the value used as the original port data is read from the output data latch not the input pins OV N 2 accumulator contains 0C3H 11000011B and RO contains 55H 01010101 After executing the instruction ORL A RO A 107 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel the accumulator contains 0D7H 11010111B When the destination is a directly addressed byte the instruction can set combinations of bits in any RAM location or hardware register The pattern of bits to be set is determined by a mask byte which may be a constant data value in the instruction or a variable computed in the accumulator at run time After executing the instruction ORL 1 001100108 Sets bits 5 4 and 1 of output Port 1 Variations ORL dir8 A Binary Mode Source Mode Bytes 2 2 States 2T 2t tlf this instruction addresses a port Px x 0 3 add 2 states Encoding 0100 0010 direct addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation ORL dir8 lt dir8 V ORL dir8 data Binary Mode Source Mode Bytes 3 3 States 3t 3t Tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 0100 0011 direct addr
234. bit enables external interrupt 0 Figure 6 3 Interrupt Enable Register 0 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Number Mnemonic IE1 Address S B1H Reset State 00H Interrupt Enable 1 Register 7 0 IE1 3 IE1 2 IE1 1 IE1 0 Bit Bit Function 7 4 Reserved Values read from these bits are indeterminate Write zeros to these bits 3 0 1 3 0 Interrupt Enable Endpoints 3 0 Figure 6 4 Interrupt Enable Register 1 intel INTERRUPTS SBIE Address S A1H Reset State 00H USB Interrupt Enable Register 7 0 RXIE3 RXIE2 TXIE2 RXIE1 TXIE1 RXIEO TXIEO Function 7 RXIES Receive Done Interrupt Enable Endpoint 3 Setting this bit enables the interrupt for flag bit RXD3 in the SBI register 6 Transmit Done Interrupt Enable Endpoint 3 Setting this bit enables the interrupt for flag bit TXD3 in the SBI register 5 RXIE2 Receive Done Interrupt Enable Endpoint 2 Setting this bit enables the interrupt for flag bit RXD2 in the SBI register 4 TXIE2 Transmit Done Interrupt Enable Endpoint 2 Setting this bit enables the interrupt for flag bit TXD2 in the SBI register 3 RXIE1 Receive Done Interrupt Enable Endpoint 1 Setting this bit enables the interrupt for flag bit RXD1 in the SBI register 2 TXIE1 Transmit Done
235. broutine call 5 14 4 13 WRj Long subroutine call indirect 3 9 2 8 LCALL 16 Long subroutine call 3 9 3 9 RET Return from subroutine 1 6 1 6 ERET Extended subroutine return 3 10 2 9 RETI Return from interrupt 6 1 6 AJMP addr11 Absolute jump 2 3 2 3 addr24 Extended jump 5 6 4 5 EJMP DRk Extended jump indirect 3 7 2 6 Long jump indirect 3 6 2 5 LJMP addr16 Long jump 3 4 3 4 SJMP rel Short jump relative addr 2 3 2 3 JMP A DPTR Jump indir relative to the DPTR 1 5 1 5 JC rel Jump if carry is set 2 1 4 2 1 4 JNC rel Jump if carry not set 2 1 4 2 1 4 bit51 Jump if dir bit is set 3 2 5 3 2 5 JB bit rel Jump if dir bit of 8 bit addr location 5 4 7 4 3 6 is set bit51 Jump if dir bit is not set 3 2 5 3 2 5 JNB bit rel Jump if dir bit of 8 bit addr location 4 7 3 6 is not set bit51 rel Jump if dir bit is set amp clear bit 3 4 7 3 4 7 JBC bit rel Jump if dir bit of 8 bit addr location 5 7 10 4 6 9 is set and clear bit JZ rel Jump if acc is zero 2 2 5 2 2 5 JNZ rel Jump if acc is not zero 2 2 5 2 2 5 JE rel Jump if equal 3 2 5 2 1 4 JNE rel Jump if not equal 3 2 5 2 1 4 JG rel Jump if greater than 3 2 5 2 1 4 JLE rel Jump if less than or equal 3 2 5 2 1 4 JSL rel Jump if less than signed 3 2 5 2 1 4 NOTES 1 A shaded cell denotes an instruction in the MCS 51 architecture 2 For conditional jumps times are given as not taken taken A 25 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER US
236. byte block the 2 Kbyte block that includes the first byte of the next instruction addr16 Only the lower 16 bits of the PC are changed i e the target address must be in the current 64 Kbyte region the 64 Kbyte region that includes the first byte of the next instruction addr24 The target address can be anywhere in the 16 Mbyte address space ndirect addressing There are two types of indirect addressing for control instructions For the instructions LCALL WRj and LIMP WRJ the target address is in the current 64 Kbyte region The 16 bit address in WRj is placed in the lower 16 bits of the PC The upper eight bits of the PC remain unchanged from the address of the next instruction For the instruction JMP A DPTR the sum of the accumulator and DPTR is placed in the lower 16 bits of the PC and the upper eight bits of the PC are FF which restricts the target address to the code memory space of the MCS 51 architecture Table 5 8 Addressing Modes for Control Instructions Description Address Bits Address Range Provided Relative 8 bit relative address rel 8 128 to 127 from first byte of next instruction Direct 11 bit target address addr11 11 Current 2 Kbytes Direct 16 bit target address addr16 16 Current 64 Kbytes Direct 24 bit target address addr24 t 24 00 0000H FF FFFFH Indirect WRi t 16 Current 64 Kbytes Indirect A DPTR 16 64 Kbyte region specifie
237. bytes FFFFH 64 Kbytes External Flash 0000H 0420H 7FFFH 32 Kbytes 1056 Bytes External RAM 1056 Bytes On chip RAM 4168 02 Figure 15 15 Memory Space for Example 2 15 15 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel 15 6 3 Example 3 RD1 0 11 16 bit Bus External EPROM and RAM In this example an 82930A operates in nonpage mode with a 16 bit external address bus inter faced to 64 Kbytes of EPROM and 64 Kbytes of RAM Figure 15 16 The 82930A is configured so that RD is asserted for addresses 7F FFFFH and PSEN is asserted for addresses gt 80 0000H Figure 15 17 shows two ways to address the external memory in the internal memory space Addressing external RAM locations in either region 00 or region 01 produces the same address at the external bus pins However if the external EPROM and the external RAM require different numbers of wait states the external RAM must be addressed entirely in region 01 Recall that the number of wait states for region 01 is independent of the remaining regions which always have the same number of wait states See Table 4 3 in Chapter 4 Device Configuration The examples that follow illustrate two possibilities for addressing the external RAM 15 6 3 1 An Application Requiring Fast Access to the Stack If an application requires fast access to the stack the stack can reside in the fast on chip data RAM 00 0020 00 041 and
238. c the symbol prefixes an immediate value in immediate addressing mode Italics identify variables and introduce new terminology The context in which italics are used distinguishes between the two possible meanings Variables in registers and signal names are commonly represented by x and y where x represents the first variable and y represents the second variable For example in register Px y x represents the variable 1 4 that identifies the specific port and y represents the register bit variable 7 0 Variables must be replaced with the correct values when configuring or programming registers or identifying signals Uppercase X no italics represents an unknown value or a don t care state or condition The value may be either binary or hexadecimal depending on the context For example 2XAFH hex indicates that bits 11 8 are unknown 10XX in binary context indicates that the two LSBs are unknown The terms assert and deassert refer to the act of making a signal active enabled and inactive disabled respectively The active polarity high low is defined by the signal name Active low signals are designated by a pound symbol suffix active high signals have no suffix To assert RD is to drive it low to assert ALE is to drive it high to deassert RD is to drive it high to deassert ALE is to drive it low Instruction mnemonics are shown in upper case to avoid confusion When writing code either upper case or l
239. cates that a flag influences the decision to jump Table A 28 Flag Symbols Symbol Description The instruction does not modify the flag instruction sets or clears the flag as appropriate 1 The instruction sets the flag 0 The instruction clears the flag The instruction leaves the flag in an indeterminate state For a conditional jump instruction The state of the flag before the instruction executes influences the decision to jump or not jump lt addr11 gt Function Absolute call Description Unconditionally calls a subroutine at the specified address The instruction increments the 3 byte PC twice to obtain the address of the following instruction then pushes bytes 0 and 1 of the result onto the stack byte 0 first and increments the stack pointer twice The destination address is obtained by successively concatenating bits 15 11 of the incremented PC opcode bits 7 5 and the second byte of the instruction The subroutine called must therefore start within the same 2 Kbyte page of the program memory as the first byte of the instruction following ACALL Flags OV N 2 Example The stack pointer SP contains 07H and the label SUBRTN is at program memory location 0345H After executing the instruction ACALL SUBRTN at location 0123H SP contains 09H on chip RAM locations 08H and 09H contain 01H and 25H respectiv
240. cations 20H 41FH These RAM locations can be accessed with direct indirect and displacement addressing Ninety six of these locations 20H 7FH are bit addressable An additional 32 bytes of on chip RAM 00H 1FH provide stor age for the four banks of registers RO R7 2 4 PERIPHERALS The on chip peripherals which lie outside the core perform specialized functions Software ac cesses the peripherals via their special function registers SFRs The 82930A has five peripher als the USB the watchdog timer the timer counters the programmable counter array PC A and the serial I O port 2 4 1 Universal Serial Bus The 82930A has eight FIFOS four transmit FIFOs TXFIFOx x 0 3 and four receive FIFOs RXFIFOx x 0 3 A transmit FIFO TXFIFOXx is written by the 82930A and then read by the SIE Interface Unit SIU for transmission A receive FIFO RXFIFOx is written by the SIU fol lowing reception and then read by the 82930A The FIFO pair for endpoint 1 has a capacity of 256 bytes each FIFO The FIFOs for the other endpoints have capacities of 16 bytes see Chap ter 7 Universal Serial Bus Table 7 1 All transmit FIFOs have the same architecture and all receive FIFOs have the same architecture The serial bus interface unit SIU manages communications between the 82930A and the USB host It consists of the Serial Interface Engine SIE which handles the communication protocol of Universal Serial Bus and the Ser
241. ce Mode ken Taken 3 A 43 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel States 3 6 3 6 Encoding 1011 0101 direct addr rel addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation PC 3 IF A dir8 THEN PC relative offset IF A dir8 THEN lt 1 ELSE CY 0 CJNE Ri data rel Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes 3 3 4 4 States 3 6 4 7 Encoding 1011 011i immed data rel addr Hex Code in Binary Mode Encoding Source Mode A5 Encoding Operation PC 3 IF Ri data THEN PC lt relative offset IF Ri lt data THEN CY 1 ELSE CY 0 CJNE Rn data rel Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes 3 3 4 4 States 2 5 3 6 Encoding 1011 Tree immed data rel addr A 44 intel Hex Code in Operation CLRA Function Description Flags Example Bytes States Encoding Hex Code in Operation CLR bit Function Description INSTRUCTION SET REFERENCE Binary Mode Encoding Source Mode A5 Encoding PC 3 IF Rn data THEN PC relative offset IF Rn lt THEN CY 1 ELSE CY 0 Clear accumulator Clears the accumulator i e resets all bits to zero
242. cessor communication automatic address recognition and the serial port interrupt bits SADDR Serial Address Defines the individual address for a slave device A8H SADEN Serial Address Enable Specifies the mask byte that is used to define the B8H given address for a slave device IB Bus Mode 0 Transmit Receive Shift Register Interrupt Request RI TI Serial Control SEN 4123 01 12 2 Figure 12 1 Serial Port Block Diagram intel SERIAL PORT The serial port control SCON register Figure 12 2 configures and controls the serial port SCON Address 98H Reset State 0000 0000B 7 0 FE SMO SM1 SM2 REN TB8 RB8 TI RI Bit Bit Function Number Mnemonic 7 FE Framing Error Bit To select this function set the SMODO bit in the PCON register Set by hardware to indicate an invalid stop bit Cleared by software not by valid frames SMO Serial Port Mode Bit 0 To select this function clear the SMODO bit in the PCON register Software writes to bits SMO and SM1 to select the serial port operating mode Refer to the SM1 bit for the mode selections 6 SM1 Serial Port Mode Bit 1 Software writes to bits SM1 and SMO above to select the serial port operating mode SMO SM1 Mode Description Baud Rate 0 0 0 Shift register Fosc 12 0 1 1 8 bit UART Variable 1 0 2 9 bit UART Fosc 32 or Fogc 64 1 1 3 9 bit UART Variable TSelect by program
243. coding Source Mode Encoding Operation MOV dir8 lt WRJ MOV dir8 DRk Binary Mode Source Mode Bytes 4 3 States 7 6 Encoding 0111 1010 uuuu 1101 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV dir8 lt MOV dir16 Rm Binary Mode Source Mode Bytes 5 4 States 4 3 A 92 intel INSTRUCTION SET REFERENCE Encoding 0111 1010 5555 0011 direct addr direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV dir16 lt Rm MOV dir16 WRj Binary Mode Source Mode Bytes 5 4 States 5 4 Encoding 0111 1010 tttt 0111 direct addr direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV 416 lt WRj MOV dir16 DRk Binary Mode Source Mode Bytes 5 4 States 7 6 Encoding 0111 1010 uuuu 1111 direct addr direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV 16 lt MOV WRj Rm Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 0111 1010 tttt 1001 5555 0000 Hex Code Binary Mode A5 Encoding Source Mode Encoding Operation MOV WRj lt Rm A 93 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL
244. configuration bytes UCONFIGO and UCONFIG1 located in the application code memory space 42 DEVICE CONFIGURATION The 82930A reserves the top eight bytes of the memory address space FF FFF8H FF FFFFH for an eight byte configuration array The two lowest bytes of the configuration array are assigned to the two configuration bytes UCONFIGO FF FFF8H and UCONFIGI FF FFF9H The con figuration information is accessed from external memory using these same addresses This is done by programming the configuration information in an eight byte configuration array located at the highest addresses implemented in external application code memory space See Table 4 1 and Figure 4 3 and 4 1 Bit definitions of UCONFIGO and UCONFIGI are provided in Figures 4 2 and 4 3 The upper 6 bytes of the configuration array are reserved for future use When EA 0 the 82930A obtains configuration information at reset from external application memory us ing internal addresses FF FFF8H and FF FFF9H CAUTION The eight highest addresses in the memory address space FF FFFSH FF FFFFH are reserved for the configuration array Do not read or write application code at these locations These address are also used to access the configuration array in external memory so the same restrictions apply to the 4 1 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel eight highest addresses implemented in external memory Instructions that might inadvertently
245. corporate the 82930 To order documents please call Intel Literature Fulfillment 1 800 548 4725 in the U S and Canada 44 0 793 431155 in Europe Embedded Microcontrollers Order Number 270646 Embedded Processors Order Number 272396 Embedded Applications Order Number 270648 Packaging Order Number 240800 1 3 1 Data Sheet The data sheet is included in Embedded Microcontrollers and is also available individually 82930 Universal Serial Bus Microcontroller Order Number 272797 Application Notes The following MCS 251 application notes apply to the 82930A AP 125 Designing Microcontroller Systems Order Number 210313 for Electrically Noisy Environments AP 155 Oscillators for Microcontrollers Order Number 230659 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel AP 708 Introducing the MCS 251 Microcontroller the 8XC251SB 709 Maximizing Performance Using MCS 251 Microcontroller Programming the 8 2518 AP 710 Migrating from the MCS9 51 Microcontroller to the MCS 251 Microcontroller SXC251SB Software and Hardware Considerations Order Number 272670 Order Number 272671 Order Number 272672 The following MCS 51 microcontroller application notes also apply to the 82930 AP70 Using the Intel MCS9 51 Boolean Processing Capabilities AP 223 8051 Based CRT Terminal Controller AP 252 Designing With the 80 51 AP 425 Small DC Motor Control AP 410 Enhanced Ser
246. ct addr Binary Mode Encoding Source Mode Encoding ANL A A A dir8 Binary Mode Source Mode 1 2 2 3 0101 011i Binary Mode Encoding Source Mode A5 Encoding ANL A lt A A Ri Binary Mode Source Mode 1 2 1 2 0101 37 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Hex Code in Binary Mode Encoding Source Mode A5 Encoding Operation ANL A A Rn ANL Rmd Rms Binary Mode Source Mode Bytes 3 2 States 2 1 Encoding 0101 1100 5555 5555 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ANL Rmd Rmd A Rms ANL WRjd WRjs Binary Mode Source Mode Bytes 3 2 States 3 2 Encoding 0101 1101 tttt Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ANL WRjd WRjd A WRjs ANL Rm Zdata Binary Mode Source Mode Bytes 4 3 States 3 2 Encoding 0101 1110 5555 0000 data Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ANL Rm Rm A data ANL WRij data16 Binary Mode Source Mode Bytes 5 4 States 4 3 A 38 intel INSTRUCTION SET REFERENCE Encoding 0101 1110 tttt 0100 data hi data low Hex Code in Binary
247. cted outputs at the port pins the instruction immediately following the instruction that activated the powerdown mode should not write to a port pin or to the external RAM 14 6 intel SPECIAL OPERATING MODES 14 5 ON CIRCUIT EMULATION ONCE MODE The on circuit emulation ONCE mode permits external testers to test and debug 82930A based systems without removing the chip from the circuit board A clamp on emulator or test CPU is used in place of the 82930A which is electrically isolated from the system 14 5 1 Entering ONCE Mode To enter the ONCE mode 1 Assert RST to initiate a device reset See section 13 4 1 Externally Initiated Resets and the reset waveforms in Figure 13 5 2 While holding RST asserted apply and hold logic levels to I O pins as follows PSEN low P0 7 5 low P0 4 high 0 3 0 low i e port 0 10H 3 Deassert RST then remove the logic levels from PSEN and port 0 These actions cause the 82930A to enter the ONCE mode Port 1 2 and 3 pins are weakly pulled high and port 0 ALE and pins are floating Table 14 1 Thus the device is electrically isolated from the remainder of the system which can then be tested by an emulator or test CPU Note that in the ONCE mode the device oscillator remains active 14 5 2 Exiting ONCE Mode To exit ONCE mode reset the device 14 7 intel 15 External Memory Interface 15 EXTERNAL MEMORY INTERFACE This cha
248. d intel Description Flags Example Bytes States Encoding Hex Code in Operation JSGE rel Function Description Flags Example INSTRUCTION SET REFERENCE If the Z flag is clear AND the N flag and the OV flag have the same value branch to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice OV N 2 The instruction JSG LABEL 1 causes program execution to continue at LABEL 1 if the Z flag is clear AND the N flag and the OV flag have the same value Binary Mode Source Mode Not Taken Taken Not Taken Taken 3 3 2 2 2 5 1 4 0001 1000 Binary Mode A5 Encoding Source Mode Encoding JSG PC PC 2 IF 0 AND OV THEN lt rel Jump if greater than or equal signed If the N flag and the OV flag have the same value branch to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice OV N 2 The instruction JSGE LABEL 1 causes program execution to continue at LABEL 1 if the N flag and the OV flag
249. d Rms Byte reg to byte reg 3 2 2 1 WRjd WRjs Word reg to word reg 3 2 2 1 DRkd DRks Dword reg to dword reg 3 3 2 2 Rm data 8 bit immediate data to byte reg 4 3 3 2 WR data16 16 bit immediate data to word reg 5 3 4 2 DRk 0data16 zero extended 16 bit immediate data 5 5 4 4 to dword reg DRk 1data16 one extended 16 bit immediate data 5 5 4 4 to dword reg NOTES 1 2 3 4 A shaded cell denotes an instruction in the MCS 51 architecture Instructions that move bits are in Table A 26 If this instruction addresses an I O port Px x 0 3 add 1 to the number of states External memory addressed by instructions in the MCS 51 architecture is in the region specified by DPXL reset value 01H See Compatibility with the MCS 51 Architecture in Chapter 3 A 20 INSTRUCTION SET REFERENCE intel Table A 24 Summary of Move Instructions Continued Move 2 Move with Sign Extension Move with Zero Extension Move Code Byte Move to External Mem Move from External Mem MOV lt dest gt lt src gt MOVS lt dest gt lt src gt MOVZ lt dest gt lt src gt MOVC lt dest gt lt src gt MOVX dest src MOVX lt dest gt lt srce gt destination lt src destination lt src with sign extend destination src with zero extend A lt code byte external mem lt A A lt source in external mem
250. d by DPXL reset value 01H These modes are not used by instructions in the MCS 51 architecture 5 5 2 Conditional Jumps The 82930A architecture supports bit conditional jumps compare conditional jumps and jumps based on the value of the accumulator A bit conditional jump is based on the state of a bit Ina compare conditional jump the jump is based on a comparison of two operands All conditional jumps are relative and the target address rel must be in the current 256 byte block of code The instruction set includes three kinds of bit conditional jumps intel INSTRUCTIONS AND ADDRESSING JB Jump on Bit Jump if the bit is set JNB Jump on Not Bit Jump if the bit is clear JBC Jump on Bit then Clear it Jump if the bit is set then clear it Section 5 4 1 Bit Addressing describes the bit addressing used in these instructions Compare conditional jumps test a condition resulting from a compare instruction that is assumed to precede the jump instruction The jump instruction examines the PSW and PSW1 reg isters and interprets their flags as though they were set or cleared by a compare CMP instruction Actually the state of each flag is determined by the last instruction that could have affected that flag The condition flags are used to test one of the following six relations between the operands equal not equal gt greater than 2 less than greater than or equal 2
251. ddress A 16 bit memory address 00 0000 00 used in direct addressing The 16 bit data pointer In 82930A microcontrollers DPTR is the lower 16 bits of the 24 bit extended data pointer DPX The 24 bit extended data pointer in 82930A microcontrollers See also DPTR The term deassert refers to the act of making a signal inactive disabled The polarity high low is defined by the signal name Active low signals are designated by a pound symbol suffix active high signals have no suffix To deassert RD is to drive it high to deassert ALE is to drive it low The process of introducing a periodic table Group III or Group V element into a Group IV element e g silicon A Group III impurity e g indium or gallium results in a p type material A Group V intel double word dword edge triggered encryption array EPROM external address FET idle mode input leakage integer internal address interrupt handler interrupt latency interrupt response time interrupt service routine ISR GLOSSARY impurity e g arsenic or antimony results in an n type material A 32 bit unit of data In memory a double word comprises four contiguous bytes See double word The mode in which a device or component recognizes a falling edge high to low transition a rising edge low to high transition or a rising or falling edge of an input signal as the assertion of that signal See also
252. ddress alignment on two byte or four byte 5 1 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel boundaries is not required Words and dwords are stored in memory and the register file in big endien form Table 5 1 Data Types Data Type Number of Bits Bit 1 Byte 8 Word 16 Dword Double Word 32 5 2 1 1 Order of Byte Storage for Words and Double Words The 82930 microcontroller stores words 2 bytes and double words 4 bytes in memory and in the register file in big endien form In memory storage the most significant byte MSB of the word or double word is stored in the memory byte specified in the instruction the remaining bytes are stored at higher addresses with the least significant byte LSB at the highest address Words and double words can be stored in memory starting at any byte address In the register file the MSB is stored in the lowest byte of the register specified in the instruction For a description of the register file see section 3 3 82930A Register File The code fragment in Figure 5 1 illus trates the storage of words and double words in big endien form 5 2 2 Register Notation In register addressing instructions specific indices denote the registers that can be used in that instruction For example the instruction ADD A Rn uses to denote any one of RO R7 i e the range of n is 0 7 The instruction ADD Rm data uses Rm to denote RO
253. ddresses for both memory locations and SFRs because memory locations are addressed only indirectly and SFR locations are ad dressed only directly For compatibility software tools for 82930A microcontrollers recognize this notation for instructions in the 82930 architecture No change is necessary in any code writ ten for MCS 51 controllers For the MCS 251 architecture instructions the memory region prefixes 00 01 FF and the SFR prefix S are required Also software tools for the 82930A architecture permit 00 to be used for memory addresses 00H FFH and permit the prefix S to be used for SFR addresses in instructions in the 82930A architecture 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel 5 2 4 Addressing Modes The 82930A architecture supports the following addressing modes register addressing The instruction specifies the register that contains the operand immediate addressing The instruction contains the operand direct addressing The instruction contains the operand address indirect addressing The instruction specifies the register that contains the operand address displacement addressing The instruction specifies a register and an offset The operand address is the sum of the register contents the base address and the offset relative addressing The instruction contains the signed offset from the next instruction to the target address the address for transfer of control e g
254. digit with that of the on chip RAM location indirectly addressed by the specified register Does not affect the high nibble bits 7 4 of either register A 135 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Flags Example Bytes States Encoding Hex Code in Operation intel OV N 2 RO contains the address 20H the accumulator contains 36H 00110110 and on chip RAM location 20H contains 75H 01110101B After executing the instruction XCHD A RO on chip RAM location 20H contains 76H 01110110B and 35H 00110101B in the accumu lator Binary Mode Source Mode 1101 011i Binary Mode Encoding Source Mode Encoding XCHD A 3 0 gt lt Ri 3 0 XRL dest src Function Description Flags A 136 Logical Exclusive OR for byte variables Performs the bitwise logical Exclusive OR operation V between the specified variables storing the results in the destination The destination operand can be the accumulator a register or a direct address The two operands allow 12 addressing mode combinations When the destination is the accumulator or a register the source addressing can be register direct register indirect or immediate when the destination is a direct address the source can be the accumulator or immediate data Note When this instruction is used to modify an output port the value used as the origina
255. e additional port pin 1 1 P1 7 CEX4 RD asserted for addresses lt 7F FFFFH Asserted for 2 80 0000H Asserted only for writes to MCS9 51 microcontroller data memory locations 64 Kbyte external memory Compatible with MCS 51 microcontrollers NOTE RD1 0 are bits 3 2 of configuration byte UCONFIGO Figure 4 2 Table B 5 82930A Operating Frequency PLLSEL2 PLLSEL1 USB Rate Internal 82930A External XTAL1 Pin 43 Pin 42 Clock Frequency Frequency Required 0 0 N A N A N A 0 1 N A N A N A 1 0 1 5 Mbps 6 Mhz 12 Mhz 1 1 12 Mbps 12 Mhz 12 Mhz intel Registers intel REGISTERS APPENDIX C REGISTERS This appendix is a reference source of information on the 82930A special function registers SFRs The SFR map in Table C 1 provides the address and reset value for each SFR Tables C 2 through C 6 list the SFRs by functional category The remainder of the appendix contains descrip tive tables of the SFRs arranged in alphabetical order Use the prefix S with SFR addresses to distinguish them from other addresses Table C 1 82930A SFR Map and Reset Values F8 RXSTATO CH CCAPOH CCAP1H CCAP2H 0 000 00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX B RXSTAT1 RXSTAT2 RXSTAT3 RXCNTO 1 RXCNT2 F7 00000000 0xxxx000
256. e instructions that read port 0 read this register The other instructions that read port 0 read the port 0 pins When port 0 is used for an external bus cycle the CPU always writes FFH to PO and the former contents of PO are lost 7 0 Contents Bit Bit Number Mnemonic Function 7 0 P0 7 0 Port 0 Register Write data to be driven onto the port 0 pins to these bits C 21 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel P1 Address Reset State S 90H 1111 1111B Port 1 P1 is the SFR that contains data to be driven out from the port 1 pins Read write modify instructions that read port 1 read this register Other instructions that read port 1 read the port 1 pins 7 0 P1 Contents Bit Bit Mnemonic Foneuon 7 0 P1 7 0 Port 1 Register Write data to be driven onto the port 1 pins to these bits C 22 intel REGISTERS P2 Address Reset State Port 2 P2 is the SFR that contains data to be driven out from the port 2 pins Read modify write instructions that read port 2 read this register Other instructions that read port 2 read the port 2 pins S A0H 1111 1111B 7 0 P2 Contents Bit Bit Function 7 0 P2 7 0 Port 2 Register Write data to be driven onto the port 2 pins to these bits C 23 82930A UNIVERSAL SERIAL BUS MICROCONT
257. e lower address bits A7 0 are on port 0 Figure 15 5 shows the two types of external bus cycles for code fetches in page mode The page miss cycle is the same as a code fetch cycle in nonpage mode except D7 0 is multiplexed with A15 8 on P2 For the page hit cycle the upper eight address bits are the same as for the preced ing cycle Therefore ALE is not asserted and the values of A15 8 are retained in the address latches In a single state the new values of A7 0 are placed on port 0 and memory places the in A page rollover occurs when the address increments from the top of one 256 byte page to the bottom of the next e g from FF FAFFH to 15 5 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel struction byte on port 2 Notice that a page hit reduces the available address access time by one state Therefore faster memories may be required to support page mode Figure 15 6 and Figure 15 7 show the bus cycles for data reads and data writes in page mode These cycles are identical to those for nonpage mode except for the different signals on ports 0 and 2 Cycle 1 Page Miss Cycle 2 Page Hit I lt gt State 1 State 2 State 1 ALE PSEN f T Y A17 A16 PO A17 A16 A7 0 17 16 7 0 P2 A15 8 070 D7 0 t During a sequence of page hits PSEN remains low until the end of the last page hit cycle A4274 01 Figure 15 5
258. e 8 15 summarizes the flow of SIU operations for receiving non isochronous data A recep tion begins if the OUT token is decoded as valid by the SIU and the RXFIFO has a vacancy for the data set if the endpoint is enabled If the RXFIFO is prepared to receive data and if the SEQ bits in the packet and the SIU match the SIU writes the data to the RXFIFO and writes the byte count After checking for an overrun error and a CRC error the SIU attends to the SEQ bit sends a handshake to the host to report on the reception and initiates the post receive ISR If ARM 1 the write pointer and write marker are adjusted automatically by the hardware This is not shown in Figure 8 15 Figures 8 16 8 17 and 8 18 provide details of the SIU operations 8 19 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Valid OUT token RX endpoint enabled See Truth Table 5 6 for RX endpoint enabled RX endpoint prepared to receive Set up NACK STALL hshk T D Ae grapes OVE eng eee wi Receive data but discard Send timeout hshk Receive data and send ACK hshk Receive data and write to RXFIFO Check for overrun Check CRC Manage SEQ bit Send and latch hshk status Generate RXD interrupt if enabled Done 4198 01 8 20 Figure 8 15 SIU Receive Operations for Non isochronous Data Overview intel USB OPERATING MODES Table 8 6 Truth Table For RX Endpoint Enable
259. e 82930A uses input output I O ports to exchange data with external devices In addition to performing general purpose I O some ports are capable of external memory operations see Chapter 15 External Memory Interface others allow for alternate functions All four 82930A ports are bidirectional Each port contains a latch an output driver and an input buffer Port 0 and port 2 output drivers and input buffers facilitate external memory operations Port 0 drives the lower address byte onto the parallel address bus and port 2 drives the upper address byte onto the bus In nonpage mode the data is multiplexed with the lower address byte on port 0 In page mode the data is multiplexed with the upper address byte on port 2 All port 1 and port 3 pins serve for both general purpose I O and alternate functions see Table 9 1 Table 9 1 Input Output Port Pin Descriptions NUN Type PENES Alternate Description pq 7 0 I O AD7 0 Address Data Lines Mode Address Lines Mode VO P1 0 VO T2 Timer 2 Clock Input Output y o P1 1 2 Timer 2 External Input 1 2 VO External Clock Input 1 3 PCA Module 0 y o P1 4 VO CEX1 PCA Module 1 I O 1 5 VO 2 PCA Module 2 I O 1 6 Module 3 yo P1 7 lO CEX4 A17 PCA Module 4 I O or 18th Address Bit
260. e 9 1 To use a pin for general purpose output set or clear the corresponding bit in the Px register x 1 3 To use a pin for general purpose input set the bit in the Px register This turns off the output driver FET To configure a pin for its alternate function set the bit in the Px register When the latch is set the alternate output function signal controls the output level Figure 9 1 The operation of ports 1 and 3 is discussed further in Quasi bidirectional Port Operation on page 9 5 9 4 PORT 0 AND PORT 2 Ports 0 and 2 are used for general purpose or as the external address data bus Port 0 shown in Figure 9 2 differs from the other ports in not having internal pullups Figure 9 3 on page 9 4 shows the structure of port 2 An external source can pull a port 2 pin low To use a pin for general purpose output set or clear the corresponding bit in the Px register x 0 2 To use a pin for general purpose input set the bit in the Px register to turn off the output driver FET 9 2 intel INPUT OUTPUT PORTS Alternate Read Output Latch Function Internal Pullup P3 x Internal Bus Write to Latch REA Alternate is Input Function A2239 01 Figure 9 1 Port 1 and Port 3 Structure Address Read Data Control Vcc Latch Internal Bus Write to Latch Read Pin A2238 01 Figure 9 2 Port 0 Structure 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S M
261. e branch destination is computed by adding the signed displacement in the second instruction byte to the PC after incrementing the PC twice Therefore the range of destinations allowed is from 128 bytes preceding this instruction to 127 bytes following it A 123 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Flags Example Bytes States Encoding Hex Code in Operation SLL src Function Description Flags Example Variations SLL Rm Bytes A 124 OV N 2 The label RELADR is assigned to an instruction at program memory location 0123H instruction SJMP RELADR assembles into location 0100H After executing the instruction the PC contains 0123H Note In the above example the instruction following SJMP is located at 102H Therefore the displacement byte of the instruction is the relative offset 0123H 0102H 21H Put another way an SJMP with a displacement of OFEH would be a one instruction infinite loop Binary Mode Source Mode 2 2 4 4 1000 0000 rel addr Binary Mode Encoding Source Mode Encoding SJMP PC 2 lt Shift logical left by 1 bit Shifts the specified variable to the left by 1 bit replacing the LSB with zero The bit shifted out MSB is stored in the CY bit OV N 2 Register 1 co
262. e for code that may contain instructions from both architectures An instruction with a prefixed opcode requires one more byte for code storage and if an addition al fetch is required for the extra byte the execution time is increased by one state This means that using fewer prefixed opcodes produces more efficient code If a program uses only instructions from the MCS 51 architecture the binary mode code is more efficient because it uses no prefixes On the other hand if a program uses many more new instruc tions than instructions from the MCS 51 architecture source mode is likely to produce more ef ficient code For a program where the choice is not clear the better mode can be found by experimenting with a simulator A5H Prefix OH 5H 6H FH 6H FH OH MCS 51 MCS 51 MCS 251 Architecture Architecture Architecture A4131 01 Figure 4 6 Binary Mode Opcode Map intel DEVICE CONFIGURATION A5H Prefix 5H 6H FH 6H FH MCS 51 MCS 251 MCS 51 Architecture Architecture Architecture A4130 01 Figure 4 7 Source Mode Opcode Map 4 6 INTERRUPT STACK MODE INTR The INTR bit UCONFIGI 4 determines what bytes are stored on the stack when an interrupt occurs and how the RETI Return from Interrupt instruction restores operation For INTR 0 an interrupt pushes the two lower bytes of the PC onto the stack in the following order PC 7 0 PC 15 8 The RETI instruction pops these
263. e in Binary Mode A5 Encoding Source Mode Encoding Operation ADD Rm Rm ADD WRj dir8 Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 0010 1110 ttti 0101 direct addr A 31 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ADD WRJ lt WRj dir8 ADD 16 Binary Mode Source Mode Bytes 5 4 States 3 2 Encoding 0010 1110 55565 0011 direct addr direct add Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ADD Rm Rm dir16 ADD WhRj dir16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding 0010 1110 tttt 0111 direct addr direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ADD WRJ lt WRJ 16 ADD Rm WRj Binary Mode Source Mode Bytes 4 3 States 3 2 Encoding 0010 1110 tttt 1001 5555 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ADD A 32 Rm lt Rm WRj intel INSTRUCTION SET REFERENCE ADD Rm DRk Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 0010 1110 uuuu 1011 ssss 0000 Hex Code in Binary Mode A5 Encoding Operation ADDC A lt src gt Function Description Flags Exam
264. e instructions can set clear or complement any addressable bit ANL And Logical ANL And Logical Complement ORL OR Logical ORL Or Logical Complement These instructions allow ANDing and ORing of any addressable bit or its complement with the CY flag MOV Move instructions transfer any addressable bit to the carry CY bit or vice versa Bit conditional jump instructions execute a jump if the bit has a specified state The bit conditional jump instructions are classified with the control instructions and are described in section 5 5 2 Conditional Jumps 5 4 1 Bit Addressing The bits that can be individually addressed are in the on chip RAM and the SFRs Table 5 5 The bit instructions that are unique to the MCS 251 architecture can address a wider range of bits than the instructions from the MCS 51 architecture There are some differences in the way the instructions from the two architectures address bits In the MCS 51 architecture a bit denoted by bit51 can be specified in terms of its location within certain register or it can be specified by a bit address in the range 00H 7FH The 82930A ar chitecture does not have bit addresses as such A bit can be addressed by name or by its location within a certain register but not by a bit address Table 5 6 illustrates bit addressing in the two architectures by using two sample bits e RAMBIT is bit 5 in RAMREG which is location 23H and RA
265. e mode bus cycle the data is multiplexed with the upper address byte on port 2 However if the instruction uses 8 bit address e g MOVX the contents of P2 are driven onto the pins when data is not on the pins These logic levels can be used to select 256 bit pages in external memory During bus idle the port 0 and port 2 pins are held at high impedance For port pin status when the chip in is idle mode powerdown mode or reset see Chapter 14 Special Operating Modes 15 6 EXTERNAL MEMORY DESIGN EXAMPLES This section presents several external memory designs for 82930 systems These examples il lustrate the design flexibility provided by the configuration options especially for the PSEN and RD signals Many designs are possible For a general discussion on external memory see Chapter 4 Device Configuration Figures 4 4 and 4 5 depict the mapping of internal memory space into external memory 15 6 4 Example 1 RD1 0 z 00 18 bit Bus External Flash and RAM In this example an 82930A operates in page mode with an 18 bit external address bus interfaced to 128 Kbytes of external flash memory and 128 Kbytes of external RAM Figure 15 12 Figure 15 11 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel 15 13 shows how the external flash and RAM are addressed in the internal memory space On chip data RAM 1056 bytes occupies the lowest addresses in region 00 CE 82930A RAM Flash
266. e reg to word reg with zeros 3 2 2 1 MOVE extension Move A A DPTR Code byte relative to DPTR to acc 1 6 1 6 A A PC Code byte relative to PC to acc 1 6 1 6 A Ri External mem 8 bit addr to acc 4 1 4 2 5 Gus A DPTR External mem 16 bit addr to acc 4 1 5 1 5 Ri A Acc to external mem 8 bit addr 4 1 4 1 4 DPTR A Acc to external mem 16 bit addr 4 1 5 1 5 NOTES EON gt A shaded cell denotes an instruction in the MCS 51 architecture Instructions that move bits are in Table A 26 If this instruction addresses an I O port Px x 0 3 add 1 to the number of states External memory addressed by instructions in the MCS 51 architecture is in the region specified by DPXL reset value 01H See Compatibility with the MCS 51 Architecture in Chapter 3 A 22 intel INSTRUCTION SET REFERENCE Table A 25 Summary of Exchange Push and Pop Instructions Exchange Contents lt dest gt lt src gt A o src Exchange Digit XCHD lt dest gt lt src gt A3 0 lt gt on chip RAM bits 3 0 Push PUSH lt gt SP lt SP 1 SP src Pop POP dest dest lt SP SP lt SP 1 Binary Mode Source Mode Mnemonic lt dest gt lt src gt Notes Bytes States Bytes States A Rn Acc and reg 1 3 2 4 XCH A dir8 Acc and dir addr 2 3 2 2 3 2 A Ri Acc and on chip RAM 8 bit addr 1 4 2 5 A Ri Acc and low nibble in on chip
267. e reset timing sequence While the RST pin is high ALE PSEN and the port pins are weakly pulled high The first ALE occurs 32Tosc after the reset signal goes low For this reason other devices can not be synchro nized to the internal timings of the 82930A NOTE Externally driving the ALE and or PSEN pins to 0 during the reset routine may cause the device to go into an indeterminate state Powering up the 82930A without a reset may improperly initialize the program counter and SFRs and cause the CPU to execute instructions from an undetermined memory location 13 4 4 Power on Reset To automatically generate a reset on power up connect the RST pin to the V cc pin through a 1 uF capacitor as shown in Figure 13 1 When Vecis applied the RST pin rises to Vcc then decays exponentially as the capacitor charg es The time constant must be such that RST remains high above the turn off threshold of the Schmitt trigger long enough for the oscillator to start and stabilize plus 64Tosc At power up Vcc should rise within approximately 10 ms Oscillator start up time is a function the crystal fre quency typical start up times are 1 ms for a 10 MHz crystal and 10 ms for a 1 Mhz crystal During power up the port pins are in a random state until forced to their reset state by the asyn chronous logic Reducing V oc quickly to 0 causes the RST pin voltage to momentarily fall below 0 V This volt age is internally limited and does not harm
268. e this bit 2 FULL RXFIFO Full Flag Hardware sets this bit after a byte is written to RXFIFO when the write pointer is one location below the read pointer or the write marker Hardware clears the bit when this condition no longer holds Software can read and write this bit 1 URF RXFIFO Underrun Flag Hardware sets this bit when an additional byte is read from an empty RXFIFO Hardware does not clear the bit Software can read and write this bit 0 OVF RXFIFO Overrun Flag This bit is set when the SIU writes an additional byte to a full FIFO or writes a byte count to TXONTx with FIF1 0 11 Hardware does not clear this bit Software can read and write this bit Figure 7 13 RXFLGx Register 7 20 intel UNIVERSAL SERIAL BUS Table 7 14 RXFLGx Addresses and Reset Values Register Address Reset Value RXFLGO S E4H 00XX1000B RXFLG1 S E5H 00XX1000B RXFLG2 S E6H 00XX1000B RXFLG3 S E7H 00XX1000B 7 4 SERIAL BUS INTERFACE UNIT 510 The serial bus interface unit SIU manages communications between the 82930A and the USB host It consists of the Serial Interface Engine SIE which handles the communication protocol of Universal Serial Bus and the Serial Bus Manager SBM which manages the USB data that is received and transmitted by the 82930A 7 4 1 Serial Bus Manager SBM The Serial Bus Manager SBM manages data transactions between the 82930A and the USB host
269. e timer value in response to a transition on an in 2 8 intel INTRODUCTION put pin generating an interrupt request when the timer matches a stored value toggling an output pin when the timer matches a stored value generating a programmable PWM pulse width mod ulator signal on an output pin and serving as a software watchdog timer Chapter 11 Program mable Counter Array describes this peripheral in detail 2 4 4 Serial Port The serial I O port provides one synchronous and three asynchronous communication modes synchronous mode mode 0 is half duplex the serial port outputs a clock signal on one pin and transmits or receives data on another pin asynchronous modes modes 1 3 are full duplex i e the port can send and receive simul taneously Mode 1 uses a serial frame of 10 bits a start bit 8 data bits and a stop bit The baud rate is generated by overflow of timer 1 or timer 2 Modes 2 and 3 use a serial frame of 11 bits a start bit eight data bits a programmable ninth data bit and a stop bit The ninth bit can be used for parity checking or to specify that the frame contains an address and data In mode 2 you can use a baud rate of 1 32 or 1 64 of the oscillator frequency In mode 3 you can use the overflow from timer 1 or timer 2 to determine the baud rate In its synchronous modes modes 1 3 the serial port can operate as a slave in an environment where multiple slaves share a single serial
270. ed 8 bit accumulator contents and the contents of a 16 bit base register which may be the 16 LSBs of the data pointer or PC In the latter case the PC is incremented to the address of the following instruction before being added with the accumulator otherwise the base register is not altered Sixteen bit addition is performed OV N 2 99 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Example The accumulator contains a number between 0 and 3 The following instruction sequence translates the value in the accumulator to one of four values defined by the DB define byte directive RELPC INC A MOVC A A PC RET DB 66H DB 77H DB 88H DB 99H If the subroutine is called with the accumulator equal to 01H it returns with 77H in the accumulator The INC A before the MOVC instruction is needed to get around the RET instruction above the table If several bytes of code separated the MOVC from the table the corresponding number would be added to the accumulator instead Variations MOVC A A PC Binary Mode Source Mode Bytes 1 1 States 6 6 Encoding 1000 0011 Hex Code in Binary Mode Encoding Source Mode Encoding Operation MOVC PC PC 1 lt A PC MOVC A A DPTR Binary Mode Source Mode Bytes 1 1 States 6 6 Encoding 1001 0011 Hex Code in Binary Mode Encoding Source Mode Encoding Operation
271. elect the operating mode with T2MOD and TCON register bits as shown in Table 10 3 Auto reload is the default mode Setting RCLK and or TCLK selects the baud rate generator mode Timer 2 operation is similar to timer 0 and timer 1 C T2 selects Fosc 12 timer operation or external pin T2 counter operation as the timer register input Setting TF2 allows TL2 to be in cremented by the selected input The operating modes are described in the following paragraphs Block diagrams in Figures 10 7 through 10 10 show the timer 2 configuration for each mode 10 10 intel TIMER COUNTERS AND WATCHDOG TIMER 10 6 1 Capture Mode In the capture mode timer 2 functions as a 16 bit timer or counter Figure 10 7 An overflow condition sets bit TF2 which you can use to request an interrupt Setting the external enable bit EXEN allows the RCAP2H and RCAP2L registers to capture the current value in timer registers 2 and TL2 in response to a 1 10 0 transition at external input T2EX The transition at 2 also sets bit EXF2 in T2CON 2 bit like TF2 can generate an interrupt Overflow TH2 8 Bits TL2 8 Bits Interrupt Request EXEN2 A4113 02 Figure 10 7 Timer 2 Capture Mode 10 11 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel 10 6 2 Auto reload Mode The auto reload mode configures timer 2 as a 16 bit timer or event counter with automatic reload T
272. ely and the PC contains 0345H Binary Mode Source Mode Bytes 2 2 A 27 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL States Encoding Hex Code in Operation 9 9 a10 a9 a8 1 0001 a7 a5 a4 a3 a2 a1 a0 Binary Mode Encoding Source Mode Encoding ACALL P 1 PC 15 8 ADD dest src Function Description Flags Example Variations ADD A data Bytes States Encoding A 28 Add Adds the source operand to the destination operand which can be a register or the accumu lator leaving the result in the register or accumulator If there is a carry out of bit 7 CY the CY flag is set If byte variables are added and if there is a carry out of bit 3 AC the AC flag is set For addition of unsigned integers the CY flag indicates that an overflow occurred If there is a carry out of bit 6 but not out of bit 7 or a carry out of bit 7 but not bit 6 the OV flag is set When adding signed integers the OV flag indicates a negative number produced as the sum of two positive operands or a positive sum from two negative operands Bit 6 and bit 7 in this description refer to the most significant byte of the operand 8 16 or 32 bit Four source operand addressing modes are allowed register direct register indirect and immediate OV N 2 V V V Register 1 contains 11000011B and regist
273. enumerated SETUP token SOF token Receive SOF IN token Transmit OUT token 4260 01 Figure 8 1 Operating Modes 8 1 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel 8 1 1 82930A Unenumerated Mode From reset the 82930A goes to the unenumerated mode This mode which is different from idle mode precedes bus enumeration In the unenumerated mode the function address in the FADDR register has the default value 00H 8 1 2 82930A Idle Mode The 82930A proceeds from unenumerated mode to idle mode after bus enumeration occurs Dur ing bus enumeration the function address register FADDR is written with a unique value assigned by the host The enumeration process has three steps 1 host sends the 82930A s function address in a data packet through endpoint 0 2 Firmware interprets data 3 Firmware instructs the 82930 CPU to write to the SIU SIE function address register FADDR 82930A is now in idle mode and from this point on it responds to tokens with the assigned address 8 1 3 Transmit and Receive Modes When the 82930A is sending and receiving packets in the transmit and receive modes its opera tion depends on the type of data that is transferred isochronous or non isochronous and the adjustment of the FIFO markers and pointers automatic or manual These differences affect both the 82930A firmware and the operation of the 82930A hardware For isochro
274. equence execution jumps to LABEL2 Remember that AJMP is a two byte instruction so the jump instructions start at every other address Binary Mode Source Mode 1 1 5 5 0111 0011 Binary Mode Encoding Source Mode Encoding JMP PC 15 0 lt DPTR Jump if bit not set If the specified bit is clear branch to the specified address otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC after incrementing the PC to the first byte of the next instruction The bit tested is not modified OV N 2 73 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Example Input port 1 contains 11001010B and the accumulator contains 56H 01010110B After executing the instruction sequence JNB P1 3 LABEL1 JNB ACC 3 LABEL2 program execution continues at label LABEL2 Variations JNB bit51 rel Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes 3 3 3 3 States 2 5 2 5 Encoding 0011 0000 bit addr rel addr Hex Codein Binary Mode Encoding Source Mode Encoding Operation JNB PC PC 3 IF bitb1 0 THEN PC lt PC rel JNB bit rel Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes 5 5 4 4 States 4 7 3 6 Encoding 1010 1001 0011 0 yy directaddr rel adar
275. er 0 contains OAAH 10101010B After executing the instruction ADD R1 RO register 1 contains 6DH 01101101B the AC flag is clear and the CY and OV flags are set Binary Mode Source Mode 2 2 1 1 0010 0100 immed data intel Hex Code in Operation ADD 8 Bytes States Encoding Hex Code in Operation ADD A GRi Bytes States Encoding Hex Code in Operation ADD A Rn Bytes States Encoding Hex Code in Operation ADD Rmd Rms Bytes INSTRUCTION SET REFERENCE Binary Mode Encoding Source Mode Encoding ADD A A data Binary Mode Source Mode 2 2 TT 11 tlf this instruction addresses a port Px x 0 3 add 1 state 0010 0101 direct addr Binary Mode Encoding Source Mode Encoding ADD A A dir8 Binary Mode Source Mode 1 2 2 3 0010 011i Binary Mode Encoding Source Mode A5 Encoding ADD A lt Ri Binary Mode Source Mode 1 2 1 2 0010 drrr Binary Mode Encoding Source Mode A5 Encoding ADD A lt Rn Binary Mode Source Mode 3 2 A 29 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel States 2 1 Encoding 0010 1100 5555 5555 Hex Code in Binary Mode A5 Encoding Source M
276. er counters and discusses their application This chapter also provides instructions for using the hardware watchdog timer WDT and describes the operation of the WDT during the idle and powerdown modes Chapter 11 Programmable Counter Array describes the PCA on chip peripheral and ex plains how to configure it for general purpose applications timers and counters and special ap plications programmable WDT and pulse width modulator Chapter 12 Serial I O Port describes the full duplex serial I O port and explains how to program it to communicate with external peripherals This chapter also discusses baud rate gen eration framing error detection multiprocessor communications and automatic address recog nition Chapter 13 Minimum Hardware Setup describes the basic requirements for operating the 82930A in a system It also discusses on chip and external clock sources and describes device resets including power on reset Chapter 14 Special Operating Modes provides an overview of the idle powerdown and on circuit emulation ONCE modes and describes how to enter and exit each mode This chapter also describes the power control PCON special function register and lists the status of the device pins during the special modes and reset Chapter 15 External Memory Interface describes the external memory signals and bus cy cles and provides examples of external memory design It provides waveform diagra
277. ernal bus Port 3 9 2 structure 9 3 Ports at power on 13 6 exiting idle mode 14 5 exiting powerdown mode 14 5 extended execution times 5 1 A 1 A 12 Power supply 13 2 Powerdown mode 2 5 14 1 14 5 14 6 accidental entry 14 4 entering 14 6 exiting 13 5 14 6 external bus 15 3 Program status word See PSW PSWI PSEN caution 13 6 description 15 2 idle mode 14 4 regions for asserting 4 6 PSW A 27 PSW PSWI 3 15 5 14 5 15 C 2 C 26 27 conditional jumps 5 13 effects of instructions on flags 5 15 PSWI 27 Pullups 9 7 ports 1 2 3 9 5 Pulse width measurements 10 10 PUSH instruction 3 13 5 10 A 23 R RCAP2H RCAP2L 3 16 10 2 12 12 C 3 C 28 RD 9 1 described 15 2 regions for asserting 4 6 RD1 0 configuration bits 4 6 Read modify write instructions 9 2 9 4 Register addressing 5 4 5 5 Register banks 3 2 3 8 accessing in memory address space 5 4 implementation 3 8 3 11 MCS 51 architecture 3 2 selection bits RS1 0 5 16 5 17 Register file 2 6 3 1 3 5 3 8 3 13 address space 3 2 addressing locations in 3 10 Index 5 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel and reset 13 6 MCS 51 architecture 3 4 naming registers 3 10 register types 3 10 Registers See Register addressing Register banks Register file rel A 3 Relative addressing 5 4 5 12 Reset 13 5 13 7 cold start 13 5 14 1 entering ONCE mode 14 7 exiting idle mode 14 5
278. ernal enable for timer 2 7 0 TF2 EXF2 RCLK TCLK 2 TR2 C T2 CP RL2 Bit Bit Number Mnemonic Function 7 TF2 Timer 2 Overflow Flag Set by timer 2 overflow Must be cleared by software TF2 is not set if RCLK 1 or TCLK 1 6 EXF2 Timer 2 External Flag If EXEN2 1 capture or reload caused by a negative transition on T2EX Sets EFX2 EXF2 does not cause an interrupt in up down counter mode DCEN 1 5 RCLK Receive Clock Bit Selects timer 2 overflow pulses RCLK 1 or timer 1 overflow pulses RCLK 0 as the baud rate generator for serial port modes 1 and 3 4 TCLK Transmit Clock Bit Selects timer 2 overflow pulses TCLK 1 or timer 1 overflow pulses TCLK 0 as the baud rate generator for serial port modes 1 and 3 3 EXEN2 Timer 2 External Enable Bit Setting EXEN2 causes a capture or reload to occur as a result of a negative transition on T2EX unless timer 2 is being used as the baud rate generator for the serial port Clearing EXEN2 causes timer 2 to ignore events at T2EX 2 TR2 Timer 2 Run Control Bit Setting this bit starts the timer 1 C T2 Timer 2 Counter Timer Select C T2 0 selects timer operation timer 2 counts the divided down system clock C T2 1 selects counter operation timer 2 counts negative transitions on external pin T2 0 CP RL2 Capture Reload Bit When set captures occur on negative transitions at T2EX if EXEN2 1 W
279. errun RXFIFO 8 22 intel USB OPERATING MODES B B Set up Set ACK hshk RXSTATx 0 End of transfer Done 4200 01 Figure 8 17 SIU Receive Operations for Non isochronous Data Details Part 8 23 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel USB data to RXFIFO RXCNTx 12 See RXFLGx 0 Table 5 9 amp Table 5 10 Toggle R SEQ Set R ERR RXSTATx 7 RXSTATx 1 Send and latch hshk status Set RXDx Generate interrupt if enabled SBI 2x 1 Done A4201 01 Figure 8 18 SIU Receive Operations for Non isochronous Data Details Parts C and D 8 3 2 2 SIU Receive Isochronous Data Figure 8 19 shows an overview of SIU operations for isochronous data ISO data packets are not retransmitted following a bad transmission Accordingly the SIU does not respond to the hand shake does not toggle the SEQ bit and does not generate an interrupt The second firmware rou 8 24 intel USB OPERATING MODES tine is a normal subroutine or an ISR and is initiated upon reception of the next SOF token The write marker and write pointer are adjusted automatically by the FIFO hardware ARM 1 or by the second firmware routine ARM 0 Figure 8 20 shows details of the SIU operations Valid OUT token RX endpoint enabled See Table 5 6 for RX endpoint enabled See note Endpoint prep
280. ers powerdown mode 14 4 intel SPECIAL OPERATING MODES 14 3 2 Exiting Idle Mode There are two ways to exit idle mode Generate an enabled interrupt Hardware clears the PCON register IDL bit which restores the clocks to the CPU Execution resumes with the interrupt service routine Upon completion of the interrupt service routine program execution resumes with the instruction immediately following the instruction that activated idle mode The general purpose flags GF1 and GFO in the PCON register may be used to indicate whether an interrupt occurred during normal operation or during idle mode When idle mode is exited by an interrupt the interrupt service routine may examine and e Reset the chip See section 13 4 Reset A logic high on the RST pin clears the IDL bit in the PCON register directly and asynchronously This restores the clocks to the CPU Program execution momentarily resumes with the instruction immediately following the instruction that activated the idle mode and may continue for a number of clock cycles before the internal reset algorithm takes control Reset initializes the 82930A and vectors the CPU to address FF 0000H NOTE During the time that execution resumes the internal RAM cannot be accessed however it is possible for the port pins to be accessed To avoid unexpected outputs at the port pins the instruction immediately following the instruction that activated idle mode should not wr
281. est Timer 0 Overflow 10 gt 8 Bits 8 Bits gt P1 2 ECI 1 1 CCON 7 Timer Counter Overflow I ECF CMOD 2 CMOD 7 CMOD 0 xn PCON 0 CCON 6 Idle Mode Run Control A4162 03 Figure 11 1 Programmable Counter Array 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Table 11 1 PCA Special Function Registers SFRs intel Mnemonic Description Address CL PCA Timer Counter These registers serve as a common 16 bit timer or S E9H CH event counter for the five compare capture modules Counts F4 12 S F9H Fog 4 timer 0 overflow or the external signal on P1 2 ECI as selected by CMOD In PWM mode CL operates as an 8 bit timer CCON PCA Timer Counter Control Register Contains the run control bit and S D8H the overflow flag for the PCA timer counter and interrupt flags for the five compare capture modules CMOD PCA Timer Counter Mode Register Contains bits for disabling the PCA S D9H timer counter during idle mode enabling the PCA watchdog timer module 4 selecting the timer counter input and enabling the PCA timer counter overflow interrupt CCAPOH PCA Module 0 Compare Capture Registers This register pair stores the S FAH CCAPOL comparison value or the captured value In the PWM mode the low byte S EAH register controls the duty cycle of the output waveform CCAP1H PCA Module 1 Compare Capture Registers This reg
282. et to OFFH respectively intel DECA Bytes States Encoding Hex Code in Operation DEC dir8 Bytes States Encoding Hex Code in Operation DEC Bytes States Encoding Hex Code in Operation DEC Rn INSTRUCTION SET REFERENCE Binary Mode Source Mode 1 1 1 1 0001 0100 Binary Mode Encoding Source Mode Encoding DEC lt A 1 Binary Mode Source Mode 2 2 2t 2t tlf this instruction addresses a port Px x 0 3 add 2 states 0001 0101 dir addr Binary Mode Encoding Source Mode Encoding DEC dir8 lt dir8 1 Binary Mode Source Mode 1 2 3 4 0001 011i Binary Mode Encoding Source Mode A5 Encoding DEC Ri lt Ri 1 55 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Bytes States Encoding Hex Code in Operation Binary Mode Source Mode 1 2 1 2 0001 irrr Binary Mode Encoding Source Mode A5 Encoding DEC Rn lt Rn 1 DEC dest src Function Description Flags Example Variations Decrement Decrements the specified variable at the destination operand by 1 2 or 4 An original value of 00H underflows to OFFH OV N Register 0 contains 7FH 01111111B After executing the instructi DEC RO 1 register 0 contain
283. ets the module s compare capture flag CCFx in the CCON register This generates an interrupt request if the corresponding interrupt enable bit ECCFx in the register is set Since hardware does not clear the compare capture flag when the interrupt is processed the user must clear the flag in software During the interrupt routine a new 16 bit compare value can be written to the compare capture registers CCAPxH CCAPxL NOTE To prevent an invalid match while updating these registers user software should write to CCAPXL first then CCAPxH A write to CCAPxL clears the bit disabling the compare function while a write to sets the bit re enabling the compare function 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Compare Capture PCA Timer Counter Module CH CL CCAPxL 8 Bits 8 Bits 8 dU 8 Bits Count Interrupt Request CCAPMx Mode Register Reset Write to CCAPxL X Don t Care 0 1 2 3 4 For software timer mode set MATx For high speed output mode set TOGx 4164 01 Write to Figure 11 3 PCA Software Timer and High speed Output Modes 11 3 4 High speed Output Mode The high speed output mode Figure 11 3 generates an output signal by toggling the module s I O pin CEXx when a match occurs This provides greater accuracy than togg
284. ex Code in Operation XRL A dir8 Bytes States Encoding Hex Code in Operation XRL A GRi Bytes States Encoding Hex Code in Operation XRL A Rn Bytes A 138 Binary Mode Source Mode 2 2 1 1 0110 0100 immed data Binary Mode Encoding Source Mode Encoding XRL A v data Binary Mode Source Mode 2 2 11 11 Tlf this instruction addresses port Px x 0 3 add 1 state 0110 0101 direct addr Binary Mode Encoding Source Mode Encoding XRL lt A dir8 Binary Mode Source Mode 1 2 2 3 0110 011i Binary Mode Encoding Source Mode A5 Encoding XRL A lt A v Ri Binary Mode Source Mode 1 2 intel States Encoding Hex Code in Operation XRL Rmd Rms Bytes States Encoding Hex Code in Operation 0110 drrr INSTRUCTION SET REFERENCE Binary Mode Encoding Source Mode A5 Encoding XRL A lt A Rn Binary Mode Source Mode 3 2 2 1 0110 1100 5555 5555 Binary Mode A5 Encoding Source Mode Encoding XRL Rma Rmd v Rms XRL WRjd WRjs Bytes States Encoding Hex Code in Operation XRL Rm data Bytes States Encoding Hex Code in Operation Binary Mode Source Mode 3 2 3 2 0110 1101 tttt TTTT
285. ex Code in Binary Mode Encoding Source Mode Encoding Operation CPL bit51 lt bit51 CPL CY Binary Mode Source Mode Bytes 1 1 States 1 1 Encoding 1011 0011 Hex Code in Binary Mode Encoding Source Mode Encoding Operation CPL CY CPL bit Binary Mode Source Mode Bytes 4 3 States 4t 3t A 52 intel Encoding INSTRUCTION SET REFERENCE tlf this instruction addresses a port Px x 0 3 add 2 states 1010 1001 1011 0 yyy dir addr Hex Code in Operation DAA Function Description Flags Example Binary Mode A5 Encoding Source Mode Encoding CPL bit lt Decimal adjust accumulator for addition Adjusts the 8 bit value in the accumulator that resulted from the earlier addition of two variables each in packed BCD format producing two 4 bit digits Any ADD or ADDC instruction may have been used to perform the addition If accumulator bits 3 0 are greater than nine XXXX1010 XXXX1111 or if the AC flag is set six is added to the accumulator producing the proper BCD digit in the low nibble This internal addition sets the CY flag if a carry out of the lowest 4 bits propagated through all higher bits but it does not clear the CY flag otherwise If the CY flag is now set or if the upper four bits now exceed nine 1010XXXX 1111XXXX these four bits are incremented by six producing
286. f Flag Set by hardware as Vcc rises above 3 V to indicate that power has been off or Vcc had fallen below 3 V and that on chip volatile memory is indeterminate Set or cleared by software 3 GF1 General Purpose Flag Set or cleared by software One use is to indicate whether an interrupt occurred during normal operation or during idle mode 2 GFO General Purpose Flag Set or cleared by software One use is to indicate whether an interrupt occurred during normal operation or during idle mode 1 PD Powerdown Mode Bit When set activates powerdown mode Cleared by hardware when an interrupt or reset occurs 0 IDL Idle Mode Bit When set activates idle mode Cleared by hardware when an interrupt or reset occurs If IDL PD are both set PD takes precedence C 25 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel PSW Address 5 Reset State 0000 0000B Program Status Word PSW contains bits that reflect the results of operations bits that select the register bank for registers RO R7 and two general purpose flags that are available to the user d 0 FO RS1 RSO OV UD Bit Bit Number Mnemonic Function 7 Carry Flag The carry flag is set by an addition instruction ADD ADDO if there is a carry out of the MSB It is set by a subtraction SUB SUBB or compare CMP if a borrow is needed for the MSB The car
287. f Transfer Cycle X X 0 0 No operation X 0 1 0 Write marker and write pointer managed by software they do not change automatically X 0 0 1 Write marker and write pointer managed by software they do not change automatically 0 1 0 1 Write marker advanced automatically FIF bit for corresponding data set is cleared 0 1 1 0 Write pointer reversed automatically FIF bits remain unchanged intel UNIVERSAL SERIAL BUS bad write set REV WP M TU iy bad write set REV WP RXFIFOx RXFIFOx Lo zi read set FFRO a m 2 E pe oo Wel Vea 4 FIF1 0 RXFIFOx mE w v lt lc ead set FFRO bad write set REV WP bad write set REV WP 4187 01 Figure 7 9 RXFIFO Operational Model 7 15 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Four registers are directly involved in the operation of the receive FIFO for endpoint x x 0 3 RXDATX the receive FIFO data register RXCNT the receive FIFO byte count register RXCON x the receive FIFO control register RXFLG x the receive FIFO flag register RXDATx Address See Table 7 11 x z 0 3 Reset See Table 7 11 Receive FIFO Data Register 7 0 RXDATx 7 0 Bit Bit Number Mnemonic Function 7 0 RXDATx 7 0 To write data to the RXFIFO the SIU writes to this register To read data
288. fferent internal memory addresses can access the same location in external memory For example if the 82930A 15 configured for 18 external address lines a write to location 03 6000H and a write to location FF 6000H accesses the same 18 bit external address 1 6000H because A16 1 and A17 1 for both internal addresses In other words regions 00 and FC map into the same 64 Kbyte region in external memory 4 4 2 1 RD1 0 00 18 External Address Bits The selection RD1 0 00 provides 18 external address bits A15 0 ports PO and P2 A16 from P3 7 RD A16 and A17 from P1 7 CEX4 A17 Bits A16 and A17 can select four 64 Kbyte regions of external memory for a total of 256 Kbytes top half of Figure 4 4 This is the largest possible external memory space Regions 00 and FC each having A17 16 00 map into the same 64 Kbyte region in external memory This duplication also occurs for regions 01 and FD 02 and FE and 03 and FF See Chapter 15 Example 1 RD1 0 00 18 bit Bus External Flash and RAM 4 4 2 2 RD1 0 z 01 17 External Address Bits The selection RD1 0 01 provides 17 external address bits A15 0 ports PO and P2 and A16 from P3 7 RD A16 Bit A16 can select two 64 Kbyte regions of external memory for a total of 128 Kbytes bottom half of Figure 4 4 Regions 00 02 FC and FE each having A16 0 map into the same 64 Kbyte region in external memory This duplication also occurs for regions 01 03 FD
289. flow flag in the TCON register and reloads TLO with the contents of THO which is preset by software When the interrupt re quest is serviced hardware clears TFO The reload leaves THO unchanged See section 10 5 1 Auto load Setup Example Interrupt Overflow Request 4111 02 Figure 10 3 Timer 0 1 Mode 2 Auto Reload 10 3 4 Mode 3 Two 8 bit Timers Mode 3 configures timer 0 such that registers TLO and THO operate as separate 8 bit timers Fig ure 10 4 This mode is provided for applications requiring an additional 8 bit timer or counter TLO uses the timer 0 control bits 0 and GATEO in TMOD and TRO and in TCON in the normal manner THO is locked into a timer function counting Fosc 12 and takes over use of the timer interrupt TF1 and run control bits Thus operation of timer 1 is restricted when timer 0 is in mode 3 See section 10 4 Timer 1 and section 10 4 4 3 Halt 10 5 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel 10 4 TIMER 1 Timer 1 functions as either a timer or event counter in three modes of operation Figures 10 2 and 10 3 show the logical configuration for modes 0 1 and 2 Timer 175 mode 3 is a hold count mode Timer 1 is controlled by the four high order bits of the TMOD register Figure 10 5 and bits 7 6 3 and 2 of the TCON register Figure 10 6 The TMOD register selects the method of timer gating GATEL
290. frequency 12 S CDH timer operation or an external input event counter operation TCON Timer 0 1 Control Register Contains the run control bits overflow flags S 88H interrupt flags and interrupt type control bits for timer 0 and timer 1 TMOD Timer 0 1 Mode Control Register Contains the mode select bits S 89H counter timer select bits and external control gate bits for timer 0 and timer 1 T2CON Timer 2 Control Register Contains the receive clock transmit clock and S C8H capture reload bits used to configure timer 2 Also contains the run control bit counter timer select bit overflow flag external flag and external enable for timer 2 T2MOD Timer 2 Mode Control Register Contains the timer 2 output enable and S C9H down count enable bits RCAP2L Timer 2 Reload Capture Registers RCAP2L RCAP2H Provide values S CAH RCAP2H to and receive values from the timer registers TL2 TH2 S CBH WDTRST Watchdog Timer Reset Register WDTRST Used to reset and enable S A6H the WDT XTAL1 Interrupt THx Tlx Request 8 Bits 8 Bits Tx 0 1 2 4121 02 Figure 10 1 Basic Logic of the Timer Counters 10 2 intel TIMER COUNTERS AND WATCHDOG TIMER control bit selects timer operation or counter operation by selecting the divided down system clock or external pin Tx as the source for the counted signal For timer ope
291. g Operation LCALL PC 3 SP SP 1 SP PC 7 0 SP SP 1 SP PC 15 8 PC addr 15 0 DD LCALL QWRj A 80 intel Bytes States Encoding Hex Code in Operation LJMP dest Function Description Flags Example LJMP addr16 Bytes States Encoding Hex Code in Operation INSTRUCTION SET REFERENCE Binary Mode Source Mode 3 2 9 8 1001 1001 tttt 0100 Binary Mode A5 Encoding Source Mode Encoding LCALL PC 3 SP lt SP 1 SP PC 7 0 SP lt SP 1 SP lt 15 8 PC lt WRj Long Jump Causes an unconditional branch to the specified address by loading the high and low bytes of the PC respectively with the second and third instruction bytes The destination may therefore be anywhere in the 64 Kbyte memory region where the next instruction is located OV N 2 The label is assigned to the instruction at program memory location 1234H After executing the instruction LJMP JMPADR at location 0123H the program counter contains 1234H Binary Mode Source Mode 3 3 5 5 0000 0010 Jladdrt5 addr8 addr7 adaro Binary Mode Encoding Source Mode Encoding LJMP lt addr 15 0 81 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel
292. g a capacitor between this lead and Vcc Asserting RST when the chip is in idle mode or powerdown mode returns the chip to normal operation RXD y o Receive Serial Data RXD sends and receives data in serial I O mode 0 and receives data in serial I O modes 1 2 and 3 P3 0 SOF Start of Frame This lead is asserted for eight states when an SOF token is received T1 0 Timer 1 0 External Clock Inputs When timer 1 0 operates as a counter a falling edge on the T1 0 lead increments the count P3 5 4 T2 y o Timer 2 Clock Input Output For the timer 2 capture mode this signal is the external clock input For the clock out mode it is the timer 2 clock output P1 0 T2EX Timer 2 External Input In timer 2 capture mode a falling edge initiates a capture of the timer 2 registers In auto reload mode a falling edge causes the timer 2 registers to be reloaded In the up down counter mode this signal determines the count direction 1 up 0 down P1 1 TXD Transmit Serial Data TXD outputs the shift clock in serial I O mode 0 and transmits serial data in serial I O modes 1 2 and 3 P3 1 Voc PWR Supply Voltage Connect this lead to the 5V supply voltage y o Voltage Plus USB plus voltage line interface y o Voltage Minus USB minus voltage line interface GND Circuit Ground Connect this lead to ground WR Write Write signal output to exter
293. g is allowed For 8 bit operands the result is 16 bits The most significant byte of the result is stored in the low byte of the word where the destination register resides The least significant byte is stored in the following byte register The OV flag is set if the product is greater than 255 OFFH otherwise it is cleared For 16 bit operands the result is 32 bits The most significant word is stored in the low word of the the dword where the destination register resides The least significant word is stored in the following word register In this operation the OV flag is set if the product is greater than OFFFFH otherwise it is cleared The CY flag is always cleared The N flag is set when the MSB of the result is set The Z flag is set when the result is zero Flags OV N 2 0 Register R1 contains 80 or 10010000B register RO contains 160 or 10010000B After executing the instruction MUL R1 RO which gives the product 12 800 3200H register RO contains 32H 00110010B register R1 contains the OV flag is set and the CY flag is clear MUL Rmd Rms Binary Mode Source Mode Bytes 3 2 States 6 5 Encoding 1010 1100 5555 5555 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MUL 8 bit operands if lt dest gt md 0 2 4 14 lt high byte of the X Rms Rmd 1 lt low byte of the X Rms if dest md 1 3 5 15 Rmd 1
294. gions except 01 For external memory accesses selects the number of wait states for RD and PSEN WSA1 WSAO 0 0 Inserts 3 wait states for all regions except 01 0 1 Inserts 2 wait states for all regions except 01 1 0 Inserts 1 wait state for all regions except 01 1 1 Zero wait states for all regions except 01 4 XALE Extend ALE Set this bit for ALE Clear this bit for ALE 3Tos adds one external wait state 3 2 RD1 0 Memory Signal Selection RD1 0 bit codes specify an 18 bit 17 bit or 16 bit external address bus and address ranges for RD WR and PSEN See Table 4 2 1 PAGE Page Mode Select Clear this bit for page mode enabled with A15 8 D7 0 on P2 and A7 0 on PO Set this bit for page mode disabled with A15 8 on P2 and A7 0 D7 0 on PO 0 SRC Source Mode Binary Mode Select Clear this bit for binary mode opcodes compatible with MCS 51 microcontrollers Set this bit for source mode NOTES 1 2 Configuration bytes UCONFIGO and UCONFIG1 define the configuration of the 82930A Address UCONFIGO is the lowest byte of the 8 byte configuration array When EA 0 the 82930A obtains configuration information from a configuration array located at the highest addresses implemented in external application memory using addresses FF FFF8H FF FFF9H The physical location of the configuration array in external memory depends on the size and decode arrangement of t
295. gister file see section 3 3 82930A Register File 2 The MCS 251 architecture supports SFRs in locations S 000H S 1FFH however in the 82930A all SFRs in the range S 080H S 0FFH 5 3 1 5 Displacement Several move instructions use displacement addressing to move bytes or words from a source to a destination Sixteen bit displacement addressing 9 WRj dis16 accesses indirectly the lowest 64 Kbytes in memory The base address can be in any word register WRj The instruction contains a 16 bit signed offset which is added to the base address Only the lowest 16 bits of the sum are used to compute the operand address If the sum of the base address and a positive offset exceeds FFFFH the computed address wraps around within region 00 e g FOOOH 2005H becomes 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel 1005H Similarly if the sum of the base address and a negative offset is less than zero the com puted address wraps around the top of region 00 e g 2005 F000H becomes 1005 Twenty four bit displacement addressing DRk dis24 accesses indirectly the entire 16 Mbyte address space The base address must be in DRO DR4 DR24 DR28 DR56 or DR60 The upper byte in the dword register must be zero The instruction contains a 16 bit signed offset which is added to the base address 5 3 2 Arithmetic Instructions The set of arithmetic instructions is greatly expanded in the MCS 251 architec
296. gs Example INSTRUCTION SET REFERENCE If the Z flag is set OR if the the N flag and the OV flag have different values branch to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice OV N 2 The instruction JSLE LABEL1 causes program execution to continue at LABEL 1 if the 2 flag is set OR if the the N flag and the OV flag have different values Binary Mode Source Mode Not Taken Taken Not Taken Taken 3 3 2 2 2 5 1 4 0000 1000 rel addr Binary Mode A5 Encoding Source Mode Encoding JSLE PC 2 IF 2 1 OR OV THEN rel Jump if accumulator zero If all bits of the accumulator are clear zero branch to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice The accumulator is not modified 2 accumulator contains 01H After executing the instruction sequence JZ LABEL 1 DECA JZ LABEL2 the accumulator contains 00H and program execution continues at label LABEL2 Source Mode Not Taken Taken Binary Mode Not Taken Ta
297. h destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice Flags 2 A Example The instruction JLE LABEL1 causes program execution to continue at LABEL1 if the Z flag or the CY flag is set Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes 3 3 2 2 States 2 5 1 4 Encoding 0010 1000 rel addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation JLE PC PC 2 2 1 OR CY 1 THEN PC lt PC rel JMP A DPTR Function Jump indirect Description Add the 8 bit unsigned contents of the accumulator with the 16 bit data pointer and load the resulting sum into the lower 16 bits of the program counter This is the address for subsequent instruction fetches The contents of the accumulator and the data pointer are not affected Flags A 72 CY AC OV N Z intel Example Bytes States Encoding Hex Code in Operation JNB bit51 rel JNB bit rel Function Description Flags INSTRUCTION SET REFERENCE The accumulator contains an even number from 0 to 6 The following sequence of instruc tions branch to one of four AJMP instructions in a jump table starting at JMP_TBL MOV DPTR JMP_TBL JMP A DPTR 2 LABELO JMESEBE AJMP LABEL1 AJMP LABEL2 AJMP LABEL3 If the accumulator contains 04H at the start this s
298. he MCS 51 microcontroller performance will be better with the 82930A running in binary mode Object code written for the MCS 51 microcontroller runs faster on the 82930A However if most of the code is rewritten using the MCS 251 instruction set performance will be better with the 82930A running in source mode In this case the 82930A can run significantly fast er than the MCS 51 microcontroller See Chapter 4 Device Configuration for a discussion of binary mode and source mode 82930A microcontrollers store both code and data in a single linear 16 Mbyte memory space The 82930A can address up to 256 Kbytes of external memory The special function registers SFRs and the register file have separate address spaces See Chapter 3 82930A Memory Par titions for a description of the address modes 2 5 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel 2 3 MCS 251 MICROCONTROLLER CORE The MCS 251 microcontroller core contains the CPU the clock and reset unit the interrupt han dler the bus interface and the peripheral interface The CPU contains the instruction sequencer ALU register file and data memory interface 2 3 4 CPU Figure 2 4 is a functional block diagram of the CPU central processor unit The 82930 fetches instructions from on chip code memory two bytes at a time or from external memory in single bytes The instructions are sent over the 16 bit code bus to the execution unit You can c
299. he SFR memory map in Table 3 4 gives the addresses and reset values of the 82930A SFR s SFR addresses are preceded by S to differentiate them from addresses in the memory space Shaded locations in Table 3 4 and locations below S 80H and above S FFH are unimplemented i e no register exists If an instruction attempts to write to an unimplemented SFR location the instruction executes but nothing is actually written If an unimplemented SFR location is read it returns an unspecified value Descriptive tables for the SFRs are presented in alphabetical order in Appendix C NOTE SFRs may be accessed only as bytes they may not be accessed as words or dwords 3 13 F8 FO E8 EO D8 DO C8 co B8 A8 0 98 90 88 80 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Table 3 4 82930A SFR Map and Reset Values In tel 3 14 RXSTATO CH 2 0 000 00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX B RXSTAT1 RXSTAT2 RXSTAT3 RXCNTO RXCNT1 RXCNT2 RXCNT3 F7 00000000 0 000 0 000 0 000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX TXSTATO CL CCAPOL CCAP1L CCAP2L CCAP3L CCAP4L EF 0 000 00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ACC TXSTAT1 TXSTAT2 TXSTAT3 RXFLGO RXFLG1 RXFLG2 RXFLG3 EZ 00000000 0
300. he external memory system see Table 4 1 and Figure 4 1 Figure 4 2 User Configuration Byte 0 UCONFIGO 4 4 intel DEVICE CONFIGURATION UCONFIG1 Address FF FFF9H 2 1 7 0 EN INR WSBis WSBO Mais Mni Function 7 5 Reserved write a 1 to these bits 4 INTR Interrupt Stack Mode If this bit is set interrupts push 4 bytes onto the stack the 3 bytes of the PC and PSW1 If this bit is clear interrupts push the 2 lower bytes of the PC onto the stack See Interrupt Stack Mode INTR Reserved write a 1 to this bit 2 1 WSB1 0 External Wait State B Region 01 WSB1 WSBO 0 0 Inserts 3 wait states for region 01 0 1 Inserts 2 wait states for region 01 1 0 Inserts 1 wait state for region 01 1 1 Zero wait states for region 01 0 Reserved write a 1 to this bit NOTES 1 Configuration bytes UCONFIGO and UCONFIG1 define the configuration of the 82930A 2 Address UCONF IG is the 2nd lowest byte of a configuration array When EA 0 the 82930A obtains configuration information from a configuration array located at the highest addresses implemented in external application memory using addresses FF FFF8H FF FFF9H The physical location of the configuration array in external memory depends on the size and decode arrangement of the external memory system see Table 4 1 Figure 4 3 User Configuration Byte 1 UCONFIG1 4 5
301. he following modem settings 14400 N 8 1 If your modem does not support 14 4K baud the system provides auto configuration support for 1200 baud through 14 4K baud modems To access the BBS dial the telephone number and respond to the system prompts During your first session the system asks you to register with the system operator by entering your name and location The system operator will then set up your access account within 24 hours At that time you can access the files on the BBS For a listing of files call the FaxBack service and order cat alog 6 the BBS catalog If you encounter any difficulty accessing our high speed modem try our dedicated 2400 baud modem see page 1 7 Use the following modem settings 2400baud N 8 1 1 4 8 How to Find the Latest ADBUILDER Files and Hypertext Manuals and Data Sheets on the BBS The latest ApBUILDER files and hypertext manuals and data sheets are available first from the BBS To access the files 1 Select F from the BBS Main menu Select L from the Intel Apps Files menu The BBS displays the list of all area levels and prompts for the area number Select 25 to choose the ApBUILDER Hypertext area Area level 25 has four sublevels 1 General 2 196 Files 3 186 Files and 4 8051 Files Si ASS pan 159 6 Select 1 to find the latest ApBUILDER files or the number of the appropriate product family sublevel to find the hypertext manuals and data sheet
302. he timer operates an as an up counter or as an up down counter as determined by the down counter enable bit DCEN At device reset DCEN is cleared so in the auto reload mode timer 2 defaults to operation as an up counter 10 6 2 1 Up Counter Operation When DCEN 0 timer 2 operates as an up counter Figure 10 8 The external enable bit EXEN2 in the T2CON register provides two options Figure 10 12 If EXEN2 0 timer 2 counts up to FFFFH and sets the TF2 overflow flag The overflow condition loads the 16 bit value in the re load capture registers RCAP2H RCAP2L into the timer registers TH2 TL2 The values in RCAP2H and RCAP2L are preset by software If EXEN2 1 the timer registers are reloaded by either a timer overflow or a high to low tran sition at external input T2EX This transition also sets the EXF2 bit in the T2CON register Either TF2 or EXE2 bit can generate a timer 2 interrupt request XTAL1 J TH2 8 Bits TL2 Overflow 8 Bits Interrupt Request EXEN2 4115 02 Figure 10 8 Timer 2 Auto Reload Mode DCEN 0 10 12 intel TIMER COUNTERS AND WATCHDOG TIMER 10 6 2 2 Up Down Counter Operation When DCEN 1 timer 2 operates as an up down counter Figure 10 9 External pin T2EX con trols the direction of the count Table 10 2 When T2EX is high timer 2 counts up The timer overflow occurs at FFFFH which sets the timer 2 overflow flag TF2 and generates
303. hen cleared auto reloads occur on timer 2 overflows or negative transitions at T2EX if EXEN2 1 The CP RL2 bit is ignored and timer 2 forced to auto reload on timer 2 overflow if RCLK 1 or TCLK 1 C 42 intel REGISTERS T2MOD Address S C9H Reset State XX00B Timer 2 Mode Control Register Contains the timer 2 down count enable and clock out enable bits for timer 2 7 0 I 2 Function 7 2 Reserved Values read from these bits are indeterminate Write zeros to these bits 1 2 Timer 2 Output Enable Bit In the timer 2 clock out mode connects the programmable clock output to external pin T2 0 DCEN Down Count Enable Bit Configures timer 2 as an up down counter C 43 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel TCON Address 5 88 Reset State 0000 0000B Timer Counter Control Register Contains the overflow and external interrupt flags and the run control and interrupt transition select bits for timer 0 and timer 1 7 0 TF1 TR1 TFO TRO IE1 IT1 IEO ITO Bit Bit Function Number Mnemonic unctio 7 TF1 Timer 1 Overflow Flag Set by hardware when the timer 1 register overflows Cleared by hardware when the processor vectors to the interrupt routine 6 TR1 Timer 1 Run Control Bit Set cleared by software to tu
304. hree ensures at least one more instruction executes before the system vectors to additional interrupts if the in struction in progress is a RETI or any write to IEO IE1 IPHO IPHI IPLO or IPL1 The complete polling cycle is repeated each four state times 6 8 2 5 Interrupt Vector Cycle When an interrupt vector cycle is initiated the CPU breaks the instruction stream sequence re solves all instruction pipeline decisions and pushes multiple program counter PC bytes onto the stack The CPU then reloads the PC with a start address for the appropriate ISR The number of bytes pushed to the stack depends upon the INTR bit in the UCONFIGI Figure 4 3 configura tion byte The complete sample poll request and context switch vector sequence is illustrated in the interrupt latency timing diagram see Figure 6 10 NOTE If the interrupt flag for a level triggered external interrupt is set but denied for one of the above conditions and is clear when the blocking condition is removed then the denied interrupt is ignored In other words blocked interrupt requests are not buffered for retention intel INTERRUPTS 6 8 3 ISRs in Process ISR execution proceeds until the RETI instruction is encountered The RETI instruction informs the processor the interrupt routine is completed The RETI instruction in the ISR pops PC address bytes off the stack as well as PSW1 for INTR 1 and execution resumes at the suspended in struction stream NOT
305. ial Bus Manager SBM see Chapter 7 Universal Serial Bus which manages the USB data that is received and transmitted by the 82930A 2 4 3 Timer Counters and Watchdog Timer The timer counter unit has three timer counters which can be clocked by the oscillator for timer operation or by an external input for counter operation You can set up an 8 bit 13 bit or 16 bit timer counter and you can program them for special applications such as capturing the time of an event on an external pin outputting a programmable clock signal on an external pin or gen erating a baud rate for the serial I O port Timer counter events can generate interrupt requests The watchdog timer is a circuit that automatically resets the 82930A in the event of a hardware or software upset When enabled by software the watchdog timer begins running and unless software intervenes the timer reaches a maximum count and initiates a chip reset In normal op eration software periodically clears the timer register to prevent the reset If an upset occurs and software fails to clear the timer the resulting chip reset disables the timer and returns the system to a known state The watchdog and the timer counters are described in Chapter 10 Tim er Counters and WatchDog Timer 2 4 3 Programmable Counter Array The programmable counter array PCA has its own timer and five capture compare modules that perform several functions capturing storing th
306. ial Port on the 83 51 415 83 51 PCA Cookbook AP 476 How to Implement Serial Communication Using Intel MCS9 51 Microcontrollers 1 4 CUSTOMER SERVICE Order Number 203830 Order Number 270032 Order Number 270068 Order Number 270622 Order Number 270490 Order Number 270609 Order Number 272319 This section provides telephone numbers and describes various customer services Technical Support U S and Canada 800 628 8686 916 356 7599 and 916 356 6100 fax Customer Training U S and Canada 800 234 8806 Product Literature 800 548 4725 U S and Canada 708 296 9333 U S from overseas 44 0 1793 431155 Europe U K 44 0 1793 421333 Germany 44 0 1793 421777 France 81 0 120 47 88 32 Japan fax only FaxBack Service 1 6 intel GUIDE TO THIS MANUAL 800 525 3019 U S and Canada 44 0 1793 496646 Europe 503 264 6835 U S Canada Japan Asia Pacific Application Bulletin Board System 800 897 2536 U S and Canada 916 356 3600 U S Canada Japan Asia Pacific up to 19 2 Kbaud line 916 356 7209 U S Canada Japan Asia Pacific dedicated 2400 baud line 44 0 1793 496340 Europe Intel provides 24 hour automated technical support through our FaxBack service and our central ized Intel Application Bulletin Board System BBS The FaxBack service is a simple to use in formation system that lets you order technical documents b
307. igures depict the bus cycle waveforms in idealized form and do not provide precise timing information This section does not cover wait states see section 15 3 Ex ternal Bus Cycles with Wait States For configuration byte bus cycles see section 15 4 Con figuration Byte Bus Cycles An inactive external bus exists when the 82930A is not executing external bus cycles This oc curs under any of the three following conditions Bus Idle The chip is in normal operating mode but no external bus cycles are executing The chip is in idle mode The chip is in powerdown mode 15 2 1 Bus Cycle Definitions Table 15 2 lists the types of external bus cycles It also shows the activity on the bus for nonpage mode and page mode bus cycles with no wait states There are three types of nonpage mode bus cycles code read data read and data write There are four types of page mode bus cycles code read page miss code read page hit data read and data write The data read and data write cy cles are the same for page mode and nonpage mode except the multiplexing of D7 0 on ports 0 and 2 Table 15 2 Bus Cycle Definitions No Wait States Bus Activity Mode Bus Cycle State 1 State 2 State 3 Code Read ALE RD PSEN code in et Data Read 2 ALE RD PSEN data in Data Write 2 ALE WR WR high data out Code Read Page Miss ALE RD PSEN code in Page Code Read Hit 3
308. imer 2 You may select either or both timer s to generate the baud rate s for the transmitter and or the receiv er 12 6 3 1 Timer 1 Generated Baud Rates Modes 1 and 3 Timer 1 is the default baud rate generator for the transmitter and the receiver in modes 1 and 3 The baud rate is determined by the timer 1 overflow rate and the value of SMOD as shown in the following formula SMOD Timer 1 Overflow Rate Serial Modes 1 and 3 Baud Rate 2 45 12 6 3 2 Selecting Timer 1 as the Baud Rate Generator To select timer 1 as the baud rate generator 12 10 intel SERIAL I O PORT Disable the timer interrupt by clearing the ETI bit in the IEO register Figure 6 3 Configure timer 1 as a timer or an event counter set or clear the C T bit in the TMOD register Figure 10 5 Select timer mode 0 3 by programming the M1 MO bits in the TMOD register In most applications timer 1 is configured as a timer in auto reload mode high nibble of TMOD 0010B The resulting baud rate is defined by the following expression SMOD Fosc Serial Modes 1 and 3 Baud Rate 2 x 82 x 12 256 THT Timer 1 can generate very low baud rates with the following setup Enable the timer 1 interrupt by setting the bit in the IE register e Configure timer 1 to run as a 16 bit timer high nibble of TMOD 0001B Use the timer 1 interrupt to initiate a 16 bit software reload Table 12 4 lists commonly used baud rates
309. inary Mode A5 Encoding Source Mode Encoding Operation MOV Rm DRk dis MOV WRj DRk dis24 Binary Mode Source Mode Bytes 5 4 States 8 7 Encoding 0110 1001 tttt uuuu dis hi dis low Hex Code in Binary Mode A5 Encoding Source Mode Encoding A 95 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Operation MOV lt DRk dis MOV WRj dis16 Rm Binary Mode Source Mode Bytes States Encoding 0001 1001 ttt 5555 dishi Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV WRj dis Rm MOV QWhRj dis16 WRj Binary Mode Source Mode Bytes States Encoding 0101 1001 tttt TTTT dis hi dis low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV WRj dis lt WRj MOV DRk dis24 Rm Binary Mode Source Mode Bytes States Encoding 0011 1001 uuuu 5555 dis hi dis low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV DRK dis Rm MOV DRk dis24 WRj A 96 intel INSTRUCTION SET REFERENCE Binary Mode Source Mode Bytes 5 4 States 8 7 Encoding 0111 1001 uuuu tttt dis hi dis low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV DRk dis lt WRj
310. ing 1001 1111 uuuu UUUU Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation SUB DRkd DRkd DRks SUB Rm data Binary Mode Source Mode Bytes 4 3 A 128 intel INSTRUCTION SET REFERENCE States 3 2 Encoding 1001 1110 5555 0000 data Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation SUB Rm Rm data SUB WRij data16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding 1001 1110 tttt 0100 data hi data low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation SUB WRJ lt WRj data16 SUB DRk data16 Binary Mode Source Mode Bytes 5 4 States 6 5 Encoding 1001 1110 uuuu 1000 data hi data low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation SUB DRk DRk data16 SUB 8 Binary Mode Source Mode Bytes 4 3 States 3t 21 tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 1001 1110 5555 0001 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation SUB A 129 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Rm lt Rm dir8 intel SUB
311. instruction 5 8 A 15 ADDC instruction 5 8 15 addrll 5 12 A 3 addrl6 5 12 A 3 addr24 5 12 A 3 Address spaces See Memory space SFRs Register file External memory Compatibility Addresses internal vs external 4 7 Addressing modes 3 5 5 4 See also Data instructions Bit instructions Control instructions AJMP instruction 5 13 A 25 ALE caution 13 6 description 15 2 extended 4 10 following reset 13 6 idle mode 14 4 ANL instruction 5 9 5 10 for bits A 24 ANL instruction 5 10 for bits A 24 INDEX Arithmetic instructions 5 8 5 9 table of A 15 A 16 A 17 B B register 3 13 C 6 as SER 3 15 C 2 in register file 3 11 Base address 5 4 Baud rate See Serial I O port Timer 1 Timer 2 Binary and source modes 2 5 4 11 4 13 5 1 opcode maps 4 11 selection guidelines 2 5 4 12 Bit address addressing modes 5 11 definition A 3 examples 5 10 Bitinstructions 5 10 5 11 addressing modes 5 4 5 10 bit51 5 10 A 3 Broadcast address See Serial I O port C Call instructions 5 14 Capacitors bypass 13 2 CCAPIL CCAPAL 3 17 C 4 C 7 CCAPM 1 4 3 16 11 16 4 C 8 interrupts 6 5 CCON 3 16 11 14 C 4 C 9 Ceramic resonator 13 3 4 0 9 1 CH CL 3 17 C 4 C 10 CJNE instruction 26 Clock 2 7 external 13 4 external source 13 2 idle and powerdown modes 14 5 idle mode 14 4 powerdown mode 14 5 14 6 sources 13 2 CLR instruction 5 9 5 10
312. instructions operate on bytes and words that are accessed via several addressing modes Table A 23 A byte register word register or the accumulator can be logically combined with a register immediate data or data that is addressed directly or indirectly These instructions affect the Z and N flags In addition to the CLR clear CPL complement SWAP swap and four rotate instructions that operate on the accumulator 82930A microcontroller has three shift commands for byte and word registers SLL Shift Left Logical shifts the register one bit left and replaces the LSB with 0 SRL Shift Right Logical shifts the register one bit right and replaces the MSB with 0 SRA Shift Right Arithmetic shifts the register one bit right the MSB is unchanged 5 3 4 Data Transfer Instructions Data transfer instructions copy data from one register or memory location to another These in structions include the move instructions Table A 24 and the exchange push and pop instruc tions Table A 25 Instructions that move only a single bit are listed with the other bit instructions in Table A 26 MOV Move is the most versatile instruction and its addressing modes are expanded in the 82930A architecture MOV can transfer a byte word or dword between any two registers or be tween a register and any location in the address space The MOVX Move External instruction moves a byte from external memory to the accumulator or from the accumul
313. ion 16 bits x 16 bits 32 bits e eight bit division 8 bits 8 bits 16 bits 8 bit quotient 8 bit remainder sixteen bit division 16 bits 16 bits 32 bits 16 bit quotient 16 bit remainder These instructions operate on pairs of byte registers Rmd Rms word registers WRjd WRjs or the accumulator and B register A B For 8 bit register multiplies the result is stored in the word register that contains the first operand register For example the product from an instruction MUL R3 R8 is stored in WR2 Similarly for 16 bit multiplies the result is stored in the dword register that contains the first operand register For example the product from the instruction MUL WR6 WR18 is stored in DR4 5 8 intel INSTRUCTIONS AND ADDRESSING For 8 bit divides the operands are byte registers The result is stored in the word register that con tains the first operand register The quotient is stored in the lower byte and the remainder is stored in the higher byte A 16 bit divide is similar The first operand is a word register and the result is stored in the double word register that contains that word register If the second operand the di visor is zero the overflow flag OV is set and the other bits in PSW and PSW1 are meaningless 5 3 3 Logical Instructions 829304 architecture provides a set of instructions that perform logical operations The ANL ORL and XRL logical AND logical OR and logical exclusive OR
314. ion Hardware clears this bit when the flush operation is completed 6 5 Reserved Values read from these bits are indeterminate Write zeros to these bits 4 FFRC FIFO Read Complete Software sets this bit to signal when a data set read is complete Setting this bit clears the FIF bit corresponding to the data set that was just read Hardware clears this bit after the FIF bit is cleared 3 ISO Isochronous Data Type Software sets this bit to indicate that RXFIFOx is programmed to receive isochronous data and to set up the USB Interface to handle an isochronous data transfer This bit must be cleared by software 2 ARM Auto Receive Management If software sets this bit the write pointer and write marker are adjusted automatically based on the following conditions ISO RX Status Write Pointer Write Marker X ACK Unchanged Advanced 0 Not ACK Reversed Unchanged 1 Not ACK Unchanged Advanced When this bit is set setting REV WP or ADV WM has no effect Software can read and write this blt hardware neither clears nor sets this bit 1 ADV WM Advance Write Marker Software sets this bit to advance the write marker to the origin of the next data set Advancing the write marker is used for back to back receptions Hardware clears this bit after the write marker is advanced Setting this bit is effective only when the REV WP ARM and CLR bits are clear 0 REV WP Reverse Write Pointer Software sets this bit to return
315. ion 13 4 4 Power on Reset The RST pin has a Schmitt trigger input and a pulldown resistor 13 4 2 WDT Initiated Resets Expiration of the hardware WDT overflow or the PCA WDT comparison match generates a reset signal WDT initiated resets have the same effect as an external reset See section 10 7 Watchdog Timer and section 11 3 5 PCA Watchdog Timer Mode 13 5 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel 13 4 3 Reset Operation When a reset is initiated whether externally or by a WDT the port pins are immediately forced to their reset condition as a fail safe precaution whether the clock is running or not The external reset signal and the WDT initiated reset signals are combined internally For an ex ternal reset the voltage on the RST pin must be held high for 64Tosc For WDT initiated resets 5 bit counter in the reset logic maintains the signal for the required 64Tosc The CPU checks for the presence of the combined reset signal every 270 When a reset is de tected the CPU responds by triggering the internal reset routine The reset routine loads the SFR s with their reset values see Table 3 4 Reset does not affect on chip data RAM or the register file However following a cold start reset these are indeterminate because V has fallen too low has been off Following a synchronizing operation and the configuration fetch the CPU vectors to address FF 0000 Figure 13 5 shows th
316. ions 00 0020 00 041 3 8 intel 82930A MEMORY PARTITIONS Byte Registers Note R10 B R11 Ro 5 fro n2 Ro As 87 Word Registers Register File 31 23 Banks 0 3 DR24 DR28 DR16 DR20 DR12 DR A4099 01 Figure 3 6 The Register File 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Register File Memory Address Space FF FFFFH PSW bits RS1 0 select one bank to be accessed via the register file Banks 0 3 accessible in memory address space Banks 0 3 A4215 01 Figure 3 7 Register File Locations 0 7 Table 3 2 Register Bank Selection PSW Selection Bits Bank Address Range RS1 RSO Bank 0 00H 07H 0 0 Bank 1 08 0 1 2 10 17 1 0 Bank 3 18H 1FH 1 1 3 3 4 Byte Word and Dword Registers Depending on its location in the register file a register is addressable as a byte a word and or a dword as shown on the right side of Figure 3 6 A register is named for its lowest numbered byte location For example is the byte register consisting of location 4 WRA is the word register consisting of registers 4 and 5 DRA is the dword register consisting of registers 4 7 Locations RO R 15 are addressable as bytes words or dwords Locations 16 31 are addressable only as words or dwords Location
317. ions by a logical one written to the latch For additional electrical information refer to the current 82930A datasheet NOTE Port latch values change near the end of read modify write instruction cycles Output buffers and therefore the pin state update early in the instruction after the read modify write instruction cycle Logical zero to one transitions in port 1 port 2 and port 3 utilize an additional pullup to aid this logic transition see Figure 9 4 This increases switch speed The extra pullup briefly sources 100 times normal internal circuit current The internal pullups are field effect transistors rather than linear resistors Pullups consist of three p channel FET pFET devices A pFET is on when the gate senses logical zero and off when the gate senses logical one pFET 1 is turned on for two oscillator periods immediately after a zero to one transition in the port latch A logic one at the port pin turns on pFET 3 a weak pullup through the inverter This inverter and pFET pair form a latch to drive logic one 2 is a very weak pullup switched on whenever the associated nFET is switched off This is traditional CMOS switch convention Current strengths are 1 10 that of pFET 3 9 5 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel 2 Osc Periods Voc Voc Voc Port Q From Port Latch Input Data Read Port Pin A2242 01 Figure 9 4 Internal Pullup Configurations 97 PORT LOAD
318. iption If the specified bit is one branch to the specified address otherwise proceed with the next A 68 instruction The bit is not cleared if it is already a zero The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC after incre menting the PC to the first byte of the next instruction Note When this instruction is used to test an output pin the value used as the original data is read from the output data latch not the input pin intel INSTRUCTION SET REFERENCE Flags 2 accumulator contains 56H 01010110 After the instruction sequence JBC ACC 3 LABEL 1 JBC ACC 2 LABEL2 the accumulator contains 52H 01010010B and program execution continues at label LABEL2 Variations JBC bit51 rel Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes 3 3 3 3 States 4 7 4 7 Encoding 0001 0000 bitaddr Hex Code in Binary Mode Encoding Source Mode Encoding Operation JBC PC 3 IF bitb1 1 THEN 0151 0 lt rel JBC bit rel Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes 5 5 4 4 States 4 7 3 6 Encoding 1010 1001 0001 0 diectaddr rel adar Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation JBC lt 3 IF bitb1 1 THEN
319. irect addr direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ORL ORL WRj dir16 Bytes States Rm lt Rm V dir16 Binary Mode Source Mode 5 4 4 3 A 111 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Encoding 0100 1110 tttt 0111 direct addr direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ORL WRj lt WRJ V dir16 ORL Rm WRj Binary Mode Source Mode Bytes 4 3 States 3 2 Encoding 0100 1110 tttt 1001 ssss 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ORL Rm lt Rm V WRj ORL Rm DRk Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 0100 1110 uuuu 1011 5555 0000 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ORL Rm lt Rm V DRk ORL CY lt src bit gt Function Description A 112 Logical OR for bit variables Sets the CY flag if the Boolean value is a logical 1 leaves the CY flag in its current state otherwise A slash preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value but the source bit itself is not affected intel INSTRUCTION SET REFERENCE Flag
320. is at program memory location 0123H After executing the instruction AJMP JMPADR at location 0345H the PC contains 0123H Binary Mode Source Mode 2 2 3 3 a10 a9 a8 0 0001 a7 a6 a5a4 a3 a2 a1 a0 Binary Mode Encoding Source Mode Encoding AJMP PC 2 10 0 page address ANL lt dest gt lt src gt Function Description Flags Logical AND Performs the bitwise logical AND A operation between the specified variables and stores the results in the destination variable The two operands allow 10 addressing mode combinations When the destination is the register or accumulator the source can use register direct register indirect or immediate addressing when the destination is a direct address the source can be the accumulator or immediate data Note When this instruction is used to modify an output port the value used as the original port data is read from the output data latch not the input pins CY AC OV 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Example Variations ANL dir8 A Bytes States Encoding Hex Code in Operation ANL dir8 data Bytes States Encoding Hex Code in Operation ANL A data Bytes A 36 Register 1 contains 11000011B and register 0 contains 55H 01010101B After executing the instruction ANL R1 RO register 1 contains
321. iscard data hshk status R ERR Setup ACK hshk lt lt Send hshk amp update RX status Interrupt enabled 5 Generate RXD interrupt no hshk status R VOID Done Note This branch should never be allowed under proper setup operation dictated by firmware A4266 01 Figure 8 25 SIU Operations for a SETUP Token 8 32 intel USB OPERATING MODES Table 8 11 Truth Table For SETUP Token Enable STL RX RX IE CTL EP RX Enable For SETUP Token 0 0 0 No 0 1 0 No 1 0 0 No 1 1 0 No X X 1 Yes always 8 5 SIU OPERATIONS FOR START OF FRAME SOF TOKEN Figure 8 26 illustrates the SIU operations for a start of frame SOF token The host issues an SOF token at a nominal rate of once every 1 00 ms An SOF token is valid if the PID is good The SOF token is not endpoint specific it should be received by every node on the bus 8 33 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Valid SOF token Set RxSOF bit Write SOF registers End of transfer y SOFH 6 SOFH SOFL Clear bit SOFH 7 Clear SFACK bit Set SFACK SOF token received SOFH 7 without error Generate SOF pulse by asserting SOF pin Done 4267 01 Figure 8 26 SIU Operations for SOF Token 8 34 intel Input Output Ports intel CHAPTER 9 INPUT OUTPUT PORTS 9 1 INPUT OUTPUT PORT OVERVIEW Th
322. ischarge ESD devices D1 and D2 which are diodes parasitic to the FETs They serve as clamps to Voc and Feedback resistor in the inverter circuit formed from paralleled n and p channel FETs permits the PD bit in the PCON register Figure 14 1 to disable the clock during powerdown Noise spikes at XTAL1 and XTAL2 can disrupt microcontroller timing To minimize coupling between other digital circuits and the oscillator locate the crystal and the capacitors near the chip and connect to XTAL1 XTAL2 and V with short direct traces To further reduce the effects of noise place guard rings around the oscillator circuitry and ground the metal crystal case For a more in depth discussion of crystal specifications ceramic resonators and the selection of and C2 see Applications Note AP 155 Oscillators for Microcontrollers in the Embedded Applications handbook 13 3 2 On chip Oscillator Ceramic Resonator In cost sensitive applications you may choose a ceramic resonator instead of a crystal Ceramic resonator applications may require slightly different capacitor values and circuit configuration Consult the manufacturer s data sheet for specific information To Internal Timing Circuit Internal lt E g Quartz Crystal or Ceramic Resonator 4143 03 Figure 13 2 CHMOS Oscillator 13 3 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL in
323. ister pair stores the S FBH CCAP1L comparison value or the captured value In the PWM mode the low byte S EBH register controls the duty cycle of the output waveform CCAP2H PCA Module 2 Compare Capture Registers This register pair stores the S FCH CCAP2L comparison value or the captured value In the PWM mode the low byte S ECH register controls the duty cycle of the output waveform PCA Module 3 Compare Capture Registers This register pair stores the S FDH CCAP3L comparison value or the captured value In the PWM mode the low byte S EDH register controls the duty cycle of the output waveform CCAP4H PCA Module 4 Compare Capture Registers This register pair stores the S FEH CCAP4L comparison value or the captured value In the PWM mode the low byte S EEH register controls the duty cycle of the output waveform CCAPMO PCA Compare Capture Module Mode Registers Contain bits for S DAH CCAPM1 selecting the operating mode of the compare capture modules and S DBH CCAPM2 enabling the compare capture flag See Table 11 3 for mode select bit S DCH CCAPM3 combinations S DDH CCAPM4 S DEH Table 11 2 External Signals Signal Multiplexed Description With ECI Timer counter External Input This signal is the external clock P1 2 input for the PCA timer counter CEXO Compare Capture Module External I O Each compare capture 1 3 module connects to Port 1 pin for external I O
324. it time stamp stored SOFO and SOF 1 is valid This bit is updated everytime a SOF token is received 6 RXSOF When set this bit is an indication that SOF token was received Must be cleared by software An 8 state pulse is generated and routed to the SOF pin 53 Reserved Values read from these bits are indeterminate Write zeros to these bits 2 0 TS10 8 Time stamp received from host This time stamp is valid only if the SFACK bit in the SOFH register is set TS10 8 are the upper three bits of the 11 bit frame number issued with an SOF token Figure 7 18 SOFH Start of Frame High Register FADDR Address S 8FH Reset State 00H 7 0 6 0 Bit Bit Function Number Mnemonic 7 Reserved The value read from this bit is indeterminate Write a zero to this bit 6 0 A6 0 7 bit programmable function address This register is programmed through the commands received via endpoint 0 on configuration Figure 7 19 FADDR Function Address Register 7 27 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel 7 4 2 Serial Bus Interface Engine SIE The SIE is the Universal Serial Bus protocol interpreter It serves as a communicator between the 82930A and the host through the USB lines A complete description of the bus specification can be found in Universal Serial Bus Specification The serial bus manager SBM serves as the in
325. ite to a port pin or to the external RAM 14 4 POWERDOWN MODE The powerdown mode places the 82930A in a very low power state Powerdown mode stops the oscillator and freezes all clocks at known states Figure 14 2 The CPU status prior to entering powerdown mode is preserved i e the program counter program status word register and reg ister file retain their data for the duration of powerdown mode In addition the SFRs and RAM contents are preserved The status of the port pins depends on the location of the program mem Internal program memory the ALE and PSEN pins are pulled low and the ports 0 1 2 and 3 pins are reading data Table 14 1 External program memory the and pins are pulled low the port 0 pins are floating and the pins of ports 1 2 and 3 are reading data Table 14 1 NOTE Vcc may be reduced to as low as 2 V during powerdown to further reduce power dissipation Take care however that Vcc is not reduced until power down is invoked 14 5 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel 14 4 1 Entering Powerdown Mode To enter powerdown mode set the PCON register PD bit The 82930A enters the power down mode upon execution of the instruction that sets the PD bit The instruction that sets the PD bit is the last instruction executed 14 4 2 Exiting Powerdown Mode CAUTION If Voc was reduced during the powerdown mode do not exit powerdown until Vcc i
326. ites the number of bytes to TXCNTx The data set index bits are updated after the write to TXCNTx This process is illustrated in Table 7 2 set in the FIFO is successfully transmitted the SIU reads a set from the FIFO and when a good transmission is acknowledged the read marker is advanced to the read pointer The data set index bits are updated after the read marker is advanced Table 7 2 Writing to the Byte Count Register Data Sets Written 4 FIF1 0 Set for Next Write Write bytes FIF1 0 451 450 to TXCNTX to TXDATx 0 No No Empty dsO gt Write byte gt 0 1 count to 1 No Yes 1 set 051 TXCNTx 1 1 1 0 Yes No 1 set 450 1 1 1 1 Yes Yes 2 sets Write ignored 1 1 The data set index bits also determine the set for which the next byte count is read Table 7 3 Note that FIF1 indicates the data set for the next read of TXCNTx except when FIF1 0 11 In that case the read is from the same set as the last read If TXCNTx is read when no data sets are in the FIFO the read pointer is cleared otherwise the read pointer is unaffected by reading the byte count last column of Table 7 3 Table 7 3 Reading the Byte Count Register Data Sets Written Data Set for Read Pointer FIF1 0 Next Read of Following Read ds1 950 of TXCNTx 0 No No 450 Cleared 1 No Yes 450 Unchanged 1 0 Yes No ds1 Unchanged 1 1 Yes Yes Same as last
327. ith R_ERR bit at the end of data reception mutually exclusive with R_ERR C 32 intel REGISTERS SADDR Address S A9H Reset State 0000 0000B Slave Individual Address Register SADDR contains the device s individual address for multiprocessor communication 7 0 Slave Individual Address Bit Bit Function Number Mnemonic uneto 7 0 SADDR 7 0 C 33 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel SADEN Address S B9H Reset State 0000 0000B Mask Byte Register This register masks bits in the SADDR register to form the device s given address for multiprocessor communication 7 0 Mask for SADDR Bit Bit Function 7 0 SADEN 7 0 Address S 91H Reset State 00H USB Interrupt Register The bits in SBl indicate which event caused an interrupt 7 0 RXD3 TXD3 RXD2 TXD2 RXD1 TXD1 RXDO TXDO Bit Bit 7 RXD3 6 TXD3 RXDX Xx 0 3 Receive Done Endpoint x Hardware sets this bit indicate that the 5 RXD2 RXFIFO for endpoint x has received data and the 82930A has sent 4 TXD2 handshake 3 RXD1 TXDx x 0 3 Transmit Done Endpoint x Hardware sets this bit to indicate that the 1 RXDO TXFIFO for endpoint x has transmitted data and the 82930A
328. itialized to 00H i e the given and broadcast addresses are XXXX XXXX all don t care bits This ensures that the serial port is backwards compatible with MCS 51 microcontrollers that do not support automatic address recognition 12 9 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel 12 6 BAUD RATES You must select the baud rate for the serial port transmitter and receiver when operating in modes 1 2 and 3 The baud rate is preset for mode 0 In its asynchronous modes the serial port can transmit and receive simultaneously Depending on the mode the transmission and reception rates can be the same or different Table 12 3 summarizes the baud rates that can be used for the four serial I O modes Table 12 3 Summary of Baud Rates Mode No of Send and Receive Send and Receive Baud Rates at the Same Rate at Different Rates 0 1 N A N A 1 Many Yes Yes 2 2 Yes No 3 Many Yes Yes Baud rates are determined by overflow of timer 1 and or timer 2 12 6 1 Baud Rate for Mode 0 The baud rate for mode 0 is fixed at Fosc 12 12 6 2 Baud Rates for Mode 2 Mode 2 has two baud rates which are selected by the SMODI bit in the PCON register Figure 14 1 The following expression defines the baud rate SMOD Fosc 64 Serial Mode 2 Baud Rate 2 12 6 3 Baud Rates for Modes 1 and 3 In modes 1 and 3 the baud rate is generated by overflow of timer 1 default and or t
329. joystick scanner etc In an event control application an end function signals the availability of data via an interrupt that ini tiates an interrupt service routine ISR In the case of isochronous data the interrupt is triggered by a function in response to a Start Of Frame SOF packet The ISR should prepare the data for transmission and initiate the transmission process Figure 8 3 is a flow diagram of a typical trans mit request ISR Details are shown in Figures 8 4 and 8 5 Start 80 17 TXCONx 3 ISO data Verify TXFIFO for data if not RETI Write current or previous data to FIFO Check for TXFIFO error Stall if error otherwise write byte count RETI Clear any FIFO error If no vacancy in TXFIFO RETI Write current data to FIFO Check for FIFO error RETI if error otherwise write byte count 4188 01 Figure 8 3 Transmit Request ISR Overview 8 4 intel USB OPERATING MODES A FIF1 0 11 TXFLGx 7 6 17 TXFIFO y TXFLGx 0 vacancy Clear FIFO FIF1 0 11 TXFIFO TXFLGx 7 6 vacancy Backup data set Backup current data set Restore previous data set 1 TXFLGx 0 set STL_TX EPCONx 6 Stall next TX Write byte count Backup data in TXFIFO RETI 4189 01 Figure 8 4 Transmit Request ISR Details Part 1 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUA
330. ken A 79 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Bytes 2 2 2 2 States 2 5 2 5 Encoding 0110 0000 rel addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation JZ PC PC 2 IF 20 THEN PC rel LCALL lt dest gt Function Long call Description Calls a subroutine located at the specified address The instruction adds three to the program counter to generate the address of the next instruction and then pushes the 16 bit result onto the stack low byte first The stack pointer is incremented by two The high and low bytes of the PC are then loaded respectively with the second and third bytes of the LCALL instruction Program execution continues with the instruction at this address The subroutine may therefore begin anywhere in the 64 Kbyte region of memory where the next instruction is located Flags OV N 2 stack pointer contains 07H and the label SUBRTN is assigned to program memory location 1234H After executing the instruction LCALL SUBRTN at location 0123H the stack pointer contains 09H on chip RAM locations 08H and 09H contain 01H and 26H and the PC contains 1234H LCALL addr16 Binary Mode Source Mode Bytes 3 3 States 9 9 Encoding 0001 0010 addr15 addr8 addr7 addrO Hex Code in Binary Mode Encoding Source Mode Encodin
331. l port data is read from the output data latch not the input pins OV intel INSTRUCTION SET REFERENCE Example The accumulator contains OC3H 11000011 and RO contains OAAH 10101010B After executing the instruction A RO the accumulator contains 69H 01101001B When the destination is a directly addressed byte this instruction can complement combina tions of bits in any RAM location or hardware register The pattern of bits to be comple mented is then determined by a mask byte either a constant contained in the instruction or a variable computed in the accumulator at run time The instruction XRL P1 00110001B complements bits 5 4 and 0 of output Port 1 Variations XRL dir8 A Binary Mode Source Mode Bytes 2 2 States 2 21 tlf this instruction addresses a port Px x 0 3 add 2 states Encoding 0110 0010 direct addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation XRL dir8 lt dir8 v A XRL dir8 data Binary Mode Source Mode Bytes 3 3 States 3t 3t tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 0110 0011 direct addr immed data Hex Code in Binary Mode Encoding Source Mode Encoding Operation XRL dir8 dir8 v data A data A 137 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Bytes States Encoding H
332. lator may be compared with any directly addressed byte or immediate data and any indirect RAM location or working register can be compared with an immediate constant INSTRUCTION SET REFERENCE intel Flags OV N 2 Example The accumulator contains 34H and R7 contains 56H After executing the first instruction in the sequence CJNE R7 460H NOT EQ R7 IF R7 lt 60H R7 gt 60H the CY flag is set and program execution continues at label NOT EQ By testing the CY flag this instruction determines whether R7 is greater or less than 60H NOT JC REQ LOW If the data being presented to Port 1 is also 34H then executing the instruction WAIT CJNE A P1 WAIT clears the CY flag and continues with the next instruction in the sequence since the accumulator does equal the data read from P1 If some other value was being input on P1 the program loops at this point until the P1 data changes to 34H Variations CJNE A data rel Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes 3 3 3 3 States 2 5 2 5 Encoding 1011 0100 immed data rel addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation PC 3 IF data THEN PC relative offset IF A data THEN lt 1 ELSE CY 0 CJNE A dir8 rel Binary Mode Not Taken Taken Bytes 3 3 Not Ta 3 Sour
333. lear this bit to select level triggered active low Figure 10 6 TCON Timer Counter Control Register 10 8 intel TIMER COUNTERS AND WATCHDOG TIMER 10 4 1 Mode 0 13 bit Timer Mode 0 configures timer 0 as a 13 bit timer which is set up as an 8 bit timer register with a modulo 32 prescaler implemented with the lower 5 bits of the TL1 register Figure 10 2 The upper 3 bits of the TL1 register are ignored Prescaler overflow increments the register 10 4 2 Mode 1 16 bit Timer Mode 1 configures timer 1 as a 16 bit timer with TH1 and TL1 connected in cascade Figure 10 2 The selected input increments TL 1 10 4 3 Mode 2 8 bit Timer with Auto reload Mode 2 configures timer 1 as an 8 bit timer TL1 register with automatic reload from the register on overflow Figure 10 3 Overflow from 1 sets overflow flag TF1 in the TCON reg ister and reloads TL1 with the contents of TH1 which is preset by software The reload leaves unchanged See section 10 5 1 Auto load Setup Example 10 4 4 Mode 3 Halt Placing timer 1 in mode 3 causes it to halt and hold its count This can be used to halt timer 1 when the run control bit is not available i e when timer 0 is in mode 3 See the final para graph of section 10 4 Timer 1 10 5 TIMER 0 1 APPLICATIONS Timer 0 and timer 1 are general purpose timers that can be used in a variety of ways The timer applications
334. ling pins in soft ware because the toggle occurs before the interrupt request is serviced Thus interrupt response time does not affect the accuracy of the output To program a compare capture module for the high speed output mode set the TOGx bits in the module s CCAPMXx register Table 11 3 lists the bit combinations for selecting module modes A match between the PCA timer counter and the compare capture registers CCAPxH CCAPxL toggles the CEXx pin and sets the module s compare capture flag CCEx in the CCON register By setting or clearing the CEXx pin in software the user selects whether the match toggles the pin from low to high or vice versa The user also has the option of generating an interrupt request when the match occurs by setting the corresponding interrupt enable bit ECCFEx in the register Since hardware does not clear the compare capture flag when the interrupt is processed the user must clear the flag in soft ware intel PROGRAMMABLE COUNTER ARRAY If the user does not change the compare capture registers in the interrupt routine the next toggle occurs after the PCA timer counter rolls over and the count again matches the comparison value During the interrupt routine a new 16 bit compare value can be written to the compare capture registers NOTE To prevent an invalid match while updating these registers user software should write to CCAPXL first the
335. lizes the 82930 and vectors the CPU to address FF 0000H reset is re quired after applying power at turn on A reset is a means of exiting the idle and powerdown modes or recovering from software malfunctions To achieve a valid reset Voc must be within its normal operating range see device data sheet and the reset signal must be maintained for 64 clock cycles 64Tosc after the oscillator has sta bilized Device reset is initiated in two ways externally by asserting the RST pin internally if the hardware WDT or the PCA WDT expires power off flag POF in the PCON register indicates whether a reset is a warm start or a cold start A cold start reset POF 1 is a reset that occurs after power has been off or V o has fallen below 3 V so the contents of volatile memory are indeterminate POF is set by hardware when rises from less than to its normal operating level See section 14 2 2 Power Off Flag warm start reset 0 is a reset that occurs while the chip is at operating voltage for ex ample a reset initiated by a WDT overflow or an external reset used to terminate the idle or pow erdown modes 13 4 1 Externally Initiated Resets To reset the 82930A hold the RST pin at a logic high for at least 64 clock cycles 64 while the oscillator is running Reset can be accomplished automatically at the time power is applied by capacitively coupling RST to see Figure 13 1 and sect
336. load them for the desired configuration It also describes how internal memory maps into external memory Chapter 5 Instructions and Addressing provides an overview of the instruction set It de scribes each instruction type control arithmetic logical etc and lists the instructions in tabular form This chapter also discusses the addressing modes bit instructions and the program status words Appendix A Instruction Set Reference provides a detailed description of each instruc tion Chapter 6 Interrupts describes the 82930A interrupt circuitry which provides a TRAP in struction interrupt and seven maskable interrupts two external interrupts three timer interrupts a PCA interrupt and a serial port interrupt This chapter also discusses the interrupt priority scheme interrupt enable interrupt processing and interrupt response time Chapter 7 Universal Serial Bus the primary description of the USB FIFO operation and the Serial Interface Unit SIU Chapter 8 USB Operating Modes discusses the various operating modes for the 82930A Chapter 9 Input Output Ports describes the four 8 bit I O ports ports 0 3 and discusses their configuration for general purpose I O external memory accesses ports 0 2 and alternative special functions 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Chapter 10 Timer Counters and WatchDog Timer describes the three on chip tim
337. lt DRk SP SP 3 Return from subroutine Pops the high and low bytes of the PC successively from the stack decrementing the stack pointer by two Program execution continues at the resulting address which normally is the instruction immediately following ACALL or LCALL OV N 2 The stack pointer contains on chip RAM locations 0AH contain 01H and 23H respectively After executing the instruction RET the stack pointer contains 09H and program execution continues at location 0123H Binary Mode Source Mode 1 1 7 7 0010 0010 Binary Mode Encoding Source Mode Encoding RET PC 15 8 SP lt SP 1 Return from interrupt This instruction pops two or four bytes from the stack depending on the INTR bit in the register intel INSTRUCTION SET REFERENCE If INTR 0 RETI pops the high and low bytes of the PC successively from the stack and uses them as the 16 bit return address in region FF The stack pointer is decremented by two No other registers are affected and neither PSW nor PSW1 is automatically restored to its pre interrupt status If INTR 1 RETI pops four bytes from the stack PSW1 and the three bytes of the PC The three bytes of the PC are the return address which can be anywhere in the 16 Mbyte memory space The stack pointer is decremented by four PSW1 is restored to its pre
338. ming the SMOD bit in the PCON register see section 12 6 Baud Rates 5 SM2 Serial Port Mode Bit 2 Software writes to bit SM2 to enable and disable the multiprocessor communication and automatic address recognition features This allows the serial port to differentiate between data and command frames and to recognize slave and broadcast addresses 4 REN Receiver Enable Bit To enable reception set this bit To enable transmission clear this bit 3 TB8 Transmit Bit 8 In modes 2 and 3 software writes the ninth data bit to be transmitted to TB8 Not used in modes 0 and 1 2 RB8 Receiver Bit 8 Mode 0 Not used Mode 1 5 2 clear Set or cleared by hardware to reflect the stop bit received Modes 2 and 3 5 2 set Set or cleared by hardware to reflect the ninth data bit received Figure 12 2 SCON Serial Port Control Register 12 3 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel 1 TI Transmit Interrupt Flag Bit Set by the transmitter after the last data bit is transmitted Cleared by software 0 RI Receive Interrupt Flag Bit Set by the receiver after the last data bit of a frame has been received Cleared by software Figure 10 2 SCON Serial Port Control Register Continued 12 2 MODES OF OPERATION The serial I O port can operate in one synchronous and three asynchronous modes 12 2 1 Synchronous Mode Mode 0 M
339. ms for the bus cycles bus cycles with wait states and the configuration byte bus cycles It also provides bus cycle diagrams with AC timing symbols and definitions of the symbols Appendix Instruction Set Reference provides reference information for the instruction set It describes each instruction defines the bits in the program status word registers PSW PSW1 shows the relationships between instructions and PSW flags and lists hexadecimal op codes instruction lengths and execution times Appendix B Signal Descriptions describes the function s of each device pin Descriptions are listed alphabetically by signal name This appendix also provides a list of the signals grouped by functional category Appendix C Registers accumulates for convenient reference copies of the register defi nition figures that appear throughout the manual Glossary a glossary of terms has been provided for reference of technical terms 1 2 intel GUIDE TO THIS MANUAL 1 2 NOTATIONAL OF CONVENTIONS AND TERMINOLOGY The following notations and terminology are used in this manual The Glossary defines other terms with special meanings italics XXXX Assert and Deassert Instructions Logic 0 Low Logic 1 High The pound symbol has either of two meanings depending on the context When used with a signal name the symbol means that the signal is active low When used with an instruction pneumoni
340. n Figure 12 1 The SBUF register which holds re ceived bytes and bytes to be transmitted actually consists of two physically different registers To send software writes a byte to SBUF to receive software reads SBUF The receive shift reg ister allows reception of a second byte before the first byte has been read from SBUF However if software has not read the first byte by the time the second byte is received the second byte will overwrite the first The UART sets interrupt bits TI and RI on transmission and reception respec tively These two bits share a single interrupt request and interrupt vector Table 12 1 Serial Port Signals Function Multiplexed Description With TXD Transmit Data In mode 0 TXD transmits the clock signal In P3 1 modes 1 2 and 3 TXD transmits serial data RXD y o Receive Data mode 0 RXD transmits and receives serial P3 0 data In modes 1 2 and 3 RXD receives serial data 12 1 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Table 12 2 Serial Port Special Function Registers intel Mnemonic Description Address SBUF Serial Buffer Two separate registers comprise the SBUF register Writing 99H to SBUF loads the transmit buffer reading SBUF accesses the receive buffer SCON Serial Port Control Selects the serial port operating mode SCON enables 98H and disables the receiver framing bit error detection multipro
341. n CCAPxH A write to CCAPxL clears the bit disabling the compare function while a write to sets the bit re enabling the compare function 11 3 5 Watchdog Timer Mode A watchdog timer WDT provides the means to recover from routines that do not complete suc cessfully A WDT automatically invokes a device reset if it does not regularly receive hold off signals WDTs are used in applications that are subject to electrical noise power glitches elec trostatic discharges etc or where high reliability is required In addition to the 82930A s 14 bit hardware WDT the PCA provides a programmable frequency 16 bit WDT as a mode option on compare capture module 4 This mode generates a device reset when the count in the PCA timer counter matches the value stored in the module 4 compare cap ture registers A PCA WDT reset has the same effect as an external reset Module 4 is the only PCA module that has the WDT mode When not programmed as a WDT it can be used in the other modes To program module 4 for the WDT mode Figure 11 4 set the ECOMA and bits in the CCAPM4 register and the WDTE bit in the register Table 11 3 lists the bit combina tions for selecting module modes Also select the desired input for the PCA timer counter by pro gramming the CPSO and CPS1 bits in register see Figure 11 7 Enter a 16 bit comparison value in the compare capture registers CCAP4H C
342. n a valid ACK handshake 6 3 Reserved Values read from these bits are indeterminate Write zeros to these bits 2 T VOID A time out condition has occurred in response to a valid IN token Transmit time out is closely associated with NACK STALL handshake returned by function after a valid IN token due to the following conditions 1 There is no data in TXFIFO to send 2 STL TX is set This bit does not affect TXD bit Updated in respond to a valid IN token 1 T ERR An error condition has occurred with the transmission Complete or partial data has been transmitted It can be one of the following 1 Data transmitted successfully but no handshake received 2 TXFIFO goes into underrun condition while transmitting Corresponding TXD bit is set when active Updated together with T ACK bit atthe end of data transmission mutually exclusive with T ACK 0 T ACK Data transmission completed and acknowledged successfully Corresponding TXD bit is set when active Updated together with T ERR bit atthe end of data transmission mutually exclusive with T ERR C 53 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel WDTRST Watchdog Timer Reset Register Writing the two byte sequence 1EH E1H to the WDTRST register clears and enables the hardware WDT The WDTRST register is a write only register Attempts to read it return FFH The WDT itself is not read or write accessible See Chapter 10
343. nal interrupt pins must be deasserted for at least four state times prior to a request External interrupt pins are sampled once every four state times a frame length of 666 4 ns at 12 MHz A level triggered interrupt pin held low or high for any five state time period guarantees 6 3 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel detection Edge triggered external interrupts must hold the request pin low for at least five state times This ensures edge recognition and sets interrupt request bit EXx The CPU clears EXx au tomatically during service routine fetch cycles for edge triggered interrupts Table 6 3 Interrupt Control Matrix Interrupt D pied n TO INTHE me INTO Bit Name in IEO Register EA EC ET2 ES ET1 EX1 ETO EXO Interrupt Priority Within Level 7 Low Priority i 6 P 3 1 1 High Priority Bit Names in IPHO Reserved IPHO 6 IPHO 5 IPHO 4 IPHO 3 IPHO 2 IPHO 1 0 0 Reserved 0 6 IPLO 5 IPLO 4 0 3 0 2 0 1 0 0 Programmable for Negative edge Triggered or Level NA Edge No No No Yes No Yes triggered Detect Interrupt Request Flag in CCON CF 2 T2CON SCON or 2 TEO TCON Register Interrupt Request Edge Edge Flag Cleared by No No No No Yes Yes Yes Yes Hardware Level No Level No ISR Vector Address NA FF FF FF FF FF F
344. nal memory Asserted for the memory address range specified by configuration bits RD1 0 UCONFIGO 3 2 See RD and Table 4 XTAL1 Input to the On chip Inverting Oscillator Amplifier To use the internal oscillator a crystal resonator circuit is connected to this lead If an external oscillator is used its output is connected to this lead XTAL 1 is the clock source for internal timing XTAL2 Output of the On chip Inverting Oscillator Amplifier To use the internal oscillator a crystal resonator circuit is connected to this lead If an external oscillator is used leave XTAL2 unconnected t The descriptions of A15 8 P2 7 0 AD7 0 P0 7 0 are for the nonpage mode chip configuration If the chip is configured for page mode operation port 0 carries the lower address bits A7 0 and port 2 carries the upper address bits A15 8 and the data 07 0 B 5 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Table B 4 Memory Signal Selections RD1 0 intel RD1 0 P1 7 CEX A17 P3 7 RD A16 PSEN WR Features 00 17 A16 Asserted for Asserted for writes to 256 Kbyte external all addresses all memory locations memory 01 P1 7 CEX4 A16 Asserted for Asserted for writes to 128 Kbyte external all addresses all memory locations memory 1 0 P1 7 CEX4 P3 7 only Asserted for Asserted for writes to 64 Kbyte external all addresses all memory locations memory On
345. ncoding Source Mode Encoding Operation MOV MOV Rm data DRkd lt DRks A 87 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Binary Mode Source Mode Bytes 4 3 States 3 2 Encoding 0111 1110 5555 0000 data Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV Rm data MOV WRi data16 Binary Mode Source Mode Bytes 5 4 States 3 2 Encoding 0111 1110 tttt 0100 data hi data low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV WRJ lt data16 MOV DRk 0data16 Binary Mode Source Mode Bytes 5 4 States 5 4 Encoding 0111 1110 uuuu 1000 data hi data low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV lt 0data16 MOV DRk 1data16 Bytes 5 States 5 A 88 Source Mode 4 4 intel INSTRUCTION SET REFERENCE Encoding 0111 1110 uuuu 1100 data hi data low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV lt 1data16 MOV Rm 8 Binary Mode Source Mode Bytes 4 3 States 3t 2T tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 0111 1110 SSSS 0001 direct addr Hex Code in Binar
346. nic unctio 7 CIDL PCA Timer Counter Idle Control CIDL 1 disables the PCA timer counter during idle mode CIDL 0 allows the PCA timer counter to run during idle mode 6 WDTE Watchdog Timer Enable WDTE 1 enables the watchdog timer output on PCA module 4 WDTE 0 disables the PCA watchdog timer output 5 8 Reserved Values read from these bits are indeterminate Write zeros to these bits 2 1 CPS1 0 PCA Timer Counter Input Select CPS1 CPSO 0 0 Fosc 12 0 1 Fosc 4 1 0 Timer 0 overflow 1 1 External clock at pin maximum rate Fog 8 0 ECF PCA Timer Counter Interrupt Enable 1 enables the CF bit in the CCON register to generate an interrupt request 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel DPH Address 5 83 Reset State 0000 0000B Data Pointer High DPH provides SFR access to register file location 58 also named DPH DPH is the upper byte of the 16 bit data pointer DPTR Instructions in the MCS 51 architecture use DPTR for data moves code moves and for a jump instruction JMP A DPTR See also DPL DPXL DPH Contents Bit Bit Number Mnemonic Function 7 0 DPH 7 0 Data Pointer High Bits 8 15 of the extended data pointer DPX DR56 DPL Address 5 82 Reset State 0000 0000B Data Pointer Low DPL provides SFR access to register file location 59 also named DPL
347. not gen erate an interrupt The second firmware routine is a normal subroutine not an ISR and is initiated upon reception of the next SOF token The read marker and read pointer are adjusted automati cally by the FIFO hardware ARM 1 or by the second firmware routine ARM 0 Figure 8 9 summarizes the flow of SIU operations and Figure 8 10 provides details Valid IN token Endpoint enabled Endpoint prepared to send Transmit zero length packet Set timeout status Send data If TXFIFO error send error Update TX status Done A4191 01 Figure 8 9 SIU Transmit Operations for Isochronous Data Overview 8 13 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel See Table 5 2 for transmit enable T VOID status TX enabled y See Table 5 3 for n T VOID transmit ready status Transmit zero length packet Read byte count register TXFIFO error status 5 Insert bit stuff error and force last data Transmit data over USB See Table 5 4 amp 5 5 Last data byte End of packet EOP Set y VOID Update TX status Done 4207 01 Figure 8 10 SIU Transmit Operations for Isochronous Data Details intel USB OPERATING MODES 8 2 4 Post transmit Operations Transmission status is updated at the end of data transmission based on the handshake received from the host non isochronous data
348. nous data a failed transfer is not retried lossy data For non isochronous data a failed transfer can be repeat ed Data that has to be repeated is considered lossless data Automatic adjustment of the FIFO markers and pointers is accomplished by the SIU hardware Manual adjustment is accomplished by the 82930A firmware 8 2 TRANSMIT OPERATIONS 8 2 1 Overview A transmit operation occurs in three major steps Pre transmit data preparation by firmware 2 Data packet transmission by the SIU hardware 3 Post transmit management by firmware These steps are depicted in a high level view of the transmit operations Figure 8 2 The pre transmit and the post transmit operations are executed by the two firmware routines on the left side The SIU hardware right side transmits the data packet over the USB line Details of these three operations are described in Transmit Request ISR SIU Transmit Operations and Post transmit Operations This section provides an overview 8 2 Firmware Transmit request routine Interrupt keybd etc Write data to TXFIFO RETI Post transmit routine TXD Int ISO 0 SOF Token ISO 1 ISR ISO 0 Check status If ATM 0 Adjust FIFO read marker and pointer RETI ISO 0 RET RETI ISO 1 USB OPERATING MODES Hardware SIU FIFO Send data over USB If ATM 1 Adjust FIFO read marker and pointer If ISO 0
349. ns Continued intel Sianal Multiplexe EE Type Description d With EA External Access Directs program memory accesses to on chip or off chip code memory EA 1 directs program memory accesses to on chip code memory if the address is within the range of the on chip code memory otherwise the access is to external memory EA 0 directs program memory accesses to external memory Devices without on chip program memory should have EA strapped to Vss The value of EA is latched at reset ECAP External Capacitor Must be connected to a capacitor or larger to ensure proper operation of the differential line driver The other lead of the capacitor must be connected to Va ECI External Clock Input External clock input to the 16 bit P1 2 timer INT 1 0 External Interrupts 0 and 1 These inputs set bits IE1 0 inthe P3 3 2 register If bits IT1 0 in the TCON register are set bits IE1 0 are set by a falling edge on INT1 INTO If bits INT1 0 are clear bits IE1 0 set by a low level on INT1 0 P0 7 0 Port 0 This is an 8 bit open drain bidirectional I O port AD7 0 P1 0 Port 1 This is an 8 bit bidirectional I O port with internal pullups T2 P1 1 T2EX P1 2 ECI P1 7 3 CEX3 0 CEX4 A17 P2 7 0 V O Port 2 This is an 8 bit bidirectional I O port with internal pullups A15 8 P3 0 Port 3 This is an 8 bit bidirectional I O port
350. nt Register Endpoint x This two byte ring buffer stores the number of bytes in data set 0 and data set 1 7 0 Byte Count 0 255 Bit Bit Number Function 7 0 TXCNTx7 0 Byte Count The number of bytes in data set 0 or data set 1 When this register is accessed the byte count written read is for data set 0 or data set 1 depending on the data set index bits FIF1 0 in TXFLAGx as shown Table 7 2 and Table 7 3 Following a read of this register the read write index is unchanged following a write the read write index is toggled Write the byte count to this register after writing the data to TXDATx C 49 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel TXCONx Address See Table 7 7 xz 0 3 Reset State See Table 7 7 USB Transmit FIFO Control Register Endpoint x The bits in this register control the operation of TXFIFOx 7 0 CLR ISO ATM ADV RM REV RP Bit Bit Functio 7 CLR Clear Setting this bit flushes TXFIFOx sets the EMPTY bit in TXFLGx and clears all other bits in TXFLGx After the flush hardware clears this bit Setting this bit does not affect the ATM and ISO bits 6 4 Reserved Values read from these bits are indeterminate Write zeros to these bits 3 ISO Isochronous Data Software sets this bit to indicate that TXFIFOx contains i
351. ntains 0C5H 11000101B After executing the instruction SLL register 1 Register 1 contains 8AH 10001010B and CY 1 Binary Mode Source Mode 3 2 intel States Encoding Hex Code in Operation SLL WRj Bytes States Encoding Hex Code in Operation SRA src Function Description Flags Example Variations SRA Rm Bytes INSTRUCTION SET REFERENCE 0011 1110 5555 0000 Binary Mode A5 Encoding Source Mode Encoding SLL Rm a 1 lt Rm a Rm 0 0 CY Rm 7 Binary Mode Source Mode 3 2 2 1 0011 1110 tttt 0100 Binary Mode A5 Encoding Source Mode Encoding SLL WRi b 1 WRj b WRj 0 lt 0 CYc WRj 15 Shift arithmetic right by 1 bit Shifts the specified variable to the arithmetic right by 1 bit The MSB is unchanged The bit shifted out LSB is stored in the CY bit OV Register 1 contains 0C5H 11000101 After executing the instruction SRA register 1 Register 1 contains OE2H 11100010B and CY 1 Binary Mode Source Mode 3 2 A 125 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel States Encoding Hex Code in Operation SRA WRj Bytes States Encoding Hex Code in Operation SRL src Function Description Flags Example Variations SRL Rm Bytes A
352. nter runs for a programmed length of time then issues an interrupt request When operating as a counter a timer counter counts negative transitions on an external pin After a preset number of counts the counter issues an interrupt re quest The watchdog timer provides a way to monitor system operation It causes a system reset if a soft ware malfunction allows it to expire The watchdog timer is covered in Section 10 7 10 1 TIMER COUNTER OVERVIEW 82930A contains three general purpose 16 bit timer counters Although they are identified as timer 0 timer 1 and timer 2 you can independently configure each to operate in a variety of modes as a timer or as an event counter Each timer employs two 8 bit timer registers used sep arately or in cascade to maintain the count The timer registers and associated control and capture registers are implemented as addressable special function registers SFRs Table 10 1 briefly de scribes the SFRs referred to in this chapter Four of the SFRs provide programmable control of the timers as follows Timer counter mode control register TMOD and timer counter control register control timer 0 and timer 1 Timer counter 2 mode control register TZ2MOD and timer counter 2 control register T2CON control timer 2 For a map of the SFR address space see Table 3 4 in Chapter 3 Table 10 2 describes the external signals referred to in this chapter 10 2 TIMER COUNTER OPERATION
353. nterrupt Priority Bit Low 0 IPL1 0 Endpoint 0 Interrupt Priority Bit Low Figure 6 9 IPL1 Interrupt Priority Low Register 1 6 8 INTERRUPT PROCESSING Interrupt processing is a dynamic operation that begins when a source requests an interrupt and lasts until the execution of the first instruction in the interrupt service routine see Figure 6 10 Response time is the amount of time between the interrupt request and the resulting break in the current instruction stream Latency is the amount of time between the interrupt request and the execution of the first instruction in the interrupt service routine These periods are dynamic due to the presence of both fixed time sequences and several variable conditions These conditions contribute to total elapsed time Response Time OSC State Time FLTLFLFLELTLTLTITLTLTLTLTLTLTLTLTLTLTLTLTUTLTLTLTLTLTLTLTLTLTLTLTLTLTLTLTI External N U Interrupt Request Ending Instructions Push PC call sR MESES Latency A4153 01 Figure 6 10 The Interrupt Process 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Both response time and latency begin with the request The subsequent minimum fixed sequence comprises the interrupt sample poll and request operations The variables consist of but are not limited to specific instructions in use at request time internal versus external interrupt source requests internal versus external pr
354. nts of the RCAP2H and RCAP2L registers are loaded into TH2 TL2 In this mode timer 2 overflows do not generate interrupts The formula gives the clock out frequency as a function of the system oscillator frequency and the value in the RCAP2H and RCAP2L registers Fosc Clock out Frequency 2 55535 ROAPZH RCAP2D For a 12 system clock timer 2 has a programmable frequency range of 47 8 Hz to 3 MHz The generated clock signal is brought out to the T2 pin Timer 2 is programmed for the clock out mode as follows 1 Set the T2OE bit in T2MOD This gates the timer register overflow to the 2 counter 2 Clear the C T2 bit in T2CON to select F 2 as the timer input signal This also gates the output of the 2 counter to pin T2 3 Determine the 16 bit reload value from the formula and enter in the RCAP2H RCAP2L registers 4 Enter a 16 bit initial value in timer register TH2 TL2 This can be the same as the reload value or different depending on the application 5 start the timer set the TR2 run control bit in T2CON Operation is similar to timer 2 operation as a baud rate generator It is possible to use timer 2 as baud rate generator and a clock generator simultaneously For this configuration the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers 10 14 intel TIMER COUNTERS AND WATCHDOG TIMER TH2 8 Bits Interrupt Request T2
355. o turn the timer on and off This setup can be used to measure the width of a positive going pulse present at pin INTx Pulse width measurements using timer 0 in mode 1 can be made as follows 1 Program the four low order bits of the TMOD register Figure 10 5 to specify mode 1 for timer 0 0 to select Fosc 12 as the timer input and 1 to select INTO as timer run control 2 Enter an initial value of all zeros in the 16 bit timer register THO TLO or read and store the current contents of the register Set the TRO bit in the TCON register Figure 10 6 to enable INTO Apply the pulse to be measured to pin INTO The timer runs when the waveform is high Clear the TRO bit to disable INTO Read timer register THO TLO to obtain the new value Calculate pulse width 12 x new value initial value 995 SOY co PES Example Fosc 12 MHz and 12Tosc 1 us If the new value 10 000 6 and the initial value 0 the pulse width 1 us x 10 000 10 ms 10 6 TIMER 2 Timer 2 is a 16 bit timer counter The count is maintained by two eight bit timer registers TH2 TL2 connected in cascade The timer counter 2 mode control register T2MOD Figure 10 11 and the timer counter 2 control register T2CON Figure 10 12 control the operation of timer 2 Timer 2 provides the following operating modes capture mode auto reload mode baud rate gen erator mode and programmable clock out mode S
356. o communicate with Slaves B and C but not Slave A the master must send an address with bits 0 and 1 both set e g 1111 0011 12 8 intel SERIAL PORT For Slaves and B bit 2 is a don t care bit for Slave C bit 2 is a 0 To communicate with Slaves A and B but not Slave C the master must send an address with bit O set bit 1 clear and bit 2 set e g 1111 0101 To communicate with Slaves A B and C the master must send an address with bit O set bit 1 clear and bit 2 clear e g 1111 0001 12 5 2 Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don t care bits e g SADDR 01010110 SADEN 1111 1100 SADDR OR SADEN 1111 111X The use of don t care bits provides flexibility in defining the broadcast address however in most applications a broadcast address is OFFH The following is an example of using broadcast addresses Slave A SADDR 1111 0001 Slave C SADDR 11110010 SADEN 1111 1010 SADEN 1111 1101 Broadcast 1111 1X11 Broadcast 11111111 Slave SADDR SADEN Broadcast 1111 0011 1111 1001 1111 1X11 For Slaves A and B bit 2 is a don t care bit for Slave C bit 2 is set To communicate with all of the slaves the master must send an address FFH To communicate with Slaves A and B but not Slave C the master can send an address FBH 12 5 3 Reset Addresses On reset the SADDR and SADEN registers are in
357. ock CPU A4160 01 Figure 14 2 Idle and Powerdown Clock Control 14 3 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel 14 3 IDLE MODE Idle mode is a power reduction mode that reduces power consumption to about 40 of normal In this mode program execution halts Idle mode freezes the clocks to the CPU at known states while the peripherals continue to be clocked Figure 14 2 The CPU status before entering idle mode is preserved i e the program counter program status word register and register file retain their data for the duration of idle mode The contents of the SFRs and RAM are also retained The status of the port pins depends upon the location of the program memory Internal program memory the ALE and PSEN pins are pulled high and the ports 0 1 2 and 3 pins are reading data Table 14 1 External program memory the ALE and pins are pulled high the port 0 pins are floating and the pins of ports 1 2 and 3 are reading data Table 14 1 NOTE If desired the PCA may be instructed to pause during idle mode by setting the CIDL bit in the CMOD register Figure 11 7 14 3 1 Entering Idle Mode To enter idle mode set the PCON register IDL bit The 82930A enters idle mode upon execution of the instruction that sets the IDL bit The instruction that sets the IDL bit is the last instruction executed CAUTION If the IDL bit and the PD bit are set simultaneously the 82930A ent
358. ode Encoding Operation ADD Rmd Rms ADD WRjd WRjs Binary Mode Source Mode Bytes 3 2 States 3 2 Encoding 0010 1101 tttt Hex Code Binary Mode A5 Encoding Source Mode Encoding Operation ADD WRjd lt WRijd ADD DRkd DRks Binary Mode Source Mode Bytes 3 2 States 5 4 Encoding 0010 1111 uuuu UUUU Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ADD DRkd DRkd DRks ADD Rm data Binary Mode Source Mode Bytes 4 3 States 3 2 Encoding 0010 1110 5555 0000 data Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ADD A 30 Rm Rm data intel INSTRUCTION SET REFERENCE ADD WRj data16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding 0010 1110 0100 low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ADD WRj lt WRj data16 ADD DRk 0data16 Binary Mode Source Mode Bytes 5 4 States 6 5 Encoding 0010 1110 uuuu 1000 data hi data low Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ADD DRk DRk data16 ADD 8 Binary Mode Source Mode Bytes 4 3 States 3t 21 tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 0010 1110 5555 0001 direct addr Hex Cod
359. ode 0 is a half duplex synchronous mode which is commonly used to expand the I O capabil ities of a device with shift registers The transmit data TXD pin outputs a set of eight clock puls es while the receive data RXD pin transmits or receives a byte of data The eight data bits are transmitted and received least significant bit LSB first Shifts occur in the last phase S6P2 of every peripheral cycle which corresponds to a baud rate of Fosc 12 Figure 12 3 shows the timing for transmission and reception in mode 0 12 2 1 1 Transmission Mode 0 Follow these steps to begin a transmission 1 Write to the SCON register clearing bits SMO SM1 and REN 2 Write the byte to be transmitted to the SBUF register This write starts the transmission Hardware executes the write to SBUF in the last phase S6P2 of a peripheral cycle At S6P2 of the following cycle hardware shifts the LSB DO onto the pin At S3P1 of the next cycle the TXD pin goes low for the first clock signal pulse Shifts continue every peripheral cycle In the ninth cycle after the write to SBUF the MSB D7 is on the RXD pin At the beginning of the tenth cycle hardware drives the pin high and asserts to indicate the end of the transmission 12 4 intel SERIAL PORT Transmit Be eee le S3P1 S6P1 Write to SBUF E o S6P2 Shift T D Dn S6P2 S6P2 S6P2 S6P2 mo Noo X 9
360. odes 1 and 3 3 EXEN2 Timer 2 External Enable Bit Setting EXEN2 causes a capture or reload to occur as a result of a negative transition on T2EX unless timer 2 is being used as the baud rate generator for the serial port Clearing 2 causes timer 2 to ignore events at T2EX 2 TR2 Timer 2 Run Control Bit Setting this bit starts the timer 1 C T2 Timer 2 Counter Timer Select C T2 0 selects timer operation timer 2 counts the divided down system clock C T2 1 selects counter operation timer 2 counts negative transitions on external pin T2 0 CP RL2 Capture Reload Bit When set captures occur on negative transitions at T2EX if EXEN2 1 When cleared auto reloads occur on timer 2 overflows or negative transitions at T2EX if EXEN2 1 The CP RL2 bit is ignored and timer 2 forced to auto reload on timer 2 overflow if RCLK 1 or TCLK 1 Figure 10 12 T2CON Timer 2 Control Register 10 17 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel 10 7 2 Using the WDT To use the WDT to recover from software malfunctions the user program should control the WDT as follows 1 Following device reset write the two byte sequence IEH E1H to the WDTRST register to enable the WDT The WDT begins counting from 0 2 Repeatedly for the duration of program execution write the two byte sequence IEH EIH to the WDTRST register to clear and enable the WDT before it ove
361. ogram operation stack location presence of wait states page mode operation and branch pointer length NOTE In the following discussion external interrupt request pins are assumed to be inactive for at least four state times prior to assertion In this chapter all external hardware signals maintain some setup period 1 less than one state time Signals must meet Vm and specifications prior to any state time under discussion This setup state time is not included in examples or calcula tions for either response or latency 6 8 1 Minimum Fixed Interrupt Time interrupts are sampled or polled every four state times see Figure 6 10 Two of eight inter rupts are latched and polled per state time within any given four state time window One addition al state time is required for a context switch request For code branches to jump locations in the current 64 Kbyte memory region compatible with MCS 51 microcontrollers the context switch time is 11 states Therefore the minimum fixed poll and request time is 16 states 4 poll states 1 request state 11 states for the context switch 16 state times Therefore this minimum fixed period rests upon four assumptions The source request is an internal interrupt with high enough priority to take precedence over other potential interrupts The request is coincident with internal execution and needs no instruction completion time The program uses an internal stack loca
362. onfigure the 82930 to operate in page mode for accelerated instruction fetches from external memory In page mode if an instruction fetch is to the same 256 byte page as the previous fetch the fetch requires one state two clocks rather than two states four clocks The 82930A register file has forty registers which can be accessed as bytes words and double words As in the MCS 51 architecture registers 0 7 consist of four banks of eight registers each where the active bank is selected by the program status word PSW for fast context switches 82930A is single pipeline machine When the pipeline is full and code is executing from on chip code memory an instruction is completed every state time When the pipeline is full and code is executing from external memory with no wait states and no extension of the ALE signal an instruction is completed every two state times Code Bus 16 Code Address 24 LL Interrupt Handler Instruction Sequencer lt Data Bus 8 Fil 15 Interface Data Address 24 A4272 01 Figure 2 4 The CPU 2 6 intel INTRODUCTION 2 3 2 Clock and Reset Unit timing source for the 82930 can be an external oscillator or an internal oscillator with an external crystal resonator see Chapter 13 Minimum Hardware Setup The basic unit of time in 82930A microcontrollers is the state time or state which is two oscillator periods see Figure 2 5
363. only In the MCS 251 architecture all locations in region 00 are accessible by direct indirect and displacement addressing see section 3 2 82930A Memory Space The 128 byte SFR space for MCS 51 microcontrollers is mapped into the 512 byte SFR space of the MCS 251 architecture starting at address S 080H as shown in Figure 3 3 This provides com plete compatibility with direct addressing of MCS 51 microcontroller SFRs including bit ad dressing The SFR addresses are unchanged in the new architecture In the MCS 251 architecture SFRs A B DPL DPH and SP as well as the new SFRs DPXL and SPH reside in the register file for high performance However to maintain compatibility they are also mapped into the SFR space at the same addresses as in the MCS 51 architecture 3 2 82930A MEMORY SPACE Figure 3 4 shows the logical memory space for the 82930A microcontroller The usable memory space of the 82930A consists of eight 64 Kbyte regions 00 01 02 03 FC FD FE and FF Code can execute from all eight regions code execution begins at FF 0000H Regions 04 are reserved Reading a location in the reserved area returns an unspecified value Software can execute a write to the reserved area but nothing is actually written Although the memory space comprises eight regions not all of these regions are available at the same time The maximum number of external address lines is 18 which limits external memory to a maximum
364. or the other endpoints have capacities of 16 bytes see Table 7 1 All transmit FIFOs have the same architecture and all receive FIFOs have the same archi tecture Table 7 1 FIFO Capacities T A 0 16 bytes 16 bytes 1 256 bytes 256 bytes 2 16 bytes 16 bytes 3 16 bytes 16 bytes 7 2 TRANSMIT FIFOS 7 2 1 Transmit FIFO Overview The transmit FIFO is a circulating FIFO with the following features support for up to two separate data sets of variable sizes abyte count register that accesses the number of bytes in the data sets protection against overwriting data in a full FIFO capability to retransmit the current data set Figure 7 1 illustrates a transmit FIFO TXFIFOx and its associated logic can manage up to two data sets data set 0 450 and data set 1 ds1 The ability to have two data sets in the FIFO sup ports back to back transmissions 7 1 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Write Pointer 82930 CPU Writes to FIFO SIU Reads FIFO Read Pointer ADV RM Read Marker 4258 01 Figure 7 1 Transmit FIFO TXFIFOx The 82930A writes to the FIFO location specified by the write pointer which increments by one automatically following a write The read marker points to the first byte of data written to a data set and the read pointer points to the next FIFO location to be read by the SIU The read pointer increments by one
365. ord and the 16 bits of the low word of the PC are then loaded respectively with the second third and fourth bytes of the ECALL instruction Program execution continues with the instruction at this address The subroutine may therefore begin anywhere in the full 16 Mbyte memory space Flags OV N 2 Example The stack pointer contains 07H and the label SUBRTN is assigned to program memory location 123456H After executing the instruction ECALL SUBRTN at location 012345H SP contains on chip RAM locations 08H 09H and contain 01H 23H and 45H respectively and the PC contains 123456H Variations ECALL addr24 A 61 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Bytes States Encoding Hex Code in Operation ECALL DRk Bytes States Encoding Hex Code in Operation EJMP dest Function Description Flags A 62 intel Binary Mode Source Mode 5 4 14 13 1001 1010 23 addr15 addr8 7 16 Binary Mode A5 Encoding Source Mode Encoding ECALL PC 4 SP lt SP 1 PC 23 16 SP 1 15 8 SP 1 7 0 addr 23 0 0 9 1 Binary Mode Source Mode 3 2 12 11 1001 1001 uuuu Binary Mode A5 Encoding Source Mode Encoding ECALL PC lt PC 4 SP SP 1 SP lt
366. ore the 16 bit comparison value or captured value for the corresponding compare capture modules In the PWM mode the low byte register controls the duty cycle of the output waveform 7 0 High Low Byte of Compare Capture Values Bit Bit Number Mnemonic Function 7 0 CCAPxH 7 0 High byte of PCA comparison or capture values CCAPxL 7 0 Low byte of PCA comparison or capture values 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel x 0 4 Address CCAPMO S DAH CCAPM1 S DBH CCAPM2 S DCH S DDH CCAPM4 S DEH Reset State X000 0000B PCA Compare Capture Module Mode Registers These five registers select the operating mode of the corresponding compare capture module Each register also contains an enable interrupt bit ECCFx for generating an interrupt request when the module s compare capture flag CCFx in the CCON register is set See Table 11 3 in Chapter 11 for mode select bit combinations 7 0 MATx TOGx PWMx ECCFx Bn Bit Function Number Mnemonic 7 Reserved The value read from this bit is indeterminate Write a zero to this bit 6 ECOMx Compare Modes ECOMx 1 enables the module comparator function The comparator is used to implement the software timer high speed output pulse width modulation and watchdog timer modes 5 CAPPx Capture
367. ory The reset value of DPXL is 01H 3 12 82930 MEMORY PARTITIONS intel 3 3 2 3 Extended Stack Pointer SPX D word register DROO is the stack pointer SPX Figure 3 8 The byte at location 63 is the 8 bit stack pointer SP in the MCS 51 architecture The byte at location 62 is the stack pointer high SPH The two bytes allow the stack to extend to the top of memory region 00 SP and SPH can be accessed as SFRs Two instructions PUSH and POP directly address the stack pointer Subroutine calls ACALL ECALL LCALL and returns ERET RET RETI also use the stack pointer To preserve the stack do not use DR60 as a general purpose register Table 3 3 Dedicated Registers in the Register File and their Corresponding SFRs Register File SFRs Name Mnemonic Reg Location Mnemonic Address 60 Stack 61 Z Pointer DR60 SPX Stack Pointer High SPH 62 SPH S BEH Stack Pointer Low SP 63 SP 5 81 Data Pointer Extended High DPXH 56 DPXH S 85H Data Data Pointer Extended Low DPXL 57 DPXL S 84H edd Data Pointer High DPH bis 58 DPH S 83H ata Pointer Hi DPTR 9 Data Pointer Low DPL 59 DPL 5 82 Accumulator A Register A R11 11 ACC 5 B Register B R10 10 B S FOH 3 4 SPECIAL FUNCTION REGISTERS SFRS The special function registers SFRs reside in their associated on chip peripherals or in the core T
368. oscillator hardware setup 13 1 On chip RAM 3 8 bit addressable 3 8 5 10 bit addressable in MCS 51 architecture 5 10 idle mode 14 4 MCS 51 architecture 3 2 3 4 reset 13 6 ONCE mode 14 1 14 7 entering 14 7 exiting 14 7 Opcodes for binary and source modes 4 11 5 1 map A 4 binary mode 4 12 source mode 4 13 See also Binary and source modes ORL instruction 5 9 5 10 for bits A 24 ORL instruction 5 10 for bits A 24 Oscillator 2 7 at startup 13 6 intel during reset 13 5 on chip 13 2 ONCE mode 14 7 powerdown mode 14 5 14 6 OV bit 5 16 5 17 Overflow See OV bit P P bit 5 16 3 15 9 2 C 2 C 21 3 15 9 2 2 22 2 3 15 9 2 2 23 P3 3 15 9 2 2 24 Page mode 2 6 address access time 15 6 bus cycles See External bus cycles page mode configuration 4 6 design example 15 13 15 19 port pin status 15 11 PAGE bit 4 6 Parity See P bit PCA compare capture modules 11 1 idle mode 14 4 pulse width modulation 11 10 SFRs 3 16 C 4 timer counter 11 1 watchdog timer 11 1 11 9 PCON 3 15 12 7 14 1 14 2 14 5 C 2 C 25 idle mode 14 4 powerdown mode 14 6 reset 13 5 Peripheral cycle 2 7 Phase and phase 2 2 7 Pin conditions 14 3 Pins unused inputs 13 2 Pipeline 2 6 POP instruction 3 13 5 10 A 23 Port 0 9 2 pullups 9 7 structure 9 3 See also External bus Port 1 9 2 structure 9 3 Port 2 9 2 INDEX structure 9 4 See also Ext
369. output for the clock out mode 2 Timer 2 External Input In timer 2 capture mode falling edge P1 1 initiates a capture of the timer 2 registers In auto reload mode a falling edge causes the timer 2 registers to be reloaded In the up down counter mode this signal determines the count direction high up low down 0 External Interrupts 1 0 These inputs set the IE1 0 interrupt flags P3 3 2 the TCON register TCON bits IT1 0 select the triggering method IT1 0 1 selects edge triggered high to low IT1 0 0 selects level triggered active low INT1 0 also serves as external run control for timer 1 0 when selected by TCON bits GATE1 0 T1 0 Timer 1 0 External Clock Inputs When timer 1 0 operates as 3 5 4 counter falling edge on the 1 0 pin increments the count 10 3 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel 10 3 TIMER 0 Timer 0 functions as either a timer or event counter in four modes of operation Figures 10 2 10 3 and 10 4 show the logical configuration of each mode Timer 0 is controlled by the four low order bits of the TMOD register Figure 10 5 and bits 5 4 1 and 0 of the TCON register Figure 10 6 The TMOD register selects the method of timer gat ing GATEO timer or counter operation and mode of operation M10 and The TCON register provides timer 0 control functions overflow flag TFO run control
370. ower case may be used An input voltage level equal to or less than the maximum value of an output voltage level equal to or less than the maximum value of Vo See data sheet for values An input voltage level equal to or greater than the minimum value of an output voltage level equal to or greater than the minimum value of See data sheet for values 1 3 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Numbers Register Bits Register Names Reserved Bits Set and Clear Signal Names Units of Measure 1 4 Hexadecimal numbers are represented by string of hexadecimal digits followed by the character H Decimal and binary numbers are represented by their customary notations That is 255 is a decimal number and 1111 1111 is a binary number In some cases the letter B is added for clarity Bit locations are indexed by 7 0 for byte registers 15 0 for word registers ands 31 0 for double word dword registers where bit 0 is the least significant bit and 7 15 or 31 is the most significant bit An individual bit is represented by the register name followed by a period and the bit number For example PCON 4 is bit 4 of the power control register In some discussions bit names are used For example the name of PCON 4 is POF the power off flag Register names are shown in upper case For example PCON is the power control register If register name contains a lowercase
371. own mode Glossary 4 The mode in which a device or component recognizes high level logic one or a low level logic zero of an input signal as the assertion of that signal See also edge triggered Least significant bit of a byte or least significant byte of a word An interrupt that can be disabled masked by its individual mask bit in an interrupt enable register AII 82930A interrupts except the software trap TRAP are maskable Most significant bit of a byte or most significant byte of a word A bus on which the data is time multiplexed with some of the address bits A field effect transistor with an n type conducting path channel Semiconductor material with introduced impurities doping causing it to have an excess of negatively charged carriers An interrupt that cannot be disabled masked The software trap TRAP is the 82930A s only nonmaskable interrupt A transistor consisting of one part p type material and two parts n type material One time programmable read only memory a version of EPROM A field effect transistor with a p type conducting path Semiconductor material with introduced impurities doping causing it to have an excess of positively charged carriers Program counter A part of memory where instructions can be stored for fetching and execution The power conservation mode that freezes both the core clocks and the peripheral clocks intel PWM rel reser
372. peration RLC A Function Description Flags A 120 RETI PC 15 8 SP SP lt SP 1 PO 7 0 SP SP lt SP 1 PC 23 16 lt SP SP SP 1 PSW1 lt SP SP lt SP 1 Rotate accumulator left Rotates the eight bits in the accumulator one bit to the left Bit 7 is rotated into the bit 0 position CY AC OV N 2 accumulator contains 0C5H 11000101 After executing the instruction RLA the accumulator contains 8BH 10001011B the CY flag is unaffected Binary Mode Source Mode 1 1 1 1 0010 0011 Binary Mode Encoding Source Mode Encoding RL 1 lt 0 lt 7 Rotate accumulator left through the carry flag Rotates the eight bits in the accumulator and the CY flag one bit to the left Bit 7 moves into the CY flag position and the original state of the CY flag moves into bit O position OV intel Example Bytes States Encoding Hex Code in Operation RRA Function Description Flags Example Bytes States Encoding Hex Code in Operation RRCA INSTRUCTION SET REFERENCE The accumulator contains 0C5H 11000101B and the CY flag is clear After executing the instruction RLCA the accumulator contains 8AH 10001010B and the CY flag is set Binary Mode Source Mode 1 1 1 1
373. ple Variations ADDC A data Bytes Source Mode Encoding ADD Rm lt Rm DRk Add with carry Simultaneously adds the specified byte variable the CY flag and the accumulator contents leaving the result in the accumulator If there is a carry out of bit 7 CY the CY flag is set if there is a carry out of bit 3 AC the AC flag is set When adding unsigned integers the CY flag indicates that an overflow occurred If there is a carry out of bit 6 but not out of bit 7 or a carry out of bit 7 but not bit 6 the OV flag is set When adding signed integers the OV flag indicates a negative number produced as the sum of two positive operands or a positive sum from two negative operands Bit 6 and bit 7 in this description refer to the most significant byte of the operand 8 16 or 32 bit Four source operand addressing modes are allowed register direct register indirect and immediate y AC V OV y The accumulator contains 11000011B register 0 contains OAAH 10101010B and the CY flag is set After executing the instruction ADDC A RO the accumulator contains 6EH 01101110 the AC flag is clear and the CY and OV flags are set Source Mode 2 Binary Mode 2 A 33 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL States Encoding Hex Code in Operation ADDC A dir8 Bytes States Encoding Hex Code in Ope
374. point to the origin of the last data set the position of the read marker so that the SIU can reread the last set for retransmission Hardware clears this bit after the read pointer is reversed Setting this bit is effective only when the ADV RM ATM and CLR bits are all clear Figure 7 6 TXCONx USB Transmit FIFO Control Register Endpoint x 7 9 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL 7 10 Table 7 7 TXCONx Addresses and Reset Values Register Address Reset Value TXCONO S 9AH 0XXX0000B 1 5 9 0XXX0000B TXCON2 S 9CH 0XXX0000B TXCON3 S 9DH 0XXX0000B In tel intel UNIVERSAL SERIAL BUS TXFLGx Address See Table 7 8 0 3 Reset State See Table 7 8 USB Transmit FIFO Flag Register Endpoint x The bits in this register provide information on the data in the FIFO 2 0 FIF1 FIFO EMPTY FULL URF OVF Bit Bit Function 7 6 FIF1 0 FIFO Index Flags These read only flags indicate which data sets are present in the TXFIFO see Table 7 3 The FIF bits are updated after each write to TXCNTx to reflect the addition of a data set Likewise after the read marker is advanced because a set is no longer needed FIF1 or FIFO is cleared to indicate that the set is effectively discarded the bit is cleared whether the read marker is advanced by software setting ADV RM o
375. presented in this section are intended to demonstrate timer setup and do not repre sent the only arrangement nor necessarily the best arrangement for a given task These examples employ timer O but timer 1 can be set up in the same manner using the appropriate registers 10 5 1 Auto load Setup Example Timer 0 can be configured as an eight bit timer TLO with automatic reload as follows 1 Program the four low order bits of the TMOD register Figure 10 5 to specify mode 2 for timer 0 0 to select Fosc 12 as the timer input and GATEO 0 to select TRO as the timer run control 2 Enter an eight bit initial value ng in timer register TLO so that the timer overflows after the desired number of peripheral cycles 3 Enter an eight bit reload value ng in register THO This can be the same as no different depending on the application 4 Set the TRO bit in the TCON register Figure 10 6 to start the timer Timer overflow occurs after FFH 1 ng peripheral cycles setting the flag and loading into TLO from THO When the interrupt is serviced hardware clears TFO 10 9 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel 5 The timer continues to overflow and generate interrupt requests every FFH 1 peripheral cycles 6 To halt the timer clear the TRO bit 10 5 2 Pulse Width Measurements For timer 0 and timer 1 setting GATEx and TRx allows an external waveform at pin INTx t
376. pt request if the ECF interrupt enable bit in CMOD is set CF can be set by hardware or software but can be cleared only by software CR PCA Timer Counter Run Control Bit Set and cleared by software to turn the PCA timer counter on and off Reserved The value read from this bit is indeterminate Write a zero to this bit 4 0 CCF4 0 PCA Module Compare Capture Flags Set by hardware when a match or capture occurs This generates a PCA interrupt request if the ECCFx interrupt enable bit in the corresponding register is set Must be cleared by software 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel CH CL Address S F9H S E9H Reset State 0000 0000B CH CL Registers These registers operate in cascade to form the 16 bit PCA timer counter 7 0 High Low Byte PCA Timer Counter Bit Bit Function 7 0 7 0 High byte of the timer counter CL 7 0 Low byte of the PCA timer counter intel REGISTERS CMOD Address S D9H Reset State 00 X000B PCA Timer Counter Mode Register Contains bits for selecting the PCA timer counter input disabling the PCA timer counter during idle mode enabling the PCA WDT reset output module 4 only and enabling the PCA timer counter overflow interrupt CIDL WDTE CPS1 CPSO ECF Bit Bit 2 Function Number Mnemo
377. pter describes the external memory interface and the external bus cycles Examples illus trate several types of external memory designs 15 1 OVERVIEW The external memory interface comprises the external bus ports 0 and 2 and the bus control sig nals Chip configuration bytes Chapter 4 Device Configuration determine several interface options page mode or nonpage mode for external code fetches the number of external address bits 16 17 or 18 the address ranges for RD WR and PSEN and the number of external wait states You can use these options to tailor the interface to your application See Configuring the External Memory Interface in Chapter 4 Device Configuration The external memory interface operates in either page mode and nonpage mode Page mode pro vides increased performance by reducing the time for external code fetches Page mode does not apply to code fetches from on chip memory The reset routine configures the 82930A for opera tion in page mode or nonpage mode according to bit 1 of configuration bytes UCONFIGO Figure 15 1 shows the structure of the external address bus for page and nonpage mode operation PO carries address A7 0 while P2 carries address A15 8 Data D7 0 is multiplexed with A7 0 on PO in nonpage mode and with A15 8 on P2 in page mode Table 15 1 describes the external memory interface signals The address and data signals AD7 0 on port 0 and A15 8 on port 2 are defined for nonpage mode
378. r WRj A memory location 00 0000H 00 FFFFH addressed indirectly through word register WRO WR30 gt Data RAM location 00 0000H 00 FFFFH addressed indirectly dis16 through a word register WRO WR30 displacement value where the displacement value is from 0 to 64 Kbytes j jd js Word register index jd js 0 30 tttt Binary representation of j or jd TTTT Binary representation of js DRk Dword register DRO DR4 DR28 DR56 DR60O of the currently selected register file DRkd Destination Register DRks Source Register DRk memory location 00 0000H FF FFFFH addressed Indirectly through dword register DRO DR28 DR56 DR60 DRk Data RAM location 00 0000H FF FFFFH addressed indirectly dis24 through a dword register DRO DR28 DR56 DR60 displacement value where the displacement value is from 0 to 64 Kbytes k kd ks Dword register index kd ks 0 4 8 28 56 60 uuuu Binary representation of k or kd UUUU Binary representation of ks A 2 INSTRUCTION SET REFERENCE Table A 2 Notation for Direct Addresses Direct na 82930A MCS 51 Address Description Arch Arch dir8 An 8 bit direct address This can be a memory address v v 00 0000 00 007 or an SFR address S 00H S FFH dir16 16 bit memory address 00 0000H 00 FFFFH used in direct v addressing Table A 3 Notation for Immediate Addressing
379. r automatically by hardware ATM 1 The next state table for FIF bits is shown below FIF 1 0 Operation Flag NextFIF 1 0 Next Flag 00 Wr X 01 Unchanged 01 Wr X 11 Unchanged 10 Wr X 11 Unchanged 11 WrTXCNTx X 11 OVF 1 00 ADV RM X 00 Unchanged 01 ADV RM X 00 Unchanged 11 ADV RM X 10 01 Unchanged 10 ADV RM X 00 Unchanged X REV RP X Unchanged Unchanged 5 4 Reserved Values read from these bits are indeterminate Write zeros to these bits 3 EMPTY TXFIFO Empty Flag Hardware sets this bit when the write pointer is at the same location as read pointer Hardware clears this bit when the pointers are at different locations Software can read and write this bit 2 FULL TXFIFO Full Flag Hardware sets this bit after a byte is written to TXFIFO when the write pointer is one location below the read marker Hardware clears this bit when this condition no longer holds Software can read and write this bit 1 URF TXFIFO Underrun Flag Hardware sets this bit when the SIU reads a byte from an empty FIFO Hardware does not clear this bit Software can read and write this bit 0 OVF TXFIFO Overrun Flag This bit is set when the 82930A writes an additional byte to a full FIFO or writes byte count to with FIF1 0 11 Hardware does not clear this bit Software can read and write this bit Figure 7 7 TXFLGx USB Transmit FIFO Flag Register 82930A
380. r for the system clock and provides power on reset Control signals and Ports 0 1 2 and 3 are not shown See section 13 3 Clock Sources and section 13 4 4 Power on Reset 82930A PLLSEL1 PLLSEL2 A4291 01 Figure 13 1 Minimum Setup NOTE Use PLLSEL1 PLLSEL2 to select the 82930A operating frequency See Table 2 1 13 1 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel 13 2 ELECTRICAL ENVIRONMENT 82930A is a high speed CHMOS device To achieve satisfactory performance its operating environment should accommodate the device signal waveforms without introducing distortion or noise Design considerations relating to device performance are discussed in this section See the device data sheet for voltage and current requirements operating frequency and waveform tim ing 13 2 1 Power and Ground Pins Power the 82930A from a well regulated power supply designed for high speed digital loads Use short low impedance connections to the power and ground V pins 13 2 2 Unused Pins To provide stable predictable performance connect unused input pins to Vs or Voc Untermi nated input pins can float to a mid voltage level and draw excessive current Unterminated inter rupt inputs may generate spurious interrupts 13 2 3 Noise Considerations The fast rise and fall times of high speed CHMOS logic may produce noise spikes on the power supply lines and signal outputs
381. r increments every 1000 nanoseconds Fosc 4 Provides clock pulses at 81 2 S3P2 and S5P2 of every peripheral cycle With Fosc 12 MHz the time counter increments every 333 1 3 nanoseconds Timer 0 overflow The CL register is incremented at S5P2 of the peripheral cycle when timer 0 overflows This selection provides the PCA with a programmable frequency input External signal on P1 2 ECI The CPU samples the ECI pin at S1P2 S3P2 and S5P2 of every peripheral cycle The first clock pulse 51 2 S3P2 or S5P2 that occurs following a high to low transition at the ECI pin increments the CL register The maximum input frequency for this input selection is 8 For a description of peripheral cycle timing see section 2 3 2 Clock and Reset Unit Setting the run control bit CR in the CCON register turns the PCA timer counter on if the out put of the NAND gate Figure 11 1 equals logic 1 The PCA timer counter continues to operate during idle mode unless the CIDL bit of the CMOD register is set The CPU can read the contents of the CH and CL registers at any time However writing to them is inhibited while they are counting i e when the CR bit is set 11 2 intel PROGRAMMABLE COUNTER ARRAY Compare Capture Modules 1 3 P 4 CEXt iia 2 ee P1 5 CEX2 __ 3 1 6 Module 4 1 7 16 Bits A17 Fosc 12 00 OSC 01 Interrupt Fosc 4 CH CL Requ
382. r page mode it places UCONFIGO on P2 as D7 0 overwriting A15 8 FFH If external memory is set up for nonpage mode 15 8 is not overwritten The 82930A examines P2 bit 1 Subsequent configuration byte fetches are in page mode if P2 1 0 and nonpage mode if P2 1 1 The 82930 fetches UCONFIGO again states 5 8 in Figure 15 11 and then UCONFIGI via internal address FF FFF9H The configuration byte bus cycles always execute with ALE extended and one wait state 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel State 1 State 2 State 3 State 4 State 5 State 6 State 7 State 8 m SYS UN ALE PSEN PO A7 0 Ai8 FFH A538 FFH Page Mode i i 2 A15 8 FFH Nonpage Mode 4228 01 Figure 15 11 Configuration Byte Cycles 15 5 PORT 0 AND PORT 2 STATUS This section summarizes the status of the port 0 and port 2 pins when these ports are used as the external bus A more comprehensive description of the ports and their use is given in Chapter 9 Input Output Ports When port 0 and port 2 are used as the external memory bus the signals on the port pins can orig inate from three sources the 82930A address bits data bits the port SFRs PO and P2 logic levels anexternal device data bits The port 0 pins but not the port 2 pins can also be held in a high impedance state Table 15 3 lists the status of the por
383. ration 0 the timer register counts the divided down system clock The timer register is incremented once every peripheral cycle i e once every six states see section 2 3 2 Clock and Reset Unit Since six states equals 12 clock cycles the timer clock rate is Fosc 2 Exceptions are the timer 2 baud rate and clock out modes where the timer register is incremented by the system clock divided by two For counter operation 1 the timer register counts the negative transitions on the Tx ex ternal input pin The external input is sampled during every S5P2 state Clock and Reset Unit in Chapter 2 describes the notation for the states in a peripheral cycle When the sample is high in one cycle and low in the next the counter is incremented The new count value appears in the register during the next S3P1 state after the transition was detected Since it takes 12 states 24 oscillator periods to recognize a negative transition the maximum count rate is 1 24 of the os cillator frequency There are no restrictions on the duty cycle of the external input signal but to ensure that a given level is sampled at least once before it changes it should be held for at least one full peripheral cycle Table 10 2 External Signals Signal Name Multiplexed Type Description With T2 lO Timer 2 Clock Input Output This signal is the external clock input P1 0 for the timer 2 capture mode and it is the timer 2 clock
384. ration ADDC A Ri Bytes States Encoding Hex Code in Operation ADDC A Rn Bytes States Encoding Hex Code in Operation A 34 0011 0100 immed data Binary Mode Encoding Source Mode Encoding ADDC lt A CY data Binary Mode Source Mode 2 2 11 11 Tlf this instruction addresses a port x 0 3 add 1 state 0011 0101 direct addr Binary Mode Encoding Source Mode Encoding ADDC A A CY dir8 Binary Mode Source Mode 1 2 2 3 0011 011i Binary Mode Encoding Source Mode A5 Encoding ADDC A lt A Ri Binary Mode Source Mode 1 2 1 2 0011 Binary Mode Encoding Source Mode A5 Encoding ADDC A CY Rn intel AJMP addr11 Function Description Flags Example Bytes States Encoding Hex Code in Operation INSTRUCTION SET REFERENCE Absolute jump Transfers program execution to the specified address which is formed at run time by concatenating the upper five bits of the PC after incrementing the PC twice opcode bits 7 5 and the second byte of the instruction The destination must therefore be within the same 2 Kbyte page of program memory as the first byte of the instruction following AJMP OV N 2 The label JMPADR
385. receive Operations on page 8 27 This sec tion provides an overview Two bits in RXCONx have a major influence on the receive operation The ISO bit RXCONx 3 determines whether the reception is for isochronous data ISO 1 or non isochronous data ISO 0 For non isochronous data only the SIU sends handshake to the host checks the sequence bit and generates a receive done RXD interrupt Also for non isochronous data the post receive routine is an ISR for isochronous data the post receive routine can be a normal subroutine or ISR that is initiated by an SOF token The ARM bit RXCONx 2 determines whether the FIFO write marker and write pointer are managed automatically by the FIFO hardware ARM 1 or manually by the firmware routine ARM 0 intel USB OPERATING MODES Firmware Hardware SIU FIFO OUT Token Post receive routine Receive data over USB XD Int ISO 0 SOF Token ISO 1 If ARM 1 Adjust FIFO write marker and pointer ISR ISO 0 Check status and read data If ARM 0 Adjust FIFO write marker and pointer If ISO 0 Send host hshk Adjust SEQ bit Generate RXDx Done interrupt RETI ISO 0 RET RETI ISO 1 A4265 01 Figure 8 14 High level View of Receive Operations 8 3 2 SIU Receive Operations This section describes the SIU receive operations shown on the right side of Figure 8 14 8 3 2 1 SIU Receive Non isochronous Data Figur
386. resses a port Px x 0 3 add 1 state Encoding 1011 1110 5555 0001 dir addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CMP Rm dir8 CMP WRij dir8 A 49 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 1011 1110 tttt 0101 dir addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CMP WRj dir8 CMP 16 Binary Mode Source Mode Bytes 5 4 States 3 2 Encoding 1011 1110 5555 0011 dir dir Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CMP Rm dir16 CMP WRj dir16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding 1011 1110 tttt 0111 dir addr dir addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CMP WRj dir16 CMP Rm WRj Binary Mode Source Mode Bytes 4 3 States 3 2 Encoding 1011 1110 tttt 1001 ssss 0000 Hex Code in Binary Mode A5 Encoding A 50 Source Mode Encoding intel INSTRUCTION SET REFERENCE Operation CMP Rm WRi CMP Rm DRk Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 1011 1110 uuuu 1011 5855 0000 Hex Code in Binary Mode A5 Encoding Source Mode
387. resses for binary compatible code or with the external bus configured for extended memory ad dressing 17 bit or 18 bit External data memory transfers use an 8 16 17 or 18 bit address bus depending on the in struction and the configuration ofthe external bus Table 9 2 lists the instructions that can be used for the these bus widths Table 9 2 Instructions for External Data Moves Bus Width Instructions 8 MOVX Ri MOV Rm MOV 16 MOVX DPTR MOV WRj MOV WRi dis MOV dir16 17 MOV DRk MOV DRk dis 18 MOV DRk MOV DRk dis NOTE Avoid MOV instructions for external memory accesses These instructions can corrupt input code bytes at port 0 External signal ALE address latch enable facilitates external address latch capture The address byte is valid after the ALE pin drives For write cycles valid data is written to port 0 just prior to the write WR pin asserting Data remains valid until WR is undriven For read cycles data returned from external memory must appear at port 0 before the read pin is undriven refer to the 82930A datasheet for specifications Wait states by definition affect bus timing 9 7 intel 10 Timer Counters and Watchdog Timer intel CHAPTER 10 TIMER COUNTERS AND WATCHDOG TIMER This chapter describes the timer counters and the watchdog timer WDT included as peripherals on the 82930A When operating as a timer a timer cou
388. rflows The WDT starts over at 0 If the WDT overflows it initiates a device reset see section 13 4 Reset Device reset clears the WDT and disables it 10 7 3 WDT During Idle Mode Operation of the WDT during the power reduction modes deserves special attention The WDT continues to count while the microcontroller is in idle mode This means the user must service the WDT during idle One approach is to use a peripheral timer to generate an interrupt request when the timer overflows The interrupt service routine then clears the WDT reloads the peripheral timer for the next service period and puts the microcontroller back into idle 10 7 4 WDT During PowerDown The powerdown mode stops all phase clocks This causes the WDT to stop counting and to hold its count The WDT resumes counting from where it left off if the powerdown mode is terminated by INTO INTI To ensure that the WDT does not overflow shortly after exiting the powerdown mode clear the WDT just before entering powerdown The WDT is cleared and disabled if the powerdown mode is terminated by a reset 10 18 intel 1 Programmable Counter Array 11 PROGRAMMABLE COUNTER ARRAY This chapter describes the programmable counter array PCA an on chip peripheral of the 82930A that performs a variety of timing and counting operations including pulse width modu lation PWM The PCA provides the capability for a software watchdog timer WDT 11 1 PCA D
389. ring the time the RXFIFO is empty causes the URF flag in RXFLGx to be set Always read the FIF bits to determine if data is present in the RXFIFO The RXFLGx FIF bits are updated after RXCNTX is written at the end of the receive operation Table 7 12 RXCNTx Addresses and Reset Values Register Address Reset Value RXCNTO S F4H XXH RXCNT1 S F5H XXH RXCNT2 S F6H XXH RXCNT3 S F7H XXH 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel RXCONx x 0 3 Address See Table 7 13 Reset State See Table 7 13 CLR FFRC l ISO ARM ADV WM REV WP Bit Number Bit Mnemonic Function CLR Clear the FIFO Software sets this bit to flush the entire FIFO flags in RXFLGx revert to their reset states EMPTY is set all other flags clear The ARM and ISO bits are not affected by this operation Hardware clears this bit when the flush operation is completed 6 5 Reserved Values read from these bits are indeterminate Write zeros to these bits FFRC FIFO Read Complete Software sets this bit to signal when a data set read is complete Setting this bit clears the FIF bit corresponding to the data set that was just read Hardware clears this bit after the FIF bit is cleared ISO Isochronous Data Type Software sets this bit to indicate that RXFIFOx is programmed to receive isochronous data and to set up the USB Interface to
390. rity interrupts 1 sampled within the same four state interrupt cycle is determined by a hardware priority within level resolver see Table 6 6 Table 6 6 Interrupt Priority Within Level Priority Number Interrupt Name 1 Highest Priority INTO 2 Timer 0 3 INT1 4 Timer 1 5 Serial Port 6 Timer 2 7 PCA 8 USB Transmit Receive Done 9 USB EP1 Transmit Receive Done 10 USB EP2 Transmit Receive Done 11 Lowest Priority USB Transmit Receive Done intel INTERRUPTS IPHO Address S B7H Reset State X000 0000B 7 0 m IPHO 6 IPHO 5 IPHO 4 IPHO 3 IPHO 2 IPHO 1 0 0 faite Function 7 Reserved The value read from this bit is indeterminate Write a zero to this bit 6 IPHO 6 PCA Interrupt Priority Bit High 5 0 5 Timer 2 Overflow Interrupt Priority Bit High 4 IPHO 4 Serial I O Port Interrupt Priority Bit High 3 IPHO 3 Timer 1 Overflow Interrupt Priority Bit High 2 IPHO 2 External Interrupt 1 Priority Bit High 1 IPHO 1 Timer 0 Overflow Interrupt Priority Bit High 0 0 0 External Interrupt 0 Priority Bit High Figure 6 6 IPHO Interrupt Priority High Register 0 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel IPLO Address S B8H
391. rn timer 1 on off 5 TFO Timer 0 Overflow Flag Set by hardware when the timer 0 register overflows Cleared by hardware when the processor vectors to the interrupt routine 4 TRO Timer 0 Run Control Bit Set cleared by software to turn timer 1 on off 3 IE1 Interrupt 1 Flag Set by hardware when an external interrupt is detected on the INT1 pin Edge or level triggered see IT1 Cleared when interrupt is processed if edge triggered 2 IT1 Interrupt 1 Type Control Bit Set this bit to select edge triggered high to low for external interrupt 1 Clear this bit to select level triggered active low 1 IEO Interrupt 1 Flag Set by hardware when an external interrupt is detected on the INTO pin Edge or level triggered see ITO Cleared when interrupt is processed if edge triggered 0 ITO Interrupt O Type Control Bit Set this bit to select edge triggered high to low for external interrupt 0 Clear this bit to select level triggered active low C 44 intel REGISTERS TMOD Address 5 89 Reset State 0000 0000B Timer Counter Mode Control Register Contains mode select run control select and counter timer select bits for controlling timer 0 and timer 1 7 0 GATE1 C T1 M11 01 GATEO 10 Moo Bit Bit Function Number Mnemonic unctio 7 GATE1 Timer 1 Gate When GATE 1 0 run control bit TR1 gates the input signal
392. row flag if a borrow is needed for bit 7 and clears CY otherwise If CY was set before executing a SUBB instruction this indicates that a borrow was needed for the previous step in a multiple precision subtraction so the CY flag is subtracted from the accumulator along with the source operand AC is set if a borrow is needed for bit 3 and cleared otherwise OV is set if a borrow is needed into bit 6 but not into bit 7 or into bit 7 but not bit 6 When subtracting signed integers the OV flag indicates a negative number produced when a negative value is subtracted from a positive value or a positive result when a positive number is subtracted from a negative number Bit 6 and bit 7 in this description refer to the most significant byte of the operand 8 16 or 32 bit The source operand allows four addressing modes register direct register indirect or immediate OV N 2 V V V The accumulator contains OC9H 11001001B register 2 contains 54H 01010100B and the CY flag is set After executing the instruction 131 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Variations SUBB data Bytes States Encoding Hex Code in Operation SUBB A dir8 Bytes States Encoding Hex Code in Operation SUBB A Ri Bytes States Encoding Hex Code in Operation A 132 SUBB A R2 intel the accumulator contains 74H 01110100B the
393. ry Mode Source Bytes 3 3 States 3t 3t tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 0111 0101 direct addr immed data Hex Code in Binary Mode Encoding Source Mode Encoding Operation MOV dir8 lt data MOV Ri data Binary Mode Source Mode Bytes 2 3 States 3 4 Encoding 0111 011i immed data Hex Code in Binary Mode Encoding Source Mode A5 Encoding Operation MOV MOV Rn data Ri lt data Binary Mode Source Mode Bytes 2 3 States 1 2 Encoding 0111 irrrr immed data A 83 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Hex Code in Operation MOV dir8 dir8 Bytes States Encoding Hex Code in Operation MOV dir8 Ri Bytes States Encoding Hex Code in Operation MOV dir8 Rn Bytes States Encoding Hex Code in Operation MOV Ri dir8 A 84 Binary Mode Encoding Source Mode A5 Encoding MOV Rn data Binary Mode Source Mode 3 3 3 3 1000 0101 direct addr direct addr Binary Mode Encoding Source Mode Encoding MOV dir8 lt dir8 Binary Mode Source Mode 2 3 3 4 1000 011i direct addr Binary Mode Encoding Source Mode A5 Encoding MOV dir8 lt Ri Binary Mode Source Mode 2 3 2t 3t
394. ry flag is also affected by logical bit bit move multiply decimal adjust and some rotate and shift instructions see Table 5 10 6 AC Auxiliary Carry Flag The auxiliary carry flag is affected only by instructions that address 8 bit operands The AC flag is set if an arithmetic instruction with an 8 bit operand produces a carry out of bit 3 from addition or a borrow into bit 3 from subtraction Otherwise it is cleared This flag is useful for BCD arithmetic see Table 5 10 5 FO Flag 0 This general purpose flag is available to the user 4 3 RS1 0 Register Bank Select Bits 1 and 0 These bits select the memory locations that comprise the active bank of the register file registers RO R7 RS1 RSO Bank Address 0 0 0 00H 07H 0 1 1 08H 0FH 1 0 2 10H 17H 1 1 3 18H 1FH 2 OV Overflow Flag This bit is set if an addition or subtraction of signed variables results in an overflow error i e if the magnitude of the sum or difference is too great for the seven LSBs in 2 s complement representation The overflow flag is also set if a multiplication product overflows one byte or if a division by zero is attempted 1 UD User definable Flag This general purpose flag is available to the user 0 P Parity Bit This bit indicates the parity of the accumulator It is set if an odd number of bits in the accumulator are set Otherwise it is cleared Not all instructions update the parity bit The parity bit is
395. ry flag is set by an addition instruction ADD ADDO if there is a carry out of the MSB It is set by a subtraction SUB SUBB or compare CMP if a borrow is needed for the MSB The carry flag is also affected by logical bit bit move multiply decimal adjust and some rotate and shift instructions see Table 5 10 6 AC Auxiliary Carry Flag The auxiliary carry flag is affected only by instructions that address 8 bit operands The AC flag is set if an arithmetic instruction with an 8 bit operand produces a carry out of bit 3 from addition or a borrow into bit 3 from subtraction Otherwise it is cleared This flag is useful for BCD arithmetic see Table 5 10 5 FO Flag 0 This general purpose flag is available to the user 4 3 RS1 0 Register Bank Select Bits 1 and 0 These bits select the memory locations that comprise the active bank of the register file registers RO R7 RS1 RSO Bank Address 0 0 0 00H 07H 0 1 1 08H 0FH 1 0 2 10H 17H 1 1 3 18H 1FH 2 OV Overflow Flag This bit is set if an addition or subtraction of signed variables results in an overflow error i e if the magnitude of the sum or difference is too great for the seven LSBs in 2 s complement representation The overflow flag is also set if a multiplication product overflows one byte or if a division by zero is attempted 1 UD User definable Flag This general purpose flag is available to the user 0 P Parity Bit This bit indica
396. s 7 0 EA EC 2 ES ET ETO EXO Ho Function 7 EA Global Interrupt Enable Setting this bit enables all interrupts that are individually enabled by bits 0 6 Clearing this bit disables all interrupts except the TRAP interrupt which is always enabled 6 EC PCA Interrupt Enable Setting this bit enables the PCA interrupt 5 ET2 Timer 2 Overflow Interrupt Enable Setting this bit enables the timer 2 overflow interrupt 4 ES Serial I O Port Interrupt Enable Setting this bit enables the serial I O port interrupt 3 Timer 1 Overflow Interrupt Enable Setting this bit enables the timer 1 overflow interrupt 2 EX1 External Interrupt 1 Enable Setting this bit enables external interrupt 1 1 ETO Timer 0 Overflow Interrupt Enable Setting this bit enables the timer 0 overflow interrupt 0 EXO External Interrupt O Enable Setting this bit enables external interrupt 0 intel REGISTERS IE1 Address S B1H Reset State 00H Interrupt Enable 1 Register 7 0 IE1 3 IE1 2 IE1 1 IE1 0 Bit Bit Number Mnemonic Function 7 4 E Reserved Values read from these bits are indeterminate Write zeros to these bits 3 0 IE1 3 0 Interrupt Enable Endpoints 3 0 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel IPHO Address S B7H Reset State X000 0000B Interrup
397. s OV N 2 mE Example Set the CY flag if and only if P1 0 1 ACC 7 1 or OV 0 MOV CY P1 0 LOAD CARRY WITH INPUT PIN P10 ORL CY ACC 7 OR CARRY WITH THE ACC BIT 7 ORL CY OV CARRY WITH THE INVERSE OF Variations ORL CY bit51 Binary Mode Source Mode Bytes 2 2 States 11 11 tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 0111 0010 bit addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation ORL lt CY V bit51 ORL CY bit51 Binary Mode Source Mode Bytes 2 2 States 11 1 tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 1010 0000 bitaddr Hex Code in Binary Mode Encoding Source Mode Encoding Operation ORL CY lt CY bit51 ORL CY bit Binary Mode Source Mode Bytes 4 3 States 31 21 tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 1010 1001 0111 0 yyy direct addr 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ORL lt CY V bit ORL CY bit Binary Mode Source Mode Bytes 4 3 States 3t 21 tlf this instruction addresses a port Px x 0 3 add 1 state Encoding 1010 1001 1110 0 yyy direct addr Hex Code in Binary Mode A5 Encoding Source Mode
398. s Encoding Hex Code in Operation MOV GRi A Bytes States Encoding Hex Code in Operation MOV Rn A Bytes A 86 Binary Mode Source Mode 1 2 1 2 1110 drrr Binary Mode Encoding Source Mode A5 Encoding MOV lt Rn Binary Mode Source Mode 2 2 2t 2t tlf this instruction addresses a port Px x 0 3 add 1 state 14 1 0101 direct addr Binary Mode Encoding Source Mode Encoding MOV dir8 lt A Binary Mode Source Mode 1 2 3 4 1111 011i Binary Mode Encoding Source Mode A5 Encoding MOV Ri lt Binary Mode Source Mode 1 2 intel INSTRUCTION SET REFERENCE States 1 2 Encoding 1111 111r Hex Code in Binary Mode Encoding Source Mode A5 Encoding Operation MOV Rn lt MOV Rmd Rms Binary Mode Source Mode Bytes 3 2 States 2 1 Encoding 0111 1100 5555 5555 Hex Code Binary Mode A5 Encoding Source Mode Encoding Operation MOV Rms MOV WRjd WRjs Binary Mode Source Mode Bytes 3 2 States 2 1 Encoding 0111 1101 tttt TTTT Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV WRjd lt WRjs MOV DRkd DRks Binary Mode Source Mode Bytes 3 2 States 3 2 Encoding 0111 1111 uuuu UUUU Hex Code in Binary Mode A5 E
399. s 7 Enterthe file number to tag the files you wish to download The BBS displays the approximate download time for tagged files 1 8 intel Introduction 2 INTRODUCTION 82930A is a peripheral interface chip for Universal Serial Bus USB applications It sup ports the connection of a PC peripheral such as a keyboard or a modem to a host PC via the USB The USB is specified by the Universal Serial Bus Specification Much of the material in this doc ument rests on this USB specification In the language of the USB specification the 82930 is a USB device USB device can serve as a function by providing an interface for a peripheral and it can serve as a hub by providing additional connections to the USB The 82930A described in this manual serves as a function but it does not serve as a hub Figure 2 1 shows the 82930A in a system using the USB Hub 82930A 82930A 82930 4 Function Function Function 4263 01 Figure 2 1 The 82930A in a System with a Universal Serial Bus 2 1 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel System Bus and I O Ports Peripheral Signals and 1 Ports P0 7 0 P2 7 0 P1 7 0 P3 7 0 o 9 Watchdog e ELS yo Bus Interface Code Bus 16 Instruction Sequencer oOo Timer Peripheral Interface amp Pca snm O OO 724 a v s
400. s Table 3 7 Serial I O SFRs Table 3 8 Timer Counter and Watchdog Timer SFRs Table 3 9 Programmable Counter Array SFRs Table 3 5 Core SFRs Mnemonic Name Address Accumulator S EOH Bt B Register S FOH PSW Program Status Word S DOH PSW1 Program Status Word 1 S D1H SP Stack Pointer LSB of SPX S 81H SPH Stack Pointer High MSB of SPX S BEH DPTR Data Pointer 2 bytes DPL Low Byte of DPTR S 82H High Byte of DPTR 5 83 DPXL Data Pointer Extended Low 5 84 DPXH Data Pointer Extended High S 85H PCON Power Control 5 87 IEO Interrupt Enable Control 0 S A8H IPHO Interrupt Priority Control High 0 S B7H IPLO Interrupt Priority Control Low 0 S B8H These SFRs can also be accessed by their corresponding registers in the register file see Table 3 3 Table 3 6 Port SFRs Mnemonic Name Address PO Port 0 5 80 1 Port 1 5 90 2 Port 2 S A0H P3 Port 3 S BOH 3 15 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Table 3 7 Serial I O SFRs intel Mnemonic Name Address SCON Serial Control 5 98 SBUF Serial Data Buffer 5 99 SADEN Slave Address Mask S B9H SADDR Slave Address S A9H Table 3 8 Timer Counter and Watchdog Timer SFRs Mnemonic Name Address TLO Timer Counter 0 Low Byte S 8AH THO Timer
401. s 56 63 are addressable only as dwords Registers ad dressed only by the names shown in Figure 3 6 except for the 32 registers that comprise the intel 82930A MEMORY PARTITIONS four banks of registers RO R7 which can also be accessed as locations 00 0000H 00 001FH in the memory space 3 3 2 Dedicated Registers The register file has four dedicated registers e R10 is the B register R11 is the accumulator ACC DR56is the extended data pointer DPX DR60 is the extended stack pointer SPX These registers are located in the register file however R10 R11 the DPXH DPXL DPH and DPL bytes in DR56 and the SPH and SP bytes in DR60 are also accessible as SFRs The bytes of DPX and SPX can be accessed in the register file only by addressing the dword registers The dedicated registers in the register file and their corresponding SFRs are illustrated in Figure 3 8 and listed in Table 3 3 3 3 2 1 Accumulator and B Register The 8 bit accumulator ACC is byte register R11 which is also accessible in the SFR space as ACC at 5 Figure 3 8 The register used in multiplies and divides is register R10 which is also accessible in the SFR space as B at S FOH Accessing ACC or B as a register is one state faster than accessing them as SFRs Instructions in the MCS 51 architecture use the accumulator as the primary register for data moves and calculations However the MCS 251 architecture any of registers 1
402. s 7EH on sequence DEC Rm Zshort Binary Mode Source Mode Bytes 3 2 States 2 1 Encoding 0001 1011 5555 01 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation DEC Rm Rm short DEC WRij short Binary Mode Source Mode Bytes 3 2 States 2 1 A 56 intel Encoding Hex Code in Operation INSTRUCTION SET REFERENCE 0001 1011 tttt 01 Binary Mode A5 Encoding Source Mode Encoding DEC lt WRj short DEC DRk short Bytes States Encoding Hex Code in Operation Binary Mode Source Mode 3 2 5 4 0001 1011 uuuu 11 Binary Mode A5 Encoding Source Mode Encoding DEC lt short DIV lt dest gt lt src gt Function Description Flags Variations Divide Divides the unsigned integer in the register by the unsigned integer operand in register addressing mode and clears the CY and OV flags For byte operands lt dest gt lt src gt Rmd Rms the result is 16 bits The 8 bit quotient is stored in the higher byte of the word where Rmd resides the 8 bit remainder is stored in the lower byte of the word where Rmd resides For example Register 1 contains 251 OFBH or 11111011B and register 5 contains 18 12H or 00010010B After executing the instruction DIV R1 R5 register 1 contains 13 OD
403. s bits on port 2 16 bit address It is possible in some situations to mix the two MOVX types A large RAM array with its upper address lines driven by P2 can be addressed via the data pointer or with code to output upper address bits to P2 followed by a MOVX instruction using RO or R1 OV N 2 The 82930 controller is operating in nonpage mode external 256 byte RAM using multiplexed address data lines e g an Intel 8155 RAM I O Timer is connected to port 0 Port 3 provides control lines for the external RAM ports 1 and 2 used for normal 1 RO and R1 contain 12H and 34H Location 34H of the external RAM contains 56H After executing the instruction sequence intel INSTRUCTION SET REFERENCE MOVX A R1 MOVX R0 A the accumulator and external RAM location 12H contain 56H Variations MOVX A DPTR Binary Mode Source Mode Bytes 1 1 States 5 5 Encoding 1110 0000 Hex Code in Binary Mode Encoding Source Mode Encoding Operation MOVX lt DPTR MOVX A Ri Binary Mode Source Mode Bytes 1 1 States 3 3 Encoding 1110 001i Hex Code in Binary Mode Encoding Source Mode A5 Encoding Operation MOVX lt Ri DPTR A Binary Mode Source Mode Bytes 1 1 States 5 5 Encoding 1111 0000 Hex Code in Binary Mode Encoding Source Mode Encoding Operation MOVX DPTR lt
404. s restored to the normal operating level There are two ways to exit the powerdown mode Generate an enabled external interrupt Hardware clears the PD bit in the PCON register which starts the oscillator and restores the clocks to the CPU and peripherals Execution resumes with the interrupt service routine Upon completion of the interrupt service routine program execution resumes with the instruction immediately following the instruction that activated powerdown mode NOTE To enable an external interrupt set the IE register EXO and or EXI bit s The external interrupt used to exit powerdown mode must be configured as level sensitive and must be assigned the highest priority In addition the duration of the interrupt must be of sufficient length to allow the oscillator to stabilize Generate a reset See section 13 4 Reset A logic high on the RST pin clears the PD bit in the PCON register directly and asynchronously This starts the oscillator and restores the clocks to the CPU and peripherals Program execution momentarily resumes with the instruction immediately following the instruction that activated powerdown and may continue for a number of clock cycles before the internal reset algorithm takes control Reset initializes the 82930A and vectors the CPU to address FF 0000H NOTE During the time that execution resumes the internal RAM cannot be accessed however it is possible for the port pins to be accessed To avoid unexpe
405. set or cleared by instructions that change the contents of the accumulator ACC Register R11 C 26 intel REGISTERS PSW1 Program Status Word 1 PSW1 contains bits that reflect the results of operations and bits that select the register bank for reg 7 isters RO R7 Address S D1H Reset State 0000 0000B RS1 RSO OV Z Bit Number Bit Mnemonic Function 7 Carry Flag Identical to the CY bit in the PSW register AC Auxiliary Carry Flag Identical to the AC bit in the PSW register Negative Flag This bit is set if the result of the last logical or arithmetic operation was negative Otherwise it is cleared 4 3 RS1 0 Register Bank Select Bits 0 and 1 Identical to the RS1 0 bits in the PSW register OV Overflow Flag Identical to the OV bit in the PSW register Zero Flag This flag is set if the result of the last logical or arithmetic operation is zero Otherwise it is cleared Reserved The value read from this bit is indeterminate Write a zero to this bit C 27 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel RCAP2H RCAP2L Address RCAP2H S CBH RCAP2L S CAH Reset State 0000 0000B Timer 2 Reload Capture Registers This register pair stores 16 bit values to be loaded into or captured from the timer register
406. sochronous data This bit must be cleared by software The SIU uses this bit to set up the handshake protocol at the end of a transmission 2 ATM Automatic Transmit Management Setting this bit causes the read pointer and read marker to be adjusted automatically as indicated ISO Status Read Pointer Read Marker X ACK Unchanged Advanced 0 Not ACK Reversed Unchanged 1 Not ACK Unchanged Advanced to origin of next data set to origin of the data set last read When this bit is set setting REV RP or ADV RM has no effect Software can read and write this bit hardware neither clears nor sets this bit 1 ADV RM Advance Read Marker Setting this bit advances the read marker to point to the origin of next data set the position of the read pointer to prepare for the next transmission Hardware clears this bit after the read marker is advanced Setting this bit is effective only when the REV RP and CLR bits are all clear 0 REV RP Reverse Read Pointer Setting this bit reverses the read pointer to point to the origin of the last data set the position of the read marker so that the SIU can reread the last set for retransmission Hardware clears this bit after the read pointer is reversed Setting this bit is effective only when the ADV RM ATM and CLR bits are all clear C 50 intel REGISTERS TXDATx Address See Table 7 5 x 0 3 Reset State See Table 7 5 USB Transmit FIF
407. structions Table A 27 Section A 4 contains a detailed description of each instruction NOTE The instruction execution times given in this appendix are for an internal BASE TIME using data that is read from and written to on chip RAM These times do not include your application s systembus performance time necessary to fetch and execute code from external memory accessing peripheral SFRs using wait states or extending the ALE pulse For some instructions accessing the port SFRs Px x 2 0 3 increases the execution time beyond that of the BASE TIME These cases are listed in Table A 18 and are noted in the instruction summary tables and the instruction descriptions A 1 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel NOTATION FOR INSTRUCTION OPERANDS Table A 1 Notation for Register Operands Register Notation 829906 y 2 A memory location 00 addressed indirectly via byte register v RO or R1 Rn Byte register RO R7 of the currently selected register bank n Byte register index n 2 0 7 v rrr Binary representation of n Rm Byte register RO R15 of the currently selected register file Rmd Destination register Rms Source register T m md ms Byte register index m md ms 0 15 55565 Binary representation of m or md 5555 Binary representation of ms WRj Word register WRO WR2 WR30 of the currently selected register file WRid Destination register WRijs Source registe
408. t 0 and port 2 pins when the chip in is the normal operating mode and the external bus is idle or executing a bus cycle 15 10 intel EXTERNAL MEMORY INTERFACE Table 15 3 Port 0 and Port 2 Pin Status In Normal Operating Mode Mode Page Mode Bus Cycle Bus Idle Bus Cycle Bus Idle Port 0 8 or 16 07 0 1 High Impedance A7 0 1 High Impedance pies 8 P2 2 P2 P2 D7 0 2 High Impedance 16 A15 8 P2 A15 8 D7 0 High Impedance NOTES 1 During external memory accesses the 82930A writes FFH to the PO register and the register contents are lost 2 The P2 register can be used to select 256 byte pages in external memory 15 5 1 Port 0 and Port 2 Pin Status in Nonpage Mode In nonpage mode the port pins have the same signals as those on the 8XC51FX For an external memory instruction using a 16 bit address the port pins carry address and data bits during the bus cycle However if the instruction uses an 8 bit address 2 MOVX the contents of P2 are driven onto the pins These pin signals can be used to select 256 bit pages in external memory During a bus cycle the CPU always writes FFH to PO and the former contents of PO are lost A bus cycle does not change the contents of P2 When the bus is idle the port 0 pins are held at high impedance and the contents of P2 are driven onto the port 2 pins 15 5 2 Port 0 and Port 2 Pin Status in Page Mode In a pag
409. t Priority High Control Register 0 IPHO together with IPLO assigns each interrupt a priority level from 0 lowest to 3 highest IPHO x IPLO x Priority Level 0 0 0 lowest priority 0 1 1 1 0 2 1 1 3 highest priority 7 0 IPHO 6 IPHO 5 IPHO 4 IPHO 3 IPHO 2 IPHO 1 0 0 Number Function 7 Reserved The value read from this bit is indeterminate Write a zero to this bit 6 IPHO 6 PCA Interrupt Priority Bit High 5 0 5 Timer 2 Overflow Interrupt Priority Bit High 4 IPHO 4 Serial I O Port Interrupt Priority Bit High 3 IPHO 3 Timer 1 Overflow Interrupt Priority Bit High 2 IPHO 2 External Interrupt 1 Priority Bit High 1 IPHO 1 Timer 0 Overflow Interrupt Priority Bit High 0 0 0 External Interrupt 0 Priority Bit High C 18 intel REGISTERS IPLO Address S B8H Reset State X000 00008 Interrupt Priority Low Control Register 0 IPLO together with IPHO assigns each interrupt a priority level from 0 lowest to 3 highest IPHO x IPLO x Priority Level 0 0 0 lowest priority 0 1 1 1 0 2 1 1 3 highest priority 7 0 IPLO 6 IPLO 5 0 4 0 3 0 2 0 11 0 0 Number Function 7 Reserved The value read from this bit is indeterminate Write a zero to this bit 6 IPLO 6 PCA Interrupt Priority Bit Low 5 IPLO 5 Timer 2 O
410. t follows RCAP2H RCAP2L denotes the contents of RCAP2H and RCAP2L taken as a 16 bit unsigned integer Fosc 32 x 65536 RCAP2H RCAP2L NOTE When timer 2 is configured as a timer and is in baud rate generator mode do not read or write the TH2 or TL2 registers The timer is being incremented every state time and the results of a read or write may not be accurate In addition you may read but not write to the RCAP2 registers a write may overlap a reload and cause write and or reload errors Serial I O Modes 1 and Baud Rates Table 12 6 lists commonly used baud rates and shows how they are generated by timer 2 Table 12 6 Timer 2 Generated Baud Rates Oscillator Baud Rate Frequency RCAP2H RCAP2L Fosc 375 0 Kbaud 12 MHz FFH FFH 9 6 Kbaud 12 MHz FFH 4 8 Kbaud 12 MHz FFH B2H 2 4 Kbaud 12 MHz FFH 64H 1 2 Kbaud 12 MHz FEH C8H 300 0 baud 12 MHz FBH 1EH 110 0 baud 12 MHz F2H AFH 300 0 baud 6 MHz FDH 8FH 110 0 baud 6 MHz F9H 57H 12 14 intel 13 Minimum Hardware Setup 13 MINIMUM HARDWARE SETUP This chapter discusses the basic operating requirements of the 82930A and describes a minimum hardware setup Topics covered include power ground clock source and device reset For pa rameter values refer to the device data sheet 13 1 MINIMUM HARDWARE SETUP Figure 13 1 shows a minimum hardware setup that employs the on chip oscillato
411. t is used to enable data from the USB to be written into RXFIFO If disabled the endpoint will not write the received data into RXFIFO and at the end of reception it returns a NACK handshake if STL_RX bit is not set The state of this bit is sampled on a valid OUT token RXEP E Receive endpoint enable This bit is used to enable the receive endpoint When disabled the endpoint does not respond to a valid OUT token The state of this bit is sampled on a valid OUT token TX OE Transmit output enable This bit is used to enable the data in the TXFIFO to be transmitted If disabled the endpoint returns a NACK handshake to a valid IN token if the STL TX bit is not set The state of this bit is sampled on a valid IN token TXEP E Transmit endpoint enable This bit is used to enable the transmit endpoint When disabled the endpoint does not respond to a valid IN token The state of this bit is sampled on a valid IN token 7 22 Figure 7 14 Data Flow Control Register Endpoint x intel UNIVERSAL SERIAL BUS Table 7 15 EPCONXx Addresses and Reset Values Register Address Reset Value EPCONO S COH 0010 1111 1 S C1H 0000 1111 EPCON2 S BAH 0000 1111 S BBH 0000 1111 TXSTATx Address See Table 7 16 x 0 3 Reset State See Table 7 16 7 0 T_SEQ T VOID T ERR T ACK Bit Bit
412. te 00H 7 0 SFACK RXSOF TS10 TS9 58 Bit Bit Function Number Mnemonic 7 SFACK SOF token received without error When set it indicates that the 11 bit time stamp stored in SOFO and SOF1 is valid This bit is updated everytime a SOF token is received 6 RXSOF When set this bit is an indication that SOF token was received Must be cleared by software An 8 state pulse is generated and routed to the SOF pin 53 Reserved Values read from these bits are indeterminate Write zeros to these bits 2 0 TS10 8 Time stamp received from host This time stamp is valid only if the SFACK bit in the SOFH register is set 510 8 are the upper three bits of the 11 bit frame number issued with an SOF token SOFL Address S D2H Reset State 00H 7 0 TS7 0 Bit Bit Number Function 7 0 TS7 0 Time stamp received from host This time stamp is valid only if the SFACK bit in the SOFH register is set TS7 0 are the lower eight bits of the 11 bit frame number issued with a SOF token C 39 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel SP Address 81H Reset State 0000 0111B Stack Pointer SP provides SFR access to location 63 in the register file also named SP SP is the lowest byte of the extended stack pointer SPX DR60 The extended stack pointer points to the current top of stack
413. te variable Loads the accumulator with the contents of the specified variable at the same time writing the original accumulator contents to the specified variable The source destination operand can use register direct or register indirect addressing OV N 2 RO contains the address 20H the accumulator contains 00111111 and on chip RAM location 20H contains 75H 01110101B After executing the instruction XCH A RO RAM location 20H contains 00111111 and the accumulator contains 75H 01110101B intel INSTRUCTION SET REFERENCE XCH A dir8 Binary Mode Source Mode Bytes 2 2 States 3t 3t tlf this instruction addresses a port x 0 3 add 2 states Encoding 1100 0101 direct addr Hex Code in Binary Mode Encoding Source Mode Encoding Operation XCH lt dir8 XCH A GRi Binary Mode Source Mode Bytes 1 2 States 4 5 Encoding 1100 011i Hex Code in Binary Mode Encoding Source Mode A5 Encoding Operation XCH gt lt Ri XCH A Rn Binary Mode Source Mode Bytes 1 2 States 3 4 Encoding 1100 Tree Hex Code in Binary Mode Encoding Source Mode A5 Encoding Operation XCH A gt lt Rn Variations XCHD A Ri Function Exchange digit Description Exchanges the low nibble of the accumulator bits 3 0 generally representing hexadecimal or BCD
414. ted on P2 or PO See Bus Structure in Nonpage Mode and Page Mode in Chapter 15 and Device Configuration in this chapter for a description of the bus structure and page mode operation Nonpage mode PAGE 1 The bus structure is the same as for the MCS 51 architecture with data D7 0 multiplexed with A7 0 on PO External code fetches require two state times 4Tosc Page mode PAGE 0 The bus structure differs from the bus structure in MCS 51 controllers Data D7 0 is multiplexed with A15 8 on P2 Under certain conditions external code fetches require only one state time 2 lt 4 4 2 Configuration Bits RD1 0 The RD1 0 configuration bits UCONFIGO 3 2 determine the number of external address lines and the address ranges for asserting the read signals PSEN RD and the write signal WR These selections offer different ways of addressing external memory Figures 4 4 and 4 5 show how internal memory space maps into external memory space for the four values of RD1 0 Chap 4 6 intel DEVICE CONFIGURATION ter 15 External Memory Interface provides examples of external memory designs for each choice of RD1 0 A key to the memory interface is the relationship between internal memory addresses and exter nal memory addresses While the 82930A has 24 internal address bits the number of external ad dress lines is less than 24 i e 16 17 or 18 depending on the values of RD1 0 This means that reads writes to di
415. tel 13 3 3 External Clock To operate the 82930A from an external clock connect the clock source to the pin as shown in Figure 13 3 Leave the XTAL2 pin floating The external clock driver can be a CMOS gate If the clock driver is a TTL device its output must be connected to through a 4 7 pullup resistor For external clock drive requirements see the device data sheet Figure 13 4 shows the clock drive waveform The external clock source must meet the minimum high and low times and and the maximum rise and fall times and to minimize the effect of ex ternal noise on the clock generator circuit Long rise and fall times increase the chance that ex ternal noise will affect the clock circuitry and cause unreliable operation The external clock driver may encounter increased capacitance loading at due to the Miller effect of the internal inverter as the clock waveform builds up in amplitude following power on Once the input waveform requirements are met the input capacitance remains under 20 pE External Clock gt 2 CMOS Clock Driver N C Note If TTL clock driver is used connect a 4 7kQ pullup resistor from driver output to Vec A4142 03 Figure 13 3 External Clock Connection for the 82930A 13 4 intel MINIMUM HARDWARE SETUP A4119 01 Figure 13 4 External Clock Drive Waveforms 13 4 RESET A device reset initia
416. ter 0 High Byte S 8CH TL1 Timer Counter 1 Low Byte S 8BH TH1 Timer Counter 1 High Byte S 8DH TL2 Timer Counter 2 Low Byte S CCH TH2 Timer Counter 2 High Byte S CDH TCON Timer Counter 0 and 1 Control 5 88 TMOD Timer Counter 0 and 1 Mode Control 5 89 T2CON Timer Counter 2 Control S C8H T2MOD Timer Counter 2 Mode Control S C9H RCAP2L Timer 2 Reload Capture Low Byte S CAH RCAP2H Timer 2 Reload Capture High Byte S CBH WDTRST WatchDog Timer Reset S A6H 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Table C 6 Programmable Counter Array PCA SFRs In Mnemonic Name Address CCON PCA Timer Counter Control S D8H CMOD PCA Timer Counter Mode S D9H CCAPMO PCA Timer Counter Mode 0 S DAH CCAPM 1 PCA Timer Counter Mode 1 S DBH CCAPM2 PCA Timer Counter Mode 2 S DCH Timer Counter Mode 3 S DDH CCAPM4 PCA Timer Counter Mode 4 S DEH CL PCA Timer Counter Low Byte S E9H CH PCA Timer Counter High Byte S F9H CCAPOL PCA Compare Capture Module 0 Low Byte S EAH CCAP1L PCA Compare Capture Module 1 Low Byte S EBH CCAP2L PCA Compare Capture Module 2 Low Byte S ECH CCAP3L PCA Compare Capture Module 3 Low Byte S EDH CCAP4L PCA Compare Capture Module 4 Low Byte S EEH CCAPOH PCA Compare Capture Module 0 High Byte S FAH CCAP1H PCA Compare Capture Module 1 High Byte S FBH CCAP2H PCA Compare Capture Module 2 High Byte S FCH CCAP3H PCA Compare Capture Module 3 High B
417. ter Idle Control CIDL 1 disables the PCA timer counter during idle mode CIDL 0 allows the PCA timer counter to run during idle mode 6 WDTE Watchdog Timer Enable WDTE 1 enables the watchdog timer output on PCA module 4 WDTE 0 disables the PCA watchdog timer output 5 3 Reserved Values read from these bits are indeterminate Write zeros to these bits 2 1 CPS1 0 PCA Timer Counter Input Select CPS1 CPSO 0 0 Fosc 12 0 1 Fosc 4 1 0 Timer 0 overflow 1 1 External clock at pin maximum rate Fog 8 0 ECF PCA Timer Counter Interrupt Enable 1 enables the CF bit in the CCON register to generate an interrupt request Figure 11 7 CMOD PCA Timer Counter Mode Register 11 13 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel CCON Address S D8H Reset State 00X0 0000B 7 0 CR CCF4 CCF3 CCF2 CCF1 CCFO Bit Bit Number Mnemonic Function 7 CF PCA Timer Counter Overflow Flag Set by hardware when the PCA timer counter rolls over This generates an interrupt request if the ECF interrupt enable bit in CMOD is set CF can be set by hardware or software but can be cleared only by software 6 CR PCA Timer Counter Run Control Bit Set and cleared by software to turn the PCA timer counter on and off 5 Reserved The value read from this bit is indeterminate Write a zero to this bit 4 0
418. tes and words and addresses the SFRs dir8 S 080H S 1FFH as bytes only See the second note on page 5 4 regarding SFRs in the MCS 251 architecture The 16 bit direct mode addresses both bytes and words in memory dir16 00 0000H 00 FFFFH MCS 51 architecture The 8 bit direct mode addresses 256 bytes of on chip RAM dir8 00H 7FH as bytes only and the SFRs dir8 80H FFH as bytes only Table 5 3 Addressing Modes for Data Instructions in the MCS 51 Architecture Address Range of Assembly Language Mode Operand Reference Comments RO R7 Register DOE TE Bank selected by PSW Immediate Operand in Instruction data 00H 7FH dir8 00H 7FH On chip RAM Direct dir8 80H FFH SFRs OF SER SFR address 5 5 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Table 5 3 Addressing Modes for Data Instructions in the MCS 51 Address Range of Assembly Language Mode Operand Reference Comments Accesses on chip RAM or the 00H FFH o RO R1 lowest 256 bytes of external data memory MOVX Indirect Accesses external data 0000H FFFFH DPTR A DPTR memory MOVX Accesses region FF of code 0000H FFFFH A DPTR A PC memory MOVC 5 3 1 4 Indirect In arithmetic and logical instructions that use indirect addressing the source operand is always a byte and the destination is either the accumulator or a byte register
419. tes the parity of the accumulator It is set if an odd number of bits in the accumulator are set Otherwise it is cleared Not all instructions update the parity bit The parity bit is set or cleared by instructions that change the contents of the accumulator ACC Register R11 Figure 5 2 Program Status Word Register intel INSTRUCTIONS AND ADDRESSING PSW1 Address S D1H Reset State 0000 0000B 7 0 RS1 50 OV 2 Function 7 Carry Flag Identical to the CY bit in the PSW register 6 AC Auxiliary Carry Flag Identical to the AC bit in the PSW register 5 N Negative Flag This bit is set if the result of the last logical or arithmetic operation was negative i e bit 15 1 Otherwise it is cleared 4 3 RS1 0 Register Bank Select Bits 0 and 1 Identical to the RS1 0 bits in the PSW register 2 OV Overflow Flag Identical to the OV bit in the PSW register 1 2 Zero Flag This flag is set if the result of the last logical or arithmetic operation is zero Otherwise it is cleared 0 Reserved The value read from this bit is indeterminate Write a zero to this bit Figure 5 3 Program Status Word 1 Register 5 17 intel Interrupts intel CHAPTER 6 INTERRUPTS 6 1 OVERVIEW The 82930A like other control oriented computer architectures employs a program interrupt method This oper
420. the device 13 6 MINIMUM HARDWARE SETUP Internal Reset Routine PSEN ALE bs 4103 01 Figure 13 5 Reset Timing Sequence 19 7 intel 14 Special Operating Modes 14 SPECIAL OPERATING MODES This chapter describes the power control PCON register and three special operating modes idle powerdown and on circuit emulation ONCE 14 4 GENERAL The idle and powerdown modes are power reduction modes for use in applications where power consumption is a concern User instructions activate these modes by setting bits in the PCON reg ister Program execution halts but resumes when the mode is exited by an interrupt While in idle or power down the pin is the input for backup power ONCE is a test mode that electrically isolates the 82930 from the system in which it operates 14 2 POWER CONTROL REGISTER The PCON special function register Figure 14 1 provides two control bits for the serial function bits for selecting the idle and powerdown modes the power off flag and two general purpose flags 14 2 1 Serial Control Bits The SMODI bit in the PCON register is a factor in determining the serial I O baud rate See Fig ure 14 1 and section 12 6 Baud Rates The SMODO bit in the PCON register determines whether bit 7 of SCON register provides read write access to the framing error FE bit SMODO 1 or to SMO a
421. the number of bytes in the set The byte count register TXCNTx has a read write index to allow it to access the byte count for either of the two data sets see Figure 7 2 After reset the read write index points to data set 0 Thereafter the following logic determines the position of the read write index e After a write to TXCNTx the read write index is toggled e After a read of TXCNTx the read write index is unchanged The position of the read write index can also be determined from the data set index bits FIF1 0 see 7 2 3 Byte Count dsO Byte Count ds1 Read Write Select Byte Count Byte Count Register TXCNTx A4261 01 Figure 7 2 TXFIFOx Byte Count Register TXCNTx 7 2 8 Data Set Management Two read only data set index bits FIF1 0 in the TXFLGx register indicate which data sets 480 and or ds1 have been written into the FIFO see the left side of Table 7 2 FIFx 1 indicates that data set x has been written Following reset FIF1 0 00 signifying an empty FIFO FIF1 0 also determine which data set is written next Note that FIFO specifies the next data set to be writ ten except for the case of FIF1 0 11 In this case further writes to TXDATx or TXCNTx are ignored 7 3 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Two events cause the data set index bits to be updated A new set is written to the FIFO the 82930A writes bytes to the FIFO via TXDATx and wr
422. the proper BCD digit in the high nibble Again this sets the CY flag if there was a carry out of the upper four bits but does not clear the carry The CY flag thus indicates if the sum of the original two BCD variables is greater than 100 allowing multiple precision decimal addition The OV flag is not affected All of this occurs during one instruction cycle Essentially this instruction performs the decimal conversion by adding 00H 06H 60H or 66H to the accumulator depending on initial accumulator and PSW conditions Note DA A cannot simply convert a hexadecimal number in the accumulator to BCD notation nor does DA A apply to decimal subtraction OV N 2 V accumulator contains 56H 01010110B which represents the packed BCD digits of the decimal number 56 Register 3 contains 67H 01100111B which represents the packed BCD digits of the decimal number 67 The CY flag is set After executing the instruction Sequence ADDC A R3 DAA the accumulator contains OBEH 10111110 and the CY and AC flags are clear The Decimal Adjust instruction then alters the accumulator to the value 24H 00100100B indicating the packed BCD digits of the decimal number 24 the lower two digits of the decimal sum of 56 67 and the carry in The CY flag is set by the Decimal Adjust instruction indicating that a decimal overflow occurred The true sum of 56 67 and 1 is 124 A 53 82930A UNIVERSAL SERIA
423. the write pointer to the origin of the last data Set received as identified by the write marker REV WP is used when a data packet is bad When the SIU receives the data packet again the write starts at the origin of the previous bad data set Hardware clears this bit after the write pointer is reversed Setting this bit is effective only when the ADV WM ARM and CLR bits are all clear C 29 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel RXDATx Address See Table 7 11 x 0 3 Reset See Table 7 11 Receive FIFO Data Register 7 0 RXDATx 7 0 Bit Bit Number Mnemonic Function 7 0 RXDATx 7 0 To write data to the RXFIFO the SIU writes to this register To read data from the RXFIFO the 82930A reads from this register The write pointer and read pointer are incremented automatically after a write and read respectively C 30 intel REGISTERS RXFLGx Address See Table 7 14 0 3 Reset State See Table 7 14 7 0 FIF1 FIFO EMPTY FULL URF OVF Function 7 6 FIF1 0 FIFO Index Flags These read only flags indicate which data sets are present in the RXFIFO see Table 7 9 The FIF bits are updated after each write to RXCNTx to reflect the addition of a data set Likewise the FIF bits are updated after the FFRC bit is set The next state table for FIF bits is shown below for operation in
424. tion The call is to an address that is in the same 2 Kbyte block of memory as the address of the next instruction LCALL Long Call pushes the lower 16 bits of the next instruction address onto the stack and then changes the lower 16 bits of the PC to the 16 bit address specified by the instruction The call is to an address in the same 64 Kbyte block of memory as the address of the next instruction ECALL Extended Call pushes the 24 bits of the next instruction address onto the stack and then changes the 24 bits of the PC to the 24 bit address specified by the instruction The call is to an address anywhere in the 16 Mbyte memory space RET Return pops the top two bytes from the stack to return to the instruction following a sub routine call The return address must be in the same 64 Kbyte region ERET Extended Return pops the top three bytes from the stack to return to the address follow ing a subroutine call The return address can be anywhere in the 16 Mbyte address space RETI Return from Interrupt provides a return from an interrupt service routine The operation of RETI depends on the INTR bit in the UCONFIGI or CONFIGI configuration byte e For INTR 0 an interrupt pushes the two lower bytes of the PC onto the stack in the following order PC 7 0 PC 15 8 The RETI instruction pops these two bytes and uses them as the 16 bit return address in region FF RETI also restores the interrupt logic to accept additional interrupts
425. tion and The ISR is in on chip OTPROM ROM 6 8 2 Variable Interrupt Parameters Both response time and latency calculations contain fixed and variable components By defini tion it is often difficult to predict exact timing calculations for real time requests One large vari able is the completion time of an instruction cycle coincident with the occurrence of an interrupt request Worst case predictions typically use the longest executing instruction in an architecture s code set the case of the 82930A the longest executing instruction is 16 bit divide DIV However even this 21 state instruction may have only 1 or 2 remaining states to complete before the interrupt system injects a context switch This uncertainty affects both response time and la tency 6 14 intel INTERRUPTS 6 8 2 1 Response Time Variables Response time is defined as the start of a dynamic time period when a source requests an interrupt and lasts until a break in the current instruction execution stream occurs see Figure 6 10 Re sponse time and therefore latency is affected by two primary factors the incidence of the re quest relative to the four state time sample window and the completion time of instructions in the response period 1 shorter instructions complete earlier than longer instructions NOTE External interrupt signals require one additional state time in comparison to internal interrupts This is necessary to sample and latch
426. tput Mode seen 11 3 5 Watchdog Timer Mode enne enne enne ener nnne 11 9 11 3 6 Pulse Width Modulation Mode eemmemdi0 CHAPTER 12 SERIAL I O PORT 12 2 MODES OF OPERATION tierce rr perti eae 12 4 12 2 1 Synchronous Mode Mode 0 12 4 12 22141 Transmission Mode 0 eerte te ntu beer en Re 12 4 12 2 1 2 Reception Mode 0 12 5 12 2 2 Asynchronous Modes Modes 1 2 and 3 12 2 2 1 Transmission Modes 1 2 3 12 2 2 2 Reception Modes 1 2 3 em 123 FRAMING BIT ERROR DETECTION MODES 1 2 AND 3 124 MULTIPROCESSOR COMMUNICATION MODES 2 3 12 6 12 6 12 6 12 7 12 7 vii 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL 12 5 AUTOMATIC ADDRESS 0000 12 5 1 Given Address nennen A 12 5 2 125 3 Reset Addresses onu nun LED NOSE eie 12 6 BAUD RATES aceti 12 6 1 Baud Rate for 0 12 6 2 Baud Rates for Mode 2 ener enne eene nnne 12 6 3 Baud Rates for Modes 1 12 6 8 1 Timer 1 Generated
427. ts 3 0 and bits 7 4 This operation can also be thought of as a 4 bit rotate instruction OV The accumulator contains 0C5H 11000101B After executing the instruction SWAP A the accumulator contains 01011100B Binary Mode Source Mode 1 2 1 2 1100 0100 Binary Mode Encoding Source Mode Encoding SWAP 3 0 gt lt 7 4 Causes interrupt call A 133 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Description Causes an interrupt call that is vectored through location OFF007BH The operation of this instruction is not affected by the state of the interrupt enable flag in PSWO and PSW1 Interrupt calls can not occur immediately following this instruction This instruction is intended for use by Intel provided development tools These tools do not support user application of this instruction Flags OV N 2 Example The instruction TRAP causes an interrupt call to location OFF007BH during normal operation Binary Mode Source Mode Bytes 2 1 States 2 bytes 11 10 States 4 bytes 16 15 Encoding 1011 1001 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation TRAP SP SP 2 SP PC PC lt OFF007BH XCH A lt byte gt Function Description Flags Example Variations A 134 Exchange accumulator with by
428. tuffing All bits are sent out onto the bus least significant bit LSb first following by the next LSb and so on Bytes are sent out onto the bus least significant byte LSB first following by the next LSB and so on The SIE ensures that the LSb is first but the 82930 programmer must order the bytes The SIE decodes and takes care of all packet types and packet fields mentioned in Protocol Lay er chapter of Universal Serial Bus Specification The SBM communicates data information such as data type isochronous or asynchronous to the SIE and instructs the SIE in handling hand shakes Programmers may refer to the Interconnect Description chapter the USB Devices chapter and the USB Host chapter of Universal Serial Bus Specification for detailed informa tion on how the host and function communicate 7 28 intel USB Operating Modes 8 USB OPERATING MODES This chapter describes the operating modes of the 82930A For the FIFO transmit and receive erations it describes the interactions of the suggested firmware flow and the SIU hardware 8 1 OVERVIEW OF OPERATING MODES After a reset the 82930 proceeds first to an unenumerated mode and then after enumeration by the host to an idle mode From the idle mode it can move to any of four operating modes a trans mit mode receive mode an SOF receive mode and a setup mode Figure 8 1 shows the rela tionships between these modes Un
429. ture The ADD and SUB instructions Table A 19 in Appendix A operate on byte and word data that is accessed in several ways as the contents of the accumulator a byte register Rn or a word register WRj in the instruction itself immediate data in memory via direct or indirect addressing The ADDC and SUBB instructions Table A 19 are the same as those for MCS 51 microcontrol lers The CMP compare instruction Table A 20 calculates the difference of two bytes or words and then writes to flags CY OV AC and Z in the PSW and PSWI registers The difference is not stored The operands can be addressed in a variety of modes The most frequent use of CMP is to compare data or addresses preceding a conditional jump instruction Table A 21 lists the INC increment and DEC decrement instructions The instructions for MCS 51 microcontrollers are supplemented by instructions that can address byte word and dword registers and increment or decrement them by 1 2 4 denoted by short These instruc tions are supplied primarily for register based address pointers and loop counters The 82930A architecture provides the MUL multiply and DIV divide instructions for un signed 8 bit and 16 bit data Table A 22 Signed multiply and divide are left for the user to man age through a conversion process The following operations are implemented e eight bit multiplication 8 bits x 8 bits 16 bits sixteen bit multiplicat
430. tware service routine executes assigned tasks and as a final activity performs a RETI re turn from interrupt instruction This instruction signals completion of the interrupt resets the in terrupt in progress priority and reloads the program counter Program operation then continues from the original point of interruption Table 6 1 Interrupt System Input Signals Signal Multiplexed Name Type Description With INT1 0 External Interrupts 0 and 1 These inputs set bits IE1 0 in the P3 3 2 TCON register If bits IT1 0 in the TCON register are set bits IE1 0 are controlled by a negative edge trigger on INT1 INTO If bits INT1 0 are clear bits IE1 0 are controlled by a low level trigger on INT1 0 NOTE Other pin signals are defined in their respective chapters and in the appendix A non maskable interrupt NMI is not included on the 82930A 6 1 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Interrupt Enable Priority Enable Highest Priority Interrupt i m o INTO C ITO 0 TFO INT1s4 IT1 1 TF1 USB BXDx RXIEx Receive 3 PCA Counter ECF Overflow 1 152 E 0 a Match or ECCFx 1 5 E Receive R 2 Transmit Timer 2 TF2 gt T2EX EXF2 USB Transmit gt lt A o Lowest Priority Interr
431. uage Notation Comments RO R7 WRO WR6 DRO 00 0000 00 001 Register RO R15 WRO WR30 DR2 are in the register bank 9 RO R7 WRO WR3 DRO DR28 DR56 DR60 currently selected by the DRO DR2 1 PSW and PSW1 Immediate N A Operand is in the A Used only in increment and 2 bits instruction decrement instructions Immediate N A Operand is in the E 8 bits instruction OO SEEN Immediate N A Operand is in the _ ts 16 bits instruction 16 0000H FFFFH TET 00 0000H 00 007FH dir8 00 0000H 00 007FH On chip RAM irect 8 address bits dir8 S 080H S 1FFH 2 in or SFR mnemonic SFR address Direct 00 0000H 00 FFFFH dir16 00 0000H 00 FFFFH 16 address bits d ir16 00 00 Indirect 16 address bits 00 0000H 00 FFFFH WRO WR30 Indirect DRO DR30 DR56 Upper 8 bits of DRk must be 24 address bits 00 0000H FF FFFFH DR60 OOH Displacement 16 address bits 00 0000H 00 FFFFH WRj dis16 OH through WR30 FFFFH Offset is signed address wraps around in region 00 Displacement 24 address bits 00 0000H FF FFFFH DRk dis24 DRO OH through DR28 FFFFH DR56 OH FFFFH DR60 OH FFFFH Offset is signed upper 8 bits of DRk must be 00H NOTES 1 These registers are accessible in the memory space as well as in the re
432. umber Mnemonic unctio 7 GATE1 Timer 1 Gate When GATE1 0 run control bit TR1 gates the input signal to the timer register When GATE1 1 and TR1 1 external signal INT1 gates the timer input 6 C T1 Timer 1 Counter Timer Select C T1 0 selects timer operation timer 1 counts the divided down system clock C T1 1 selects counter operation timer 1 counts negative transitions on external pin T1 5 4 M11 01 Timer 1 Mode Select M11 M01 0 0 Mode 0 8 bit timer counter TH1 with 5 bit prescalar TL1 0 1 Mode 1 16 bit timer counter 1 0 Mode 2 8 bit auto reload timer counter TL1 Reloaded from 1 at overflow 1 1 3 Timer 1 halted Retains count 3 GATEO Timer 0 Gate When GATEO 0 run control bit TRO gates the input signal to the timer register When GATEO 1 and TRO 1 external signal INTO gates the timer input 2 Timer 0 Counter Timer Select 0 selects timer operation timer 0 counts the divided down System clock 0 1 selects counter operation timer 0 counts negative transitions on external pin TO 1 0 M10 00 Timer 0 Mode Select M10 00 0 0 Mode 0 8 bit timer counter TO with 5 bit prescaler TLO 0 1 Mode 1 16 bit timer counter 1 0 Mode 2 8 bit auto reload timer counter TLO Reloaded from THO at overflow T Mode 3 TLO is an 8 bit timer counter THO is an 8 bit timer using timer 1 s TR1 and TF1 bits
433. upt 4280 01 Figure 6 1 Interrupt Control System intel INTERRUPTS Table 6 2 Interrupt System Special Function Registers Mnemonic Description Address IEO Interrupt Enable Register 0 Used to enable and disable programmable S A8H interrupts The reset value of this register is zero interrupts disabled IPLO Interrupt Priority Low Register 0 Establishes relative priority for program S B8H mable interrupts Used in conjunction with IPHO IPHO Interrupt Priority High Register 0 Establishes relative priority for program S B7H mable interrupts Used in conjunction with IPLO SBI USB Interrupt Register The bits in SBI indicate the event causing an S 91H interrupt SBIE USB Endpoint Interrupt Enable Register Used to enable and disable USB S A1H endpoint interrupts IE1 Interrupt Enable Register 1 Used to enable and disable programmable S B1H interrupts The reset value of this register is zero interrupts disabled IPL1 Interrupt Priority Low Register 1 Establishes relative priority for program S B2H mable interrupts Used in conjunction with IPH1 IPH1 Interrupt Priority High Register 1 Establishes relative priority for program S B3H mable interrupts Used in conjunction with IPL1 NOTE Other special function registers are described in their respective chapters and in the appendix 6 2 82930A INTERRUPT SOURCES Figure 6 1 illustrates the interrupt control system
434. urce Mode 1 1 10 10 1000 0100 Binary Mode Encoding Source Mode Encoding DIV lt quotient A B B lt remainder A B DJNZ lt byte gt lt rel addr gt Function Decrement and jump if not zero A 59 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Description Flags Example Variations DJNZ dir8 rel Bytes States Encoding Hex Code in A 60 intel Decrements the specified location by 1 and branches to the address specified by the second operand if the resulting value is not zero An original value of 00H underflows to OFFH The branch destination is computed by adding the signed relative displacement value in the last instruction byte to the PC after incrementing the PC to the first byte of the following instruction The location decremented may be a register or directly addressed byte Note When this instruction is used to modify an output port the value used as the original port data is read from the output data latch not the input pins OV N 2 The RAM locations 40H 50H and 60H contain 01H 70H and 15H respectively After executing the following instruction sequence DJNZ 40H LABEL1 DJNZ 50H LABEL2 DJNZ 60H LABEL on chip RAM locations 40H 50H and 60H contain 00H 6FH and 14H respectively and program execution continues at label LABEL2 The first jump was not taken because the
435. ved bits set SFR sign extension sink current source code compatibility source current source mode SP SPX state time or state GLOSSARY Pulse width modulated outputs A signed two s complement 8 bit relative destination address The destination is 128 to 127 bytes relative to the first byte of the next instruction Register bits that are not used in this device but may be used in future implementations Avoid any software dependence on these bits In the 82930A the value read from a reserved bit is indeterminate do not write 1 to a reserved bit The term set refers to the value of a bit or the act of giving it a value If a bitis set its value is 1 setting a bit gives it a 1 value Special function register A method for converting data to a larger format by filling the extra bit positions with the value of the sign This conversion preserves the positive or negative value of signed integers Current flowing into a device to ground Always a positive value The ability of an 82930A to execute recompiled source code written for an MCS 51 microcontroller Current flowing out of a device from Voc Always negative value An operating mode that is selected by a configuration bit In source mode an 82930A can execute recompiled source code written for an MCS 51 microcontroller In source mode the 82930A cannot execute unmodified binary code written for an MCS 51 microcontroller
436. verflow Interrupt Priority Bit Low 4 IPLO 4 Serial I O Port Interrupt Priority Bit Low 3 IPLO 3 Timer 1 Overflow Interrupt Priority Bit Low 2 IPLO 2 External Interrupt 1 Priority Bit Low 1 IPLO 1 Timer 0 Overflow Interrupt Priority Bit Low 0 IPLO O External Interrupt O Priority Bit Low 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL IPH1 Address S B3H Reset State 00H 7 0 IPH1 3 IPH1 2 IPH1 1 IPH1 0 7 4 Reserved Values read from these bits are indeterminate Write zeros to these bits IPH1 3 Endpoint 3 Interrupt Priority Bit High 2 IPH1 2 Endpoint 2 Interrupt Priority Bit High 1 IPH1 1 Endpoint 1 Interrupt Priority Bit High 0 IPH1 0 Endpoint 0 Interrupt Priority Bit High IPL1 Address 5 2 Reset State 00H 7 0 IPL1 3 IPL1 2 IPL1 1 IPL1 0 nies Function 7 4 Reserved Values read from these bits are indeterminate Write zeros to these bits IPL1 3 Endpoint 3 Interrupt Priority Bit Low 2 IPL1 2 Endpoint 2 Interrupt Priority Bit Low 1 IPL1 1 Endpoint 1 Interrupt Priority Bit Low 0 IPL1 0 Endpoint 0 Interrupt Priority Bit Low C 20 intel REGISTERS Address Reset State S 80H 1111 1111B Port 0 PO is the SFR that contains data to be driven out from the port 0 pins Read modify writ
437. within the 16 Mbyte address space Arithmetic logic unit The part of the CPU that processes arithmetic and logical operations The term assert refers to the act of making a signal active enabled The polarity high low is defined by the signal name Active low signals are designated by a pound symbol suffix active high signals have no suffix To assert RD is to drive it low to assert ALE is to drive it high Glossary 1 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel binary code compatibility binary mode bit bit operand bit51 byte clear code memory configuration bytes dir8 dir16 DPTR DPX deassert doping Glossary 2 The ability of an 829304 to execute without modification binary code written for an MCS 51 microcontroller An operating mode selected by a configuration bit that enables an 82930A to execute without modification binary code written for an MCS 51 microcontroller A binary digit An addressable bit in the 82930A architecture An addressable bit in the MCS 51 architecture Any 8 bit unit of data The term clear refers to the value of a bit or the act of giving it a value If a bit is clear its value is 0 clearing a bit gives it a 0 value See program memory Bytes residing in on chip OTPROM ROM that determine a set of operating parameters for the 82930 An 8 bit direct address This be a memory address or an SFR a
438. y Mode A5 Encoding Source Mode Encoding Operation MOV Rm lt dir8 MOV WRi dir8 Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding 0111 1110 0101 direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV WRj dir8 MOV DRk dir8 Binary Mode Source Mode Bytes 4 3 States 6 5 Encoding 0111 1110 uuuu 1101 direct addr A 89 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV DRk lt dir8 MOV 16 Binary Source Mode Bytes 5 4 States 3 2 Encoding 0111 1110 5555 0011 direct addr direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV Rm lt dir16 MOV WhRj dir16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding 0111 1110 tttt 0111 direct addr direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV WRj dir16 MOV DRk dir16 Binary Mode Source Mode Bytes 5 4 States 6 5 Encoding 0111 1110 uuuu 1111 direct addr direct addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV lt 16 MOV Rm WRj A 90 Binary Mode Source Mode intel INSTRUCTION SET REFERENCE
439. y dir addr Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CLR bit lt 0 CMP lt dest gt lt src gt Function Description Flags Example Variations CMP Rmd Rms Bytes States Encoding Hex Code in Compare Subtracts the source operand from the destination operand The result is not stored in the destination operand If a borrow is needed for bit 7 the CY borrow flag is set otherwise it is clear When subtracting signed integers the OV flag indicates a negative result when a negative value is subtracted from a positive value or a positive result when a positive value is subtracted from a negative value Bit 7 in this description refers to the most significant byte of the operand 8 16 or 32 bit The source operand allows four addressing modes register direct immediate and indirect CY AC OV N Z V V V Register 1 contains 0 11001001 and register 0 contains 01010100B The instruction CMP R1 RO clears the CY and AC flags and sets the OV flag Binary Mode Source Mode 3 2 2 1 1011 1100 ssss 5555 Binary Mode A5 Encoding Source Mode Encoding A 47 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Operation CMP Rmd Rms CMP WRjd WRjs Binary Mode Source Mode Bytes 3 2
440. y phone for immediate delivery to your fax machine The BBS is a centralized computer bulletin board system that provides updated application specific information about Intel products Intel offers a variety of information through the World Wide Web URL http www intel com Select Embedded Design Products from the Intel home page 1 41 Howto Use Intel s FaxBack Service Think of the FaxBack service as a library of technical documents that you can access with your phone Just dial the telephone number and respond to the system prompts After you select a doc ument the system sends a copy to your fax machine Each document is assigned an order number and is listed in a subject catalog First time users should order the appropriate subject catalogs to get a complete listing of document order num bers The following catalogs and information packets are available 1 Microcontroller Flash and iPLD catalog Development Tools Handbook System catalog DVI and multimedia catalog BBS catalog Microprocessor and peripheral catalog Quality and reliability catalog PEE Dao Technical questionnaire 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel 1 42 How to Use Intel s Application BBS The Application Bulletin Board System BBS provides centralized access to information soft ware drivers firmware upgrades and revised software Any user with a modem and computer can access the BBS Use t
441. yte S FDH Compare Capture Module 4 High Byte S FEH tel intel REGISTERS ACC Address EOH Reset State 0000 0000B Accumulator ACC provides SFR access to the accumulator which resides in the register file as byte register R11 also named ACC Instructions in the MCS 51 architecture use the accumulator as both Source and destination for calculations and moves Instructions in the MCS 251 architecture assign no special significance to R11 These instructions can use byte registers Rm m 0 15 interchangeably 7 0 Accumulator Contents Bit Bit Number Mnemonic Function 7 0 7 0 Accumulator 82930A UNIVERSAL SERIAL BUS MICROCONTROLLER USER S MANUAL intel Address Reset State FOH 0000 0000B B Register The B register provides SFR access to byte register R10 also named B in the register file The B register is used as both a source and destination in multiply and divide operations For all other operations the B register is available for use as one of the byte registers Rm m 0 15 0 Register Contents Bit Bit Number Mnemonic Function 7 0 B 7 0 B Register intel REGISTERS CCAPXL x 0 4 Address PATH SE CCAP2H L S FCH S ECH CCAPSH L S FDH S EDH CCAP4H L S FEH S EEH Reset State XXXX XXXXB PCA Module Compare Capture Registers These five register pairs st
442. yte UCONFIG1 see also RD RD1 RDO Address Range for Assertion 0 0 All addresses 0 1 All addresses 1 0 All addresses 1 1 All addresses gt 80 0000 RD Read or 17th Address Bit A16 Read signal output to external data memory or 17th external address bit A16 depending on the values of bits RDO and RD1 in configuration byte UCONFIG1 See also PSEN RD1 RDO Function 0 0 The pin functions as A16 only 0 1 The pin functions as A16 only 1 0 The pin functions as P3 7 only 1 1 RD asserted for reads at all addresses x7F FFFFH 7 16 WR Write Write signal output to external memory For configuration bits RD1 0 11 WR is asserted for writes to all compatible MCS 51 microcontroller memory locations For other values of RD1 0 WR is asserted for writes to all memory locations P3 6 NOTE 15 2 tThe descriptions of A15 8 P2 7 0 and AD7 0 P0 7 0 are for the nonpage mode chip configuration compatible with 44 pin PLCC MCS 51 microcontrollers If the chip is configured for page mode operation port 0 carries the lower address bits A7 0 and port 2 carries the upper address bits A15 8 and the data D7 0 intel EXTERNAL MEMORY INTERFACE 15 2 EXTERNAL BUS CYCLES The section describes the bus cycles the 82930A executes to fetch code read data and write data in external memory Both page mode and nonpage mode are described and illustrated For sim plicity the accompanying f

82930A Universal Serial Bus Microcontroller User`s Manual

Contents

Download Pdf Manuals

Related Search

Related Contents