Home

Atari on an FPGA - ECE

Contents

1. Color Table SRAM VGA Out Video is generated in NTSC format by the Atari but the system uses a VGA display so the signal must be converted to VGA Since VGA and NTSC run at different clock rates the pixel data must be stored in an intermediate format as it is impossible to synchronize the two formats The converter works by emulating a screen It keeps an NTSC size copy of the current screen image in memory filling in pixels as they come out of the Atari each pixel clock Since blanking signals are shown between lines and frames the converter uses them to find the ends of lines and frames and move it s current pixel location accordingly The VGA controller then accesses this stored screen image and encodes a VGA signal based on it This project uses a premade VGA controller provided by Altera Because NTSC has one fourth the number of pixels in a scanline as VGA every four consecutive VGA pixels are read from the same stored image pixel The pixel colors stored in the SRAM are indexes in an Atari color table They must be passed into the color table to convert them to RGB values which are then passed to the VGA controller The screen image is too large to fit in memory on the FPGA so the external SRAM chip of the DE2 board is used Since the SRAM only has one read write port a state machine takes care of synchronizing accesses to it When the VGA controller is not blanking or syncing an
2. Catridge4k romFile cartridge hex address ATARI ROM Addr Clken ATARI ROM CS Clock ATARI CLOCKBUS q ATARI ROM Dout Clock generation modules wire ATARI CLOCKPIXEL16 ATARI CLOCKBUS16 wire DLY RST AtariClockGenerator areset DLY RST inclkO CLOCK 50 CO ATARI CLOCKPIXEL16 C1 ATARI CLOCKBUS16 ClockDivi6 inclk ATARI CLOCKPIXEL16 Outclk ATARI CLOCKPIXEL reset n RES n ClockDivi6 inclk ATARI CLOCKBUS16 Outclk ATARI CLOCKBUS reset n RES n Peripherals assign RES n DLY RST assign ATARI SW COLOR SW 0 assign ATARI SW SELECT KEY 0 assign ATARI SW START KEY 11 JOY A in ATARI JOY A in MySystem v 3 5 assign ATARI SW DIFF SW 2 1 assign ATARI JOY A in SW 7 3 assign ATARI JOY B in SW 12 8 NTSC to VGA converter Circular pixel buffers to temporarily store pixel data when the NGA controller has control of the SRAM reg 7 0 pixelColor 511 0 reg 8 0 pixelX 511 0 pixelY 511 0 reg 8 0 curWriteIndex curReadIndex NTSC Emulator reg 7 0 ATARI Video PixelX reg 8 0 ATARI Video PixelY reg R ATARI HBLANK reg 7 0 R ATARI COLOROUT always negedge ATARI CLOCKPIXEL begin Registered signals R ATARI HBLANK ATARI HBLANK R ATARI COLOROUT ATARI COLOROUT if RES n begin ATARI Video PixelX
3. outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor s outColor outcColor outColor outColor outColor outColor 24 hFFFFFF 24 h000000 24 h2121FF 24 hF03C79 24 hFF50FF 24 h7FFF00 24 h7FFFFF 24 hFFFF3F 24 hFFFFFF 24 h000000 24 h2121FF 24 hF03C79 24 hFF50FF 24 h7FFF00 24 h7FFFFF 24 hFFFF3F 24 hFFFFFF 24 h000000 24 h2121FF 24 hF03C79 24 hFF50FF 24 h7FFF00 24 h7FFFFF 24 hFFFF3F 24 hFFFFFF 24 h000000 24 h2121FF 24 hF03C79 24 hFF50FF 24 h7FFF00 24 h7FFFFF 24 hFFFF3F 24 hFFFFFF 24 h000000 24 h2121FF 24 hF03C79 24 hFF50FF 24 h7FFF00 24 h7FFFFF 24 hFFFF3F 24 hFFFFFF 24 h000000 24 h2121FF 24 hF03C79 24 hFF50FF 24 h7FFF00 24 h7FFFFF 24 hFFFF3F 24 hFFFFFF 24 h000000 24 h2121FF 24 hF03C79 24 hFF50FF 24 h7FFF00 24 h7FFFFF 24 hFFFF3F 24 hFFFFFF 24 h000000 24 h2121FF 24 hF03C79 24 hFF50FF 24 h7FFF00 24 h7FFFFF 24 hFFFF3F 24 hFFFFFF 24 h000000 24 h2121FF 24 hF03C79 24 hFF50FF 24 h7FFF00 24 h7FFFFF 24 hFFFF3F 24 hFFFFFF 24 h000000 TIAColorTable v 6 6 9 d337 9 d338 910339 9 d340 9 d341 9 d342 9 d343 9 d344 910345 9 d346 9 d347 9 d348 9 d349 9 d350 913351 9 d352 9 d3
4. 8 d0 ATARI Video PixelY 9 d0 curWriteIndex 9 d0 end else begin Use the end of the horizontal blanking signal to find the end of the scanline LE ATARI_HBLANK begin ATARI Video PixelX lt 8 d0 At the end of a scanline move down one scanline if R ATARI HBLANK amp ATARI VBLANK ATARI Video PixelY lt ATARI Video PixelY 9 d1 end If we are not blanking go to the next pixel in the scanline else ATARI Video PixelX lt ATARI Video PixelX 8 d1 Use the vertical blanking signal to find the end of the frame LE ATARI_VBLANK ATARI Video PixelY lt 9 d0 Write the pixel location and color to the circular buffer pixelColor curWriteIndex lt R ATARI COLOROUT pixelX curWriteIndex lt 1 b0 ATARI Video PixelX pixelY curWriteIndex ATARI Video PixelY curWriteIndex curWriteIndex 9 d1 end end NGA Controller wire VGA CTRL CLK wire AUD CTRL CLK wire 9 0 mVGA R wire 9 0 mVGA G wire 9 0 mVGA B wire 19 0 mVGA ADDR wire 9 0 Coord X Coord Y Reset Delay ro iCLK CLOCK 50 oRESET DLY RST iRESET KEY 3 VGA Audio PLL pl areset DLY RST inclkO CLOCK 27 cO VGA CTRL CLK c1 AUD CTRL CLK c2 VGA CLK VGA Controller ul Host Side ju MySystem v 4 5 iCursor RGB EN 4 b0111 oAddress mVGA ADDR oCoord X Coord X oCoord Y Coord Y iRed mVGA R iGreen mVGA G iBlue mVGA
5. RIOT h define READ RAM define WRITE RAM define READ DRA define WRITE DRA define READ DDRA define WRITE DDRA define READ DRB define WRITE DRB define READ DDRB define WRITE DDRB define WRITE TIMER define READ TIMER define READ INT FLAG define WRITE EDGE DETECT define NOP define TM_ define TM define TM 64 2 b10 define TM 1024 2 b11 7 bOlxxxxx 7 bOOxxxxx 7 b11xx000 7 b10xx000 7 b11xx001 7 bl10xx001 7 b11xx010 7 b10xx010 7 bllxx01l1 7 b10xx011 7 b101xlxx 7 b 11xx1x0 7 b11xx1x1 7 b100x1x0 7 b0100000 TIA v 1 7 Atari on an FPGA Masters of Engineering Project Cornell University 2007 Daniel Beer TIA v Redesign of the Atari TIA chip Sound generation and I O id include TIA h module TIA A Din Data bus input Dout Data bus output CS n Active low chip select input CS Chip select input R W n Active low read write input RDY CPU ready output MASTERCLK 3 58 Mhz pixel clock input CLK2 1 19 Mhz bus clock input Idump Dumped I O Ilatch Latched I O HSYNC Nideo horizontal sync output HBLANK Nideo horizontal blank output VSYNC Nideo vertical sync output VBLANK Nideo vertical sync output COLOROUT Indexed color output RES n Active low reset input input 5 0 A input 7 0 Din output 7 0 Dout input 2 0 CS n input CS input
6. amp 9 P00010101 3 d4 objSizeOn lt objByteIndex amp 9 b10000001 3 d5 objSizeOn lt objByteIndex amp 9 b00000011 3 d6 objSizeOn lt objByteIndex amp 9 b10010001 3 d7 objSizeOn lt objByteIndex amp 9 b00001111 endcase end always objSize objIndex begin case objSize 3 d5 objMaskSel lt objIndex 3 1 3 d7 objMaskSel lt objIndex 4 2 default objMaskSel objIndex 2 0 endcase end assign objMaskOn assign objPosOn assign pixelOn endmodule objMask objMaskSel pixelNum gt objPos amp amp 1 b0 pixelNum lt 1 b0 objPos 9 d72 objSizeOn amp amp objMaskOn amp amp objPosOn ooo TIA h 1 1 Atari on an FPGA Masters of Engineering Project Cornell University 2007 Daniel Beer TIA h E define CXMOP define CXMIP define CXPOFB define CXP1FB define CXMOFB define CXM1FB define CXBLPF define CXPPMM define INPTO define INPT1 define INPT2 define INPT3 define INPT4 define INPT5 define VSYNC define VBLANK define WSYNC define RSYNC define NUSIZO define NUSIZ1 define COLUPO define COLUP1 define COLUPF define COLUBK define CTRLPF define REFPO define REFP1 define PFO define PF1 define PF2 define RESPO define RESP1 define RESMO define RESM1 define RESBL define AUDCO define AUDC1 define AUDFO define AUDF1
7. verifying them for the correct values The Altera SignalTap module a logic analyzer that can be included in the system allowed these values to be extracted stored in a log and verified The test program used was an original unmodified Atari game Combat This game was used as it is very prolific and many disassemblies and analyses are available online for it The game consists of two players steering enemy tanks and firing missiles at each other Execution could be traced one instruction at a time while the state of the system could be verified so it matched the analysis of what the instruction should do While the original cartridge was available and could have been connected directly to the FPGA there was insufficient time to build a header for it Therefore a binary capture of the cartridge was used instead it s contents programmed into the cartridge module on the FPGA Finally a test of gross functionality was done with only the DE2 board and a VGA monitor The Atari system was used to play Combat and test the actual gameplay Most features worked correctly the game could be run screen objects were displayed on the VGA screen controls could be used to play the game and the game seemed to execute correctly in general A photo of the test display is shown below Incorrect missile placement Too many scanlines Stretched sprites There were a few problems with the final test all of which are highlighted on the photo
8. 9 d45 9 d46 9 d47 9 d48 9 d49 9 d50 91951 9 g523 9 d53 9 d54 9 d55u 9 d564 9 d57 9 d58 9 d594 9 d60 9 d6l 9 d62 9 d63 9 d64 9 d65 9 d66s 9 d67 9 d68 9 d69 9 370 9 471 9 d723 9 ga73 9 d74 9 d75 9 dT76 91977 91478 9 d79 9 d80 9 d81 9 d82 9 d83 9 d84 9 d85 9 d86 9 d87 9 d88 9 d89 9 gd90 9 d91 9 d92 9 g933 9 d94 9 d95 9 g96 9 d97 9 d98 9 d99 9 d100 9 d101 9 d102 9 d103 9 d104 9 d105 9 106 9 d107 9 d108 9 d109 9 d110 9 d111 9 112 9 dTL3 9 d114 9 dlr5 94118 9 dli7 9 d118 outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor cutColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor out Color outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outcolor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor s outColor outColor outColor outColor outColor outCo
9. HEXO HEX5 HEX1 HEX6 RESET HEX2 HEX7 HEX3 HEX4 Clock Input input E input CLOCK 50 PIVOT TIE ALAA TELAT ALI SRAM Interface inout 15 0 SRAM DQ output 17 0 SRAM ADDR output SRAM UB N output SRAM LB N output SRAM WE N output SRAM CE N output SRAM OE N HH MH M VGA output VGA CLK output VGA HS output VGA VS output VGA BLANK output VGA SYNC output 9 0 VGA R output 9 0 VGA G output 9 0 VGA B output TD RESET input 3 0 KEY output 8 0 LEDG output 17 0 LEDR input 17 0 SW output 6 0 HEXO HEX1 HEX2 HEX3 HEX4 HEX5 Turn off all LEDs assign HEXO 7 h7F assign HEX1 7 h7F assign HEX2 7 h7F assign HEX3 7 h7F assign HEX4 7 h7F Clock Input SRAM Interface CELULITI IAIL 27 MHz 17 50 MHz FITEPLITTILPELT 47 SRAM Data bus 16 Bits A SRAM Address bus 18 Bits 4 SRAM High byte Data Mask LI SRAM Low byte Data Mask Lf SRAM Write Enable 4 SRAM Chip Enable Vara SRAM Output Enable HH HH T Ji VGA Clock VGA H_SYNC VGA V_SYNC VGA BLANK VGA SYNC ii VGA Red 9 0 4 VGA Green 9 0 7 VGA Blue 9 0 27 Mhz Enable Push Buttons Green LEDs Red LEDs Switches 7 Segment displays RU AREE I POL PDL 27 MHz 50 MHz AISATI TTI TALS ETAL AT SRAM Data bus 16 Bits fy SRAM Address bus 18 Bits 4 SRAM High byte Data Mask SRAM Low byte Data Mask LI SRAM
10. R W n A T65 A DI Din DO Dout Sync EF MF XF ML n VP n VDA VPA assign A T65 A 12 0 assign T65 CLK CLK n endmodule
11. R W n output RDY input MASTERCLK input CLK2 input 1 0 Ilatch inout 3 0 Idump output HSYNC HBLANK output VSYNC VBLANK output 7 0 COLOROUT input RES n Data output register reg 7 0 Dout Video control signal wire HSYNC reg VSYNC VBLANK Address bus input registers Horizontal pixel counter reg 7 0 hCount reg 3 0 hCountReset Pixel counter update always posedge MASTERCLK begin Reset operation if RES n begin hCount 8 d0 hCountReset 3 1 3 d0 end else begin Increment the count and reset if necessary if hCountReset 3 hCount 8 4227 else hCount 8 d0 hCount hCount 8 d1 Software resets are delayed by three cycles Provides the Atari with video generation TIA v 2 7 hCountReset 3 1 lt hCountReset 2 0 end end assign HSYNC hCount gt 8 d20 amp amp hCount 8 d36 assign HBLANK hCount 8 d68 Screen object registers These registers are set by the software and used to generate pixels reg 7 0 playerOPos playerlPos missile0Pos missilelPos ballPos reg 4 0 playerosize playerlSize reg 7 0 playerOColor playeriColor ballColor pfColor bgcolor reg 3 0 playerOMotion playeriMotion missileOMotion missilelMotion ballMotion reg missileOEnable missilelEnable ballEnable R ballEnable reg 1 0 ballSize reg 19 0 pfGraphic reg 7 0 playe
12. amp wSync amp amp inputLatchEnabled ch 1 0 6 b000000 ch 3 2 6 b000000 lt collisionLatch 5 4 6 b000000 collisionLatch 7 6 6 5000000 collisionLatch 9 8 6 5000000 collisionLatch 11 10 6 b000000 collisionLatch 12 7 b0000000 collisionLatch 14 13 6 b000000 lt Idump 0 7 b0000000 sValue 0 7 b0000000 INPTO Dout INPT1 Dout lt Idump 1 7 b0000000 INPT2 Dout lt Idump 2 7 b0000000 INPT3 Dout lt Idump 3 7 b0000000 INPT4 Dout lt latchedInput INPT5 Dout lt latchedInput Video signals VSYNC VSYNC lt Din 1 VBLANK begin input sValue 1 7 b0000000 LatchEnabled lt Din 6 inputDumpEnabled lt Din 7 VBLANK lt Din 1 end WSYNC RSYNC Screen object register acc NUSIZO playeroSize lt Din NUSIZ1 playerlSize lt Din COLUPO playerocolor lt Din COLUP1 playeriColor lt Din COLUPF pfColor lt Din COLUBK bgcolor lt Din CTRLPF begin pfRef ess 5 4 Din 2 01 5 4 Din 2 01 lect lt Din 0 pfColorCtrl lt Din 1 prioC balls end trl lt Din 2 ize lt Din 5 4 REFPO playerOReflect lt Din 3 REFP1 playerlReflect lt Din 3 PFO pfGraphic 3 0 lt Din 7 4 PF1 pfGraphic 11 4 lt Din 0 Din i1 Din 2 Dinl 3 Din 4 Din 5 Din 6 Din 7 PF2 pfGra
13. buttons and switches mapped to the Atari s controls Original unmodified Atari software is tested with the system and the execution is mostly correct Small problems with the video generation and sprite system are the only noticeable errors Design Problem The Atari 2600 is a computer system whose design has become very impractical to reimplement When the system was first designed in the 1980s the logic technologies available required optimized design using practices that are now outdated For example almost all counters in the original design are polynomial counters used for their quick update time However polynomial counters do not count in numerical order making all logic that relies on the count difficult to understand Also many different clock signals and cascading output registers prevent synchronous analysis of the system These practices and others result in complex schematics detailing a partially asynchronous design rw VIDEO COMPUTER SYSTEM 2i cotor f e kJ m The Atari 2600 System In addition to this the schematics reference discontinued commercial parts that exist today only as documentation The design calls for video memory and timer chips manufactured by the now defunct MOS Technologies company and Atari hardware division Useful documentation for these include Atari programmer s manuals hardware specification sheets and readily available analyses of the parts from the Atari community The
14. goal of this project is to recreate the design of the Atari 2600 using modern synchronous design and current technologies Synchronous designs allow for a more robust and flexible system as one can ensure correct operation of the system as long as input clock requirements are met The technologies used include hardware description languages Verilog VHDL field programmable gate arrays FPGAs phase locked loop PLL clock generation and the video graphics array VGA standard for video generation Further this project aims to create a clear and well organized implementation of the system that is easily understandable and can be used in different contexts with few changes System Requirements The design project consists of a mostly functioning Atari 2600 implemented in Verilog VHDL running on an Altera DE2 development board and displaying on a VGA monitor All functionality of the original system is implemented except for the built in sound processor a decision made to simplify the scope of the project In addition to that a open source version of the Atari s main processor is used instead of being made as part of the project Intricacies in the system and lack of full documentation make some features hard to implement completely so fully correct execution is not required for all features Range of solutions Software Emulation of computer systems in software on a host computer is an effective but potentially wasteful technique A sof
15. hFFFF3F 24 hFFFFFF ClockDiv16 v 1 1 Atari on an FPGA Masters of Engineering Project Cornell University 2007 Daniel Beer ClockDiv16 v Clock divider used to generate atari clocks Divides the clock by 16 counts Li module ClockDiv16 inclk Input clock signal outclk Output clock signal reset n Active low reset signal input inclk reset n output outclk Count register reg 15 0 cnt reg outclk Use a 16 bit shift register to divide the clock by 16 counts always posedge inclk negedge reset_ n begin if reset n cnt lt 16 40 else begin ent lt cnt 14 0 cnt 15 outclk lt cnt 15 end end endmodule MOS6507 v 1 1 Atari on an FPGA Masters of Engineering Project Cornell University 2007 Daniel Beer MOS6507 v Wrapper for a 6502 CPU module that emulates the MOS 6507 module MOS6507 A 13 bit address bus output Din 8 bit data in bus Dout 8 bit data out bus RWn Active low read write output CLK n Negated clock signal RDY Active high ready line RES n Active low reset line output 12 0 A input 7 0 Din output 7 0 Dout output R W n input CLK n input RDY input RES n Instatiate a 6502 and selectively connect used lines wire 23 0 T65 A wire T65 CLK T65 Mode 2 b0 Res n RES n Clk T65 CLK Rdy RDY Abort n 1 bl1 IRO n 1 b1 NMI n 1 b1 SO n 1 bl1 R W n
16. indexed color output ROM CS ROM chip select output ROM Addr ROM address output ROM Dout ROM data input RES n Active low reset input HSYNC Video horizontal sync output HBLANK Nideo horizontal blank output VSYNC Nideo verical sync output VBLANK Video verical blank output SW COLOR Color BW switch input SW DIFF Difficulty switch input SW SELECT Select switch input SW START Start switch input JOY A in Joystick A inputs JOY B in Joystick B inputs input CLOCKPIXEL CLOCKBUS output 7 0 COLOROUT output ROM CS output 11 0 ROM Addr output HSYNC HBLANK VSYNC VBLANK input 7 0 ROM Dout input RES n input SW COLOR SW SELECT SW START input 1 0 SW DIFF input 4 0 JOY A in JOY B in MOS6507 CPU wire 12 0 CPU Addr reg 7 0 CPU Din wire 7 0 CPU Dout wire CPU R W n wire CPU CLK n wire CPU RDY wire CPU RES n MOS6507 cpu A CPU Addr Din CPU Din Dout CPU Dout CLK n CPU CLK n RDY CPU RDY assign CPU CLK n CLOCKBUS assign CPU RES n RES n assign ROM Addr CPU Addr 11 0 assign ROM CS CPU Addr 12 R W n CPU R W n R n ES n CPU RES n MOS6532 RIOT module wire 6 0 RIOT Addr wire 7 0 RIOT Din wire 7 0 RIOT Dout wire RIOT CS RIOT CS n RIOT R W n RIOT RS n RIOT RES n RIOT CLK wire RIOT IRO n wire 7 0 RIOT PAin RIOT PBin wire 7 0 RIOT PAout RIOT PBout RI
17. 4 h747474 24 h949494 24 hB4B4B4 24 hDODODO 24 hECECEC 24 h000000 24 h2121FF 24 hF03C79 24 hFF50FF 24 h7FFF00 24 h7FFFFF 24 hFFFF3F TIAColorTable v 5 6 9 A263 9 d264 919265 9 4266 9 A267 9 d268 9 A269 9 d270 9 d271 9 d272 9 d273 9 d274 919275 OT d2 76 9 d277 9 d278 9 d279 9 d280 9 d281 9 32821 9 d283 9 d284 9 d285 9 d286 9 d287 9 d288 9 d289 9 d290 9 d2914 9 d292 9 d293 9 d294 9 d295 9 d296 9 d297 9 d298 9 d299 9 d300 919301 9 A302 9 d303 9 d304 9 gsos 9 d306 9 d307 9 d308 9 d309 9 d310 9 a3 Lic 9 qd312 9 d313 9 d314 9 d315 9 d316 9 d317 9 d318 g d3l9 9 d320D4 9 d321 9 303221 9 d3231 9 d324 9 d325 9 d326 9 d3275 9 d328 9 d329 9 d330 94331 9 d332 9 d333 9 d334 9 d335 9 d336 outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor
18. 53 9 d354 9 d355 9 d356 9 d357 9 3358 9 d359 9 d360 9 d361 9 d362 9 d363 9 d364 9 d365 9 d366 9 d367 9 d368 9 d369 9 d370 9 d371 9 d372 9 d3 73 9 d374 9 d375 9 d376 9 d377 9 d378 9 qd379 9 qd380 9 qd381 9 qd382 9 qd383 endcase end endmodule outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor 24 h2121FF 24 hF03C79 24 hFF50FF 24 h7FFF00 24 h7FFFFF 24 hFFFF3F 24 hFFFFFF 24 h000000 24 h2121FF 24 hF03C79 24 hFF50FF 24 h7FFF00 24 h7FFFFF 24 hFFFF3F 24 hFFFFFF 24 h000000 24 h2121FF 24 hF03C79 24 hFF50FF 24 h7FFF00 24 h7FFFFF 24 hFFFF3F 24 hFFFFFF 24 h000000 24 h2121FF 24 hF03C79 24 hFF50FF 24 h7FFF00 24 h7FFFFF 24 hFFFF3F 24 hFFFFFF 24 h000000 24 h2121FF 24 hF03C79 24 hFF50FF 24 h7FFF00 24 h7FFFFF 24 hFFFF3F 24 hFFFFFF 24 h000000 24 h2121FF 24 hF03C79 24 hFF50FF 24 h7FFF00 24 h7FFFFF 24
19. 8C PAL Colors 9 d128 outColor 24 h000000 9 d129 outColor 24 h282828 9 d130 outColor 24 h505050 9 d131 outColor 24 h747474 9 d132 outColor 24 h949494 9 d133 outColor 24 hB4B4B4 9 d134 outColor 24 hD0D0D0 9 d135 outColor 24 hECECEC 9 d136 outColor 24 h000000 9 d137 outColor 24 h282828 9 3d138 outColor 24 h505050 9 d139 outColor 24 h747474 9 d140 outColor 24 h949494 9 d141 outColor 24 hB4B4B4 9 d142 outColor 24 hDODODO 9 d143 outColor 24 hECECEC 9 d144 outColor 24 h805800 9 d145 outColor 24 h947020 9 d146 outColor 24 hA8843C 9 d147 outColor 24 hBC9C58 9 d148 outColor 24 hCCAC70 9 d149 outColor 24 hDCC084 9 d150 outColor 24 hECD09C 9 d151 outColor 24 hFCEOBO0 9 d152 outColor 24 h445C00 9 d153 outColor 24 h5C7820 9 d154 outColor 24 h74903C 9 d155 outColor 24 h8CAC58 9 d156 outColor 24 hA0C070 9 d157 outColor 24 hB0D484 9 d158 outColor 24 hC4E89C 9 d159 outColor 24 hD4FCBO 9 d160 outColor 24 h703400 9 d161 outColor 24 h885020 9 d162 outColor 24 hA0683C 9 d163 outColor 24 hB48458 9 d164 outColor 24 hC89870 9 d165 outColor 24 hDCAC84 9 dl66 outColor 24 hECCO9C 9 d167 outColor 24 hFCDA4B0 9 d168 outColor 24 h006414 9 d169 outColor 24 h208034 9 d170 outColor 24 h3C9850 9 d171 outColor 24 h58B06C 9 d172 outColor 24 h70C484 9 d173 outColor 24 h84D89C
20. 9 d174 outColor 24 h9CE8B4 9 dl175 outColor 24 hBOFCCS 9 d176 outColor 24 h700014 9 d177 outColor 24 h882034 9 d178 outColor 24 hA03C50 9 d179 outColor 24 hB4586C 9 d180 outColor 24 hC87084 9 d181 outColor 24 hDC849C 9 d182 outColor 24 hEC9CB4 9 d183 outColor 24 hFCBOC8 9 d184 outColor 24 h005C5C 9 d185 outColor 24 h207474 9 d186 outColor 24 h3C8C8C 9 d187 outColor 24 h58A4A4 9 d188 outColor 24 h70B8B8 9 d189 outColor 24 h84C8C8 9 d190 outColor 24 h9CDCDC TIAColorTable v 4 6 9 d191 919192 913193 9 d194 9 d195 9 d196 9 d197 9 d198 9 d199 9 d200 9 d201 9 0202 9 3203 9 d204 913205 9 0206 9 d207 9 d208 9 209 9 d210 913211 9192123 9 d213 9 d214 9 g215 9 d216 9 0217 9 3218 9 d219 910220 97 3221 9 3222 9 3223 9 d224 9 d225 9 3226 9 3227 9 3228 9 229 973230 9 d231 9 0232 973233 9 d234 9 d235 9 3236 910231 9 0238 9 3239 9 d240 9 d241 9 d242 9 d243 9 d244 9 d245 9 d246 9 d247 9 d248 9 d249 9 9250 9 d251 9 d252 9 d253 9 d254 9102553 outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor ou
21. Atari on an FPGA A Design Project Report Presented to the Engineering Division of the Graduate School of Cornell University in Partial Fulfillment of the Requirements for the Degree of Master of Engineering Electrical by Daniel Beer Project Advisor Bruce Land Degree Date May 2007 Abstract Master of Electrical Engineering Program Cornell University Design Project Report Project Title Atari on an FPGA Author Daniel Beer Abstract This report presents a full redesign of Atari 2600 computer system using modern digital design techniques and modern hardware The system is designed to be synchronous and modular is implemented in Verilog and VHDL and run on an Altera Cyclone II using a VGA display The hardware package chosen for this project is the Altera DE2 development board which pairs an Altera Cyclone II chip with a number of useful components Almost all of the major components of the system have been designed from functional descriptions and schematics This includes the MOS 6532 RIOT chip and Atari TIA chip that provide most of the needed functionality for the system However the Atari s CPU a MOS 6507 was adapted from an open source project and sound hardware was not implemented in this project Other hardware made for this project includes an NTSC to VGA converter clock generator bus controller and software cartridge emulator Each piece of hardware was first tested separately then combined into the full sys
22. B fy VGA Side oVGA R VGA R oVGA G VGA G oVGA B VGA B oVGA H SYNC VGA HS oVGA V SYNC VGA VS oVGA SYNC VGA SYNC i oVGA BLANK VGA BLANK Control Signal iCLK VGA CTRL CLK iRST N DLY RST SRAM registers and controls reg 17 0 addr reg Memory address register for SRAM reg 15 0 data reg Memory data register for SRAM reg we Write enable for SRAM assign SRAM ADDR addr reg assign SRAM DQ we 16 hzzzz data reg assign SRAM UB N 0 hi byte select enabled assign SRAM LB N 0 lo byte select enabled assign SRAM CE N 0 chip is enabled assign SRAM WE N we write when ZERO assign SRAM OE N 0 output enable is overidden by WE Connect the color table to the SRAM wire CT clk wire 3 0 CT lum wire 3 0 CT hue wire 1 0 CT mode wire 23 0 CT outColor TIAColorTable clk CT clk lum CT lum hue CT hue mode CT mode outColor CT outColor VGA CTRL CLK Il assign CT_clk assign CT_lum SRAM DQ 3 0 assign CT_hue SRAM DQ 7 4 assign CT mode 2 b00 Il Show the color table output on the VGA assign mVGA R CT outColor 23 16 2 CT_outColor 23 16 2 b0 assign mVGA G CT outColor 15 8 2 CT outColor 15 8 2 b0 assign mVGA B CT outColor 7 0 2 CT_outColor 7 0 2 b0 State machine to synchronize accesses to the SRAM wire syncing assign syncing VGA VS VGA HS always po
23. OT A RIOT Addr Din RIOT Din Dout RIOT Dout CS RIOT CS CS n RIOT CS n R W n RIOT R Won RS n RIOT RS n RES n RIOT RES n IRQ n RIOT IRQ n CLK RIOT CLK PAin RIOT PAin PAout RIOT PAout PBin RIOT PBin PBout RIOT PBout assign RIOT Addr CPU Addr 6 0 assign RIOT Din CPU Dout assign RIOT CS CPU Addr 7 assign RIOT CS n CPU Addr 12 assign RIOT R Wn CPU R_W n assign RIOT RS n CPU Addr 9 assign RIOT RES n RES n assign RIOT CLK CLOCKBUS Atari2600 v 2 2 assign RIOT PAin JOY A in 3 0 JOY B in 3 01 assign RIOT PBin TIA module wire 5 0 TIA Addr wire 7 0 TIA Din wire 7 0 TIA Dout wire 2 0 TIA CS n wire TIA CS wire TIA R W n wire TIA RDY wire TIA MASTERCLK wire TIA CLKO0 wire TIA CLK2 wire 1 0 TIA Ilatch wire 3 0 TIA Idump wire TIA HSYNC TIA HBLANK wire TIA VSYNC TIA VBLANK SW DIFF 2 d0 SW COLOR 1 d0 SW SELECT SW START ES n wire 7 0 TIA COLOROUT wire TIA RES n TIA A TIA Addr Din TIA Din Dout TIA Dout CS n TIA CS n CS TIA CS R W n TIA R W n RDY TIA RDY MASTERCLK TIA MASTERCLK CLK2 TIA CLK2 Idump TIA Idump Ilatch TIA Ilatch HSYNC TIA HSYNC HBLANK TIA HBLANK VSYNC TIA VSYNC VBLANK TIA VBLANK COLOROUT TIA COLOROUT RES n TIA R assign TIA Addr CPU Addr 5 0 assign TIA Din CPU Dout assign TIA CS n CPU Addr 12 C
24. PU Addr 7 1 b0j assign TIA CS 1 b1 assign TIA R W n CPUR W n assign TIA RDY CPU RDY assign TIA CLK2 CLOCKBUS assign TIA MASTERCLK CLOCKPIXEL assign TIA RES n RES n assign COLOROUT TIA COLOROUT assign HSYNC TIA HSYNC assign HBLANK TIA HBLANK assign VSYNC TIA VSYNC assign VBLANK TIA VBLANK assign TIA Ilatch J0Y B in 4 JOY A in 41 Bus Controller always CPU Addr RIOT Dout TIA Dout ROM Dout begin if CPU Addr 12 CPU Din ROM Dout else if CPU Addr 7 CPU Din RIOT Dout else CPU Din TIA Dout end endmodule RIOT v 1 3 Atari on an FPGA Masters of Engineering Project Cornell University 2007 Daniel Beer RIOT v Redesign of the MOS 6532 chip Provides RAM I O and timers to the Atari include RIOT h module RIOT A Address bus input Din Data bus input Dout Data bus output CS Chip select input CS n Active low chip select input RWn Active low read write input RS n Active low rom select input RES n Active low reset input IROn Active low interrupt output CLK Clock input PAin 8 bit port A input PAout 8 bit port A output PBin 8 bit port B input PBout 8 bit port B output input 6 0 A input 7 0 Din output 7 0 Dout input CS CS n R Wn RS n RES n CLK output IRQ n input 7 0 PAin PBin output 7 0 PAout PBout Output registe
25. RAM Access State Machine VGA Clock In Color Table VGA Controller VGA Out RIOT v Redesign of the MOS 6532 chip Provides RAM I O and timers to the Atari RIOT h Header file that contains useful definitions for the RIOT module Output Ports Data Direction Registers Masking I O Input Ports Logic Registers e Status Register Prescaler Prescale Counter Table Counter Data In Address In Control RAM Clock In Logic Block Output Register Data Out Interrupt Request TIA v Redesign of the Atari TIA chip Provides the Atari with video generation sound generation and I O TIA h Header file that contains useful definitions for the TIA module CPU Enable Out Latched Inputs Dumped Inputs Color Out Latched I O Registers Dumped I O Controls Dumped I O Registers Output Register WSYNC Latch Data In Address In Control Bus Clock In Logic HSYNC HBLANK Out HBLANK Logic HSYNC Out Pixel Clock In Horizontal Counter vsyNc BLANK Out VBLANK Register VSYNC Out Player Pixel Registe
26. Write Enable Zi SRAM Chip Enable SRAM Output Enable 747 87 9 AI 9749 9 0749 I ULILA A VGA Clock VGA H_SYNC fi VGA V SYNC VGA BLANK VGA SYNC VGA Red 9 0 Vea VGA Green 9 0 Lf VGA Blue 9 0 AA Pushbutton 3 0 EX7 HEX6 H MySystem v 2 5 assign HEX5 7 h7F assign HEX6 7 h7F assign HEX7 7 h7F assign LEDG 0 assign LEDR 0 Turn on the 27 Mhz clock assign TD RESET 1 b1 Atari System wire ATARI CLOCKPIXEL ATARI CLOCKBUS wire 7 0 ATARI COLOROUT wire ATARI ROM CS wire 11 0 ATARI ROM Addr wire 7 0 ATARI ROM Dout wire ATARI HSYNC ATARI HBLANK ATARI VSYNC ATARI VBLANK wire ATARI SW COLOR ATARI SW SELECT ATARI SW START wire 1 0 ATARI SW DIFF wire 4 0 ATARI JOY A in ATARI JOY B in wire RES n Atari2600 CLOCKPIXEL ATARI CLOCKPIXEL CLOCKBUS ATARI CLOCKBUS COLOROUT ATARI COLOROUT ROM Addr ATARI ROM Addr ROM CS ATARI ROM CS ROM Dout ATARI ROM Dout HSYNC ATARI HSYNC HBLANK ATARI HBLANK VSYNC ATARI VSYNC VBLANK ATARI VBLANK RES n RES n SW COLOR ATARI SW COLOR SW DIFF ATARI SW DIFF SW SELECT ATARI SW SELECT SW START ATARI SW START JOY B in ATARI JOY B in Cartridge module Catridge2k romFile cartridge hex address ATARI ROM Addr 10 0 Clken ATARI ROM CS Clock ATARI CLOCKBUS q ATARI ROM Dout Uncomment this block to use 4k cartridges
27. above Debugging the entire system is time consuming and involved as it involves analyzing millions of instructions per second Even a scanline consists of hundreds of instructions and can be hard to isolate The first problem was that too many scanlines were being drawn by the Atari per frame causing the bottom of the display to be cut off In addition to this execution of the game was slow running at less than 30 frames per second Some scanlines were obviously doubled where they shouldn t have been stretching parts of the sprites vertically This symptom was very hard to diagnose as it could be caused by many parts of the Atari system The problem seems to be caused by a WSYNC signal behaving improperly if a WSYNC is signaled at the beginning of the next scanline instead of being at the end of the scanline before the scanline will be doubled and a scanline worth of time will be wasted One possible cause of this is that the CPU might not be cycle accurate however it was not created as part of this project and debugging of it proved to be too hard It is also possible that the WSYNC signal is not implemented properly however closer debugging has turned up no specific problems Finally the NTSC to VGA converter might be doubling lines but this would not account for the slow down of the software The other problem with the system is improper missile behavior In the Combat game missiles should remain stationary until they are launched How
28. allows for a structured testing process where a test suite can be made for each module supplying it with test inputs and checking for the correct output for those inputs Synchronous Design Most digital circuits designed today in computer systems follow the technique of synchronous design The idea behind the technique is to reduce the entire system to a state and logic to update the state The update logic can include inputs to the system and output logic uses the current state to create the outputs This gives the designer an easy way to verify the correctness of their design the resulting state machine can be mathematically analyzed or simulated and checked for the correct outputs Output Outputs Inputs pus Logic Clock A diagram of a synchronous system is shown above A global clock signal is distributed throughout the system and used to signal all updates The state is kept in registers and updated on every edge of the clock signal Synchronous design simplifies the timing analysis of the system The maximum clock speed can be determined from the amount of time the update logic takes to resolve This can then be used to find the timing requirements on the input and derive timing characteristics for the output High Level Design System Design Controller Clock Input Clock Input C
29. are these must be retrieved before the compilation 1 Download the T65 CPU package from opencores org which can be found at http www opencores org projects cgi web t65 and decompress the archive Copy the following files from the archive s t65 rtl vhdl directory to the project s 6502 directory T65 vhd T65_ALU vhd T65 MCode vhd T65_Pack vhd 2 Download the DE2 System package from http www terasic com downloads cd rom de2 and decompress the archive Copy the following files from the archive s DE2 demonstrations DE2 Default directory to the projects VGA directory VGA Audio PLL v Reset Delay v Then copy the following files from the archive s DE2 demonstrationsDE2 DefaultVGA Controller directory to the projects VGA directory VGA_Controller v VGA Param h 3 Software to be loaded into the compiled Atari must be placed in the project s root directory It should be in Intel HEX format and named cartridge hex If the software you have is in binary format it can be converted to Intel HEX format using the binex software found at http home hetnet nl newlife software Binex binex htm The project is set up to use 2k Atari cartridges but this can be switched to use the 4k cartridge module by editing MySystem v 4 Next open the project in Quartus II and make sure that the top level module is MySystem v Compile the project and program it to a DE2 board Connect a VGA monitor to the VGA connector The controls are as follows Sel
30. as the paddle consists of variable capacitor connected to a knob The design of the TIA module used in this project is primarily based off of the Stella Programmer s Guide the main source book for Atari programmers It contains a high level description of each component in the TIA as well as tips on how to use each part in Atari software Also listed inside are tables of register listings possible settings and their meaning WSYNC CPU Enable Out Latch Data In Sos Address In Control atched Bus Clock In Logic HSYNC HBLANK Out Latched Inputs Registers HBLANK Logic HSYNC Out _ Output Data Out f Register Pixel Clock In Horizontal VBLANK Out Dumped I O Counter VSYNCI lt Controls Dumped Inputs VELANE VSYNC Out A Register 91 N amp Out Zi Player Pixel Dumped I O Registers Logic L Priority Pixel Color Color Out Registers Hh Encoder Multiplexer Prot eon Screen Object Color E g Registers Ball Pixel Collision Collision Registers Logic Logic Latch A block diagram of the TIA module is shown above A horizontal counter keeps track of the current location in the scanline Settings for the video line are loaded into screen object registers and pixel l
31. bled execute an operation else if CS amp CS n begin Register inputs for use later R PA7 lt PA7 R op op R Din Din Update the timer interrupt flag casex op WRITE TIMER Timer Int Flag lt 1 b0 READ TIMER Timer Int Flag 1 b0 default if Timer 9 b111111111 Timer Int Flag lt 1 b1 endcase Update the port A interrupt flag casex op READ INT FLAG PA7 Int Flag 1 b0 default PA7 Int Flag lt PA7 Int Flag PA7 R PA7 amp PA7 PA7 Int Mode endcase Process the current operation casex op RAM access READ RAM Dout lt RAM A WRITE RAM RAM A lt Din Port A data access READ DRA Dout lt PAin amp DDRA DRA amp DDRA WRITE DRA DRA Din Port A direction register access READ DDRA Dout lt DDRA WRITE DDRA DDRA lt Din Port B data access READ DRB Dout lt PBin amp DDRB DRB amp DDRB WRITE DRB DRB Din Port B direction register access READ DDRB Dout DDRB WRITE DDRB DDRB lt Din Timer access READ TIMER Dout Timer 7 0 Status register access READ INT FLAG Dout lt Timer Int Flag PA7 Int Flag 6 b0 RIOT v 3 3 Enable the port A interrupt WRITE EDGE DETECT begin PA7 Int Mode lt A 0 PA7 Int Enable lt A 1 end endcase end Even if the chip is not enabled update background functions e
32. d into the bus controller Multiplexers are used to make connections between the input and output data busses based on the value of the address line Clock Generator Execution of the Atari code and video generation rely on steady and accurate global clocks This is because the software written for the system is timed on a cycle by cycle basis with programmers required to count cycles when writing the code For example the Atari video kernel is run in software requiring exact synchronization with the NTSC clock to display video on the screen 27 Mhz Clock PLL Multiply by 17 8 PLL Multiply by 17 24 Divide by 16 Divide by 16 Pixel Clock Bus Clock The clock generator expects a 27 Mhz signal as an input It then uses two PLLs to multiply the clock by 17 8 and 17 24 generating 57 375 Mhz and 19 125 Mhz clock signals These are then divided by 16 using a 16 bit shift register where a bit is shifted through before the output clock is negated The final clock signals generated are very close to 3 58 Mhz and 1 19 Mhz the required values Color Table NTSC to VGA Converter and VGA Controller NTSC Color In NTSC Control Signals In Pixel Clock In NTSC Emulation Logic Pixel Circular Pixel Buffer Counters SRAM Access State Machine ul VGA Clock In VGA Controller
33. d needs access to the data it is given access to the address and data port of the SRAM so it can read pixels out Otherwise the NTSC to VGA converter has access to the SRAM filling the image with pixels Pixels generated by the NTSC to VGA converter are first placed in a circular buffer so they are not lost when the VGA controller has access to the SRAM Game Cartridge The basic Atari software cartridge is a simple addressable ROM chip containing 2 kilobytes or 4 kilobytes of memory the largest amount of contiguous memory addressable using the address lines As the Atari got more mature companies started packing more into the cartridge including extra memory that could be bank switched more RAM or even special processing units Bank switching allows the Atari to address more memory by separating the memory into 4 kilobyte banks then specifying a special address that can be used to switch the banks into the main address space Using this method as much as 128 kilobytes of data were fit into a single Atari cartridge though only 4 kilobytes were accessible at a time For this project 2 kilobyte and 4 kilobyte cartridge modules were created by instantiating a block of ROM in the FPGA The main difference between the two is that the 2 kilobyte cartridge acts like a 4 kilobyte cartridge where the first half and second half of the ROM are mirrors of each other DE2 Testbench While the system is made general enough to use with many FPGA ty
34. define AUDVO define AUDV1 define GRPO define GRP1 define ENAMO define ENAM1 define ENABL define HMPO define HMP1 define HMMO define HMM1 define HMBL define V define VI define VDELBL R R define define define HMOVE define HMCLR define CXCLR Header file that contains useful definitions for the TIA module 7 h70 7 h71 7 h72 7 h73 7 h74 7 h75 7 h76 7 h77 7 h78 7 h79 7 h7A 7 h7B 75h7 7 h7D 7 h00 7 h01 7 h02 7 h03 7 h04 7 h05 7 h06 7 h07 7 h08 7 h09 7 h0A 7 hOB 7 hOC 7 hoD 7 hoE 7 hOF 7 h10 VEI 7 h12 7 h13 7 h14 7 h15 7 h16 7 h17 7 h18 7 h19 7 h1A 7 h1B 7 h1C 7 h1D 7 hlE 7 h1F 7 h20 7 h21 7 h22 7 h23 7 h24 7 h25 7 h26 7 h27 7 h28 7 h29 7 h2A 7 h2B 7 h2 TIAColorTable v 1 6 Atari on an FPGA Masters of Engineering Project Cornell University 2007 Daniel Beer TIAColorTable v Synchronous color lookup table that maps the Atari indexed colors to RGB module TIAColorTable clk Clock input lum 4 bit luminance input hue 4 bit hue input mode Mode input 0 NTSC 1 PAL 2 SECAM outColor 24 bit color output input clk input 3 0 lum input 3 0 hue input 1 0 mode output 23 0 outColor Output register reg 23 0 outColor Implicit instantiation of ROM on the FPGA to store the color table always posedge clk b
35. e ATARI CLOCKPIXEL ATARI CLOCKBUS wire 7 0 ATARI COLOROUT wire ATARI ROM CS wire 11 0 ATARI ROM Addr wire 7 0 ATARI ROM Dout wire ATARI HSYNC ATARI HBLANK ATARI VSYNC ATARI VBLANK wire RES n Atari System Atari2600 CLOCKPIXEL ATARI CLOCKPIXEL CLOCKBUS ATARI CLOCKBUS COLOROUT ATARI COLOROUT ROM CS ATARI ROM CS ROM Addr ATARI ROM Addr ROM Dout ATARI ROM Dout RES n RES n Cartridge Catridge2k romFile cartridge hex address ATARI_ROM Addr 10 0 clken ATARI ROM CS clock ATARI_CLOCKBUS q ATARI_ROM Dout Uncomment this block to use 4k cartridges Catridge4k romFile cartridge hex address ATARI_ ROM Addr clken ATARI ROM CS clock ATARI_CLOCKBUS q ATARI ROM Dout Clock Dividers wire ATARI CLOCKPIXEL16 ATARI CLOCKBUS16 ClockDivi6 inclk ATARI CLOCKPIXEL16 outclk ATARI CLOCKPIXEL reset n RES n ClockDivi6 inclk ATARI CLOCKBUS16 Outclk ATARI CLOCKBUS reset n RES n endmodule Atari2600 v 1 2 Atari on an FPGA Masters of Engineering Project Cornell University 2007 Daniel Beer Atari2600 v Atari system module Expects clock controller and switch inputs and a ROM port Outputs are the video signal and NTSC control signals ud module Atari2600 CLOCKPIXEL 3 58 Mhz pixel clock input CLOCKBUS 1 19 Mhz bus clock input COLOROUT 8 bit
36. ect Pushbutton 0 Start Pushbutton 1 Reset Pushbutton 3 Color BW Selection Switch 0 Difficulty Selection Switches 1 2 Joystick A Switches 3 7 Joystick B Switches 8 12 Appendix Diagrams and Code Listing The following is an overview of the code files created for the project and a short description of each Block diagrams from the text are shown after the files they were created from The code listing for the files is shown after the overview MySystem v Top level system for synthesis and programming on a DE2 board MySystemSim v Top level system for simulation purposes This can be run in the Quartus II simulator by supplying it with the necessary clocks and inputs Atari2600 v Atari system module Expects clock controller and switch inputs and a ROM port Outputs are the video signal and NTSC control signals Video Output SRAM Controller Ulock Input Clock Input Clock Generator Inputs Clock Clock I O Clock vO sc V i NT VGA CPU RIOT TIA d To Controller VGA Data Addr Data Addr Data Addr Clock Addr LN N Cartridge Data Bus Controller Atari 2600 NTSC Color In Circular Pixel Buffer NTSC Control Signals In NTSC x Emulation Riel j Pixel Clock In Logic Counters S
37. egin case mode hue lum 3 1 NTSC Colors 9 d0 outColor 24 h000000 9 d1 outColor 24 h404040 9 d2 outColor 24 h6C6C6C 9 d3 outColor 24 h909090 9 d4 outColor 24 hBOBOBO 9 d5 outColor 24 hC8C8C8 9 d6 outColor 24 hDCDCDC 9 d7 outColor 24 hECECEC 9 d8 outColor 24 h444400 9 d9 outColor 24 h646410 9 d10 outColor 24 h848424 9 dll outColor 24 hA0A034 9 d12 outColor 24 hB8B840 9 d13 outColor 24 hD0D050 9 d14 outColor 24 hE8E85C 9 d15 outColor 24 hFCFC68 9 d16 outColor 24 h702800 9 d17 outColor 24 h844414 9 d18 outColor 24 h985C28 9 d19 outColor 24 hAC783C 9 d20 outColor 24 hBC8C4C 9 d21 outColor 24 hCCA05C 9 d22 outColor 24 hDCB468 9 d23 outColor 24 hECC878 9 d24 outColor 24 h841800 9 d25 outColor 24 h983418 9 d26 outColor 24 hAC5030 9 d27 outColor 24 hC06848 9 d28 outColor 24 hD0805C 9 d29 outColor 24 hE09470 9 d30 outColor 24 hECA880 9 d31 outColor 24 hFCBC94 9 d32 outColor 24 h880000 9 d33 outColor 24 h9C2020 9 d34 outColor 24 hB03C3C 9 d35 outColor e 24 hC05858 9 d36 outColor 24 hD07070 9 d37 outColor 24 hE08888 9 d38 outColor 24 hECA0A0 9 d39 outColor 24 hFCB4B4 9 d40 outColor 24 h78005C 9 d41 outColor 24 h8C2074 9 d42 outColor 24 hA03C88 9 d43 outColor 24 hB0589C 9 d44 outColor 24 hC070B0 TIAColorTable v 2 6
38. en objects If two objects are drawn on the same pixel a specific bit in the collision latch is set to high depending on what layers the two objects are on The collision latch register can be read by the programmer to check for collisions Another feature the TIA provides is synchronization control Synchronizing the CPU with the video output is very important to proper execution of the software The main method the TIA provides is to halt the processor until the beginning of the next scanline An Atari programmer triggers this by strobing the WSYNC address after which they can be guaranteed that the next instruction executed corresponds to the next scanline The TIA provides two special types of I O ports for specific purposes The first are the two latched input ports which latch to a low input until they are reset to high These are used for the controller button inputs so the programmer can check if the user pressed a button even if the button was not held down There are also two dumped inputs which are normally pulled to logic low internally in the TIA When they are triggered by the programmer the pull down is disconnected allowing the line to be pulled externally to logic high The level of the line can then be read allowing the programmer to check how long it takes for the line to be pulled high and effectively determine the capacitance on the port This is used for to determine the state of a paddle controller connected to the port
39. ess registers that change the TIA behavior while a few trigger events when the address is strobed or written to The audio generation circuits are outside of the scope of this project and as such are not discussed The video generator is effectively a shift register that can be loaded in parallel with the screen objects Video lines loaded into the TIA are constantly sent out to the display at the correct speed along with the horizontal sync signal needed to synchronize the display to the video signal Vertical sync signals must be manually triggered by the Atari programmer as well as vertical blank signals The Atari creates frames that are 160x192 pixels with 68 pixels of horizontal blanking per line 40 lines of vertical sync and vertical blank per frame and 30 lines of overscan per frame Screen objects can include two 8 pixel wide sprites a ball two missiles and a background image or playfield For every scanline the Atari programmer loads single line sprite slices ball and missile graphics and a slice of the playfield into the TIA for each line The ball and missile graphics are picked from a list of preset graphics The position of each of these objects on the scanline can be changed as well as their colors and ordering The graphics can be stretched and duplicated while the playfield can be reflected Also a delay bit allows graphics to be loaded but delayed to the next scanline The TIA performs collision detection between all the scre
40. ever the missiles would move in a vertical line until they were launched Since the vertical placement of the missile is determined by the software this problem was also deemed a CPU problem pertaining to incorrect execution of an instruction Conclusions and Future Work In this project the Atari 2600 was redesigned using modern design techniques and technologies The resulting system was programmed onto an Altera DE2 development board and tested with original Atari software Tests showed that the system has all of the needed functionality to properly execute the software and only a few minor problems exist in the implementation Future work that could be done on the project includes an extension of the hardware part of the project to include connections for Atari cartridges and controllers References 1 6502 Introduction http www obelisk demon co uk 6502 2 Atari 2600 Schematics NTSC http www atariage com 2600 archives schematics index html 3 Wright Steve Stella Programmer s Guide Dec 1979 http www urchlay com stelladoc v2 4 Definitive Combat Disassembly http www atariage com 2600 archives combat_asm dicombat asm 5 Atari 2600 Specifications http nocash emubase de 2k6specs htm User s Manual This project requires Altera Quartus II 6 0 or higher to compile and an Altera DE2 development board to run on Since this project relies on a number of pieces of other softw
41. gy corporation The 6502 processor is an 8 bit RISC processor that features an accumulator two general purpose registers a stack pointer and many different addressing modes optimized for different situations It has the ability to address 64 kilobytes of memory and supports both maskable and non maskable interrupts An enable control allows the CPU to be halted The 6507 on the other hand can only address 8 kilobytes of memory and cannot respond to interrupts When the CPU is reset it immediately jumps to the reset vector and begins executing code An instruction can take from 1 to 5 cycles to execute as the processor is able to overlap an instruction fetch and execution Instructions are variable length consist of an opcode and possibly an immediate value and can be 1 or 2 bytes long One interesting feature of the processor is that it has over 100 undocumented opcodes many of which vary depending on the manufacturing specifics of the chip These opcodes were used by Atari programmers to pack multiple operations into a single instruction As recreation of the processor is outside the scope of this project an open source VHDL version of the 6502 called T65 is used found at Opencores org A 6507 shell module is created to integrate the processor into the Atari design The shell module renames the I O lines to match Atari nomenclature leaves some of the address lines floating and ties the interrupt lines to ground RIOT Chip The RIOT ch
42. ileoMotion 3 missileoMotion 3 0 missilelPos lt missilelPos 4 missilelMotion 3 missilelMotion 3 0 ballPos lt ballPos 4 ballMotion 3 ballMotion 3 0 end Motion register clear HMCLR begin playerOMotion lt Din 7 4 playerlMotion lt Din 7 4 missileOMotion lt Din 7 4 missilelMotion lt Din 7 4 ballMotion lt Din 7 4 end OXCLR default Dout 8 b00000000 endcase end If the chip is not enabled do nothing else begin inputLatchReset 1 b0 collisionLatchReset lt 1 b0 hCountReset 0 wSyncReset 1 b0 Dout lt 8 b0000 end end endmodule objPixelOn module lt 1 b0 0000 Checks the pixel number against a stretched and possibly duplicated version of the object module objPixelOn pixelNum obj objPos objMask input 7 0 pixelNum input 2 0 objSize Pos objSize objMask pixelOn TIA v TIT output pixelOn wire 7 0 objIndex wire 8 0 objByteIndex obj PosOn wire objMaskOn reg objSizeOn reg 2 0 objMaskSel assign objIndex pixelNum objPos 8 d1 assign objByteIndex always objSize 9 b1 lt lt objIndex 7 3 objByteIndex begin case objSize 3 d0 objSizeOn lt objByteIndex amp 9 b00000001 0 3 d1 objSizeOn lt objByteIndex amp 9 b00000101 3 d2 objSizeOn lt objByteIndex amp 9 P00010001 3 d3 objSizeOn lt objByteIndex
43. ip or MOS Technology s 6532 contains the Atari s RAM timers and partial I O system Communication with the CPU is done via an address line and data line There are 128 bytes of RAM on the chip all of which can be read from and written to In addition there are 16 I O lines each of which can be set as an input or output using an I O direction register An I O data register is then used to either set the output levels or read the input levels One of the I O lines can be used to detect input level edges and signal an interrupt Finally the chip contains a counter and status register The counter s update is tied to the input clock but can be prescaled by 1 8 64 or 1024 counts The clock is continuously running but can be reset by preloading it with a count When the count hits 0 an interrupt is signaled and a flag in the status register is raised The desired function of the chip is selected based on the address placed on the address line The ram is implemented using synchronous RAM on the FPGA In the original design the I O lines were implemented as single lines which could be tri stated however in the project each I O line has a separate output and input line These I O ports are used primarily for controller direction input and console switches Design of the RIOT chip was done from the functional specifications given in the MOS 6532 data sheet It contains address assignments high level descriptions of the different functions the chi
44. l test wire ballPixelOut ballPixelOn ballEnableDel reg 7 0 ballMask always e ballsize begin case ballSize 2 d0 ballMask 8 h01 2 d1 ballMask lt 8 h03 2 d2 ballMask lt 8 hOF 2 d3 ballMask 8 hFF endcase end objPixelOn pixelNum ballPos 3 d0 ballMask ballPixelOut assign ballEnableDel ballVertDelay R ballEnable ballEnable assign ballPixelOn ballPixelOut amp amp ballEnableDel Playfield color selection The programmer can select a unique color for the playfield or have it match the player s sprites colors reg 7 0 pfActualColor always pfColorCtrl pfColor player0Color playeriColor pfPixelNum begin if pfColorCtrl begin if pfPixelNum lt 6 d20 pfActualColor lt playerOColor else pfActualColor lt playerlColor end else pfActualColor lt pfColor end Final pixel color selection reg 7 0 pixelColor assign COLOROUT HBLANK 8 b0 pixelColor This combinational logic uses a priority encoder like structure to select the highest priority screen object and color the pixel always G prioCtrl pfPixelOn plOPixelOn pllPixelOn misOPixelOn mislPixelOn ballPixelOn pfActualColor playerocolor playerlColor bgColor begin Show the playfield behind the players if prioCtrl begin if plOPixelOn misoPixelOn pixelColor lt player0Color else if pliPixelOn misiPixelOn pixelColor lt playerlColor else if pfPixelO
45. lls then programmed to the FPGA In this way the FPGA can be used to prototype an actual hardware implementation of the design or even be included in the final design Altera DE2 Development Board from the Altera website This project uses Verilog and VHDL along with the Altera Cyclone II FPGA on an Altera DE2 Development board These were chosen because they are widely used in the industry today and easy to develop for PLL Clock Generation Phase locked loops PLLs are circuits that can modulate the frequency of an oscillating signal by a constant factor This can be used to generate accurate frequencies but only for ones that can be obtained by an integer multiply and integer divide of the original frequency In other words the frequency can only be multiplied by a rational number Input Clock Phase Variable Output Clock Detector Oscillator Frequency Divider The layout of a PLL is shown above It operates by creating a feedback control system where the difference between the desired frequency and output frequency is measured to get an error term which is then used to modify the output The phase detector measures the difference in phase between the two signals while the variable oscillator responds to the phase difference and generates a new output signal The feedback loop will continue to modify the output frequency until the error term disappears and the output freque
46. lock Generator Inputs Clock Clock I O Clock vO NTSC V CPU RIOT TIA To Cont er aeo Output Output VGA Data Addr Data Addr Data Addr Clock Addr 1 N Cartridge Data Bus Controller Atari 2600 The full project block diagram is shown above The Atari 2600 has three main modules the TIA chip which generates video the RIOT chip which contains the RAM and timers and the 6507 CPU All three modules share common data and address busses which can also connected via a header to an external cartridge ROM The CPU controls the address bus using it to address the cartridge ROM the RAM and various functions on the modules like memory mapped I O All modules have an input and output data line connected to the bus controller which makes the correct connections between them according to the address The system is driven by two clocks a 3 58 Mhz pixel clock and a 1 19 Mhz bus clock The pixel clock runs at NTSC speed running the video generator and pixel counter The bus clock runs the CPU the bus communications and all the module operations Both clocks are generated by the PLL clock generators from external clocks The RIOT and TIA chips handle controller input lines letting the CPU read their states Video signals are generated in the TIA chips passed to the NTSC to VGA converter then finally to the VGA controller to be output on the screen 6507 CPU The 6507 is a budget version of the widely used MOS6502 CPU from the MOS Technolo
47. lor 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 hD084C0 hDC9CD0 hECBOEO h480078 h602090 h783CA4 h8C58B8 hA070CC hB484DC hC49CEC hD4BOFC h140084 h302098 h4C3CAC h6858C0 h7C70D0 h9488E0 hA8AOEC hBCB4FC h000088 h1C209C h3840B0 h505CC0 h6874D0 h7C8CEO h90A4EC hA4B8FC h00187C h1C3890 h3854A8 h5070BC h6888CC h7C9CDC h90B4EC hA4C8FC h002C5C h1C4C78 h386890 h5084AC h689CCO0 h7CB4D4 h90CCE8 hA4EOFC h003C2C h1C5C48 h387C64 h509C80 h68B494 h7CDOAC h90E4C0 hA4FCD4 h003C00 h205C20 h407C40 h5C9C5C 24 h74B474 24 24 h8CD08C DA4E4A4 24 hB8FCB8 24 24 h143800 h345C1C 24 h507C38 24 24 h6C9850 h84B468 24 h9CCC7C 24 24 hB4E490 hC8FCAA 24 h2C3000 24 24 h4C501C h687034 24 h848C4C 24 24 h9CA864 hB4C078 24 hCCD488 TIAColorTable v 3 6 9 d119 outColor 24 hEOEC9C 9 d120 outColor 24 h442800 9 d121 outColor 24 h644818 9 d122 outColor 24 h846830 9 d123 outColor 24 hA08444 9 d124 outColor 24 hB89C58 9 d125 outColor 24 hDOB46C 9 d126 outColor 24 hE8CC7C 9 d127 outColor 24 hFCEO0
48. lse begin Update the timer interrupt if Timer 9 b111111111 Timer Int Flag lt 1 b1 Update the port A interrupt R PA7 lt PA7 PA7 Int Flag PA7 Int Flag PA7 R PA7 amp PA7 PA7 Int Mode Set the operation to a NOP R op lt NOP end end Update the timer at the negative edge of the clock always G negedge CLK begin Reset operation if RES n begin Timer lt 9 b0 Timer Mode 2 b0 Prescaler 10 b0 Timer Int Enable 1 b0 end Otherwise process timer operations else casex R op Write value to the timer and update the prescaler based on the address WRITE TIMER begin Timer lt 1 b0 R Din Timer Mode lt R op 1 01 Prescaler lt PRESCALER VALS R_op 1 0 Timer Int Enable R op 3 end Otherwise decrement the prescaler and if necessary the timer The prescaler holds a variable number of counts that must be run before the timer is decremented default if Timer 9 b100000000 begin if Prescaler 10 b0 Prescaler Prescaler 10 b1 else begin if Timer 9 b0 begin Prescaler 10 b0 Timer Mode 2 b0 end else Prescaler PRESCALER VALS Timer Mode Timer lt Timer 9 b1 end end endcase end endmodule RIOT h 1 1 Atari on an FPGA Masters of Engineering Project Cornell University Daniel Beer Header file that contains useful definitions for the RIOT module
49. n TIA v 4 7 pixelColor lt pfActualColor else pixelColor lt bgColor end Otherwise show the playfield in front of the players else begin if pfPixelOn pixelColor pfActualColor else if plOPixelOn misOPixelOn pixelColor lt player0Color else if pliPixelOn misiPixelOn pixelColor lt playerlColor else pixelColor lt bgColor end end Collision register and latching update wire 14 0 collisions reg collisionLatchReset assign collisions plOPixelOn amp amp pllPixelOn misOPixelOn amp amp mislPixelOn ballPixelOn amp amp pfPixelOn mislPixelOn amp amp pfPixelOn mislPixelOn amp amp ballPixelOn misOPixelOn amp amp pfPixelOn misOPixelOn amp amp ballPixelOn pliPixelOn amp amp pfPixelOn pllPixelOn amp amp ballPixelOn plOPixelOn amp amp pfPixelOn plOPixelOn amp amp ballPixelOn mislPixelOn amp amp plOPixelOn mislPixelOn amp amp pllPixelOn misOPixelOn amp amp pllPixelOn misOPixelOn amp amp plOPixelOn always posedge MASTERCLK posedge collisionLatchReset begin if collisionLatchReset collisionLatch lt 15 b000000000000000 else collisionLatch lt collisionLatch collisions end WSYNC logic When a WSYNC is signalled by the programmer the CPU ready line is lowered until the end of a scanline reg wSync wSyncReset always hCount wSyncReset begin if hCount 8 d3 wSync lt 1 b0 el
50. ncy settles on the desired frequency VGA and NTSC The video graphics array VGA and National Television Standards Committee NTSC standards are widely used protocols for sending a video signal to a display Both define a way for a video producer to synchronize with the screen blank the screen and display colors on the screen The display is organized into lines that it scans across filling with incoming data Horizontal sync signals are sent to tell the display to go to the next line while vertical sync signals tell the display to reset its position to the top of the display VGA data consists of a 640 x 480 pixel screen sent to the display at a communications rate of 25 Mhz with a variable refresh rate NTSC runs at 3 58 Mhz and uses a 262 line display running at 30 frames per second VGA colors are selected from a preset palette of colors while NTSC uses a color burst whose phase determines the colors shown The Atari is designed to create a NTSC signal however this is converted to a VGA signal in this project Design Techniques Modular Design This project is made up of a number of logical modules with a top level module which connects all the lower level modules Each module has its own functionality and can operate independently of the others giving the system a hierarchical structure and making it easier to understand Modules can be reused in the project if needed and also exported and used as part of other projects This also
51. ogic uses these registers to select the correct color for each pixel Like in the RIOT module enable lines on the registers are connected to the address input to selectively update the registers while the output register s value is selected using a multiplexer The pixel generation logic module is made to test if a screen object is on a pixel Objects can be stretched by a factor of 2 or 4 and can be duplicated a number of ways across the screen The inputs the module takes are the pixel position object position object width object duplication parameters and object graphic The pixel position and object position are tested to make sure the pixel can fall within the object Next the object position is subtracted from the pixel position to get an index into the object s pixels This object index is shifted down and checked against a mask table to make sure a copy of the object should appear at this position Finally the object index is checked against the object graphic to see if this pixel should be on If all three tests pass the module gives an output of 1 Bus Controller In the original Atari all the modules used the same data bus for reading and writing with the help of tri state buffers that removed their connection to the bus if they were not being addressed This relies on special hardware and can lead to line contention on the data bus Therefore in the updated design each module has its own input and output data bus which is fe
52. p can perform and timing diagrams which show the necessary timing characteristics of the inputs and outputs A module was created for the project that is functionally identical to the MOS 6532 Data Direction Registers mcos Output Ports Masking I O J Input Ports Logic Registers lise Status Register Prescaler Prescale Coler Output Data Out Table Counter Register Data In Address In Control RAM Clock In Logic Block Interrupt Request The layout of the redesigned RIOT chip is shown above The module contains a synchronous memory module timer unit and I O registers each with enable lines controlled by the address input A multiplexer controlled by the address input selects the value to place on the output line The timer is held in a register and a state machine and prescale counter are used to update the timer The I O registers are updated every clock cycle and the status register is updated based on the I O lines and the counter TIA Chip The TIA chip a custom chip from Atari provides the Atari s sprite and video generation sound generation and extra I O capabilities Access to the TIA chip is done using the shared address bus and data busses Like the RIOT chip the function of the chip is selected by the address Most addresses acc
53. pes a test bench must be made to tailor the system to the hardware that this project uses the Altera DE2 development board This board has a number of useful components for the project including a Cyclone If FPGA VGA connector external SRAM pushbuttons and switches This testbench connects the NTSC to VGA controller data port to the SRAM and the VGA controller to the VGA connector The switches and pushbuttons are connected to the data ports on the TIA and RIOT modules Finally a pushbutton is connected to the global reset signal a signal that resets all the components of the Atari and restarts the PLLs Results Testing and Results Each component was first tested by itself to verify correctness A sample system was made with only a RIOT module in it and test inputs were passed in while the outputs were verified Next the same was done with the TIA module setting up test scanlines then manually checking the output to make sure the correct pixels were generated The VGA generation units were fed with a sample synthesized NTSC signal and the output on the VGA display was verified After the components were verified they were connected together in the testbench using the original top level Atari schematics as a guide Software was loaded into the system by placing it in the cartridge module and testing was done on the system as a whole This was done mostly by tracing the execution of the program and analyzing various wires inside the design
54. phic 19 12 lt Din T7 0 RESPO playerOPos lt pixelNum RESP1 playerlPos lt pixelNum RESMO missile0Pos lt pixelNum RESM1 missilelPos lt pixelNum RESBL ballPos lt pixelNum Audio controls not implemented AUDCO VAUDCT AUDFO TIA v 6 7 AUDF1 AUDVO AUDV1 Screen object register access GRP0 begin playeroGraphic lt Din 0 Din 1 Din 2 DinI3 Din 4 Din 5 Din 6 Din 7 R_playerlGraphic lt playerlGraphic end GRP1 begin playerlGraphic lt Din 0 Din 1 Din 2 Dinl 3 Din 4 Din 5 Din 6 Din 7 R playerOGraphic lt playeroGraphic R_ballEnable lt ballEnable end ENAMO missileOEnable lt Din 1 ENAM1 missilelEnable lt Din 1 ENABL ballEnable lt Din 1 HMP0 playerOMotion lt Din 7 4 HMP1 playerlMotion lt Din 7 4 HMM0 missileOMotion lt Din 7 4 HMM1 missilelMotion lt Din 7 4 HMBL ballMotion lt Din 7 4 VDELPO playerovertDelay lt Din 0 VDELP1 playerlVertDelay lt Din 0 VDELBL ballVertDelay lt Din 0 RESMPO missileOLock lt Din 1 RESMP1 missilelLock lt Din 1 Strobed line that initiates an object move HMOVE begin playerOPos lt playerOPos 4 playeroMotion 3 playerOMotion 3 0 playerlPos lt playerlPos 4 playerlMotion 3 playerlMotion 3 0 missile0Pos lt missileOPos 4 miss
55. pl0Mask plOPixelOn Player 1 sprite pixel test wire pllPixelOn wire 7 0 pliMask pliMaskDel assign pllMaskDel playerlVertDelay R playerlGraphic playerlGraphic assign pllMask playerlReflect pliMaskDel pllMaskDel 0 pliMaskDel 1 pliMaskDel 2 pliMaskDel 3 pliMaskDel 4 pliMaskDel 5 pliMaskDel 6 pl1MaskDel 7 objPixelOn pixelNum playerlPos playerlSize 2 0 pliMask pllPixelOn Missile 0 pixel test wire misOPixelOn misOPixelOut wire 7 0 misOActualPos reg 7 0 misOMask always e playerosize begin case playerosize 4 3 2 d0 misOMask lt 8 h01 2 dl misOMask lt 8 h03 2 d2 misOMask lt 8 h0F TIA v 3 7 2 d3 misOMask lt 8 hFF endcase end assign misOActualPos missileOLock playerOPos missile0Pos objPixelOn pixelNum misOActualPos player0Size 2 0 misOMask misOPixelOut assign misOPixelOn misOPixelOut amp amp missileOEnable Missile 1 pixel test wire mislPixelOn mislPixelOut wire 7 0 mislActualPos reg 7 0 mislMask always playerlSize begin case playerlSize 4 3 2 d0 mislMask 8 h01 2 dl mislMask lt 8 h03 2 d2 mislMask lt 8 h0F 2 d3 mislMask 8 hFF endcase end assign mislActualPos missilelLock playerlPos missilelPos objPixelOn pixelNum mislActualPos playerlSize 2 0 mislMask mislPixelOut assign mislPixelOn mislPixelOut amp amp missilelEnable Ball pixe
56. r reg 7 0 Dout RAM allocation reg 7 0 RAM 127 0 I O registers reg 7 0 DRA DRB Data registers reg 7 0 DDRA DDRB Data direction registers wire PA7 reg R_PA7 assign PA7 PAin 7 amp DDRA 7 DRA 7 amp DDRA 7 assign PAout assign PBout DRA amp DDRA DRB amp DDRB Il Il Timer registers reg 8 0 Timer reg 9 0 Prescaler reg 1 0 Timer Mode reg Timer Int Flag PA7 Int Flag Timer Int Enable PA7 Int Enable PA7 Int Mode Timer prescaler constants wire 9 0 PRESCALER VALS 3 0 assign PRESCALER VALS 0 10 d0 assign PRESCALER VALS 1 10 d7 assign PRESCALER VALS 2 10 d63 assign PRESCALER VALS 3 10 d1023 Il Interrupt assign IRQ n Timer Int Flag amp Timer Int Enable PA7 Int Flag amp PA7 Int Enable Operation decoding wire 6 0 op reg 6 0 R op assign op RS n R W n A 4 0 Registered data in reg 7 0 R Din RIOT v 2 3 integer cnt Software operations always posedge CLK begin Reset operation if RES_n begin end DRA lt 8 b0 DDRA lt 8 b0 DRB lt 8 b0 DDRB lt 8 b0 Timer Int Flag lt 1 b0 PA7 Int Flag 1 b0 PA7 Int Enable lt 1 b0 PA7 Int Mode 1 b0 Fill RAM with Os for ont 0 cnt 128 cont cont 1 RAM cnt lt 8 b0 R PA7 1 b0 R op lt NOP R Din 8 b0 If the chip is ena
57. roGraphic playeriGraphic reg 7 0 R playeroGraphic R playeriGraphic reg pfReflect playerOReflect playerlReflect reg prioCtrl reg pfColorCtrl reg 14 0 collisionLatch reg missileOLock missilelLock reg playerOVertDelay playerlVertDelay ballVertDelay Pixel number calculation wire 7 0 pixelNum assign pixelNum hCount gt 68 hCount 8 d68 8 d227 Pixel tests For each pixel and screen object a test is done based on the screen objects register to determine if the screen object should show on that pixel The results of all the tests are fed into logic to pick which displayed object has priority and color the pixel the color of that object Playfield pixel test wire 5 0 pfPixelNum wire pfPixelOn pfLeftPixelVal pfRightPixelVal assign pfPixelNum pixelNum 7 2 assign pfLeftPixelVal pfGraphic pfPixelNum assign pfRightPixelVal pfReflect 1 b0 pfGraphic pfPixelNum 6 d20 pfGraphic 6 d39 pfPixelNum assign pfPixelOn pfPixelNum lt 6 d20 pfLeftPixelVal pfRightPixelVal Player 0 sprite pixel test wire plOPixelOn wire 7 0 plOMask ploMaskDel assign plOMaskDel player0OVertDelay R playeroGraphic playeroGraphic assign ploMask playerOReflect ploMaskDel ploMaskDel 0 plOMaskDel 1 plOMaskDel 2 ploMaskDel 3 plOMaskDel 4 ploMaskDel 5 ploMaskDel 6 ploMaskDel 7 objPixelOn pixelNum playerOPos playerosize 2 0
58. rs Logic L Priority Pixel Color LI Encoder Multiplexer NI E ER E jy Screen Object Color 9 9 Registers ca Pr sica Registers Logic 9 Data Out TIAColorTable v Synchronous color lookup table that maps the Atari indexed colors to RGB ClockDiv16 v Clock divider used to generate Atari clocks Divides the clock by 16 counts MOS6507 v Wrapper for a 6502 CPU module that emulates the MOS 6507 The following files are part of the code created for the project but their listing is not included in the project This is because these files were generated by the design software and do not provide any information as hardware descriptor language files AtariClockGenerator v Clock Generator using PLL Megafunction Cartridge2k v Cartridge ROM instantiation using Synchronous RAM Megafunction Cartridge4k v Cartridge ROM instantiation using Synchronous RAM Megafunction MySystem v Masters of Engineering Project ty 2007 Top level system for synthesis and programming on a DE2 board Atari on an FPGA Cornell Universi Daniel Beer MySystem v 47 module MySystem LI TET CLOCK 27 CLOCK 50 HH GS abt HI EU ETE TATA ATLL SRAM DO LB MM Gg Lll SRAM ADDR SRAM UB N SRAM LB N SRAM WE N SRAM CE N SRAM OE N HHITHEHHHETHHT VGA Cl VGA H VGA V VGA BI LK S S VGA LANK VGA SYNC VGA R VGA G VGA B TD KEY LEDG LEDR SW
59. se if wSyncReset amp amp hCount 8 d5 wSync 1 b1 end assign RDY wSync Latched input registers and update wire 1 0 latchedInputsValue reg inputLatchEnabled inputLatchReset reg 1 0 latchedInputs always e Ilatch inputLatchReset begin if inputLatchReset latchedInputs 2 b11 else latchedInputs latchedInputs amp Ilatch end assign latchedInputsValue inputLatchEnabled latchedInputs Ilatch Dumped input registers update reg inputDumpEnabled assign Idump inputDumpEnabled 4 b0000 4 bzzzz Software operations always posedge CLK2 begin Reset operation TIA v 5 7 LE end If the chip is enabled else if RES n begin inputLatchReset 1 b0 collisionLatchReset lt 1 b0 hCountReset 0 lt 1 b0 wSyncReset 1 b0 Dout lt 8 b00000000 execute an operati CS amp amp CS n begin Software reset signals inputLatchReset lt R_W n A 5 0 collisionLatchReset R W n A 5 0 hCountReset 0 lt RW n A 5 0 wSyncReset lt R W n A 5 0 case R W n A 5 0 Collision latch reads CXMOP Dout lt collisionLat CXMIP Dout lt collisionLat CXPOFB Dout CXP1FB Dout lt CXMOFB Dout lt CXMIFB Dout lt CXBLPF Dout lt CXPPMM Dout lt 1 0 reads WSYNC on VBLANK amp amp Din 6 1 CXCLR RSYNC amp
60. sedge VGA CTRL CLK begin if RES n begin Clear the screen addr reg lt Coord X 9 2 Coord Y 9 1 we 1 b0 data reg 16 h0000 curReadIndex 9 d0 end If we are syncing read pixels from the circular buffer and write them to the SRAM else if syncing begin addr reg lt pixelX curReadIndex pixelY curReadIndex we 1 b0 data reg lt 8 b0 pixelColor curReadIndex curReadIndex curReadIndex 9 d1 end MySystem v 5 5 When the VGA controller needs the SRAM else begin end end endmodule retreive pixels from SRAM addr reg lt Coord_X 9 2 Coord_Y 9 1 we lt l bl MySystemSim v 1 1 Atari on an FPGA Masters of Engineering Project Cornell University 2007 Daniel Beer MySystemSim v Top level system for simulation purposes This can be run in the Quartus II simulator by supplying it with the necessary clocks and inputs module MySystemSim CLOCK 50 50 Mhz clock input CLOCK 27 27 Mhz clock input RES n Active low reset input ATARI CLOCKBUS16 Atari 1 19 Mhz clock input ATARI CLOCKPIXEL16 Atari 3 58 Mhz clock input ATARI ROM CS ROM chip select output ATARI ROM Addr ROM address output ATARI ROM Dout ROM data input input CLOCK 50 CLOCK 27 RES n input ATARI CLOCKBUS16 ATARI CLOCKPIXEL16 output ATARI ROM CS output 11 0 ATARI ROM Addr output 7 0 ATARI ROM Dout wir
61. tColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor outColor SECAM Colors 9 d256 9 d257 9 d258 9 d259 9 d260 914261 9 d262 outColor outColor outColor outColor outColor outColor outColor 24 hBOECEC 24 h70005C 24 h842074 24 h943C88 24 hA8589C 24 hB470B0 24 hC484C0 24 hDO9CDO 24 hEOBOEO 24 h003C70 24 h1C5888 24 h3874A0 24 h508CB4 24 h68A4C8 24 h7CB8DC 24 h90CCEC 24 hA4EOFC 24 h580070 24 h6C2088 24 h803CA0 24 h9458B4 24 hA470C8 24 hB484DC 24 hCA9CEC 24 hDABOFC 24 h002070 24 h1C3C88 24 h3858A0 24 h5074B4 24 h6888C8 24 h7CAODC 24 h90B4EC 24 hA4C8FC 24 h3C0080 24 h542094 24 h6C3CA8 24 h8058BC 24 h9470CC 24 hA884DC 24 hB89CEC 24 hC8BOFC 24 h000088 24 h20209C 24 h3C3CBO0 24 h5858C0 24 h7070D0 24 h8484E0 24 h9C9CEC 24 hBOBOFC 24 h000000 24 h282828 24 h505050 24 h747474 24 h949494 24 hB4B4B4 24 hDODODO 24 hECECEC 24 h000000 24 h282828 24 h505050 2
62. tem which was tested again The original Atari software Combat was run on the system and performed well despite a few execution flaws Report Approved by Project Advisor Date Executive Summary The Atari 2600 is a computer system from the early 1980s One of the first gaming consoles it provides an interesting look at early hardware architecture and programming for a system with limited resources However few working units of the original hardware are available today preventing easy access to the system Furthermore any schematics and design details for the system use outdated design methodologies and refer to obsolete hardware making it hard to reconstruct a working system using them This project attempts to redesign an Atari 2600 using functional descriptions of the parts coupled with original Atari schematics of the system Software and hardware solutions are considered for the actual realization of the system but a hardware design was chosen for this project The design is implemented using two industry standard hardware programming languages tailored to run on prototyping hardware and use standard VGA displays In redesigning the system the parts are made so that they are run synchronized to a common clock and are able to be easily reused in other projects Testing is done on the module level and system level to verify correct behavior of the redesigned parts The final design is programmed onto a development board which has
63. to truly replicate the original design of the system but a number of projects have implemented a system that functions like the original Atari usually following the basic structure Technologies Used HDLs and FPGAs Hardware description languages HDLs allow hardware designers to implement digital circuit designs using a high level structured programming language Unlike most software programming languages which only specify functionality HDLs also allow the programmer to describe timing of the design This frees the designer to focus on creating the high level system while the underlying hardware can be synthesized automatically The two languages used in this project Verilog and VHDL are very similar languages with Verilog being slightly more abstract and VHDL giving a little more control over the actual hardware that is instantiated Most HDLs have a method for creating wires and registers Logic primitives such as gates and buffers are connected together using these and organized into larger functional blocks Libraries of commonly used circuits are often available such as Altera s Megafunction library which has wizard programs to help build the part needed Field programmable gate arrays FPGAs constitute the next stage of the design process An FPGA is a piece of hardware that contains many on the fly reconfigurable logic cells with flexible connections between them An HDL design is synthesized down to a configuration of logic ce
64. tware simulator can be made to imitate all parts of the original computer system including the CPU memory and I O To properly emulate a computer system requires much overhead including memory overhead and extra processing to interpret the instructions from the original system to ones that can be executed on the host system For this reason emulation can only be done on a host that has significantly more processing power than the original system However emulation allows easy access to unavailable computer architectures and allows new features to be built in such as debuggers memory dumpers and graphical enhancements A number of software emulators exist for the Atari 2600 the most well known of which is the Stella emulator While many of these emulators provide exact execution of Atari code they do require a personal computer to host them Hardware Using hardware to implement an existing computer design is another option This allows a solution that can run without a host computer and allows for further optimization of power space and speed Recreation of the actual Atari hardware is impossible today due to the financial restrictions on small amounts of hardware However FPGAs allow custom hardware to be cheaply synthesized and are used widely for prototyping hardware before it is manufactured Two approaches can be taken to create an Atari on an FPGA accurate recreation of the hardware or redesign of the system No projects attempt

Download Pdf Manuals

Related Search

Related Contents

Bedienungsanleitung HDTV Satelliten  Catalogo Jouef 2010.indb  Bimar VB30  User`s Manual  Cisco Aironet 1600i  Versión 6.10 Guía de usuario del cliente Agosto de  Potager urbain 100x40cmxh.80cm sur pied en acier    GNU Mailman - List Administration Manual    

Copyright © All rights reserved. Failed to retrieve file