The L6230 DMOS driver for three
Contents
1. Table 3 Document revision history Date Revision Changes 29 Jan 2013 1 Initial release Doc ID 024199 Rev 1 AN4243 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCL2. SENSE DIAG EN amp OUT IN 2 EN4 IN EN SENSE IN3 Q VS EN3 Q 5V OCD3 l amp OUT o 10V VOLTAGE REGULATOR SENSE CPOUT Q b cps CP COMPARATOR AM16563v1 Doc ID 024199 Rev 1 3 29 Designing an application with the L6230 AN4243 2 2 1 2 2 4 29 Designing an application with the L6230 Current ratings With MOSFET DMOS devices unlike bipolar transistors the current under short circuit conditions is at first approximation limited by the Rps on of the DMOS themselves and could reach very high values The L6230 OUT pins and the two Vga and Vsg pins are rated for a maximum of 1 4 A r m s and 2 8 A peak typical values These values are meant to avoid damaging metal structures including the metallization on the die and bond wires In practical applications maximum allowable current is less than these limits actually the constraint is the power dissipation The device integrates overcurrent detection OCD that provides protection against short circuits between the outputs and between an output and ground see Section 2 10 Voltage ratings and operating range The L6230 requires a single supply voltage Vs for the motor supply Internal voltage regulators provide the 5 V and 10 V required for the internal circuitry The operating range for Vg is from 8 to 52 V To prevent from working into undesirable low voltage supply an undervoltage lockout UVLO circuit shuts down the device when
3. E ra ICE JN N YN CN 3 E 4 f Lt p c cccz4 2 2 2 OY 0 x me gt o Le E o 1 o Z E E 5 E bile dae meade wea sees gt d CY Y 5 7 S Pi QA gt Wa i o E a 8 0 o i p Eee esee Ws Em Ses gt Y Y O1 0 8 o nos LEN PRIN e y HANS nee E E D M NK Pap ES nA 5 e pm sue m E 3 Ico oe ooo lolo lees Ss o S Loeb eee Y Y 5 Li E o A ee ee Oe ee Gee IK L 2 2 4 c YY Og EZ Xx ir O gt x x gg E EE ap Me E E PEE E li gee E Joo ie SE ed VaR a aes Ee ER gt O c AMN NA o Sa 5 D ir Designing an application with the L6230 AM16580v1 Doc ID 024199 Rev 1 20 29 AN4243 Application information 3 Application information Here below some general suggestions for applications based on the L6230 three phase BLDC motor driver A high quality ceramic capacitor C2 in the range of 100 nF to 200 nF should be placed between the power pins Vsa and Vsg and ground near the L6230 to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching The capacitor Ceyn and resistor Rey connected between the DIAG EN input and ground set the delay time and disable time when an overcurrent is detected see Section 2 10 The current sensing inputs SENSEy should be connected to the sensing resistors Rsense with a trace length as short as possible in
4. wa AN4243 YZ Application note The L6230 DMOS driver for three phase brushless DC motor By Cristiana Scaramel Introduction Modern motion control applications need more flexibility that can be only addressed with specialized ICs products The L6230 is a DMOS fully integrated three phase BLDC motor driver optimized for field oriented control FOC application thanks to the independent current senses The device integrates six DMOS power transistors with CMOS and bipolar circuits on the same chip including overcurrent protection for safe operation and flexibility An uncommitted comparator with open drain output for optional function is available January 2013 Doc ID 024199 Rev 1 1 29 www st com Contents AN4243 Contents 1 L6230 block diagram 0 06 eeu rr RR nnnm a R8 e mm hn 8 nne 3 2 Designing an application with the L6230 4 2 1 Current ratings PCT 4 2 2 Voltage ratings and operating range ssaa sasaaa eaaa 4 2 3 Choosing the bulk capacitor naana aaea 6 2 4 Layout considerations s aaua m b RR RR RE Rh OR oe Ri 8 25 Sensing resistor uda dneP tA PR OECD Add dub Banob Aricia dod 9 2 6 Charge pump external components 0000 cee eee eee 10 2 7 Sharing the charge pump circuitry llle 12 2 8 How to generate a reference voltage for the current control 12 2 9 Input logic pins 20 0 RR RII 14 2 10 Overcurrent protection 22s scee
5. connected to the internal comparator that can be used to control the peak value of the motor current through an external control loop A fixed reference voltage can be easily obtained with a resistive divider from an available pull up voltage rail maybe the one supplying the microcontroller or the rest of the application and GND A very simple way to obtain a variable voltage without using a DAC is to low pass filter a PWM output of a uC Figure 9 Doc ID 024199 Rev 1 ky AN4243 Designing an application with the L6230 Figure 9 Obtaining a reference voltage through a PWM output of microcontroller PWM Output of a uC Rop JUL CP Pop2 Cp GND AM16571v1 Assuming that this output swings from 0 to 5V the resulting average voltage is Equation 10 BELL i Rcp1 Rcp2 where DuC is the duty cycle of the PWM output of the microcontroller Assuming that the microcontroller output impedance is lower than 1 KQ with Rep 5 6 KQ Repo 1 5 k Ccp 100 nF and a PWM switching from 0 to 5 V at 100 kHz the low pass filter time constant is about 0 12 ms and the remaining ripple on the Vcp voltage is about 20 mV Higher values for Rcp4 Rope and Ccp reduce the ripple but the reference voltage takes more time to vary after changing the duty cycle of the microcontroller PWM Besides too high values of Rep also increase the impedance of the CP net at low frequencies causing a poor noise immunity As sen
6. A c lt 3 ni adt toa ida 4 ld j LAJ VTHOFR 4 IT Venom 4 tocp orF gt I DIAG EN EN RISE M Soons Chi X 1 36 V 6 sey M4 0gs Chi X 1 36 V 6 se aw 2 00V Ch4 5 004 11 0 2 00V Ch4 5 00A 11 0 AM16576v1 The maximum value reached by the current depends on its slew rate thus on the state of short circuit the supply voltage and on the total intervention delay tpg Ay It can be noticed that after the first current peak the maximum value reached by the output current becomes lower because the capacitor on DIAG EN pins is discharged starting from a lower voltage resulting in a shorter tpg Ay The following approximate relations estimate the disable time and the first OCD intervention delay after the short circuit worst case The time the device remains disabled is Equation 11 toisaBLe locp orr ten RISE D ON EN where Equation 12 t R Ca Vpp VENLOW EN RISE 7 NEN EN N Vpb VIHON The total intervention time is Equation 13 beLay tocpcon ten FALL D OFF EN where Equation 14 Vpp tencFALL Ropor Cen Inyo TH OFF tocD OFF tocD ON lD ON EN lD OFF EN and Roppr are device intrinsic parameters Vpp is the pull up voltage applied to Ren Doc ID 024199 Rev 1 17 29 Designing an application with the L6230 AN4243 2 11 18 29 The external RC network Cen in particular must be chosen obtaini
7. gt R4 Only when the OUT is in high impedance the CPOUT performs a commutation each time a BEMF zero crossing is detected In this configuration one sense resistor is needed the three OUT pins are connected together to RsENsE Figure 21 Six step with zero crossing detection typical application Fen 0 o DIAG ENQ ENABLE we E s EEG J T POWE GROUN TA A IN1 Oo Q EN1Q ENI CBoor IN2 IN2 SIGNAL VBOOT GROUND Rg EN20 EN Q D Hm BS ES SENSE R A R E l Zero Crossing R 3RJ l CPOUT signal OUT THREE PHASE MOTOR Q OUR le oJ O OUR 9 j 9 3 AM16583v1 Doc ID 024199 Rev 1 ky AN4243 Demonstration boards 4 4 1 Demonstration boards EVAL6230QR demonstration board A demonstration board has been produced to help the evaluation of the device in VFQFPN32L 5 x 5 mm package It implements a typical application which can be used as a reference design to drive three phase brushless DC motors with currents up to 1 A DC Thanks to the small footprint of the L6230Q the PCB is very compact 32 x 31 mm For more details on the EVAL6230QR refer to the application note AN3244 Figure 22 Demonstration board S I amp PC DIV IB EVAL62300R drio SHOX 2 o 3 P L4 m INVI AM16584v1 Doc ID 024199 Rev 1 25 29 Demonstration boards AN4243 4 2 26 29 STEVAL IFN003V1 PMSM FOC motor driver based on
8. supply voltage falls below 6 V to resume normal operating conditions Vs must then exceed 6 8 V The hysteresis is provided to avoid false intervention of the UVLO function during fast Vs ringings It should be noted however that DMOS s Rps o is a function of the Vs supply voltage Actually when Vs is less than 10 V Rps on is adversely affected and this is particularly true for the high side DMOS that are driven from VBOOT supply This supply is obtained through a charge pump from the internal 10 V supply which tends to reduce its output voltage when Vs goes below 10 V Figure 2 shows the supply voltage of the high side gate drivers VBOOT Vs versus the supply voltage Vs Figure 2 Supply voltage of high side gate drivers versus supply voltage Veoor Vs M AM16564v1 Doc ID 024199 Rev 1 ky AN4243 Designing an application with the L6230 Note that Vs must be connected to both Vga and Vsg since the bootstrap voltage at VBOOT pin is the same as the three half bridges The integrated DMOS have a rated drain source breakdown voltage of 60 V However Vs should be kept below 52 V since in normal working conditions the DMOS see a V voltage that exceeds the Vs supply In particular when a high side DMOS turns off due to a phase change OUT1 in Figure 3 if one of the other outputs OUT2 in Figure 3 is high the load current starts flowing in the low side freewheeling diode and the SENSE pin sees
9. the layout The sense resistors should be non inductive resistors to minimize the dl dt transients across the resistors To increase noise immunity unused logic pins are connected either to 5 V high logic level or GND low logic level The power ground and signal ground have to be kept separated on PCB In Table 2 recommended values are reported for external components Table 2 Component values for typical applications Component Value Description C4 100 uF Bulk capacitor Co 100 nF Supply voltage ceramic capacitor one for Vg pins 220 nF Bootstrap capacitor connected between Vgoor and Vs charge pump Cen 5 6 nF Capacitor connected to DIAG EN pin Cp 10 nF Fly capacitor connected to CP pin charge pump D4 1N4148 Charge pump diode Do 1N4148 Charge pump diode Ren 100 KQ Resistor connected to DIAG EN pin Doc ID 024199 Rev 1 21 29 Application information AN4243 3 1 22 29 Field oriented control driving method The field oriented control F O C method allows smooth and precise motor control of BLDC motors to be provided In this configuration see Figure 19 three sensing resistors are required one for each channel The sensing signals coming from the output power stage are conditioned by external operational amplifiers which provide the proper feedback signals to the analog to digital converter and the system controller According to the feedback signals the six input lines ar
10. 0 mA The reverse voltage is about 10 V in all conditions The 1N4148 diodes withstand about 200 mA DC 1 A peak and the maximum reverse voltage is 75 V so they should fit for the majority of applications ky Doc ID 024199 Rev 1 11 29 Designing an application with the L6230 AN4243 2 7 2 8 12 29 Sharing the charge pump circuitry If more than one device is used in the application it is possible to use the charge pump from one L6230 to supply the Vgoor pins of several ICs The unused CP pins on the slave devices are left unconnected as shown in Figure 8 A 100 nF capacitor Cyoot2 should be connected to the Vgoor pin of each device Supply voltage pins Vs of the devices sharing charge pump must be connected together The higher the number of devices sharing the same charge pump the lower the differential voltage available for gate drive Vgoor Vs causing a higher Rps on for the high side DMOS so higher dissipating power A better performance can also be obtained using a 33 nF capacitor for Cy and using Schottky diodes for example BAT47 are recommended Sharing the same charge pump circuitry for more than 3 or 4 devices is not recommended since it reduces the Vgoor voltage increasing the high side MOS on resistance and thus power dissipation Figure 8 Sharing the charge pump circuitry AM16570v1 How to generate a reference voltage for the current control The device has an analog input CP
11. 100 pF the capacitance role is much less than the ESR then supply voltage ripple can be estimated as Equation 4 lour ESR in slow decay Equation 5 lout ESR in fast decay For example if a maximum ripple of 500 mV is allowed and lour 1 A the capacitor ESR should be lower than Equation 6 ESR lt x 500mQ in slow decay Equation 7 ESR i E 250 500 mQ in fast decay Actually current sunk by Vsa and Vgp pins of the device is subject to higher peaks due to reverse recovery charge of internal freewheeling diodes The duration of these peaks is tough very short and can be filtered using a small value 100 200 nF good quality ceramic capacitor connected as close as possible to the Vsa Vsg and GND pins of the IC The bulk capacitor is chosen with maximum operating voltage 25 greater than the maximum supply voltage considering also power supply tolerances Doc ID 024199 Rev 1 7 29 Designing an application with the L6230 AN4243 2 4 8 29 For example with a 48 V nominal power supply with 5 tolerance maximum voltage is 50 4 V then operating voltage for the capacitor should be at least 63 V Layout considerations Working with devices that combine high power switches and control logic in the same IC special attention has to be paid to the PCB layout In extreme cases Power DMOS commutation can induce noises that could cause improper operation in the logic section of the device Noise can be radia
12. 43 Designing an application with the L6230 2 12 PCB the right package should be chosen considering the power dissipation Heat sinking can be achieved using copper on the PCB with proper area and thickness For instance using a VFQFPN32L 5 x 5 package the typical Retna S about 42 C W when mounted on a double layer FR4 PCB with a dissipating copper area of 0 5 cm on the top side plus 6 cm ground layer connected through 18 via holes 9 below the IC Otherwise using a Power SO package with copper slug soldered on a 1 5 mm copper thickness FR4 board with 6 cm dissipating footprint copper thickness of 35 um the Rinia is about 35 C W Using a multi layer board with vias to a ground plane the thermal impedance can be reduced down to 15 C W Brake In general motor braking can be achieved making a short circuit across the windings the BEMF forces a current proportional to the braking torque that flows in the opposite direction than in normal running mode For high BEMF and inertia moment the current may reach very high values a power resistor is often used to reduce the maximum braking current and dissipate the motor energy In the L6230 brake function can be achieved to quickly stop the motor while it is running providing a high logic level to the three IN pins all the high side DMOS switch on making a short circuit across the motor windings A power resistor is not used while the motor is braking both therma
13. 600 kHz see Figure 1 Doc ID 024199 Rev 1 ky AN4243 Designing an application with the L6230 Figure 7 Charge pump circuitry Vs 10 V Vpi V Vs 10 V Vp Gy Vaoor CP Vsa To High Side 5 10V Charge Pump vtt v f 600 kH amp o PNE E AE T T E esnsumuunnnunnnnnmunnnnnnnnnnnunununnnnnnnnnnnnnnnnnnnnnnna t AM16569v1 When the oscillator output is at ground Cy is charged by Vs through D2 When it rises to 10 V D2 is reverse biased and the charge flows from Ciy to Choot through D1 so the VggoT pin after some few cycles reaches the maximum voltage of Vs 10 V Vp Vpo which supplies the high side gate drivers With a differential voltage between Vs and Vgoor of about 9 V and both the bridges switching at 50 kHz the typical current drawn by the Vgoor pin is 1 85 mA Care must be taken to develop the PCB layout of Cry D1 D2 connections in order to minimize interferences with the rest of the circuit see also the Section 2 4 Recommended values for the charge pump circuitry are e D1 D2 1N4148 e Cry 10 nF 100V ceramic capacitor Cboot 220 nF 35V ceramic capacitor Due to the high charge pump frequency fast diodes are required Connecting the cold side of the bulk capacitor C2 to Vs instead of GND the average current in the external diodes during operation is less than 10 mA At IC power up the current in the external diodes during operation is less than 20
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15. a negative spike due to a non negligible parasitic inductance of the PCB path from the pin to GND This spike is followed by a stable negative voltage due to the drop on Rgenge The OUT pin sees a similar behavior but with a slightly larger voltage due to the forward recovery time of the integrated freewheeling diode and the forward voltage drop across it Typical duration of this spike is 30 ns At the same time the OUT2 pin in the example of Figure 3 sees a voltage above Vs due to voltage drop across the high side integrated freewheeling diode as the current reverses direction and flows into the bulk capacitor It turns out that the highest differential voltage is observed between two OUT pins when a phase change turns a high side off and this must always be kept below 60 V Figure3 Currents and voltages if a phase change turns a high side off during off time os Current starts flowing in the third dp PCB Parasitic half bridge Bulk Capacitor Equivalent i D 1 1 1 1 1 1 1 1 1 1 1 1 1 Y during off time a phase change can occur AM16565v1 Figure 4 shows the voltage waveforms at the OUT pins referring to a possible practical situation with a peak output current of 1 4 A Vs 52 V Rgense 0 33 Q Ty 25 C approximately and a good PCB layout Below ground spike amplitude is 2 65 V for one output the other OUT pin is at about 55 V In these conditions total differential vo
16. ccd vid ek e 3 e rr REX ak eds 15 2 311 Thermal management 200 eee ee 18 212 Brake cake oney tpe ranan Ge sies exeS dau aa aTe he oe Bie MEN 19 3 Application information eeeellleeeee 21 3 1 Field oriented control driving method 0000 e eee ee eee 22 3 2 Six step driving method with current control 00005 23 3 3 Six step driving method with BEMF zero crossing detection 24 4 Demonstration boards sees 25 4 1 EVAL6230QR demonstration board 000 eee ees 25 4 2 STEVAL IFNOOSV1 PMSM FOC motor driver based on the L6230 and STM32F103 52 i224 d uiedacterccr ieitt0sedgbb3 Sid bedboss 26 4 3 STEVAL IFNOO4V t BLDC six step motor driver based on the L6230 and SrMBS TU s622525 eoecen ren ens Suave soutesGoddeee douse s 27 5 REVISION history usas acie wo acaso eee nase endo ROIG e eee we 28 2 29 Doc ID 024199 Rev 1 ky AN4243 L6230 block diagram L6230 block diagram The L6230 see Figure 1 includes logic for CMOS TTL interface a charge pump that provides auxiliary voltage to drive the high side DMOS non dissipative overcurrent protection circuitry on the high side DMOS with a fixed trip point set at 2 8 A see Section 2 10 overtemperature protection undervoltage lockout for reliable startup Figure 1 L6230 block diagram VSA VBOOT Q e Vgoor CHARGE THERMAL Vere PUMP PROTECTION OUT4 OCD1 OCD3
17. e generated by the controller Note that some filtering and level shifting RC networks should be added between the sense resistor and the correspondent op amp input The uncommitted internal comparator with open drain output is available Figure 19 F O C typical application DIAG ENQ ENABLE Vs 8 52Vbc POWER GROUND Cy SIGNAL GROUND AM16581v1 Doc ID 024199 Rev 1 ky AN4243 Application information 3 2 Six step driving method with current control The input sequence is generated by the external controller and the L6230 comparator is used to obtain the information for the peak current control In this configuration only one sense resistor is needed the three OUT pins are connected together to Rgense see Figure 20 The non inverting input comparator CP monitors the voltage drop across the external sense resistor connected between the source of the three lower power MOS transistors and ground As the current in the motor increases the voltage across the Rsense increases proportionally When the voltage drop across the sense resistor becomes greater than the reference voltage applied to inverting input CP the comparator open drain output is switched on pulling down the CPOUT pin This signal could be managed by controller to generate the proper input sequence for six step driving method with current control and select what current decay method to implement When the sens
18. e sensing resistor to the negative terminal of the bulk capacitor power ground requires particular attention These tracks must be as short as possible in order to minimize parasitic inductances that can cause dangerous voltage spikes on SENSE and OUT pins see Section 2 2 For the same reason the capacitors on Vsa Vsg and GND pins should be very close to the GND and supply pins Refer to the Section 2 5 for information on selecting the sense resistors Traces connected to Vsa Vsp SENSEA SENSEB and the three OUT pins must be designed with adequate width since high currents are flowing through these traces and layer changes should be Doc ID 024199 Rev 1 ky AN4243 Designing an application with the L6230 2 5 avoided Should a layer change be necessary multiple and large via holes have to be used A wide GND copper area can be used to improve power dissipation for the device Figure 6 shows two typical situations that must be avoided An important consideration about the location of the bulk capacitor is the ability to absorb the inductive energy from the load without allowing the supply voltage to exceed the maximum rating The diode shown in Figure 6 prevents the recirculation current from reaching the capacitors and results in a high voltage on the IC pins that can damage the device Having a switch or a power connection that can disconnect the capacitors from the IC while there is still current in the motor also results i
19. e voltage decreases below the CP voltage the open drain is switched off and the voltage at CPOUT pin increases charging the capacitor C3 The reference voltage at pin CP is set according to the sense resistor value and the desired regulated current Equation 15 Vop Rsense X lranaET A very simple way to obtain a variable voltage is to low pass filter a PWM output of a controller refer to Section 2 8 Figure 20 Six step with current control typical application 0 DIAG ENO ENABLE POWE GROUND from controller Repout Current control signal THREE PHASE MOTOR AM16582v1 Doc ID 024199 Rev 1 23 29 Application information AN4243 3 3 24 29 Six step driving method with BEMF zero crossing detection To implement a sensorless motor control system the information on rotor position is achieved by BEMF zero crossing detection in this way no hall effect sensors or encoders are needed In six step driving mode one of the three phases is left in high impedance state Comparing the voltage of this phase with the motor neutral point voltage or star point we can detect the BEMF zero crossing This information about the commutation between two consecutive steps allows the rotor synchronization to be achieved In the example of Figure 21 the OUT1 phase voltage is monitored by the CP the center tap voltage is obtained as combination of three phase voltages and monitored by the CP pin R gt
20. l and overcurrent protections still work avoiding BEMF to cause a current exceeding the device s maximum ratings Using a RC network see Section 2 10 a disable time between each overcurrent event can be set reducing the maximum RMS value of the current Figure 17 shows what happens if the current exceeds the OCD threshold while the motor is braking as soon as the current in one of the three motor phases reaches the OCD threshold 2 8 A typ the open drain MOSFET internally connected to the DIAG EN pin discharges the external capacitor the DIAG EN pin voltage falls to GND and all the bridges of the device are disabled for a time that depends on the RC network values During this disable time the current forced by the BEMF decreases and so the braking torque when the current becomes zero because the motor inductances have been fully discharged if the BEMF is less than the supply voltage there is no braking effect since the freewheeling diodes cannot be turned on until the disable time expires and all the high side power DMOS turn on again Doc ID 024199 Rev 1 19 29 AN4243 Figure 17 Example of overcurrent during motor braking E 4 S Reo ete ee eee zz Nt CY YN CO o Lc a V E um i 2 zm E HE 28 KCcYYNN O19 uq eee ee eee L lt c p TH 10 T Nag etre
21. ltage reaches almost 60 V which is the absolute maximum rating for the DMOS Keeping differential voltage between two output pins within rated values is a must that can be accomplished with proper selection of bulk capacitor value and equivalent series resistance ESR according to the current peaks and adopting good layout practices to minimize PCB parasitic inductances Doc ID 024199 Rev 1 5 29 Designing an application with the L6230 AN4243 Figure 4 Voltage at the two outputs if a phase change turns a high side off Tek 1 00GS s 5 Acqs E Vertical Offset 50 000 V amp 2 3 6 29 Ch2 Offset C2 Max lvertical Offset 50 000 V Set to 0 V Chi i1 00V Wi 2 00 l d 1 00V Coupling DC C E Bandwidth 99 2 Position RoE Deskew Probe Full 7dlv 3 00 div MEITHEUTAS 0s Functions AM16566v1 Choosing the bulk capacitor Since the bulk capacitor placed between Vs and GND pins is charged and discharged during IC operation its AC current capability must be greater than the RMS value of the charge discharge current This current flows from the capacitor to the IC during the on time ton and from the IC implementing a fast decay current recirculation technique or from the power supply implementing a slow decay current recirculation technique to the capacitor during the off time torr The RMS value of the current flowing into the bulk capacitor depends on peak ou
22. monstration board is based on the DMOS fully integrated three phase motor driver L6230 and STMicroelectronics STM8S105 microcontroller implementing 6 step scalar control of a BLDC motor The board is designed as an evaluation environment for motor control applications in the range of 8 V 48 V of DC bus voltage and up to 35 W exploiting the embedded features of the STM8S105 The L6230 DMOS driver features 2 8 A output peak current non dissipative overcurrent detection protection cross conduction protection internal comparator used for cycle by cycle current limitation regulation thermal shutdown and undervoltage lockout The STEVAL IFN004V1 is provided with a specific BEMF detection network with dynamic method selection Offering dedicated hardware evaluation features the STEVAL IFNO04V1 board is designed to help developers evaluate the device and develop their own applications The STEVAL IFNOO4V1 can be used together with the STM8Sxxx three phase BLDC motor control software library and constitutes a cost effective complete motor control evaluation and development platform For more details on the STEVAL IFNOO4V1 refer to the user manual UM1477 Figure 24 STEVAL IFN004V1 board kPC DIV IB EVAL6230QR CP4 SNS a i c r L 9 ler Lc r Ciy 3asezoo ITE LLNO SHON AM16586v1 Doc ID 024199 Rev 1 27 29 Revision history AN4243 5 28 29 Revision history
23. n a high voltage transient since there is no capacitance to absorb the recirculation current Figure 6 Layout suggestions DO NOT put a diode here Recirculating current cannot flow into the eat bulk capacitor and causes a high voltage SENSE spike that can damage the IC SENSE L62 30 SENSE3 GND GND GND GND DO NOT connect the logic GND here Voltage drop due to current in sense path can disturb logic GND AM16568v1 Sensing resistor Each motor winding current flows through the sensing resistors causing a voltage drop that is used to control the peak value of the load current Two issues must be taken into account when choosing the Rsense value The sensing resistor dissipates energy and provides dangerous negative voltages on the SENSE pins during the current recirculation For this reason the resistance of this component should be kept low The voltage drop across Rsense can be compared to a reference voltage The lower is the Rsense Value the higher is the peak current error due to noise input and to the input offset of the current sense comparator too small values of Rgense must be avoided A good compromise is to calculate the sensing resistor value so that the voltage drop corresponding to the peak current in the load Ipeak is about 0 5 V Equation 8 0 5V HsENsE peak Doc ID 024199 Rev 1 9 29 Designing an application with the L6230 AN4243 2 6 10 29 It should be clear that se
24. ng a reasonable fast OCD intervention short tpg Ay and a safe disable time long tpisagLe Figure 15 shows both tp sAg g and tpg Ay as a function of Cex at least 100ys for tpisAgi E are recommended keeping the delay time about 1 to 2us at the same time Figure 15 Typical disable time vs Cgy on varying Ren Ren 220 Qk Ren 100 Qk 140 E Ren 47 Qk Ren 33 Qk Ren 10 Qk m 100 Ww a 10 1 a 10 100 Cen NF AM16577v1 Figure 16 Typical delay time vs Cen 10 toevay HS otg 10 100 Cen nF AM16578v1 The internal open drain can also be turned on if the device experiences an overtemperature OVT condition The OVT causes the device to shut down when the die temperature exceeds the OVT threshold Ty gt 165 C typ Since the OVT is also connected directly to the gate drive circuit see Figure 1 all the power DMOS shut down even if DIAG EN pin voltage is still over Vigor When the junction temperature falls below the OVT turn off threshold 150 C typ the open drain turns off Cen is recharged up to Vryon and then the power DMOS are turned back on Thermal management In most applications the power dissipation in the IC is the main factor that sets the maximum current that can be delivered by the device in a safe operating condition Therefore it has to be taken into account very carefully Besides the available space on the Doc ID 024199 Rev 1 ky AN42
25. nsing resistor must absolutely be non inductive type in order to avoid dangerous negative spikes on SENSE pins Wire wounded resistors cannot be used here while metallic film resistors are recommended for their high peak current capability and low inductance For the same reason the connections between the SENSE pins C1 C2 Vsa Vsg and GND pins see Figure 6 must be taken as short as possible see Section 2 4 The average power dissipated by the sensing resistor is e Fast decay recirculation Pp js Rsense e Slow decay recirculation Pus lms Regense D Where D is the duty cycle of the PWM current control I m is the RMS value of the load current Nevertheless the sensing resistor power rating should be chosen taking into account the peak value of the dissipated power Equation 9 2 Paz l pk Rgense Where lpk is the peak value of the load current Multiple resistors in parallel help to obtain the required power rating with standard resistors and reduce the inductance The Rsense tolerance reflects on the peak current error 1 resistors should be preferred Table 1 shows Rgense recommended values for a 0 5 V drops and power ratings for typical RMS and peak current values Table 1 Rsense recommended values JA Poot ReneeboserraoUi Memes 0 25 2 0 125 0 5 1 0 25 Charge pump external components An internal oscillator with its output at CP pin switches from GND to 10 V with a typical frequency of
26. occurrence The values of Rey and Cen are selected to ensure proper operation of the device under a short circuit condition When the current flowing through the high side DMOS reaches the OCD threshold 2 8 A typ after an internal propagation delay tocp ow the open drain starts discharging Cen When the DIAG EN pin voltage falls below the turn off threshold VTH OFF all the Power DMOS turn off after the internal propagation delay tp oerjgx The current begins decaying as it circulates through the freewheeling diodes Since the DMOS are off there is no current flowing through them and no current to sense so the OCD circuit after a short delay tocp orr Switches the internal open drain device off and Rey can charge Ceyn When the voltage at DIAG EN pin reaches the turn on threshold Vtyon after the tp on en delay the DMOS turn on and the current restarts Even if the maximum output current can be very high the external RC network provides a disable time tpjsAp p to ensure a safe RMS value see Figure 14 Doc ID 024199 Rev 1 ky AN4243 Designing an application with the L6230 X Figure 14 Overcurrent operation timing ft D OFF EN I I Tek KE Single Seq 2 00GS s Tek E Single Seq 25 0MS s t F 1 E F e env y toisaBLe i i lt H t I 1 tocp oN i mi Output Current TA URS ir Output Current j i i Isover i mtu i 1 l i i or tEN FALL f B
27. put may be driven in one of two configurations as shown in Figure 11 or Figure 12 If driven by an open drain collector structure a pull up resistor Rey and a capacitor Cey are connected as shown in Figure 11 If the driver is a standard push pull structure the resistor Rey and the capacitor Cey are connected as shown in Figure 12 The resistor Rey should be chosen in the range from 2 2 kQ to 180 kQ Recommended values for Ren and Cen are respectively 10 kQ and 5 6 nF More information on selecting the values is found in Section 2 10 Doc ID 024199 Rev 1 ky AN4243 Designing an application with the L6230 Figure 11 Pin DIAG EN open collector driving OPEN COLLECTOR OUTPUT AM16573v1 Figure 12 Pin DIAG EN push pull driving PUSH PULL Sheet OUTPUT L ESD PROTECTION AM16574v1 2 10 Overcurrent protection To implement an overcurrent protection a dedicated overcurrent detection OCD circuitry see Figure 13 for a simplified schematic senses the current in each high side Power DMOS are actually made of thousands of individual identical cells each carrying a fraction of the total current flowing The current sensing element connected in parallel to the power DMOS is made of only a few cells having a 1 N ratio compared to the power DMOS The total drain current is split between the output and the sense element according to the cell ratio Sensed current is then a small fraction of the output current and doe
28. rance Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com ky Doc ID 024199 Rev 1 29 29
29. s not contribute significantly to power dissipation Doc ID 024199 Rev 1 15 29 Designing an application with the L6230 AN4243 16 29 Figure 13 L6230 overcurrent detection simplified circuitry OUT VS OUT OUT VSg HIGH SIDE DMOS POWER SENSE cell POWER SENSE 1 cell POWER SENSE POWER DMOS 1 cell 1 ncells POWER DMOS n cells uC or LOGIC TO GATE OCD COMPARATOR INTERNAL i llo Ig n OPEN DRAIN Posion BER 400 TYP OVER TEMPERATURE AM16575v1 This sensed current is compared to an internally generated reference to detect an overcurrent condition An internal open drain MOSFET turns on when the sum of the currents in the bridge 1 the bridge 2 or the bridge 3 reaches the threshold 2 8 A typical value the open drain is available at the DIAG EN pin for diagnostic purposes and to ensure an overcurrent protection connecting an RC network see Figure 13 Figure 14 shows the device operating in overcurrent condition When an overcurrent is detected the internal open drain MOSFET pulls the DIAG EN pin to GND switching off all 6 power DMOS of the device and allowing the current to decay Under a persistent overcurrent condition like a short to ground or a short between two output pins the external RC network on the EN pin see Figure 13 reduces the RMS value of the output current by imposing a fixed disable time after each overcurrent
30. sing resistor value is typically kept small a small noise on CP input pins might cause a considerable error in the output current It is then recommended to decouple this pin with a ceramic capacitor of some tens of nF placed very close to CP and GND pins Note that CP pin connected to GND cannot guarantee zero current due to voltage offset in the internal comparator The best way to cut down the IC power consumption and to clear the load current is to pull down the DIAG EN pin With very small reference voltage PWM current control method can lose control of the current due to the minimum allowed duration of on time ky Doc ID 024199 Rev 1 13 29 Designing an application with the L6230 AN4243 2 9 14 29 Input logic pins INx and ENx pins are TTL CMOS and microcontroller compatible logic input pins The internal structure is shown in Figure 10 Typical values for turn on and turn off thresholds are VTH ON 1 8 V and VTH OFF 1 3V Pins are ESD protected and can be directly connected to the logic outputs of a microcontroller a series resistor is generally not recommended as it could help inducted noise to disturb the inputs Figure 10 Logic input internal structure AM16572v1 DIAG EN pin has the same input structure with the exception that the drain of the overcurrent and MOSFET thermal protection is also connected to this pin Due to this connection this pin has to be driven very carefully The EN in
31. ted by high dV dt nodes or high dl dt paths or conducted through GND or supply connections Logic connections especially high impedance nodes actually all logic input see further must be kept far from switching nodes and paths With the L6230 in particular external components for the charge pump circuitry should be connected together through short paths since these components are subject to voltage and current switching at relatively high frequency 600 kHz The primary means to minimize conducted noise is to have a good GND layout see Figure 5 Figure 5 Typical application and layout suggestions Microcontroller lt a co S S AM16567v1 High current GND tracks i e the tracks connected to the sensing resistor must be connected directly to the negative terminal of the bulk capacitor A good quality high frequency bypass capacitor is also required typically from 100 nF to 200 nF ceramic would suffice since electrolytic capacitors show a poor high frequency performance Both bulk electrolytic and high frequency bypass capacitors have to be connected with short tracks to Vsa Vsg and GND On the L6230 GND pins are the logic ground since only the quiescent current flows through them Logic ground and power ground should be connected together in a single point the bulk capacitor to avoid the power ground noise from affecting the logic ground Layouting the path from the SENSE pins through th
32. the L6230 and STM32F103 The STEVAL IFNO03V1 demonstration board is based on the DMOS fully integrated three phase motor driver L6230 and STMicroelectronics ARM Cortex M3 core based STM32F103 microcontroller implementing field oriented control of a PMSM motor The board is designed as an evaluation environment for motor control applications in the range of 8 V 48 V of DC bus voltage and up to 45 W exploiting the computational power of the STM32F103 The L6230 DMOS driver features 2 8 A output peak current non dissipative overcurrent detection protection cross conduction protection uncommitted comparator thermal shutdown and undervoltage lockout The STEVAL IFNOOSV1 is provided with a specific USB interface for the real time data exchange Offering dedicated hardware evaluation features the STEVAL IFNOOSV1 board is designed to allow developers to evaluate the device and develop their own applications The STEVAL IFNOO3V1 can be used together with the STM32 PMSM single dual FOC SDK v3 0 and constitutes a complete motor control evaluation and development platform For more details on the STEVAL IFNOO3V1 refer to the user manual UM1478 Figure 23 STEVAL IFN003V1 board STEVAL IFNOOSV1 z daS DEMO BOARD FOR EVALUATION PURPOSE ONLY AM16585v1 Doc ID 024199 Rev 1 ky AN4243 Demonstration boards 4 3 STEVAL IFN004V1 BLDC six step motor driver based on the L6230 and STM8S105 The STEVAL IFNOOAV1 de
33. tput current output current ripple switching frequency duty cycle It also depends on power supply characteristics A power supply with poor high frequency performances or long inductive connections to the IC causes the bulk capacitor to be recharged slowly the higher the current control switching frequency the higher the current ripple in the capacitor RMS current in the capacitor however does not exceed the RMS output current Bulk capacitor value C and the ESR determine the amount of voltage ripple on the capacitor itself and on the IC In slow decay neglecting the deadtime and output current ripple and assuming that during the on time the capacitor is not recharged by the power supply the voltage at the end of the on time is Doc ID 024199 Rev 1 ky AN4243 Designing an application with the L6230 Equation 1 t Vs lout ESR 20 so the supply voltage ripple is Equation 2 t Vs lout esr a where lour is the output current With fast decay instead recirculating current recharges the capacitor causing the supply voltage to exceed the nominal voltage This can be very dangerous if the nominal supply voltage is close to the maximum recommended supply voltage 52 V In fast decay the supply voltage ripple is about Equation 3 ton torr bun 2 ESR id always assuming that the power supply does not recharge the capacitor and neglecting the output current ripple and the deadtime Usually if C gt
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