32-bit general purpose microcontroller core User manual
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1. d C 2 Mosel 7 o EESSSDEES SS ERR RE E D AIoRdEn 2 AIoRdEn 1 L J J AIoRdEn 0 J Comment Comments for IO read diagrams see picture above Comment Explanation Reading of 1 byte Address 1 0 0x00 AloRdEn 0 is active Data is read from AloMiso 7 0 Reading of 1 byte Address 1 0 0x01 AloRdEn 0 is active Data is read from AloMiso 7 0 Reading of 2 bytes Address 1 0 0x00 AloRdEn 1 0 is active Data is read from AloMiso 15 0 Reading of 2 bytes Address 1 0 0x01 AloRdEn 1 0 is active Data is read from AloMiso 15 0 Reading of 4 bytes Address 1 0 0x00 AloRdEn 2 0 is active Data is read from AloMiso 31 0 35 37 User manual 36 37 oa y User manual Disclaimer The information contained in this document is for general information purposes only The information is provided by birusinka com and while we try to keep the information up to date and correct we make no representations or warranties of any kind express or implied about the completeness accuracy reliability suitability or availability with respect to the document or the information products services or related content for any purpose Any reliance you place on such information is therefore strictly at your own risk In no event will we be liable for any loss or damage including w2. Q C 3j AMemMiso 47 40 l Lr AMemMiso 39 32 Lr AMemMiso 31 24 _ __ AMemMiso 23 16 Am i Hf AMemMiso 15 8 lt amp _ _ _ CL Cr AMemMiso 7 0 M AMemRdEn 7 AMemRdEn 6 AMemRdEn 5 AMemRdEn 4 AMemRdEn 3 AMemRdEn 2 AMemRdEn 1 AMemRdEn 0 E Comment A B E B Comments for memory read diagrams see picture above Comment Explanation Reading of 1 byte Address 2 0 0x00 Only AMemRdEn 0 is active Data is read from AMemMiso 7 0 Reading of 1 byte Address 2 0 0x03 Only AMemRdEn 3 is active Data is read from AMemMiso 31 24 Reading of 1 byte Address 2 0 0x06 Only AMemRdEn 6 is active Data is read from AMemMiso 55 48 Reading of 2 bytes Address 2 0 0x02 AMemRdEn 3 2 are active Data is read from AMemMiso 31 16 Reading of 4 bytes Address 2 0 0x04 AMemRdEn 7 4 are active Data is read from AMemMiso 63 32 Memory interface is optimized for working with synchronous memory blocks Multi byte variables must be properly aligned See alignment chapter for details 33 37 Y User manual 7 4 IO Interface While memory operations require 2 and 4 byte data to be aligned for IO operations this is not necessary Hardware periphery units are responsible for interpreting addre
3. bwx dwx ewX tCWX ewx dwx Many commands have several variations All of them will be listed Some commands change flags others don t If Flag register is changed by the instruction it will be indicated Data transfer instructions Command Variations Result Example mov dr sr dr sr mov ax cx mov dr dr mov dw 0x08 mov dr mmm dr mem mov cl dwx mov mmm sr mmm sr mov FData bl mov dr rat dr ra mov al awx ra ra XX dr ra Xx mov ch ax ra ra XX ra sr mov ex ew ra ra Xx ra XX sr mov ewx bw ra ra XX port ri al jout aw al port 8 al out 0x10 al Comments Flags are not changed by this command unless F is a destination register Avoid commands where IP is used as a destination Use flow control commands instead XX 1 2 or 4 depending of the size of a source or destination register mov al ewx will increment ewx by 1 mov ax ewx will increment ewx by 2 mov dr ra mov rat sr mov ra sr Take care of alignment when source or destination is located in memory It is advised to create an include file where all port addresses are defined This file will be out ri sr out 8 sr in dr ri al port ri in al dw in dr 8 al port 8 in al IoComm common for the entire project ldc a ra Push and pop instructions a code ra ldc al bwx Read code memory On
4. All elements of project have associated pop up menus Right click on the element to open it Double click on the file name opens associated source file 5 5 Starting a new project Select File New in the menu A window with an object list will open Select B3 project and press OK button You will be requested to choose a directory and give a name for your new project Select the directory 26 37 User manual and type the name of the project When you press OK button project will be created IDE window will look like following mcAsm mcdLedUart By default output directory is the same as project directory You can change it by right clicking Output element in the left part of the window and change it By right clicking Sources element in the left part of the window append existing source files or specify files which have to be created The order of source files is important See chapter Memory organization and execution start point for details If there are references to include files in the project the location of include files must be specified Right click on Include path element and add locations 27 37 Y User manual Ei F Projects McdLedUart mcdLedUart prj In order to remove source file from the project source file list B Ifa Directories right click on the file name Select Remove from project in the i i Output Out menu File will only be removed from project i
5. yr 32 bit general purpose microcontroller core User manual Rev 1 0 1 37 May 2012 birusinka com oa y User manual Summary The document describes Osinka32 MCU the internal architecture including registers set of commands and different working modes It shows how MCU can be integrated into the system with different periphery modules and communication between them All explanations are given both from software and hardware sides There will also be a description of development tools assembler directives and step by step instructions of how to build a project 2 37 oa y User manual Table of Contents De WTOC UGH OM sissies eas sisted 4 PA Mint nal S T CU TO c 5 3 Programming OSINKAS2 cccusevacnstsuessxansen eeina aaa EAEN Rn ser Ayaan AN bstn ek SER 6 3 1 REGISTER CESCIIPUOM pM 6 3 2 Structure OF ThE ASSEMBISN tile certo ttr dte p en teu keen SY tee ER ree eau ete peer tes 8 3 3 Memory AACGIESSING e 9 3 3 1 Compiler directives and variable CeClaratiON ssesssssesrererererrrrrrsrssrssrrrrennrr esse rr rr enar rr Kr rr RR RR rr rna 9 3 3 2 Address calculation and assembler MNEMONiICS sssesserrrrrssesrerrsssrrerrssrrsr sn sars e 11 3 3 3 Sequential memory reading and WIitilO sssssessreerererrrrrsssrssrssrrrrrnrrrrrrr rr rr resan rr RR rr KKR KRK ARKA ARR RAR Ra 11 3 3 4 Reading data from co
6. 3 5 2 Thread context and thread list Though thread switch is almost transparent for the user it is important to know what Thread context is Thread context is an image of all registers at the moment thread switch occurs Thread contexts of all threads are stored in the memory one after another When thread switch occurs MCU saves all registers of the current thread and loads from memory all registers of the next thread in the list executing threads one after another When it arrives to the end of the list it simply restarts from the first thread in the list Before the first swt command can be executed SW must prepare and initialize the Thread list in the memory The Thread list must be aligned by 8 Registers in the Thread context are stored in the following order 18 37 User manual When initializing Thread list SW has to initialize at least EIP and FWX register of each thread EIP is a starting point from which thread will start execution FWX must contain zero at least in IF flag because interrupts at the beginning of thread should be disabled Once thread contexts in the list are initialized application has to place the address to the list into BWX register and execute sbl command This command has one parameter number of threads in the list minus 1 Note that the thread context with index zero does not have to be initialized because it represents currently working process Example Let s make a project which contai
7. address bus has no lines 2 0 Signals Memory Write Enable and Memory Read Enable indicate which part of data is active Following pictures illustrate memory write and memory read procedures See comments for each picture Memory write diagrams AMemMosi 63 56 a A AMemMosi 55 48 AN AMemMosi 47 40 LL 00 AMemMosi 39 32 ff AMemMosi 31 24 _ J y AMemMosi 23 16 I AM emM os i 15 8 lt lt amp amp lt amp i AMemMosi 7 0 e RR O O AMemwrEn 7 J AMemwrEn 6 AMemwrEn 5 AMemwrEn 4 AMemwrEn 3 J AMemwrEn 2 AMemwrEn 1 AMemwrEn 0 J m NEN ERN DM Comment Comments for memory write diagrams see picture above Comment Explanation Writing of 1 byte Address 2 0 0x00 Only AMemWrEn 0 is active Data is present in AMemMosi 7 0 Writing of 1 byte Address 2 0 0x03 Only AMemWrEn 3 is active Data is present in AMemMosi 31 24 Writing of 1 byte Address 2 0 0x06 Only AMemWrEn 6 is active Data is present in AMemMosi 55 48 Writing of 2 bytes Address 2 0 0x02 AMemWrEn 3 2 are active Data is present in AMemMosi 31 16 Writing of 4 bytes Address 2 0 0x4 AMemWrEn 7 4 are active Data is present in AMemMosi 63 32 32 37 User manual Memory read diagrams AMemMi so 63 56 rr V AMemMiso 55 48
8. Do not save result nil r Subtract constant from register but don t save result changes only flags Logical AND dr dr amp sr Logical OR dr dr sr Logical XOR dr dr sr Next command IP NextCmd See flow control command description Do nothing just go to next command Current register context ThThis ThPrev Context of previous thread ThPrev ThThis Context of next thread ThThis ThNext Uses to indicate a Thread Context Used during Thread flow control command description Sometimes instead of r we will use definition sr or dr sr to specify the source register dr to specify destination Both source and destination must have same length both 8 bit both 16 bit or both 32 bit registers Example Command mov dr sr performs operation mov where dr is a destination register 8 16 or 32 bit and sr is a source register same length as dr 22 37 oa y User manual Memory can be addressed by different ways register constant a pair of registers and register constant Possible values of mmm 16 bit addressing 32 bit addressing axt 16 awx awxt 32 bx 16 bwx bwx 32 Cxt 16 CWX CWX H32 dx 16 dwx dwx 32 bx cx ewx bwx cwx bx dx fwx spt 16 ex cx espt 32 16 ex dx 32 These combinations are listed at the table in the left 16 or 32 bit addresses can be used 16 bit address can access only lower 64K of memory
9. El see AE RR RENSAR 31 A ursi EET 31 HZ ClOCK ANGIRESEL ER 32 1 3 Memory Interface nae erc HX ee OR E EERERR ERR E NAR ERN e EARN Yat eu URN ex Pss U RR BRL e ne RNA KRKA REFN AE 33 pe xrelim eee Ar SSA rerrcerre te rrerer errr err errr Terr errr ree tre rar 35 3 37 ka F User manual 1 Introduction Osinka32 is a high performance easy to use microcontroller core targeted for working as an embedded processor in different applications It has a rich variety of commands and is able to execute up to 2 commands per clock MCU operates with 8 16 and 32 bit data Executable program and data are located in different memory spaces Maximal program size is 8Gbytes maximal data memory addressing range is 4 Gbytes MCU has an additional 64K IO space which allows connecting different periphery modules Typical system Program memory interface ROM Flash EEPROM Data memory interface Osinka32 MCU IO periphery interface Timer Osinka32 has a hardware multithreading support IRQ handling is fast and in general the switch from thread routine to IRQ routine does not require any clock cycle meaning that if last thread command is executed in clock N the first IRQ routine command can be executed in clock N 1 IRQ routine does not need to save registers because they are saved automatically by the hardware when interrupt is handled The register content is restored upon exit from IRQ routine Saving and restoring of register conte
10. Jarzdr amp subc 3 sub c 3 3 Commands where destination register is IP cmp dr sr Ide dr sr cmp ix ax should be avoided and flow control commands land ax cb land ax cb um and c OxFE test dr sr test ax ax test dr test al 0x80 or dr sr or cD ax or dr or al 1 xor dr sr xor al e xor dr xor e 0x55 VERE Command cmp performs the same operation as sub but doesn t save the result of the operation This command is used to compare 2 operands Command test performs the same operation as and but doesn t save the result of the operation This command is used to check which bits in the register are set PY EEE ERY Shift instructions Variations Result Example Comments See explanation below 24 37 User manual Condition Result Comments Absolute Always EIP 32 Everywhere It is difficult to estimate how many clock Relative Always if Condition then 512 511 cycles flow control commands will require CF 1 or ZE 1 begin from current for execution MCU makes all possible EIP EIP 8 IP value efforts to use as less clocks as possible CF 1 end There is a powerful early branch detection CF 0 else algorithm Also MCU often executes ZF 1 begin branch command with another command ZE 0 EIP NextCmd at the same clock 2 commands per clock end CF 0 and ZF 0 In general all JMP comm
11. a or Windows 7 Linux Mint 12 Fedora 16 May work with other distributions but not tested MacOS Leopard This version is not available through birusinka site 25 37 User manual 5 2 Installation There is no installation deinstallation required IDE does not modify any system parameters Copy executable file mcdasm somewhere to your computer 5 3 Deinstallation Delete executable file mcdasm and file mcdConfig cfg from your computer File mcdConfig cfg is created automatically by IDE This is a text file where IDE saves some settings 5 4 IDE main window mcAsm mcdLedUart O x File Edit Search Project Run Environment Help Ce C Projects McdLedUart y dd 0 dup s dd 0 dup 16 FMainStack code Start sjmp sMain Align 4 There is no interrupts in this example v b gt 25 44 INS C ProjectsWMcdLedUart SrcynluMain asm compilation started 07 Jun 2012 22 23 32 Old compilation files are deleted 07 Jun 2012 22 23 33 Executable occupies 14 words less than 1 of memory Project compiled successfully 07 Jun 2012 22 23 33 Compilation files are generated 07 Jun 2012 22 23 33 e Top part of the window is a main menu e Left part of the window lists all project source files output directory and include path Right part of the window contains all open files which can be edited Bottom part shows the compilation result
12. a will be located starting with address 16 0x0010 and code segment will be started from address OxFOOO 7 Label declaration Any name with a semicolon at the end declares a label Name cannot contain spaces cannot start from a number and must contain only alphanumeric symbols Labels are used to declare variables buffers procedure names JMP targets etc 8 Space reservation db reserves 1 byte dw reserves 2 bytes 1 word dd reserves 4 bytes If directive dup is placed after space reservation it shows how many bytes words or double words to reserve In the example above FFlags occupies only 1 byte FDataBuffer occupies 64 bytes FMainStack occupies 64 bytes 4 16 64 CAlphaConst occupies 6 bytes Initialization of the variables and arrays in the data segment often has no effect if we write FFlags db 4 it doesn t always mean that at the beginning of the execution FFlags variable will contain 4 It depends whether there is a mechanism of initialization of RAM location or not in your system Initialization of constants in code segment is always done otherwise program will not work So it is guaranteed that CAlphaConst will be initialized with a zero terminated string Alpha Note that label FMainStack is placed after the space reservation and not before This will be explained later 9 Alignment of the element If we write Align 2 it forces a compiler to place following element at the even address If we write Align 4 the ad
13. al address in memory where the segment has to be located This address has to be specified for both data segment and code segment It is enough to specify this address only once in the project but it has to be specified in the file which will be compiled first This will be clarified by following examples Example Let s imagine that the project consists of only one source file 2 IRQ vectors are used to handle interrupts IrqTimer IRQ 1 and IrqUart IRQ 2 Both data and code segments are physically located at address 0 So directive 13 37 Y User manual org can be omitted See following source code data Data segment dw 0 dup 16 FStack FFlags db 0 FFifoBuf db dup 16 code Code segment sjmp Start Execution starts here Align 4 It is important to align IRQ table by 4 IRQ table starts here dd IrqTimer Pointer to the interrupt routine IrqTimer dd IrqUart Pointer to the interrupt routine IrqUart Start mov esp FStack Execution of program will start here mov al 0 mov FFlags al IrqTimer Implementation of IRQ routine is here iret Irquart Implementation of IRQ routine is here iret Example Very often at the beginning of the execution it is necessary to initialize an IRQ vector table Let s start another project which is similar to the previous one but which consists of 2 source files Main asm and IrqVect asm In the first file we keep an entry point and in the secon
14. ands require not CF 0 more than 1 clock cycle both if condition is true and if condition is false Absolute Always if Condition then Everywhere 2 4 if begin condition is CF 1 or ZF 1 lt eon A EIP TRUE In a very rare case if branch is not detected CF 1 EIP 32 early and branch command cannot form a CF 0 esp esp 4 1 if condition pair with another command and a ZF 1 end is FALSE destination command is badly aligned fo e else maximum 4 clock cycles are used begin CF 0 and ZF 0 gt EIP NextCmd CF 0 end Always EIP esp Everywhere esp esp 4 Always IP NextCmd Condition Comments IF 1 ThPrev ThThis 5 See Thread switch IRQ control chapters eip IrqIndex lt lt 1 for details Always ThThis ThPrev Always ThPrev 32 esp fwx ewx dwx cwx b Maximal number of clocks supposes that wx awx request arrived just after swt command CF 1 or ZF 1 ThThis ThNext when context of thread ThPrev is not yet CF 1 transferred to the memory AND target CF 0 command is not aligned by 4 Usually this case is rare ZF 1 ZF 0 CF 0 and ZF 0 CF 0 Other commands Command Purpose CLK Comments sbl 32 Prepares Thread mechanism 1 See Thread switch chapter for details 5 IDE description 5 1 System requirements System requirements Version Requirements Windows XP Vist
15. ch Thread which suspends the execution of a process and instructs MCU to start executing next process Remark In this version of Osinka32 thread switch cannot be initiated by hardware Similar to jump commands swt can be conditional and unconditional and has a label name as a parameter Execution will resume from indicated label Example In the following example there is a piece of code which waits data from UART and returns control to other processes if UART is not ready There are some variables and constants in the example Their declaration will not be shown We just assume that IoUartFlags name of port to read UART flags IoUartData reading from this port reads UART data buffer CByteReceived predefined constant to check UART reception flags Next byte mwaitByte in al IoUartFlags Get UART flags test al CByteReceived Check if byte is received swt z mwaitByte Pass control to next process jump to label mwaitByte mByteReceived i al IoUartData Read data from UART bwx al Copy data to the buffer Increase byte counter It will take maximum 9 CLK to switch from one thread to another but usually the switch takes as less as 3 CLK This is because MCU can prepare to the thread switch by filling internal cache If there are enough commands between 2 target labels in the example above mWaitByte and the swt_z command in the example above there are 2 so MCU will have enough time to fill cache
16. d one we will implement IRQ handlers There will be 2 IRQ handlers IrqTimer mapped on vector 0 and IrqUart mapped on vector 1 14 37 vy User manual Source file Main asm Extern IrqTimer Extern IrqUart data Data segment dw 0 dup 16 FStack FFlags db 0 FFifoBuf db dup 16 code Code segment sjmp Start Execution starts here Align 4 It is important to align IRQ table by 4 IRQ table starts here dd IrqTimer Pointer to the interrupt routine IrqTimer dd IrqUart Pointer to the interrupt routine IrqUart Start mov esp FStack Execution of program will start here mov al 0 mov FFlags al Source file IrqVect asm Public IrqTimer Public IrqUart code Code segment IrqTimer Implement code here iret IrqUart Implement code here iret 15 37 User manual Remark In the example above file Main asm must be first in the project source list file IrqVect asm must be second If it is not a case move file up or down in the list Details of using IDE will be described later See following screen shot mcAsm TestA File Edit Search Project Run Environment Help media PENDRIVE Proje v ff Directories CE Output Out v B Sources h E Src Main asm gt EJ Src Irqvect asm vig Include path 61 Inc Extern Timerirg Extern UartIrq data dw O dup 16 FStack code sjnp Start Align 4 dd TimerIrq dd UartIrq Start E
17. de MEMONIY sssossrrsrrsrrssssrsssnnnrenrssnrrrressnrnr rasar ee te RAA ARA ener RR KRK KRKA RR RR AR RR RR AA 12 3 3 5 Memory AlQNIMEN e 12 3 3 6 Data memory OFGANIZALION 0 2 2 2 cece cece cece usd a RAN Nar ANAR a aaa e iDa 13 3 3 7 Code memory organization and execution Start point 13 3 4 IO bus and communication with periphery units mnes 17 3 5 TUNGA LE 17 3 5 1 Purpose ANG Ideas eaaa ine adna EAER EDANE dusts be ARR KA FSD RASAR SRA RE aa Nee Fake ler 17 3 5 2 Thread context and thread list eene 18 3 6 Inter pis IRQ m n 21 4 Command sum may MEM 22 SIDE descriptos iana Ea ERE ens anabesauwabecetapinbasayediaasaaanaaWuusde gygededndbecbeessabetaareas 25 5 1 System requirements ccceeeecccccccecee cece eee ELLLER ESS RENE AR ARA RAR ARR KARA KRK RAR RAKA RA ARR RR RR RR RK KRK RAR RR AR RR RR RR RR ERE ERE LEE 25 SEPA inre TEE 26 sederit m 26 5 4 IDE MAIN WIDOOW ecce ee es co eene dos veces bete Reps RATE IDEAE LA SIE AR ERR EIER sedsaauuagebaceg sated ataguwageessieetneneeeeee 26 5 5 Starting a NOW proJect uec re etn enge sna RR ER EN ERERIGE KKRRTRERT RE HER ue Edere BRASAN ER RE 26 5 6 COMPpIING the projeti sc n 28 6 OUTPUT Tiles Foma aa sai o En N b SNES ANNES REN SEN SA RES ENT AE K RA R r SNR BER RN are KA SEA AS teas 30 T Hardware implementation saisies eden eb kd drar RR Arn ker h NRK a AA El aa dia RN
18. dress of the following element will be divisible by 4 0x0000 0x0004 0x0008 and so on See Memory alignment chapter for details 10 Declaration of label Similar to the data declaration label Start declares a start of the procedure or any executable code It can also be a target for JMP command 11 Executable code commands Each command occupies 1 line There can be a comment at the end of the line started with of course The full command list will be given later in this document 12 If interrupts are used the interrupt address table must be declared In this case immediately after the executable entry point label Start label in this example place short jump command to the first command to be executed and a line Align 4 The first command executed after reset will be simp Main 13 Interrupt vector table This table must be aligned by 4 and contain addresses of IRQ routines corresponding to the interrupt source Note that IRQ O does not exist in osinka32 and the first interrupt has index 1 and not O In this example there are 2 interrupts IrqTimer and IrqUart org directive for data and code segments is given only as an example In most cases both data and code segments start with address 0 examples you may download from the site So directive org is not needed 3 3 Memory addressing 3 3 1 Compiler directives and variable declaration Implementation of microcontroller systems usually requires 2 types of memory
19. e Memory which contains executable code and constants code memory e Memory which contains data variables buffers stack etc data memory Code memory is implemented as ROM EEPROM Flash It can be implemented as RAM in FPGAs but has to be loaded with executable code Data memory is implemented as RAM In order to start code segment directive code is used Directive data starts data segment In the same source file there can be several pieces of code and several pieces of data If memory segment is not specified an error message will be given by the compiler During compilation all pieces of data and code will be grouped together and one linear binary file will be produced See binary description for details 9 37 User manual Compiler directives Directive Description Starts code segment Starts data segment Reserves 1 byte for the variable Reserves 2 bytes for the variable Reserves 4 bytes for the variable Specifies the length of the array Aligns following data Specifies the physical address of mapping Makes a label declared in this module visible from other modules In order to use label declared in another module it must be declared by Extern directive Memory mapping chapter will explain how to map code and data to exact physical location Example of the assembler file Similar to the example in Structure of the assembler file chapter Public Start Extern IrqTi
20. e its first command mov esp FTermStack and continue till swt tpWait Since it is the last thread in the list control will return back to the main process and command inc ax will be executed Note that AX keeps its value despite several tasks were already executed in other threads When main process executes swt sSupervisor control is passed to UartProcess and it executes command in al IoUartFlags and so on one task after another 3 6 Interrupts IRQ Sometimes microcontroller system has to react on the external event and the reaction should be as soon as possible IRQ mechanism is used for this purpose IRQ is an external event and associated with this event small procedure handler 21 37 User manual IRQ routine should be small and fast and should return control to the system as soon as possible Command iret is used to exit IRQ routine and return control to the interrupted process IRQ routine is free to use any registers Due to thread mechanism it does not have to save register values When IRQ routine is called registers contain garbage except of IF flag which is set to 0 IRQ routine is not allowed to set this flag i e no nested IRQs are allowed IRQ routine cannot use swt command In worst case switch from thread execution to interrupt routine execution requires 5 clocks But this only happens when IRQ is sensed just after swt command is executed In general switch from thread to interrupt routine requires O clock cyc
21. ithout limitation indirect or consequential loss or damage or any loss or damage whatsoever arising from loss of data or profits arising out of or in connection with the use of this document 37 37
22. l In case of incorrect alignment compiler will give a warning but this warning is sometimes difficult to interpret See following example data StartAddr 16 FFlags db 0 FDataword not aligned dw 60 code ProcTest mov ax 0x1234 mov FDataword ax will cause an error 3 3 6 Data memory organization Data memory is organized as a linear array Start address depends on digital organization but usually starts from 0 Maximal addressable range is 4Gbytes 3 3 7 Code memory organization and execution start point Code memory is organized as a linear array Start address depends on digital settings It is O by default In order to change this value change the parameter CstartAddr in mcdCore v and recompile the project Maximal addressable range is 8Gbytes 0x0000 gt Execution start point Interrupt vectors are located at the beginning of the memory starting with address 0x0004 Each interrupt vector occupies 0x0004 gt IRQ vector 1 4 bytes of address Maximal number of interrupts supported by the MCU is 7 Interrupt O does not exist IRQ vector 2 If interrupts are used place command sjmp Start at the beginning of executable code example will be given Start gt Code constatns The order in which files are compiled is important Execution start point must be located in a file which is linked first Assembler directive org is used to specify the physic
23. l contain 0x0108 The same effect we will have if we execute mov ax 0x0108 Command mov bw ax will load the current value of AX into BW register In this example after the execution of this command BW will contain 0x0108 mov cx ah cannot be executed because the length of the operands is not the same Compiler will give an error report Flag register contain 3 special bits FL register flags bit 7 enables IRQ requests when set Z bit 1 shows that the result of the last operation is Zero C bit 0 shows that operation caused carry contains a shift or rotation result LT izicg Cono P i 7 0 All other bits can be used by the application Handling and values of the flags will be explained later in this document with the description of commands Some commands modify flags some commands don t Example SUB command can be used to subtract constant from the value loaded into the register Let s assume that BL register contains a value of 5 sub bl 5 will set flag Z indicating that the result of operation is Zero 6 37 X r User manual MOV command does not modify flags mov bl 3 will not change any flag FL register will keep its previous value When FL register is used as a source operations on it are the same as with any other registers Example mov al fl will copy the value of FL register into AL This can be useful to access memory depending on a result of previous opera
24. les Before enabling IRQ SW has to initialize thread mechanism This is because when IRQ is called all registers are saved into the current thread context IRQs can be enabled or disabled by the SW individually for each thread See Memory organization and execution start point chapter for more details 4 Command summary During command description some definitions will be used Definitions used for command description Definition Comment Example 8 16 or 32 bit register Only 8 bit register Only 16 bit register Explanation for the example Command inc increments register Any register can be used 8 16 or 32 bit Only 32 bit register pop r32 Command applies only for 32 bit registers pop al will cause an error Address register mov ah ra ra is a 16 or 32 bit register which can be used for addressing Port address Out dw awx Only AW BX CW DW registers can be used to address an IO port Only 8 bit constant mov al 8 Only 8 bit constant can be used mov al 260 is invalid Only 16 bit constant mov bx 16 ex Even if we write mov bx 4 ex constant 4 will occupy 2 bytes Only 32 bit constant mov bwx 32 el Even if we write mov bwx 5 ex constant 5 will occupy 4 bytes Memory location mov al mmm mmm specifies a memory location See following table for more details IO port in al port dw DW register contains an address of IO port
25. ly A register can be used as a destination Variations push r32 esp 4 r32 esp esp 4 Example push awx pop r32 esp r32 esp esp 4 pop cwx Comments push and pop is just another mnemonic for mov esp r32 mov r32 esp Memory read and port read instructions require 1 clock cycle for execution if the result is not required immediately by the next command Otherwise they require 2 cycles Example There are 2 examples of code which do exactly the same The 1 one requires 4 clocks for execution and the 2 one requires 3 1 example mov al bwx and al 0x01 mov cx 0x0008 23 37 X r User manual 2 example mov al bwx mov cx 0x0008 and al 0x01 The difference is in the order of commands In the 1 example the value read from the memory is required immediately by the next command and al 0x01 and in the 2 example the memory read operation is followed by a command where the read value is not used mov cx 0x0008 Note that MCU can combine memory read write operation with other operation and execute 2 commands per clock In this example this feature is not used Arithmetic instructions Variations Result Example Comments add dr sr dr dr sr add ax cb When Flag register is a destination of the add dr dr dr add al 4 command the result for 2 lower bits is different sub dr sr dires sub al e See Register description chapter for details pub dr
26. ly compiled 5 files will be generated into the output directory mcdLedUart bin e mcdLedUart hex mcdLedUart lst mcdLedUart mif e mcdLedUart s90 Output files Extension Purpose Raw data in binary format Used for direct memory programming Unused memory is filled with zeroes Motorola s90 format Only executable code is present Intel HEX format Executable code padding is present Altera s mif file format Used to implement RAM based ROM Readable listing file Contains command codes together with source code Physical address is provided for each line 29 37 US User manual 7 Hardware implementation 7 1 External interface Osinka32 external interface ACIKH ARomAddr 32 3 4 gt ROM AResetB ARomMiso 63 0 interface ACIkEn AMemAddr 31 3 Initial IP AStartAddr 31 0 AMemMiso 63 0 Address i AMemMosi 63 0 RAM interface AMemWrEn 7 0 Interrupt Alrq 7 1 requests Osinka32 AMemRdEn T7 0 ADbgExecVal lt lt AloAddr 15 0 ADbgExecEn Debug ARegFile 255 0 ae lt lt z i AloMosi 31 0 interface AlpNew 31 0 oMosi 31 0 IB AloWrEn 2 0 ADbgData 561 0 2 0 J interface AloRdEn 2 0 AloBusy 30 37 Y User manual Interface signal description Signal Direction Purpse Comments Clock and Reset ACIKH input Main clock signal input Global reset signal active low input Clock enable signal ROM interface ARo
27. mAdadr 32 3 output ROM address Address bus has no lines 2 0 64 bit data is read at once ARomMiso 63 0 _ jinput ROM data Memory gt MCU Memory interface AMemAddi 31 3 output Memory address Address bus has no lines 2 0 signals memory write enable and AMemMosi 63 0 output Data MCU gt Memory memory read enable indicate which part of data is active Not all bits AMemMiso 63 0 input Data Memory gt MCU on data bus can be valid See memory interface description for details AMemWrEn 3 0 output Memory write enable signal AMemRdEn 3 0 output Memory read enable signal I O interface AloAddr 15 0 output lO address IO address space and memory address space do not overlap IO bus AloMosi 31 0 output Data MCU gt IO can address only 65536 addresses AloMiso 31 0 input Data IO gt MCU AloWrEn 2 0 output O write enable signal AloRdEn 2 0 output O read enable signal IRQ Alrq 7 0 input Interrupt request This bus is not mandatory If no IOs are used all unused inputs of this bus must be connected to Zero 7 2 Clock and Reset ACIkH is the Main clock signal ACIkEn is the clock enable signal delivered to all the Flip Flops of the design This signal must be synchronized with ACIKH AResetB is an asynchronous reset signal delivered to all asynchronous reset inputs of all the Flip Flops of the design 31 37 Y User manual 7 3 Memory interface Memory
28. mer include IoDef h data org 16 FFlags db 0 FDataBuffer db dup 64 Align 4 dd dup 16 FMainStack code 20 org 0xF000 S t ex t addres X 9 see comment below Start sjmp Main Align 4 dd IrqTimer dd IrqUart Main esp FMainStack al 0x80 FFlags al Note that since stack grows down label FMainStack is declared after the reservation of the space All other labels are declared before the space reservation In the example above we loaded a pointer to FMainStack into ESP register using instruction mov esp FMainStack We initialized a value of FFlags using instruction mov FFlags al Note that we use square brackets when we need to access a value of the variable and we don t use brackets to get a pointer to the variable This will be explained in the following chapter 10 37 X User manual 3 3 2 Address calculation and assembler mnemonics In the assembler we will use square brackets T and in order to say that value specifies the address in memory Example Let s assume that register BWX 0x00001234 At the address 0x00001234 in the memory we had previously written OXxFF10AES54 mov awx bwx will load the value of BWX into AWX register AWX will contain 0x00001234 mov awx bwx will read 4 bytes at the memory location 0x00001234 and load this value into AWX AWX will contain OxFF10AE54 Illustration for the example Memory same for both Before execu
29. ns 3 threads Main thread supervisor Uart thread used to communicate by UART Terminal thread used to output some data on the screen The entry point of Uart thread will be called UartProcess and the entry point of Terminal thread we will call TerminalProcess Each thread will be implemented in a separate source file for simplicity So project will contain 3 files Main asm e Uart asm e Term asm At the beginning of thread list initialization we will fill all registers with zeros to avoid garbage and basically to initialize FWX Flags Then we will specify the entry point for each thread 19 37 Y User manual Source file Main asm Extern UartProcess Extern TerminalProcess data Data segment Variable declaration dd dup 16 FStack Align 8 FThreadList FThMain dd dup 8 FThUart dd dup 8 FThTerminal dd 0 dup 8 code Code segment Start mov esp FStack Execution of program will start here Thread list initialization Fill thread list with zeroes mov awx 0 mov cl 24 3 8 24 size of entire list mov bwx FThreadList fill list with zeroes sThListFill mov bwx awx dec cl jnz sThListFill Specify entry points aa Vart mov bwx FThUart mov awx UartProcess shr awx 1 Code memory is organized by words so divide address by 2 mov bwx 28 awx 28 is EIP offset Terminal mov bwx FThTerminal mov awx TerminalProcess shr awx mov bwx 28 awx ini
30. nt does not require any clock cycle and is done by the hardware in the background In the document the code memory space will be called ROM and the data memory space will be called RAM 4 37 User manual 2 Internal structure Simplified MCU structure osinka32 Earl y Command MCU Branch decoder E detector Command priority Command Command and decoder B i Execution compati Unit Command bility queue check Command Command decoder A Command Command fetch amp align decoding execution Registers Thread control Next thread cache Prev thread cache keg IRQ controller ROM RAM IO IRQ interface interface interface External controller Interface MCU consists of several blocks External interface is used to communicate with RAM ROM and IO Interrupt controller receives and prioritizes interrupt requests Command fetch and align controller constantly fills command queue with commands loaded from ROM detects potential JMPs in the queue and tries to pre decode them Command decoder takes commands from queue decodes them and checks command compatibility trying to execute 2 commands per clock Command execution unit provides execution of decoded commands MUX and ALU block selects registers operands and executes arithmetical or logical operations Registers contain data operands pointers and command execution results Thread controller provides switch from one thread to another for multi
31. r will be read to AL in ax 0x13 Data will be read from port 40x13 and be placed into AX register out bx awx Data previously placed into AWX register will be written to the port addressed by BX register out 0x12 awx Data from AWX register will be written to the port 40x12 Remark When working with IO space the alignment is not necessary For example we can output AWX to address Ox13 The hardware periphery is responsible for the data treatment We can use the same address to output data of different width and periphery can perform different functions By doing so we can save IO space There are free periphery examples given with the MCU They actively use this feature See periphery examples for details 3 5 Thread switch 3 5 1 Purpose and idea Thread switch is a mechanism which allows to execute several processes at the same MCU at virtually the same time Of course since there is only one core MCU will execute one process at a given time But the switch from one process to another is very fast and in general requires 3 clock cycles when MCU executes thread switch it suspends active process the process which is executed now and starts executing another process Later the execution of suspended process resumes The process does not feel the thread switch because registers stays unchanged 17 37 y User manual Thread switch can be initiated by SW there is a special command swt Swit
32. remented by 2 before execution of the command and data will be read from the new address OXAE 0x1032 0x24 0x1034 gt 0x14 This command will We are trying to write 4 byte data to cause an error non aligned address MCU will not because address of 4 perform this operation Take special byte element is not care to align all variables arrays aligned etc 0x1034 gt mov ewx dwx ed 0x8055 iy 0x1033 3 3 4 Reading data from code memory Application can keep some data in the code memory ROM EEPROM Flash It is very useful to store there some initialization data constants etc In order to read code memory special command Idc is used Only b c d and e registers 32 or 16 bit can be used as an address code Code segment CConstString Some constant db Test string O Align 2 do not forget to align executable code ProcTest mov bwx CConstString Initialize pointer BWX in this case ldc al bwx After this operation al will contain T 3 3 5 Memory alignment MCU cannot read or write 2 byte variables if their address is not aligned by 2 and 4 byte variables if their address is not aligned by 4 This rule applies to all data both in data segment and in code segment This rule applies for all arrays of 2 byte and 4 byte elements Since push and pop commands which access stack work with 4 byte data stack must be aligned by 4 12 37 oa yv User manua
33. ress 0x1234ABCD mov eip lt value gt is the equivalent of JMP instruction In fact jmp lt label gt is just another more readable mnemonic of mov eip lt value gt command User should avoid using direct loading into the EIP register but use versions of the JMP and CALL instructions instead which will be described later in the document Of course sometimes it is not possible or bigger flexibility is needed For example SW designers can keep the procedure address table in the memory and execute JMP or CALL using pointers in this table This method is fast very flexible and well readable and can be considered as a good style of programming ESP register is the General Purpose register It can be freely used by the SW in Stack pointer any operations as a source and as a destination In the IDE there are commands push and pop which use ESP register as a stack pointer 8 and 16 bit parts of stack pointer register are addressable If application does not use stack it can freely use ESP as a general purpose register even parts of it For example SPH addresses bits 15 8 of ESP 7 37 y User manual Remark PUSH and POP commands are the pseudonyms of more common memory addressing commands push lt register gt mov esp lt register gt pop lt register gt mov register esp User can implement the equivalent of them using any other register 3 2 Structure of the as
34. sembler file The description of the assembler file structure will be given here by the example Later in this document all elements will be explained in details Example of assembler file structure Element Source text Public Start Extern IrqTimer include IoDef h data org 16 FFlags db 0 FDataBuffer db 0 dup 64 Align 4 dd dup 16 FMainStack code org 0xF000 S ec X see comment below Start sjmp Main 4 IrqTimer IrqUart mov esp FMainStack mov al 0x80 mov FFlags al CAlphaConst db Alpha 0 Explanation of elements 1 Comment Starts with Can be placed at the end of the line 2 Public declaration Label Start is implemented in this module but must be accessed from another module 3 External declaration Label IrqTimer is declared and implemented in another module of the project but it is used here in this module 4 Include files usually contain definitions common for entire project It can be different constants definitions of IO ports etc 5 data is a declaration of the data segment It is a place in the memory where internal variables buffers stack are declared code is a declaration of code segment Usually it contains executable 8 37 Y y User manual code and constants 6 org directive placed immediately after the declaration of the segment code or data specifies the physical location of the segment in memory For this example dat
35. ssing 4 2 and 1 byte access of the same address can be interpreted differently AloWrEn can only have these values e O0 no operation e 1 byte write e 3 word write e 7 double word 32 bit write All other values are RFU IO write diagrams aroader as e OOOO AIoMosi 31 24 III NV AIoMosi 23 16 AIoMosi 15 8 HH C 2 C DD sonst 7 61 O RES ES AIoWrEn 2 AIoWrEn 1 AIoWrEn 0 Comment Comments for IO write diagrams see picture above Comment Explanation Writing of 1 byte Address 1 0 0x00 AloWrEn 0 is active Data is present in AloMosi 7 0 Writing of 1 byte Address 1 0 0x01 AloWrEn 0 is active Data is present in AloMosi 7 0 Writing of 2 bytes Address 1 0 0x00 AloWrEn 1 0 is active Data is present in AloMosi 15 0 Writing of 2 bytes Address 1 0 0x01 AloWrEn 1 0 is active Data is present in AloMosi 15 0 Writing of 4 bytes Address 1 0 0x00 AloWrEn 2 0 is active Data is present in AloMosi 31 0 34 37 oa y User manual AloRdEn can only have these values e O0 no operation e 1 byte read e 3 word read e 7 double word 32 bit read All other values are RFU IO read diagrams Atomddr 15 o FIDE DE ERE Ef AIoMiso 31 24 n AIoMiso 23 16 or AIoMiso 15 8
36. t will not be B 8 Sources physically deleted from the disk B Src mluMain asm In order to change a position of the file in the list select Move Up or Move Down in the menu i Src mluLed asm Eh Remove from project zi 7 Ef Openin editor dbl ick T Move Up 4L Move Down 5 6 Compiling the project Press F9 or select Project Build in the menu to compile the project If there is no errors project will be compiled Otherwise the file where the first error was found will be opened and error will be reported mcAsm mcdLedUart sjmp sMain Align 4 There is no interrupts in this sMain mov esp FHainStack nopa mov Unknown command nopa or command mov does not exist with this list of mov Parameters Compilation started 11 Jun 2012 20 39 25 Old compilation files are deleted 11 Jun 2012 20 39 25 Src mluMain asm 22 13 Unknown command nopa or command does not exist with this list of parameters Compilation stopped due to errors 11 Jun 2012 20 39 25 28 37 yv User manual 6 Output files format Compiler produces different types of output files All of them have the same name as the project file but differ by the extension They are generated into the output directory Example Project name is mcdLedUart prj It is located in the directory F Projects McdLedUart Output directory is F Projects McdLedUart Out See picture above When project is successful
37. thread support loads and stores thread context in the background when RAM bus is not free 5 37 gt User manual 3 Programming osinka32 3 1 Register description MCU has 8 32 bit registers Each of them can be split and a part 8 or 16 bit of register can be addressed Each row is named by letters A B C D E F ESP and EIP Each column is addressed by a suffix Naming of registers Registers Column bits Suffix Example 7 0 L ELis the lowest part of E register bits 7 0 15 8 H DH addresses bits 15 8 o D register 15 0 X ICX is lower 16 bit part of C register bits 15 0 31 16 W BW is higher 16 bit part of B register bits 31 16 31 0 WX AWX is a complete 32 bit A register bits 31 0 Some registers have special function Register FL contains flags Some of flags represent the result of the last operation another is used to enable and disable interrupt request Register IP is Instruction pointer It contains the address of a command which will be executed at the next clock This register is changed incremented by the command size automatically during execution Remark It is not likely that SW will use 8 or 16 bit parts of registers IP and SP Example MOV command can be used to load value to the register For example mov al 0x08 loads 0x08 to AL register mov ah 0x01 loads 0x01 to AH register After execution of these 2 commands AX register wil
38. tialize start point Enable thread mechanism mov bwx FThreadList sbl 2 3 1 2 number of threads in the list Now we are free to execute swt mov ax 17 sSupervisor inc ax swt sSupervisor 20 37 Y User manual Source file Uart asm Public UartProcess data Align 4 dd 0 dup 16 FUartStack code UartProcess mov esp FUartStack call UartInit upWait in al IoUartFlags Read UART flags test al 0x80 Let s imagine to verify if the data was received we analyze a flag swt z upwait If UART not ready switch task and wait It is just an example upProcessData Implement code here Source file Term asm Public TerminalProcess data Align 4 dd 0 dup 16 FTermStack code TerminalProcess mov esp FTermStack call TimerInit tpwait in al IoTimerFlags Let s imagine we are waiting some timer event test al 0x01 It is just an example jnz tpTimerOver test al 0x02 jnz tpSomethingElse swt tpwait tpTimerOver Implement code here In this example we do not initialize ESP for all threads Thread procedure is responsible to initialize ESP itself in this case When we first call swt sSupervisor in Main function control will be given to the next thread In our case it is UartProcess It will execute its first command mov esp FUartStack and continue execution till swt z upWait At this point control will pass to the next thread Terminal process Like UartProcess it will execut
39. tion After execution Comment commands Address awx 0x00000000 awx 0x00001234 Value of BWX is copied into AWX 0x1234 bwx 0x00001234 bwx 0x00001234 register 0x1235 0x1236 0x1237 0x1238 awx 0x00000000 awx OXFF10AE54 Value of memory at the address in bwx 0x00001234 bwx 0x00001234 BWX register is copied into AWX register There are several possibility to specify address Any of 32 or 16 bit register except of IP can be used by the SW to hold a pointer We can also use a pair of registers base index a register and a constant Following table gives all possible combinations indicates a constant 32 bit constant is used in a pair with a 32 bit register 16 bit constant makes a pair with a 16 bit register Note that if 16 bit register is used the addressable range cannot exceed 64K Possible combinations to compose an address Register Example Comments b ax ax bwx ewx cwx al dx ewx al fx fw ax esp 2 Since stack grows down constant in this command is gt 0 mov ax sp 2 does not exist ew FData FData is the variable declared somewhere in the application FDataBuf awx bh FDataBuf is the name of an array declared somewhere in the application bx 2 bx ax cwx 4 al dx 3 ax bwx cwx With of registers which form a pair must be identical i e Both registers must be of 32 bit or al bx dx both registers m
40. tion where flags Z and or C will be used to compose an address to access See memory access commands for more details Following piece of code illustrates how to add flag C to AH register mov al fl and al 0x01 add ah al When FL register is used as a destination the values of the flags Z and C are logical OR of the previous value of the flag and the result of the operation Though this is possible in the SW using C and Z bits of F register as a destination should be avoided because it is difficult to imagine the exact result of these bits The exception is MOV command when result values can be easily predicted Example mov fl 0x80 will enable interrupts EIP register is the address of the instruction which will be executed in the next Instruction pointer inter clock This register is incremented automatically by the length of the command P with parameters each time MCU executes a command EIP Though 8 and 16 bit parts of instruction pointer register can also be addressed for example we can address IPL as a lowest 8 bit part of the register it is not recommended to do so EIP register can be freely used in the SW as a source Any use of this register as a destination will instruct MCU to clean the instruction queue and to continue execution from the address loaded into EIP register Example mov eip 0x1234ABCD will instruct MCU to clean the command queue and continue execution from the command located in add
41. ust be of 16 bit ewx cwx ah al ex dx 3 3 3 Sequential memory reading and writing When dialing with arrays it is often necessary to access their elements sequentially There is a set of commands which will automatically increment or decrement the pointer When command access 2 bytes 11 37 amp ye User manual value pointer will be incremented or decremented by 2 If 4 bytes is accessed the pointer will be incremented or decremented by 4 Only post incrementing and pre decrementing are allowed In the assembler we will place after the pointer in order to show that address has to be incremented after the operation We will place before the pointer to force the address to be decremented before operation Examples of sequential memory access commands Example mov al bx Before execution al 0x00 bx 0x1000 After execution al 0x12 bx 0x1001 Comment Address in this case it is a BX register is incremented after Memory execution 0x1000 gt Memory 0x1000 gt After execution of this command address CWX register is incremented by 2 because we have written 2 bytes mov cwx ax ax 0x8055 ax 0x8055 Cwx 0x1000 Cwx 0x1002 Memory Memory 0x1000 gt 0x1000 gt ew 0x8055 ew Ox24AE dx 0x1034 dx 0x1032 Memory Memory Address DX register is dec
42. xecution will start here Compilation started 25 Oct 2012 22 21 30 old compilation files are deleted 25 Oct 2012 22 21 30 Executable occupies 2 words 0 of memory Project compiled successfully 25 Oct 2012 22 21 30 Compilation files are generated 25 Oct 2012 22 21 30 Screen shot above is made under Linux Fedora 16 16 37 oa y User manual 3 4 IO bus and communication with periphery units IO bus is provided for addressing periphery units such us timers UART ports SPI Codecs etc Digital designers can map all these devices to the memory address space as well but separate IO bus has several advantages Address decoding is easier less address lines to decode e Performance of the system is better usually the slowest path goes through the memory additional multiplexers bring bigger delay Command size is smaller There are several disadvantages e There are lower variety of commands to work with IO than with memory Register choice to work with IO is restricted only B register can be used as a port address only A register can hold data IO port can be addressed by a 16 bit register or a 8 bit constant If a 8 bit constant is used port address cannot exceed 255 Only 4 16 bit registers are available as a port address AW BX BW DW Only A register AL AX or AWX can be used to hold data IO access commands Example Comment in al dw Data from port addressed by DW registe
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