ispLeverCORE IP Module Evaluation Tutorial
Contents
1. File View Help H Schematic Verilog HDL 7 Ta 3BM416C R ispxPGA 4 9 ispXPLD 5000M e CO Iv5g00 a CH oRZcO0A ORZTOOA ispL ever Project Path JCATEMPS S se ORZTOOE lt a oR3COO CSS EN Module Name MyCompany_JAS_Encoder Eed 5 OR4E00 IP Device_Family 0R4E00 Design Entry Schematic verilog HDL zl Lattice Pe 4 Convolutional_Encoder Macro_Type IF a DDR_SDRAM_Controller c Kaes Device Jorde04 3BM41 ER x a MC DMA_Controller HE a PCI_Target RSeEncoder T PL3 Luke Layer Core_Name a PL3_PHY_Layer RS_Encoder Customize Help El Triple_Speed_Ethernet_ e Turbo Decoder ES UTOPIA3 Master vi gt foHepesFi O NNN 5 Click Customize to open the configuration screen for your chosen IP module Set the desires options and then click Generate Lattice IP Core Reed Solomon Encoder 0 3 1 Setting daira Options Ee a gstart P nee met rootspace i 2 3 lten S Coretype Lei 92 ei Algotype fi D Registered Input Encoder Type e Yes C w CS Continuous Handshake Generate Load Parameters Cancel Help The Module IP Manager generates the Lattice Parameter Configuration LPC file to the specified location 6 To verify the parameter settings click on the Load Parameters button and select your saved 1pc file Your saved parameter will load into the Module IP Manager tool for verification 72. This procedure shows you how to use Synplicity s Synplify outside the ep EVER Project Navigator to synthesize your isoLeverCORE IP module and create an EDIF file To run synthesis using Synplify 1 2 3 4 5 Create a new working directory for synthesis Open Synplify Add the design files specified in your IP download readme htm file Set the Implementation Options that are specified in your IP download readme htm file Click Run to generate an EDIF file Note For more detailed information refer to the Synplify for Lattice User Guide and the ispLEVER online Help and tutorials Lattice Semiconductor Corporation 9 ispLeverCore IP Module Evaluation Tutorial Running Synthesis Using LeonardoSpectrum This procedure shows you how to use Mentor Graphics LeonardoSpectrum outside the ispLEVER Project Navigator to synthesize your ispLeverCORE IP module and create an EDIF file To run synthesis using LeonardoSpectrum il 2 3 4 5 6 Open LeonardoSpectrum Select the target device and options specified in your IP download readme htm file Set the Working Directory path pointing to the lt download_name gt lt device gt lt version gt source directory Add the design files specified in your IP download readme htm file Set any other options that are specified in your IP download readme htm file Click Run Flow to generate an EDIF file Note For more detailed information refer to the LeonardoS
3. Lattice Semiconductor Corporation ispLeverCore IP Module Evaluation Tutorial Purchasing an ispLeverCORE If you are satisfied with the results of the evaluation you may purchase Lattice s ispLeverCORE Intellectual Property modules through your local Lattice Sales Office Lattice s ispLeverCORE IP modules are sold in either bitstream format for part numbers ending in B or 1 configuration of a post synthesis gate level netlist part numbers ending in N Each ispLeverCORE is sold with 1 year or 10 hours of technical support whichever comes first Extended service contracts are also available For IP purchasing in general you will follow these steps 1 Identify the IP module that you want to purchase 2 Download Lattice s standard Intellectual Property License Agreement from the Lattice website http www latticesemi com products devtools ip levercore cfm Review sign and deliver the License Agreement to your local Lattice Sales Office Select the parameters for your IP module and send the configuration file to your local Lattice Sales Office After Purchasing After you have purchased and licensed your ispLeverCORE you can continue the implementation and programming flow You will be able to perform full timing simulation and generate a bitstream file for programming your Lattice device Lattice Semiconductor Corporation 13 ispLeverCore IP Module Evaluation Tutorial Configuring your ispLeverCORE You can
4. the included top level RTL source can be used as your top level design without modification VHDL Designs To instantiate a VHDL module 1 2 Using a text editor open your top level design file Open the top level RTL source located in the source directory of the Evaluation Pack and copy the contents into your top level design Connect the ports to the IP module by replacing the default port names in the I O section of the instantiation template with the actual port names from your design Note If the top level RTL source in the package contains any instantiated PLL and or specific I O types those modules must also be instantiated in your top level design Include attribute statements for Synplify or Leonardo Spectrum synthesis by typing one of the following depending upon the synthesis tool you have chosen attribute syn_black_box boolean attribute syn_black_box of lt module_component gt component is true attribute noopt boolean attribute noopt of lt module_component gt component is true 5 Save your top level design file Lattice Semiconductor Corporation ispLeverCore IP Module Evaluation Tutorial Note If you want to check the core implementation result for core evaluation purposes the included top level RTL source can be used as your top level design without modification Lattice Semiconductor Corporation 7 ispLeverCore IP Module Evaluation Tutorial Running Functional Simulation Usin
5. You must send us the LPC file 1pc to Lattice so that we can configure the IP core and send it to you Please send your LPC file to the Lattice location listed in your purchase 16 Lattice Semiconductor Corporation ispLeverCore IP Module Evaluation Tutorial confirmation e mail or to your local Lattice Sales office As soon as Lattice receives your LPC file we will e mail you a confirmation of receipt and the scheduled shipping date of your ispLeverCORE Lattice Semiconductor Corporation 17 ispLeverCore IP Module Evaluation Tutorial Getting Technical Assistance For technical support assistance please contact Lattice Applications at Hotline 1 800 LATTICE Domestic 1 408 826 6002 International E mail techsupport latticesemi com Internet http www latticesemi com Evaluating Other IP Modules To evaluate IP module configurations that are not included in the Evaluation Packages contact your local Lattice sales office 18 Lattice Semiconductor Corporation
6. these links to work properly the tutorial must be installed in the IP download folder for example lt reeds_enco_o4_1_004 gt tutorial Directory Path Description To accommodate all ispLeverCORE IP module download packages the directory paths are described as lt variables gt For example the actual directory path for the Reed Solomon Encoder for an ORCA4 device is reeds_enco_o4_1_004 orca4 verl source However the path name in the tutorial would be represented as lt download_name gt lt device gt lt version gt source 2 Lattice Semiconductor Corporation ispLeverCore IP Module Evaluation Tutorial Evaluation Pack Directory Structure The directory structure for the Lattice ispLeverCORE evaluation package is shown below and includes the basic description of the contents lt download_name gt readme htm Contains specific instructions for using the ispLeverCORE default css Style sheet for the readme lt tutorial gt Empty tutorial folder lt device gt lt version gt eval Customer RTL functional simulation directory for evaluation readme txt file contains specific simulation information testbench Contents testbench for evaluation tests Contents Stimulus file s simulation Run execute functional RTL simulation here Example do script runsim_rt1 do scripts Contents ModelSim macro do to run simulation
7. CHASING DEET 13 ie te idee Tee EEN 14 Getting Technical Assistance ccceccceeeeeeeeeeeeeeeee cee eeeeaeeeeaeeeaeeeceaeeeeaaeeeeaaeseaeeeeaeeseaaeseeaeeseeeees 18 eil 18 EES We seed E da oe sarees Eege desde deed ge eebe EE Eege deed 18 ala EE A E dente degen eneen gege 18 Evaluating Other IP Modules ccccccceeceeeeeeeeeeeceeeeeceaeeeeaaeceeeeeceaeeeeaaeeseaeeseeeescaeeesaeeseneeseaees 18 ispLeverCore IP Module Evaluation Tutorial Getting Started Lattice s ispLeverCORE IP modules are large modular design blocks that can be reused and easily placed within your programmable logic design Other Tutorial Versions and Formats This quick start tutorial is designed to help you evaluate and purchase the IP module package you have chosen as quickly as possible Admittedly it is brief and intended for users that are familiar with all the required tools and processes Other versions and formats are available as described below A printable PDF version of this tutorial is available from the Lattice website Supported Technologies Lattice ispoLeverCORE IP modules are available for ispoXPLD isoXPGA ORCA4 FPGA ORCA FPSC LatticeEC ECP and LatticeXP technologies This tutorial is written to support all device technologies with differences noted where important Tutorial Location This tutorial contains links to additional information in the evaluation core s readme htni file necessary to complete the tasks For
8. g ModelSim A simulation script file is provided in the eval directory for functional RTL simulation The script file lt nodelsim_macro_name gt do uses pre compiled models provided with this package The pre compiled library of models are located in the directory lt download_name gt lt device gt lt version gt lib modelsim work NOTE This procedure is applicable ONLY when using ModelSim SE for simulation The Lattice Edition of ModelSim that comes with the ispLEVER software does not support the pre compiled models necessary for functional simulation To run functional simulation using ModelSim 1 Open ModelSim 2 Choose File gt Change Directory and go to the lt download_name gt lt device gt lt version gt eval simulation directory 3 Run the ModelSim DO macro file If you are running version 5 5e or earlier choose Macro gt Execute Macro and select the fille scripts lt modelsim_macro_name gt do If you are running version 5 6a or later choose Tools gt Execute Macro and select the fille scripts lt modelsim_macro_name gt do The ModelSim macro executes an evaluation test bench designed to show some example transactions or functions associated with the core Using the precompiled libraries you can build your own test benches 4 View the waveform results in the Wave window 8 Lattice Semiconductor Corporation ispLeverCore IP Module Evaluation Tutorial Running Synthesis Using Synplify
9. gui_script Contents module_gen zip See Note below par Contents 1 1pc file specifying IP module configuration 2 One of the following database constraint file pairs ispXPGA 1d2 database file and 1ct constraint file ORCA 4 FPSC EC ECP XP ngo or nmc database file and prf constraint file isoXPLD b11 database file and 1ct constraint file source Contents 1 Verilog and or VHDL top level source files for instantiation and synthesis 2 Parameter file s that contain IP specific configuration values modelsim work Compiled simulation models for ModelSim Lattice Semiconductor Corporation 3 ispLeverCore IP Module Evaluation Tutorial Installing IP Graphical User Interface If the gui_script module_gen zip file is present in this release package it is because the isoLEVER software does not contain the utility that allows for the configuration of this specific IP module using the Module IP Manager The gui_script module_gen zip file contains a directory of files that allows for the configuration of this IP module using the Module IP Manager To configure the IP module using the Gol EVER Module IP Manager 1 Go to the directory in where the isoLEVER software is installed 2 Unzip the module_gen zip file into the ispcpld folder 3 If you are prompted to overwrite some existing files respond Yes 4 If the isoLEVER Project Navigator is open exit and rerun the tool The IP module wi
10. ispLeverCore IP Module Evaluation Tutorial IP Module Evaluation Tutorial Table Of Contents Getting Started ck adi Lan ai ele i ee ae ic cle 2 Other Tutorial Versions and Formats c cccccceceseeceeneeceeeeeeaeeeeneeceeeesaeeesaaeseeeeeseaeeesaeeseaeeseaees 2 Supported Technologies cccccceeeeeceenceceeeeeceaeeeeaaeeeneeecaeeeeaaesaaeeceeeeecaaeseeaaesseneescaeeseaaesseneeenaees 2 Tutorial Be LI 2 Directory Path DeScription ccasicckis east needa eevee te tennant ee aes 2 Evaluation Pack Directory Giruciure nenn nnn tennent 3 Installing IP Graphical User Interface c cccccceecececeeeeceneeeeeaeeeeeeeseeeeeceaeeeeeaeseeeeeseaeessaeeeeeeteeeeess 4 Evaluation Tutorial FIOW csccescccicecsetlecipestedetasatvecssinuadessinideciatiiadendsacdecdsiitade asin dectstaladesauatdecasenade dtd 5 Instantiating the Evaluation Core 6 Verilog Bee E 6 Viel UR NEE 6 Running Functional Simulation Using ModelSim ccccceeeeeeeeeeeeeeeeeeeeeeaeseeeeeseeeeeaeeeeeeseeeeess 8 Running Synthesis Using Synplify AANEREN 9 Running Synthesis Using Leonardotzpechum nt 10 Implementing the IP Module Using pl EVER AAA 11 For CPLD Devices ccccccceeeeeceeeeeeceeeceaeeeeaaesseaeecaaeeecaaeseeaaesgaeeecaaeeseaaesseaaeseeeesaeeseaaeseeneeesaees 11 FOr ISOXP GA DEVICES surasini naiaiae i aaa a a aian aaea eaaa a 11 For ORCA FPSC EC ECP XP DeVICES A 11 Timing Report e EE 11 Purchasing an Iepl ever OPE 13 Aiter PUR
11. ll be included in the list when the Module IP Manager is run Lattice Semiconductor Corporation ispLeverCore IP Module Evaluation Tutorial Evaluation Tutorial Flow You must run this tutorial in its organized sequence The only flow option is the synthesis tool you are using You can return to this flow diagram by clicking the Flow button at the end of each lesson You can also navigate this tutorial using the Contents pane on the left side of your browser Lattice Semiconductor Corporation 5 ispLeverCore IP Module Evaluation Tutorial Instantiating the Evaluation Core The IP module evaluation package includes a top level RTL source Verilog and or VHDL that can be used as an instantiation template for the IP core Verilog Designs To instantiate a Verilog module 1 2 Using a text editor open your top level design file Open the top level RTL source located in the source directory of the Evaluation Pack and copy the contents into your top level design Connect the ports to the IP module by replacing the default port names in the I O section of the instantiation template with the actual port names from your design Note If the top level RTL source in the package contains any instantiated PLL and or specific I O types those modules must also be instantiated in your top level design Save your top level design file Note If you want to check the core implementation result for core evaluation purposes
12. pectrum for Lattice User s Manual and the ispLEVER online Help and tutorials Lattice Semiconductor Corporation ispLeverCore IP Module Evaluation Tutorial Implementing the IP Module Using ispLEVER This procedure shows you how to implement the IP module using the isoLEVER Project Navigator and read the timing report To implement the IP module and generate the timing report 1 Open ispLEVER and create an EDIF project in a new place A route directory 2 Select the target device specified in your IP download readme htm file same as you used for synthesis Delete the existing constraint file created when starting a new project Copy the evaluation database and constraint files from the lt download_name gt lt device gt lt version gt par directory to your place amp route directory These files are specified in your IP download readme htm file 5 Rename the copied constraint file to the same name as your project For example if your project is named demo syn then the constraint file must be named demo 1ct or demo prf 6 Choose Source gt Import and select the EDIF netlist file For CPLD Devices 7 Double click the Timing Report process to open the Timing Report 8 You are finished with the evaluation tutorial For ispXPGA Devices 7 Double click the Post Route Timing Report process to open the Timing Report 8 You are finished with the evaluation tutorial For ORCA FPSC EC ECP XP Devices 7 Choo
13. se Tools gt Timing Checkpoint Options and set the options as specified in your IP download readme htm file 8 Select the Place amp Route Design process right click to open the Properties dialog box and then set the properties as specified in your IP download readme htm file 9 Double click the Place amp Route Trace Report process to run place and route and to open the Timing Report Note For some ORCA4 ispLeverCOREs the Cycle Stealing Process may be required to achieve the required timing specification Check the isoLeverCORE readme file to see if this additional process step is necessary Timing Report File Some cores are overconstrained to achieve maximum timing performance The user may observe timing violations when viewing the timing report To obtain actual results use the Post Route Trace preference files to generate the correct timing report Lattice Semiconductor Corporation 11 ispLeverCore IP Module Evaluation Tutorial 1 Replace the preference file Ict or prf in the project directory with the following Post Route Trace file Rename the Post Route Trace preference file to match the project name o post_route_trace_synplify Ict or prf for Synplify o post_route_trace_leonardo ct or prf for LeonardoSpectrum 2 From the GUI of the Project Navigator right click on Post_Route_Timing_Report for XPGA or Place_Route_Trace_Report for ORCA ORCA FPSC EC ECP XP The new timing file is generated 12
14. t View Favorites Tools Help Feiniedit exe 96KB Application Plinstalls exe 84KB Application ial idispchkPtOptn exe 36KB Application Plispdsdmn exe 388 KB Application OiispExp exe 40KB Application P 15Pflow exe 352KB Application ispmg exe 1 024KB Application Plispnetlist exe 156KB Application Plisprpt2html exe 40KB Application fF isptca exe 40KB Application isptla exe 40KB Application WB isptrceoptn exe 36KB Application 4 Update ee 40KB Application L LZelm ep Anniication 3 Inthe Open Project dialog box do the following 14 Lattice Semiconductor Corporation ispLeverCore IP Module Evaluation Tutorial Select To start a new design Set the directory path for the Lattice Parameter Configuration file 1pc This can be any location Select the netlist format Select your target device Open Project Schenatc eiegHOL z e04 3BM E 4 Click Continue to load your selections into the Module IP Manager and open the GUI In the GUI do the following Expand tree for the device family you have selected and select the IP module that you want to configure and purchase Under Module Name type a name for your IP module This can be any name you choose Special characters are allowed Lattice Semiconductor Corporation 15 ispLeverCore IP Module Evaluation Tutorial FyModule IP Manager C TEMP
15. use Lattice s Module IP Manager tool included with Lattice s ep EVER software to specify the IP module parameter settings This will generate a Lattice Parameter Configuration file 1pc You must send us this LPC file before we can send you your configured IP module Please send it to the Lattice location listed in the confirmation e mail As soon as we get this file we will e mail you a confirmation of receipt and a scheduled ship date The Lattice IP parameterization tool Module IP Manager is incorporated in the ispLEVER software It provides a GUI for entering the required parameters to configure the core After all required parameters have been entered the following file are generated Parameter file lt IPname gt 1pc This file contains the configuration parameters you entered via the Module IP Manager GUI Usually the Module IP Manager is run from the ispLEVER Project Navigator However for generating your IP module configuration file you will run the Module IP Manager in standalone mode Note This procedure uses the Reed Solomon Encoder for a Verilog design implemented in a Lattice ORCA 4 device as an example Your specific settings will be different To use the Module IP Manager to generate an LPC file 1 Go to the directory where your Module IP Manager application is installed for example lt isplever_install_path gt ispcpld bin 2 Double click ispmg exe SS C ispTOOLS ispcpld bin File Edi
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