Simple Conversion
Contents
1. 10 Double click on the SDF icon to edit the Enlarge the desktop and insert another Verilog in operation as signal definition file Add the readout and shown writeout control signals to the bidir buses ad 7 0 amp a 7 0 as shown A sample file is z included sio85 sdf mod ened aa geme 11 Highlight the first verilog in and right click cut to delete it We don t need it to generate the signal definition file more 2 Highlight the rem right click select InsertNew 13 A new SEF databa Highlight and rename it to to commit the in sef name se icon is inserted in sef Hit Enter 14 Now run the scenario and the VCD flow has arrived at the same stage as the EVCD s described in section a Next add timing and pattern to SEF and generate a WDB this is cyclization 15 Save the scenario with Save As Then type in my ved in scenario and click OK E eo seein sin te 4 Cyclization From SEF to WDB This section shows you how to add timing and pattern to the simulation events in the SEF database and create from it a WDB database ready for ATE consumption The test case included for this tutorial is a very well behaved uniform transitions and with simple timing thanks to well considerate design testhench Therefore we will not discuss much simulation conditioning here In many cases bus transiti2. test So the output files will be test ave pattern test dve timing test pin pin test run script to run the Verigy AIT tools to generate binary pattern from the test ascii files and test aic configuration file for the Verigy AIT tools mentioned To configure your outputs or various options of the agilent93000ait wavebridge double click on its icon to reveal the PropertySheet ad File Advanced Test Control from external ASCII file Use default NO Assign ATE resource to produce test program Use default YES Produce ATE Repeats Loops Subroutines autom default FLATTEN cally Use Use default YES Use a user specified pinmap file Use default 0 for now Output pin timing pattern files separately Use default SEPARATE I p open temporary scenario 2 stip Run View wavebridge agilent9300 File ES generate ATE scan patterns If NO flatten scan to parallel patterns Use default Remove or Use Equations in Timing Use default Remove for now a493000_p1000 EJ Verigy93000 highspeed Output Tester Control for re use in later runs Name specied at the upper scenario level ames specied at the upper scenario level nodes AUTO x2 x3 or 44 Use default AUTO Tester model Use default ag93000 p1000 Adjust minor ATE
3. the sio85 eved file We ll name it in sef for reference later when we describe automatic timing and pattern extraction from it b In Converta VCD File to a TDS SEF Database Because in VCD signals have no direction users will have to specify their own signal directions and bidirectional change controls Double click on the ee Sen a eee eee Ee Syed folder to eater bi s ee went vua vm oti n A Browser iix Click to select the He s om senses pni vior qutm d sio85 vcd file Then right en click to reveal the drop down menu and select Operation in verilog Once release a TDS Desktop with a Scenario flow called verilog in ready to convert sio85 ved to a TDS zr nau cana uncyclized binary database V RE SEF Standard Event Format wees 2 enie at tein ede Database Double click on the verilog in Change make signal defn qo YES to tell TDS to open its PropertySheet generate the Signal Definition File auNqmatically E DeskTop temporary scenarie 1 BEEN Properties niveriog t ils rie opem nentes mmeertop mun Hem mm rai L A es TSI 5 6 The Verilog in scenario desktop now should change to output only 1 port which will cut be the Signal Definition File TEE 8 Move the SDF text file icon to the right Run the scenario to generate a list of signals into the SDF text and connect verilog operation upto it file
4. TSSI Test Development Series TDS Product Tutorial Simple Conversion Flows January 2010 Rev2 Test Systems Strategies Inc www tessi com TSI Setup Information This tutorial assumes you have an existing TDS installation and it has been properly licensed If that s not the case please contact your local TSSI representative or email sales tessi com to arrange for an evaluation package Furthermore you should have access to the TDS User Manual comes with the TDS installation for reference Minimum System Requirements Processor All x86 32 bit and x86 64 64 bit processors from Intel and AMD are supported Recommended 3 GHz speed Operating System Linux Redhat 5 x or openSUSE 11 x Memory 2GB recommend 8GB Diskspace 100GB Test case copy tds training product tgz to your working directory eg home mywork ed home mywork tar xvfz tds training product tgz This creates a directory named tds training with all the files referenced in this document Introduction The main component of TDS is the ATE neutral database called WDB Waveform Database which is a binary representation of WGL Waveform Generation Language created by TSSI in the 1980 s It serves as a single standard format that all TDS tools work on as opposed to point to point conversions where many similar conversions are duplicated and hence presents chances for inconsistency TDS pattern conversion methodology co
5. and select Operation Em gt in gt stil Once release a Ss TDS Desktop with a PM cenario flow called stil oom in ready to convert syn0 stil toa TDS binary database WDB and it will have a temporary name Itis recommended that you 7 tate at change it to a more ues meaningful name see Note RUE below E z ees SEE Click on Run Dco o fee gt Scenario to start the iem conversion to a WDB and you ll be ready to following the Bridge process in the later sections Exc 3 Note It s a good practice to rename your WDB before running the scenario for easy reference in the future To do so simply click on the WDB icon ctrl U to clean out the temporary name and type in your new name plus don t forget to hit ENTER to commit to the name change TsSI 3 In Convert EVCD and VCD Files to SEF a In Convert an EVCD File to a TDS SEF Standard Event Format Database SEF is event based rent from WDB in that SEF does not yet have timing and it s dif cd folder to nel Double click on th enter it Pium il L Double click on the eved in scenario to open a pre set scenario Double Click on the verilog in icon to Note that the fFHN XXXX entry It is to map F to X F to X n to X and N to X These are state characters not needed by ATE but commonly found in EVCD files Run the scenario to generate the SEF equivalent of
6. g step above Step 1 In the same scenario EE RTL EEED EL from the previous step select InsertOp gt condition sequencematch i Mat ee tae ay ve TsSI Step 2 Click to place the sequencematch condition icon on to the desktop Now high light the in sef SEF and right click to make a copy into memory Step 3 Right click and select paste Step 4 Click to place a copy of in sef SEF as shown Step 5 A copy of in sef is placed This is the same as the first in sef but it is placed here for easy wiring it up to the sequencematch s wave source wsrc port Step 6 Wire the wat wdb timing WDB to the timing source tsrc port of sequencematch Step 7 Right select sequencematch and do As Needed Step 8 Rename the new WDB as timing pattern wdb Step 9 Run the scenario and it should generate the final timing pattern wdb cyclized database ready for ATE files eration Step 10 Optional but highly recommended save your scenario for future reference Let s save it as cyclization scenario TsSI 5 Out Convert from a WDB to Teradyne UltraFlex When a valid cyclized WDB is obtain whether it was from a WGL STIL VCD EVCD or any other flow it is ready to be converted to a target ATE format Since in the cyclization we ve already targeted the Teradyne Ultraflex via the specification of the shape file in the Waveform Anal
7. nsists of two major steps 1l In Conversion Convert all EDA formats to a WDB 2 Out Conversion From WDB apply writers or Bridges to output target ATE format and design files for re simulation When ready go to your working directory cd home mywork tds training and launch TDS TDSDIR wavemaker_mt amp And follow a flow of your choice below TSI 1 In Convert a WGL File Double click on the E i Lii wgl folder to enter it Bile Hb open Mena Browser zu Click to select the UG GT NE ESESCUES scan07 wgl WGL file Then right click to reveal the drop down menu and Operation gt in gt wgl Once release a TDS Desktop with a Scenario flow called wel et in ready to convert on scan07 wgl to a TDS binary E temporary named cu o VA US tmpfltdswdst 29 Ctick on Run gt Scenario to start the conversion Note It s a good practice to rename your ie es the scenario for easy reference in the future To do so simply click on the WDB icon ctrl U to clean out the temporary name and type in your new name plus don t forget to hit ENTER to commit to the name change TsSI 2 In Convert a STIL File J Double click on the ELLE J il folder to enter it PiE i aa E E E Click to select the kile st wes cmeeftawert gens vieo e Dus syn0 stil file Then right imma click to reveal the drop down menu
8. on edge alignment glitch removal guard banding various conditioning techniques will be necessary to achieve successful and accurate cyclization without violating n and test rules For that please reference TDS Tutorial Advanced Topics for more complicated a Adding Timing A TDS Conditioner called Waveform Analyzer Tool WAT is used Step 1 Highlight and right click on the SEF Step 2 The wat or Waveform Analyzer Tool database that we just in converterd from the condition VCD or EVCD file in sef The menu will scenario desktop will pop up Double click on wat to reveal and we ll select Operation gt condition gt configure its operation wat Tus M a cete quatn De Mae De i tt we gerne Mey Ra Re iiisaacas Tesi Step 3 Change the cycle length to 150ns for Step 4 Right click on the shapes file field to select this test case the UltraFlex which is the target ATE for this test case Then click OK and we re done with timing set up b Adding Pattern For pattern we ll use a TDS conditioner called SequenceMatch In the previous step the wat wdb is the WDB database that will contain the timing extracted from the in sef database SequenceMatch now will apply the WDB timing to the in sef SEF For each timing cycle and waveform SequenceMatch will create a pattern row with the appropriate state for each pin Here s the set up in the same scenario as the Adding Timin
9. timing resolution violations Use default NO TaSi 7 Running and Controlling Scenarios from the Command Line a Invocation All scenarios that have been saved with a name can be invoked from the command line For example in section 3 b we ve created a scenario called my vcd in scenario It can be invoked from the command line as STDSDIR wavemaker mt b my ved in scenario A sample script is available in tds training vcd run evcd sh to show one way to invoke several scenarios to convert an EVCD file to Teradyne UltraFlex format b Setting Changing Scenario PropertySheet Values from the Command Line STDSDIR wavemaker mt b my vcd in scenario lt operation gt n parameterName lt new value lt operarion gt n parameterName lt new value rent cycle length than the 150ns do For example to run the my STDSDIR wavemaker mt b my cyclization scenar c condition cydeLengt 300ns NENNEN cyclization scenario with a di CycleLength is the name of the field inside of the scenario and they re trickier to know the exact name but they are all listed in the TDS User Manual Contact TSSI Email hotline tessi c Phone 1 503 626 8806 Web www tessi com
10. yzer Tool step we ll choose Teradyne Ultraflex here Step 1 Highlight the previous cyelzed WDB Hla Bt Ope ERREA Menon uy pions ne timing pattern wdb then select Operation gt aM ES testerbridge ultarflex Eo pr n pec weattty usa Step 2 When the ultraflex testerbridge scenario f EIE EE pops up select run scenario and the SERRE Iz pem testerbridge will generate Ultraflex tester files in the specifed output directory 6 Out Convert from a WDB to Verigy 93000 files Click to select a WDB Then right click to reveal the drop down menu or identically click on the Operation from the top menu and select Operation gt wavebridge gt agilent93000ait Once release a TDS Desktop with a Scenario flow called agilent93000ait wavebridge ready to convert the selected WDB to Verigy93000 files E Browser File Edit Open Dreate bonvert Operation View Options Tafa Trane olan denos sta condition emate zi dbridge etbridgs E ghridge probebridge testerbridge tock utility vbridge sevebridge arterion catalyst afe duo hp 3000 apsenun 659000 jn s0212 6500 6902 teradyna tintin vista 0000 2 ick on Run Scenario to start the conversion Verigy93000 files will be created in the directory specified by the dir port Default current directory The Verigy93000 files to be created using the name specified by tprg Default
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