ATC-SCC-04 - Alphi Technology
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1. v AS w j foes v Tes Swaswwemus Remi X _ ALPHI TECHNOLOGY CORP Page 10 REV 1 22 Part Number 753 12 000 4000 Copyright 2000 ALPHI Technology Corporation ATC SCC 04 HARDWARE REFERENCE MANUAL 5 ZILOG SCC 285230 The ATC SCC 04 INDUSTRY PACK contains two NMOS Z8530 devices and the following description gives you the features of these Z85230 controllers Each Z8530 device provides two full duplex serial channels for multiprotocol asynchronous and synchronous transmission modes The Z85230 handles asynchronous formats synchronous byte oriented protocols such as IBM Bisync and synchronous bit oriented protocol such as HDLC and IBM SDLC This versatile device supports virtually any serial data transfer application The Z85230 can generate and check CRC codes in any synchronous mode and can be programmed to check data integrity in various modes The device also has facilities for modem control in both channels Each Z85230 channel provides a receiver FIFO of 8 Bytes deep and a transmitter FIFO of 4 byte deep Each Z85230 controller provides an interrupt connected to IRQO and IRQ1 of the INDUSTRY PACK logic interface respectively ALPHI TECHNOLOGY CORP Page 11 REV 1 22 Part Number 753 12 000 4000 Copyright 2000 ALPHI Technology Corporation ATC SCC 04 HARDWARE REFERENCE MANUAL 6 BAUD RATE GENERATOR The 285230 provides a baud rate generator for each channel consisting of one16 bit time constant2. is optional For even parity the parity bit is set when the data bits plus the parity bit contain an even number of 1s For odd parity the parity bit is set when the data bits plus the parity bit contain an odd number of 1s The stop bit s signal s the end of transmit character and provide s a minimum interval between two emission characters The available number of stop bit is one one and a half and two There are four modem control signals associated with the transmitter provided by the Z85230 RTS CTS DTR and D CD When the auto enable function is set for more information refer to the Zilog Z85230 User s manual the RTS ALPHI TECHNOLOGY CORP Page 12 REV 1 22 Part Number 753 12 000 4000 Copyright 2000 ALPHI Technology Corporation ATC SCC 04 HARDWARE REFERENCE MANUAL signal remains low until the transmitter is completely empty and the last stop bit has left the TxD pin The CTS line becomes active when the transmitter is enabled The DCD line becomes active when the receiver is enabled The DTR signal goes low to indicate the terminal ready state and goes high when the transmit is reseted If these control functions are not required these pins can be used as general purpose signals The receive data path provides an error FIFO in parallel with the data FIFO Three error conditions that the receiver checks in asynchronous mode are e Framing error when the data length is too long e Parity error The
3. parity bit disagrees with the programmed sens e Overrun errors When the receive FIFO overflows 6 2 SYNCHRONOUS MODE The synchronous versus asynchronous communication requires a common clock signal reference to both transmitter and receiver This solution eliminates the overhead associated with every character start and stop bits in asynchronous mode and increases the line efficiency In the receiver data path the mode clock must be equal to one that allows higher speed communication links Some applications may encode the clock information on the same line as the data Because of the phase relationship of synchronous data to a clock data is transferred in blocks with no gaps between characters A synchronization pattern 6 bit 8 bit or 16 bit length is normally used to indicate the location of a block transmission For example monosync protocol usually uses 16 as this special character and the SDLC protocol uses the 7E character to mark the beginning and the end of a block of data The Z85230 supports the three following byte oriented protocols monosynchronous bisynchronous and external synchronous The Z85230 offers several options to support synchronous mode including various sync generation and checking CRC generation and checking as well as modem controls and a transmitter to receiver synchronization function In synchronous communication the number of bits per character can be set between five six seven or eight An ad
4. 5230 0 interrupt line is connected to the IRQO and the Z85230 1 interrupt line is connected to the IRQ1 signal on the INDUSTRY PACK logic interface 6 5 28530 REGISTERS ACCESS Two cycles are necessary to address an internal register as the internal Z85230 registers are accessed through an internal pointer register The first cycle is the write pointer operation into the Write Register 0 which selects the internal register The next cycle is the data access operation The following state machine shows the internal register operation The state 0 waits for the pointer writing in the Write Register 0 which selects the internal register selection After the data access read or write cycle the state machine returns to the state 0 waiting for the next pointer writing A minimum time of 500 ns is required between the pointer writing and the data access operation All internal ClO registers including the internal data register are accessed through this method The pointer register is automatically cleared after each following read or write cycle For more details on register programming and 285230 functionalities please refer to the Zilog 785230 User s manual ALPHI TECHNOLOGY CORP Page 16 REV 1 22 Part Number 753 12 000 4000 Copyright 2000 ALPHI Technology Corporation ATC SCC 04 HARDWARE REFERENCE MANUAL 7 ATC SCC 04A CONNECTION The ATC SCC 04A signals of the four RS 232C serial communication channels are present
5. ATC SCC 04 Quad Channel Serial Communication Controller RS 232 422 485 TTL Industry Pack Module REFERENCE MANUAL 773 12 000 4000 Revision 1 2 April 2003 ALPHI TECHNOLOGY CORPORATION 6202 S Maple Avenue 120 Tempe AZ 85283 USA Tel 480 838 2428 Fax 480 838 4477 ATC SCC 04 HARDWARE REFERENCE MANUAL NOTICE The information in this document has been carefully checked and is believed to be entirely reliable While all reasonable efforts to ensure accuracy have been taken in the preparation of this manual ALPHI TECHNOLOGY assumes no responsibility resulting from omissions or errors in this manual or from the use of information contain herein ALPHI TECHNOLOGY reserves the right to make any changes without notice to this or any of ALPHI TECHNOLOGY s products to improve reliability performance function or design ALPHI TECHNOLOGY does not assume any liability arising out of the application or use of any product or circuit described herein nor does ALPHI TECHNOLOGY convey any license under its patent rights or the rights of others ALPHI TECHNOLOGY CORPORATION All Rights Reserved This document shall not be duplicated nor its contents used for any purpose unless express permission has been granted in advance ALPHI TECHNOLOGY CORP Page ii REV 1 22 Part Number 753 12 000 4000 Copyright 2000 ALPHI Technology Corporation ATC SCC 04 HARDWARE REFERENCE MANUAL TABLE OF CONTENTS 1 I
6. NTRODUCTION 4 2 SUMMARY OF FEATURES 5 3 DESCRIPTION 6 3 1 BLOCK DIAGRAM 6 3 2 INDUSTRY PACK SPACES 6 3 3 O SPACE 7 3 4 ID SPACE 8 3 5 WAIT STATE CYCLES 9 4 ATC SCC 04 CHARACTERISTICS 10 5 ZILOG SCC 285230 11 6 BAUD RATE GENERATOR 12 6 1 ASYNCHRONOUS MODE 12 6 2 SYNCHRONOUS MODE 13 6 3 DATA ENCODING 14 6 4 285230 INTERRUPT FUNCTION 14 6 5 28530 REGISTERS ACCESS 16 7 ATC SCC 04A CONNECTION 17 7 1 SCC 04A I O 50 PINCONNECTOR DESCRIPTION 18 8 ATC SCC 04B CONNECTION 19 8 1 SCC 04B I O 50 PIN CONNECTOR DESCRIPTION 20 9 ATC SCC 04 TTL CONNECTION 21 9 1 CLOCK SOURCES 21 9 2 04 I O 50 PIN CONNECTOR DESCRIPTION 23 10 ADENDUM TO MANUAL 24 ALPHI TECHNOLOGY CORP Page iii REV 1 22 Part Number 753 12 000 4000 Copyright 2000 ALPHI Technology Corporation ATC SCC 04 HARDWARE REFERENCE MANUAL 1 INTRODUCTION The ATC ATC SCC 04 module from ALPHI TECHNOLOGY is a Serial Communication Controller based on the Zilog 85230 SCC and is implemented on a single wide Industry Pack according to the INDUSTRY PACK VITA 4 specification Two types are available Reference Description ATC SCC 04A Four RS 232C serial channels ATC SCC 04B Four RS 422 RS 485 serial channels ATC SCC 04 ttl Four ttl level serial channels 20 to 85 temperature grade version is available as a opt ATC SCC 04 Industry Pack provides four asychronous or synchronous full duplex serial channels with an seperate baud rate generator for each cha
7. ditional odd or even parity bit can be carried for each transmit character Typically the parity bit is not used in synchronous applications because the CRC provides a more reliable method for detecting errors Either the CRC 16 polynomial or the CRC CCITT polynomial may be used to check the data integrity The modem control signals RTS and in synchronous transmission are used as simple I O pin Note On the ATC SCC 04B the RTS signal controls the output enable driver of the RS 422 RS 485 serial interface In this way before each transmission the RTS signal must be set to low and automatically return to the high state at the end of the complete block transmission to insure no collision ALPHI TECHNOLOGY CORP Page 13 REV 1 22 Part Number 753 12 000 4000 Copyright 2000 ALPHI Technology Corporation ATC SCC 04 HARDWARE REFERENCE MANUAL In bit oriented protocol Synchronous Data Link Control mode SDLC the synchronization character is similar to bisync and monosync modes High level Data Link Control HDLC is defined as CCITT also EIAJ standards SDLC is one of the implementation made by IBM Frames of information are enclosed by a unique bit pattern called a flag usually equal at 7E The basic format of an SDLC HDLC frame is described as following e 8 bit flag character 7E to mark the frame beginning e 8 bit address field it is used to designed receiving stations e A 8 bit control field
8. e The data information field e A 16 bit frame checking field in SDLC mode only the CRC CCITT is used e 8 bit flag character 7E to mark the frame ending 6 3 DATA ENCODING Four data encoding capabilities are provided by the Z85230 to allow the transmit of the data information and the clock transmission one the same line NRZ Non Return to Zero encoding a 1 is represented by a high level and a 0 is represented by a low level e NRZI Non Return to Zero Inverted encoding a 1 is represented by no change in the level and a 0 is represented by a change in the level e FM1 biphase mark a transition is present on every transmit bit encoding a 1 is represented by an additional transition presents in the bit middle the 0 state contains no transition in the bit middle The FM1 encoded data contains sufficient information to recover a clock from the data e FMO biphase space the encoding method is the same that FM1 but the 1 is represented such as a 0 in FM1 encoding also the 0 level is encoded such as the 1 in FM1 Each Z85230 channel contains a Digital Phase Locked Loop DPLL that can be used to recover the clock information from the received data with NRZ NRZI FM1 and FMO encoding 6 4 Z85230 INTERRUPT FUNCTION The Z85230 operations must be controlled by polling or interrupt modes In polling mode the 785230 transmitter receiver status is show by a continuous reading into the 785230 status registers for more i
9. e show each condition CONTROL REGISTER Read Write Address 10 with Alphi DSP carrier and 40 with slave carrier IPCLK REGISTER 10 85230 PCLK CONDITION WRITE INPUT 8Mhz 4Mhz 32Mhz 16Mhz RD WR 60ns ALPHI TECHNOLOGY CORP Page 24 REV 1 22 Part Number 753 12 000 4000 Copyright 2000 ALPHI Technology Corporation
10. er module RJ45Q from ALPHI TECHNOLOGY is also available for an easily user connection 9 1 CLOCK SOURCES ALPHI TECHNOLOGY CORP Page 21 REV 1 22 Part Number 753 12 000 4000 Copyright 2000 ALPHI Technology Corporation ATC SCC 04 HARDWARE REFERENCE MANUAL J1 J2 J3 J4 Clock source for RTxC e Pin 1 to 2 jumpered is for external clock on P2 e Pin 2 to 3 jumpered Internal clock J5 Clock source for TRxC e Pin 1 to 2 jumpered is for input clock e Pin 2 to 3 jumpered is for output clock ALPHI TECHNOLOGY CORP Page 22 REV 1 22 Part Number 753 12 000 4000 Copyright 2000 ALPHI Technology Corporation ATC SCC 04 HARDWARE REFERENCE MANUAL 9 2 SCC 04TTL O 50 PIN CONNECTOR DESCRIPTION PIN SIGNAL PIN SIGNAL 5 8 e pa je sme m ere a C x i 13 GND 38 GND NC No Connect ALPHI TECHNOLOGY CORP Page 23 REV 1 22 Part Number 753 12 000 4000 Copyright 2000 ALPHI Technology Corporation ATC SCC 04 HARDWARE REFERENCE MANUAL 10 ADENDUM TO MANUAL This product has been modified in the Altera code to work with an IP CLK of 8Mhz or 32Mhz by adding a control register accessed on the I O space address 10 of DSP carrier or 40 of a slave carrier board The register controls the clock speed of the 85230 on board The 85230 s are either 16Mhz or 20Mhz so they can only run at 8Mhz or 16Mhz there is a 32Mhz condition with this register that cannot be used A table below w
11. le type byte ATC SCC 04A ATC SCC 04B ATC SCC 04 ttl 09 ALPHI TECHNOLOGY CORP Page 8 REV 1 22 Part Number 753 12 000 4000 Copyright 2000 ALPHI Technology Corporation ATC SCC 04 HARDWARE REFERENCE MANUAL The next byte identifies the INDUSTRY PACK revision in accordance with the following definition Revision ASCII char hex value NI UL The byte 0F is reserved for future extension The bytes 11 and 13 allow the identification of the INDUSTRY PACK software driver The number of bytes used in the identification space is stored at address 15 To verify the identification data integrity the byte 17 contains a 8 bit Checksum CRC This CRC covers only the number of identification codes set by the manufacturer The CRC used is an industry standard It s the low 8 bit of the FCS as described in CCITT T 30 Fascicle VII 3 section 5 3 7 The next bytes 19 to 3F are free for user data storage 3 5 WAIT STATE CYCLES The following table gives the number of wait states asserted in each INDUSTRY PACKs space Wait state Wait state Read Identification Interrupt ack ALPHI TECHNOLOGY CORP Page 9 REV 1 22 Part Number 753 12 000 4000 Copyright 2000 ALPHI Technology Corporation ATC SCC 04 HARDWARE REFERENCE MANUAL 4 ATC SCC 04 CHARACTERISTICS Symbol Parameters Test Unit eR 21720 Baud C E Baur Www m LN ea OE MOS
12. nformation refer to the Zilog 285230 User s maual The interrupt mode reduces the CPU overhead system Three 785230 sources can generate an interrupt request the receiver the ALPHI TECHNOLOGY CORP Page 14 REV 1 22 Part Number 753 12 000 4000 Copyright 2000 ALPHI Technology Corporation ATC SCC 04 HARDWARE REFERENCE MANUAL transmitter and the external status this makes a total of six Z85230 interrupt sources total of twelve interrupt sources into the ATC SCC 04 module The 285230 is very flexible for interrupt acknowledge method it supports vectorized or non vectorized cycle The following table gives the several 785230 interrupt sources Interrupt source Condition Character available Receiver Framing error End of frame SDLC DCD CTS Tx underrun EOM Channel A or C has a higher priority than channel B or D with the six interrupt sources This source priority is showed in the following table Priority level Interrupt source Highest Receive channel A or C Transmit channel A OOO rela chanel AoC 0 0 ALPHI TECHNOLOGY CORP Page 15 REV 1 22 Part Number 753 12 000 4000 Copyright 2000 ALPHI Technology Corporation ATC SCC 04 HARDWARE REFERENCE MANUAL The hardware daisy chain operation is not implemented because each ClOcontroller has its own interrupt request line into the INDUSTRY PACK logic interface In the ATC SCC 04 module the 28
13. nnel An on board non volatile EEPROM maintains ATC SCC 04 identification codes and provides additional user space ALPHI TECHNOLOGY CORP Page 4 REV 1 22 Part Number 753 12 000 4000 Copyright 2000 ALPHI Technology Corporation ATC SCC 04 HARDWARE REFERENCE MANUAL 2 SUMMARY OF FEATURES e Single size INDUSTRY PACK module e Four asynchronous and synchronous full duplex serial channels e Fully compatible with the VITA 4 INDUSTRY PACK specification e RS 232 interface ATC SCC 04A e RS 422 485 interface ATC SCC 04B e TTL interface ATC SCC ttl e 4 Byte transmitter FIFO and the 8 Byte receiver FIFO e Status FIFO anti lock feature in DMA driven system e Separate baud rate generator for each channel e Data rate up to 115 kbaud in async mode 2 Mbaud in synchronous mode e Supports multi drop 2 wire configuration ATC SCC 04B with driver output enable through RTS signal e Zilog SCC 285230 controller e 5V only power supply e Extended temperature grade available 40 to 85 C ALPHI TECHNOLOGY CORP Page 5 REV 1 22 Part Number 753 12 000 4000 Copyright 2000 ALPHI Technology Corporation ATC SCC 04 HARDWARE REFERENCE MANUAL 3 DESCRIPTION The ATC SCC 04 is based on the Serial Communication Controller SCC 285230 from Zilog Each 285230 provides two full duplex ports for asynchronous and synchronous communication The transmitter has an 8 bit transmit data register loaded from the internal data b
14. on the 50 pin INDUSTRY PACK I O connector The power supply 5V is also provided for external signal conditioning and it s short circuit protected from ATC SCC 04A revision A module Signals Description TxD Transmit Data RTS Request To Send CTS Clear To Send DTR Data Set Ready DCD Data Carrier Detect VDD 5V500 mA max Fuse protected on xO sw This connection is compatible with the I O connection standard on the 50 pin INDUSTRY PACK I O connector defined by ALPHI TECHNOLOGY An adaptor module RJ45Q from ALPHI TECHNOLOGY is also available for an easily user connection It provides four RJ 45 connectors and measures 3HE x 4 on front panel ALPHI TECHNOLOGY CORP Page 17 REV 1 22 Part Number 753 12 000 4000 Copyright 2000 ALPHI Technology Corporation ATC SCC 04 HARDWARE REFERENCE MANUAL 7 1 SCC 04A 50 PIN CONNECTOR DESCRIPTION PIN SIGNAL PIN SIGNAL 5 ic we e wo TXDA 34 ome js 5 7 15 RTSD a g Note NC No Connect VDD 5 volt Fused ALPHI TECHNOLOGY CORP Page 18 REV 1 22 Part Number 753 12 000 4000 Copyright 2000 ALPHI Technology Corporation ATC SCC 04 HARDWARE REFERENCE MANUAL 8 ATC SCC 04B CONNECTION The ATC SCC 04B C differential signals of the four RS 422 RS 485 serial communication channels are present on the 50 pin INDUSTRY PACK connector The power supply 5V is also provided for external signal conditi
15. oning and it s short circuit protected from ATC SCC 04B C revision A module Signals Description V 5V 500mA Fuse protected DD This connection is compatible with the I O connection standard on the 50 pin INDUSTRY PACK I O connector defined by ALPHI TECHNOLOGY An adapter module RJ45Q from ALPHI TECHNOLOGY is also available for an easily user connection ALPHI TECHNOLOGY CORP Page 19 REV 1 22 Part Number 753 12 000 4000 Copyright 2000 ALPHI Technology Corporation ATC SCC 04 HARDWARE REFERENCE MANUAL 8 1 SCC 04B 50 PIN CONNECTOR DESCRIPTION PIN SIGNAL PIN SIGNAL kam TXDA 29 RXDC s moe s Tc NC 33 TXCC s pow s 10 35 RXCC 5 7 15 TXDD 16 RXDD 18 RXDB NC s a Note NC No Connect 5VF 5 volt Fused ALPHI TECHNOLOGY CORP Page 20 REV 1 22 Part Number 753 12 000 4000 Copyright 2000 ALPHI Technology Corporation ATC SCC 04 HARDWARE REFERENCE MANUAL 9 ATC SCC 04 TTL CONNECTION The ATC SCC 04 ttl ttl buffered signals The power supply 5V is also provided for external signal conditioning and it s short circuit protected Signals Description Transmit Data RD Receive Data Receive Clock Request to send Clear to send Data set ready DCD Data carrier detect 45V 500Ma fused This connection is compatible with the I O connection standard on the 50 pin INDUSTRY PACK I O connector defined by ALPHI TECHNOLOGY An adapt
16. register a 16 bit down counter and a flip flop on the output that makes the output a square wave The down counter clock is divided by the clock mode value and the clock mode source allows to select the master clock between the system clock PCLK and the input pin RTxC On startup the value in the time constant register is loaded into the counter and the counter begins counting down When a count of zero is reached the output of the baud rate generator toggles the time constant value is loaded into the counter and the process repeats In asynchrounous mode two clock sources are available PCLK pin 8 MHz with clock mode equal to 16 32 or 64 or RTxC pin 2 4576 MHz with clock mode equal to 1 In synchronous mode ATC SCC 04B and ATC SCC 04C modules RTxC pin Receive clock line is the clock source the clock mode selection is always equal to 1 The mode clock value representes the frequency ratio between the data rate output and the frequency sample of the received character The following formula allows to define the desired baud rate output 61 ASYNCHRONOUS MODE In this transmission mode an asynchronous message format is defined as follows Astart bit e The data field e The parity bit e Stop bit s The start bit indicates the beginning of the character transmission The data field contains the character to be transmited and the number of bits per character can be set from 5 to 8 The parity bit generation and checking
17. ss of these spaces depends on the specific INDUSTRY PACK carrier used ALPHI TECHNOLOGY CORP Page 6 REV 1 22 Part Number 753 12 000 4000 Copyright 2000 ALPHI Technology Corporation ATC SCC 04 HARDWARE REFERENCE MANUAL 3 3 I O SPACE The two Z85230 controllers are mapped into the INDUSTRY PACK I O space Data and command registers of the 785230 controllers are placed on 8 consecutive addresses 8 bit data path DSP Carrier Register Description space addr CBCR Channel B Command Register D 0009 Ghana Command 7 ERE Slave Carrier Register Description space addr Z85230 0 controller 1 0 Command Rear si ALPHI TECHNOLOGY CORP Page 7 REV 1 22 Part Number 753 12 000 4000 Copyright 2000 ALPHI Technology Corporation ATC SCC 04 HARDWARE REFERENCE MANUAL All port configurations are defined with the Z85230 control registers The data registers allow the transmit receive data of each channels to be accessed directly 3 4 ID SPACE The identification space is defined as follows ID space addr Description value ww 0D Revision module 0 00 17 The four first bytes contain the ASCII text IPAC This clearly identifies the ROM beginning The manufacturer code identifies ALPHI TECHNOLOGY INDUSTRY PACKs The ATC SCC 04 device is defined as follows by the module type byte Module Modu
18. us and a shift register loaded from the transmit data register The receiver has a 4 8 Byte data FIFO with an 8 bit error FIFO and a 8 bit shift register This arrangement reduces CPU time overhead The 285230 interrupt structure supports vectorized or vectorized interrupts The ATC SCC 04A module provides superior performance for multiple serial channels Data transmission and reception are performed independently on each channel with five to eight data bits per character plus optional even or odd parity The transmitter can supply one one and a half or two stop bits per character The full modem control signals of the four independent channels are available on the 50 pin INDUSTRY PACK connector The ATC SCC 04B module provides four RS 422 485 channels It is especially oriented for high speed synchronous communications and allows the connection of up 32 transmitters and receivers to a single multi drop bus 2 wire 3 1 BLOCK DIAGRAM There are four basic section to the ATC SCC 04 e The INDUSTRY PACK bus interface e The Z85230 controllers e The serial communication physical interface RS 232C for the ATC SCC 04A or RS 422 RS 485 for the ATC SCC 04B ATC SCC 04 ttl e The 2 kByte of non volatile memory 3 2 INDUSTRY PACK SPACES The following table gives the four ATC SCC 04 memory spaces ID space INDUSTRY PACK identification codes e O space ClO controllers access e INT Ack Interrupt acknowledge The base addre
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