ADSP-216x Data Sheet
Contents
1. 13 ABSOLUTE MAXIMUM RATINGS 13 SPECIFICATIONS SUPPLY CURRENT AND POWER 5 2161 5 2163 8 2165 14 POWER DISSIPATION EXAMPLE 15 ENVIRONMENTAL CONDITIONS 15 CAPACITIVE LOADING 15 SPECIFICATIONS ADSP 2161 ADSP 2163 ADSP 2165 16 TEST CONDITIONS 16 Output Disable 16 Output Enable Time 16 SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS ADSP 2162 ADSP 2164 ADSP 2166 17 ELECTRICAL CHARACTERISTICS 17 ABSOLUTE MAXIMUM RATINGS 17 SPECIFICATIONS SUPPLY CURRENT AND POWER ADSP 2162 ADSP 2164 ADSP 2166 18 POWER DISSIPATION EXAMPLE 19 ENVIRONMENTAL CONDITIONS 19 CAPACITIVE LOADING 19 TEST CONDITIONS 20 Output Disable 20 Output Enable Time 20 TIMING PARAMETERS ADSP 2161 ADSP 2163 ADSP 2165 21 GENERAL NOTES 21 TIMING NOTES 4 21 MEMORY REQUIREMENTS 21 CLOCK SIGNALS AND RESET 22 INTERRUPTS AND FLAGS 23 BUS REQUEST BUS GRANT 24 M2. 60 ns 27 mA Ipp Supply Current Idle 2 Vpp max tcx 40 ns 12 mA Vpp max tcx 50 ns 11 mA Vpp max tcx 60 ns 10 mA NOTES Current reflects device operating with no output loads Vin 0 4 V and 2 4 V 3Idle refers to ADSP 21xx state of operation during execution of IDLE instruction Deasserted pins are driven to either V pp or GND For typical supply current internal power dissipation figures see Figure 9 Specifications subject to change without notice POWER mW IDD DYNAMIC 220 200 180 z 160 0 140 Q120 100 80 60 10 00 13 83 20 00 25 00 30 00 FREQUENCY MHz IDD IDLE IDD IDLE n MODES 65 60 55 50 45 POWER mW 40 35 0 30 10 00 13 83 20 00 25 00 30 00 10 00 13 83 20 00 25 00 30 00 FREQUENCY MHz FREQUENCY MHz VALID FOR ALL TEMPERATURE GRADES 1POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS 2IDLE REFERS TO ADSP 216x OPERATION DURING EXECUTION OF IDLE INSTRUCTION DEASSERTED PINS ARE DRIVEN TO EITHER Vpp OR GND 3MAXIMUM POWER DISSIPATION AT Vpp 5 5V DURING EXECUTION OF DLE n INSTRUCTION Figure 9 ADSP 2161 ADSP 2163 ADSP 2165 Typical vs Frequency 14 REV 0 ADSP 216x ADSP 2161 ADSP 2163 ADSP 2165 POWER DISSIPATION EXAMPLE To determine total power dissipation in a specific application the following e
3. cond SR SR OR LSHIFT Logical Shift SR SR OR ASHIFT BY lt exp gt Arithmetic Shift Immediate SR SR OR LSHIFT BY exp Logical Shift Immediate Conditional MR Saturation IF cond SE EXP xop Derive Exponent cond SB EXPADJ Block Exponent Adjust IF cond SR SR OR NORM Normalize Data Move Instructions reg Register to Register Move reg lt data gt Load Register Immediate reg DM lt addr gt dreg DM Ix dreg PM Ix DM lt addr gt reg DM Ix My dreg PM x My dreg Multifunction Instructions lt gt MAC lt 5 gt dreg dreg Data Memory Read Direct Address Data Memory Read Indirect Address Program Memory Read Indirect Address Data Memory Write Direct Address Data Memory Write Indirect Address Program Memory Write Indirect Address Computation with Register to Register Move lt ALU gt lt MAC gt lt SHIFT gt dreg DM lt ALU gt lt MAC gt lt SHIFT gt dreg PM DM 1 My dreg lt ALU gt lt MAC gt lt SHIFT gt PM Ix My dreg lt ALU gt lt MAC gt lt SHIFT gt dreg DM Ix My dreg PM Ix My lt ALU gt lt MAC gt dreg DM dreg PM Ix REV 0 Computation with Memory Read Computation with Memory Read Computation with Memory Write Computation with Memory Wri
4. ADSP 216x TIMING PARAMETERS ADSP 2162 ADSP 2164 ADSP 2166 SERIAL PORTS 10 24 MHz 13 0 MHz 13 824 MHz Frequency Dependency Parameter Min Max Min Max Min Max Min Max Unit Timing Requirements tsex 5 Period 97 6 76 9 72 31 tex ns tses DR TFS RFS Setup Before SCLK Low 8 8 8 8 ns DR TFS RFS Hold After SCLK Low 10 10 10 10 ns tscp SCLKyy Width 28 28 28 28 ns Switching Characteristics tcc CLKOUT High to 24 4 39 4 19 2 34 2 18 1 33 1 0 25 0 251 15 ns SCLK High to DT Enable 0 0 0 0 ns tscpy SCLK High to DT Valid 28 20 20 20 ns TFS RFSour Hold After SCLK High 0 0 0 0 ns trp 5 5 Delay from SCLK High 282 20 20 202 ns tscpu DT Hold After High 0 0 0 0 ns trog TFS Alt to DT Enable 0 0 0 0 ns trov TFS Alt to DT Valid 18 18 18 18 ns tscpp SCLK High to DT Disable 30 25 25 25 ns trov RFS Multichannel Frame 20 Delay Zero to DT Valid 20 20 20 20 ns NOTES 1Maximum serial port operating frequency is 13 824 MHz for all processor speed grades faster then 13 824 MHz For 10 24 MHz only the maximum frequency dependency for tgcpy 28 ns tgp 28 ns tgcpp 30 ns CLKOUT SCLK DR TFSiN RFSin RFSout TFSout DT TFS ALTERNATE FRAME MODE RFS MULTICHANNEL MODE 5 me trp l ISCDV gt FRAME DELAY 0 0 Figure 32 Serial Ports 34 R
5. tsp High to DMS PMS BMS RD WR Disable 44 4 39 2 35 0 0 251 20 ns tsps DMS PMS BMS RD WR Disable to BG Low 0 0 0 0 ns tss BG High to DMS PMS BMS RD WR Enable 0 0 0 0 ns DMS PMS BMS RD WR Enable to CLKOUT High 14 4 9 2 5 0 0 251 10 ns NOTES Tf BR meets the tgs and tgg setup hold requirements it will be recognized in the current processor cycle otherwise it is recognized in the following cycle BR requires a pulsewidth greater than 10 ns Section 10 2 4 Bus Request Grant of the ADSP 2100 Family User s Manual Third Edition states that When BR is recognized the processor responds immedi ately by asserting BG during the same cycle This is incorrect for the current versions of all ADSP 21xx processors BG is asserted in the cycle after BR is recognized No external synchronization circuit is needed when BR is generated as an asynchronous signal teH CLKOUT 7 R tsp gt tsec Figure 29 Bus Request Grant REV 0 31 ADSP 216x TIMING PARAMETERS ADSP 2162 ADSP 2164 ADSP 2166 MEMORY READ 10 24 MHz 13 0 MHz 16 67 MHz Frequency Dependency Parameter Min Max Max Min Max Min Max Unit Timing Requirements troo RD Low to Data Valid 33 8 23 5 15 O tck 15 w ns A0 A13 PMS DMS BMS to Data Valid ae 49 2 33 7 21 0 75tck 24 w ns Data Hold from RD High 0 0 0 0 ns Switching Character
6. www analog com Fax 781 326 8703 Analog Devices Inc 1999 ADSP 216x TABLE OF CONTENTS SUMMARY 5 es sape tee eee HOS 1 FEATURES i389 Sean be MALE ee 1 GENERAL DESCRIPTION 1 Development Tools 3 Additional Information 3 ARCHITECTURE OVERVIEW 3 Serial Ports bmx 4 Interrupts o e pe Cen TERR TA ERG 5 SYSTEM INTERFACE 5 Glock Sienals Rex rex Woe kr RR ER 5 Reset 22525 Dem eR epa eerte aie RO Bee geass 6 PIN FUNCTION DESCRIPTIONS 6 Program Memory Interface 7 Program Memory 7 Data Memory Interface 8 Data Memory Map 8 Bus Interface eese cock duet Gr eret me eee wears 9 POWER DOWNE aha HERE VT Rte 9 Power Down Control 9 Entering Power Down 9 Exiting Power Down 10 Low Power IDLE Instruction 10 ADSP 216x Prototyping 10 Ordering Procedure for ADSP 216x ROM Processors 10 Instruction Sets LA RR ea oe AE 11 SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS 5 2161 8 2163 8 2165 13 ELECTRICAL CHARACTERISTICS
7. 24 MHz 13 0 MHz 16 67 MHz Dependency Parameter Min Max Min Max Min Max Min Max Unit Timing Requirements trs IRQx or FI Setup Before CLKOUT Low 3 44 4 39 2 35 0 0 251 20 ns tru IRQx or FI Hold After CLKOUT High 24 4 19 2 15 0 0 25tck ns Switching Characteristics trop FO Hold After CLKOUT High 0 0 0 0 ns trop FO Delay from CLKOUT High 15 15 15 15 ns NOTES IRQO IRQI and IRQ2 If IRQx and FI inputs meet and setup hold requirements they will be recognized during the current clock cycle otherwise they will be recognized during the following cycle Refer to the Interrupt Controller section in Chapter 3 Program Control of the ADSP 2100 Family User s Manual Third Edition for further information on interrupt servicing 3Edge sensitive interrupts require pulse widths greater than 10 ns Level sensitive interrupts must be held low until serviced CLKOUT V a trop trou FLAG OUTPUT S 4 tr IROx FI 4 lirs Figure 28 Interrupts and Flags 30 REV 0 ADSP 216x TIMING PARAMETERS ADSP 2162 ADSP 2164 ADSP 2166 BUS REQUEST BUS GRANT 10 24 MHz 13 0 MHz 16 67 MHz Frequency Dependency Parameter Min Max Min Max Min Max Min Max Unit Timing Requirements BR Hold After CLKOUT High 29 4 24 2 20 0 0 251 5 0 tps BR Setup Before CLKOUT Low 44 4 39 2 35 0 0 251 20 ns Switching Characteristics
8. 80 ADSP 2163KP 100 0 C to 70 25 68 Lead PLCC P 68A ADSP 2163BP 100 409 to 85 25 68 Lead PLCC P 68A ADSP 2163KS 100 0 C to 70 C 25 80 Lead 5 80 ADSP 2163BS 100 409 to 85 25 80 Lead MQFP S 80 ADSP 2164KP 40 3 3 0 C to 70 C 10 24 68 Lead PLCC P 68A ADSP 2164BP 40 3 3 409 to 85 C 10 24 68 Lead PLCC P 68A ADSP 2164KS 40 3 3 0 C to 70 C 10 24 80 Lead MQFP S 80 ADSP 2164BS 40 3 3 V 40 C to 85 C 10 24 80 Lead MQFP S 80 ADSP 2165KS 80 0 C to 70 20 00 80 Lead MQFP S 80 ADSP 2165KS 100 0 C to 70 25 00 80 Lead MQFP S 80 ADSP 2165BS 80 409 to 85 20 00 80 Lead MQFP S 80 ADSP 2165BS 100 409 to 85 25 00 80 Lead MQFP S 80 ADSP 2166KS 52 3 3 V 0 C to 70 C 13 00 80 Lead MQFP 5 80 ADSP 2166KS 66 3 3 V 0 C to 70 C 16 67 80 Lead MQFP S 80 ADSP 2166BS 52 3 3 V 40 to 85 C 13 00 80 Lead MQFP 5 80 ADSP 2166BS 66 3 3 V 409 to 85 C 16 67 80 Lead MQFP S 80 NOTES IK B Commercial Temperature Range 0 C to 70 C Industrial Temperature Range 40 C to 85 C C3511 3 10 99 P PLCC Plastic Leaded Chip Carrier S Plastic Quad Flatpack Minimum order quantities required Contact factory for further information Refer to the section titled Ordering Procedure for ROM Coded ADSP 216x Processors for information about ROM coded parts REV 0 39 PRINTED IN U S A
9. ADSP 2100 Family User s Manual Third Edition states that When BR is recognized the processor responds immediately by asserting BG during the same cycle This is incorrect for the current versions of all ADSP 21xx processors BG is asserted in the cycle after BR is recognized No external synchronization circuit is needed when BR is generated as an asynchronous signal CLKOUT teH tsec Figure 23 Bus Request Bus Grant 24 REV 0 ADSP 216x TIMING PARAMETERS ADSP 2161 ADSP 2163 ADSP 2165 MEMORY READ 16 67 MHz 20 MHz 25 MHz Parameter Min Max Min Max Min Max Unit Timing Requirements RD Low to Data Valid 17 12 7 ns 0 13 PMS DMS BMS to Data Valid 27 19 5 12 ns troy Data Hold from RD High 0 0 0 ns Switching Characteristics trp RD Pulsewidth 22 17 12 ns CLKOUT High to RD Low 10 25 7 5 22 5 5 20 ns tASR 0 13 PMS DMS BMS Setup Before RD Low 5 2 5 1 5 ns tRDA 0 13 PMS DMS BMS Hold After RD Deasserted 6 3 5 1 ns tRWR RD High to RD or WR Low 25 20 15 ns Frequency Dependency CLKIN lt 25 MHz Parameter Min Max Unit Timing Requirements RD Low to Data Valid 0 5 13 w ns 0 13 PMS DMS BMS to Data Valid 0 75 18 w ns Data Hold from RD High 0 Switching Characteristics tgp RD Pulsewidth 0 5 8 w ns tcgp CLKOUT High to RD Low 0 251 5 0 25tcy 10 ns TASR A0 A13 PMS DMS BMS Setup B
10. After this information is received it is entered into Analog Devices ROM Manager System which assigns a custom ROM model number to the product This model number will be branded on all prototype and production units manufactured to these specifications To minimize the risk of code being altered during this process Analog Devices verifies that the EXE files on both floppy disks are identical and recalculates the checksums for the EXE file entered into the ROM Manager System The checksum data in the form of a ROM Memory Map a hard copy of the EXE file and a ROM Data Verification form are returned to you for inspection A signed ROM Verification Form and a purchase order for production units are required prior to any product being manu factured Prototype units may be applied toward the minimum order quantity Upon completion of prototype manufacture Analog Devices will ship prototype units and a delivery schedule update for production units An invoice against your purchase order for the NRE charges is issued at this time There is a charge for each ROM mask generated and a mini mum order quantity Consult your sales representative for de tails A separate order must be placed for parts of a specific package type temperature range and speed grade REV 0 ADSP 216x Instruction Set parallelism There are five basic categories of instructions data The ADSP 216x assembly language uses an algebraic syntax for move inst
11. L L put p P proximated by the following equation CrLx0 5V 11 tDECAY from which tprs MEASURED is calculated If multiple pins such as the data bus are disabled the measurement value is that of the last pin to stop driving 16 Output Enable Time Output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driving The output enable time is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point as shown in Figure 13 If multiple pins such as the data bus are enabled the measurement value is that of the first pin to start driving REFERENCE SIGNAL Vou MEASURED Vou MEASURED MEASURED 0 5V 20V OUTPUT Vo MEASURED 0 5V VoL t VoL MEASURED DEGAY MEASURED OUTPUT STOPS OUTPUT STARTS DRIVING DRIVING HIGH IMPEDANCE STATE TEST CONDITIONS CAUSE THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1 5V Figure 13 Output Enable Disable loL TO OUTPUT 1 5V 50pF loH Figure 14 Equivalent Device Loading for AC Measurements Except Output Enable Disable REV 0 ADSP 216x ADSP 2162 ADSP 2164 ADSP 2166 RECOMMENDED OPERATING CONDITIONS K Grade B Grade Parameter Min Max Min Max Unit Vpp Supply Voltage 3 00 3 60 3 00 3 60 V Tams Ambient Operating Temperature
12. Low 0 251 5 0 25tcy 10 ns taw 0 13 DMS PMS Setup Before WR Deasserted 0 75tck 22 w ns 0 13 DMS PMS Hold After WR Deasserted 0 25tck 9 ns twwR WR High to RD or WR Low 0 5tck 5 ns NOTES For 25 MHz only the minimum frequency dependency formula for t asw and tppg 0 25tcy 8 5 w wait states X tox Figure 25 Memory Write 26 REV 0 ADSP 216x TIMING PARAMETERS ADSP 2161 ADSP 2163 ADSP 2165 SERIAL PORTS 13 824 MHz Frequency Dependency Parameter Min Max Min Max Unit Timing Requirements tsck SCLK Period 72 3 72 3 ns tscs DR TFS RFS Setup Before SCLK Low 8 8 ns tscH DR TFS RFS Hold After SCLK Low 10 10 ns tscp SCLKyy Width 28 28 ns Switching Characteristics tec CLKOUT High to SCLKoyr 18 1 33 1 0 25tcK 0 25tck 15 ns tscpE SCLK High to DT Enable 0 0 ns tscpv SCLK High to DT Valid 20 20 ns TFS RFSour Hold After SCLK High 0 0 ns trp TFS RFSour Delay from SCLK High 20 20 ns tscbH DT Hold After SCLK High 0 0 ns trpE TFS Alt to DT Enable 0 0 ns trpv TES Alt to DT Valid 18 18 ns tscpp SCLK High to DT Disable 25 25 ns RFS Multichannel Frame Delay Zero 20 20 ns to DT Valid Maximum serial port operating frequency is 13 824 MHz for all processor speed grades CLKOUT tsck SCLK DR TFSiN RFSiN e trp RFSour TFSout gt tscpe DT TFS ALTERNATE FRAME MODE trov gt RFS MULTIC
13. VIEW PINS UP ADSP 216x OUTLINE DIMENSIONS ADSP 216x 80 Lead Plastic Quad Flatpack MQFP SEATING PLANE 0 134 3 40 MAX 0 010 0 25 gt MIN 0 120 3 05 0 100 2 55 0 690 17 45 0 667 16 95 0 555 14 10 0 547 13 90 pm 0 486 12 35 BSC 80 61 4 1 60 LI cU o Dan 2 5 5 5 lt TOP VIEW PINS DOWN N in ojt 9 o doe 255515 20 41 Y 21 40 gt 4 4 0 026 0 65 0 014 0 35 BSC 0 010 0 25 THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0 0047 0 12 FROM ITS IDEAL POSITION WHEN MEASURED IN THE LATERAL DIRECTION 38 REV 0 ADSP 216x ORDERING GUIDE Ambient Temperature Instruction Package Package Part Number Range Rate MHz Description Option ADSP 2161KP 66 0 C to 70 C 16 67 68 Lead PLCC P 68A ADSP 2161BP 66 409 to 85 16 67 68 Lead PLCC P 68A ADSP 2161KS 66 0 C to 70 16 67 80 Lead MQFP S 80 ADSP 2161BS 66 409 to 85 16 67 80 Lead MQFP S 80 ADSP 2162KP 40 3 3 0 C to 70 10 24 68 Lead PLCC P 68A ADSP 2162BP 40 3 3 40 to 85 C 10 24 68 Lead PLCC P 68A ADSP 2162KS 40 3 3 V 0 C to 70 C 10 24 80 Lead MQFP S 80 ADSP 2163KP 66 0 C to 70 16 67 68 Lead PLCC P 68A ADSP 2163BP 66 409 to 85 16 67 68 Lead PLCC P 68A ADSP 2163KS 66 0 C to 70 16 67 80 Lead MQFP S 80 ADSP 2163BS 66 409 to 85 16 67 80 Lead MQFP S
14. Voltage Vpp min Io 2 mA 0 4 V Im Hi Level Input Current Vpp max Vpp max 10 In Lo Level Input Current Vpp max Vin 0V 10 Three State Leakage Current Vpp max Vpp max 10 Three State Leakage Current Vpp max Vin 0 V 10 Input Pin Capacitance 6 9 Vin 2 5 V fin 1 0 MHz Tams 25 8 pF Co Output Pin Capacitance 10 Vin 2 5 V fin 1 0 MHz Tams 25 C 8 pF NOTES Bidirectional pins 20 023 SCLK1 RFS1 TFS1 SCLK0 RFSO 50 Input only pins RESET IRQ2 BR DRI DRO Input only pins CLKIN RESET IRQ2 BR MMAP DRI DRO Output pins BG PMS DMS BMS RD WR A0 A13 CLKOUT DTI Although specified for TTL outputs all ADSP 21xx outputs are CMOS compatible and will drive to V and GND assuming dc loads Guaranteed but not tested Three stateable pins 0 13 D0 D23 PMS DMS BMS RD WR DT1 SCLK1 RFS1 TFS1 5 0 0 TFSO 80 V on BR CLKIN Active to force three state condition Applies to PLCC MQFP package types Output pin capacitance is the capacitive load for any three stated output pin Specifications subject to change without notice ABSOLUTE MAXIMUM RATINGS Supply 0 3 V to 7 V Input Voltage 0 3 V to Vpp 0 3 V Output Voltage Swing 0
15. data memory is divided into five zones each associated with its own wait state generator This allows slower peripherals to be memory mapped into data memory for which wait states are specified By mapping peripherals into different zones you can accommodate peripherals with different wait state require ments All zones default to seven wait states after RESET REV 0 ADSP 216x Bus Interface The ADSP 216x processors can relinquish control of their data and address buses to an external device When the external device requires control of the buses it asserts the bus request signal BR If the ADSP 21 6x is not performing an external memory access it responds to the active BR input in the next cycle by Three stating the data and address buses and the PMS DMS BMS RD WR output drivers Asserting the bus grant BG signal and halting program execution If the Go mode is set however the ADSP 21 6x will not halt program execution until it encounters an instruction that requires an external memory access If the ADSP 216x is performing an external memory access when the external device asserts the BR signal it will not three state the memory interfaces or assert the BG signal until the cycle after the access completes up to eight cycles later depend ing on the number of wait states The instruction does not need to be completed when the bus is granted the ADSP 21xx will grant the bus between two memory acces
16. 0 70 40 85 See Environmental Conditions for information on thermal specifications Parameter Test Conditions Min Max Unit Vin Hi Level Input Voltage Vpp max 2 0 V Vin Hi Level CLKIN and Reset Voltage Vpp max 2 2 V Vir Lo Level Input Voltage 3 Vpp min 0 4 V Hi Level Output Voltage 4 Vpp min 0 5 mA 2 4 V Vor Lo Level Output Voltage 4 Vpp min Ip 2 mA 0 4 V Im Hi Level Input Current Vpp max Vin max 10 Lo Level Input Current Vpp max Vin 0 V 10 Three State Leakage Current Vpp max Vin Vpp max 10 Three State Leakage Current Vpp max Vin 0 10 Input Pin Capacitance 8 Vin 2 5 V f 1 0 MHz Tams 25 C 8 pF Co Output Pin Capacitance 9 Vin 2 5 V f 1 0 MHz Tamp 25 C 8 pF NOTES Input only pins CLKIN RESET IRQ2 BR MMAP DRO Bidirectional pins 20 023 SCLK1 RFS1 TFS1 5 0 RFSO 50 3Output pins BG PMS DMS BMS RD WR A0 A13 CLKOUT DTI ADSP 2162 ADSP 2164 and ADSP 2166 outputs are CMOS and will drive to V pp and GND with no dc loads gt Three stateable pins 0 13 20 023 PMS DMS BMS RD WR DT1 SCLK1 RFS1 TFS1 SCLKO0 RFSO 0 60 V on BR CLKIN Active to force three state condition Guaranteed but not tested applies to PLCC and package types Output
17. 0 00 MHz 50 ns 25 MHz 40 ns d Packages 68 Lead PLCC 80 Lead MQFP x 6 Temperature Grades K Commercial 0 C to 70 C 2 Y B Industrial 40 C to 85 C s K 2 e Development Tools ARCHITECTURE OVERVIEW The ADSP 216x processors are supported by a complete set of tools for system development The ADSP 2100 Family Devel opment Software includes C and assembly language tools that allow programmers to write code for any of the ADSP 216x processors The ANSI C compiler generates ADSP 216x assem bly source code while the runtime C library provides ANSI standard and custom DSP library routines The ADSP 216x assembler produces object code modules that the linker com bines into an executable file The processor simulators provide an interactive instruction level simulation with a reconfigurable windowed user interface A PROM splitter utility generates PROM programmer compatible files EZ ICE in circuit emulators allow debugging of ADSP 21xx systems by providing a full range of emulation functions such as modification of memory and register values and execution breakpoints EZ LAB demonstration boards are complete DSP systems that execute EPROM based programs The EZ Kit Lite is a very low cost evaluation development platform that contains both the hardware and software needed to evaluate the ADSP 21xx architecture Additional details and ordering information are available in the ADSP 2100 Fa
18. 128 The instruction leaves the chip in an idle state operating at the slower rate While it is in this state the processor s other inter nal clock signals such as SCLK CLKOUT and the timer clock are reduced by the same ratio Upon receipt of an en abled interrupt the processor will stay in the IDLE state for up to a maximum of CLKIN cycles where 7 is the divisor speci fied in the instruction before resuming normal operation When the IDLE n instruction is used it slows the processor s internal clock and thus its response time to incoming interrupts the 1 cycle response time of the standard IDLE state is increased by the clock divisor When an enabled interrupt is received the ADSP 216x will remain in the IDLE state for up to a maxi mum of n CLKIN cycles where 16 32 64 or 128 before resuming normal operation When the IDLE n instruction is used in systems that have an externally generated serial clock SCLK the serial clock rate may be faster than the processor s reduced internal clock rate Under these conditions interrupts must not be generated at a faster rate than can be serviced due to the additional time the processor takes to come out of the IDLE state a maximum of n CLKIN cycles 10 ADSP 216x Prototyping You can prototype your ADSP 216x system with either ADSP 2101 or ADSP 2103 RAM based processors When code is fully developed and debugged it can be submitted to Analog Devices for convers
19. 3 V to Vpp 0 3 V Operating Temperature Range Ambient 40 C to 85 C No Extended Temperature Range Storage Temperature Range 65 C to 150 Lead Temperature 10 sec 300 Lead Temperature 5 sec PLCC MQFP TQFP 280 Stresses greater than those listed above may cause permanent damage to the device These are stress ratings only functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily WARNING accumulate on the human and test equipment can discharge without detection Although the ADSP 216x features proprietary ESD protection circuitry permanent damage may occur on Sept Athe devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are ESD SENSITIVE DEVICE recommended to avoid performance degradation or loss of functionality REV 0 13 ADSP 216x SPECIFICATIONS ADSP 2161 ADSP 2163 ADSP 2165 SUPPLY CURRENT AND POWER Parameter Test Conditions Min Max Unit Ipp Supply Current Dynamic Vpp max 40 ns 38 mA Vpp max tcx 50 ns 31 mA Vpp max
20. 3FF 0x3400 0x37FF 0x3800 0x37FF 0x3800 2K x 24 EXTERNAL 0 Ox3FFF Ox3FFF Figure 4 ADSP 2165 ADSP 2166 Program Memory Maps ADSP 2161 ADSP 2162 When MMAP 0 on chip program memory ROM occupies 8K words beginning at address 0x0000 Off chip program memory uses the remaining 8K words beginning at address 0x2000 When MMAP 1 2K words of off chip program memory begin at address 0x0000 6K words of on chip program memory ROM at 0x0800 to 0x1 FFO and the remainder 2K words of pro gram memory ROM is at 0x3800 to 0x3FFF An additional 6K of off chip program memory is at 0x2000 to 0x37FF 0x0000 0x0000 2K EXTERNAL 8K Ox7FFF INTERNAL 0x0800 ROM 6K INTERNAL ROM Ox1FFO 0x1FFO RESERVED RESERVED Ox1FFF 0x1FFF 0x2000 0x2000 6K 8K EXTERNAL EXTERNAL 0x37FF 2K 0x3800 INTERNAL Ox3FFF Ox3FFF MMAP 0 MMAP 1 Figure 5 ADSP 2161 ADSP 2162 Program Memory Maps ADSP 216x ADSP 21631ADSP 2164 When MMAP 0 on chip program memory ROM occupies 4K words beginning at address 0x0000 Off chip program memory uses the remaining 12K words beginning at address 0x1000 When MMAP 1 2K words of off chip program memory begin at address 0x0000 2K words of on chip program memory ROM is at 0x0800 to 0 0 0 and the remainder 2K words of pro gram memory ROM is at 0x3800 to Ox3FFF An additional 10K of off chip program memory is at 0x1000 to Ox37FF 0x0000 0x0000 2K 4K EXTERNAL INTERNAL
21. 4 word or 32 word time division multiplexed serial bit stream this feature is especially useful for T1 or CEPT interfaces or as a network communication scheme for multiple processors Alternate Configuration SPORT can be alternatively configured as two external interrupt inputs IRQO IRQ1 and the Flag In and Flag Out signals FI FO Interrupts The ADSP 216x s interrupt controller lets the processor re spond to interrupts with a minimum of overhead Up to three external interrupt input pins IRQ0 IRQI and 2 are pro vided IRQ2 is always available as a dedicated pin IRQ1 and IRQO may be alternately configured as part of Serial Port 1 The ADSP 216x also supports internal interrupts from the timer and the serial ports The interrupts are internally prioritized and individually maskable except for RESET which is nonmaskable The IRQx input pins can be programmed for either level or edge sensitivity The interrupt priorities for each ADSP 216x processor are shown in Table II Table II Interrupt Vector Addresses and Priority Interrupt ADSP 216x Interrupt Source Vector Address RESET Startup 0x0000 IRQ2 or Power Down 0x0004 High Priority SPORTO Transmit 0x0008 SPORTO Receive 0x000C SPORTI Transmit or IRQI 0x0010 1 Receive IRQO 0x0014 Timer 0x0018 Low Priority REV 0 The ADSP 216x uses a vectored interrupt scheme when an interrupt is acknowledged the processor s
22. 5 20 ns tcky CLKIN Width High 20 20 15 20 ns trsp RESET Width Low 300 250 200 5 Switching Characteristics tcp CLKOUT Width Low 20 15 10 0 51 10 ns CLKOUT Width High 20 15 10 0 51 10 ns CLKIN High to CLKOUT High 0 20 0 20 0 152 0 202 ns NOTES lApplies after power up sequence is complete Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN not including crystal oscillator startup time For 25 MHz only the maximum frequency dependency for 15 ns CLKIN CLKOUT Figure 21 Clock Signals 22 REV 0 ADSP 216x TIMING PARAMETERS ADSP 2161 ADSP 2163 ADSP 2165 INTERRUPTS AND FLAGS 16 67 MHz 20 MHz 25 MHz Frequency Dependency Parameter Min Max Min Max Min Max Min Max Unit Timing Requirements tips IRQx or FI Setup Before 30 27 5 25 0 251 15 ns CLKOUT Low tres IRQx or FI Setup Before 33 30 5 28 0 25 18 ns CLKOUT Low tru IRQx or FI Hold After CLKOUT 15 12 5 10 0 251 ns High Switching Characteristics tron FO Hold After CLKOUT High 0 0 0 0 ns trop FO Delay from CLKOUT High 15 15 127 15 1 IRQO IRQ1 and IRQ2 If IRQx and FI inputs meet tres and setup hold requirements they will be recognized during the current clock cycle otherwise they will be recognized during the following cycle Refer to the Interrupt Contro
23. ANALOG DEVICES DSP Microcomputers with ROM ADSP 216x SUMMARY 16 Bit Fixed Point DSP Microprocessors with On Chip Memory Enhanced Harvard Architecture for Three Bus Performance Instruction Bus and Dual Data Buses Independent Computation Units ALU Multiplier Accumulator and Shifter Single Cycle Instruction Execution and Multifunction Instructions On Chip Program Memory ROM and Data Memory RAM Integrated I O Peripherals Serial Ports Timer FEATURES 25 MIPS 40 ns Maximum Instruction Rate 5 V Separate On Chip Buses for Program and Data Memory Program Memory Stores Both Instructions and Data Three Bus Performance Dual Data Address Generators with Modulo and Bit Reverse Addressing Efficient Program Sequencing with Zero Overhead Looping Single Cycle Loop Setup Double Buffered Serial Ports with Companding Hardware Automatic Data Buffering and Multichannel Operation Three Edge or Level Sensitive Interrupts Low Power IDLE Instruction PLCC and MOFP Packages GENERAL DESCRIPTION The ADSP 216x Family processors are single chip micro computers optimized for digital signal processing DSP and other high speed numeric processing applications The ADSP 216x processors are all built upon a common core with ADSP 2100 Each processor combines the core DSP architec ture computation units data address generators and program sequencer with features such as on chip program ROM and data memory RAM a programmable ti
24. EMORY READ 25 MEMORY WRITE 26 SERIAL PORT S qe I RR e 27 TIMING PARAMETERS ADSP 2162 ADSP 2164 ADSP 2166 28 GENERAL NOTES E er RUE RR hs 28 TIMING NOTES 28 MEMORY REQUIREMENTS 28 CLOCK SIGNALS AND RESET 29 INTERRUPTS AND 30 BUS REQUEST BUS GRANT 31 MEMORY READ 32 MEMORY WRITE 33 SERIAL PORTS Wah 34 PIN CONFIGURATIONS 68 Lead PLCC ADSP 216x 35 80 Lead MQFP 216 36 PACKAGE OUTLINE DIMENSIONS 68 L ad PLCC 5 eee tr Lr SEPAN 37 80 Lead MQFP 38 ORDERING GUIDE 39 REV 0 ADSP 216x Table I ADSP 216x ROM Programmed Processor Features Feature 2161 2162 2163 2164 2165 2166 Data Memory RAM 1 2K 1 2K 1 2K 1 2K 4k Program Memory ROM 8K 8K 12K 12K Program Memory RAM 1K 1K Timer e e Serial Port 0 Multichannel Serial Port 1 Supply Voltage 5V 3 3 V 5V 3 3 V 5V 3 3 V Speed Grades Instruction Cycle Time 10 24 MHz 97 6 ns 13 00 MHz 76 9 ns 16 67 MHz 60 ns 2
25. EV 0 ADSP 216x PIN CONFIGURATIONS 68 Lead PLCC D16 015 D9 amp 08 z 2 D14 213 jo 012 j 211 2 210 2 D7 2 06 2 D5 8 D4 D3 On rr el s XPIN1 IDENTIFIER MMAP ADSP 216x BR TOP VIEW Ae Not to Scale gt gt gt o gt gt PLCC Pin PLCC Pin PLCC Pin PLCC Pin Number Name Number Name Number Name Number Name 1 D11 18 BR 35 A12 52 FO DT1 2 GND 19 IRQ2 36 13_ 53 IRQI 3 D12 20 RESET 37 PMS 54 1800 RFS1 4 D13 21 AO 38 DMS 55 FI 5 D14 22 Al 39 BMS 56 SCLKI 6 D15 23 A2 40 BG 57 7 D16 24 41 XTAL 58 DO 8 D17 25 A4 42 CLKIN 59 DI 9 D18 26 43 CLKOUT 60 D2 10 GND 21 A5 44 WR 61 D3 11 D19 28 A6 45 RD 62 D4 12 D20 29 GND 46 DTO 63 D5 13 D21 30 A7 47 TFSO 64 D6 14 D22 31 A8 48 RFSO 65 D7 15 D23 32 A9 49 GND 66 D8 16 Vp 33 A10 50 DRO 67 D9 17 MMAP 34 All 51 SCLKO 68 D10 REV 0 35 ADSP 216x PIN CONFIGURATIONS 80 Lead MQFP RESET BR qa A a gt gt eje 78 4 77 76 2 75 1 74 0 73 72 iRa2 70 MMAP 69 Vpp 68 Vpp 67 D23 66 D22 65 D21 64 20 63 D19 71 62 GND 61 GND D18 A6 2 IDENTIFIER D17 GND 3 D16 GND D15 A7 5 014 A8 6 013 A9 7 012 A10 8 GND 11 9 ADSP 216x GND 12 10 TOR VIEW 11 A13 11 Not to Sca
26. HANNEL MODE FRAME DELAY 0 MFD 0 Figure 26 Serial Ports REV 0 27 ADSP 216x TIMING PARAMETERS ADSP 2162 ADSP 2164 ADSP 2166 GENERAL NOTES Use the exact timing information given Do not attempt to de rive parameters from the addition or subtraction of others While addition or subtraction would yield meaningful results for an individual device the values given in this data sheet reflect sta tistical variations and worst cases Consequently you cannot meaningfully add parameters to derive longer times TIMING NOTES Switching Characteristics specify how the processor changes its signals You have no control over this timing circuitry external to the processor must be designed for compatibility with these signal characteristics Switching characteristics tell you what the processor will do in a given circumstance You can also use switching characteristics to ensure that any timing requirement of a device connected to the processor such as memory is satisfied Timing Requirements apply to signals that are controlled by cir cuitry external to the processor such as the data input for a read operation Timing requirements guarantee that the processor operates correctly with other devices MEMORY REQUIREMENTS The table below shows common memory device specifications and the corresponding ADSP 216x timing parameters for your convenience Timing Parameter Definition ADSP 216x Memory Device Specifi
27. IDLE instruction Deasserted pins are driven to either Vpp or GND For typical supply current internal power dissipation figures see Figure 15 Specifications subject to change without notice POWER mW IDD DYNAMIC 2 POWER mW 0 5 00 7 00 10 00 13 83 15 00 FREQUENCY MHz IDD IDLE IDD IDLE n MODES POWER mW 0 0 5 00 7 00 10 00 13 83 15 00 5 00 7 00 10 00 13 83 15 00 FREQUENCY MHz FREQUENCY MHz VALID FOR ALL TEMPERATURE GRADES 1POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS 2IDLE REFERS TO ADSP 216x OPERATION DURING EXECUTION OF IDLE INSTRUCTION DEASSERTED PINS ARE DRIVEN TO EITHER Vpp OR GND 3MAXIMUM POWER DISSIPATION AT Vpp 3 6V DURING EXECUTION OF DLE n INSTRUCTION Figure 15 ADSP 2162 Power Typical vs Frequency 18 REV 0 ADSP 216x ADSP 2162 ADSP 2164 ADSP 2166 POWER DISSIPATION EXAMPLE CAPACITIVE LOADING To determine total power dissipation in a specific application Figures 16 and 17 show capacitive loading characteristics for the following equation should be applied for each output the ADSP 2162 and ADSP 2164 Vpp xf C load capacitance f output switching frequency Example In an ADSP 2162 application where external data memory is used and no other outputs are active power dissipation is calcu lated as follows Assumptions External data memory is a
28. ING Figures 10 and 11 show capacitive loading characteristics for the ADSP 2161 ADSP 2163 ADSP 2165 RISE TIME 0 4V 2 0V ns 0 25 50 75 100 125 150 175 C pF Figure 10 Typical Output Rise Time vs Load Capacitance at Maximum Ambient Operating Temperature 4 5V VALID OUTPUT DELAY HOLD ns 0 25 50 75 100 125 150 175 C pF Figure 11 Typical Output Valid Delay or Hold vs Load Capacitance C at Maximum Ambient Operating Temperature 15 ADSP 216x SPECIFICATIONS ADSP 2161 ADSP 2163 ADSP 2165 TEST CONDITIONS Figure 12 shows voltage reference levels for ac measurements 3 0V INPUT 1 5V 0 0V 2 0V OUTPUT 1 5V 0 8V Figure 12 Voltage Reference Levels for AC Measurements Except Output Enable Disable Output Disable Time Output pins are considered to be disabled when they have stopped driving and started a transition from the measured out put high or low voltage to a high impedance state The output disable time is the difference of tupasurpp and tpgcay gt as shown in Figure 13 The time tygasurgp is the interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0 5 V from the mea sured output high or low voltage The decay time tpgcay is dependent on the capacitative load and the current load ij on the output pin It can be ap
29. Ox07FF ROM 2K 0x0800 INTERNAL ROM OxOFFO OxOFFO RESERVED RESERVED OxOFFF OxOFFF 0x1000 0x1000 10K EXTERNAL 12K EXTERNAL Ox37FF 2K 0x3800 INTERNAL Ox3FFF ROM 0x3FFF MMAP 0 1 Figure 6 ADSP 2163 ADSP 2164 Program Memory Maps Data Memory Interface The data memory address bus DMA is 14 bits wide The bidirectional external data bus is 24 bits wide with the upper 16 bits used for data memory data DMD transfers The data memory select DMS signal indicates access to data memory and can be used as a chip select signal The write WR signal indicates a write operation and can be used as a write strobe The read RD signal indicates a read operation and can be used as a read strobe or output enable signal The ADSP 216x processors support memory mapped I O with the peripherals memory mapped into the data memory address space and accessed by the processor in the same manner as data memory Data Memory Map For the ADSP 2165 ADSP 2166 on chip data memory RAM resides in the 4K words beginning at address 0x2000 as shown in Figure 7 Data memory locations from 0x3000 to the end of data memory at 0x3FFF are reserved Control and status regis ters for the system timer wait state configuration and serial port operations are located in this region of memory The remaining 8K of data memory is located off chip This external data memory is divided into three zones each associ ated with its own wait state gen
30. Synchronization I O TFS Transmit Frame Synchronization I O DR Serial Data Receive DT Serial Data Transmit REV 0 EXTERNAL ADSP 216x The ADSP 216x serial ports offer the following capabilities Bidirectional Each SPORT has a separate double buffered transmit and receive function Flexible Clocking Each SPORT can use an external serial clock or generate its own clock internally Flexible Framing The SPORT have independent framing for the transmit and receive functions each function can run in a frameless mode or with frame synchronization signals inter nally generated or externally generated frame sync signals may be active high or inverted with either of two pulsewidths and timings Different Word Lengths Each SPORT supports serial data word lengths from 3 to 16 bits Companding in Hardware Each SPORT provides optional A law and u law companding according to CCITT recommen dation G 711 Flexible Interrupt Scheme Receive and transmit functions can generate a unique interrupt upon completion of a data word transfer Autobuffering with Single Cycle Overhead Each SPORT can automatically receive or transmit the contents of an entire circular data buffer with only one overhead cycle per data word an interrupt is generated after the transfer of the entire buffer is completed Multichannel Capability SPORT0 Only SPORTO pro vides a multichannel interface to selectively receive or transmit a 2
31. cation Timing Parameter Address Setup to Write Start tasw Address Setup to Write End taw Address Hold Time Data Setup Time tpw Data Hold Time tDH OE to Data Valid trpp Address Access Time taa 0 13 DMS PMS Setup Before WR Low 0 13 DMS PMS Setup Before WR Deasserted A0 A13 DMS PMS Hold After WR Deasserted Data Setup Before WR High Data Hold After WR High RD Low to Data Valid 0 13 DMS PMS BMS to Data Valid 28 REV 0 ADSP 216x TIMING PARAMETERS ADSP 2162 ADSP 2164 ADSP 2166 CLOCK SIGNALS AND RESET Frequency 10 24 MHz 13 0 MHz 16 67 MHz Dependency Parameter Min Max Min Max Min Max Min Max Unit Timing Requirements tck CLKIN Period 97 6 150 76 9 150 60 0 150 tck 150 ns tex Width Low 20 20 20 20 ns CLKIN Width High 20 20 20 20 ns trsp RESET Width Low 488 384 5 300 5 Switching Characteristics tcp CLKOUT Width Low 38 8 28 5 20 0 5 10 ns tcp Width High 38 8 28 5 20 0 5 10 ns CLKIN High to CLKOUT High 0 20 0 20 0 20 0 20 ns NOTE lApplies after power up sequence is complete Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN not including crystal oscillator startup time CLKIN CLKOUT Figure 27 Clock Signals REV 0 29 ADSP 216x TIMING PARAMETERS ADSP 2162 ADSP 2164 ADSP 2166 INTERRUPTS AND FLAGS Frequency 10
32. ccessed every cycle with 50 of the address pins switching RISE TIME 0 4V 2 0V ns External data memory writes occur every other cycle with 5096 of the data pins switching Each address and data pin has a 10 pF total load at the pin 0 55 75 D M38 3802 2475 The application operates at Vpp 3 3 V and 100 ns C pF Figure 16 Typical Output Rise Time vs Load Capaci Total Power Dissipation x f tance C at Maximum Ambient Operating Temperature internal power dissipation from Figure 15 C x Vpp x f is calculated for each output 8 of 6 Output Pins x C x Vpop x f Address DMS 8 x10 pF 3 3 V x 10 MHz 8 71 mW z Y Data WR 9 xIOpF x 3 3 Vx 5MHz 4 90 mW g j RD 1 10 3 32 5 2 0 55 mW CLKOUT 1 x 10 pF x 3 3 V x 10 MHz 1 00 mW NOMINAL 15 25 mW 2 Total power dissipation for this example 15 25 mW 740 25 50 75 100 125 150 175 ENVIRONMENTAL CONDITIONS C pF Ambient Temperature Rating E 5 Figure 17 Typical Output Valid Delay or Hold vs Load Tamp PD x 0c4 Capacitance at Maximum Ambient Operating Tcasz Case Temperature in C Temperature PD Power Dissipation in W Oca Thermal Resistance Case to Ambient 0j Thermal Resistance Junction to Ambient Thermal Resistance Junction t
33. efore RD Low 0 25 10 ns trpa 0 13 PMS DMS BMS Hold After RD Deasserted 0 251 9 ns RD High to RD or WR Low 0 5tcx 5 ns NOTES IFor 25 MHz only minimum frequency dependency formula for t asr 0 25tcx 8 5 w wait states X CLKOUT 0 13 Figure 24 Memory Read REV 0 25 ADSP 216x TIMING PARAMETERS ADSP 2161 ADSP 2163 ADSP 2165 MEMORY WRITE 16 67 MHz 20 MHz 25 MHz Parameter Min Max Min Max Min Unit Switching Characteristics tow Data Setup Before WR High 17 12 7 ns tpH Data Hold After WR High 5 2 5 0 ns twp WR Pulsewidth 22 17 12 ns twDE WR Low to Data Enabled 0 0 ns tasw A0 A13 DMS PMS Setup Before WR Low 5 2 5 1 51 ns tppR Data Disable Before WR or RD Low 5 2 5 1 5 ns teyr CLKOUT High to WR Low 10 25 7 5 22 5 20 ns taw 0 13 DMS PMS Setup Before WR Deasserted 23 15 5 ns 0 13 DMS PMS Hold After WR Deasserted 6 3 5 ns twwR WR High to RD or WR Low 25 20 15 ns Frequency Dependency CLKIN lt 25 MHz Parameter Min Max Unit Switching Characteristics Data Setup Before WR High 0 5tcK 13 w ns tpH Data Hold After WR High 0 251 10 ns twp WR Pulsewidth 0 51 8 w ns twDE WR Low to Data Enabled 0 tasw A0 A13 DMS PMS Setup Before WR Low 0 25 10 ns tppR Data Disable Before WR or RD Low 0 251 10 ns teyr CLKOUT High to WR
34. ena bit in the power down sportl autobuffer control register Note In order to power down the PWDENA bit must be set before the IRQ2 interrupt is initiated nitiate the power down sequence by generating an IRQ2 interrupt either externally or by software use of the IFC register The processor vectors to the IRQ2 interrupt vector located at 0x0004 Any number of housekeeping instructions starting at loca tion 0x0004 can be executed prior to the processor entering the power down mode The processor enters the power down mode when the pro cessor executes an IDLE instruction while executing the IRQ2 interrupt routine Notes fan RTI instruction is executed before the processor en counter an IDLE instruction then the processor returns from the IRQ2 interrupt and the power down sequence is aborted The user can differentiate between a normal IRQ2 inter rupt and a power down IRQ2 interrupt by resetting the PWDFLAG pin and checking the status of this pin by testing the PWDFLAG bit in the power down SPORT1 autobuffer control register located at DM 0x3FEF ADSP 216x Exiting Power Down The power down mode can be exited with the use of the PWDFLAG or RESET pin Applying a low to high transition to the PWDFLAG pin takes the processor out of power down mode In this case a delay of 4096 cycles is automatically in duced by the processor Also depending on the status of the power up context reset b
35. erator This allows slower pe ripherals to be memory mapped into data memory for which wait states are specified By mapping peripherals into different Zones you can accommodate peripherals with different wait state requirements All zones default to 7 wait states after RESET A ADDRESS HEX 0x0000 1K EXTERNAL DWAITO 0x0400 1K EXTERNAL EXTERNAL DWAIT1 RAM 0x0800 6K EXTERNAL DWAIT2 0x2000 4K x 16 INTERNAL INTERNAL RAM 0x3000 4K x 16 MEMORY MAPPED REGISTERS amp RESERVED Y Figure 7 ADSP 2165 ADSP 2166 Data Memory Map ADSP 21611ADSP 21621ADSP 21631ADSP 2164 For the ADSP 2161 ADSP 2162 ADSP 2163 ADSP 2164 on chip data memory RAM resides in the 512 words beginning at address 0x3800 also shown in Figure 8 Data memory locations from 0x3A00 to the end of data memory at Ox3FFF are reserved Control and status registers for the system timer wait state configuration and serial port operations are located in this region of memory Ox3FFF ADDRESS HEX 0x0000 1K EXTERNAL DWAITO 0x0400 A 1K EXTERNAL DWAIT1 0x0800 EXTERNAL 10K EXTERNAL DWAIT2 0 3000 1K EXTERNAL DWAIT3 0x3400 1K EXTERNAL DWAIT4 0x3800 512 ADSP 2161 62 63 64 0x3A00 0 3 00 MEMORY MAPPED CONTROL REGISTERS amp RESERVED Ox3FFF Figure 8 ADSP 2161 ADSP 2162 ADSP 2163 ADSP 2164 Data Memory Map The remaining 14K of data memory is located off chip This external
36. f the Power Down Flag Input pin can be used to terminate power down NOTES Unused data bus lines may be left floating must be tied high to Vpp if not used 3Only on ADSP 2165 ADSP 2166 REV 0 ADSP 216x CLOCK OR CRYSTAL XTAL CLKOUT SERIAL SERIAL DEVICE PORT 0 ADSP 216x mag TFS OR IRQ1 SERIAL DEVICE OPTIONAL SERIAL PORT 1 PROGRAM MEMORY OPTIONAL MEMORY amp PERIPHERALS Figure 3 Basic System Configuration Program Memory Interface The on chip program memory address bus PMA and on chip program memory data bus PMD are multiplexed with the on chip data memory buses DMA DMD creating a single exter nal data bus and a single external address bus The external data bus is bidirectional and is 24 bits wide to allow instruction fetches from external program memory Program memory may contain code and data The external address bus is 14 bits wide For the ADSP 216x these lines can directly address up to 16K words of which 2K are on chip The data lines are bidirectional The program memory select PMS signal indicates accesses to program memory and can be used as a chip select signal The write WR signal indicates a write operation and is used as a write strobe The read RD signal indicates a read operation and is used as a read strobe or output enable signal The ADSP 216x processors write data from their 16 bit regis ters to 24 bit program memory using t
37. he PX register to provide the lower eight bits When the processor reads 16 bit data from 24 bit program memory to a 16 bit data register the lower eight bits are placed in the PX register The program memory interface can generate 0 to 7 wait states for external memory devices default is to 7 wait states after RESET Program Memory Maps Program memory can be mapped in two ways depending on the state of the MMAP pin Figure 4 shows the program memory map for the ADSP 2165 ADSP 2166 Figures 5 and 6 show the program memory maps for the ADSP 2161 ADSP 2162 and ADSP 2163 ADSP 2164 respectively REV 0 ADSP 2165I MADSP 2166 When MMAP 0 on chip program memory ROM occupies 12K words beginning at address 0x0000 Internal program memory RAM occupies 1K words beginning at address 0x3000 Off chip program memory uses the 2K words beginning at address 0x3800 The ADSP 2165 ADSP 2166 does not support boot memory When MMAP 1 2K words of off chip program memory begin at address 0x0000 10K words of on chip program memory ROM at 0x800 to 0x2FFF and the remainder 2K words of program memory ROM is at 0x3800 to 0x3FFF Internal pro gram memory RAM occupies 1K words at address 0x300 to 0x33FF EXTERNAL 0x0000 0x0000 0x07FF 0x0800 12K x 24 INTERNAL ROM 10K x 24 INTERNAL ROM Ox2FFF 0x3000 Ox2FFF 0x3000 1K x 24 RAM RESERVED 2K x 24 INTERNAL ROM MMAP 1 1K x 24 RAM RESERVED 0x33FF 0x3400 0x3
38. he highest performance ADSP 216x proces sors operate at 25 MHz with a 40 ns instruction cycle time Every instruction can execute in a single cycle Fabrication in CMOS results in low power dissipation The ADSP 2100 Family s flexible architecture and compre hensive instruction set support a high degree of parallelism In one cycle the ADSP 216x can perform all of the following operations Generate the next program address Fetch the next instruction Perform one or two data moves Update or two data address pointers Perform a computation Receive and transmit data via one or two serial ports Table I shows the features of each ADSP 216x processor The ADSP 216x series are memory variant versions of the ADSP 2101 and ADSP 2103 that contain factory programmed on chip ROM program memory These devices offer different amounts of on chip memory for program and data storage Table I shows the features available in the ADSP 216x series of custom ROM coded processors The ADSP 216x products eliminate the need for an external boot EPROM in your system and can also eliminate the need for any external program memory by fitting the entire applica tion program in on chip ROM These devices thus provide an excellent option for volume applications where board space and system cost constraints are of critical concern One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 World Wide Web Site http
39. hifts program control to the interrupt vector address corresponding to the interrupt received Interrupts can be optionally nested so that a higher priority interrupt can preempt the currently executing interrupt service routine Each interrupt vector location is four instruc tions in length so that simple service routines can be coded entirely in this space Longer service routines require an addi tional JUMP or CALL instruction Individual interrupt requests are logically ANDed with the bits in the IMASK register the highest priority unmasked interrupt is then selected The interrupt control register ICNTL allows the external interrupts to be set as either edge or level sensitive Depending on Bit 4 in ICNTL interrupt service routines can either be nested with higher priority interrupts taking precedence or be processed sequentially with only one interrupt service active at a time The interrupt force and clear register IFC is a write only regis ter that contains a force bit and a clear bit for each interrupt When responding to an interrupt the ASTAT MSTAT and IMASK status registers are pushed onto the status stack and the PC counter is loaded with the appropriate vector address The status stack is seven levels deep to allow interrupt nesting The stack is automatically popped when a return from the inter rupt instruction is executed Pin Definitions Pin Function Descriptions show pin definitions for the ADSP 216x
40. ion into an ADSP 216x ROM product The ADSP 2101 EZ ICE emulator can be used for development of ADSP 216x systems For the 3 3 V ADSP 2162 ADSP 2164 and ADSP 2166 a voltage converter interface board provides 3 3 V emulation Additional overlay memory is used for emulation of ADSP 2161 ADSP 2162 systems It should be noted that due to the use of off chip overlay memory to emulate the ADSP 2161 ADSP 2162 a performance loss may be experienced when both executing instructions and fetching program memory data from the off chip overlay memory in the same cycle This can be overcome by locating program memory data in on chip memory Ordering Procedure for ADSP 216x ROM Processors To place an order for a custom ROM coded ADSP 2161 ADSP 2162 ADSP 2163 ADSP 2164 ADSP 2165 or ADSP 2166 processor you must 1 Complete the following forms contained in the ADSP ROM Ordering Package available from your Analog Devices sales representative ADSP 216x ROM Specification Form ROM Release Agreement ROM NRE Agreement amp Minimum Quantity Order MQO Acceptance Agreement for Preproduction ROM Products 2 Return the forms to Analog Devices along with two copies of the Memory Image File EXE file of your ROM code The files must be supplied on two 3 5 or 5 25 floppy disks for the IBM PC DOS 2 01 or higher 3 Place a purchase order with Analog Devices for nonrecurring engineering changes NRE associated with ROM product development
41. istics tgp RD Pulsewidth 43 8 33 25 25 0 5 5 w ns tcrp CLKOUT High to RD Low 19 4 34 4 14 2 29 2 10 0 25 0 0 25tcK 5 0 251 10 ns tasr 0 13 PMS DMS BMS Setup Before RD Low 12 4 7 2 3 0 0 25 12 ns trpa 0 13 PMS DMS BMS Hold After RD Deasserted 14 4 9 2 5 0 0 25tcx 10 ns trwr RD High to RD or WR Low 38 8 28 5 20 0 0 5 10 ns w wait states X CLKOUT 0 13 Figure 30 Memory Read 32 REV 0 ADSP 216x TIMING PARAMETERS ADSP 2162 ADSP 2164 ADSP 2166 MEMORY WRITE Frequency 10 24 MHz 13 0 MHz 16 67 MHz Dependency Parameter Min Min Max Min Max Min Max Unit Switching Characteristics tpw Data Setup Before WR High 38 8 28 25 20 0 5 10 ns Hold After WR High 14 4 9 2 5 0 0 25 10 ns typ WR Pulsewidth 43 8 33 25 25 0 5 5 w ns WR Low to Data Enabled 0 0 0 0 tasw 0 13 DMS DMS Setup Before WR Low 12 4 7 2 3 0 0 251 12 toor Data Disable Before WR or RD Low 14 4 9 2 5 0 0 251 10 tcwr CLKOUT High to WR Low 19 4 34 4 14 2 292 10 0 0 25tck 5 0 25tck 10 ns taw A0 AI3 DMS PMS Setup Before WR Deasserted 58 2 42 7 30 0 75tck 15 w ns twra A0 A13 DMS PMS Hold After WR Deasserted 14 4 9 2 5 0 0 251 10 twwr WR High to RD or WR Low 38 8 28 25 20 0 5tcg 10 ns w wait states X REV 0 Figure 31 Memory Write 33
42. it pucr the processor either 1 continues to execute instructions following the IDLE instruc tion that caused the power down A RTI instruction is re quired to pass control back to the main routine pucr 0 or 2 resumes operation from power down by clearing the PC STATUS LOOP and CNTR stack The IMASK and ASTAT registers are set to 0 and the SSTAT goes to 0x55 The processor then starts executing instructions from the address zero pucr 1 In the case where the power down mode is exited by asserting the RESET pin the processor state is reset and instruction are executed from address 0x0000 The RESET pin in this case must be held low long enough for the external crystal if any and the on chip PLL to stabilize and lock Low Power IDLE Instruction The IDLE instruction places the ADSP 216x processor in low power state in which it waits for an interrupt When an interrupt occurs it is serviced and execution continues with instruction following IDLE Typically this next instruction will be a JUMP back to the IDLE instruction This implements a low power standby loop The IDLE n instruction is a special version of IDLE that slows the processor s internal clock signal to further reduce power consumption The reduced clock frequency a programmable fraction of the normal clock rate is specified by a selectable divisor given in the IDLE instruction The syntax of the instruction is IDLE n where 16 32 64 or
43. le D10 PMS 12 09 DMS 13 08 5 14 D7 BG 15 D6 XTAL 16 05 CLKIN 17 D4 PWDACK 18 NC PWDFLAG 19 NC Nc 20 NC 1 3 a NC NO CONNECT MQFP Pin MQFP Pin MQFP Pin MQFP Pin Number Name Number Name Number Name Number Name 1 A5 21 CLKOUT 41 NC 61 GND 2 22 WR 42 NC 62 GND 3 GND 23 RD 43 NC 63 D19 4 GND 24 DTO 44 D4 64 D20 5 A7 25 TFSO 45 D5 65 D21 6 A8 26 RFSO 46 D6 66 D22 7 A9 27 GND 47 D7 67 D23 8 10 28 GND 48 D8 68 Vpp 9 11 29 DRO 49 D9 69 10 12 20 SCLKO 50 D10 70 MMAP 11 A13 31 FO DTI 51 D11 71 BR 12 PMS 32 TFSI 52 GND 72 IRQ2 13 DMS 33 IRQO RFSI 53 GND 73 14 BMS 34 FI DR1 54 D12 74 AO 15 BG 35 SCLKI 55 D13 75 AI 16 XTAL 36 Vpp 56 D14 76 A2 17 CLKIN 37 DO 57 D15 77 A3 18 PWDACK 38 DI 58 D16 78 A4 19 PWDFLAG 39 D2 59 D17 79 20 40 D3 60 D18 80 Vpp ADSP 2165 ADSP 2166 only Others NC 36 REV 0 ADSP 216x OUTLINE DIMENSIONS REV 0 0 995 25 27 0 985 25 02 90 ADSP 216x 68 Lead Plastic Leaded Chip Carrier PLCC 0 175 4 45 0 169 4 29 1 VIEW PINS DOWN 0 954 24 23 0 950 24 13 0 925 23 50 0 895 22 73 0 019 0 48 0 017 0 43 0 029 0 74 0 027 0 69 0 104 2 64 TYP 37 IDENTIFIER BOTTOM
44. ller section in Chapter 3 Program Control of the ADSP 2100 Family User s Manual Third Edition for further information on interrupt servicing 3Edge sensitive interrupts require pulsewidths greater than 10 ns Level sensitive interrupts must be held low until serviced For 25 MHz only the maximum frequency dependency for tgop 12 ns REV 0 CLKOUT FLAG OUTPUT S lirs Figure 22 Interrupts and Flags 23 ADSP 216x TIMING PARAMETERS ADSP 2161 ADSP 2163 ADSP 2165 BUS REQUEST BUS GRANT 16 67 MHz 20 MHz 25 MHz Frequency Dependency Parameter Min Max Min Max Min Max Min Max Unit Timing Requirements BR Hold After CLKOUT High 20 17 5 15 0 251 5 ns tgs BR Setup Before CLKOUT Low 35 32 5 30 0 25tcK 20 ns Switching Characteristics tsp CLKOUT High to DMS 35 32 5 30 0 25 20 ns PMS BMS RD WR Disable tsp DMS PMS BMS RD WR 0 0 0 0 ns Disable to BG Low tsE BG High to DMS PMS 0 0 0 0 ns BMS RD WR Enable DMS PMS BMS RD WR 5 2 5 1 5 0 251 10 Enable to CLKOUT High NOTES BR meets the tgs and setup hold requirements it will be recognized in the current processor cycle otherwise it is recognized in the following cycle BR requires a pulsewidth greater than 10 ns For 25 MHz only the minimum frequency dependency formula for tggc 0 251 8 5 Section 10 2 4 Bus Request Grant on page 212 of the
45. mer and two serial ports The ADSP 2165 ADSP 2166 also adds program memory and power down mode This data sheet describes the following ADSP 216x Family processors ADSP 2161 ADSP 2162 ADSP 2163 ADSP 2164 ADSP 2165 ADSP 2166 Custom ROM programmed DSPs ROM programmed ADSP 216x processors with power down and larger on chip memories 12K Pro gram Memory ROM 1K Program Memory RAM 4K Data Memory RAM REV 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAM C B DATA ADDRESS MEMORY GENERATORS PROGRAM pRoGRAM DATA DAG1 DAG2 5 memory MEMORY pM eh FT ML PROGRAM MEMORY ADDRESS EXTERNAL L ADDRESS DATA MEMORY ADDRESS BUS PROGRAM MEMORY DATA EXTERNAL Y Y KE DATA DATA MEMORY DATA BUS Y Y ARITHMETIC UNITS SERIAL PORTS TIMER SHIFTER 5 o 1 ADSP 2100 CORE Fabricated in a high speed submicron double layer metal CMOS process t
46. mily Software amp Hardware Development Tools data sheet ADDS 21xx TOOLS This data sheet can be requested from any Analog Devices sales office or distributor Additional Information This data sheet provides a general overview of ADSP 216x processor functionality For detailed design information on the architecture and instruction set refer to the ADSP 2100 Family User s Manual Third Edition available from Analog Devices EZ ICE and EZ LAB are registered trademarks of Analog Devices Inc REV 0 3 Figure 1 shows a block diagram of the ADSP 216x architecture The processors contain three independent computational units the ALU the multiplier accumulator MAC and the shifter The computational units process 16 bit data directly and have provisions to support multiprecision computations The ALU performs a standard set of arithmetic and logic operations division primitives are also supported The MAC performs single cycle multiply multiply add and multiply subtract opera tions The shifter performs logical and arithmetic shifts normal ization denormalization and derive exponent operations The shifter can be used to efficiently implement numeric format control including multiword floating point representations The internal result R bus directly connects the computational units so that the output of any unit may be used as the input of any unit on the next cycle A powerful program sequencer and two dedicated data add
47. o Case Package Oya MQFP 60 C W 18 C W 42 C W REV 0 19 ADSP 216x SPECIFICATIONS ADSP 2162 ADSP 2164 ADSP 2166 TEST CONDITIONS Figure 18 shows voltage reference levels for ac measurements 7 2 OUTPUT Figure 18 Voltage Reference Levels for AC Measurements Except Output Enable Disable Output Disable Time Output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state The out put disable time is the difference of tugAsungp and tpgcay as shown in Figure 19 The time is the interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0 5 V from the mea sured output high or low voltage The decay time tpgcay is dependent on the capacitative load and the current load on the output pin It can be ap proximated by the following equation x0 5V 1L tDECAY from which tprs MEASURED is calculated If multiple pins such as the data bus are disabled the measurement value is that of the last pin to stop driving 20 Output Enable Time Output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driving The output enable time tga is the interval from when a
48. ory Data PMD Bus Data Memory Address DMA Bus Data Memory Data DMD Bus Result R Bus The two address buses PMA DMA share a single external address bus allowing memory to be expanded off chip and the two data buses PMD DMD share a single external data bus The BMS DMS and PMS signals indicate which memory space is using the external buses Program memory can store both instructions and data permit ting the ADSP 216x to fetch two operands in a single cycle one from program memory and one from data memory The processor can fetch an operand from on chip program memory and the next instruction in the same cycle The memory interface supports slow memories and memory mapped peripherals with programmable wait state generation External devices can gain control of the processor s buses with the use of the bus request grant signals BR BG One bus grant execution mode GO Mode allows the ADSP 216x to continue running from internal memory A second execution mode requires the processor to halt while buses are granted Each ADSP 216x processor can respond to several different interrupts There can be up to three external interrupts configured as edge or level sensitive Internal interrupts can be generated by the timer and serial ports There is also a master RESET signal Booting circuitry provides for loading on chip program memory automatically from byte wide external memory After reset three wait sta
49. own Interrupt support allows an unlimited number of instructions to be executed before optionally powering down Context clear save control allows the processor to continue where it left off or start with a clean context when leaving the power down state REV 0 Low to high transition of the power down flag input pin PWDFLAQG can be used to terminate power down The RESET pin also can also be used to terminate power down Power Down Control Several parameters of power down operation can be controlled through control bits of the power down sportl autobuffer con trol register This control register is memory mapped at loca tion Ox3FEF and the power down control bits are as follows bit 15 xtal xtal pin disable during power down 1 disabled 0 enable default bit 14 pwdflag read only when pwdena 1 the value of bit 14 pwdflag is equal to the status of the pwdflag input pin when pwdena 0 the value of bit 14 pwdflag is equal to 0 bit 13 pwdena power down enable 1 enable 0 disable default if pwdena is set to 0 then the output pin PWDACK is driven low and the input pin PWDFLAG is disabled Note It is not recommended that power down enable be set or cleared during an IRQ2 interrupt bit 12 pucr power up context reset 1 soft reset 0 resume execution default Entering Power Down The power down sequence is defined as follows Enable power down logic by setting the pwd
50. pin capacitance is the capacitive load for any three stated output pin Specifications subject to change without notice ABSOLUTE MAXIMUM RATINGS Supply 0 3 V to 4 5 V Input Voltage 0 3 V to Vpp 0 3 V Output Voltage Swing 0 3 V to Vpp 0 3 V Operating Temperature Range Ambient 40 C to 85 C Storage Temperature Range 659 to 150 Lead Temperature 5 sec PLCC MQFP 280 Stresses greater than those listed above may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability REV 0 17 ADSP 216x SPECIFICATIONS ADSP 2162 ADSP 2164 ADSP 2166 SUPPLY CURRENT AND POWER Parameter Test Conditions Min Max Unit Ipp Supply Current Dynamic Vpp max tcx 60 ns 16 mA Vpp max tcx 76 9 ns 15 mA Vpp max tcx 97 6 ns 14 mA Ipp Supply Current Idle 2 Vpn max 60 ns 5 mA Vpp max tcx 76 9 ns 4 mA Vpp max tcx 97 6 ns 4 mA NOTES Current reflects device operating with no output loads Vin 0 4 V and 2 4 V 3Idle refers to ADSP 216x state of operation during execution of
51. processors Any inputs not used must be tied to Vpp SYSTEM INTERFACE Figure 3 shows a typical system for the ADSP 216x with two serial I O devices an optional external program and data memory A total of 12K words of data memory and 15K words of program memory is addressable Programmable wait state generation allows the processors to easily interface to slow external memories The ADSP 216x processors also provide either one external interrupt IRQ2 and two serial ports SPORT0 SPORT1 or three external interrupts IRQ2 IRQ1 IRQO and one serial port 5 Clock Signals The ADSP 216x processors CLKIN input may be driven by a crystal or by TTL compatible external clock signal The CLKIN input may not be halted or changed in frequency during operation nor operated below the specified low frequency limit If an external clock is used it should be a TTL compatible signal running at the instruction rate The signal should be connected to the processor s CLKIN input in this case the XTAL input must be left unconnected Because the ADSP 216x processors include an on chip oscilla tor circuit an external crystal may also be used The crystal should be connected across the CLKIN and XTAL pins with two capacitors connected as shown in Figure 2 A parallel resonant fundamental frequency microprocessor grade crystal should be used ADSP 216x XTAL CLKIN CLKOUT ADSP 216x Figure 2 Exte
52. quation should be applied for each output load capacitance f output switching frequency Example In an ADSP 2161 application where external data memory is used and no other outputs are active power dissipation is calcu lated as follows Assumptions External data memory is accessed every cycle with 50 of the address pins switching External data memory writes occur every other cycle with 50 of the data pins switching Each address and data pin has a 10 pF total load at the pin The application operates at Vpp 5 0 V and tcx 50 ns Total Power Dissipation C x Vpp x f internal power dissipation from Figure 9 C x Vpp x f is calculated for each output of Output Pins x X X f Address DMS 8 x10 pF x5 V x 20 MHz 40 0 mW Data WR 9 x10 pF x5 V x 10 MHz 22 5 mW RD 1 x10 pF x5 V 10 MHz 2 5 mW CLKOUT 1 10 x5 V 20 2 5 0 mW 70 0 mW Total power dissipation for this example Pwr 70 0 mW ENVIRONMENTAL CONDITIONS Ambient Temperature Rating Tams Tease PD x Tcasg Case Temperature in PD Power Dissipation in W Thermal Resistance Case to Ambient Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Package Oya PLCC 27 C W 16 C W 11 C W MQFP 60 C W 18 C W 42 C W REV 0 CAPACITIVE LOAD
53. reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point as shown in Figure 19 If multiple pins such as the data bus are enabled the measurement value is that of the first pin to start driving REFERENCE SIGNAL VoH VoH MEASURED MEASURED MEASURED 0 5V 2 0V OUTPUT Vor MEASURED 0 5V VoL MEASURED Voi L MEASURED ipEcaY OUTPUT STARTS OUTPUT STOPS DRIVING DRIVING HIGH IMPEDANCE STATE TEST CONDITIONS CAUSE THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1 5V Figure 19 Output Enable Disable lot TO OUTPUT 50pF ur lon Figure 20 Equivalent Device Loading for AC Measurements Except Output Enable Disable REV 0 ADSP 216x TIMING PARAMETERS ADSP 2161 ADSP 2163 ADSP 2165 GENERAL NOTES Use the exact timing information given Do not attempt to de rive parameters from the addition or subtraction of others While addition or subtraction would yield meaningful results for an individual device the values given in this data sheet reflect sta tistical variations and worst cases Consequently you cannot meaningfully add parameters to derive longer times TIMING NOTES Switching Characteristics specify how the processor changes its signals You have no control over this timing circuitry external to the processor must be designed for compatibility with these signal characteristics Switching characteri
54. register When RESET is released the boot loading sequence is performed provided there is no pending bus request and the chip is configured for booting with MMAP 0 The first instruction is then fetched from internal program memory location 0x0000 PIN FUNCTION DESCRIPTIONS Pin of Input Name s Pins Output Function Address 14 Address outputs for program data and boot memory Data 24 IO Data I O pins for program and data memories Input only for boot memory with two MSBs used for boot memory addresses Unused data lines may be left floating RESET 1 1 Processor Reset Input IRQ2 1 I External Interrupt Request 2 BR 1 I External Bus Request Input BG 1 External Bus Grant Output PMS 1 External Program Memory Select DMS 1 External Data Memory Select BMS 1 Boot Memory Select RD 1 External Memory Read Enable WR 1 External Memory Write Enable MMAP 1 I Memory Map Select Input CLKIN XTAL 2 I External Clock or Quartz Crystal Input CLKOUT 1 Processor Clock Output Power Supply Pins GND Ground Pins SPORTO 5 IO Serial Port 0 Pins 0 RFS0 070 DRO SCLKO SPORTI 5 IO Serial Port 1 Pins 1 RFS1 DT1 DR1 SCLK1 or Interrupts and Flags IRQO RFS1 1 1 External Interrupt Request 0 IROI TFS1 1 1 External Interrupt Request 1 FI DRI 1 I Flag Input Pin FO DTI 1 Flag Output Pin PWDACK 1 Indicates when the processor has entered power down PWDFLAG 1 I Low to High Transition o
55. ress generators ensure efficient use of these computational units The sequencer supports conditional jumps subroutine calls and returns in a single cycle With internal loop counters and loop stacks the ADSP 216x executes looped code with zero overhead no explicit jump instructions are required to main tain the loop Two data address generators DAGs provide addresses for simultaneous dual operand fetches from data memory and program memory Each DAG maintains and updates four address pointers Whenever the pointer is used to access data indirect addressing it is post modified by the value of one of four modify registers A length value may be associated with each pointer to implement automatic modulo addressing for circular buffers The circular buffering feature is also used by the serial ports for automatic data transfers to and from on chip memory ADSP 216x INSTRUCTION REGISTER PROGRAM SEQUENCER K PROGRAM MEMORY DATA ADDRESS GENERATOR DATA ADDRESS GENERATOR 1 SRAM 14 T INPUT REGS MAC SHIFTER ALU MEMORY SRAM TRANSMIT REG OUTPUT REGS OUTPUT REGS OUTPUT REGS RECEIVE REG SERIAL i i PORT 0 DATA BOOT ADDRESS GENERATOR 14 CZ gt ADDRESS BUS Figure 1 ADSP 216x Block Diagram Efficient data transfer is achieved with the use of five internal buses Program Memory Address PMA Bus Program Mem
56. rnal Crystal Connections A clock output signal CLKOUT is generated by the processor synchronized to the processor s internal cycles Reset The RESET signal initiates a complete reset of the ADSP 21 6x The RESET signal must be asserted when the chip is powered up to assure proper initialization If the RESET signal is applied during initial power up it must be held long enough to allow the processor s internal clock to stabilize If RESET is activated at any time after power up and the input clock frequency does not change the processor s internal clock continues and does not require this stabilization time The power up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid Vpp is applied to the processor and for the internal phase locked loop PLL to lock onto the specific crystal frequency A minimum of 2000 tcx cycles will ensure that the PLL has locked this does not however include the crystal oscillator start up time During this power up sequence the RESET signal should be held low On any subsequent resets the RESET signal must meet the minimum pulsewidth specification tsp To generate the RESET signal use either an RC circuit with an external Schmidt trigger or a commercially available reset IC Do not use only an RC circuit The RESET input resets all internal stack pointers to the empty stack condition masks all interrupts and clears the MSTAT
57. ructions computational instructions multifunction ease of coding and readability The sources and destinations of instructions program flow control instructions and miscella computations and data movements are written explicitly in each neous instructions Multifunction instructions perform one or assembly statement eliminating cryptic assembler mnemonics two data moves and a computation Every instruction assembles into a single 24 bit word and executes The instruction set is summarized below The ADSP 2100 in a single cycle The instructions encompass a wide variety of Family Users Manual contains a complete reference to the instruction types along with a high degree of operational instruction set ALU Instructions cond AR AF yop C 1 t C 1 with Subtract X Y Subtract X Y with Borrow Subtract Y X Subtract Y X with Borrow AND yop AND OR yop OR XOR yop XOR PASS Pass Clear Negate Absolute Value yoptl Increment yop 1 Decrement DIVS yop Divide DIVQ MAC Instructions cond xop yop Multiply yop MultiplylAccumulate MR xop yop MultiplylSubtract MR Transfer MR 0 Clear SAT MR Shifter Instructions cond SR SR OR ASHIFT Arithmetic Shift
58. ses if an instruction requires more than one external memory access When the BR signal is released the processor releases the BG signal re enables the output drivers and continues program execution from the point at which it stopped The bus request feature operates at all times including when the processor is booting and when RESET is active If this feature is not used the BR input should be tied high to Vpp POWER DOWN The ADSP 2165 ADSP 2166 processors have a low power feature that lets the processor enter a very low power dormant state through hardware or software control A list of power down features follows Processor registers and on chip memory contents are main tained during power down Power down mode holds the processor in CMOS standby with a maximum current of less than 100 uA in some modes Support for an externally generated TTL or CMOS proces sor clock The external clock can continue running during power down without affecting the lowest power rating Support for crystal operation includes disabling the oscillator to save power The processor automatically waits 4096 CLKIN cycles for the crystal oscillator to start and stabilize When power down mode is enabled powering down of the processor can be initiated either by externally generated IRQ2 interrupt or by using the IRQ2 force bit in the IFC register Power Down Acknowledge Pin PWDACK indicates when the processor has entered power d
59. stics tell you what the processor will do in a given circumstance You can also use switching characteristics to ensure that any timing requirement of a device connected to the processor such as memory is satisfied Timing Requirements apply to signals that are controlled by cir cuitry external to the processor such as the data input for a read operation Timing requirements guarantee that the processor operates correctly with other devices MEMORY REQUIREMENTS The table below shows common memory device specifications and the corresponding ADSP 216x timing parameters for your convenience Timing Parameter Definition ADSP 216x Memory Device Specification Timing Parameter Address Setup to Write Start tasw Address Setup to Write End taw Address Hold Time Data Setup Time tow Data Hold Time tDH OE to Data Valid trpp Address Access Time 0 13 DMS PMS Setup Before WR Low 0 13 DMS PMS Setup Before WR Deasserted 0 13 DMS PMS Hold After WR Deasserted Data Setup Before WR High Data Hold After WR High RD Low to Data Valid 0 13 DMS PMS BMS to Data Valid REV 0 21 ADSP 216x TIMING PARAMETERS ADSP 2161 ADSP 2163 ADSP 2165 CLOCK SIGNALS AND RESET 16 67 MHz 20 MHz 25 MHz Frequency Dependency Parameter Min Max Min Max Min Max Min Max Unit Timing Requirements tex CLKIN Period 60 150 50 150 40 150 tck 150 ns CLKIN Width Low 20 20 1
60. te Data amp Program Memory Read ALUIMAC with Data amp Program Memory Read ADSP 216x Program Flow Instructions DO lt addr gt UNTIL term IF cond JUMP Ix IF cond JUMP lt addr gt IF cond CALL Ix IF cond CALL lt addr gt IF NOT FLAG IN JUMP lt addr gt IF NOT FLAG IN CALL lt addr gt IF cond SET RESET TOGGLE FLAG OUT IF cond RTS IF cond RTI IDLE n Miscellaneous Instructions NOP MODIFY Ix My PUSH STS POP CNTR POP PC POP LOOP Do Until Loop Jump Call Subroutine Jump Call on Flag In Pin Modify Flag Out Pin Return from Subroutine Return from Interrupt Service Routine Idle No Operation Modify Address Register Stack Control ENA DIS SEC REG Mode Control BIT_REV AV_LATCH AR_SAT M_MODE TIMER G_MODE Notation Conventions Ix Index registers for indirect addressing My Modify registers for indirect addressing lt data gt Immediate data value lt addr gt Immediate address value lt exp gt Exponent shift value in shift immediate instructions 8 bit signed number lt ALU gt Any ALU instruction except divide lt MAC gt Any multiply accumulate instruction lt SHIFT gt Any shift instruction except shift immediate cond Condition code for conditional instruction term Termination code for DO UNTIL loop dreg Data register of ALU MAC or Shifter reg Any register including dregs 3 A semicolon terminates the instr
61. tes are automatically generated This allows for example a 60 ns ADSP 2161 to use a 200 ns EPROM as external boot memory Multiple programs can be selected and loaded from the EPROM with no additional hardware The data receive and transmit pins on SPORTI Serial Port 1 can be alternatively configured as a general purpose input flag and output flag You can use these pins for event signalling to and from an external device programmable interval timer can generate periodic interrupts 16 bit count register TCOUNT is decremented every n cycles where n 1 is a scaling value stored in an 8 bit register TSCALE When the value of the count register reaches zero an interrupt is generated and the count register is reloaded from a 16 bit period register TPERIOD Serial Ports The ADSP 216x processors include two synchronous serial ports SPORTs for serial communications and multiprocessor communication All of the ADSP 216x processors have two serial ports SPORT1 The serial ports provide a complete synchronous serial interface with optional companding in hardware A wide variety of framed or frameless data transmit and receive modes of opera tion are available Each SPORT can generate an internal pro grammable serial clock or accept an external serial clock Each serial port has a 5 pin interface consisting of the following signals Signal Name Function SCLK Serial Clock I O RFS Receive Frame
62. uction 5 Commas separate multiple operations of a single instruction 1 optionl option2 Optional part of instruction Optional multiple operations of an instruction List of options choose one Assembly Code Example The following example is a code fragment that performs the filter tap update for an adaptive filter based on a least mean squared algorithm Notice that the computations in the instructions are written like algebraic equations MF MX0 MY1 RND MX0 DM I2 M1 MR MX0 MF RND AYO PM I6 M5 DO adapt UNTIL CE AR MR1 AY0 MXO DM 1I2 M1 AYO PM I6 PM I6 M6 AR RND F error beta 7 adapt MODIFY I2 M3 MODIFY 16 7 Point to oldest data Point to start of data 12 REV 0 ADSP 216x SPECIFICATIONS ADSP 2161 ADSP 2163 ADSP 2165 RECOMMENDED OPERATING CONDITIONS K Grade B Grade Parameter Min Max Min Max Unit Supply Voltage 4 50 5 50 4 50 5 50 V Tams Ambient Operating Temperature 0 70 40 85 C See Environmental Conditions for information on thermal specifications Parameter Test Conditions Min Max Unit Vin Hi Level Input Voltage 2 Vpp max 2 0 V Vin Hi Level CLKIN and Reset Voltage Vpp max 2 2 V Lo Level Input Voltage 3 Vpp min 0 8 V Vox Hi Level Output Voltage Vpp min 0 5 mA 2 4 V 100 0 3 V Vor Lo Level Output
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